drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 /*
  77  * High threshold controlling when to start sending XOFF frames. Must be at
  78  * least 8 bytes less than receive packet buffer size. This value is in units
  79  * of 1024 bytes.
  80  */
  81 #define IXGBE_FC_HI    0x80
  82
  83 /*
  84  * Low threshold controlling when to start sending XON frames. This value is
  85  * in units of 1024 bytes.
  86  */
  87 #define IXGBE_FC_LO    0x40
  88
  89 /* Default minimum inter-interrupt interval for EITR configuration */
  90 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  91
  92 /* Timer value included in XOFF frames. */
  93 #define IXGBE_FC_PAUSE 0x680
  94
  95 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  96 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  97 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  98
  99 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 100 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 101 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 102
 103 /*
 104  *  Default values for RX/TX configuration
 105  */
 106 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 107 #define IXGBE_DEFAULT_RX_PTHRESH      8
 108 #define IXGBE_DEFAULT_RX_HTHRESH      8
 109 #define IXGBE_DEFAULT_RX_WTHRESH      0
 110
 111 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 112 #define IXGBE_DEFAULT_TX_PTHRESH      32
 113 #define IXGBE_DEFAULT_TX_HTHRESH      0
 114 #define IXGBE_DEFAULT_TX_WTHRESH      0
 115 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 116
 117 /* Bit shift and mask */
 118 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 119 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 120 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 121 #define IXGBE_8_BIT_MASK   UINT8_MAX
 122
 123 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 124
 125 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 126
 127 #define IXGBE_HKEY_MAX_INDEX 10
 128
 129 /* Additional timesync values. */
 130 #define NSEC_PER_SEC             1000000000L
 131 #define IXGBE_INCVAL_10GB        0x66666666
 132 #define IXGBE_INCVAL_1GB         0x40000000
 133 #define IXGBE_INCVAL_100         0x50000000
 134 #define IXGBE_INCVAL_SHIFT_10GB  28
 135 #define IXGBE_INCVAL_SHIFT_1GB   24
 136 #define IXGBE_INCVAL_SHIFT_100   21
 137 #define IXGBE_INCVAL_SHIFT_82599 7
 138 #define IXGBE_INCPER_SHIFT_82599 24
 139
 140 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 141
 142 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 143 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 144 #define DEFAULT_ETAG_ETYPE                     0x893f
 145 #define IXGBE_ETAG_ETYPE                       0x00005084
 146 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 147 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 148 #define IXGBE_RAH_ADTYPE                       0x40000000
 149 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 150 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 151 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 152 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 153 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 154 #define IXGBE_VTEICR_MASK                      0x07
 155
 156 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 157 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 158
 159 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 160 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 161 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 167 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static int
 186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 187                 uint64_t *values, unsigned int n);
 188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names,
 192         unsigned int size);
 193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 195 static int ixgbe_dev_xstats_get_names_by_id(
 196         struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names,
 198         const uint64_t *ids,
 199         unsigned int limit);
 200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 201                                              uint16_t queue_id,
 202                                              uint8_t stat_idx,
 203                                              uint8_t is_rx);
 204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 205                                  size_t fw_size);
 206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_dev_info *dev_info);
 208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 210                                  struct rte_eth_dev_info *dev_info);
 211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 212
 213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 216                                enum rte_vlan_type vlan_type,
 217                                uint16_t tpid_id);
 218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 219                 uint16_t queue, bool on);
 220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 221                 int on);
 222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 227
 228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 233                                struct rte_eth_fc_conf *fc_conf);
 234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 235                 struct rte_eth_pfc_conf *pfc_conf);
 236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 237                         struct rte_eth_rss_reta_entry64 *reta_conf,
 238                         uint16_t reta_size);
 239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_reta_entry64 *reta_conf,
 241                         uint16_t reta_size);
 242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 248                                       struct rte_intr_handle *handle);
 249 static void ixgbe_dev_interrupt_handler(void *param);
 250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 252                          uint32_t index, uint32_t pool);
 253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 255                                            struct ether_addr *mac_addr);
 256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 257 static bool is_device_supported(struct rte_eth_dev *dev,
 258                                 struct rte_pci_driver *drv);
 259
 260 /* For Virtual Function support */
 261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 263 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 264 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 265 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 266                                    int wait_to_complete);
 267 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 268 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 269 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 270 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 271 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 272 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 273                 struct rte_eth_stats *stats);
 274 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 275 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 276                 uint16_t vlan_id, int on);
 277 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 278                 uint16_t queue, int on);
 279 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 280 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 281 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 282                                             uint16_t queue_id);
 283 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 284                                              uint16_t queue_id);
 285 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 286                                  uint8_t queue, uint8_t msix_vector);
 287 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 288 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 289 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 290
 291 /* For Eth VMDQ APIs support */
 292 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 293                 ether_addr * mac_addr, uint8_t on);
 294 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 295 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 296                 struct rte_eth_mirror_conf *mirror_conf,
 297                 uint8_t rule_id, uint8_t on);
 298 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 299                 uint8_t rule_id);
 300 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 301                                           uint16_t queue_id);
 302 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 303                                            uint16_t queue_id);
 304 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 305                                uint8_t queue, uint8_t msix_vector);
 306 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 307
 308 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 309                                 struct ether_addr *mac_addr,
 310                                 uint32_t index, uint32_t pool);
 311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 313                                              struct ether_addr *mac_addr);
 314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter);
 316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 317                         enum rte_filter_op filter_op,
 318                         void *arg);
 319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 322                         struct ixgbe_5tuple_filter *filter);
 323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ntuple_filter *filter);
 328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 332                         struct rte_eth_ethertype_filter *filter);
 333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 334                      enum rte_filter_type filter_type,
 335                      enum rte_filter_op filter_op,
 336                      void *arg);
 337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 338
 339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 340                                       struct ether_addr *mc_addr_set,
 341                                       uint32_t nb_mc_addr);
 342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 343                                    struct rte_eth_dcb_info *dcb_info);
 344
 345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 347                             struct rte_dev_reg_info *regs);
 348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353
 354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 356                                 struct rte_dev_reg_info *regs);
 357
 358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 361                                             struct timespec *timestamp,
 362                                             uint32_t flags);
 363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 364                                             struct timespec *timestamp);
 365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 367                                    struct timespec *timestamp);
 368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 369                                    const struct timespec *timestamp);
 370 static void ixgbevf_dev_interrupt_handler(void *param);
 371
 372 static int ixgbe_dev_l2_tunnel_eth_type_conf
 373         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 374 static int ixgbe_dev_l2_tunnel_offload_set
 375         (struct rte_eth_dev *dev,
 376          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 377          uint32_t mask,
 378          uint8_t en);
 379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 380                                              enum rte_filter_op filter_op,
 381                                              void *arg);
 382
 383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 384                                          struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 386                                          struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 389
 390 /*
 391  * Define VF Stats MACRO for Non "cleared on read" register
 392  */
 393 #define UPDATE_VF_STAT(reg, last, cur)                          \
 394 {                                                               \
 395         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 396         cur += (latest - last) & UINT_MAX;                      \
 397         last = latest;                                          \
 398 }
 399
 400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 401 {                                                                \
 402         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 403         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 404         u64 latest = ((new_msb << 32) | new_lsb);                \
 405         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 406         last = latest;                                           \
 407 }
 408
 409 #define IXGBE_SET_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] |= 1 << bit;\
 413         } while (0)
 414
 415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (h)->bitmap[idx] &= ~(1 << bit);\
 419         } while (0)
 420
 421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 422                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 423                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 424                 (r) = (h)->bitmap[idx] >> bit & 1;\
 425         } while (0)
 426
 427 /*
 428  * The set of PCI devices this driver supports
 429  */
 430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 479 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 481 #endif
 482         { .vendor_id = 0, /* sentinel */ },
 483 };
 484
 485 /*
 486  * The set of PCI devices this driver supports (for 82599 VF)
 487  */
 488 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 499         { .vendor_id = 0, /* sentinel */ },
 500 };
 501
 502 static const struct rte_eth_desc_lim rx_desc_lim = {
 503         .nb_max = IXGBE_MAX_RING_DESC,
 504         .nb_min = IXGBE_MIN_RING_DESC,
 505         .nb_align = IXGBE_RXD_ALIGN,
 506 };
 507
 508 static const struct rte_eth_desc_lim tx_desc_lim = {
 509         .nb_max = IXGBE_MAX_RING_DESC,
 510         .nb_min = IXGBE_MIN_RING_DESC,
 511         .nb_align = IXGBE_TXD_ALIGN,
 512         .nb_seg_max = IXGBE_TX_MAX_SEG,
 513         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 514 };
 515
 516 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 517         .dev_configure        = ixgbe_dev_configure,
 518         .dev_start            = ixgbe_dev_start,
 519         .dev_stop             = ixgbe_dev_stop,
 520         .dev_set_link_up    = ixgbe_dev_set_link_up,
 521         .dev_set_link_down  = ixgbe_dev_set_link_down,
 522         .dev_close            = ixgbe_dev_close,
 523         .dev_reset            = ixgbe_dev_reset,
 524         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 525         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 526         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 527         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 528         .link_update          = ixgbe_dev_link_update,
 529         .stats_get            = ixgbe_dev_stats_get,
 530         .xstats_get           = ixgbe_dev_xstats_get,
 531         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 532         .stats_reset          = ixgbe_dev_stats_reset,
 533         .xstats_reset         = ixgbe_dev_xstats_reset,
 534         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 535         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 536         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 537         .fw_version_get       = ixgbe_fw_version_get,
 538         .dev_infos_get        = ixgbe_dev_info_get,
 539         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 540         .mtu_set              = ixgbe_dev_mtu_set,
 541         .vlan_filter_set      = ixgbe_vlan_filter_set,
 542         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 543         .vlan_offload_set     = ixgbe_vlan_offload_set,
 544         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 545         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 546         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 547         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 548         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 549         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 550         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 551         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 552         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 553         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 554         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 555         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 556         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 557         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 558         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 559         .dev_led_on           = ixgbe_dev_led_on,
 560         .dev_led_off          = ixgbe_dev_led_off,
 561         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 562         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 563         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 564         .mac_addr_add         = ixgbe_add_rar,
 565         .mac_addr_remove      = ixgbe_remove_rar,
 566         .mac_addr_set         = ixgbe_set_default_mac_addr,
 567         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 568         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 569         .mirror_rule_set      = ixgbe_mirror_rule_set,
 570         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 571         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 572         .reta_update          = ixgbe_dev_rss_reta_update,
 573         .reta_query           = ixgbe_dev_rss_reta_query,
 574         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 575         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 576         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 577         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 578         .rxq_info_get         = ixgbe_rxq_info_get,
 579         .txq_info_get         = ixgbe_txq_info_get,
 580         .timesync_enable      = ixgbe_timesync_enable,
 581         .timesync_disable     = ixgbe_timesync_disable,
 582         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 583         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 584         .get_reg              = ixgbe_get_regs,
 585         .get_eeprom_length    = ixgbe_get_eeprom_length,
 586         .get_eeprom           = ixgbe_get_eeprom,
 587         .set_eeprom           = ixgbe_set_eeprom,
 588         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 589         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 590         .timesync_read_time   = ixgbe_timesync_read_time,
 591         .timesync_write_time  = ixgbe_timesync_write_time,
 592         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 593         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 594         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 595         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 596         .tm_ops_get           = ixgbe_tm_ops_get,
 597 };
 598
 599 /*
 600  * dev_ops for virtual function, bare necessities for basic vf
 601  * operation have been implemented
 602  */
 603 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 604         .dev_configure        = ixgbevf_dev_configure,
 605         .dev_start            = ixgbevf_dev_start,
 606         .dev_stop             = ixgbevf_dev_stop,
 607         .link_update          = ixgbevf_dev_link_update,
 608         .stats_get            = ixgbevf_dev_stats_get,
 609         .xstats_get           = ixgbevf_dev_xstats_get,
 610         .stats_reset          = ixgbevf_dev_stats_reset,
 611         .xstats_reset         = ixgbevf_dev_stats_reset,
 612         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 613         .dev_close            = ixgbevf_dev_close,
 614         .dev_reset            = ixgbevf_dev_reset,
 615         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 616         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 617         .dev_infos_get        = ixgbevf_dev_info_get,
 618         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 619         .mtu_set              = ixgbevf_dev_set_mtu,
 620         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 621         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 622         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 623         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 624         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 625         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 626         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 627         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 628         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 629         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 630         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 631         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 632         .mac_addr_add         = ixgbevf_add_mac_addr,
 633         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 634         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 635         .rxq_info_get         = ixgbe_rxq_info_get,
 636         .txq_info_get         = ixgbe_txq_info_get,
 637         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 638         .get_reg              = ixgbevf_get_regs,
 639         .reta_update          = ixgbe_dev_rss_reta_update,
 640         .reta_query           = ixgbe_dev_rss_reta_query,
 641         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 642         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 643 };
 644
 645 /* store statistics names and its offset in stats structure */
 646 struct rte_ixgbe_xstats_name_off {
 647         char name[RTE_ETH_XSTATS_NAME_SIZE];
 648         unsigned offset;
 649 };
 650
 651 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 652         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 653         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 654         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 655         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 656         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 657         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 658         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 659         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 660         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 661         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 662         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 663         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 664         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 665         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 666         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 667                 prc1023)},
 668         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 669                 prc1522)},
 670         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 671         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 672         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 673         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 674         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 675         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 676         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 677         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 678         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 679         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 680         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 681         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 682         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 683         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 684         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 685         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 686         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 687                 ptc1023)},
 688         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 689                 ptc1522)},
 690         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 691         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 692         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 693         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 694
 695         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 696                 fdirustat_add)},
 697         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirustat_remove)},
 699         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 700                 fdirfstat_fadd)},
 701         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 702                 fdirfstat_fremove)},
 703         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 704                 fdirmatch)},
 705         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirmiss)},
 707
 708         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 709         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 710         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 711                 fclast)},
 712         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 713         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 714         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 715         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 716         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 717                 fcoe_noddp)},
 718         {"rx_fcoe_no_direct_data_placement_ext_buff",
 719                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 720
 721         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 722                 lxontxc)},
 723         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 724                 lxonrxc)},
 725         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 726                 lxofftxc)},
 727         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 728                 lxoffrxc)},
 729         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 730 };
 731
 732 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 733                            sizeof(rte_ixgbe_stats_strings[0]))
 734
 735 /* MACsec statistics */
 736 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 737         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 738                 out_pkts_untagged)},
 739         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 740                 out_pkts_encrypted)},
 741         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 742                 out_pkts_protected)},
 743         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 744                 out_octets_encrypted)},
 745         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 746                 out_octets_protected)},
 747         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_untagged)},
 749         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_badtag)},
 751         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_nosci)},
 753         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_unknownsci)},
 755         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 756                 in_octets_decrypted)},
 757         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 758                 in_octets_validated)},
 759         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_unchecked)},
 761         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_delayed)},
 763         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_late)},
 765         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_ok)},
 767         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_invalid)},
 769         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_notvalid)},
 771         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_unusedsa)},
 773         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_notusingsa)},
 775 };
 776
 777 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 778                            sizeof(rte_ixgbe_macsec_strings[0]))
 779
 780 /* Per-queue statistics */
 781 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 782         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 783         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 784         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 785         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 786 };
 787
 788 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 789                            sizeof(rte_ixgbe_rxq_strings[0]))
 790 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 791
 792 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 793         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 794         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 795         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 796                 pxon2offc)},
 797 };
 798
 799 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 800                            sizeof(rte_ixgbe_txq_strings[0]))
 801 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 802
 803 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 804         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 805 };
 806
 807 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 808                 sizeof(rte_ixgbevf_stats_strings[0]))
 809
 810 /**
 811  * Atomically reads the link status information from global
 812  * structure rte_eth_dev.
 813  *
 814  * @param dev
 815  *   - Pointer to the structure rte_eth_dev to read from.
 816  *   - Pointer to the buffer to be saved with the link status.
 817  *
 818  * @return
 819  *   - On success, zero.
 820  *   - On failure, negative value.
 821  */
 822 static inline int
 823 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 824                                 struct rte_eth_link *link)
 825 {
 826         struct rte_eth_link *dst = link;
 827         struct rte_eth_link *src = &(dev->data->dev_link);
 828
 829         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 830                                         *(uint64_t *)src) == 0)
 831                 return -1;
 832
 833         return 0;
 834 }
 835
 836 /**
 837  * Atomically writes the link status information into global
 838  * structure rte_eth_dev.
 839  *
 840  * @param dev
 841  *   - Pointer to the structure rte_eth_dev to read from.
 842  *   - Pointer to the buffer to be saved with the link status.
 843  *
 844  * @return
 845  *   - On success, zero.
 846  *   - On failure, negative value.
 847  */
 848 static inline int
 849 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 850                                 struct rte_eth_link *link)
 851 {
 852         struct rte_eth_link *dst = &(dev->data->dev_link);
 853         struct rte_eth_link *src = link;
 854
 855         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 856                                         *(uint64_t *)src) == 0)
 857                 return -1;
 858
 859         return 0;
 860 }
 861
 862 /*
 863  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 864  */
 865 static inline int
 866 ixgbe_is_sfp(struct ixgbe_hw *hw)
 867 {
 868         switch (hw->phy.type) {
 869         case ixgbe_phy_sfp_avago:
 870         case ixgbe_phy_sfp_ftl:
 871         case ixgbe_phy_sfp_intel:
 872         case ixgbe_phy_sfp_unknown:
 873         case ixgbe_phy_sfp_passive_tyco:
 874         case ixgbe_phy_sfp_passive_unknown:
 875                 return 1;
 876         default:
 877                 return 0;
 878         }
 879 }
 880
 881 static inline int32_t
 882 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 883 {
 884         uint32_t ctrl_ext;
 885         int32_t status;
 886
 887         status = ixgbe_reset_hw(hw);
 888
 889         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 890         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 891         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 892         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 893         IXGBE_WRITE_FLUSH(hw);
 894
 895         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 896                 status = IXGBE_SUCCESS;
 897         return status;
 898 }
 899
 900 static inline void
 901 ixgbe_enable_intr(struct rte_eth_dev *dev)
 902 {
 903         struct ixgbe_interrupt *intr =
 904                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 905         struct ixgbe_hw *hw =
 906                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 907
 908         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 909         IXGBE_WRITE_FLUSH(hw);
 910 }
 911
 912 /*
 913  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 914  */
 915 static void
 916 ixgbe_disable_intr(struct ixgbe_hw *hw)
 917 {
 918         PMD_INIT_FUNC_TRACE();
 919
 920         if (hw->mac.type == ixgbe_mac_82598EB) {
 921                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 922         } else {
 923                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 924                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 926         }
 927         IXGBE_WRITE_FLUSH(hw);
 928 }
 929
 930 /*
 931  * This function resets queue statistics mapping registers.
 932  * From Niantic datasheet, Initialization of Statistics section:
 933  * "...if software requires the queue counters, the RQSMR and TQSM registers
 934  * must be re-programmed following a device reset.
 935  */
 936 static void
 937 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 938 {
 939         uint32_t i;
 940
 941         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 942                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 943                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 944         }
 945 }
 946
 947
 948 static int
 949 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 950                                   uint16_t queue_id,
 951                                   uint8_t stat_idx,
 952                                   uint8_t is_rx)
 953 {
 954 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 955 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 956 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 957
 958         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 959         struct ixgbe_stat_mapping_registers *stat_mappings =
 960                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 961         uint32_t qsmr_mask = 0;
 962         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 963         uint32_t q_map;
 964         uint8_t n, offset;
 965
 966         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 967                 (hw->mac.type != ixgbe_mac_X540) &&
 968                 (hw->mac.type != ixgbe_mac_X550) &&
 969                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 970                 (hw->mac.type != ixgbe_mac_X550EM_a))
 971                 return -ENOSYS;
 972
 973         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 974                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 975                      queue_id, stat_idx);
 976
 977         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 978         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 979                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 980                 return -EIO;
 981         }
 982         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 983
 984         /* Now clear any previous stat_idx set */
 985         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 986         if (!is_rx)
 987                 stat_mappings->tqsm[n] &= ~clearing_mask;
 988         else
 989                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 990
 991         q_map = (uint32_t)stat_idx;
 992         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 993         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 994         if (!is_rx)
 995                 stat_mappings->tqsm[n] |= qsmr_mask;
 996         else
 997                 stat_mappings->rqsmr[n] |= qsmr_mask;
 998
 999         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1000                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1001                      queue_id, stat_idx);
1002         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1003                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1004
1005         /* Now write the mapping in the appropriate register */
1006         if (is_rx) {
1007                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1008                              stat_mappings->rqsmr[n], n);
1009                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1010         } else {
1011                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1012                              stat_mappings->tqsm[n], n);
1013                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1014         }
1015         return 0;
1016 }
1017
1018 static void
1019 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1020 {
1021         struct ixgbe_stat_mapping_registers *stat_mappings =
1022                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024         int i;
1025
1026         /* write whatever was in stat mapping table to the NIC */
1027         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1028                 /* rx */
1029                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1030
1031                 /* tx */
1032                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1033         }
1034 }
1035
1036 static void
1037 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1038 {
1039         uint8_t i;
1040         struct ixgbe_dcb_tc_config *tc;
1041         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1042
1043         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1044         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1045         for (i = 0; i < dcb_max_tc; i++) {
1046                 tc = &dcb_config->tc_config[i];
1047                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1048                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1049                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1050                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1051                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1052                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1053                 tc->pfc = ixgbe_dcb_pfc_disabled;
1054         }
1055
1056         /* Initialize default user to priority mapping, UPx->TC0 */
1057         tc = &dcb_config->tc_config[0];
1058         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1059         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1060         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1061                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1062                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1063         }
1064         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1065         dcb_config->pfc_mode_enable = false;
1066         dcb_config->vt_mode = true;
1067         dcb_config->round_robin_enable = false;
1068         /* support all DCB capabilities in 82599 */
1069         dcb_config->support.capabilities = 0xFF;
1070
1071         /*we only support 4 Tcs for X540, X550 */
1072         if (hw->mac.type == ixgbe_mac_X540 ||
1073                 hw->mac.type == ixgbe_mac_X550 ||
1074                 hw->mac.type == ixgbe_mac_X550EM_x ||
1075                 hw->mac.type == ixgbe_mac_X550EM_a) {
1076                 dcb_config->num_tcs.pg_tcs = 4;
1077                 dcb_config->num_tcs.pfc_tcs = 4;
1078         }
1079 }
1080
1081 /*
1082  * Ensure that all locks are released before first NVM or PHY access
1083  */
1084 static void
1085 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1086 {
1087         uint16_t mask;
1088
1089         /*
1090          * Phy lock should not fail in this early stage. If this is the case,
1091          * it is due to an improper exit of the application.
1092          * So force the release of the faulty lock. Release of common lock
1093          * is done automatically by swfw_sync function.
1094          */
1095         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1096         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1097                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1098         }
1099         ixgbe_release_swfw_semaphore(hw, mask);
1100
1101         /*
1102          * These ones are more tricky since they are common to all ports; but
1103          * swfw_sync retries last long enough (1s) to be almost sure that if
1104          * lock can not be taken it is due to an improper lock of the
1105          * semaphore.
1106          */
1107         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1108         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1109                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1110         }
1111         ixgbe_release_swfw_semaphore(hw, mask);
1112 }
1113
1114 /*
1115  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1116  * It returns 0 on success.
1117  */
1118 static int
1119 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1120 {
1121         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1122         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1123         struct ixgbe_hw *hw =
1124                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1125         struct ixgbe_vfta *shadow_vfta =
1126                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1127         struct ixgbe_hwstrip *hwstrip =
1128                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1129         struct ixgbe_dcb_config *dcb_config =
1130                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1131         struct ixgbe_filter_info *filter_info =
1132                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1133         struct ixgbe_bw_conf *bw_conf =
1134                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1135         uint32_t ctrl_ext;
1136         uint16_t csum;
1137         int diag, i;
1138
1139         PMD_INIT_FUNC_TRACE();
1140
1141         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1142         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1143         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1144         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1145
1146         /*
1147          * For secondary processes, we don't initialise any further as primary
1148          * has already done this work. Only check we don't need a different
1149          * RX and TX function.
1150          */
1151         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1152                 struct ixgbe_tx_queue *txq;
1153                 /* TX queue function in primary, set by last queue initialized
1154                  * Tx queue may not initialized by primary process
1155                  */
1156                 if (eth_dev->data->tx_queues) {
1157                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1158                         ixgbe_set_tx_function(eth_dev, txq);
1159                 } else {
1160                         /* Use default TX function if we get here */
1161                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1162                                      "Using default TX function.");
1163                 }
1164
1165                 ixgbe_set_rx_function(eth_dev);
1166
1167                 return 0;
1168         }
1169
1170         rte_eth_copy_pci_info(eth_dev, pci_dev);
1171         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1172
1173         /* Vendor and Device ID need to be set before init of shared code */
1174         hw->device_id = pci_dev->id.device_id;
1175         hw->vendor_id = pci_dev->id.vendor_id;
1176         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1177         hw->allow_unsupported_sfp = 1;
1178
1179         /* Initialize the shared code (base driver) */
1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1181         diag = ixgbe_bypass_init_shared_code(hw);
1182 #else
1183         diag = ixgbe_init_shared_code(hw);
1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1185
1186         if (diag != IXGBE_SUCCESS) {
1187                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1188                 return -EIO;
1189         }
1190
1191         /* pick up the PCI bus settings for reporting later */
1192         ixgbe_get_bus_info(hw);
1193
1194         /* Unlock any pending hardware semaphore */
1195         ixgbe_swfw_lock_reset(hw);
1196
1197         /* Initialize DCB configuration*/
1198         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1199         ixgbe_dcb_init(hw, dcb_config);
1200         /* Get Hardware Flow Control setting */
1201         hw->fc.requested_mode = ixgbe_fc_full;
1202         hw->fc.current_mode = ixgbe_fc_full;
1203         hw->fc.pause_time = IXGBE_FC_PAUSE;
1204         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1205                 hw->fc.low_water[i] = IXGBE_FC_LO;
1206                 hw->fc.high_water[i] = IXGBE_FC_HI;
1207         }
1208         hw->fc.send_xon = 1;
1209
1210         /* Make sure we have a good EEPROM before we read from it */
1211         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1212         if (diag != IXGBE_SUCCESS) {
1213                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1214                 return -EIO;
1215         }
1216
1217 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1218         diag = ixgbe_bypass_init_hw(hw);
1219 #else
1220         diag = ixgbe_init_hw(hw);
1221 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1222
1223         /*
1224          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1225          * is called too soon after the kernel driver unbinding/binding occurs.
1226          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1227          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1228          * also called. See ixgbe_identify_phy_82599(). The reason for the
1229          * failure is not known, and only occuts when virtualisation features
1230          * are disabled in the bios. A delay of 100ms  was found to be enough by
1231          * trial-and-error, and is doubled to be safe.
1232          */
1233         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1234                 rte_delay_ms(200);
1235                 diag = ixgbe_init_hw(hw);
1236         }
1237
1238         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1239                 diag = IXGBE_SUCCESS;
1240
1241         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1242                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1243                              "LOM.  Please be aware there may be issues associated "
1244                              "with your hardware.");
1245                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1246                              "please contact your Intel or hardware representative "
1247                              "who provided you with this hardware.");
1248         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1249                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1250         if (diag) {
1251                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1252                 return -EIO;
1253         }
1254
1255         /* Reset the hw statistics */
1256         ixgbe_dev_stats_reset(eth_dev);
1257
1258         /* disable interrupt */
1259         ixgbe_disable_intr(hw);
1260
1261         /* reset mappings for queue statistics hw counters*/
1262         ixgbe_reset_qstat_mappings(hw);
1263
1264         /* Allocate memory for storing MAC addresses */
1265         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1266                                                hw->mac.num_rar_entries, 0);
1267         if (eth_dev->data->mac_addrs == NULL) {
1268                 PMD_INIT_LOG(ERR,
1269                              "Failed to allocate %u bytes needed to store "
1270                              "MAC addresses",
1271                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1272                 return -ENOMEM;
1273         }
1274         /* Copy the permanent MAC address */
1275         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1276                         &eth_dev->data->mac_addrs[0]);
1277
1278         /* Allocate memory for storing hash filter MAC addresses */
1279         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1280                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1281         if (eth_dev->data->hash_mac_addrs == NULL) {
1282                 PMD_INIT_LOG(ERR,
1283                              "Failed to allocate %d bytes needed to store MAC addresses",
1284                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1285                 return -ENOMEM;
1286         }
1287
1288         /* initialize the vfta */
1289         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1290
1291         /* initialize the hw strip bitmap*/
1292         memset(hwstrip, 0, sizeof(*hwstrip));
1293
1294         /* initialize PF if max_vfs not zero */
1295         ixgbe_pf_host_init(eth_dev);
1296
1297         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1298         /* let hardware know driver is loaded */
1299         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1300         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1301         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1302         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1303         IXGBE_WRITE_FLUSH(hw);
1304
1305         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1306                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1307                              (int) hw->mac.type, (int) hw->phy.type,
1308                              (int) hw->phy.sfp_type);
1309         else
1310                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1311                              (int) hw->mac.type, (int) hw->phy.type);
1312
1313         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1314                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1315                      pci_dev->id.device_id);
1316
1317         rte_intr_callback_register(intr_handle,
1318                                    ixgbe_dev_interrupt_handler, eth_dev);
1319
1320         /* enable uio/vfio intr/eventfd mapping */
1321         rte_intr_enable(intr_handle);
1322
1323         /* enable support intr */
1324         ixgbe_enable_intr(eth_dev);
1325
1326         /* initialize filter info */
1327         memset(filter_info, 0,
1328                sizeof(struct ixgbe_filter_info));
1329
1330         /* initialize 5tuple filter list */
1331         TAILQ_INIT(&filter_info->fivetuple_list);
1332
1333         /* initialize flow director filter list & hash */
1334         ixgbe_fdir_filter_init(eth_dev);
1335
1336         /* initialize l2 tunnel filter list & hash */
1337         ixgbe_l2_tn_filter_init(eth_dev);
1338
1339         TAILQ_INIT(&filter_ntuple_list);
1340         TAILQ_INIT(&filter_ethertype_list);
1341         TAILQ_INIT(&filter_syn_list);
1342         TAILQ_INIT(&filter_fdir_list);
1343         TAILQ_INIT(&filter_l2_tunnel_list);
1344         TAILQ_INIT(&ixgbe_flow_list);
1345
1346         /* initialize bandwidth configuration info */
1347         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1348
1349         /* initialize Traffic Manager configuration */
1350         ixgbe_tm_conf_init(eth_dev);
1351
1352         return 0;
1353 }
1354
1355 static int
1356 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1357 {
1358         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1359         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1360         struct ixgbe_hw *hw;
1361
1362         PMD_INIT_FUNC_TRACE();
1363
1364         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1365                 return -EPERM;
1366
1367         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1368
1369         if (hw->adapter_stopped == 0)
1370                 ixgbe_dev_close(eth_dev);
1371
1372         eth_dev->dev_ops = NULL;
1373         eth_dev->rx_pkt_burst = NULL;
1374         eth_dev->tx_pkt_burst = NULL;
1375
1376         /* Unlock any pending hardware semaphore */
1377         ixgbe_swfw_lock_reset(hw);
1378
1379         /* disable uio intr before callback unregister */
1380         rte_intr_disable(intr_handle);
1381         rte_intr_callback_unregister(intr_handle,
1382                                      ixgbe_dev_interrupt_handler, eth_dev);
1383
1384         /* uninitialize PF if max_vfs not zero */
1385         ixgbe_pf_host_uninit(eth_dev);
1386
1387         rte_free(eth_dev->data->mac_addrs);
1388         eth_dev->data->mac_addrs = NULL;
1389
1390         rte_free(eth_dev->data->hash_mac_addrs);
1391         eth_dev->data->hash_mac_addrs = NULL;
1392
1393         /* remove all the fdir filters & hash */
1394         ixgbe_fdir_filter_uninit(eth_dev);
1395
1396         /* remove all the L2 tunnel filters & hash */
1397         ixgbe_l2_tn_filter_uninit(eth_dev);
1398
1399         /* Remove all ntuple filters of the device */
1400         ixgbe_ntuple_filter_uninit(eth_dev);
1401
1402         /* clear all the filters list */
1403         ixgbe_filterlist_flush();
1404
1405         /* Remove all Traffic Manager configuration */
1406         ixgbe_tm_conf_uninit(eth_dev);
1407
1408         return 0;
1409 }
1410
1411 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1412 {
1413         struct ixgbe_filter_info *filter_info =
1414                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1415         struct ixgbe_5tuple_filter *p_5tuple;
1416
1417         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1418                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1419                              p_5tuple,
1420                              entries);
1421                 rte_free(p_5tuple);
1422         }
1423         memset(filter_info->fivetuple_mask, 0,
1424                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1425
1426         return 0;
1427 }
1428
1429 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1430 {
1431         struct ixgbe_hw_fdir_info *fdir_info =
1432                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1433         struct ixgbe_fdir_filter *fdir_filter;
1434
1435                 if (fdir_info->hash_map)
1436                 rte_free(fdir_info->hash_map);
1437         if (fdir_info->hash_handle)
1438                 rte_hash_free(fdir_info->hash_handle);
1439
1440         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1441                 TAILQ_REMOVE(&fdir_info->fdir_list,
1442                              fdir_filter,
1443                              entries);
1444                 rte_free(fdir_filter);
1445         }
1446
1447         return 0;
1448 }
1449
1450 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1451 {
1452         struct ixgbe_l2_tn_info *l2_tn_info =
1453                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1454         struct ixgbe_l2_tn_filter *l2_tn_filter;
1455
1456         if (l2_tn_info->hash_map)
1457                 rte_free(l2_tn_info->hash_map);
1458         if (l2_tn_info->hash_handle)
1459                 rte_hash_free(l2_tn_info->hash_handle);
1460
1461         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1462                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1463                              l2_tn_filter,
1464                              entries);
1465                 rte_free(l2_tn_filter);
1466         }
1467
1468         return 0;
1469 }
1470
1471 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1472 {
1473         struct ixgbe_hw_fdir_info *fdir_info =
1474                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1475         char fdir_hash_name[RTE_HASH_NAMESIZE];
1476         struct rte_hash_parameters fdir_hash_params = {
1477                 .name = fdir_hash_name,
1478                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1479                 .key_len = sizeof(union ixgbe_atr_input),
1480                 .hash_func = rte_hash_crc,
1481                 .hash_func_init_val = 0,
1482                 .socket_id = rte_socket_id(),
1483         };
1484
1485         TAILQ_INIT(&fdir_info->fdir_list);
1486         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1487                  "fdir_%s", eth_dev->device->name);
1488         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1489         if (!fdir_info->hash_handle) {
1490                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1491                 return -EINVAL;
1492         }
1493         fdir_info->hash_map = rte_zmalloc("ixgbe",
1494                                           sizeof(struct ixgbe_fdir_filter *) *
1495                                           IXGBE_MAX_FDIR_FILTER_NUM,
1496                                           0);
1497         if (!fdir_info->hash_map) {
1498                 PMD_INIT_LOG(ERR,
1499                              "Failed to allocate memory for fdir hash map!");
1500                 return -ENOMEM;
1501         }
1502         fdir_info->mask_added = FALSE;
1503
1504         return 0;
1505 }
1506
1507 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1508 {
1509         struct ixgbe_l2_tn_info *l2_tn_info =
1510                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1511         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1512         struct rte_hash_parameters l2_tn_hash_params = {
1513                 .name = l2_tn_hash_name,
1514                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1515                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1516                 .hash_func = rte_hash_crc,
1517                 .hash_func_init_val = 0,
1518                 .socket_id = rte_socket_id(),
1519         };
1520
1521         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1522         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1523                  "l2_tn_%s", eth_dev->device->name);
1524         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1525         if (!l2_tn_info->hash_handle) {
1526                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1527                 return -EINVAL;
1528         }
1529         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1530                                    sizeof(struct ixgbe_l2_tn_filter *) *
1531                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1532                                    0);
1533         if (!l2_tn_info->hash_map) {
1534                 PMD_INIT_LOG(ERR,
1535                         "Failed to allocate memory for L2 TN hash map!");
1536                 return -ENOMEM;
1537         }
1538         l2_tn_info->e_tag_en = FALSE;
1539         l2_tn_info->e_tag_fwd_en = FALSE;
1540         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1541
1542         return 0;
1543 }
1544 /*
1545  * Negotiate mailbox API version with the PF.
1546  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1547  * Then we try to negotiate starting with the most recent one.
1548  * If all negotiation attempts fail, then we will proceed with
1549  * the default one (ixgbe_mbox_api_10).
1550  */
1551 static void
1552 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1553 {
1554         int32_t i;
1555
1556         /* start with highest supported, proceed down */
1557         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1558                 ixgbe_mbox_api_12,
1559                 ixgbe_mbox_api_11,
1560                 ixgbe_mbox_api_10,
1561         };
1562
1563         for (i = 0;
1564                         i != RTE_DIM(sup_ver) &&
1565                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1566                         i++)
1567                 ;
1568 }
1569
1570 static void
1571 generate_random_mac_addr(struct ether_addr *mac_addr)
1572 {
1573         uint64_t random;
1574
1575         /* Set Organizationally Unique Identifier (OUI) prefix. */
1576         mac_addr->addr_bytes[0] = 0x00;
1577         mac_addr->addr_bytes[1] = 0x09;
1578         mac_addr->addr_bytes[2] = 0xC0;
1579         /* Force indication of locally assigned MAC address. */
1580         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1581         /* Generate the last 3 bytes of the MAC address with a random number. */
1582         random = rte_rand();
1583         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1584 }
1585
1586 /*
1587  * Virtual Function device init
1588  */
1589 static int
1590 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1591 {
1592         int diag;
1593         uint32_t tc, tcs;
1594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1595         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1598         struct ixgbe_vfta *shadow_vfta =
1599                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1600         struct ixgbe_hwstrip *hwstrip =
1601                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1602         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1603
1604         PMD_INIT_FUNC_TRACE();
1605
1606         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1607         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1608         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1609
1610         /* for secondary processes, we don't initialise any further as primary
1611          * has already done this work. Only check we don't need a different
1612          * RX function
1613          */
1614         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1615                 struct ixgbe_tx_queue *txq;
1616                 /* TX queue function in primary, set by last queue initialized
1617                  * Tx queue may not initialized by primary process
1618                  */
1619                 if (eth_dev->data->tx_queues) {
1620                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1621                         ixgbe_set_tx_function(eth_dev, txq);
1622                 } else {
1623                         /* Use default TX function if we get here */
1624                         PMD_INIT_LOG(NOTICE,
1625                                      "No TX queues configured yet. Using default TX function.");
1626                 }
1627
1628                 ixgbe_set_rx_function(eth_dev);
1629
1630                 return 0;
1631         }
1632
1633         rte_eth_copy_pci_info(eth_dev, pci_dev);
1634         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1635
1636         hw->device_id = pci_dev->id.device_id;
1637         hw->vendor_id = pci_dev->id.vendor_id;
1638         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1639
1640         /* initialize the vfta */
1641         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1642
1643         /* initialize the hw strip bitmap*/
1644         memset(hwstrip, 0, sizeof(*hwstrip));
1645
1646         /* Initialize the shared code (base driver) */
1647         diag = ixgbe_init_shared_code(hw);
1648         if (diag != IXGBE_SUCCESS) {
1649                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1650                 return -EIO;
1651         }
1652
1653         /* init_mailbox_params */
1654         hw->mbx.ops.init_params(hw);
1655
1656         /* Reset the hw statistics */
1657         ixgbevf_dev_stats_reset(eth_dev);
1658
1659         /* Disable the interrupts for VF */
1660         ixgbevf_intr_disable(hw);
1661
1662         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1663         diag = hw->mac.ops.reset_hw(hw);
1664
1665         /*
1666          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1667          * the underlying PF driver has not assigned a MAC address to the VF.
1668          * In this case, assign a random MAC address.
1669          */
1670         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1671                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1672                 return diag;
1673         }
1674
1675         /* negotiate mailbox API version to use with the PF. */
1676         ixgbevf_negotiate_api(hw);
1677
1678         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1679         ixgbevf_get_queues(hw, &tcs, &tc);
1680
1681         /* Allocate memory for storing MAC addresses */
1682         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1683                                                hw->mac.num_rar_entries, 0);
1684         if (eth_dev->data->mac_addrs == NULL) {
1685                 PMD_INIT_LOG(ERR,
1686                              "Failed to allocate %u bytes needed to store "
1687                              "MAC addresses",
1688                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1689                 return -ENOMEM;
1690         }
1691
1692         /* Generate a random MAC address, if none was assigned by PF. */
1693         if (is_zero_ether_addr(perm_addr)) {
1694                 generate_random_mac_addr(perm_addr);
1695                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1696                 if (diag) {
1697                         rte_free(eth_dev->data->mac_addrs);
1698                         eth_dev->data->mac_addrs = NULL;
1699                         return diag;
1700                 }
1701                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1702                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1703                              "%02x:%02x:%02x:%02x:%02x:%02x",
1704                              perm_addr->addr_bytes[0],
1705                              perm_addr->addr_bytes[1],
1706                              perm_addr->addr_bytes[2],
1707                              perm_addr->addr_bytes[3],
1708                              perm_addr->addr_bytes[4],
1709                              perm_addr->addr_bytes[5]);
1710         }
1711
1712         /* Copy the permanent MAC address */
1713         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1714
1715         /* reset the hardware with the new settings */
1716         diag = hw->mac.ops.start_hw(hw);
1717         switch (diag) {
1718         case  0:
1719                 break;
1720
1721         default:
1722                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1723                 return -EIO;
1724         }
1725
1726         rte_intr_callback_register(intr_handle,
1727                                    ixgbevf_dev_interrupt_handler, eth_dev);
1728         rte_intr_enable(intr_handle);
1729         ixgbevf_intr_enable(hw);
1730
1731         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1732                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1733                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1734
1735         return 0;
1736 }
1737
1738 /* Virtual Function device uninit */
1739
1740 static int
1741 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1742 {
1743         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1744         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1745         struct ixgbe_hw *hw;
1746
1747         PMD_INIT_FUNC_TRACE();
1748
1749         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1750                 return -EPERM;
1751
1752         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1753
1754         if (hw->adapter_stopped == 0)
1755                 ixgbevf_dev_close(eth_dev);
1756
1757         eth_dev->dev_ops = NULL;
1758         eth_dev->rx_pkt_burst = NULL;
1759         eth_dev->tx_pkt_burst = NULL;
1760
1761         /* Disable the interrupts for VF */
1762         ixgbevf_intr_disable(hw);
1763
1764         rte_free(eth_dev->data->mac_addrs);
1765         eth_dev->data->mac_addrs = NULL;
1766
1767         rte_intr_disable(intr_handle);
1768         rte_intr_callback_unregister(intr_handle,
1769                                      ixgbevf_dev_interrupt_handler, eth_dev);
1770
1771         return 0;
1772 }
1773
1774 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1775         struct rte_pci_device *pci_dev)
1776 {
1777         return rte_eth_dev_pci_generic_probe(pci_dev,
1778                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1779 }
1780
1781 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1782 {
1783         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1784 }
1785
1786 static struct rte_pci_driver rte_ixgbe_pmd = {
1787         .id_table = pci_id_ixgbe_map,
1788         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1789         .probe = eth_ixgbe_pci_probe,
1790         .remove = eth_ixgbe_pci_remove,
1791 };
1792
1793 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1794         struct rte_pci_device *pci_dev)
1795 {
1796         return rte_eth_dev_pci_generic_probe(pci_dev,
1797                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1798 }
1799
1800 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1801 {
1802         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1803 }
1804
1805 /*
1806  * virtual function driver struct
1807  */
1808 static struct rte_pci_driver rte_ixgbevf_pmd = {
1809         .id_table = pci_id_ixgbevf_map,
1810         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1811         .probe = eth_ixgbevf_pci_probe,
1812         .remove = eth_ixgbevf_pci_remove,
1813 };
1814
1815 static int
1816 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1817 {
1818         struct ixgbe_hw *hw =
1819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820         struct ixgbe_vfta *shadow_vfta =
1821                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1822         uint32_t vfta;
1823         uint32_t vid_idx;
1824         uint32_t vid_bit;
1825
1826         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1827         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1828         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1829         if (on)
1830                 vfta |= vid_bit;
1831         else
1832                 vfta &= ~vid_bit;
1833         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1834
1835         /* update local VFTA copy */
1836         shadow_vfta->vfta[vid_idx] = vfta;
1837
1838         return 0;
1839 }
1840
1841 static void
1842 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1843 {
1844         if (on)
1845                 ixgbe_vlan_hw_strip_enable(dev, queue);
1846         else
1847                 ixgbe_vlan_hw_strip_disable(dev, queue);
1848 }
1849
1850 static int
1851 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1852                     enum rte_vlan_type vlan_type,
1853                     uint16_t tpid)
1854 {
1855         struct ixgbe_hw *hw =
1856                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857         int ret = 0;
1858         uint32_t reg;
1859         uint32_t qinq;
1860
1861         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1862         qinq &= IXGBE_DMATXCTL_GDV;
1863
1864         switch (vlan_type) {
1865         case ETH_VLAN_TYPE_INNER:
1866                 if (qinq) {
1867                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1868                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1869                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1870                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1871                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1872                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1873                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1874                 } else {
1875                         ret = -ENOTSUP;
1876                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1877                                     " by single VLAN");
1878                 }
1879                 break;
1880         case ETH_VLAN_TYPE_OUTER:
1881                 if (qinq) {
1882                         /* Only the high 16-bits is valid */
1883                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1884                                         IXGBE_EXVET_VET_EXT_SHIFT);
1885                 } else {
1886                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1887                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1888                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1889                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1890                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1891                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1892                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1893                 }
1894
1895                 break;
1896         default:
1897                 ret = -EINVAL;
1898                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1899                 break;
1900         }
1901
1902         return ret;
1903 }
1904
1905 void
1906 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1907 {
1908         struct ixgbe_hw *hw =
1909                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910         uint32_t vlnctrl;
1911
1912         PMD_INIT_FUNC_TRACE();
1913
1914         /* Filter Table Disable */
1915         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1916         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1917
1918         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1919 }
1920
1921 void
1922 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1923 {
1924         struct ixgbe_hw *hw =
1925                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         struct ixgbe_vfta *shadow_vfta =
1927                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1928         uint32_t vlnctrl;
1929         uint16_t i;
1930
1931         PMD_INIT_FUNC_TRACE();
1932
1933         /* Filter Table Enable */
1934         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1935         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1936         vlnctrl |= IXGBE_VLNCTRL_VFE;
1937
1938         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1939
1940         /* write whatever is in local vfta copy */
1941         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1942                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1943 }
1944
1945 static void
1946 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1947 {
1948         struct ixgbe_hwstrip *hwstrip =
1949                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1950         struct ixgbe_rx_queue *rxq;
1951
1952         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1953                 return;
1954
1955         if (on)
1956                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1957         else
1958                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1959
1960         if (queue >= dev->data->nb_rx_queues)
1961                 return;
1962
1963         rxq = dev->data->rx_queues[queue];
1964
1965         if (on)
1966                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1967         else
1968                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1969 }
1970
1971 static void
1972 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1973 {
1974         struct ixgbe_hw *hw =
1975                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1976         uint32_t ctrl;
1977
1978         PMD_INIT_FUNC_TRACE();
1979
1980         if (hw->mac.type == ixgbe_mac_82598EB) {
1981                 /* No queue level support */
1982                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1983                 return;
1984         }
1985
1986         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1987         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1988         ctrl &= ~IXGBE_RXDCTL_VME;
1989         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1990
1991         /* record those setting for HW strip per queue */
1992         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1993 }
1994
1995 static void
1996 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1997 {
1998         struct ixgbe_hw *hw =
1999                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2000         uint32_t ctrl;
2001
2002         PMD_INIT_FUNC_TRACE();
2003
2004         if (hw->mac.type == ixgbe_mac_82598EB) {
2005                 /* No queue level supported */
2006                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2007                 return;
2008         }
2009
2010         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2011         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2012         ctrl |= IXGBE_RXDCTL_VME;
2013         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2014
2015         /* record those setting for HW strip per queue */
2016         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2017 }
2018
2019 void
2020 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2021 {
2022         struct ixgbe_hw *hw =
2023                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024         uint32_t ctrl;
2025         uint16_t i;
2026         struct ixgbe_rx_queue *rxq;
2027
2028         PMD_INIT_FUNC_TRACE();
2029
2030         if (hw->mac.type == ixgbe_mac_82598EB) {
2031                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2032                 ctrl &= ~IXGBE_VLNCTRL_VME;
2033                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2034         } else {
2035                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2036                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2037                         rxq = dev->data->rx_queues[i];
2038                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2039                         ctrl &= ~IXGBE_RXDCTL_VME;
2040                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2041
2042                         /* record those setting for HW strip per queue */
2043                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2044                 }
2045         }
2046 }
2047
2048 void
2049 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2050 {
2051         struct ixgbe_hw *hw =
2052                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053         uint32_t ctrl;
2054         uint16_t i;
2055         struct ixgbe_rx_queue *rxq;
2056
2057         PMD_INIT_FUNC_TRACE();
2058
2059         if (hw->mac.type == ixgbe_mac_82598EB) {
2060                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2061                 ctrl |= IXGBE_VLNCTRL_VME;
2062                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2063         } else {
2064                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2065                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2066                         rxq = dev->data->rx_queues[i];
2067                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2068                         ctrl |= IXGBE_RXDCTL_VME;
2069                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2070
2071                         /* record those setting for HW strip per queue */
2072                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2073                 }
2074         }
2075 }
2076
2077 static void
2078 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2079 {
2080         struct ixgbe_hw *hw =
2081                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082         uint32_t ctrl;
2083
2084         PMD_INIT_FUNC_TRACE();
2085
2086         /* DMATXCTRL: Geric Double VLAN Disable */
2087         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2088         ctrl &= ~IXGBE_DMATXCTL_GDV;
2089         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2090
2091         /* CTRL_EXT: Global Double VLAN Disable */
2092         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2093         ctrl &= ~IXGBE_EXTENDED_VLAN;
2094         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2095
2096 }
2097
2098 static void
2099 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2100 {
2101         struct ixgbe_hw *hw =
2102                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         uint32_t ctrl;
2104
2105         PMD_INIT_FUNC_TRACE();
2106
2107         /* DMATXCTRL: Geric Double VLAN Enable */
2108         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2109         ctrl |= IXGBE_DMATXCTL_GDV;
2110         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2111
2112         /* CTRL_EXT: Global Double VLAN Enable */
2113         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2114         ctrl |= IXGBE_EXTENDED_VLAN;
2115         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2116
2117         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2118         if (hw->mac.type == ixgbe_mac_X550 ||
2119             hw->mac.type == ixgbe_mac_X550EM_x ||
2120             hw->mac.type == ixgbe_mac_X550EM_a) {
2121                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2122                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2123                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2124         }
2125
2126         /*
2127          * VET EXT field in the EXVET register = 0x8100 by default
2128          * So no need to change. Same to VT field of DMATXCTL register
2129          */
2130 }
2131
2132 static void
2133 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2134 {
2135         if (mask & ETH_VLAN_STRIP_MASK) {
2136                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2137                         ixgbe_vlan_hw_strip_enable_all(dev);
2138                 else
2139                         ixgbe_vlan_hw_strip_disable_all(dev);
2140         }
2141
2142         if (mask & ETH_VLAN_FILTER_MASK) {
2143                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2144                         ixgbe_vlan_hw_filter_enable(dev);
2145                 else
2146                         ixgbe_vlan_hw_filter_disable(dev);
2147         }
2148
2149         if (mask & ETH_VLAN_EXTEND_MASK) {
2150                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2151                         ixgbe_vlan_hw_extend_enable(dev);
2152                 else
2153                         ixgbe_vlan_hw_extend_disable(dev);
2154         }
2155 }
2156
2157 static void
2158 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2159 {
2160         struct ixgbe_hw *hw =
2161                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2162         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2163         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2164
2165         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2166         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2167 }
2168
2169 static int
2170 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2171 {
2172         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2173
2174         switch (nb_rx_q) {
2175         case 1:
2176         case 2:
2177                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2178                 break;
2179         case 4:
2180                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2181                 break;
2182         default:
2183                 return -EINVAL;
2184         }
2185
2186         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2187         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2188
2189         return 0;
2190 }
2191
2192 static int
2193 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2194 {
2195         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2196         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2197         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2198         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2199
2200         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2201                 /* check multi-queue mode */
2202                 switch (dev_conf->rxmode.mq_mode) {
2203                 case ETH_MQ_RX_VMDQ_DCB:
2204                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2205                         break;
2206                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2207                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2208                         PMD_INIT_LOG(ERR, "SRIOV active,"
2209                                         " unsupported mq_mode rx %d.",
2210                                         dev_conf->rxmode.mq_mode);
2211                         return -EINVAL;
2212                 case ETH_MQ_RX_RSS:
2213                 case ETH_MQ_RX_VMDQ_RSS:
2214                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2215                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2216                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2217                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2218                                                 " invalid queue number"
2219                                                 " for VMDQ RSS, allowed"
2220                                                 " value are 1, 2 or 4.");
2221                                         return -EINVAL;
2222                                 }
2223                         break;
2224                 case ETH_MQ_RX_VMDQ_ONLY:
2225                 case ETH_MQ_RX_NONE:
2226                         /* if nothing mq mode configure, use default scheme */
2227                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2228                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2229                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2230                         break;
2231                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2232                         /* SRIOV only works in VMDq enable mode */
2233                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2234                                         " wrong mq_mode rx %d.",
2235                                         dev_conf->rxmode.mq_mode);
2236                         return -EINVAL;
2237                 }
2238
2239                 switch (dev_conf->txmode.mq_mode) {
2240                 case ETH_MQ_TX_VMDQ_DCB:
2241                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2242                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2243                         break;
2244                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2245                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2246                         break;
2247                 }
2248
2249                 /* check valid queue number */
2250                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2251                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2252                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2253                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2254                                         " must be less than or equal to %d.",
2255                                         nb_rx_q, nb_tx_q,
2256                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2257                         return -EINVAL;
2258                 }
2259         } else {
2260                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2261                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2262                                           " not supported.");
2263                         return -EINVAL;
2264                 }
2265                 /* check configuration for vmdb+dcb mode */
2266                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2267                         const struct rte_eth_vmdq_dcb_conf *conf;
2268
2269                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2270                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2271                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2272                                 return -EINVAL;
2273                         }
2274                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2275                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2276                                conf->nb_queue_pools == ETH_32_POOLS)) {
2277                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2278                                                 " nb_queue_pools must be %d or %d.",
2279                                                 ETH_16_POOLS, ETH_32_POOLS);
2280                                 return -EINVAL;
2281                         }
2282                 }
2283                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2284                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2285
2286                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2287                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2288                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2289                                 return -EINVAL;
2290                         }
2291                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2292                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2293                                conf->nb_queue_pools == ETH_32_POOLS)) {
2294                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2295                                                 " nb_queue_pools != %d and"
2296                                                 " nb_queue_pools != %d.",
2297                                                 ETH_16_POOLS, ETH_32_POOLS);
2298                                 return -EINVAL;
2299                         }
2300                 }
2301
2302                 /* For DCB mode check our configuration before we go further */
2303                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2304                         const struct rte_eth_dcb_rx_conf *conf;
2305
2306                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2307                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2308                                                  IXGBE_DCB_NB_QUEUES);
2309                                 return -EINVAL;
2310                         }
2311                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2312                         if (!(conf->nb_tcs == ETH_4_TCS ||
2313                                conf->nb_tcs == ETH_8_TCS)) {
2314                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2315                                                 " and nb_tcs != %d.",
2316                                                 ETH_4_TCS, ETH_8_TCS);
2317                                 return -EINVAL;
2318                         }
2319                 }
2320
2321                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2322                         const struct rte_eth_dcb_tx_conf *conf;
2323
2324                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2325                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2326                                                  IXGBE_DCB_NB_QUEUES);
2327                                 return -EINVAL;
2328                         }
2329                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2330                         if (!(conf->nb_tcs == ETH_4_TCS ||
2331                                conf->nb_tcs == ETH_8_TCS)) {
2332                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2333                                                 " and nb_tcs != %d.",
2334                                                 ETH_4_TCS, ETH_8_TCS);
2335                                 return -EINVAL;
2336                         }
2337                 }
2338
2339                 /*
2340                  * When DCB/VT is off, maximum number of queues changes,
2341                  * except for 82598EB, which remains constant.
2342                  */
2343                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2344                                 hw->mac.type != ixgbe_mac_82598EB) {
2345                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2346                                 PMD_INIT_LOG(ERR,
2347                                              "Neither VT nor DCB are enabled, "
2348                                              "nb_tx_q > %d.",
2349                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2350                                 return -EINVAL;
2351                         }
2352                 }
2353         }
2354         return 0;
2355 }
2356
2357 static int
2358 ixgbe_dev_configure(struct rte_eth_dev *dev)
2359 {
2360         struct ixgbe_interrupt *intr =
2361                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2362         struct ixgbe_adapter *adapter =
2363                 (struct ixgbe_adapter *)dev->data->dev_private;
2364         int ret;
2365
2366         PMD_INIT_FUNC_TRACE();
2367         /* multipe queue mode checking */
2368         ret  = ixgbe_check_mq_mode(dev);
2369         if (ret != 0) {
2370                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2371                             ret);
2372                 return ret;
2373         }
2374
2375         /* set flag to update link status after init */
2376         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2377
2378         /*
2379          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2380          * allocation or vector Rx preconditions we will reset it.
2381          */
2382         adapter->rx_bulk_alloc_allowed = true;
2383         adapter->rx_vec_allowed = true;
2384
2385         return 0;
2386 }
2387
2388 static void
2389 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2390 {
2391         struct ixgbe_hw *hw =
2392                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393         struct ixgbe_interrupt *intr =
2394                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2395         uint32_t gpie;
2396
2397         /* only set up it on X550EM_X */
2398         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2399                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2400                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2401                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2402                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2403                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2404         }
2405 }
2406
2407 int
2408 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2409                         uint16_t tx_rate, uint64_t q_msk)
2410 {
2411         struct ixgbe_hw *hw;
2412         struct ixgbe_vf_info *vfinfo;
2413         struct rte_eth_link link;
2414         uint8_t  nb_q_per_pool;
2415         uint32_t queue_stride;
2416         uint32_t queue_idx, idx = 0, vf_idx;
2417         uint32_t queue_end;
2418         uint16_t total_rate = 0;
2419         struct rte_pci_device *pci_dev;
2420
2421         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2422         rte_eth_link_get_nowait(dev->data->port_id, &link);
2423
2424         if (vf >= pci_dev->max_vfs)
2425                 return -EINVAL;
2426
2427         if (tx_rate > link.link_speed)
2428                 return -EINVAL;
2429
2430         if (q_msk == 0)
2431                 return 0;
2432
2433         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2434         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2435         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2436         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2437         queue_idx = vf * queue_stride;
2438         queue_end = queue_idx + nb_q_per_pool - 1;
2439         if (queue_end >= hw->mac.max_tx_queues)
2440                 return -EINVAL;
2441
2442         if (vfinfo) {
2443                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2444                         if (vf_idx == vf)
2445                                 continue;
2446                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2447                                 idx++)
2448                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2449                 }
2450         } else {
2451                 return -EINVAL;
2452         }
2453
2454         /* Store tx_rate for this vf. */
2455         for (idx = 0; idx < nb_q_per_pool; idx++) {
2456                 if (((uint64_t)0x1 << idx) & q_msk) {
2457                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2458                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2459                         total_rate += tx_rate;
2460                 }
2461         }
2462
2463         if (total_rate > dev->data->dev_link.link_speed) {
2464                 /* Reset stored TX rate of the VF if it causes exceed
2465                  * link speed.
2466                  */
2467                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2468                 return -EINVAL;
2469         }
2470
2471         /* Set RTTBCNRC of each queue/pool for vf X  */
2472         for (; queue_idx <= queue_end; queue_idx++) {
2473                 if (0x1 & q_msk)
2474                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2475                 q_msk = q_msk >> 1;
2476         }
2477
2478         return 0;
2479 }
2480
2481 /*
2482  * Configure device link speed and setup link.
2483  * It returns 0 on success.
2484  */
2485 static int
2486 ixgbe_dev_start(struct rte_eth_dev *dev)
2487 {
2488         struct ixgbe_hw *hw =
2489                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490         struct ixgbe_vf_info *vfinfo =
2491                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2492         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2493         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2494         uint32_t intr_vector = 0;
2495         int err, link_up = 0, negotiate = 0;
2496         uint32_t speed = 0;
2497         int mask = 0;
2498         int status;
2499         uint16_t vf, idx;
2500         uint32_t *link_speeds;
2501         struct ixgbe_tm_conf *tm_conf =
2502                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2503
2504         PMD_INIT_FUNC_TRACE();
2505
2506         /* IXGBE devices don't support:
2507         *    - half duplex (checked afterwards for valid speeds)
2508         *    - fixed speed: TODO implement
2509         */
2510         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2511                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2512                              dev->data->port_id);
2513                 return -EINVAL;
2514         }
2515
2516         /* disable uio/vfio intr/eventfd mapping */
2517         rte_intr_disable(intr_handle);
2518
2519         /* stop adapter */
2520         hw->adapter_stopped = 0;
2521         ixgbe_stop_adapter(hw);
2522
2523         /* reinitialize adapter
2524          * this calls reset and start
2525          */
2526         status = ixgbe_pf_reset_hw(hw);
2527         if (status != 0)
2528                 return -1;
2529         hw->mac.ops.start_hw(hw);
2530         hw->mac.get_link_status = true;
2531
2532         /* configure PF module if SRIOV enabled */
2533         ixgbe_pf_host_configure(dev);
2534
2535         ixgbe_dev_phy_intr_setup(dev);
2536
2537         /* check and configure queue intr-vector mapping */
2538         if ((rte_intr_cap_multiple(intr_handle) ||
2539              !RTE_ETH_DEV_SRIOV(dev).active) &&
2540             dev->data->dev_conf.intr_conf.rxq != 0) {
2541                 intr_vector = dev->data->nb_rx_queues;
2542                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2543                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2544                                         IXGBE_MAX_INTR_QUEUE_NUM);
2545                         return -ENOTSUP;
2546                 }
2547                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2548                         return -1;
2549         }
2550
2551         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2552                 intr_handle->intr_vec =
2553                         rte_zmalloc("intr_vec",
2554                                     dev->data->nb_rx_queues * sizeof(int), 0);
2555                 if (intr_handle->intr_vec == NULL) {
2556                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2557                                      " intr_vec", dev->data->nb_rx_queues);
2558                         return -ENOMEM;
2559                 }
2560         }
2561
2562         /* confiugre msix for sleep until rx interrupt */
2563         ixgbe_configure_msix(dev);
2564
2565         /* initialize transmission unit */
2566         ixgbe_dev_tx_init(dev);
2567
2568         /* This can fail when allocating mbufs for descriptor rings */
2569         err = ixgbe_dev_rx_init(dev);
2570         if (err) {
2571                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2572                 goto error;
2573         }
2574
2575     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2576                 ETH_VLAN_EXTEND_MASK;
2577         ixgbe_vlan_offload_set(dev, mask);
2578
2579         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2580                 /* Enable vlan filtering for VMDq */
2581                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2582         }
2583
2584         /* Configure DCB hw */
2585         ixgbe_configure_dcb(dev);
2586
2587         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2588                 err = ixgbe_fdir_configure(dev);
2589                 if (err)
2590                         goto error;
2591         }
2592
2593         /* Restore vf rate limit */
2594         if (vfinfo != NULL) {
2595                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2596                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2597                                 if (vfinfo[vf].tx_rate[idx] != 0)
2598                                         ixgbe_set_vf_rate_limit(
2599                                                 dev, vf,
2600                                                 vfinfo[vf].tx_rate[idx],
2601                                                 1 << idx);
2602         }
2603
2604         ixgbe_restore_statistics_mapping(dev);
2605
2606         err = ixgbe_dev_rxtx_start(dev);
2607         if (err < 0) {
2608                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2609                 goto error;
2610         }
2611
2612         /* Skip link setup if loopback mode is enabled for 82599. */
2613         if (hw->mac.type == ixgbe_mac_82599EB &&
2614                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2615                 goto skip_link_setup;
2616
2617         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2618                 err = hw->mac.ops.setup_sfp(hw);
2619                 if (err)
2620                         goto error;
2621         }
2622
2623         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2624                 /* Turn on the copper */
2625                 ixgbe_set_phy_power(hw, true);
2626         } else {
2627                 /* Turn on the laser */
2628                 ixgbe_enable_tx_laser(hw);
2629         }
2630
2631         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2632         if (err)
2633                 goto error;
2634         dev->data->dev_link.link_status = link_up;
2635
2636         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2637         if (err)
2638                 goto error;
2639
2640         link_speeds = &dev->data->dev_conf.link_speeds;
2641         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2642                         ETH_LINK_SPEED_10G)) {
2643                 PMD_INIT_LOG(ERR, "Invalid link setting");
2644                 goto error;
2645         }
2646
2647         speed = 0x0;
2648         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2649                 switch (hw->mac.type) {
2650                 case ixgbe_mac_82598EB:
2651                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2652                         break;
2653                 case ixgbe_mac_82599EB:
2654                 case ixgbe_mac_X540:
2655                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2656                         break;
2657                 case ixgbe_mac_X550:
2658                 case ixgbe_mac_X550EM_x:
2659                 case ixgbe_mac_X550EM_a:
2660                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2661                         break;
2662                 default:
2663                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2664                 }
2665         } else {
2666                 if (*link_speeds & ETH_LINK_SPEED_10G)
2667                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2668                 if (*link_speeds & ETH_LINK_SPEED_1G)
2669                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2670                 if (*link_speeds & ETH_LINK_SPEED_100M)
2671                         speed |= IXGBE_LINK_SPEED_100_FULL;
2672         }
2673
2674         err = ixgbe_setup_link(hw, speed, link_up);
2675         if (err)
2676                 goto error;
2677
2678 skip_link_setup:
2679
2680         if (rte_intr_allow_others(intr_handle)) {
2681                 /* check if lsc interrupt is enabled */
2682                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2683                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2684                 else
2685                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2686                 ixgbe_dev_macsec_interrupt_setup(dev);
2687         } else {
2688                 rte_intr_callback_unregister(intr_handle,
2689                                              ixgbe_dev_interrupt_handler, dev);
2690                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2691                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2692                                      " no intr multiplex");
2693         }
2694
2695         /* check if rxq interrupt is enabled */
2696         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2697             rte_intr_dp_is_en(intr_handle))
2698                 ixgbe_dev_rxq_interrupt_setup(dev);
2699
2700         /* enable uio/vfio intr/eventfd mapping */
2701         rte_intr_enable(intr_handle);
2702
2703         /* resume enabled intr since hw reset */
2704         ixgbe_enable_intr(dev);
2705         ixgbe_l2_tunnel_conf(dev);
2706         ixgbe_filter_restore(dev);
2707
2708         if (tm_conf->root && !tm_conf->committed)
2709                 PMD_DRV_LOG(WARNING,
2710                             "please call hierarchy_commit() "
2711                             "before starting the port");
2712
2713         return 0;
2714
2715 error:
2716         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2717         ixgbe_dev_clear_queues(dev);
2718         return -EIO;
2719 }
2720
2721 /*
2722  * Stop device: disable rx and tx functions to allow for reconfiguring.
2723  */
2724 static void
2725 ixgbe_dev_stop(struct rte_eth_dev *dev)
2726 {
2727         struct rte_eth_link link;
2728         struct ixgbe_hw *hw =
2729                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2730         struct ixgbe_vf_info *vfinfo =
2731                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2732         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2733         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2734         int vf;
2735         struct ixgbe_tm_conf *tm_conf =
2736                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2737
2738         PMD_INIT_FUNC_TRACE();
2739
2740         /* disable interrupts */
2741         ixgbe_disable_intr(hw);
2742
2743         /* reset the NIC */
2744         ixgbe_pf_reset_hw(hw);
2745         hw->adapter_stopped = 0;
2746
2747         /* stop adapter */
2748         ixgbe_stop_adapter(hw);
2749
2750         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2751                 vfinfo[vf].clear_to_send = false;
2752
2753         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2754                 /* Turn off the copper */
2755                 ixgbe_set_phy_power(hw, false);
2756         } else {
2757                 /* Turn off the laser */
2758                 ixgbe_disable_tx_laser(hw);
2759         }
2760
2761         ixgbe_dev_clear_queues(dev);
2762
2763         /* Clear stored conf */
2764         dev->data->scattered_rx = 0;
2765         dev->data->lro = 0;
2766
2767         /* Clear recorded link status */
2768         memset(&link, 0, sizeof(link));
2769         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2770
2771         if (!rte_intr_allow_others(intr_handle))
2772                 /* resume to the default handler */
2773                 rte_intr_callback_register(intr_handle,
2774                                            ixgbe_dev_interrupt_handler,
2775                                            (void *)dev);
2776
2777         /* Clean datapath event and queue/vec mapping */
2778         rte_intr_efd_disable(intr_handle);
2779         if (intr_handle->intr_vec != NULL) {
2780                 rte_free(intr_handle->intr_vec);
2781                 intr_handle->intr_vec = NULL;
2782         }
2783
2784         /* reset hierarchy commit */
2785         tm_conf->committed = false;
2786 }
2787
2788 /*
2789  * Set device link up: enable tx.
2790  */
2791 static int
2792 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2793 {
2794         struct ixgbe_hw *hw =
2795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2796         if (hw->mac.type == ixgbe_mac_82599EB) {
2797 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2798                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2799                         /* Not suported in bypass mode */
2800                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2801                                      "by device id 0x%x", hw->device_id);
2802                         return -ENOTSUP;
2803                 }
2804 #endif
2805         }
2806
2807         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2808                 /* Turn on the copper */
2809                 ixgbe_set_phy_power(hw, true);
2810         } else {
2811                 /* Turn on the laser */
2812                 ixgbe_enable_tx_laser(hw);
2813         }
2814
2815         return 0;
2816 }
2817
2818 /*
2819  * Set device link down: disable tx.
2820  */
2821 static int
2822 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2823 {
2824         struct ixgbe_hw *hw =
2825                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2826         if (hw->mac.type == ixgbe_mac_82599EB) {
2827 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2828                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2829                         /* Not suported in bypass mode */
2830                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2831                                      "by device id 0x%x", hw->device_id);
2832                         return -ENOTSUP;
2833                 }
2834 #endif
2835         }
2836
2837         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2838                 /* Turn off the copper */
2839                 ixgbe_set_phy_power(hw, false);
2840         } else {
2841                 /* Turn off the laser */
2842                 ixgbe_disable_tx_laser(hw);
2843         }
2844
2845         return 0;
2846 }
2847
2848 /*
2849  * Reset and stop device.
2850  */
2851 static void
2852 ixgbe_dev_close(struct rte_eth_dev *dev)
2853 {
2854         struct ixgbe_hw *hw =
2855                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2856
2857         PMD_INIT_FUNC_TRACE();
2858
2859         ixgbe_pf_reset_hw(hw);
2860
2861         ixgbe_dev_stop(dev);
2862         hw->adapter_stopped = 1;
2863
2864         ixgbe_dev_free_queues(dev);
2865
2866         ixgbe_disable_pcie_master(hw);
2867
2868         /* reprogram the RAR[0] in case user changed it. */
2869         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2870 }
2871
2872 /*
2873  * Reset PF device.
2874  */
2875 static int
2876 ixgbe_dev_reset(struct rte_eth_dev *dev)
2877 {
2878         int ret;
2879
2880         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2881          * its VF to make them align with it. The detailed notification
2882          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2883          * To avoid unexpected behavior in VF, currently reset of PF with
2884          * SR-IOV activation is not supported. It might be supported later.
2885          */
2886         if (dev->data->sriov.active)
2887                 return -ENOTSUP;
2888
2889         ret = eth_ixgbe_dev_uninit(dev);
2890         if (ret)
2891                 return ret;
2892
2893         ret = eth_ixgbe_dev_init(dev);
2894
2895         return ret;
2896 }
2897
2898 static void
2899 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2900                            struct ixgbe_hw_stats *hw_stats,
2901                            struct ixgbe_macsec_stats *macsec_stats,
2902                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2903                            uint64_t *total_qprc, uint64_t *total_qprdc)
2904 {
2905         uint32_t bprc, lxon, lxoff, total;
2906         uint32_t delta_gprc = 0;
2907         unsigned i;
2908         /* Workaround for RX byte count not including CRC bytes when CRC
2909          * strip is enabled. CRC bytes are removed from counters when crc_strip
2910          * is disabled.
2911          */
2912         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2913                         IXGBE_HLREG0_RXCRCSTRP);
2914
2915         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2916         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2917         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2918         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2919
2920         for (i = 0; i < 8; i++) {
2921                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2922
2923                 /* global total per queue */
2924                 hw_stats->mpc[i] += mp;
2925                 /* Running comprehensive total for stats display */
2926                 *total_missed_rx += hw_stats->mpc[i];
2927                 if (hw->mac.type == ixgbe_mac_82598EB) {
2928                         hw_stats->rnbc[i] +=
2929                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2930                         hw_stats->pxonrxc[i] +=
2931                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2932                         hw_stats->pxoffrxc[i] +=
2933                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2934                 } else {
2935                         hw_stats->pxonrxc[i] +=
2936                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2937                         hw_stats->pxoffrxc[i] +=
2938                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2939                         hw_stats->pxon2offc[i] +=
2940                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2941                 }
2942                 hw_stats->pxontxc[i] +=
2943                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2944                 hw_stats->pxofftxc[i] +=
2945                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2946         }
2947         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2948                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2949                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2950                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2951
2952                 delta_gprc += delta_qprc;
2953
2954                 hw_stats->qprc[i] += delta_qprc;
2955                 hw_stats->qptc[i] += delta_qptc;
2956
2957                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2958                 hw_stats->qbrc[i] +=
2959                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2960                 if (crc_strip == 0)
2961                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2962
2963                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2964                 hw_stats->qbtc[i] +=
2965                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2966
2967                 hw_stats->qprdc[i] += delta_qprdc;
2968                 *total_qprdc += hw_stats->qprdc[i];
2969
2970                 *total_qprc += hw_stats->qprc[i];
2971                 *total_qbrc += hw_stats->qbrc[i];
2972         }
2973         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2974         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2975         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2976
2977         /*
2978          * An errata states that gprc actually counts good + missed packets:
2979          * Workaround to set gprc to summated queue packet receives
2980          */
2981         hw_stats->gprc = *total_qprc;
2982
2983         if (hw->mac.type != ixgbe_mac_82598EB) {
2984                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2985                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2986                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2987                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2988                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2989                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2990                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2991                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2992         } else {
2993                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2994                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2995                 /* 82598 only has a counter in the high register */
2996                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2997                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2998                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2999         }
3000         uint64_t old_tpr = hw_stats->tpr;
3001
3002         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3003         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3004
3005         if (crc_strip == 0)
3006                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3007
3008         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3009         hw_stats->gptc += delta_gptc;
3010         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3011         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3012
3013         /*
3014          * Workaround: mprc hardware is incorrectly counting
3015          * broadcasts, so for now we subtract those.
3016          */
3017         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3018         hw_stats->bprc += bprc;
3019         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3020         if (hw->mac.type == ixgbe_mac_82598EB)
3021                 hw_stats->mprc -= bprc;
3022
3023         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3024         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3025         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3026         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3027         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3028         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3029
3030         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3031         hw_stats->lxontxc += lxon;
3032         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3033         hw_stats->lxofftxc += lxoff;
3034         total = lxon + lxoff;
3035
3036         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3037         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3038         hw_stats->gptc -= total;
3039         hw_stats->mptc -= total;
3040         hw_stats->ptc64 -= total;
3041         hw_stats->gotc -= total * ETHER_MIN_LEN;
3042
3043         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3044         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3045         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3046         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3047         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3048         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3049         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3050         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3051         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3052         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3053         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3054         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3055         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3056         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3057         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3058         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3059         /* Only read FCOE on 82599 */
3060         if (hw->mac.type != ixgbe_mac_82598EB) {
3061                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3062                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3063                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3064                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3065                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3066         }
3067
3068         /* Flow Director Stats registers */
3069         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3070         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3071
3072         /* MACsec Stats registers */
3073         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3074         macsec_stats->out_pkts_encrypted +=
3075                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3076         macsec_stats->out_pkts_protected +=
3077                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3078         macsec_stats->out_octets_encrypted +=
3079                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3080         macsec_stats->out_octets_protected +=
3081                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3082         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3083         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3084         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3085         macsec_stats->in_pkts_unknownsci +=
3086                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3087         macsec_stats->in_octets_decrypted +=
3088                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3089         macsec_stats->in_octets_validated +=
3090                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3091         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3092         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3093         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3094         for (i = 0; i < 2; i++) {
3095                 macsec_stats->in_pkts_ok +=
3096                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3097                 macsec_stats->in_pkts_invalid +=
3098                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3099                 macsec_stats->in_pkts_notvalid +=
3100                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3101         }
3102         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3103         macsec_stats->in_pkts_notusingsa +=
3104                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3105 }
3106
3107 /*
3108  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3109  */
3110 static void
3111 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3112 {
3113         struct ixgbe_hw *hw =
3114                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3115         struct ixgbe_hw_stats *hw_stats =
3116                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3117         struct ixgbe_macsec_stats *macsec_stats =
3118                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3119                                 dev->data->dev_private);
3120         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3121         unsigned i;
3122
3123         total_missed_rx = 0;
3124         total_qbrc = 0;
3125         total_qprc = 0;
3126         total_qprdc = 0;
3127
3128         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3129                         &total_qbrc, &total_qprc, &total_qprdc);
3130
3131         if (stats == NULL)
3132                 return;
3133
3134         /* Fill out the rte_eth_stats statistics structure */
3135         stats->ipackets = total_qprc;
3136         stats->ibytes = total_qbrc;
3137         stats->opackets = hw_stats->gptc;
3138         stats->obytes = hw_stats->gotc;
3139
3140         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3141                 stats->q_ipackets[i] = hw_stats->qprc[i];
3142                 stats->q_opackets[i] = hw_stats->qptc[i];
3143                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3144                 stats->q_obytes[i] = hw_stats->qbtc[i];
3145                 stats->q_errors[i] = hw_stats->qprdc[i];
3146         }
3147
3148         /* Rx Errors */
3149         stats->imissed  = total_missed_rx;
3150         stats->ierrors  = hw_stats->crcerrs +
3151                           hw_stats->mspdc +
3152                           hw_stats->rlec +
3153                           hw_stats->ruc +
3154                           hw_stats->roc +
3155                           hw_stats->illerrc +
3156                           hw_stats->errbc +
3157                           hw_stats->rfc +
3158                           hw_stats->fccrc +
3159                           hw_stats->fclast;
3160
3161         /* Tx Errors */
3162         stats->oerrors  = 0;
3163 }
3164
3165 static void
3166 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3167 {
3168         struct ixgbe_hw_stats *stats =
3169                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3170
3171         /* HW registers are cleared on read */
3172         ixgbe_dev_stats_get(dev, NULL);
3173
3174         /* Reset software totals */
3175         memset(stats, 0, sizeof(*stats));
3176 }
3177
3178 /* This function calculates the number of xstats based on the current config */
3179 static unsigned
3180 ixgbe_xstats_calc_num(void) {
3181         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3182                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3183                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3184 }
3185
3186 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3187         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3188 {
3189         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3190         unsigned stat, i, count;
3191
3192         if (xstats_names != NULL) {
3193                 count = 0;
3194
3195                 /* Note: limit >= cnt_stats checked upstream
3196                  * in rte_eth_xstats_names()
3197                  */
3198
3199                 /* Extended stats from ixgbe_hw_stats */
3200                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3201                         snprintf(xstats_names[count].name,
3202                                 sizeof(xstats_names[count].name),
3203                                 "%s",
3204                                 rte_ixgbe_stats_strings[i].name);
3205                         count++;
3206                 }
3207
3208                 /* MACsec Stats */
3209                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3210                         snprintf(xstats_names[count].name,
3211                                 sizeof(xstats_names[count].name),
3212                                 "%s",
3213                                 rte_ixgbe_macsec_strings[i].name);
3214                         count++;
3215                 }
3216
3217                 /* RX Priority Stats */
3218                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3219                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3220                                 snprintf(xstats_names[count].name,
3221                                         sizeof(xstats_names[count].name),
3222                                         "rx_priority%u_%s", i,
3223                                         rte_ixgbe_rxq_strings[stat].name);
3224                                 count++;
3225                         }
3226                 }
3227
3228                 /* TX Priority Stats */
3229                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3230                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3231                                 snprintf(xstats_names[count].name,
3232                                         sizeof(xstats_names[count].name),
3233                                         "tx_priority%u_%s", i,
3234                                         rte_ixgbe_txq_strings[stat].name);
3235                                 count++;
3236                         }
3237                 }
3238         }
3239         return cnt_stats;
3240 }
3241
3242 static int ixgbe_dev_xstats_get_names_by_id(
3243         struct rte_eth_dev *dev,
3244         struct rte_eth_xstat_name *xstats_names,
3245         const uint64_t *ids,
3246         unsigned int limit)
3247 {
3248         if (!ids) {
3249                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3250                 unsigned int stat, i, count;
3251
3252                 if (xstats_names != NULL) {
3253                         count = 0;
3254
3255                         /* Note: limit >= cnt_stats checked upstream
3256                          * in rte_eth_xstats_names()
3257                          */
3258
3259                         /* Extended stats from ixgbe_hw_stats */
3260                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3261                                 snprintf(xstats_names[count].name,
3262                                         sizeof(xstats_names[count].name),
3263                                         "%s",
3264                                         rte_ixgbe_stats_strings[i].name);
3265                                 count++;
3266                         }
3267
3268                         /* MACsec Stats */
3269                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3270                                 snprintf(xstats_names[count].name,
3271                                         sizeof(xstats_names[count].name),
3272                                         "%s",
3273                                         rte_ixgbe_macsec_strings[i].name);
3274                                 count++;
3275                         }
3276
3277                         /* RX Priority Stats */
3278                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3279                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3280                                         snprintf(xstats_names[count].name,
3281                                             sizeof(xstats_names[count].name),
3282                                             "rx_priority%u_%s", i,
3283                                             rte_ixgbe_rxq_strings[stat].name);
3284                                         count++;
3285                                 }
3286                         }
3287
3288                         /* TX Priority Stats */
3289                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3290                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3291                                         snprintf(xstats_names[count].name,
3292                                             sizeof(xstats_names[count].name),
3293                                             "tx_priority%u_%s", i,
3294                                             rte_ixgbe_txq_strings[stat].name);
3295                                         count++;
3296                                 }
3297                         }
3298                 }
3299                 return cnt_stats;
3300         }
3301
3302         uint16_t i;
3303         uint16_t size = ixgbe_xstats_calc_num();
3304         struct rte_eth_xstat_name xstats_names_copy[size];
3305
3306         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3307                         size);
3308
3309         for (i = 0; i < limit; i++) {
3310                 if (ids[i] >= size) {
3311                         PMD_INIT_LOG(ERR, "id value isn't valid");
3312                         return -1;
3313                 }
3314                 strcpy(xstats_names[i].name,
3315                                 xstats_names_copy[ids[i]].name);
3316         }
3317         return limit;
3318 }
3319
3320 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3321         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3322 {
3323         unsigned i;
3324
3325         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3326                 return -ENOMEM;
3327
3328         if (xstats_names != NULL)
3329                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3330                         snprintf(xstats_names[i].name,
3331                                 sizeof(xstats_names[i].name),
3332                                 "%s", rte_ixgbevf_stats_strings[i].name);
3333         return IXGBEVF_NB_XSTATS;
3334 }
3335
3336 static int
3337 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3338                                          unsigned n)
3339 {
3340         struct ixgbe_hw *hw =
3341                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3342         struct ixgbe_hw_stats *hw_stats =
3343                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3344         struct ixgbe_macsec_stats *macsec_stats =
3345                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3346                                 dev->data->dev_private);
3347         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3348         unsigned i, stat, count = 0;
3349
3350         count = ixgbe_xstats_calc_num();
3351
3352         if (n < count)
3353                 return count;
3354
3355         total_missed_rx = 0;
3356         total_qbrc = 0;
3357         total_qprc = 0;
3358         total_qprdc = 0;
3359
3360         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3361                         &total_qbrc, &total_qprc, &total_qprdc);
3362
3363         /* If this is a reset xstats is NULL, and we have cleared the
3364          * registers by reading them.
3365          */
3366         if (!xstats)
3367                 return 0;
3368
3369         /* Extended stats from ixgbe_hw_stats */
3370         count = 0;
3371         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3372                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3373                                 rte_ixgbe_stats_strings[i].offset);
3374                 xstats[count].id = count;
3375                 count++;
3376         }
3377
3378         /* MACsec Stats */
3379         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3380                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3381                                 rte_ixgbe_macsec_strings[i].offset);
3382                 xstats[count].id = count;
3383                 count++;
3384         }
3385
3386         /* RX Priority Stats */
3387         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3388                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3389                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3390                                         rte_ixgbe_rxq_strings[stat].offset +
3391                                         (sizeof(uint64_t) * i));
3392                         xstats[count].id = count;
3393                         count++;
3394                 }
3395         }
3396
3397         /* TX Priority Stats */
3398         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3399                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3400                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3401                                         rte_ixgbe_txq_strings[stat].offset +
3402                                         (sizeof(uint64_t) * i));
3403                         xstats[count].id = count;
3404                         count++;
3405                 }
3406         }
3407         return count;
3408 }
3409
3410 static int
3411 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3412                 uint64_t *values, unsigned int n)
3413 {
3414         if (!ids) {
3415                 struct ixgbe_hw *hw =
3416                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417                 struct ixgbe_hw_stats *hw_stats =
3418                                 IXGBE_DEV_PRIVATE_TO_STATS(
3419                                                 dev->data->dev_private);
3420                 struct ixgbe_macsec_stats *macsec_stats =
3421                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3422                                         dev->data->dev_private);
3423                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3424                 unsigned int i, stat, count = 0;
3425
3426                 count = ixgbe_xstats_calc_num();
3427
3428                 if (!ids && n < count)
3429                         return count;
3430
3431                 total_missed_rx = 0;
3432                 total_qbrc = 0;
3433                 total_qprc = 0;
3434                 total_qprdc = 0;
3435
3436                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3437                                 &total_missed_rx, &total_qbrc, &total_qprc,
3438                                 &total_qprdc);
3439
3440                 /* If this is a reset xstats is NULL, and we have cleared the
3441                  * registers by reading them.
3442                  */
3443                 if (!ids && !values)
3444                         return 0;
3445
3446                 /* Extended stats from ixgbe_hw_stats */
3447                 count = 0;
3448                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3449                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3450                                         rte_ixgbe_stats_strings[i].offset);
3451                         count++;
3452                 }
3453
3454                 /* MACsec Stats */
3455                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3456                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3457                                         rte_ixgbe_macsec_strings[i].offset);
3458                         count++;
3459                 }
3460
3461                 /* RX Priority Stats */
3462                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3463                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3464                                 values[count] =
3465                                         *(uint64_t *)(((char *)hw_stats) +
3466                                         rte_ixgbe_rxq_strings[stat].offset +
3467                                         (sizeof(uint64_t) * i));
3468                                 count++;
3469                         }
3470                 }
3471
3472                 /* TX Priority Stats */
3473                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3474                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3475                                 values[count] =
3476                                         *(uint64_t *)(((char *)hw_stats) +
3477                                         rte_ixgbe_txq_strings[stat].offset +
3478                                         (sizeof(uint64_t) * i));
3479                                 count++;
3480                         }
3481                 }
3482                 return count;
3483         }
3484
3485         uint16_t i;
3486         uint16_t size = ixgbe_xstats_calc_num();
3487         uint64_t values_copy[size];
3488
3489         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3490
3491         for (i = 0; i < n; i++) {
3492                 if (ids[i] >= size) {
3493                         PMD_INIT_LOG(ERR, "id value isn't valid");
3494                         return -1;
3495                 }
3496                 values[i] = values_copy[ids[i]];
3497         }
3498         return n;
3499 }
3500
3501 static void
3502 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3503 {
3504         struct ixgbe_hw_stats *stats =
3505                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3506         struct ixgbe_macsec_stats *macsec_stats =
3507                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3508                                 dev->data->dev_private);
3509
3510         unsigned count = ixgbe_xstats_calc_num();
3511
3512         /* HW registers are cleared on read */
3513         ixgbe_dev_xstats_get(dev, NULL, count);
3514
3515         /* Reset software totals */
3516         memset(stats, 0, sizeof(*stats));
3517         memset(macsec_stats, 0, sizeof(*macsec_stats));
3518 }
3519
3520 static void
3521 ixgbevf_update_stats(struct rte_eth_dev *dev)
3522 {
3523         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3524         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3525                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3526
3527         /* Good Rx packet, include VF loopback */
3528         UPDATE_VF_STAT(IXGBE_VFGPRC,
3529             hw_stats->last_vfgprc, hw_stats->vfgprc);
3530
3531         /* Good Rx octets, include VF loopback */
3532         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3533             hw_stats->last_vfgorc, hw_stats->vfgorc);
3534
3535         /* Good Tx packet, include VF loopback */
3536         UPDATE_VF_STAT(IXGBE_VFGPTC,
3537             hw_stats->last_vfgptc, hw_stats->vfgptc);
3538
3539         /* Good Tx octets, include VF loopback */
3540         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3541             hw_stats->last_vfgotc, hw_stats->vfgotc);
3542
3543         /* Rx Multicst Packet */
3544         UPDATE_VF_STAT(IXGBE_VFMPRC,
3545             hw_stats->last_vfmprc, hw_stats->vfmprc);
3546 }
3547
3548 static int
3549 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3550                        unsigned n)
3551 {
3552         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3553                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3554         unsigned i;
3555
3556         if (n < IXGBEVF_NB_XSTATS)
3557                 return IXGBEVF_NB_XSTATS;
3558
3559         ixgbevf_update_stats(dev);
3560
3561         if (!xstats)
3562                 return 0;
3563
3564         /* Extended stats */
3565         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3566                 xstats[i].id = i;
3567                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3568                         rte_ixgbevf_stats_strings[i].offset);
3569         }
3570
3571         return IXGBEVF_NB_XSTATS;
3572 }
3573
3574 static void
3575 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3576 {
3577         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3578                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3579
3580         ixgbevf_update_stats(dev);
3581
3582         if (stats == NULL)
3583                 return;
3584
3585         stats->ipackets = hw_stats->vfgprc;
3586         stats->ibytes = hw_stats->vfgorc;
3587         stats->opackets = hw_stats->vfgptc;
3588         stats->obytes = hw_stats->vfgotc;
3589 }
3590
3591 static void
3592 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3593 {
3594         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3595                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3596
3597         /* Sync HW register to the last stats */
3598         ixgbevf_dev_stats_get(dev, NULL);
3599
3600         /* reset HW current stats*/
3601         hw_stats->vfgprc = 0;
3602         hw_stats->vfgorc = 0;
3603         hw_stats->vfgptc = 0;
3604         hw_stats->vfgotc = 0;
3605 }
3606
3607 static int
3608 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3609 {
3610         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3611         u16 eeprom_verh, eeprom_verl;
3612         u32 etrack_id;
3613         int ret;
3614
3615         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3616         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3617
3618         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3619         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3620
3621         ret += 1; /* add the size of '\0' */
3622         if (fw_size < (u32)ret)
3623                 return ret;
3624         else
3625                 return 0;
3626 }
3627
3628 static void
3629 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3630 {
3631         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3632         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3633         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3634
3635         dev_info->pci_dev = pci_dev;
3636         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3637         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3638         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3639                 /*
3640                  * When DCB/VT is off, maximum number of queues changes,
3641                  * except for 82598EB, which remains constant.
3642                  */
3643                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3644                                 hw->mac.type != ixgbe_mac_82598EB)
3645                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3646         }
3647         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3648         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3649         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3650         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3651         dev_info->max_vfs = pci_dev->max_vfs;
3652         if (hw->mac.type == ixgbe_mac_82598EB)
3653                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3654         else
3655                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3656         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3657         dev_info->rx_offload_capa =
3658                 DEV_RX_OFFLOAD_VLAN_STRIP |
3659                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3660                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3661                 DEV_RX_OFFLOAD_TCP_CKSUM;
3662
3663         /*
3664          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3665          * mode.
3666          */
3667         if ((hw->mac.type == ixgbe_mac_82599EB ||
3668              hw->mac.type == ixgbe_mac_X540) &&
3669             !RTE_ETH_DEV_SRIOV(dev).active)
3670                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3671
3672         if (hw->mac.type == ixgbe_mac_82599EB ||
3673             hw->mac.type == ixgbe_mac_X540)
3674                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3675
3676         if (hw->mac.type == ixgbe_mac_X550 ||
3677             hw->mac.type == ixgbe_mac_X550EM_x ||
3678             hw->mac.type == ixgbe_mac_X550EM_a)
3679                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3680
3681         dev_info->tx_offload_capa =
3682                 DEV_TX_OFFLOAD_VLAN_INSERT |
3683                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3684                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3685                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3686                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3687                 DEV_TX_OFFLOAD_TCP_TSO;
3688
3689         if (hw->mac.type == ixgbe_mac_82599EB ||
3690             hw->mac.type == ixgbe_mac_X540)
3691                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3692
3693         if (hw->mac.type == ixgbe_mac_X550 ||
3694             hw->mac.type == ixgbe_mac_X550EM_x ||
3695             hw->mac.type == ixgbe_mac_X550EM_a)
3696                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3697
3698         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3699                 .rx_thresh = {
3700                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3701                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3702                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3703                 },
3704                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3705                 .rx_drop_en = 0,
3706         };
3707
3708         dev_info->default_txconf = (struct rte_eth_txconf) {
3709                 .tx_thresh = {
3710                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3711                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3712                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3713                 },
3714                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3715                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3716                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3717                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3718         };
3719
3720         dev_info->rx_desc_lim = rx_desc_lim;
3721         dev_info->tx_desc_lim = tx_desc_lim;
3722
3723         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3724         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3725         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3726
3727         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3728         if (hw->mac.type == ixgbe_mac_X540 ||
3729             hw->mac.type == ixgbe_mac_X540_vf ||
3730             hw->mac.type == ixgbe_mac_X550 ||
3731             hw->mac.type == ixgbe_mac_X550_vf) {
3732                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3733         }
3734         if (hw->mac.type == ixgbe_mac_X550) {
3735                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3736                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3737         }
3738 }
3739
3740 static const uint32_t *
3741 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3742 {
3743         static const uint32_t ptypes[] = {
3744                 /* For non-vec functions,
3745                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3746                  * for vec functions,
3747                  * refers to _recv_raw_pkts_vec().
3748                  */
3749                 RTE_PTYPE_L2_ETHER,
3750                 RTE_PTYPE_L3_IPV4,
3751                 RTE_PTYPE_L3_IPV4_EXT,
3752                 RTE_PTYPE_L3_IPV6,
3753                 RTE_PTYPE_L3_IPV6_EXT,
3754                 RTE_PTYPE_L4_SCTP,
3755                 RTE_PTYPE_L4_TCP,
3756                 RTE_PTYPE_L4_UDP,
3757                 RTE_PTYPE_TUNNEL_IP,
3758                 RTE_PTYPE_INNER_L3_IPV6,
3759                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3760                 RTE_PTYPE_INNER_L4_TCP,
3761                 RTE_PTYPE_INNER_L4_UDP,
3762                 RTE_PTYPE_UNKNOWN
3763         };
3764
3765         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3766             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3767             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3768             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3769                 return ptypes;
3770
3771 #if defined(RTE_ARCH_X86)
3772         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3773             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3774                 return ptypes;
3775 #endif
3776         return NULL;
3777 }
3778
3779 static void
3780 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3781                      struct rte_eth_dev_info *dev_info)
3782 {
3783         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785
3786         dev_info->pci_dev = pci_dev;
3787         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3788         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3789         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3790         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3791         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3792         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3793         dev_info->max_vfs = pci_dev->max_vfs;
3794         if (hw->mac.type == ixgbe_mac_82598EB)
3795                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3796         else
3797                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3798         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3799                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3800                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3801                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3802         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3803                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3804                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3805                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3806                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3807                                 DEV_TX_OFFLOAD_TCP_TSO;
3808
3809         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3810                 .rx_thresh = {
3811                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3812                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3813                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3814                 },
3815                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3816                 .rx_drop_en = 0,
3817         };
3818
3819         dev_info->default_txconf = (struct rte_eth_txconf) {
3820                 .tx_thresh = {
3821                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3822                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3823                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3824                 },
3825                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3826                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3827                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3828                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3829         };
3830
3831         dev_info->rx_desc_lim = rx_desc_lim;
3832         dev_info->tx_desc_lim = tx_desc_lim;
3833 }
3834
3835 static int
3836 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3837                    int *link_up, int wait_to_complete)
3838 {
3839         /**
3840          * for a quick link status checking, wait_to_compelet == 0,
3841          * skip PF link status checking
3842          */
3843         bool no_pflink_check = wait_to_complete == 0;
3844         struct ixgbe_mbx_info *mbx = &hw->mbx;
3845         struct ixgbe_mac_info *mac = &hw->mac;
3846         uint32_t links_reg, in_msg;
3847         int ret_val = 0;
3848
3849         /* If we were hit with a reset drop the link */
3850         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3851                 mac->get_link_status = true;
3852
3853         if (!mac->get_link_status)
3854                 goto out;
3855
3856         /* if link status is down no point in checking to see if pf is up */
3857         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3858         if (!(links_reg & IXGBE_LINKS_UP))
3859                 goto out;
3860
3861         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3862          * before the link status is correct
3863          */
3864         if (mac->type == ixgbe_mac_82599_vf) {
3865                 int i;
3866
3867                 for (i = 0; i < 5; i++) {
3868                         rte_delay_us(100);
3869                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3870
3871                         if (!(links_reg & IXGBE_LINKS_UP))
3872                                 goto out;
3873                 }
3874         }
3875
3876         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3877         case IXGBE_LINKS_SPEED_10G_82599:
3878                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3879                 if (hw->mac.type >= ixgbe_mac_X550) {
3880                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3881                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3882                 }
3883                 break;
3884         case IXGBE_LINKS_SPEED_1G_82599:
3885                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3886                 break;
3887         case IXGBE_LINKS_SPEED_100_82599:
3888                 *speed = IXGBE_LINK_SPEED_100_FULL;
3889                 if (hw->mac.type == ixgbe_mac_X550) {
3890                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3891                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3892                 }
3893                 break;
3894         case IXGBE_LINKS_SPEED_10_X550EM_A:
3895                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3896                 /* Since Reserved in older MAC's */
3897                 if (hw->mac.type >= ixgbe_mac_X550)
3898                         *speed = IXGBE_LINK_SPEED_10_FULL;
3899                 break;
3900         default:
3901                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3902         }
3903
3904         if (no_pflink_check) {
3905                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3906                         mac->get_link_status = true;
3907                 else
3908                         mac->get_link_status = false;
3909
3910                 goto out;
3911         }
3912         /* if the read failed it could just be a mailbox collision, best wait
3913          * until we are called again and don't report an error
3914          */
3915         if (mbx->ops.read(hw, &in_msg, 1, 0))
3916                 goto out;
3917
3918         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3919                 /* msg is not CTS and is NACK we must have lost CTS status */
3920                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3921                         ret_val = -1;
3922                 goto out;
3923         }
3924
3925         /* the pf is talking, if we timed out in the past we reinit */
3926         if (!mbx->timeout) {
3927                 ret_val = -1;
3928                 goto out;
3929         }
3930
3931         /* if we passed all the tests above then the link is up and we no
3932          * longer need to check for link
3933          */
3934         mac->get_link_status = false;
3935
3936 out:
3937         *link_up = !mac->get_link_status;
3938         return ret_val;
3939 }
3940
3941 /* return 0 means link status changed, -1 means not changed */
3942 static int
3943 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3944                             int wait_to_complete, int vf)
3945 {
3946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947         struct rte_eth_link link, old;
3948         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3949         struct ixgbe_interrupt *intr =
3950                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3951         int link_up;
3952         int diag;
3953         u32 speed = 0;
3954         int wait = 1;
3955         bool autoneg = false;
3956
3957         link.link_status = ETH_LINK_DOWN;
3958         link.link_speed = 0;
3959         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3960         memset(&old, 0, sizeof(old));
3961         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3962
3963         hw->mac.get_link_status = true;
3964
3965         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3966                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3967                 speed = hw->phy.autoneg_advertised;
3968                 if (!speed)
3969                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3970                 ixgbe_setup_link(hw, speed, true);
3971         }
3972
3973         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3974         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3975                 wait = 0;
3976
3977         if (vf)
3978                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3979         else
3980                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3981
3982         if (diag != 0) {
3983                 link.link_speed = ETH_SPEED_NUM_100M;
3984                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3985                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3986                 if (link.link_status == old.link_status)
3987                         return -1;
3988                 return 0;
3989         }
3990
3991         if (link_up == 0) {
3992                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3993                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3994                 if (link.link_status == old.link_status)
3995                         return -1;
3996                 return 0;
3997         }
3998         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3999         link.link_status = ETH_LINK_UP;
4000         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4001
4002         switch (link_speed) {
4003         default:
4004         case IXGBE_LINK_SPEED_UNKNOWN:
4005                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4006                 link.link_speed = ETH_SPEED_NUM_100M;
4007                 break;
4008
4009         case IXGBE_LINK_SPEED_100_FULL:
4010                 link.link_speed = ETH_SPEED_NUM_100M;
4011                 break;
4012
4013         case IXGBE_LINK_SPEED_1GB_FULL:
4014                 link.link_speed = ETH_SPEED_NUM_1G;
4015                 break;
4016
4017         case IXGBE_LINK_SPEED_2_5GB_FULL:
4018                 link.link_speed = ETH_SPEED_NUM_2_5G;
4019                 break;
4020
4021         case IXGBE_LINK_SPEED_5GB_FULL:
4022                 link.link_speed = ETH_SPEED_NUM_5G;
4023                 break;
4024
4025         case IXGBE_LINK_SPEED_10GB_FULL:
4026                 link.link_speed = ETH_SPEED_NUM_10G;
4027                 break;
4028         }
4029         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4030
4031         if (link.link_status == old.link_status)
4032                 return -1;
4033
4034         return 0;
4035 }
4036
4037 static int
4038 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4039 {
4040         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4041 }
4042
4043 static int
4044 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4045 {
4046         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4047 }
4048
4049 static void
4050 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4051 {
4052         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4053         uint32_t fctrl;
4054
4055         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4056         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4057         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4058 }
4059
4060 static void
4061 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4062 {
4063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4064         uint32_t fctrl;
4065
4066         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4067         fctrl &= (~IXGBE_FCTRL_UPE);
4068         if (dev->data->all_multicast == 1)
4069                 fctrl |= IXGBE_FCTRL_MPE;
4070         else
4071                 fctrl &= (~IXGBE_FCTRL_MPE);
4072         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4073 }
4074
4075 static void
4076 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4077 {
4078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4079         uint32_t fctrl;
4080
4081         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4082         fctrl |= IXGBE_FCTRL_MPE;
4083         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4084 }
4085
4086 static void
4087 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4088 {
4089         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4090         uint32_t fctrl;
4091
4092         if (dev->data->promiscuous == 1)
4093                 return; /* must remain in all_multicast mode */
4094
4095         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4096         fctrl &= (~IXGBE_FCTRL_MPE);
4097         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4098 }
4099
4100 /**
4101  * It clears the interrupt causes and enables the interrupt.
4102  * It will be called once only during nic initialized.
4103  *
4104  * @param dev
4105  *  Pointer to struct rte_eth_dev.
4106  * @param on
4107  *  Enable or Disable.
4108  *
4109  * @return
4110  *  - On success, zero.
4111  *  - On failure, a negative value.
4112  */
4113 static int
4114 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4115 {
4116         struct ixgbe_interrupt *intr =
4117                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4118
4119         ixgbe_dev_link_status_print(dev);
4120         if (on)
4121                 intr->mask |= IXGBE_EICR_LSC;
4122         else
4123                 intr->mask &= ~IXGBE_EICR_LSC;
4124
4125         return 0;
4126 }
4127
4128 /**
4129  * It clears the interrupt causes and enables the interrupt.
4130  * It will be called once only during nic initialized.
4131  *
4132  * @param dev
4133  *  Pointer to struct rte_eth_dev.
4134  *
4135  * @return
4136  *  - On success, zero.
4137  *  - On failure, a negative value.
4138  */
4139 static int
4140 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4141 {
4142         struct ixgbe_interrupt *intr =
4143                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4144
4145         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4146
4147         return 0;
4148 }
4149
4150 /**
4151  * It clears the interrupt causes and enables the interrupt.
4152  * It will be called once only during nic initialized.
4153  *
4154  * @param dev
4155  *  Pointer to struct rte_eth_dev.
4156  *
4157  * @return
4158  *  - On success, zero.
4159  *  - On failure, a negative value.
4160  */
4161 static int
4162 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4163 {
4164         struct ixgbe_interrupt *intr =
4165                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4166
4167         intr->mask |= IXGBE_EICR_LINKSEC;
4168
4169         return 0;
4170 }
4171
4172 /*
4173  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4174  *
4175  * @param dev
4176  *  Pointer to struct rte_eth_dev.
4177  *
4178  * @return
4179  *  - On success, zero.
4180  *  - On failure, a negative value.
4181  */
4182 static int
4183 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4184 {
4185         uint32_t eicr;
4186         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4187         struct ixgbe_interrupt *intr =
4188                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4189
4190         /* clear all cause mask */
4191         ixgbe_disable_intr(hw);
4192
4193         /* read-on-clear nic registers here */
4194         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4195         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4196
4197         intr->flags = 0;
4198
4199         /* set flag for async link update */
4200         if (eicr & IXGBE_EICR_LSC)
4201                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4202
4203         if (eicr & IXGBE_EICR_MAILBOX)
4204                 intr->flags |= IXGBE_FLAG_MAILBOX;
4205
4206         if (eicr & IXGBE_EICR_LINKSEC)
4207                 intr->flags |= IXGBE_FLAG_MACSEC;
4208
4209         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4210             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4211             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4212                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4213
4214         return 0;
4215 }
4216
4217 /**
4218  * It gets and then prints the link status.
4219  *
4220  * @param dev
4221  *  Pointer to struct rte_eth_dev.
4222  *
4223  * @return
4224  *  - On success, zero.
4225  *  - On failure, a negative value.
4226  */
4227 static void
4228 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4229 {
4230         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4231         struct rte_eth_link link;
4232
4233         memset(&link, 0, sizeof(link));
4234         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4235         if (link.link_status) {
4236                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4237                                         (int)(dev->data->port_id),
4238                                         (unsigned)link.link_speed,
4239                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4240                                         "full-duplex" : "half-duplex");
4241         } else {
4242                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4243                                 (int)(dev->data->port_id));
4244         }
4245         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4246                                 pci_dev->addr.domain,
4247                                 pci_dev->addr.bus,
4248                                 pci_dev->addr.devid,
4249                                 pci_dev->addr.function);
4250 }
4251
4252 /*
4253  * It executes link_update after knowing an interrupt occurred.
4254  *
4255  * @param dev
4256  *  Pointer to struct rte_eth_dev.
4257  *
4258  * @return
4259  *  - On success, zero.
4260  *  - On failure, a negative value.
4261  */
4262 static int
4263 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4264                            struct rte_intr_handle *intr_handle)
4265 {
4266         struct ixgbe_interrupt *intr =
4267                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4268         int64_t timeout;
4269         struct rte_eth_link link;
4270         struct ixgbe_hw *hw =
4271                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4272
4273         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4274
4275         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4276                 ixgbe_pf_mbx_process(dev);
4277                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4278         }
4279
4280         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4281                 ixgbe_handle_lasi(hw);
4282                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4283         }
4284
4285         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4286                 /* get the link status before link update, for predicting later */
4287                 memset(&link, 0, sizeof(link));
4288                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4289
4290                 ixgbe_dev_link_update(dev, 0);
4291
4292                 /* likely to up */
4293                 if (!link.link_status)
4294                         /* handle it 1 sec later, wait it being stable */
4295                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4296                 /* likely to down */
4297                 else
4298                         /* handle it 4 sec later, wait it being stable */
4299                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4300
4301                 ixgbe_dev_link_status_print(dev);
4302                 if (rte_eal_alarm_set(timeout * 1000,
4303                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4304                         PMD_DRV_LOG(ERR, "Error setting alarm");
4305                 else {
4306                         /* remember original mask */
4307                         intr->mask_original = intr->mask;
4308                         /* only disable lsc interrupt */
4309                         intr->mask &= ~IXGBE_EIMS_LSC;
4310                 }
4311         }
4312
4313         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4314         ixgbe_enable_intr(dev);
4315         rte_intr_enable(intr_handle);
4316
4317         return 0;
4318 }
4319
4320 /**
4321  * Interrupt handler which shall be registered for alarm callback for delayed
4322  * handling specific interrupt to wait for the stable nic state. As the
4323  * NIC interrupt state is not stable for ixgbe after link is just down,
4324  * it needs to wait 4 seconds to get the stable status.
4325  *
4326  * @param handle
4327  *  Pointer to interrupt handle.
4328  * @param param
4329  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4330  *
4331  * @return
4332  *  void
4333  */
4334 static void
4335 ixgbe_dev_interrupt_delayed_handler(void *param)
4336 {
4337         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4338         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4339         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4340         struct ixgbe_interrupt *intr =
4341                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4342         struct ixgbe_hw *hw =
4343                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4344         uint32_t eicr;
4345
4346         ixgbe_disable_intr(hw);
4347
4348         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4349         if (eicr & IXGBE_EICR_MAILBOX)
4350                 ixgbe_pf_mbx_process(dev);
4351
4352         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4353                 ixgbe_handle_lasi(hw);
4354                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4355         }
4356
4357         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4358                 ixgbe_dev_link_update(dev, 0);
4359                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4360                 ixgbe_dev_link_status_print(dev);
4361                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4362                                               NULL, NULL);
4363         }
4364
4365         if (intr->flags & IXGBE_FLAG_MACSEC) {
4366                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4367                                               NULL, NULL);
4368                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4369         }
4370
4371         /* restore original mask */
4372         intr->mask = intr->mask_original;
4373         intr->mask_original = 0;
4374
4375         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4376         ixgbe_enable_intr(dev);
4377         rte_intr_enable(intr_handle);
4378 }
4379
4380 /**
4381  * Interrupt handler triggered by NIC  for handling
4382  * specific interrupt.
4383  *
4384  * @param handle
4385  *  Pointer to interrupt handle.
4386  * @param param
4387  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4388  *
4389  * @return
4390  *  void
4391  */
4392 static void
4393 ixgbe_dev_interrupt_handler(void *param)
4394 {
4395         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4396
4397         ixgbe_dev_interrupt_get_status(dev);
4398         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4399 }
4400
4401 static int
4402 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4403 {
4404         struct ixgbe_hw *hw;
4405
4406         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4408 }
4409
4410 static int
4411 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4412 {
4413         struct ixgbe_hw *hw;
4414
4415         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4416         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4417 }
4418
4419 static int
4420 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4421 {
4422         struct ixgbe_hw *hw;
4423         uint32_t mflcn_reg;
4424         uint32_t fccfg_reg;
4425         int rx_pause;
4426         int tx_pause;
4427
4428         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4429
4430         fc_conf->pause_time = hw->fc.pause_time;
4431         fc_conf->high_water = hw->fc.high_water[0];
4432         fc_conf->low_water = hw->fc.low_water[0];
4433         fc_conf->send_xon = hw->fc.send_xon;
4434         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4435
4436         /*
4437          * Return rx_pause status according to actual setting of
4438          * MFLCN register.
4439          */
4440         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4441         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4442                 rx_pause = 1;
4443         else
4444                 rx_pause = 0;
4445
4446         /*
4447          * Return tx_pause status according to actual setting of
4448          * FCCFG register.
4449          */
4450         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4451         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4452                 tx_pause = 1;
4453         else
4454                 tx_pause = 0;
4455
4456         if (rx_pause && tx_pause)
4457                 fc_conf->mode = RTE_FC_FULL;
4458         else if (rx_pause)
4459                 fc_conf->mode = RTE_FC_RX_PAUSE;
4460         else if (tx_pause)
4461                 fc_conf->mode = RTE_FC_TX_PAUSE;
4462         else
4463                 fc_conf->mode = RTE_FC_NONE;
4464
4465         return 0;
4466 }
4467
4468 static int
4469 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4470 {
4471         struct ixgbe_hw *hw;
4472         int err;
4473         uint32_t rx_buf_size;
4474         uint32_t max_high_water;
4475         uint32_t mflcn;
4476         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4477                 ixgbe_fc_none,
4478                 ixgbe_fc_rx_pause,
4479                 ixgbe_fc_tx_pause,
4480                 ixgbe_fc_full
4481         };
4482
4483         PMD_INIT_FUNC_TRACE();
4484
4485         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4486         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4487         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4488
4489         /*
4490          * At least reserve one Ethernet frame for watermark
4491          * high_water/low_water in kilo bytes for ixgbe
4492          */
4493         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4494         if ((fc_conf->high_water > max_high_water) ||
4495                 (fc_conf->high_water < fc_conf->low_water)) {
4496                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4497                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4498                 return -EINVAL;
4499         }
4500
4501         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4502         hw->fc.pause_time     = fc_conf->pause_time;
4503         hw->fc.high_water[0]  = fc_conf->high_water;
4504         hw->fc.low_water[0]   = fc_conf->low_water;
4505         hw->fc.send_xon       = fc_conf->send_xon;
4506         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4507
4508         err = ixgbe_fc_enable(hw);
4509
4510         /* Not negotiated is not an error case */
4511         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4512
4513                 /* check if we want to forward MAC frames - driver doesn't have native
4514                  * capability to do that, so we'll write the registers ourselves */
4515
4516                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4517
4518                 /* set or clear MFLCN.PMCF bit depending on configuration */
4519                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4520                         mflcn |= IXGBE_MFLCN_PMCF;
4521                 else
4522                         mflcn &= ~IXGBE_MFLCN_PMCF;
4523
4524                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4525                 IXGBE_WRITE_FLUSH(hw);
4526
4527                 return 0;
4528         }
4529
4530         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4531         return -EIO;
4532 }
4533
4534 /**
4535  *  ixgbe_pfc_enable_generic - Enable flow control
4536  *  @hw: pointer to hardware structure
4537  *  @tc_num: traffic class number
4538  *  Enable flow control according to the current settings.
4539  */
4540 static int
4541 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4542 {
4543         int ret_val = 0;
4544         uint32_t mflcn_reg, fccfg_reg;
4545         uint32_t reg;
4546         uint32_t fcrtl, fcrth;
4547         uint8_t i;
4548         uint8_t nb_rx_en;
4549
4550         /* Validate the water mark configuration */
4551         if (!hw->fc.pause_time) {
4552                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4553                 goto out;
4554         }
4555
4556         /* Low water mark of zero causes XOFF floods */
4557         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4558                  /* High/Low water can not be 0 */
4559                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4560                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4561                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4562                         goto out;
4563                 }
4564
4565                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4566                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4567                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4568                         goto out;
4569                 }
4570         }
4571         /* Negotiate the fc mode to use */
4572         ixgbe_fc_autoneg(hw);
4573
4574         /* Disable any previous flow control settings */
4575         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4576         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4577
4578         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4579         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4580
4581         switch (hw->fc.current_mode) {
4582         case ixgbe_fc_none:
4583                 /*
4584                  * If the count of enabled RX Priority Flow control >1,
4585                  * and the TX pause can not be disabled
4586                  */
4587                 nb_rx_en = 0;
4588                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4589                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4590                         if (reg & IXGBE_FCRTH_FCEN)
4591                                 nb_rx_en++;
4592                 }
4593                 if (nb_rx_en > 1)
4594                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4595                 break;
4596         case ixgbe_fc_rx_pause:
4597                 /*
4598                  * Rx Flow control is enabled and Tx Flow control is
4599                  * disabled by software override. Since there really
4600                  * isn't a way to advertise that we are capable of RX
4601                  * Pause ONLY, we will advertise that we support both
4602                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4603                  * disable the adapter's ability to send PAUSE frames.
4604                  */
4605                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4606                 /*
4607                  * If the count of enabled RX Priority Flow control >1,
4608                  * and the TX pause can not be disabled
4609                  */
4610                 nb_rx_en = 0;
4611                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4612                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4613                         if (reg & IXGBE_FCRTH_FCEN)
4614                                 nb_rx_en++;
4615                 }
4616                 if (nb_rx_en > 1)
4617                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4618                 break;
4619         case ixgbe_fc_tx_pause:
4620                 /*
4621                  * Tx Flow control is enabled, and Rx Flow control is
4622                  * disabled by software override.
4623                  */
4624                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4625                 break;
4626         case ixgbe_fc_full:
4627                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4628                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4629                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4630                 break;
4631         default:
4632                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4633                 ret_val = IXGBE_ERR_CONFIG;
4634                 goto out;
4635         }
4636
4637         /* Set 802.3x based flow control settings. */
4638         mflcn_reg |= IXGBE_MFLCN_DPF;
4639         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4640         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4641
4642         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4643         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4644                 hw->fc.high_water[tc_num]) {
4645                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4646                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4647                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4648         } else {
4649                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4650                 /*
4651                  * In order to prevent Tx hangs when the internal Tx
4652                  * switch is enabled we must set the high water mark
4653                  * to the maximum FCRTH value.  This allows the Tx
4654                  * switch to function even under heavy Rx workloads.
4655                  */
4656                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4657         }
4658         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4659
4660         /* Configure pause time (2 TCs per register) */
4661         reg = hw->fc.pause_time * 0x00010001;
4662         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4663                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4664
4665         /* Configure flow control refresh threshold value */
4666         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4667
4668 out:
4669         return ret_val;
4670 }
4671
4672 static int
4673 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4674 {
4675         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4676         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4677
4678         if (hw->mac.type != ixgbe_mac_82598EB) {
4679                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4680         }
4681         return ret_val;
4682 }
4683
4684 static int
4685 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4686 {
4687         int err;
4688         uint32_t rx_buf_size;
4689         uint32_t max_high_water;
4690         uint8_t tc_num;
4691         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4692         struct ixgbe_hw *hw =
4693                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4694         struct ixgbe_dcb_config *dcb_config =
4695                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4696
4697         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4698                 ixgbe_fc_none,
4699                 ixgbe_fc_rx_pause,
4700                 ixgbe_fc_tx_pause,
4701                 ixgbe_fc_full
4702         };
4703
4704         PMD_INIT_FUNC_TRACE();
4705
4706         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4707         tc_num = map[pfc_conf->priority];
4708         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4709         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4710         /*
4711          * At least reserve one Ethernet frame for watermark
4712          * high_water/low_water in kilo bytes for ixgbe
4713          */
4714         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4715         if ((pfc_conf->fc.high_water > max_high_water) ||
4716             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4717                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4718                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4719                 return -EINVAL;
4720         }
4721
4722         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4723         hw->fc.pause_time = pfc_conf->fc.pause_time;
4724         hw->fc.send_xon = pfc_conf->fc.send_xon;
4725         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4726         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4727
4728         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4729
4730         /* Not negotiated is not an error case */
4731         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4732                 return 0;
4733
4734         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4735         return -EIO;
4736 }
4737
4738 static int
4739 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4740                           struct rte_eth_rss_reta_entry64 *reta_conf,
4741                           uint16_t reta_size)
4742 {
4743         uint16_t i, sp_reta_size;
4744         uint8_t j, mask;
4745         uint32_t reta, r;
4746         uint16_t idx, shift;
4747         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4748         uint32_t reta_reg;
4749
4750         PMD_INIT_FUNC_TRACE();
4751
4752         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4753                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4754                         "NIC.");
4755                 return -ENOTSUP;
4756         }
4757
4758         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4759         if (reta_size != sp_reta_size) {
4760                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4761                         "(%d) doesn't match the number hardware can supported "
4762                         "(%d)", reta_size, sp_reta_size);
4763                 return -EINVAL;
4764         }
4765
4766         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4767                 idx = i / RTE_RETA_GROUP_SIZE;
4768                 shift = i % RTE_RETA_GROUP_SIZE;
4769                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4770                                                 IXGBE_4_BIT_MASK);
4771                 if (!mask)
4772                         continue;
4773                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4774                 if (mask == IXGBE_4_BIT_MASK)
4775                         r = 0;
4776                 else
4777                         r = IXGBE_READ_REG(hw, reta_reg);
4778                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4779                         if (mask & (0x1 << j))
4780                                 reta |= reta_conf[idx].reta[shift + j] <<
4781                                                         (CHAR_BIT * j);
4782                         else
4783                                 reta |= r & (IXGBE_8_BIT_MASK <<
4784                                                 (CHAR_BIT * j));
4785                 }
4786                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4787         }
4788
4789         return 0;
4790 }
4791
4792 static int
4793 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4794                          struct rte_eth_rss_reta_entry64 *reta_conf,
4795                          uint16_t reta_size)
4796 {
4797         uint16_t i, sp_reta_size;
4798         uint8_t j, mask;
4799         uint32_t reta;
4800         uint16_t idx, shift;
4801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4802         uint32_t reta_reg;
4803
4804         PMD_INIT_FUNC_TRACE();
4805         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4806         if (reta_size != sp_reta_size) {
4807                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4808                         "(%d) doesn't match the number hardware can supported "
4809                         "(%d)", reta_size, sp_reta_size);
4810                 return -EINVAL;
4811         }
4812
4813         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4814                 idx = i / RTE_RETA_GROUP_SIZE;
4815                 shift = i % RTE_RETA_GROUP_SIZE;
4816                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4817                                                 IXGBE_4_BIT_MASK);
4818                 if (!mask)
4819                         continue;
4820
4821                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4822                 reta = IXGBE_READ_REG(hw, reta_reg);
4823                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4824                         if (mask & (0x1 << j))
4825                                 reta_conf[idx].reta[shift + j] =
4826                                         ((reta >> (CHAR_BIT * j)) &
4827                                                 IXGBE_8_BIT_MASK);
4828                 }
4829         }
4830
4831         return 0;
4832 }
4833
4834 static int
4835 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4836                                 uint32_t index, uint32_t pool)
4837 {
4838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839         uint32_t enable_addr = 1;
4840
4841         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4842                              pool, enable_addr);
4843 }
4844
4845 static void
4846 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4847 {
4848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4849
4850         ixgbe_clear_rar(hw, index);
4851 }
4852
4853 static void
4854 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4855 {
4856         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4857
4858         ixgbe_remove_rar(dev, 0);
4859
4860         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4861 }
4862
4863 static bool
4864 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4865 {
4866         if (strcmp(dev->device->driver->name, drv->driver.name))
4867                 return false;
4868
4869         return true;
4870 }
4871
4872 bool
4873 is_ixgbe_supported(struct rte_eth_dev *dev)
4874 {
4875         return is_device_supported(dev, &rte_ixgbe_pmd);
4876 }
4877
4878 static int
4879 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4880 {
4881         uint32_t hlreg0;
4882         uint32_t maxfrs;
4883         struct ixgbe_hw *hw;
4884         struct rte_eth_dev_info dev_info;
4885         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4886         struct rte_eth_dev_data *dev_data = dev->data;
4887
4888         ixgbe_dev_info_get(dev, &dev_info);
4889
4890         /* check that mtu is within the allowed range */
4891         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4892                 return -EINVAL;
4893
4894         /* If device is started, refuse mtu that requires the support of
4895          * scattered packets when this feature has not been enabled before.
4896          */
4897         if (dev_data->dev_started && !dev_data->scattered_rx &&
4898             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4899              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4900                 PMD_INIT_LOG(ERR, "Stop port first.");
4901                 return -EINVAL;
4902         }
4903
4904         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4905         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4906
4907         /* switch to jumbo mode if needed */
4908         if (frame_size > ETHER_MAX_LEN) {
4909                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4910                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4911         } else {
4912                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4913                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4914         }
4915         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4916
4917         /* update max frame size */
4918         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4919
4920         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4921         maxfrs &= 0x0000FFFF;
4922         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4923         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4924
4925         return 0;
4926 }
4927
4928 /*
4929  * Virtual Function operations
4930  */
4931 static void
4932 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4933 {
4934         PMD_INIT_FUNC_TRACE();
4935
4936         /* Clear interrupt mask to stop from interrupts being generated */
4937         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4938
4939         IXGBE_WRITE_FLUSH(hw);
4940 }
4941
4942 static void
4943 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4944 {
4945         PMD_INIT_FUNC_TRACE();
4946
4947         /* VF enable interrupt autoclean */
4948         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4949         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4950         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4951
4952         IXGBE_WRITE_FLUSH(hw);
4953 }
4954
4955 static int
4956 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4957 {
4958         struct rte_eth_conf *conf = &dev->data->dev_conf;
4959         struct ixgbe_adapter *adapter =
4960                         (struct ixgbe_adapter *)dev->data->dev_private;
4961
4962         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4963                      dev->data->port_id);
4964
4965         /*
4966          * VF has no ability to enable/disable HW CRC
4967          * Keep the persistent behavior the same as Host PF
4968          */
4969 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4970         if (!conf->rxmode.hw_strip_crc) {
4971                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4972                 conf->rxmode.hw_strip_crc = 1;
4973         }
4974 #else
4975         if (conf->rxmode.hw_strip_crc) {
4976                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4977                 conf->rxmode.hw_strip_crc = 0;
4978         }
4979 #endif
4980
4981         /*
4982          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4983          * allocation or vector Rx preconditions we will reset it.
4984          */
4985         adapter->rx_bulk_alloc_allowed = true;
4986         adapter->rx_vec_allowed = true;
4987
4988         return 0;
4989 }
4990
4991 static int
4992 ixgbevf_dev_start(struct rte_eth_dev *dev)
4993 {
4994         struct ixgbe_hw *hw =
4995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4996         uint32_t intr_vector = 0;
4997         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4998         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4999
5000         int err, mask = 0;
5001
5002         PMD_INIT_FUNC_TRACE();
5003
5004         hw->mac.ops.reset_hw(hw);
5005         hw->mac.get_link_status = true;
5006
5007         /* negotiate mailbox API version to use with the PF. */
5008         ixgbevf_negotiate_api(hw);
5009
5010         ixgbevf_dev_tx_init(dev);
5011
5012         /* This can fail when allocating mbufs for descriptor rings */
5013         err = ixgbevf_dev_rx_init(dev);
5014         if (err) {
5015                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5016                 ixgbe_dev_clear_queues(dev);
5017                 return err;
5018         }
5019
5020         /* Set vfta */
5021         ixgbevf_set_vfta_all(dev, 1);
5022
5023         /* Set HW strip */
5024         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5025                 ETH_VLAN_EXTEND_MASK;
5026         ixgbevf_vlan_offload_set(dev, mask);
5027
5028         ixgbevf_dev_rxtx_start(dev);
5029
5030         /* check and configure queue intr-vector mapping */
5031         if (dev->data->dev_conf.intr_conf.rxq != 0) {
5032                 intr_vector = dev->data->nb_rx_queues;
5033                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5034                         return -1;
5035         }
5036
5037         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5038                 intr_handle->intr_vec =
5039                         rte_zmalloc("intr_vec",
5040                                     dev->data->nb_rx_queues * sizeof(int), 0);
5041                 if (intr_handle->intr_vec == NULL) {
5042                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5043                                      " intr_vec", dev->data->nb_rx_queues);
5044                         return -ENOMEM;
5045                 }
5046         }
5047         ixgbevf_configure_msix(dev);
5048
5049         rte_intr_enable(intr_handle);
5050
5051         /* Re-enable interrupt for VF */
5052         ixgbevf_intr_enable(hw);
5053
5054         return 0;
5055 }
5056
5057 static void
5058 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5059 {
5060         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5061         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5062         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5063
5064         PMD_INIT_FUNC_TRACE();
5065
5066         ixgbevf_intr_disable(hw);
5067
5068         hw->adapter_stopped = 1;
5069         ixgbe_stop_adapter(hw);
5070
5071         /*
5072           * Clear what we set, but we still keep shadow_vfta to
5073           * restore after device starts
5074           */
5075         ixgbevf_set_vfta_all(dev, 0);
5076
5077         /* Clear stored conf */
5078         dev->data->scattered_rx = 0;
5079
5080         ixgbe_dev_clear_queues(dev);
5081
5082         /* Clean datapath event and queue/vec mapping */
5083         rte_intr_efd_disable(intr_handle);
5084         if (intr_handle->intr_vec != NULL) {
5085                 rte_free(intr_handle->intr_vec);
5086                 intr_handle->intr_vec = NULL;
5087         }
5088 }
5089
5090 static void
5091 ixgbevf_dev_close(struct rte_eth_dev *dev)
5092 {
5093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5094
5095         PMD_INIT_FUNC_TRACE();
5096
5097         ixgbe_reset_hw(hw);
5098
5099         ixgbevf_dev_stop(dev);
5100
5101         ixgbe_dev_free_queues(dev);
5102
5103         /**
5104          * Remove the VF MAC address ro ensure
5105          * that the VF traffic goes to the PF
5106          * after stop, close and detach of the VF
5107          **/
5108         ixgbevf_remove_mac_addr(dev, 0);
5109 }
5110
5111 /*
5112  * Reset VF device
5113  */
5114 static int
5115 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5116 {
5117         int ret;
5118
5119         ret = eth_ixgbevf_dev_uninit(dev);
5120         if (ret)
5121                 return ret;
5122
5123         ret = eth_ixgbevf_dev_init(dev);
5124
5125         return ret;
5126 }
5127
5128 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5129 {
5130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131         struct ixgbe_vfta *shadow_vfta =
5132                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5133         int i = 0, j = 0, vfta = 0, mask = 1;
5134
5135         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5136                 vfta = shadow_vfta->vfta[i];
5137                 if (vfta) {
5138                         mask = 1;
5139                         for (j = 0; j < 32; j++) {
5140                                 if (vfta & mask)
5141                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5142                                                        on, false);
5143                                 mask <<= 1;
5144                         }
5145                 }
5146         }
5147
5148 }
5149
5150 static int
5151 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5152 {
5153         struct ixgbe_hw *hw =
5154                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155         struct ixgbe_vfta *shadow_vfta =
5156                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5157         uint32_t vid_idx = 0;
5158         uint32_t vid_bit = 0;
5159         int ret = 0;
5160
5161         PMD_INIT_FUNC_TRACE();
5162
5163         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5164         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5165         if (ret) {
5166                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5167                 return ret;
5168         }
5169         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5170         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5171
5172         /* Save what we set and retore it after device reset */
5173         if (on)
5174                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5175         else
5176                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5177
5178         return 0;
5179 }
5180
5181 static void
5182 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5183 {
5184         struct ixgbe_hw *hw =
5185                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5186         uint32_t ctrl;
5187
5188         PMD_INIT_FUNC_TRACE();
5189
5190         if (queue >= hw->mac.max_rx_queues)
5191                 return;
5192
5193         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5194         if (on)
5195                 ctrl |= IXGBE_RXDCTL_VME;
5196         else
5197                 ctrl &= ~IXGBE_RXDCTL_VME;
5198         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5199
5200         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5201 }
5202
5203 static void
5204 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5205 {
5206         struct ixgbe_hw *hw =
5207                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5208         uint16_t i;
5209         int on = 0;
5210
5211         /* VF function only support hw strip feature, others are not support */
5212         if (mask & ETH_VLAN_STRIP_MASK) {
5213                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5214
5215                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5216                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5217         }
5218 }
5219
5220 int
5221 ixgbe_vt_check(struct ixgbe_hw *hw)
5222 {
5223         uint32_t reg_val;
5224
5225         /* if Virtualization Technology is enabled */
5226         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5227         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5228                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5229                 return -1;
5230         }
5231
5232         return 0;
5233 }
5234
5235 static uint32_t
5236 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5237 {
5238         uint32_t vector = 0;
5239
5240         switch (hw->mac.mc_filter_type) {
5241         case 0:   /* use bits [47:36] of the address */
5242                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5243                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5244                 break;
5245         case 1:   /* use bits [46:35] of the address */
5246                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5247                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5248                 break;
5249         case 2:   /* use bits [45:34] of the address */
5250                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5251                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5252                 break;
5253         case 3:   /* use bits [43:32] of the address */
5254                 vector = ((uc_addr->addr_bytes[4]) |
5255                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5256                 break;
5257         default:  /* Invalid mc_filter_type */
5258                 break;
5259         }
5260
5261         /* vector can only be 12-bits or boundary will be exceeded */
5262         vector &= 0xFFF;
5263         return vector;
5264 }
5265
5266 static int
5267 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5268                         uint8_t on)
5269 {
5270         uint32_t vector;
5271         uint32_t uta_idx;
5272         uint32_t reg_val;
5273         uint32_t uta_shift;
5274         uint32_t rc;
5275         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5276         const uint32_t ixgbe_uta_bit_shift = 5;
5277         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5278         const uint32_t bit1 = 0x1;
5279
5280         struct ixgbe_hw *hw =
5281                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5282         struct ixgbe_uta_info *uta_info =
5283                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5284
5285         /* The UTA table only exists on 82599 hardware and newer */
5286         if (hw->mac.type < ixgbe_mac_82599EB)
5287                 return -ENOTSUP;
5288
5289         vector = ixgbe_uta_vector(hw, mac_addr);
5290         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5291         uta_shift = vector & ixgbe_uta_bit_mask;
5292
5293         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5294         if (rc == on)
5295                 return 0;
5296
5297         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5298         if (on) {
5299                 uta_info->uta_in_use++;
5300                 reg_val |= (bit1 << uta_shift);
5301                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5302         } else {
5303                 uta_info->uta_in_use--;
5304                 reg_val &= ~(bit1 << uta_shift);
5305                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5306         }
5307
5308         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5309
5310         if (uta_info->uta_in_use > 0)
5311                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5312                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5313         else
5314                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5315
5316         return 0;
5317 }
5318
5319 static int
5320 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5321 {
5322         int i;
5323         struct ixgbe_hw *hw =
5324                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5325         struct ixgbe_uta_info *uta_info =
5326                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5327
5328         /* The UTA table only exists on 82599 hardware and newer */
5329         if (hw->mac.type < ixgbe_mac_82599EB)
5330                 return -ENOTSUP;
5331
5332         if (on) {
5333                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5334                         uta_info->uta_shadow[i] = ~0;
5335                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5336                 }
5337         } else {
5338                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5339                         uta_info->uta_shadow[i] = 0;
5340                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5341                 }
5342         }
5343         return 0;
5344
5345 }
5346
5347 uint32_t
5348 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5349 {
5350         uint32_t new_val = orig_val;
5351
5352         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5353                 new_val |= IXGBE_VMOLR_AUPE;
5354         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5355                 new_val |= IXGBE_VMOLR_ROMPE;
5356         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5357                 new_val |= IXGBE_VMOLR_ROPE;
5358         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5359                 new_val |= IXGBE_VMOLR_BAM;
5360         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5361                 new_val |= IXGBE_VMOLR_MPE;
5362
5363         return new_val;
5364 }
5365
5366 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5367 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5368 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5369 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5370 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5371         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5372         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5373
5374 static int
5375 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5376                       struct rte_eth_mirror_conf *mirror_conf,
5377                       uint8_t rule_id, uint8_t on)
5378 {
5379         uint32_t mr_ctl, vlvf;
5380         uint32_t mp_lsb = 0;
5381         uint32_t mv_msb = 0;
5382         uint32_t mv_lsb = 0;
5383         uint32_t mp_msb = 0;
5384         uint8_t i = 0;
5385         int reg_index = 0;
5386         uint64_t vlan_mask = 0;
5387
5388         const uint8_t pool_mask_offset = 32;
5389         const uint8_t vlan_mask_offset = 32;
5390         const uint8_t dst_pool_offset = 8;
5391         const uint8_t rule_mr_offset  = 4;
5392         const uint8_t mirror_rule_mask = 0x0F;
5393
5394         struct ixgbe_mirror_info *mr_info =
5395                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5396         struct ixgbe_hw *hw =
5397                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5398         uint8_t mirror_type = 0;
5399
5400         if (ixgbe_vt_check(hw) < 0)
5401                 return -ENOTSUP;
5402
5403         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5404                 return -EINVAL;
5405
5406         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5407                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5408                             mirror_conf->rule_type);
5409                 return -EINVAL;
5410         }
5411
5412         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5413                 mirror_type |= IXGBE_MRCTL_VLME;
5414                 /* Check if vlan id is valid and find conresponding VLAN ID
5415                  * index in VLVF
5416                  */
5417                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5418                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5419                                 /* search vlan id related pool vlan filter
5420                                  * index
5421                                  */
5422                                 reg_index = ixgbe_find_vlvf_slot(
5423                                                 hw,
5424                                                 mirror_conf->vlan.vlan_id[i],
5425                                                 false);
5426                                 if (reg_index < 0)
5427                                         return -EINVAL;
5428                                 vlvf = IXGBE_READ_REG(hw,
5429                                                       IXGBE_VLVF(reg_index));
5430                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5431                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5432                                       mirror_conf->vlan.vlan_id[i]))
5433                                         vlan_mask |= (1ULL << reg_index);
5434                                 else
5435                                         return -EINVAL;
5436                         }
5437                 }
5438
5439                 if (on) {
5440                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5441                         mv_msb = vlan_mask >> vlan_mask_offset;
5442
5443                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5444                                                 mirror_conf->vlan.vlan_mask;
5445                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5446                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5447                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5448                                                 mirror_conf->vlan.vlan_id[i];
5449                         }
5450                 } else {
5451                         mv_lsb = 0;
5452                         mv_msb = 0;
5453                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5454                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5455                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5456                 }
5457         }
5458
5459         /**
5460          * if enable pool mirror, write related pool mask register,if disable
5461          * pool mirror, clear PFMRVM register
5462          */
5463         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5464                 mirror_type |= IXGBE_MRCTL_VPME;
5465                 if (on) {
5466                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5467                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5468                         mr_info->mr_conf[rule_id].pool_mask =
5469                                         mirror_conf->pool_mask;
5470
5471                 } else {
5472                         mp_lsb = 0;
5473                         mp_msb = 0;
5474                         mr_info->mr_conf[rule_id].pool_mask = 0;
5475                 }
5476         }
5477         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5478                 mirror_type |= IXGBE_MRCTL_UPME;
5479         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5480                 mirror_type |= IXGBE_MRCTL_DPME;
5481
5482         /* read  mirror control register and recalculate it */
5483         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5484
5485         if (on) {
5486                 mr_ctl |= mirror_type;
5487                 mr_ctl &= mirror_rule_mask;
5488                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5489         } else {
5490                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5491         }
5492
5493         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5494         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5495
5496         /* write mirrror control  register */
5497         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5498
5499         /* write pool mirrror control  register */
5500         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5501                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5502                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5503                                 mp_msb);
5504         }
5505         /* write VLAN mirrror control  register */
5506         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5507                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5508                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5509                                 mv_msb);
5510         }
5511
5512         return 0;
5513 }
5514
5515 static int
5516 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5517 {
5518         int mr_ctl = 0;
5519         uint32_t lsb_val = 0;
5520         uint32_t msb_val = 0;
5521         const uint8_t rule_mr_offset = 4;
5522
5523         struct ixgbe_hw *hw =
5524                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5525         struct ixgbe_mirror_info *mr_info =
5526                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5527
5528         if (ixgbe_vt_check(hw) < 0)
5529                 return -ENOTSUP;
5530
5531         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5532                 return -EINVAL;
5533
5534         memset(&mr_info->mr_conf[rule_id], 0,
5535                sizeof(struct rte_eth_mirror_conf));
5536
5537         /* clear PFVMCTL register */
5538         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5539
5540         /* clear pool mask register */
5541         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5542         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5543
5544         /* clear vlan mask register */
5545         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5546         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5547
5548         return 0;
5549 }
5550
5551 static int
5552 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5553 {
5554         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5555         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5556         uint32_t mask;
5557         struct ixgbe_hw *hw =
5558                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5559
5560         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5561         mask |= (1 << IXGBE_MISC_VEC_ID);
5562         RTE_SET_USED(queue_id);
5563         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5564
5565         rte_intr_enable(intr_handle);
5566
5567         return 0;
5568 }
5569
5570 static int
5571 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5572 {
5573         uint32_t mask;
5574         struct ixgbe_hw *hw =
5575                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5576
5577         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5578         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5579         RTE_SET_USED(queue_id);
5580         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5581
5582         return 0;
5583 }
5584
5585 static int
5586 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5587 {
5588         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5589         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5590         uint32_t mask;
5591         struct ixgbe_hw *hw =
5592                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5593         struct ixgbe_interrupt *intr =
5594                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5595
5596         if (queue_id < 16) {
5597                 ixgbe_disable_intr(hw);
5598                 intr->mask |= (1 << queue_id);
5599                 ixgbe_enable_intr(dev);
5600         } else if (queue_id < 32) {
5601                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5602                 mask &= (1 << queue_id);
5603                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5604         } else if (queue_id < 64) {
5605                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5606                 mask &= (1 << (queue_id - 32));
5607                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5608         }
5609         rte_intr_enable(intr_handle);
5610
5611         return 0;
5612 }
5613
5614 static int
5615 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5616 {
5617         uint32_t mask;
5618         struct ixgbe_hw *hw =
5619                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5620         struct ixgbe_interrupt *intr =
5621                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5622
5623         if (queue_id < 16) {
5624                 ixgbe_disable_intr(hw);
5625                 intr->mask &= ~(1 << queue_id);
5626                 ixgbe_enable_intr(dev);
5627         } else if (queue_id < 32) {
5628                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5629                 mask &= ~(1 << queue_id);
5630                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5631         } else if (queue_id < 64) {
5632                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5633                 mask &= ~(1 << (queue_id - 32));
5634                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5635         }
5636
5637         return 0;
5638 }
5639
5640 static void
5641 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5642                      uint8_t queue, uint8_t msix_vector)
5643 {
5644         uint32_t tmp, idx;
5645
5646         if (direction == -1) {
5647                 /* other causes */
5648                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5649                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5650                 tmp &= ~0xFF;
5651                 tmp |= msix_vector;
5652                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5653         } else {
5654                 /* rx or tx cause */
5655                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5656                 idx = ((16 * (queue & 1)) + (8 * direction));
5657                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5658                 tmp &= ~(0xFF << idx);
5659                 tmp |= (msix_vector << idx);
5660                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5661         }
5662 }
5663
5664 /**
5665  * set the IVAR registers, mapping interrupt causes to vectors
5666  * @param hw
5667  *  pointer to ixgbe_hw struct
5668  * @direction
5669  *  0 for Rx, 1 for Tx, -1 for other causes
5670  * @queue
5671  *  queue to map the corresponding interrupt to
5672  * @msix_vector
5673  *  the vector to map to the corresponding queue
5674  */
5675 static void
5676 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5677                    uint8_t queue, uint8_t msix_vector)
5678 {
5679         uint32_t tmp, idx;
5680
5681         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5682         if (hw->mac.type == ixgbe_mac_82598EB) {
5683                 if (direction == -1)
5684                         direction = 0;
5685                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5686                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5687                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5688                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5689                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5690         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5691                         (hw->mac.type == ixgbe_mac_X540) ||
5692                         (hw->mac.type == ixgbe_mac_X550)) {
5693                 if (direction == -1) {
5694                         /* other causes */
5695                         idx = ((queue & 1) * 8);
5696                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5697                         tmp &= ~(0xFF << idx);
5698                         tmp |= (msix_vector << idx);
5699                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5700                 } else {
5701                         /* rx or tx causes */
5702                         idx = ((16 * (queue & 1)) + (8 * direction));
5703                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5704                         tmp &= ~(0xFF << idx);
5705                         tmp |= (msix_vector << idx);
5706                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5707                 }
5708         }
5709 }
5710
5711 static void
5712 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5713 {
5714         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5715         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5716         struct ixgbe_hw *hw =
5717                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5718         uint32_t q_idx;
5719         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5720
5721         /* Configure VF other cause ivar */
5722         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5723
5724         /* won't configure msix register if no mapping is done
5725          * between intr vector and event fd.
5726          */
5727         if (!rte_intr_dp_is_en(intr_handle))
5728                 return;
5729
5730         /* Configure all RX queues of VF */
5731         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5732                 /* Force all queue use vector 0,
5733                  * as IXGBE_VF_MAXMSIVECOTR = 1
5734                  */
5735                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5736                 intr_handle->intr_vec[q_idx] = vector_idx;
5737         }
5738 }
5739
5740 /**
5741  * Sets up the hardware to properly generate MSI-X interrupts
5742  * @hw
5743  *  board private structure
5744  */
5745 static void
5746 ixgbe_configure_msix(struct rte_eth_dev *dev)
5747 {
5748         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5749         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5750         struct ixgbe_hw *hw =
5751                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5752         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5753         uint32_t vec = IXGBE_MISC_VEC_ID;
5754         uint32_t mask;
5755         uint32_t gpie;
5756
5757         /* won't configure msix register if no mapping is done
5758          * between intr vector and event fd
5759          */
5760         if (!rte_intr_dp_is_en(intr_handle))
5761                 return;
5762
5763         if (rte_intr_allow_others(intr_handle))
5764                 vec = base = IXGBE_RX_VEC_START;
5765
5766         /* setup GPIE for MSI-x mode */
5767         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5768         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5769                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5770         /* auto clearing and auto setting corresponding bits in EIMS
5771          * when MSI-X interrupt is triggered
5772          */
5773         if (hw->mac.type == ixgbe_mac_82598EB) {
5774                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5775         } else {
5776                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5777                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5778         }
5779         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5780
5781         /* Populate the IVAR table and set the ITR values to the
5782          * corresponding register.
5783          */
5784         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5785              queue_id++) {
5786                 /* by default, 1:1 mapping */
5787                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5788                 intr_handle->intr_vec[queue_id] = vec;
5789                 if (vec < base + intr_handle->nb_efd - 1)
5790                         vec++;
5791         }
5792
5793         switch (hw->mac.type) {
5794         case ixgbe_mac_82598EB:
5795                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5796                                    IXGBE_MISC_VEC_ID);
5797                 break;
5798         case ixgbe_mac_82599EB:
5799         case ixgbe_mac_X540:
5800         case ixgbe_mac_X550:
5801                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5802                 break;
5803         default:
5804                 break;
5805         }
5806         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5807                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5808
5809         /* set up to autoclear timer, and the vectors */
5810         mask = IXGBE_EIMS_ENABLE_MASK;
5811         mask &= ~(IXGBE_EIMS_OTHER |
5812                   IXGBE_EIMS_MAILBOX |
5813                   IXGBE_EIMS_LSC);
5814
5815         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5816 }
5817
5818 int
5819 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5820                            uint16_t queue_idx, uint16_t tx_rate)
5821 {
5822         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5823         uint32_t rf_dec, rf_int;
5824         uint32_t bcnrc_val;
5825         uint16_t link_speed = dev->data->dev_link.link_speed;
5826
5827         if (queue_idx >= hw->mac.max_tx_queues)
5828                 return -EINVAL;
5829
5830         if (tx_rate != 0) {
5831                 /* Calculate the rate factor values to set */
5832                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5833                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5834                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5835
5836                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5837                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5838                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5839                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5840         } else {
5841                 bcnrc_val = 0;
5842         }
5843
5844         /*
5845          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5846          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5847          * set as 0x4.
5848          */
5849         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5850                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5851                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5852                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5853                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5854         else
5855                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5856                         IXGBE_MMW_SIZE_DEFAULT);
5857
5858         /* Set RTTBCNRC of queue X */
5859         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5860         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5861         IXGBE_WRITE_FLUSH(hw);
5862
5863         return 0;
5864 }
5865
5866 static int
5867 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5868                      __attribute__((unused)) uint32_t index,
5869                      __attribute__((unused)) uint32_t pool)
5870 {
5871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5872         int diag;
5873
5874         /*
5875          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5876          * operation. Trap this case to avoid exhausting the [very limited]
5877          * set of PF resources used to store VF MAC addresses.
5878          */
5879         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5880                 return -1;
5881         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5882         if (diag != 0)
5883                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5884                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5885                             mac_addr->addr_bytes[0],
5886                             mac_addr->addr_bytes[1],
5887                             mac_addr->addr_bytes[2],
5888                             mac_addr->addr_bytes[3],
5889                             mac_addr->addr_bytes[4],
5890                             mac_addr->addr_bytes[5],
5891                             diag);
5892         return diag;
5893 }
5894
5895 static void
5896 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5897 {
5898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5899         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5900         struct ether_addr *mac_addr;
5901         uint32_t i;
5902         int diag;
5903
5904         /*
5905          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5906          * not support the deletion of a given MAC address.
5907          * Instead, it imposes to delete all MAC addresses, then to add again
5908          * all MAC addresses with the exception of the one to be deleted.
5909          */
5910         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5911
5912         /*
5913          * Add again all MAC addresses, with the exception of the deleted one
5914          * and of the permanent MAC address.
5915          */
5916         for (i = 0, mac_addr = dev->data->mac_addrs;
5917              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5918                 /* Skip the deleted MAC address */
5919                 if (i == index)
5920                         continue;
5921                 /* Skip NULL MAC addresses */
5922                 if (is_zero_ether_addr(mac_addr))
5923                         continue;
5924                 /* Skip the permanent MAC address */
5925                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5926                         continue;
5927                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5928                 if (diag != 0)
5929                         PMD_DRV_LOG(ERR,
5930                                     "Adding again MAC address "
5931                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5932                                     "diag=%d",
5933                                     mac_addr->addr_bytes[0],
5934                                     mac_addr->addr_bytes[1],
5935                                     mac_addr->addr_bytes[2],
5936                                     mac_addr->addr_bytes[3],
5937                                     mac_addr->addr_bytes[4],
5938                                     mac_addr->addr_bytes[5],
5939                                     diag);
5940         }
5941 }
5942
5943 static void
5944 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5945 {
5946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5947
5948         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5949 }
5950
5951 int
5952 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5953                         struct rte_eth_syn_filter *filter,
5954                         bool add)
5955 {
5956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5957         struct ixgbe_filter_info *filter_info =
5958                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5959         uint32_t syn_info;
5960         uint32_t synqf;
5961
5962         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5963                 return -EINVAL;
5964
5965         syn_info = filter_info->syn_info;
5966
5967         if (add) {
5968                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5969                         return -EINVAL;
5970                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5971                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5972
5973                 if (filter->hig_pri)
5974                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5975                 else
5976                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5977         } else {
5978                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5979                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5980                         return -ENOENT;
5981                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5982         }
5983
5984         filter_info->syn_info = synqf;
5985         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5986         IXGBE_WRITE_FLUSH(hw);
5987         return 0;
5988 }
5989
5990 static int
5991 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5992                         struct rte_eth_syn_filter *filter)
5993 {
5994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5995         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5996
5997         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5998                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5999                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6000                 return 0;
6001         }
6002         return -ENOENT;
6003 }
6004
6005 static int
6006 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6007                         enum rte_filter_op filter_op,
6008                         void *arg)
6009 {
6010         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6011         int ret;
6012
6013         MAC_TYPE_FILTER_SUP(hw->mac.type);
6014
6015         if (filter_op == RTE_ETH_FILTER_NOP)
6016                 return 0;
6017
6018         if (arg == NULL) {
6019                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6020                             filter_op);
6021                 return -EINVAL;
6022         }
6023
6024         switch (filter_op) {
6025         case RTE_ETH_FILTER_ADD:
6026                 ret = ixgbe_syn_filter_set(dev,
6027                                 (struct rte_eth_syn_filter *)arg,
6028                                 TRUE);
6029                 break;
6030         case RTE_ETH_FILTER_DELETE:
6031                 ret = ixgbe_syn_filter_set(dev,
6032                                 (struct rte_eth_syn_filter *)arg,
6033                                 FALSE);
6034                 break;
6035         case RTE_ETH_FILTER_GET:
6036                 ret = ixgbe_syn_filter_get(dev,
6037                                 (struct rte_eth_syn_filter *)arg);
6038                 break;
6039         default:
6040                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6041                 ret = -EINVAL;
6042                 break;
6043         }
6044
6045         return ret;
6046 }
6047
6048
6049 static inline enum ixgbe_5tuple_protocol
6050 convert_protocol_type(uint8_t protocol_value)
6051 {
6052         if (protocol_value == IPPROTO_TCP)
6053                 return IXGBE_FILTER_PROTOCOL_TCP;
6054         else if (protocol_value == IPPROTO_UDP)
6055                 return IXGBE_FILTER_PROTOCOL_UDP;
6056         else if (protocol_value == IPPROTO_SCTP)
6057                 return IXGBE_FILTER_PROTOCOL_SCTP;
6058         else
6059                 return IXGBE_FILTER_PROTOCOL_NONE;
6060 }
6061
6062 /* inject a 5-tuple filter to HW */
6063 static inline void
6064 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6065                            struct ixgbe_5tuple_filter *filter)
6066 {
6067         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6068         int i;
6069         uint32_t ftqf, sdpqf;
6070         uint32_t l34timir = 0;
6071         uint8_t mask = 0xff;
6072
6073         i = filter->index;
6074
6075         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6076                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6077         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6078
6079         ftqf = (uint32_t)(filter->filter_info.proto &
6080                 IXGBE_FTQF_PROTOCOL_MASK);
6081         ftqf |= (uint32_t)((filter->filter_info.priority &
6082                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6083         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6084                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6085         if (filter->filter_info.dst_ip_mask == 0)
6086                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6087         if (filter->filter_info.src_port_mask == 0)
6088                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6089         if (filter->filter_info.dst_port_mask == 0)
6090                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6091         if (filter->filter_info.proto_mask == 0)
6092                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6093         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6094         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6095         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6096
6097         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6098         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6099         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6100         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6101
6102         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6103         l34timir |= (uint32_t)(filter->queue <<
6104                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6105         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6106 }
6107
6108 /*
6109  * add a 5tuple filter
6110  *
6111  * @param
6112  * dev: Pointer to struct rte_eth_dev.
6113  * index: the index the filter allocates.
6114  * filter: ponter to the filter that will be added.
6115  * rx_queue: the queue id the filter assigned to.
6116  *
6117  * @return
6118  *    - On success, zero.
6119  *    - On failure, a negative value.
6120  */
6121 static int
6122 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6123                         struct ixgbe_5tuple_filter *filter)
6124 {
6125         struct ixgbe_filter_info *filter_info =
6126                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6127         int i, idx, shift;
6128
6129         /*
6130          * look for an unused 5tuple filter index,
6131          * and insert the filter to list.
6132          */
6133         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6134                 idx = i / (sizeof(uint32_t) * NBBY);
6135                 shift = i % (sizeof(uint32_t) * NBBY);
6136                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6137                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6138                         filter->index = i;
6139                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6140                                           filter,
6141                                           entries);
6142                         break;
6143                 }
6144         }
6145         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6146                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6147                 return -ENOSYS;
6148         }
6149
6150         ixgbe_inject_5tuple_filter(dev, filter);
6151
6152         return 0;
6153 }
6154
6155 /*
6156  * remove a 5tuple filter
6157  *
6158  * @param
6159  * dev: Pointer to struct rte_eth_dev.
6160  * filter: the pointer of the filter will be removed.
6161  */
6162 static void
6163 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6164                         struct ixgbe_5tuple_filter *filter)
6165 {
6166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6167         struct ixgbe_filter_info *filter_info =
6168                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6169         uint16_t index = filter->index;
6170
6171         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6172                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6173         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6174         rte_free(filter);
6175
6176         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6177         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6178         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6179         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6180         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6181 }
6182
6183 static int
6184 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6185 {
6186         struct ixgbe_hw *hw;
6187         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6188         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6189
6190         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6191
6192         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6193                 return -EINVAL;
6194
6195         /* refuse mtu that requires the support of scattered packets when this
6196          * feature has not been enabled before.
6197          */
6198         if (!rx_conf->enable_scatter &&
6199             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6200              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6201                 return -EINVAL;
6202
6203         /*
6204          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6205          * request of the version 2.0 of the mailbox API.
6206          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6207          * of the mailbox API.
6208          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6209          * prior to 3.11.33 which contains the following change:
6210          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6211          */
6212         ixgbevf_rlpml_set_vf(hw, max_frame);
6213
6214         /* update max frame size */
6215         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6216         return 0;
6217 }
6218
6219 static inline struct ixgbe_5tuple_filter *
6220 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6221                         struct ixgbe_5tuple_filter_info *key)
6222 {
6223         struct ixgbe_5tuple_filter *it;
6224
6225         TAILQ_FOREACH(it, filter_list, entries) {
6226                 if (memcmp(key, &it->filter_info,
6227                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6228                         return it;
6229                 }
6230         }
6231         return NULL;
6232 }
6233
6234 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6235 static inline int
6236 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6237                         struct ixgbe_5tuple_filter_info *filter_info)
6238 {
6239         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6240                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6241                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6242                 return -EINVAL;
6243
6244         switch (filter->dst_ip_mask) {
6245         case UINT32_MAX:
6246                 filter_info->dst_ip_mask = 0;
6247                 filter_info->dst_ip = filter->dst_ip;
6248                 break;
6249         case 0:
6250                 filter_info->dst_ip_mask = 1;
6251                 break;
6252         default:
6253                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6254                 return -EINVAL;
6255         }
6256
6257         switch (filter->src_ip_mask) {
6258         case UINT32_MAX:
6259                 filter_info->src_ip_mask = 0;
6260                 filter_info->src_ip = filter->src_ip;
6261                 break;
6262         case 0:
6263                 filter_info->src_ip_mask = 1;
6264                 break;
6265         default:
6266                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6267                 return -EINVAL;
6268         }
6269
6270         switch (filter->dst_port_mask) {
6271         case UINT16_MAX:
6272                 filter_info->dst_port_mask = 0;
6273                 filter_info->dst_port = filter->dst_port;
6274                 break;
6275         case 0:
6276                 filter_info->dst_port_mask = 1;
6277                 break;
6278         default:
6279                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6280                 return -EINVAL;
6281         }
6282
6283         switch (filter->src_port_mask) {
6284         case UINT16_MAX:
6285                 filter_info->src_port_mask = 0;
6286                 filter_info->src_port = filter->src_port;
6287                 break;
6288         case 0:
6289                 filter_info->src_port_mask = 1;
6290                 break;
6291         default:
6292                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6293                 return -EINVAL;
6294         }
6295
6296         switch (filter->proto_mask) {
6297         case UINT8_MAX:
6298                 filter_info->proto_mask = 0;
6299                 filter_info->proto =
6300                         convert_protocol_type(filter->proto);
6301                 break;
6302         case 0:
6303                 filter_info->proto_mask = 1;
6304                 break;
6305         default:
6306                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6307                 return -EINVAL;
6308         }
6309
6310         filter_info->priority = (uint8_t)filter->priority;
6311         return 0;
6312 }
6313
6314 /*
6315  * add or delete a ntuple filter
6316  *
6317  * @param
6318  * dev: Pointer to struct rte_eth_dev.
6319  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6320  * add: if true, add filter, if false, remove filter
6321  *
6322  * @return
6323  *    - On success, zero.
6324  *    - On failure, a negative value.
6325  */
6326 int
6327 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6328                         struct rte_eth_ntuple_filter *ntuple_filter,
6329                         bool add)
6330 {
6331         struct ixgbe_filter_info *filter_info =
6332                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6333         struct ixgbe_5tuple_filter_info filter_5tuple;
6334         struct ixgbe_5tuple_filter *filter;
6335         int ret;
6336
6337         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6338                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6339                 return -EINVAL;
6340         }
6341
6342         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6343         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6344         if (ret < 0)
6345                 return ret;
6346
6347         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6348                                          &filter_5tuple);
6349         if (filter != NULL && add) {
6350                 PMD_DRV_LOG(ERR, "filter exists.");
6351                 return -EEXIST;
6352         }
6353         if (filter == NULL && !add) {
6354                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6355                 return -ENOENT;
6356         }
6357
6358         if (add) {
6359                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6360                                 sizeof(struct ixgbe_5tuple_filter), 0);
6361                 if (filter == NULL)
6362                         return -ENOMEM;
6363                 rte_memcpy(&filter->filter_info,
6364                                  &filter_5tuple,
6365                                  sizeof(struct ixgbe_5tuple_filter_info));
6366                 filter->queue = ntuple_filter->queue;
6367                 ret = ixgbe_add_5tuple_filter(dev, filter);
6368                 if (ret < 0) {
6369                         rte_free(filter);
6370                         return ret;
6371                 }
6372         } else
6373                 ixgbe_remove_5tuple_filter(dev, filter);
6374
6375         return 0;
6376 }
6377
6378 /*
6379  * get a ntuple filter
6380  *
6381  * @param
6382  * dev: Pointer to struct rte_eth_dev.
6383  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6384  *
6385  * @return
6386  *    - On success, zero.
6387  *    - On failure, a negative value.
6388  */
6389 static int
6390 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6391                         struct rte_eth_ntuple_filter *ntuple_filter)
6392 {
6393         struct ixgbe_filter_info *filter_info =
6394                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6395         struct ixgbe_5tuple_filter_info filter_5tuple;
6396         struct ixgbe_5tuple_filter *filter;
6397         int ret;
6398
6399         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6400                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6401                 return -EINVAL;
6402         }
6403
6404         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6405         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6406         if (ret < 0)
6407                 return ret;
6408
6409         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6410                                          &filter_5tuple);
6411         if (filter == NULL) {
6412                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6413                 return -ENOENT;
6414         }
6415         ntuple_filter->queue = filter->queue;
6416         return 0;
6417 }
6418
6419 /*
6420  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6421  * @dev: pointer to rte_eth_dev structure
6422  * @filter_op:operation will be taken.
6423  * @arg: a pointer to specific structure corresponding to the filter_op
6424  *
6425  * @return
6426  *    - On success, zero.
6427  *    - On failure, a negative value.
6428  */
6429 static int
6430 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6431                                 enum rte_filter_op filter_op,
6432                                 void *arg)
6433 {
6434         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6435         int ret;
6436
6437         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6438
6439         if (filter_op == RTE_ETH_FILTER_NOP)
6440                 return 0;
6441
6442         if (arg == NULL) {
6443                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6444                             filter_op);
6445                 return -EINVAL;
6446         }
6447
6448         switch (filter_op) {
6449         case RTE_ETH_FILTER_ADD:
6450                 ret = ixgbe_add_del_ntuple_filter(dev,
6451                         (struct rte_eth_ntuple_filter *)arg,
6452                         TRUE);
6453                 break;
6454         case RTE_ETH_FILTER_DELETE:
6455                 ret = ixgbe_add_del_ntuple_filter(dev,
6456                         (struct rte_eth_ntuple_filter *)arg,
6457                         FALSE);
6458                 break;
6459         case RTE_ETH_FILTER_GET:
6460                 ret = ixgbe_get_ntuple_filter(dev,
6461                         (struct rte_eth_ntuple_filter *)arg);
6462                 break;
6463         default:
6464                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6465                 ret = -EINVAL;
6466                 break;
6467         }
6468         return ret;
6469 }
6470
6471 int
6472 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6473                         struct rte_eth_ethertype_filter *filter,
6474                         bool add)
6475 {
6476         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6477         struct ixgbe_filter_info *filter_info =
6478                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6479         uint32_t etqf = 0;
6480         uint32_t etqs = 0;
6481         int ret;
6482         struct ixgbe_ethertype_filter ethertype_filter;
6483
6484         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6485                 return -EINVAL;
6486
6487         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6488                 filter->ether_type == ETHER_TYPE_IPv6) {
6489                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6490                         " ethertype filter.", filter->ether_type);
6491                 return -EINVAL;
6492         }
6493
6494         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6495                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6496                 return -EINVAL;
6497         }
6498         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6499                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6500                 return -EINVAL;
6501         }
6502
6503         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6504         if (ret >= 0 && add) {
6505                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6506                             filter->ether_type);
6507                 return -EEXIST;
6508         }
6509         if (ret < 0 && !add) {
6510                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6511                             filter->ether_type);
6512                 return -ENOENT;
6513         }
6514
6515         if (add) {
6516                 etqf = IXGBE_ETQF_FILTER_EN;
6517                 etqf |= (uint32_t)filter->ether_type;
6518                 etqs |= (uint32_t)((filter->queue <<
6519                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6520                                     IXGBE_ETQS_RX_QUEUE);
6521                 etqs |= IXGBE_ETQS_QUEUE_EN;
6522
6523                 ethertype_filter.ethertype = filter->ether_type;
6524                 ethertype_filter.etqf = etqf;
6525                 ethertype_filter.etqs = etqs;
6526                 ethertype_filter.conf = FALSE;
6527                 ret = ixgbe_ethertype_filter_insert(filter_info,
6528                                                     &ethertype_filter);
6529                 if (ret < 0) {
6530                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6531                         return -ENOSPC;
6532                 }
6533         } else {
6534                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6535                 if (ret < 0)
6536                         return -ENOSYS;
6537         }
6538         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6539         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6540         IXGBE_WRITE_FLUSH(hw);
6541
6542         return 0;
6543 }
6544
6545 static int
6546 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6547                         struct rte_eth_ethertype_filter *filter)
6548 {
6549         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6550         struct ixgbe_filter_info *filter_info =
6551                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6552         uint32_t etqf, etqs;
6553         int ret;
6554
6555         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6556         if (ret < 0) {
6557                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6558                             filter->ether_type);
6559                 return -ENOENT;
6560         }
6561
6562         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6563         if (etqf & IXGBE_ETQF_FILTER_EN) {
6564                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6565                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6566                 filter->flags = 0;
6567                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6568                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6569                 return 0;
6570         }
6571         return -ENOENT;
6572 }
6573
6574 /*
6575  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6576  * @dev: pointer to rte_eth_dev structure
6577  * @filter_op:operation will be taken.
6578  * @arg: a pointer to specific structure corresponding to the filter_op
6579  */
6580 static int
6581 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6582                                 enum rte_filter_op filter_op,
6583                                 void *arg)
6584 {
6585         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6586         int ret;
6587
6588         MAC_TYPE_FILTER_SUP(hw->mac.type);
6589
6590         if (filter_op == RTE_ETH_FILTER_NOP)
6591                 return 0;
6592
6593         if (arg == NULL) {
6594                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6595                             filter_op);
6596                 return -EINVAL;
6597         }
6598
6599         switch (filter_op) {
6600         case RTE_ETH_FILTER_ADD:
6601                 ret = ixgbe_add_del_ethertype_filter(dev,
6602                         (struct rte_eth_ethertype_filter *)arg,
6603                         TRUE);
6604                 break;
6605         case RTE_ETH_FILTER_DELETE:
6606                 ret = ixgbe_add_del_ethertype_filter(dev,
6607                         (struct rte_eth_ethertype_filter *)arg,
6608                         FALSE);
6609                 break;
6610         case RTE_ETH_FILTER_GET:
6611                 ret = ixgbe_get_ethertype_filter(dev,
6612                         (struct rte_eth_ethertype_filter *)arg);
6613                 break;
6614         default:
6615                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6616                 ret = -EINVAL;
6617                 break;
6618         }
6619         return ret;
6620 }
6621
6622 static int
6623 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6624                      enum rte_filter_type filter_type,
6625                      enum rte_filter_op filter_op,
6626                      void *arg)
6627 {
6628         int ret = 0;
6629
6630         switch (filter_type) {
6631         case RTE_ETH_FILTER_NTUPLE:
6632                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6633                 break;
6634         case RTE_ETH_FILTER_ETHERTYPE:
6635                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6636                 break;
6637         case RTE_ETH_FILTER_SYN:
6638                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6639                 break;
6640         case RTE_ETH_FILTER_FDIR:
6641                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6642                 break;
6643         case RTE_ETH_FILTER_L2_TUNNEL:
6644                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6645                 break;
6646         case RTE_ETH_FILTER_GENERIC:
6647                 if (filter_op != RTE_ETH_FILTER_GET)
6648                         return -EINVAL;
6649                 *(const void **)arg = &ixgbe_flow_ops;
6650                 break;
6651         default:
6652                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6653                                                         filter_type);
6654                 ret = -EINVAL;
6655                 break;
6656         }
6657
6658         return ret;
6659 }
6660
6661 static u8 *
6662 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6663                         u8 **mc_addr_ptr, u32 *vmdq)
6664 {
6665         u8 *mc_addr;
6666
6667         *vmdq = 0;
6668         mc_addr = *mc_addr_ptr;
6669         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6670         return mc_addr;
6671 }
6672
6673 static int
6674 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6675                           struct ether_addr *mc_addr_set,
6676                           uint32_t nb_mc_addr)
6677 {
6678         struct ixgbe_hw *hw;
6679         u8 *mc_addr_list;
6680
6681         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6682         mc_addr_list = (u8 *)mc_addr_set;
6683         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6684                                          ixgbe_dev_addr_list_itr, TRUE);
6685 }
6686
6687 static uint64_t
6688 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6689 {
6690         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6691         uint64_t systime_cycles;
6692
6693         switch (hw->mac.type) {
6694         case ixgbe_mac_X550:
6695         case ixgbe_mac_X550EM_x:
6696         case ixgbe_mac_X550EM_a:
6697                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6698                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6699                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6700                                 * NSEC_PER_SEC;
6701                 break;
6702         default:
6703                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6704                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6705                                 << 32;
6706         }
6707
6708         return systime_cycles;
6709 }
6710
6711 static uint64_t
6712 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6713 {
6714         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6715         uint64_t rx_tstamp_cycles;
6716
6717         switch (hw->mac.type) {
6718         case ixgbe_mac_X550:
6719         case ixgbe_mac_X550EM_x:
6720         case ixgbe_mac_X550EM_a:
6721                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6722                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6723                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6724                                 * NSEC_PER_SEC;
6725                 break;
6726         default:
6727                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6728                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6729                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6730                                 << 32;
6731         }
6732
6733         return rx_tstamp_cycles;
6734 }
6735
6736 static uint64_t
6737 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6738 {
6739         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6740         uint64_t tx_tstamp_cycles;
6741
6742         switch (hw->mac.type) {
6743         case ixgbe_mac_X550:
6744         case ixgbe_mac_X550EM_x:
6745         case ixgbe_mac_X550EM_a:
6746                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6747                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6748                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6749                                 * NSEC_PER_SEC;
6750                 break;
6751         default:
6752                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6753                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6754                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6755                                 << 32;
6756         }
6757
6758         return tx_tstamp_cycles;
6759 }
6760
6761 static void
6762 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6763 {
6764         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6765         struct ixgbe_adapter *adapter =
6766                 (struct ixgbe_adapter *)dev->data->dev_private;
6767         struct rte_eth_link link;
6768         uint32_t incval = 0;
6769         uint32_t shift = 0;
6770
6771         /* Get current link speed. */
6772         memset(&link, 0, sizeof(link));
6773         ixgbe_dev_link_update(dev, 1);
6774         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6775
6776         switch (link.link_speed) {
6777         case ETH_SPEED_NUM_100M:
6778                 incval = IXGBE_INCVAL_100;
6779                 shift = IXGBE_INCVAL_SHIFT_100;
6780                 break;
6781         case ETH_SPEED_NUM_1G:
6782                 incval = IXGBE_INCVAL_1GB;
6783                 shift = IXGBE_INCVAL_SHIFT_1GB;
6784                 break;
6785         case ETH_SPEED_NUM_10G:
6786         default:
6787                 incval = IXGBE_INCVAL_10GB;
6788                 shift = IXGBE_INCVAL_SHIFT_10GB;
6789                 break;
6790         }
6791
6792         switch (hw->mac.type) {
6793         case ixgbe_mac_X550:
6794         case ixgbe_mac_X550EM_x:
6795         case ixgbe_mac_X550EM_a:
6796                 /* Independent of link speed. */
6797                 incval = 1;
6798                 /* Cycles read will be interpreted as ns. */
6799                 shift = 0;
6800                 /* Fall-through */
6801         case ixgbe_mac_X540:
6802                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6803                 break;
6804         case ixgbe_mac_82599EB:
6805                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6806                 shift -= IXGBE_INCVAL_SHIFT_82599;
6807                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6808                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6809                 break;
6810         default:
6811                 /* Not supported. */
6812                 return;
6813         }
6814
6815         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6816         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6817         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6818
6819         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6820         adapter->systime_tc.cc_shift = shift;
6821         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6822
6823         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6824         adapter->rx_tstamp_tc.cc_shift = shift;
6825         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6826
6827         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6828         adapter->tx_tstamp_tc.cc_shift = shift;
6829         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6830 }
6831
6832 static int
6833 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6834 {
6835         struct ixgbe_adapter *adapter =
6836                         (struct ixgbe_adapter *)dev->data->dev_private;
6837
6838         adapter->systime_tc.nsec += delta;
6839         adapter->rx_tstamp_tc.nsec += delta;
6840         adapter->tx_tstamp_tc.nsec += delta;
6841
6842         return 0;
6843 }
6844
6845 static int
6846 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6847 {
6848         uint64_t ns;
6849         struct ixgbe_adapter *adapter =
6850                         (struct ixgbe_adapter *)dev->data->dev_private;
6851
6852         ns = rte_timespec_to_ns(ts);
6853         /* Set the timecounters to a new value. */
6854         adapter->systime_tc.nsec = ns;
6855         adapter->rx_tstamp_tc.nsec = ns;
6856         adapter->tx_tstamp_tc.nsec = ns;
6857
6858         return 0;
6859 }
6860
6861 static int
6862 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6863 {
6864         uint64_t ns, systime_cycles;
6865         struct ixgbe_adapter *adapter =
6866                         (struct ixgbe_adapter *)dev->data->dev_private;
6867
6868         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6869         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6870         *ts = rte_ns_to_timespec(ns);
6871
6872         return 0;
6873 }
6874
6875 static int
6876 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6877 {
6878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6879         uint32_t tsync_ctl;
6880         uint32_t tsauxc;
6881
6882         /* Stop the timesync system time. */
6883         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6884         /* Reset the timesync system time value. */
6885         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6886         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6887
6888         /* Enable system time for platforms where it isn't on by default. */
6889         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6890         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6891         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6892
6893         ixgbe_start_timecounters(dev);
6894
6895         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6896         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6897                         (ETHER_TYPE_1588 |
6898                          IXGBE_ETQF_FILTER_EN |
6899                          IXGBE_ETQF_1588));
6900
6901         /* Enable timestamping of received PTP packets. */
6902         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6903         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6904         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6905
6906         /* Enable timestamping of transmitted PTP packets. */
6907         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6908         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6909         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6910
6911         IXGBE_WRITE_FLUSH(hw);
6912
6913         return 0;
6914 }
6915
6916 static int
6917 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6918 {
6919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6920         uint32_t tsync_ctl;
6921
6922         /* Disable timestamping of transmitted PTP packets. */
6923         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6924         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6925         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6926
6927         /* Disable timestamping of received PTP packets. */
6928         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6929         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6930         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6931
6932         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6933         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6934
6935         /* Stop incrementating the System Time registers. */
6936         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6937
6938         return 0;
6939 }
6940
6941 static int
6942 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6943                                  struct timespec *timestamp,
6944                                  uint32_t flags __rte_unused)
6945 {
6946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6947         struct ixgbe_adapter *adapter =
6948                 (struct ixgbe_adapter *)dev->data->dev_private;
6949         uint32_t tsync_rxctl;
6950         uint64_t rx_tstamp_cycles;
6951         uint64_t ns;
6952
6953         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6954         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6955                 return -EINVAL;
6956
6957         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6958         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6959         *timestamp = rte_ns_to_timespec(ns);
6960
6961         return  0;
6962 }
6963
6964 static int
6965 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6966                                  struct timespec *timestamp)
6967 {
6968         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6969         struct ixgbe_adapter *adapter =
6970                 (struct ixgbe_adapter *)dev->data->dev_private;
6971         uint32_t tsync_txctl;
6972         uint64_t tx_tstamp_cycles;
6973         uint64_t ns;
6974
6975         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6976         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6977                 return -EINVAL;
6978
6979         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6980         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6981         *timestamp = rte_ns_to_timespec(ns);
6982
6983         return 0;
6984 }
6985
6986 static int
6987 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6988 {
6989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6990         int count = 0;
6991         int g_ind = 0;
6992         const struct reg_info *reg_group;
6993         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6994                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6995
6996         while ((reg_group = reg_set[g_ind++]))
6997                 count += ixgbe_regs_group_count(reg_group);
6998
6999         return count;
7000 }
7001
7002 static int
7003 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7004 {
7005         int count = 0;
7006         int g_ind = 0;
7007         const struct reg_info *reg_group;
7008
7009         while ((reg_group = ixgbevf_regs[g_ind++]))
7010                 count += ixgbe_regs_group_count(reg_group);
7011
7012         return count;
7013 }
7014
7015 static int
7016 ixgbe_get_regs(struct rte_eth_dev *dev,
7017               struct rte_dev_reg_info *regs)
7018 {
7019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7020         uint32_t *data = regs->data;
7021         int g_ind = 0;
7022         int count = 0;
7023         const struct reg_info *reg_group;
7024         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7025                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7026
7027         if (data == NULL) {
7028                 regs->length = ixgbe_get_reg_length(dev);
7029                 regs->width = sizeof(uint32_t);
7030                 return 0;
7031         }
7032
7033         /* Support only full register dump */
7034         if ((regs->length == 0) ||
7035             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7036                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7037                         hw->device_id;
7038                 while ((reg_group = reg_set[g_ind++]))
7039                         count += ixgbe_read_regs_group(dev, &data[count],
7040                                 reg_group);
7041                 return 0;
7042         }
7043
7044         return -ENOTSUP;
7045 }
7046
7047 static int
7048 ixgbevf_get_regs(struct rte_eth_dev *dev,
7049                 struct rte_dev_reg_info *regs)
7050 {
7051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7052         uint32_t *data = regs->data;
7053         int g_ind = 0;
7054         int count = 0;
7055         const struct reg_info *reg_group;
7056
7057         if (data == NULL) {
7058                 regs->length = ixgbevf_get_reg_length(dev);
7059                 regs->width = sizeof(uint32_t);
7060                 return 0;
7061         }
7062
7063         /* Support only full register dump */
7064         if ((regs->length == 0) ||
7065             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7066                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7067                         hw->device_id;
7068                 while ((reg_group = ixgbevf_regs[g_ind++]))
7069                         count += ixgbe_read_regs_group(dev, &data[count],
7070                                                       reg_group);
7071                 return 0;
7072         }
7073
7074         return -ENOTSUP;
7075 }
7076
7077 static int
7078 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7079 {
7080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7081
7082         /* Return unit is byte count */
7083         return hw->eeprom.word_size * 2;
7084 }
7085
7086 static int
7087 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7088                 struct rte_dev_eeprom_info *in_eeprom)
7089 {
7090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7091         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7092         uint16_t *data = in_eeprom->data;
7093         int first, length;
7094
7095         first = in_eeprom->offset >> 1;
7096         length = in_eeprom->length >> 1;
7097         if ((first > hw->eeprom.word_size) ||
7098             ((first + length) > hw->eeprom.word_size))
7099                 return -EINVAL;
7100
7101         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7102
7103         return eeprom->ops.read_buffer(hw, first, length, data);
7104 }
7105
7106 static int
7107 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7108                 struct rte_dev_eeprom_info *in_eeprom)
7109 {
7110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7111         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7112         uint16_t *data = in_eeprom->data;
7113         int first, length;
7114
7115         first = in_eeprom->offset >> 1;
7116         length = in_eeprom->length >> 1;
7117         if ((first > hw->eeprom.word_size) ||
7118             ((first + length) > hw->eeprom.word_size))
7119                 return -EINVAL;
7120
7121         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7122
7123         return eeprom->ops.write_buffer(hw,  first, length, data);
7124 }
7125
7126 uint16_t
7127 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7128         switch (mac_type) {
7129         case ixgbe_mac_X550:
7130         case ixgbe_mac_X550EM_x:
7131         case ixgbe_mac_X550EM_a:
7132                 return ETH_RSS_RETA_SIZE_512;
7133         case ixgbe_mac_X550_vf:
7134         case ixgbe_mac_X550EM_x_vf:
7135         case ixgbe_mac_X550EM_a_vf:
7136                 return ETH_RSS_RETA_SIZE_64;
7137         default:
7138                 return ETH_RSS_RETA_SIZE_128;
7139         }
7140 }
7141
7142 uint32_t
7143 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7144         switch (mac_type) {
7145         case ixgbe_mac_X550:
7146         case ixgbe_mac_X550EM_x:
7147         case ixgbe_mac_X550EM_a:
7148                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7149                         return IXGBE_RETA(reta_idx >> 2);
7150                 else
7151                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7152         case ixgbe_mac_X550_vf:
7153         case ixgbe_mac_X550EM_x_vf:
7154         case ixgbe_mac_X550EM_a_vf:
7155                 return IXGBE_VFRETA(reta_idx >> 2);
7156         default:
7157                 return IXGBE_RETA(reta_idx >> 2);
7158         }
7159 }
7160
7161 uint32_t
7162 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7163         switch (mac_type) {
7164         case ixgbe_mac_X550_vf:
7165         case ixgbe_mac_X550EM_x_vf:
7166         case ixgbe_mac_X550EM_a_vf:
7167                 return IXGBE_VFMRQC;
7168         default:
7169                 return IXGBE_MRQC;
7170         }
7171 }
7172
7173 uint32_t
7174 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7175         switch (mac_type) {
7176         case ixgbe_mac_X550_vf:
7177         case ixgbe_mac_X550EM_x_vf:
7178         case ixgbe_mac_X550EM_a_vf:
7179                 return IXGBE_VFRSSRK(i);
7180         default:
7181                 return IXGBE_RSSRK(i);
7182         }
7183 }
7184
7185 bool
7186 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7187         switch (mac_type) {
7188         case ixgbe_mac_82599_vf:
7189         case ixgbe_mac_X540_vf:
7190                 return 0;
7191         default:
7192                 return 1;
7193         }
7194 }
7195
7196 static int
7197 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7198                         struct rte_eth_dcb_info *dcb_info)
7199 {
7200         struct ixgbe_dcb_config *dcb_config =
7201                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7202         struct ixgbe_dcb_tc_config *tc;
7203         uint8_t i, j;
7204
7205         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7206                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7207         else
7208                 dcb_info->nb_tcs = 1;
7209
7210         if (dcb_config->vt_mode) { /* vt is enabled*/
7211                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7212                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7213                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7214                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7215                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7216                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7217                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7218                                                 i * dcb_info->nb_tcs + j;
7219                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7220                                 dcb_info->tc_queue.tc_txq[i][j].base =
7221                                                 i * dcb_info->nb_tcs + j;
7222                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7223                         }
7224                 }
7225         } else { /* vt is disabled*/
7226                 struct rte_eth_dcb_rx_conf *rx_conf =
7227                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7228                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7229                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7230                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7231                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7232                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7233                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7234                         }
7235                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7236                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7237                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7238                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7239                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7240                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7241                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7242                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7243                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7244                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7245                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7246                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7247                         }
7248                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7249                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7250                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7251                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7252                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7253                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7254                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7255                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7256                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7257                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7258                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7259                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7260                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7261                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7262                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7263                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7264                 }
7265         }
7266         for (i = 0; i < dcb_info->nb_tcs; i++) {
7267                 tc = &dcb_config->tc_config[i];
7268                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7269         }
7270         return 0;
7271 }
7272
7273 /* Update e-tag ether type */
7274 static int
7275 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7276                             uint16_t ether_type)
7277 {
7278         uint32_t etag_etype;
7279
7280         if (hw->mac.type != ixgbe_mac_X550 &&
7281             hw->mac.type != ixgbe_mac_X550EM_x &&
7282             hw->mac.type != ixgbe_mac_X550EM_a) {
7283                 return -ENOTSUP;
7284         }
7285
7286         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7287         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7288         etag_etype |= ether_type;
7289         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7290         IXGBE_WRITE_FLUSH(hw);
7291
7292         return 0;
7293 }
7294
7295 /* Config l2 tunnel ether type */
7296 static int
7297 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7298                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7299 {
7300         int ret = 0;
7301         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7302         struct ixgbe_l2_tn_info *l2_tn_info =
7303                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7304
7305         if (l2_tunnel == NULL)
7306                 return -EINVAL;
7307
7308         switch (l2_tunnel->l2_tunnel_type) {
7309         case RTE_L2_TUNNEL_TYPE_E_TAG:
7310                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7311                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7312                 break;
7313         default:
7314                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7315                 ret = -EINVAL;
7316                 break;
7317         }
7318
7319         return ret;
7320 }
7321
7322 /* Enable e-tag tunnel */
7323 static int
7324 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7325 {
7326         uint32_t etag_etype;
7327
7328         if (hw->mac.type != ixgbe_mac_X550 &&
7329             hw->mac.type != ixgbe_mac_X550EM_x &&
7330             hw->mac.type != ixgbe_mac_X550EM_a) {
7331                 return -ENOTSUP;
7332         }
7333
7334         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7335         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7336         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7337         IXGBE_WRITE_FLUSH(hw);
7338
7339         return 0;
7340 }
7341
7342 /* Enable l2 tunnel */
7343 static int
7344 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7345                            enum rte_eth_tunnel_type l2_tunnel_type)
7346 {
7347         int ret = 0;
7348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7349         struct ixgbe_l2_tn_info *l2_tn_info =
7350                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7351
7352         switch (l2_tunnel_type) {
7353         case RTE_L2_TUNNEL_TYPE_E_TAG:
7354                 l2_tn_info->e_tag_en = TRUE;
7355                 ret = ixgbe_e_tag_enable(hw);
7356                 break;
7357         default:
7358                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7359                 ret = -EINVAL;
7360                 break;
7361         }
7362
7363         return ret;
7364 }
7365
7366 /* Disable e-tag tunnel */
7367 static int
7368 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7369 {
7370         uint32_t etag_etype;
7371
7372         if (hw->mac.type != ixgbe_mac_X550 &&
7373             hw->mac.type != ixgbe_mac_X550EM_x &&
7374             hw->mac.type != ixgbe_mac_X550EM_a) {
7375                 return -ENOTSUP;
7376         }
7377
7378         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7379         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7380         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7381         IXGBE_WRITE_FLUSH(hw);
7382
7383         return 0;
7384 }
7385
7386 /* Disable l2 tunnel */
7387 static int
7388 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7389                             enum rte_eth_tunnel_type l2_tunnel_type)
7390 {
7391         int ret = 0;
7392         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7393         struct ixgbe_l2_tn_info *l2_tn_info =
7394                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7395
7396         switch (l2_tunnel_type) {
7397         case RTE_L2_TUNNEL_TYPE_E_TAG:
7398                 l2_tn_info->e_tag_en = FALSE;
7399                 ret = ixgbe_e_tag_disable(hw);
7400                 break;
7401         default:
7402                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7403                 ret = -EINVAL;
7404                 break;
7405         }
7406
7407         return ret;
7408 }
7409
7410 static int
7411 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7412                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7413 {
7414         int ret = 0;
7415         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7416         uint32_t i, rar_entries;
7417         uint32_t rar_low, rar_high;
7418
7419         if (hw->mac.type != ixgbe_mac_X550 &&
7420             hw->mac.type != ixgbe_mac_X550EM_x &&
7421             hw->mac.type != ixgbe_mac_X550EM_a) {
7422                 return -ENOTSUP;
7423         }
7424
7425         rar_entries = ixgbe_get_num_rx_addrs(hw);
7426
7427         for (i = 1; i < rar_entries; i++) {
7428                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7429                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7430                 if ((rar_high & IXGBE_RAH_AV) &&
7431                     (rar_high & IXGBE_RAH_ADTYPE) &&
7432                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7433                      l2_tunnel->tunnel_id)) {
7434                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7435                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7436
7437                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7438
7439                         return ret;
7440                 }
7441         }
7442
7443         return ret;
7444 }
7445
7446 static int
7447 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7448                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7449 {
7450         int ret = 0;
7451         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7452         uint32_t i, rar_entries;
7453         uint32_t rar_low, rar_high;
7454
7455         if (hw->mac.type != ixgbe_mac_X550 &&
7456             hw->mac.type != ixgbe_mac_X550EM_x &&
7457             hw->mac.type != ixgbe_mac_X550EM_a) {
7458                 return -ENOTSUP;
7459         }
7460
7461         /* One entry for one tunnel. Try to remove potential existing entry. */
7462         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7463
7464         rar_entries = ixgbe_get_num_rx_addrs(hw);
7465
7466         for (i = 1; i < rar_entries; i++) {
7467                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7468                 if (rar_high & IXGBE_RAH_AV) {
7469                         continue;
7470                 } else {
7471                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7472                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7473                         rar_low = l2_tunnel->tunnel_id;
7474
7475                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7476                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7477
7478                         return ret;
7479                 }
7480         }
7481
7482         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7483                      " Please remove a rule before adding a new one.");
7484         return -EINVAL;
7485 }
7486
7487 static inline struct ixgbe_l2_tn_filter *
7488 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7489                           struct ixgbe_l2_tn_key *key)
7490 {
7491         int ret;
7492
7493         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7494         if (ret < 0)
7495                 return NULL;
7496
7497         return l2_tn_info->hash_map[ret];
7498 }
7499
7500 static inline int
7501 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7502                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7503 {
7504         int ret;
7505
7506         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7507                                &l2_tn_filter->key);
7508
7509         if (ret < 0) {
7510                 PMD_DRV_LOG(ERR,
7511                             "Failed to insert L2 tunnel filter"
7512                             " to hash table %d!",
7513                             ret);
7514                 return ret;
7515         }
7516
7517         l2_tn_info->hash_map[ret] = l2_tn_filter;
7518
7519         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7520
7521         return 0;
7522 }
7523
7524 static inline int
7525 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7526                           struct ixgbe_l2_tn_key *key)
7527 {
7528         int ret;
7529         struct ixgbe_l2_tn_filter *l2_tn_filter;
7530
7531         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7532
7533         if (ret < 0) {
7534                 PMD_DRV_LOG(ERR,
7535                             "No such L2 tunnel filter to delete %d!",
7536                             ret);
7537                 return ret;
7538         }
7539
7540         l2_tn_filter = l2_tn_info->hash_map[ret];
7541         l2_tn_info->hash_map[ret] = NULL;
7542
7543         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7544         rte_free(l2_tn_filter);
7545
7546         return 0;
7547 }
7548
7549 /* Add l2 tunnel filter */
7550 int
7551 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7552                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7553                                bool restore)
7554 {
7555         int ret;
7556         struct ixgbe_l2_tn_info *l2_tn_info =
7557                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7558         struct ixgbe_l2_tn_key key;
7559         struct ixgbe_l2_tn_filter *node;
7560
7561         if (!restore) {
7562                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7563                 key.tn_id = l2_tunnel->tunnel_id;
7564
7565                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7566
7567                 if (node) {
7568                         PMD_DRV_LOG(ERR,
7569                                     "The L2 tunnel filter already exists!");
7570                         return -EINVAL;
7571                 }
7572
7573                 node = rte_zmalloc("ixgbe_l2_tn",
7574                                    sizeof(struct ixgbe_l2_tn_filter),
7575                                    0);
7576                 if (!node)
7577                         return -ENOMEM;
7578
7579                 rte_memcpy(&node->key,
7580                                  &key,
7581                                  sizeof(struct ixgbe_l2_tn_key));
7582                 node->pool = l2_tunnel->pool;
7583                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7584                 if (ret < 0) {
7585                         rte_free(node);
7586                         return ret;
7587                 }
7588         }
7589
7590         switch (l2_tunnel->l2_tunnel_type) {
7591         case RTE_L2_TUNNEL_TYPE_E_TAG:
7592                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7593                 break;
7594         default:
7595                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7596                 ret = -EINVAL;
7597                 break;
7598         }
7599
7600         if ((!restore) && (ret < 0))
7601                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7602
7603         return ret;
7604 }
7605
7606 /* Delete l2 tunnel filter */
7607 int
7608 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7609                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7610 {
7611         int ret;
7612         struct ixgbe_l2_tn_info *l2_tn_info =
7613                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7614         struct ixgbe_l2_tn_key key;
7615
7616         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7617         key.tn_id = l2_tunnel->tunnel_id;
7618         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7619         if (ret < 0)
7620                 return ret;
7621
7622         switch (l2_tunnel->l2_tunnel_type) {
7623         case RTE_L2_TUNNEL_TYPE_E_TAG:
7624                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7625                 break;
7626         default:
7627                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7628                 ret = -EINVAL;
7629                 break;
7630         }
7631
7632         return ret;
7633 }
7634
7635 /**
7636  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7637  * @dev: pointer to rte_eth_dev structure
7638  * @filter_op:operation will be taken.
7639  * @arg: a pointer to specific structure corresponding to the filter_op
7640  */
7641 static int
7642 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7643                                   enum rte_filter_op filter_op,
7644                                   void *arg)
7645 {
7646         int ret;
7647
7648         if (filter_op == RTE_ETH_FILTER_NOP)
7649                 return 0;
7650
7651         if (arg == NULL) {
7652                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7653                             filter_op);
7654                 return -EINVAL;
7655         }
7656
7657         switch (filter_op) {
7658         case RTE_ETH_FILTER_ADD:
7659                 ret = ixgbe_dev_l2_tunnel_filter_add
7660                         (dev,
7661                          (struct rte_eth_l2_tunnel_conf *)arg,
7662                          FALSE);
7663                 break;
7664         case RTE_ETH_FILTER_DELETE:
7665                 ret = ixgbe_dev_l2_tunnel_filter_del
7666                         (dev,
7667                          (struct rte_eth_l2_tunnel_conf *)arg);
7668                 break;
7669         default:
7670                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7671                 ret = -EINVAL;
7672                 break;
7673         }
7674         return ret;
7675 }
7676
7677 static int
7678 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7679 {
7680         int ret = 0;
7681         uint32_t ctrl;
7682         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7683
7684         if (hw->mac.type != ixgbe_mac_X550 &&
7685             hw->mac.type != ixgbe_mac_X550EM_x &&
7686             hw->mac.type != ixgbe_mac_X550EM_a) {
7687                 return -ENOTSUP;
7688         }
7689
7690         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7691         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7692         if (en)
7693                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7694         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7695
7696         return ret;
7697 }
7698
7699 /* Enable l2 tunnel forwarding */
7700 static int
7701 ixgbe_dev_l2_tunnel_forwarding_enable
7702         (struct rte_eth_dev *dev,
7703          enum rte_eth_tunnel_type l2_tunnel_type)
7704 {
7705         struct ixgbe_l2_tn_info *l2_tn_info =
7706                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7707         int ret = 0;
7708
7709         switch (l2_tunnel_type) {
7710         case RTE_L2_TUNNEL_TYPE_E_TAG:
7711                 l2_tn_info->e_tag_fwd_en = TRUE;
7712                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7713                 break;
7714         default:
7715                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7716                 ret = -EINVAL;
7717                 break;
7718         }
7719
7720         return ret;
7721 }
7722
7723 /* Disable l2 tunnel forwarding */
7724 static int
7725 ixgbe_dev_l2_tunnel_forwarding_disable
7726         (struct rte_eth_dev *dev,
7727          enum rte_eth_tunnel_type l2_tunnel_type)
7728 {
7729         struct ixgbe_l2_tn_info *l2_tn_info =
7730                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7731         int ret = 0;
7732
7733         switch (l2_tunnel_type) {
7734         case RTE_L2_TUNNEL_TYPE_E_TAG:
7735                 l2_tn_info->e_tag_fwd_en = FALSE;
7736                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7737                 break;
7738         default:
7739                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7740                 ret = -EINVAL;
7741                 break;
7742         }
7743
7744         return ret;
7745 }
7746
7747 static int
7748 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7749                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7750                              bool en)
7751 {
7752         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7753         int ret = 0;
7754         uint32_t vmtir, vmvir;
7755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7756
7757         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7758                 PMD_DRV_LOG(ERR,
7759                             "VF id %u should be less than %u",
7760                             l2_tunnel->vf_id,
7761                             pci_dev->max_vfs);
7762                 return -EINVAL;
7763         }
7764
7765         if (hw->mac.type != ixgbe_mac_X550 &&
7766             hw->mac.type != ixgbe_mac_X550EM_x &&
7767             hw->mac.type != ixgbe_mac_X550EM_a) {
7768                 return -ENOTSUP;
7769         }
7770
7771         if (en)
7772                 vmtir = l2_tunnel->tunnel_id;
7773         else
7774                 vmtir = 0;
7775
7776         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7777
7778         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7779         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7780         if (en)
7781                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7782         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7783
7784         return ret;
7785 }
7786
7787 /* Enable l2 tunnel tag insertion */
7788 static int
7789 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7790                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7791 {
7792         int ret = 0;
7793
7794         switch (l2_tunnel->l2_tunnel_type) {
7795         case RTE_L2_TUNNEL_TYPE_E_TAG:
7796                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7797                 break;
7798         default:
7799                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7800                 ret = -EINVAL;
7801                 break;
7802         }
7803
7804         return ret;
7805 }
7806
7807 /* Disable l2 tunnel tag insertion */
7808 static int
7809 ixgbe_dev_l2_tunnel_insertion_disable
7810         (struct rte_eth_dev *dev,
7811          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7812 {
7813         int ret = 0;
7814
7815         switch (l2_tunnel->l2_tunnel_type) {
7816         case RTE_L2_TUNNEL_TYPE_E_TAG:
7817                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7818                 break;
7819         default:
7820                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7821                 ret = -EINVAL;
7822                 break;
7823         }
7824
7825         return ret;
7826 }
7827
7828 static int
7829 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7830                              bool en)
7831 {
7832         int ret = 0;
7833         uint32_t qde;
7834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7835
7836         if (hw->mac.type != ixgbe_mac_X550 &&
7837             hw->mac.type != ixgbe_mac_X550EM_x &&
7838             hw->mac.type != ixgbe_mac_X550EM_a) {
7839                 return -ENOTSUP;
7840         }
7841
7842         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7843         if (en)
7844                 qde |= IXGBE_QDE_STRIP_TAG;
7845         else
7846                 qde &= ~IXGBE_QDE_STRIP_TAG;
7847         qde &= ~IXGBE_QDE_READ;
7848         qde |= IXGBE_QDE_WRITE;
7849         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7850
7851         return ret;
7852 }
7853
7854 /* Enable l2 tunnel tag stripping */
7855 static int
7856 ixgbe_dev_l2_tunnel_stripping_enable
7857         (struct rte_eth_dev *dev,
7858          enum rte_eth_tunnel_type l2_tunnel_type)
7859 {
7860         int ret = 0;
7861
7862         switch (l2_tunnel_type) {
7863         case RTE_L2_TUNNEL_TYPE_E_TAG:
7864                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7865                 break;
7866         default:
7867                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7868                 ret = -EINVAL;
7869                 break;
7870         }
7871
7872         return ret;
7873 }
7874
7875 /* Disable l2 tunnel tag stripping */
7876 static int
7877 ixgbe_dev_l2_tunnel_stripping_disable
7878         (struct rte_eth_dev *dev,
7879          enum rte_eth_tunnel_type l2_tunnel_type)
7880 {
7881         int ret = 0;
7882
7883         switch (l2_tunnel_type) {
7884         case RTE_L2_TUNNEL_TYPE_E_TAG:
7885                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7886                 break;
7887         default:
7888                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7889                 ret = -EINVAL;
7890                 break;
7891         }
7892
7893         return ret;
7894 }
7895
7896 /* Enable/disable l2 tunnel offload functions */
7897 static int
7898 ixgbe_dev_l2_tunnel_offload_set
7899         (struct rte_eth_dev *dev,
7900          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7901          uint32_t mask,
7902          uint8_t en)
7903 {
7904         int ret = 0;
7905
7906         if (l2_tunnel == NULL)
7907                 return -EINVAL;
7908
7909         ret = -EINVAL;
7910         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7911                 if (en)
7912                         ret = ixgbe_dev_l2_tunnel_enable(
7913                                 dev,
7914                                 l2_tunnel->l2_tunnel_type);
7915                 else
7916                         ret = ixgbe_dev_l2_tunnel_disable(
7917                                 dev,
7918                                 l2_tunnel->l2_tunnel_type);
7919         }
7920
7921         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7922                 if (en)
7923                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7924                                 dev,
7925                                 l2_tunnel);
7926                 else
7927                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7928                                 dev,
7929                                 l2_tunnel);
7930         }
7931
7932         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7933                 if (en)
7934                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7935                                 dev,
7936                                 l2_tunnel->l2_tunnel_type);
7937                 else
7938                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7939                                 dev,
7940                                 l2_tunnel->l2_tunnel_type);
7941         }
7942
7943         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7944                 if (en)
7945                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7946                                 dev,
7947                                 l2_tunnel->l2_tunnel_type);
7948                 else
7949                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7950                                 dev,
7951                                 l2_tunnel->l2_tunnel_type);
7952         }
7953
7954         return ret;
7955 }
7956
7957 static int
7958 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7959                         uint16_t port)
7960 {
7961         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7962         IXGBE_WRITE_FLUSH(hw);
7963
7964         return 0;
7965 }
7966
7967 /* There's only one register for VxLAN UDP port.
7968  * So, we cannot add several ports. Will update it.
7969  */
7970 static int
7971 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7972                      uint16_t port)
7973 {
7974         if (port == 0) {
7975                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7976                 return -EINVAL;
7977         }
7978
7979         return ixgbe_update_vxlan_port(hw, port);
7980 }
7981
7982 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7983  * UDP port, it must have a value.
7984  * So, will reset it to the original value 0.
7985  */
7986 static int
7987 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7988                      uint16_t port)
7989 {
7990         uint16_t cur_port;
7991
7992         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7993
7994         if (cur_port != port) {
7995                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7996                 return -EINVAL;
7997         }
7998
7999         return ixgbe_update_vxlan_port(hw, 0);
8000 }
8001
8002 /* Add UDP tunneling port */
8003 static int
8004 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8005                               struct rte_eth_udp_tunnel *udp_tunnel)
8006 {
8007         int ret = 0;
8008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8009
8010         if (hw->mac.type != ixgbe_mac_X550 &&
8011             hw->mac.type != ixgbe_mac_X550EM_x &&
8012             hw->mac.type != ixgbe_mac_X550EM_a) {
8013                 return -ENOTSUP;
8014         }
8015
8016         if (udp_tunnel == NULL)
8017                 return -EINVAL;
8018
8019         switch (udp_tunnel->prot_type) {
8020         case RTE_TUNNEL_TYPE_VXLAN:
8021                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8022                 break;
8023
8024         case RTE_TUNNEL_TYPE_GENEVE:
8025         case RTE_TUNNEL_TYPE_TEREDO:
8026                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8027                 ret = -EINVAL;
8028                 break;
8029
8030         default:
8031                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8032                 ret = -EINVAL;
8033                 break;
8034         }
8035
8036         return ret;
8037 }
8038
8039 /* Remove UDP tunneling port */
8040 static int
8041 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8042                               struct rte_eth_udp_tunnel *udp_tunnel)
8043 {
8044         int ret = 0;
8045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8046
8047         if (hw->mac.type != ixgbe_mac_X550 &&
8048             hw->mac.type != ixgbe_mac_X550EM_x &&
8049             hw->mac.type != ixgbe_mac_X550EM_a) {
8050                 return -ENOTSUP;
8051         }
8052
8053         if (udp_tunnel == NULL)
8054                 return -EINVAL;
8055
8056         switch (udp_tunnel->prot_type) {
8057         case RTE_TUNNEL_TYPE_VXLAN:
8058                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8059                 break;
8060         case RTE_TUNNEL_TYPE_GENEVE:
8061         case RTE_TUNNEL_TYPE_TEREDO:
8062                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8063                 ret = -EINVAL;
8064                 break;
8065         default:
8066                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8067                 ret = -EINVAL;
8068                 break;
8069         }
8070
8071         return ret;
8072 }
8073
8074 static void
8075 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8076 {
8077         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8078
8079         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8080 }
8081
8082 static void
8083 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8084 {
8085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8086
8087         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8088 }
8089
8090 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8091 {
8092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8093         u32 in_msg = 0;
8094
8095         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8096                 return;
8097
8098         /* PF reset VF event */
8099         if (in_msg == IXGBE_PF_CONTROL_MSG)
8100                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8101                                               NULL, NULL);
8102 }
8103
8104 static int
8105 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8106 {
8107         uint32_t eicr;
8108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8109         struct ixgbe_interrupt *intr =
8110                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8111         ixgbevf_intr_disable(hw);
8112
8113         /* read-on-clear nic registers here */
8114         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8115         intr->flags = 0;
8116
8117         /* only one misc vector supported - mailbox */
8118         eicr &= IXGBE_VTEICR_MASK;
8119         if (eicr == IXGBE_MISC_VEC_ID)
8120                 intr->flags |= IXGBE_FLAG_MAILBOX;
8121
8122         return 0;
8123 }
8124
8125 static int
8126 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8127 {
8128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8129         struct ixgbe_interrupt *intr =
8130                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8131
8132         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8133                 ixgbevf_mbx_process(dev);
8134                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8135         }
8136
8137         ixgbevf_intr_enable(hw);
8138
8139         return 0;
8140 }
8141
8142 static void
8143 ixgbevf_dev_interrupt_handler(void *param)
8144 {
8145         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8146
8147         ixgbevf_dev_interrupt_get_status(dev);
8148         ixgbevf_dev_interrupt_action(dev);
8149 }
8150
8151 /**
8152  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8153  *  @hw: pointer to hardware structure
8154  *
8155  *  Stops the transmit data path and waits for the HW to internally empty
8156  *  the Tx security block
8157  **/
8158 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8159 {
8160 #define IXGBE_MAX_SECTX_POLL 40
8161
8162         int i;
8163         int sectxreg;
8164
8165         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8166         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8167         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8168         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8169                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8170                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8171                         break;
8172                 /* Use interrupt-safe sleep just in case */
8173                 usec_delay(1000);
8174         }
8175
8176         /* For informational purposes only */
8177         if (i >= IXGBE_MAX_SECTX_POLL)
8178                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8179                          "path fully disabled.  Continuing with init.");
8180
8181         return IXGBE_SUCCESS;
8182 }
8183
8184 /**
8185  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8186  *  @hw: pointer to hardware structure
8187  *
8188  *  Enables the transmit data path.
8189  **/
8190 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8191 {
8192         uint32_t sectxreg;
8193
8194         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8195         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8196         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8197         IXGBE_WRITE_FLUSH(hw);
8198
8199         return IXGBE_SUCCESS;
8200 }
8201
8202 /* restore n-tuple filter */
8203 static inline void
8204 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8205 {
8206         struct ixgbe_filter_info *filter_info =
8207                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8208         struct ixgbe_5tuple_filter *node;
8209
8210         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8211                 ixgbe_inject_5tuple_filter(dev, node);
8212         }
8213 }
8214
8215 /* restore ethernet type filter */
8216 static inline void
8217 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8218 {
8219         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8220         struct ixgbe_filter_info *filter_info =
8221                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8222         int i;
8223
8224         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8225                 if (filter_info->ethertype_mask & (1 << i)) {
8226                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8227                                         filter_info->ethertype_filters[i].etqf);
8228                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8229                                         filter_info->ethertype_filters[i].etqs);
8230                         IXGBE_WRITE_FLUSH(hw);
8231                 }
8232         }
8233 }
8234
8235 /* restore SYN filter */
8236 static inline void
8237 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8238 {
8239         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8240         struct ixgbe_filter_info *filter_info =
8241                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8242         uint32_t synqf;
8243
8244         synqf = filter_info->syn_info;
8245
8246         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8247                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8248                 IXGBE_WRITE_FLUSH(hw);
8249         }
8250 }
8251
8252 /* restore L2 tunnel filter */
8253 static inline void
8254 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8255 {
8256         struct ixgbe_l2_tn_info *l2_tn_info =
8257                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8258         struct ixgbe_l2_tn_filter *node;
8259         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8260
8261         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8262                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8263                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8264                 l2_tn_conf.pool           = node->pool;
8265                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8266         }
8267 }
8268
8269 static int
8270 ixgbe_filter_restore(struct rte_eth_dev *dev)
8271 {
8272         ixgbe_ntuple_filter_restore(dev);
8273         ixgbe_ethertype_filter_restore(dev);
8274         ixgbe_syn_filter_restore(dev);
8275         ixgbe_fdir_filter_restore(dev);
8276         ixgbe_l2_tn_filter_restore(dev);
8277
8278         return 0;
8279 }
8280
8281 static void
8282 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8283 {
8284         struct ixgbe_l2_tn_info *l2_tn_info =
8285                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8287
8288         if (l2_tn_info->e_tag_en)
8289                 (void)ixgbe_e_tag_enable(hw);
8290
8291         if (l2_tn_info->e_tag_fwd_en)
8292                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8293
8294         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8295 }
8296
8297 /* remove all the n-tuple filters */
8298 void
8299 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8300 {
8301         struct ixgbe_filter_info *filter_info =
8302                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8303         struct ixgbe_5tuple_filter *p_5tuple;
8304
8305         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8306                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8307 }
8308
8309 /* remove all the ether type filters */
8310 void
8311 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8312 {
8313         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8314         struct ixgbe_filter_info *filter_info =
8315                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8316         int i;
8317
8318         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8319                 if (filter_info->ethertype_mask & (1 << i) &&
8320                     !filter_info->ethertype_filters[i].conf) {
8321                         (void)ixgbe_ethertype_filter_remove(filter_info,
8322                                                             (uint8_t)i);
8323                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8324                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8325                         IXGBE_WRITE_FLUSH(hw);
8326                 }
8327         }
8328 }
8329
8330 /* remove the SYN filter */
8331 void
8332 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8333 {
8334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8335         struct ixgbe_filter_info *filter_info =
8336                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8337
8338         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8339                 filter_info->syn_info = 0;
8340
8341                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8342                 IXGBE_WRITE_FLUSH(hw);
8343         }
8344 }
8345
8346 /* remove all the L2 tunnel filters */
8347 int
8348 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8349 {
8350         struct ixgbe_l2_tn_info *l2_tn_info =
8351                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8352         struct ixgbe_l2_tn_filter *l2_tn_filter;
8353         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8354         int ret = 0;
8355
8356         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8357                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8358                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8359                 l2_tn_conf.pool           = l2_tn_filter->pool;
8360                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8361                 if (ret < 0)
8362                         return ret;
8363         }
8364
8365         return 0;
8366 }
8367
8368 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8369 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8370 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8371 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8372 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8373 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");