drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 190                                  struct rte_eth_dev_info *dev_info);
 191 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 192
 193 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 194                 uint16_t vlan_id, int on);
 195 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 196                                enum rte_vlan_type vlan_type,
 197                                uint16_t tpid_id);
 198 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 199                 uint16_t queue, bool on);
 200 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 201                 int on);
 202 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 203 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 205 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 206 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 207
 208 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 209 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 210 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 211                                struct rte_eth_fc_conf *fc_conf);
 212 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_pfc_conf *pfc_conf);
 216 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 217                         struct rte_eth_rss_reta_entry64 *reta_conf,
 218                         uint16_t reta_size);
 219 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 220                         struct rte_eth_rss_reta_entry64 *reta_conf,
 221                         uint16_t reta_size);
 222 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 226 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 227 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 228                 void *param);
 229 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 230 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 231                 uint32_t index, uint32_t pool);
 232 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 233 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 234                                            struct ether_addr *mac_addr);
 235 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 236
 237 /* For Virtual Function support */
 238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 240 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 241 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 246 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr* mac_addr,uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 269 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 270                 uint16_t rx_mask, uint8_t on);
 271 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 272 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 273 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 274                 uint64_t pool_mask,uint8_t vlan_on);
 275 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 276                 struct rte_eth_mirror_conf *mirror_conf,
 277                 uint8_t rule_id, uint8_t on);
 278 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 279                 uint8_t rule_id);
 280 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 281                                           uint16_t queue_id);
 282 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 283                                            uint16_t queue_id);
 284 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 285                                uint8_t queue, uint8_t msix_vector);
 286 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 287
 288 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 289                 uint16_t queue_idx, uint16_t tx_rate);
 290 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 291                 uint16_t tx_rate, uint64_t q_msk);
 292
 293 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 294                                  struct ether_addr *mac_addr,
 295                                  uint32_t index, uint32_t pool);
 296 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 297 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 298                                              struct ether_addr *mac_addr);
 299 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 300                         struct rte_eth_syn_filter *filter,
 301                         bool add);
 302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 303                         struct rte_eth_syn_filter *filter);
 304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 305                         enum rte_filter_op filter_op,
 306                         void *arg);
 307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 308                         struct ixgbe_5tuple_filter *filter);
 309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 310                         struct ixgbe_5tuple_filter *filter);
 311 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 312                         struct rte_eth_ntuple_filter *filter,
 313                         bool add);
 314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 315                                 enum rte_filter_op filter_op,
 316                                 void *arg);
 317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 318                         struct rte_eth_ntuple_filter *filter);
 319 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ethertype_filter *filter,
 321                         bool add);
 322 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ethertype_filter *filter);
 327 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 328                      enum rte_filter_type filter_type,
 329                      enum rte_filter_op filter_op,
 330                      void *arg);
 331 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 332
 333 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 334                                       struct ether_addr *mc_addr_set,
 335                                       uint32_t nb_mc_addr);
 336 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 337                                    struct rte_eth_dcb_info *dcb_info);
 338
 339 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 340 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 341                             struct rte_dev_reg_info *regs);
 342 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 343 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 344                                 struct rte_dev_eeprom_info *eeprom);
 345 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 346                                 struct rte_dev_eeprom_info *eeprom);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364
 365 static int ixgbe_dev_l2_tunnel_eth_type_conf
 366         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 367 static int ixgbe_dev_l2_tunnel_offload_set
 368         (struct rte_eth_dev *dev,
 369          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 370          uint32_t mask,
 371          uint8_t en);
 372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 373                                              enum rte_filter_op filter_op,
 374                                              void *arg);
 375
 376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 377                                          struct rte_eth_udp_tunnel *udp_tunnel);
 378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 379                                          struct rte_eth_udp_tunnel *udp_tunnel);
 380
 381 /*
 382  * Define VF Stats MACRO for Non "cleared on read" register
 383  */
 384 #define UPDATE_VF_STAT(reg, last, cur)                          \
 385 {                                                               \
 386         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 387         cur += (latest - last) & UINT_MAX;                      \
 388         last = latest;                                          \
 389 }
 390
 391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 392 {                                                                \
 393         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 394         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 395         u64 latest = ((new_msb << 32) | new_lsb);                \
 396         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 397         last = latest;                                           \
 398 }
 399
 400 #define IXGBE_SET_HWSTRIP(h, q) do{\
 401                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 403                 (h)->bitmap[idx] |= 1 << bit;\
 404         } while (0)
 405
 406 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 407                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 408                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 409                 (h)->bitmap[idx] &= ~(1 << bit);\
 410         } while (0)
 411
 412 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 413                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 414                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 415                 (r) = (h)->bitmap[idx] >> bit & 1;\
 416         } while (0)
 417
 418 /*
 419  * The set of PCI devices this driver supports
 420  */
 421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 422
 423 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 424 #include "rte_pci_dev_ids.h"
 425
 426 { .vendor_id = 0, /* sentinel */ },
 427 };
 428
 429
 430 /*
 431  * The set of PCI devices this driver supports (for 82599 VF)
 432  */
 433 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 434
 435 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 436 #include "rte_pci_dev_ids.h"
 437 { .vendor_id = 0, /* sentinel */ },
 438
 439 };
 440
 441 static const struct rte_eth_desc_lim rx_desc_lim = {
 442         .nb_max = IXGBE_MAX_RING_DESC,
 443         .nb_min = IXGBE_MIN_RING_DESC,
 444         .nb_align = IXGBE_RXD_ALIGN,
 445 };
 446
 447 static const struct rte_eth_desc_lim tx_desc_lim = {
 448         .nb_max = IXGBE_MAX_RING_DESC,
 449         .nb_min = IXGBE_MIN_RING_DESC,
 450         .nb_align = IXGBE_TXD_ALIGN,
 451 };
 452
 453 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 454         .dev_configure        = ixgbe_dev_configure,
 455         .dev_start            = ixgbe_dev_start,
 456         .dev_stop             = ixgbe_dev_stop,
 457         .dev_set_link_up    = ixgbe_dev_set_link_up,
 458         .dev_set_link_down  = ixgbe_dev_set_link_down,
 459         .dev_close            = ixgbe_dev_close,
 460         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 461         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 462         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 463         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 464         .link_update          = ixgbe_dev_link_update,
 465         .stats_get            = ixgbe_dev_stats_get,
 466         .xstats_get           = ixgbe_dev_xstats_get,
 467         .stats_reset          = ixgbe_dev_stats_reset,
 468         .xstats_reset         = ixgbe_dev_xstats_reset,
 469         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 470         .dev_infos_get        = ixgbe_dev_info_get,
 471         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 472         .mtu_set              = ixgbe_dev_mtu_set,
 473         .vlan_filter_set      = ixgbe_vlan_filter_set,
 474         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 475         .vlan_offload_set     = ixgbe_vlan_offload_set,
 476         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 477         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 478         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 479         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 480         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 481         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 482         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 484         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 485         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 486         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 487         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 488         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 489         .dev_led_on           = ixgbe_dev_led_on,
 490         .dev_led_off          = ixgbe_dev_led_off,
 491         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 492         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 493         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 494         .mac_addr_add         = ixgbe_add_rar,
 495         .mac_addr_remove      = ixgbe_remove_rar,
 496         .mac_addr_set         = ixgbe_set_default_mac_addr,
 497         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 498         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 499         .mirror_rule_set      = ixgbe_mirror_rule_set,
 500         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 501         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 502         .set_vf_rx            = ixgbe_set_pool_rx,
 503         .set_vf_tx            = ixgbe_set_pool_tx,
 504         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 505         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 506         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 507         .reta_update          = ixgbe_dev_rss_reta_update,
 508         .reta_query           = ixgbe_dev_rss_reta_query,
 509 #ifdef RTE_NIC_BYPASS
 510         .bypass_init          = ixgbe_bypass_init,
 511         .bypass_state_set     = ixgbe_bypass_state_store,
 512         .bypass_state_show    = ixgbe_bypass_state_show,
 513         .bypass_event_set     = ixgbe_bypass_event_store,
 514         .bypass_event_show    = ixgbe_bypass_event_show,
 515         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 516         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 517         .bypass_ver_show      = ixgbe_bypass_ver_show,
 518         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 519 #endif /* RTE_NIC_BYPASS */
 520         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 521         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 522         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 523         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 524         .rxq_info_get         = ixgbe_rxq_info_get,
 525         .txq_info_get         = ixgbe_txq_info_get,
 526         .timesync_enable      = ixgbe_timesync_enable,
 527         .timesync_disable     = ixgbe_timesync_disable,
 528         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 529         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 530         .get_reg_length       = ixgbe_get_reg_length,
 531         .get_reg              = ixgbe_get_regs,
 532         .get_eeprom_length    = ixgbe_get_eeprom_length,
 533         .get_eeprom           = ixgbe_get_eeprom,
 534         .set_eeprom           = ixgbe_set_eeprom,
 535         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 536         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 537         .timesync_read_time   = ixgbe_timesync_read_time,
 538         .timesync_write_time  = ixgbe_timesync_write_time,
 539         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 540         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 541         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 542         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 543 };
 544
 545 /*
 546  * dev_ops for virtual function, bare necessities for basic vf
 547  * operation have been implemented
 548  */
 549 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 550         .dev_configure        = ixgbevf_dev_configure,
 551         .dev_start            = ixgbevf_dev_start,
 552         .dev_stop             = ixgbevf_dev_stop,
 553         .link_update          = ixgbe_dev_link_update,
 554         .stats_get            = ixgbevf_dev_stats_get,
 555         .xstats_get           = ixgbevf_dev_xstats_get,
 556         .stats_reset          = ixgbevf_dev_stats_reset,
 557         .xstats_reset         = ixgbevf_dev_stats_reset,
 558         .dev_close            = ixgbevf_dev_close,
 559         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 560         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 561         .dev_infos_get        = ixgbevf_dev_info_get,
 562         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 563         .mtu_set              = ixgbevf_dev_set_mtu,
 564         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 565         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 566         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 567         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 568         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 569         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 570         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 571         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 572         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 573         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 574         .mac_addr_add         = ixgbevf_add_mac_addr,
 575         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 576         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 577         .rxq_info_get         = ixgbe_rxq_info_get,
 578         .txq_info_get         = ixgbe_txq_info_get,
 579         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 580         .get_reg_length       = ixgbevf_get_reg_length,
 581         .get_reg              = ixgbevf_get_regs,
 582         .reta_update          = ixgbe_dev_rss_reta_update,
 583         .reta_query           = ixgbe_dev_rss_reta_query,
 584         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 585         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 586 };
 587
 588 /* store statistics names and its offset in stats structure */
 589 struct rte_ixgbe_xstats_name_off {
 590         char name[RTE_ETH_XSTATS_NAME_SIZE];
 591         unsigned offset;
 592 };
 593
 594 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 595         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 596         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 597         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 598         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 599         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 600         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 601         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 602         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 603         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 604         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 605         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 606         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 607         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 608         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 609         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 610                 prc1023)},
 611         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 612                 prc1522)},
 613         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 614         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 615         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 616         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 617         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 618         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 619         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 620         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 621         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 622         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 623         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 624         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 625         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 626         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 627         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 628         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 629         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 630                 ptc1023)},
 631         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 632                 ptc1522)},
 633         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 634         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 635         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 636         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 637
 638         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 639                 fdirustat_add)},
 640         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 641                 fdirustat_remove)},
 642         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 643                 fdirfstat_fadd)},
 644         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 645                 fdirfstat_fremove)},
 646         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 647                 fdirmatch)},
 648         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 649                 fdirmiss)},
 650
 651         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 652         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 653         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 654                 fclast)},
 655         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 656         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 657         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 658         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 659         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 660                 fcoe_noddp)},
 661         {"rx_fcoe_no_direct_data_placement_ext_buff",
 662                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 663
 664         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 665                 lxontxc)},
 666         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 667                 lxonrxc)},
 668         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 669                 lxofftxc)},
 670         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 671                 lxoffrxc)},
 672         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 673 };
 674
 675 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 676                            sizeof(rte_ixgbe_stats_strings[0]))
 677
 678 /* Per-queue statistics */
 679 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 680         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 681         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 682         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 683         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 684 };
 685
 686 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 687                            sizeof(rte_ixgbe_rxq_strings[0]))
 688
 689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 690         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 691         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 692         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 693                 pxon2offc)},
 694 };
 695
 696 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 697                            sizeof(rte_ixgbe_txq_strings[0]))
 698
 699 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 700         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 701 };
 702
 703 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 704                 sizeof(rte_ixgbevf_stats_strings[0]))
 705
 706 /**
 707  * Atomically reads the link status information from global
 708  * structure rte_eth_dev.
 709  *
 710  * @param dev
 711  *   - Pointer to the structure rte_eth_dev to read from.
 712  *   - Pointer to the buffer to be saved with the link status.
 713  *
 714  * @return
 715  *   - On success, zero.
 716  *   - On failure, negative value.
 717  */
 718 static inline int
 719 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 720                                 struct rte_eth_link *link)
 721 {
 722         struct rte_eth_link *dst = link;
 723         struct rte_eth_link *src = &(dev->data->dev_link);
 724
 725         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 726                                         *(uint64_t *)src) == 0)
 727                 return -1;
 728
 729         return 0;
 730 }
 731
 732 /**
 733  * Atomically writes the link status information into global
 734  * structure rte_eth_dev.
 735  *
 736  * @param dev
 737  *   - Pointer to the structure rte_eth_dev to read from.
 738  *   - Pointer to the buffer to be saved with the link status.
 739  *
 740  * @return
 741  *   - On success, zero.
 742  *   - On failure, negative value.
 743  */
 744 static inline int
 745 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 746                                 struct rte_eth_link *link)
 747 {
 748         struct rte_eth_link *dst = &(dev->data->dev_link);
 749         struct rte_eth_link *src = link;
 750
 751         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 752                                         *(uint64_t *)src) == 0)
 753                 return -1;
 754
 755         return 0;
 756 }
 757
 758 /*
 759  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 760  */
 761 static inline int
 762 ixgbe_is_sfp(struct ixgbe_hw *hw)
 763 {
 764         switch (hw->phy.type) {
 765         case ixgbe_phy_sfp_avago:
 766         case ixgbe_phy_sfp_ftl:
 767         case ixgbe_phy_sfp_intel:
 768         case ixgbe_phy_sfp_unknown:
 769         case ixgbe_phy_sfp_passive_tyco:
 770         case ixgbe_phy_sfp_passive_unknown:
 771                 return 1;
 772         default:
 773                 return 0;
 774         }
 775 }
 776
 777 static inline int32_t
 778 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 779 {
 780         uint32_t ctrl_ext;
 781         int32_t status;
 782
 783         status = ixgbe_reset_hw(hw);
 784
 785         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 786         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 787         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 788         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 789         IXGBE_WRITE_FLUSH(hw);
 790
 791         return status;
 792 }
 793
 794 static inline void
 795 ixgbe_enable_intr(struct rte_eth_dev *dev)
 796 {
 797         struct ixgbe_interrupt *intr =
 798                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 799         struct ixgbe_hw *hw =
 800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 801
 802         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 803         IXGBE_WRITE_FLUSH(hw);
 804 }
 805
 806 /*
 807  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 808  */
 809 static void
 810 ixgbe_disable_intr(struct ixgbe_hw *hw)
 811 {
 812         PMD_INIT_FUNC_TRACE();
 813
 814         if (hw->mac.type == ixgbe_mac_82598EB) {
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 816         } else {
 817                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 818                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 819                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 820         }
 821         IXGBE_WRITE_FLUSH(hw);
 822 }
 823
 824 /*
 825  * This function resets queue statistics mapping registers.
 826  * From Niantic datasheet, Initialization of Statistics section:
 827  * "...if software requires the queue counters, the RQSMR and TQSM registers
 828  * must be re-programmed following a device reset.
 829  */
 830 static void
 831 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 832 {
 833         uint32_t i;
 834
 835         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 836                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 837                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 838         }
 839 }
 840
 841
 842 static int
 843 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 844                                   uint16_t queue_id,
 845                                   uint8_t stat_idx,
 846                                   uint8_t is_rx)
 847 {
 848 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 849 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 850 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 851
 852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 853         struct ixgbe_stat_mapping_registers *stat_mappings =
 854                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 855         uint32_t qsmr_mask = 0;
 856         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 857         uint32_t q_map;
 858         uint8_t n, offset;
 859
 860         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 861                 (hw->mac.type != ixgbe_mac_X540) &&
 862                 (hw->mac.type != ixgbe_mac_X550) &&
 863                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 864                 (hw->mac.type != ixgbe_mac_X550EM_a))
 865                 return -ENOSYS;
 866
 867         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 868                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 869                      queue_id, stat_idx);
 870
 871         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 872         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 873                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 874                 return -EIO;
 875         }
 876         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 877
 878         /* Now clear any previous stat_idx set */
 879         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 880         if (!is_rx)
 881                 stat_mappings->tqsm[n] &= ~clearing_mask;
 882         else
 883                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 884
 885         q_map = (uint32_t)stat_idx;
 886         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 887         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 888         if (!is_rx)
 889                 stat_mappings->tqsm[n] |= qsmr_mask;
 890         else
 891                 stat_mappings->rqsmr[n] |= qsmr_mask;
 892
 893         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 894                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 895                      queue_id, stat_idx);
 896         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 897                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 898
 899         /* Now write the mapping in the appropriate register */
 900         if (is_rx) {
 901                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 902                              stat_mappings->rqsmr[n], n);
 903                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 904         }
 905         else {
 906                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 907                              stat_mappings->tqsm[n], n);
 908                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 909         }
 910         return 0;
 911 }
 912
 913 static void
 914 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 915 {
 916         struct ixgbe_stat_mapping_registers *stat_mappings =
 917                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 919         int i;
 920
 921         /* write whatever was in stat mapping table to the NIC */
 922         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 923                 /* rx */
 924                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 925
 926                 /* tx */
 927                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 928         }
 929 }
 930
 931 static void
 932 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 933 {
 934         uint8_t i;
 935         struct ixgbe_dcb_tc_config *tc;
 936         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 937
 938         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 939         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 940         for (i = 0; i < dcb_max_tc; i++) {
 941                 tc = &dcb_config->tc_config[i];
 942                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 943                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 944                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 945                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 946                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 947                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 948                 tc->pfc = ixgbe_dcb_pfc_disabled;
 949         }
 950
 951         /* Initialize default user to priority mapping, UPx->TC0 */
 952         tc = &dcb_config->tc_config[0];
 953         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 954         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 955         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 956                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 957                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 958         }
 959         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 960         dcb_config->pfc_mode_enable = false;
 961         dcb_config->vt_mode = true;
 962         dcb_config->round_robin_enable = false;
 963         /* support all DCB capabilities in 82599 */
 964         dcb_config->support.capabilities = 0xFF;
 965
 966         /*we only support 4 Tcs for X540, X550 */
 967         if (hw->mac.type == ixgbe_mac_X540 ||
 968                 hw->mac.type == ixgbe_mac_X550 ||
 969                 hw->mac.type == ixgbe_mac_X550EM_x ||
 970                 hw->mac.type == ixgbe_mac_X550EM_a) {
 971                 dcb_config->num_tcs.pg_tcs = 4;
 972                 dcb_config->num_tcs.pfc_tcs = 4;
 973         }
 974 }
 975
 976 /*
 977  * Ensure that all locks are released before first NVM or PHY access
 978  */
 979 static void
 980 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 981 {
 982         uint16_t mask;
 983
 984         /*
 985          * Phy lock should not fail in this early stage. If this is the case,
 986          * it is due to an improper exit of the application.
 987          * So force the release of the faulty lock. Release of common lock
 988          * is done automatically by swfw_sync function.
 989          */
 990         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 991         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 992                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 993         }
 994         ixgbe_release_swfw_semaphore(hw, mask);
 995
 996         /*
 997          * These ones are more tricky since they are common to all ports; but
 998          * swfw_sync retries last long enough (1s) to be almost sure that if
 999          * lock can not be taken it is due to an improper lock of the
1000          * semaphore.
1001          */
1002         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1003         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1004                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1005         }
1006         ixgbe_release_swfw_semaphore(hw, mask);
1007 }
1008
1009 /*
1010  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1011  * It returns 0 on success.
1012  */
1013 static int
1014 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1015 {
1016         struct rte_pci_device *pci_dev;
1017         struct ixgbe_hw *hw =
1018                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1019         struct ixgbe_vfta * shadow_vfta =
1020                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1021         struct ixgbe_hwstrip *hwstrip =
1022                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1023         struct ixgbe_dcb_config *dcb_config =
1024                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1025         struct ixgbe_filter_info *filter_info =
1026                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1027         uint32_t ctrl_ext;
1028         uint16_t csum;
1029         int diag, i;
1030
1031         PMD_INIT_FUNC_TRACE();
1032
1033         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1034         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1035         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1036
1037         /*
1038          * For secondary processes, we don't initialise any further as primary
1039          * has already done this work. Only check we don't need a different
1040          * RX and TX function.
1041          */
1042         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1043                 struct ixgbe_tx_queue *txq;
1044                 /* TX queue function in primary, set by last queue initialized
1045                  * Tx queue may not initialized by primary process */
1046                 if (eth_dev->data->tx_queues) {
1047                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1048                         ixgbe_set_tx_function(eth_dev, txq);
1049                 } else {
1050                         /* Use default TX function if we get here */
1051                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1052                                              "Using default TX function.");
1053                 }
1054
1055                 ixgbe_set_rx_function(eth_dev);
1056
1057                 return 0;
1058         }
1059         pci_dev = eth_dev->pci_dev;
1060
1061         rte_eth_copy_pci_info(eth_dev, pci_dev);
1062
1063         /* Vendor and Device ID need to be set before init of shared code */
1064         hw->device_id = pci_dev->id.device_id;
1065         hw->vendor_id = pci_dev->id.vendor_id;
1066         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1067         hw->allow_unsupported_sfp = 1;
1068
1069         /* Initialize the shared code (base driver) */
1070 #ifdef RTE_NIC_BYPASS
1071         diag = ixgbe_bypass_init_shared_code(hw);
1072 #else
1073         diag = ixgbe_init_shared_code(hw);
1074 #endif /* RTE_NIC_BYPASS */
1075
1076         if (diag != IXGBE_SUCCESS) {
1077                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1078                 return -EIO;
1079         }
1080
1081         /* pick up the PCI bus settings for reporting later */
1082         ixgbe_get_bus_info(hw);
1083
1084         /* Unlock any pending hardware semaphore */
1085         ixgbe_swfw_lock_reset(hw);
1086
1087         /* Initialize DCB configuration*/
1088         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1089         ixgbe_dcb_init(hw,dcb_config);
1090         /* Get Hardware Flow Control setting */
1091         hw->fc.requested_mode = ixgbe_fc_full;
1092         hw->fc.current_mode = ixgbe_fc_full;
1093         hw->fc.pause_time = IXGBE_FC_PAUSE;
1094         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1095                 hw->fc.low_water[i] = IXGBE_FC_LO;
1096                 hw->fc.high_water[i] = IXGBE_FC_HI;
1097         }
1098         hw->fc.send_xon = 1;
1099
1100         /* Make sure we have a good EEPROM before we read from it */
1101         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1102         if (diag != IXGBE_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1104                 return -EIO;
1105         }
1106
1107 #ifdef RTE_NIC_BYPASS
1108         diag = ixgbe_bypass_init_hw(hw);
1109 #else
1110         diag = ixgbe_init_hw(hw);
1111 #endif /* RTE_NIC_BYPASS */
1112
1113         /*
1114          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1115          * is called too soon after the kernel driver unbinding/binding occurs.
1116          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1117          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1118          * also called. See ixgbe_identify_phy_82599(). The reason for the
1119          * failure is not known, and only occuts when virtualisation features
1120          * are disabled in the bios. A delay of 100ms  was found to be enough by
1121          * trial-and-error, and is doubled to be safe.
1122          */
1123         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1124                 rte_delay_ms(200);
1125                 diag = ixgbe_init_hw(hw);
1126         }
1127
1128         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1129                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1130                     "LOM.  Please be aware there may be issues associated "
1131                     "with your hardware.");
1132                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1133                     "please contact your Intel or hardware representative "
1134                     "who provided you with this hardware.");
1135         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1136                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1137         if (diag) {
1138                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1139                 return -EIO;
1140         }
1141
1142         /* Reset the hw statistics */
1143         ixgbe_dev_stats_reset(eth_dev);
1144
1145         /* disable interrupt */
1146         ixgbe_disable_intr(hw);
1147
1148         /* reset mappings for queue statistics hw counters*/
1149         ixgbe_reset_qstat_mappings(hw);
1150
1151         /* Allocate memory for storing MAC addresses */
1152         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1153                         hw->mac.num_rar_entries, 0);
1154         if (eth_dev->data->mac_addrs == NULL) {
1155                 PMD_INIT_LOG(ERR,
1156                         "Failed to allocate %u bytes needed to store "
1157                         "MAC addresses",
1158                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1159                 return -ENOMEM;
1160         }
1161         /* Copy the permanent MAC address */
1162         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1163                         &eth_dev->data->mac_addrs[0]);
1164
1165         /* Allocate memory for storing hash filter MAC addresses */
1166         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1168         if (eth_dev->data->hash_mac_addrs == NULL) {
1169                 PMD_INIT_LOG(ERR,
1170                         "Failed to allocate %d bytes needed to store MAC addresses",
1171                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1172                 return -ENOMEM;
1173         }
1174
1175         /* initialize the vfta */
1176         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1177
1178         /* initialize the hw strip bitmap*/
1179         memset(hwstrip, 0, sizeof(*hwstrip));
1180
1181         /* initialize PF if max_vfs not zero */
1182         ixgbe_pf_host_init(eth_dev);
1183
1184         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1185         /* let hardware know driver is loaded */
1186         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1187         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1188         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1189         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1190         IXGBE_WRITE_FLUSH(hw);
1191
1192         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1193                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1194                              (int) hw->mac.type, (int) hw->phy.type,
1195                              (int) hw->phy.sfp_type);
1196         else
1197                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1198                              (int) hw->mac.type, (int) hw->phy.type);
1199
1200         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1201                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1202                         pci_dev->id.device_id);
1203
1204         rte_intr_callback_register(&pci_dev->intr_handle,
1205                                    ixgbe_dev_interrupt_handler,
1206                                    (void *)eth_dev);
1207
1208         /* enable uio/vfio intr/eventfd mapping */
1209         rte_intr_enable(&pci_dev->intr_handle);
1210
1211         /* enable support intr */
1212         ixgbe_enable_intr(eth_dev);
1213
1214         /* initialize 5tuple filter list */
1215         TAILQ_INIT(&filter_info->fivetuple_list);
1216         memset(filter_info->fivetuple_mask, 0,
1217                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1218
1219         return 0;
1220 }
1221
1222 static int
1223 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1224 {
1225         struct rte_pci_device *pci_dev;
1226         struct ixgbe_hw *hw;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1231                 return -EPERM;
1232
1233         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1234         pci_dev = eth_dev->pci_dev;
1235
1236         if (hw->adapter_stopped == 0)
1237                 ixgbe_dev_close(eth_dev);
1238
1239         eth_dev->dev_ops = NULL;
1240         eth_dev->rx_pkt_burst = NULL;
1241         eth_dev->tx_pkt_burst = NULL;
1242
1243         /* Unlock any pending hardware semaphore */
1244         ixgbe_swfw_lock_reset(hw);
1245
1246         /* disable uio intr before callback unregister */
1247         rte_intr_disable(&(pci_dev->intr_handle));
1248         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1249                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1250
1251         /* uninitialize PF if max_vfs not zero */
1252         ixgbe_pf_host_uninit(eth_dev);
1253
1254         rte_free(eth_dev->data->mac_addrs);
1255         eth_dev->data->mac_addrs = NULL;
1256
1257         rte_free(eth_dev->data->hash_mac_addrs);
1258         eth_dev->data->hash_mac_addrs = NULL;
1259
1260         return 0;
1261 }
1262
1263 /*
1264  * Negotiate mailbox API version with the PF.
1265  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1266  * Then we try to negotiate starting with the most recent one.
1267  * If all negotiation attempts fail, then we will proceed with
1268  * the default one (ixgbe_mbox_api_10).
1269  */
1270 static void
1271 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1272 {
1273         int32_t i;
1274
1275         /* start with highest supported, proceed down */
1276         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1277                 ixgbe_mbox_api_12,
1278                 ixgbe_mbox_api_11,
1279                 ixgbe_mbox_api_10,
1280         };
1281
1282         for (i = 0;
1283                         i != RTE_DIM(sup_ver) &&
1284                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1285                         i++)
1286                 ;
1287 }
1288
1289 static void
1290 generate_random_mac_addr(struct ether_addr *mac_addr)
1291 {
1292         uint64_t random;
1293
1294         /* Set Organizationally Unique Identifier (OUI) prefix. */
1295         mac_addr->addr_bytes[0] = 0x00;
1296         mac_addr->addr_bytes[1] = 0x09;
1297         mac_addr->addr_bytes[2] = 0xC0;
1298         /* Force indication of locally assigned MAC address. */
1299         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1300         /* Generate the last 3 bytes of the MAC address with a random number. */
1301         random = rte_rand();
1302         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1303 }
1304
1305 /*
1306  * Virtual Function device init
1307  */
1308 static int
1309 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1310 {
1311         int diag;
1312         uint32_t tc, tcs;
1313         struct rte_pci_device *pci_dev;
1314         struct ixgbe_hw *hw =
1315                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316         struct ixgbe_vfta * shadow_vfta =
1317                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1318         struct ixgbe_hwstrip *hwstrip =
1319                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1320         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1325         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1326         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1327
1328         /* for secondary processes, we don't initialise any further as primary
1329          * has already done this work. Only check we don't need a different
1330          * RX function */
1331         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1332                 struct ixgbe_tx_queue *txq;
1333                 /* TX queue function in primary, set by last queue initialized
1334                  * Tx queue may not initialized by primary process
1335                  */
1336                 if (eth_dev->data->tx_queues) {
1337                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1338                         ixgbe_set_tx_function(eth_dev, txq);
1339                 } else {
1340                         /* Use default TX function if we get here */
1341                         PMD_INIT_LOG(NOTICE,
1342                                 "No TX queues configured yet. Using default TX function.");
1343                 }
1344
1345                 ixgbe_set_rx_function(eth_dev);
1346
1347                 return 0;
1348         }
1349
1350         pci_dev = eth_dev->pci_dev;
1351
1352         rte_eth_copy_pci_info(eth_dev, pci_dev);
1353
1354         hw->device_id = pci_dev->id.device_id;
1355         hw->vendor_id = pci_dev->id.vendor_id;
1356         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1357
1358         /* initialize the vfta */
1359         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1360
1361         /* initialize the hw strip bitmap*/
1362         memset(hwstrip, 0, sizeof(*hwstrip));
1363
1364         /* Initialize the shared code (base driver) */
1365         diag = ixgbe_init_shared_code(hw);
1366         if (diag != IXGBE_SUCCESS) {
1367                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1368                 return -EIO;
1369         }
1370
1371         /* init_mailbox_params */
1372         hw->mbx.ops.init_params(hw);
1373
1374         /* Reset the hw statistics */
1375         ixgbevf_dev_stats_reset(eth_dev);
1376
1377         /* Disable the interrupts for VF */
1378         ixgbevf_intr_disable(hw);
1379
1380         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1381         diag = hw->mac.ops.reset_hw(hw);
1382
1383         /*
1384          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1385          * the underlying PF driver has not assigned a MAC address to the VF.
1386          * In this case, assign a random MAC address.
1387          */
1388         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1389                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1390                 return diag;
1391         }
1392
1393         /* negotiate mailbox API version to use with the PF. */
1394         ixgbevf_negotiate_api(hw);
1395
1396         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1397         ixgbevf_get_queues(hw, &tcs, &tc);
1398
1399         /* Allocate memory for storing MAC addresses */
1400         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1401                         hw->mac.num_rar_entries, 0);
1402         if (eth_dev->data->mac_addrs == NULL) {
1403                 PMD_INIT_LOG(ERR,
1404                         "Failed to allocate %u bytes needed to store "
1405                         "MAC addresses",
1406                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1407                 return -ENOMEM;
1408         }
1409
1410         /* Generate a random MAC address, if none was assigned by PF. */
1411         if (is_zero_ether_addr(perm_addr)) {
1412                 generate_random_mac_addr(perm_addr);
1413                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1414                 if (diag) {
1415                         rte_free(eth_dev->data->mac_addrs);
1416                         eth_dev->data->mac_addrs = NULL;
1417                         return diag;
1418                 }
1419                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1420                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1421                              "%02x:%02x:%02x:%02x:%02x:%02x",
1422                              perm_addr->addr_bytes[0],
1423                              perm_addr->addr_bytes[1],
1424                              perm_addr->addr_bytes[2],
1425                              perm_addr->addr_bytes[3],
1426                              perm_addr->addr_bytes[4],
1427                              perm_addr->addr_bytes[5]);
1428         }
1429
1430         /* Copy the permanent MAC address */
1431         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1432
1433         /* reset the hardware with the new settings */
1434         diag = hw->mac.ops.start_hw(hw);
1435         switch (diag) {
1436                 case  0:
1437                         break;
1438
1439                 default:
1440                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1441                         return -EIO;
1442         }
1443
1444         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1445                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1446                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1447
1448         return 0;
1449 }
1450
1451 /* Virtual Function device uninit */
1452
1453 static int
1454 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1455 {
1456         struct ixgbe_hw *hw;
1457
1458         PMD_INIT_FUNC_TRACE();
1459
1460         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1461                 return -EPERM;
1462
1463         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1464
1465         if (hw->adapter_stopped == 0)
1466                 ixgbevf_dev_close(eth_dev);
1467
1468         eth_dev->dev_ops = NULL;
1469         eth_dev->rx_pkt_burst = NULL;
1470         eth_dev->tx_pkt_burst = NULL;
1471
1472         /* Disable the interrupts for VF */
1473         ixgbevf_intr_disable(hw);
1474
1475         rte_free(eth_dev->data->mac_addrs);
1476         eth_dev->data->mac_addrs = NULL;
1477
1478         return 0;
1479 }
1480
1481 static struct eth_driver rte_ixgbe_pmd = {
1482         .pci_drv = {
1483                 .name = "rte_ixgbe_pmd",
1484                 .id_table = pci_id_ixgbe_map,
1485                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1486                         RTE_PCI_DRV_DETACHABLE,
1487         },
1488         .eth_dev_init = eth_ixgbe_dev_init,
1489         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1490         .dev_private_size = sizeof(struct ixgbe_adapter),
1491 };
1492
1493 /*
1494  * virtual function driver struct
1495  */
1496 static struct eth_driver rte_ixgbevf_pmd = {
1497         .pci_drv = {
1498                 .name = "rte_ixgbevf_pmd",
1499                 .id_table = pci_id_ixgbevf_map,
1500                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1501         },
1502         .eth_dev_init = eth_ixgbevf_dev_init,
1503         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1504         .dev_private_size = sizeof(struct ixgbe_adapter),
1505 };
1506
1507 /*
1508  * Driver initialization routine.
1509  * Invoked once at EAL init time.
1510  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1511  */
1512 static int
1513 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1514 {
1515         PMD_INIT_FUNC_TRACE();
1516
1517         rte_eth_driver_register(&rte_ixgbe_pmd);
1518         return 0;
1519 }
1520
1521 /*
1522  * VF Driver initialization routine.
1523  * Invoked one at EAL init time.
1524  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1525  */
1526 static int
1527 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1528 {
1529         PMD_INIT_FUNC_TRACE();
1530
1531         rte_eth_driver_register(&rte_ixgbevf_pmd);
1532         return 0;
1533 }
1534
1535 static int
1536 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1537 {
1538         struct ixgbe_hw *hw =
1539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540         struct ixgbe_vfta * shadow_vfta =
1541                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1542         uint32_t vfta;
1543         uint32_t vid_idx;
1544         uint32_t vid_bit;
1545
1546         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1547         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1548         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1549         if (on)
1550                 vfta |= vid_bit;
1551         else
1552                 vfta &= ~vid_bit;
1553         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1554
1555         /* update local VFTA copy */
1556         shadow_vfta->vfta[vid_idx] = vfta;
1557
1558         return 0;
1559 }
1560
1561 static void
1562 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1563 {
1564         if (on)
1565                 ixgbe_vlan_hw_strip_enable(dev, queue);
1566         else
1567                 ixgbe_vlan_hw_strip_disable(dev, queue);
1568 }
1569
1570 static int
1571 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1572                     enum rte_vlan_type vlan_type,
1573                     uint16_t tpid)
1574 {
1575         struct ixgbe_hw *hw =
1576                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577         int ret = 0;
1578
1579         switch (vlan_type) {
1580         case ETH_VLAN_TYPE_INNER:
1581                 /* Only the high 16-bits is valid */
1582                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1583                 break;
1584         default:
1585                 ret = -EINVAL;
1586                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1587                 break;
1588         }
1589
1590         return ret;
1591 }
1592
1593 void
1594 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1595 {
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         uint32_t vlnctrl;
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         /* Filter Table Disable */
1603         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1604         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1605
1606         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1607 }
1608
1609 void
1610 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1611 {
1612         struct ixgbe_hw *hw =
1613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614         struct ixgbe_vfta * shadow_vfta =
1615                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1616         uint32_t vlnctrl;
1617         uint16_t i;
1618
1619         PMD_INIT_FUNC_TRACE();
1620
1621         /* Filter Table Enable */
1622         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1623         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1624         vlnctrl |= IXGBE_VLNCTRL_VFE;
1625
1626         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1627
1628         /* write whatever is in local vfta copy */
1629         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1630                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1631 }
1632
1633 static void
1634 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1635 {
1636         struct ixgbe_hwstrip *hwstrip =
1637                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1638
1639         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1640                 return;
1641
1642         if (on)
1643                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1644         else
1645                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1646 }
1647
1648 static void
1649 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1650 {
1651         struct ixgbe_hw *hw =
1652                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653         uint32_t ctrl;
1654
1655         PMD_INIT_FUNC_TRACE();
1656
1657         if (hw->mac.type == ixgbe_mac_82598EB) {
1658                 /* No queue level support */
1659                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1660                 return;
1661         }
1662         else {
1663                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1664                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1665                 ctrl &= ~IXGBE_RXDCTL_VME;
1666                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1667         }
1668         /* record those setting for HW strip per queue */
1669         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1670 }
1671
1672 static void
1673 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1674 {
1675         struct ixgbe_hw *hw =
1676                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         uint32_t ctrl;
1678
1679         PMD_INIT_FUNC_TRACE();
1680
1681         if (hw->mac.type == ixgbe_mac_82598EB) {
1682                 /* No queue level supported */
1683                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1684                 return;
1685         }
1686         else {
1687                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1688                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1689                 ctrl |= IXGBE_RXDCTL_VME;
1690                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1691         }
1692         /* record those setting for HW strip per queue */
1693         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1694 }
1695
1696 void
1697 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1698 {
1699         struct ixgbe_hw *hw =
1700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701         uint32_t ctrl;
1702         uint16_t i;
1703
1704         PMD_INIT_FUNC_TRACE();
1705
1706         if (hw->mac.type == ixgbe_mac_82598EB) {
1707                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1708                 ctrl &= ~IXGBE_VLNCTRL_VME;
1709                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1710         }
1711         else {
1712                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1713                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1714                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1715                         ctrl &= ~IXGBE_RXDCTL_VME;
1716                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1717
1718                         /* record those setting for HW strip per queue */
1719                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1720                 }
1721         }
1722 }
1723
1724 void
1725 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1726 {
1727         struct ixgbe_hw *hw =
1728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729         uint32_t ctrl;
1730         uint16_t i;
1731
1732         PMD_INIT_FUNC_TRACE();
1733
1734         if (hw->mac.type == ixgbe_mac_82598EB) {
1735                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1736                 ctrl |= IXGBE_VLNCTRL_VME;
1737                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1738         }
1739         else {
1740                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1741                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1742                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1743                         ctrl |= IXGBE_RXDCTL_VME;
1744                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1745
1746                         /* record those setting for HW strip per queue */
1747                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1748                 }
1749         }
1750 }
1751
1752 static void
1753 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1754 {
1755         struct ixgbe_hw *hw =
1756                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757         uint32_t ctrl;
1758
1759         PMD_INIT_FUNC_TRACE();
1760
1761         /* DMATXCTRL: Geric Double VLAN Disable */
1762         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1763         ctrl &= ~IXGBE_DMATXCTL_GDV;
1764         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1765
1766         /* CTRL_EXT: Global Double VLAN Disable */
1767         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1768         ctrl &= ~IXGBE_EXTENDED_VLAN;
1769         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1770
1771 }
1772
1773 static void
1774 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1775 {
1776         struct ixgbe_hw *hw =
1777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1778         uint32_t ctrl;
1779
1780         PMD_INIT_FUNC_TRACE();
1781
1782         /* DMATXCTRL: Geric Double VLAN Enable */
1783         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1784         ctrl |= IXGBE_DMATXCTL_GDV;
1785         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1786
1787         /* CTRL_EXT: Global Double VLAN Enable */
1788         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1789         ctrl |= IXGBE_EXTENDED_VLAN;
1790         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1791
1792         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1793         if (hw->mac.type == ixgbe_mac_X550 ||
1794             hw->mac.type == ixgbe_mac_X550EM_x) {
1795                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1796                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1797                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1798         }
1799
1800         /*
1801          * VET EXT field in the EXVET register = 0x8100 by default
1802          * So no need to change. Same to VT field of DMATXCTL register
1803          */
1804 }
1805
1806 static void
1807 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1808 {
1809         if (mask & ETH_VLAN_STRIP_MASK) {
1810                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1811                         ixgbe_vlan_hw_strip_enable_all(dev);
1812                 else
1813                         ixgbe_vlan_hw_strip_disable_all(dev);
1814         }
1815
1816         if (mask & ETH_VLAN_FILTER_MASK) {
1817                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1818                         ixgbe_vlan_hw_filter_enable(dev);
1819                 else
1820                         ixgbe_vlan_hw_filter_disable(dev);
1821         }
1822
1823         if (mask & ETH_VLAN_EXTEND_MASK) {
1824                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1825                         ixgbe_vlan_hw_extend_enable(dev);
1826                 else
1827                         ixgbe_vlan_hw_extend_disable(dev);
1828         }
1829 }
1830
1831 static void
1832 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1833 {
1834         struct ixgbe_hw *hw =
1835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1837         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1838         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1839         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1840 }
1841
1842 static int
1843 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1844 {
1845         switch (nb_rx_q) {
1846         case 1:
1847         case 2:
1848                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1849                 break;
1850         case 4:
1851                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1852                 break;
1853         default:
1854                 return -EINVAL;
1855         }
1856
1857         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1858         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1859
1860         return 0;
1861 }
1862
1863 static int
1864 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1865 {
1866         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1867         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1868         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1869
1870         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1871                 /* check multi-queue mode */
1872                 switch (dev_conf->rxmode.mq_mode) {
1873                 case ETH_MQ_RX_VMDQ_DCB:
1874                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1875                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1876                         PMD_INIT_LOG(ERR, "SRIOV active,"
1877                                         " unsupported mq_mode rx %d.",
1878                                         dev_conf->rxmode.mq_mode);
1879                         return -EINVAL;
1880                 case ETH_MQ_RX_RSS:
1881                 case ETH_MQ_RX_VMDQ_RSS:
1882                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1883                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1884                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1885                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1886                                                 " invalid queue number"
1887                                                 " for VMDQ RSS, allowed"
1888                                                 " value are 1, 2 or 4.");
1889                                         return -EINVAL;
1890                                 }
1891                         break;
1892                 case ETH_MQ_RX_VMDQ_ONLY:
1893                 case ETH_MQ_RX_NONE:
1894                         /* if nothing mq mode configure, use default scheme */
1895                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1896                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1897                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1898                         break;
1899                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1900                         /* SRIOV only works in VMDq enable mode */
1901                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1902                                         " wrong mq_mode rx %d.",
1903                                         dev_conf->rxmode.mq_mode);
1904                         return -EINVAL;
1905                 }
1906
1907                 switch (dev_conf->txmode.mq_mode) {
1908                 case ETH_MQ_TX_VMDQ_DCB:
1909                         /* DCB VMDQ in SRIOV mode, not implement yet */
1910                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1911                                         " unsupported VMDQ mq_mode tx %d.",
1912                                         dev_conf->txmode.mq_mode);
1913                         return -EINVAL;
1914                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1915                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1916                         break;
1917                 }
1918
1919                 /* check valid queue number */
1920                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1921                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1922                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1923                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1924                                         " must be less than or equal to %d.",
1925                                         nb_rx_q, nb_tx_q,
1926                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1927                         return -EINVAL;
1928                 }
1929         } else {
1930                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1931                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1932                                           " not supported.");
1933                         return -EINVAL;
1934                 }
1935                 /* check configuration for vmdb+dcb mode */
1936                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1937                         const struct rte_eth_vmdq_dcb_conf *conf;
1938
1939                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1940                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1941                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1942                                 return -EINVAL;
1943                         }
1944                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1945                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1946                                conf->nb_queue_pools == ETH_32_POOLS)) {
1947                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1948                                                 " nb_queue_pools must be %d or %d.",
1949                                                 ETH_16_POOLS, ETH_32_POOLS);
1950                                 return -EINVAL;
1951                         }
1952                 }
1953                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1954                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1955
1956                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1957                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1958                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1959                                 return -EINVAL;
1960                         }
1961                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1962                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1963                                conf->nb_queue_pools == ETH_32_POOLS)) {
1964                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1965                                                 " nb_queue_pools != %d and"
1966                                                 " nb_queue_pools != %d.",
1967                                                 ETH_16_POOLS, ETH_32_POOLS);
1968                                 return -EINVAL;
1969                         }
1970                 }
1971
1972                 /* For DCB mode check our configuration before we go further */
1973                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1974                         const struct rte_eth_dcb_rx_conf *conf;
1975
1976                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1977                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1978                                                  IXGBE_DCB_NB_QUEUES);
1979                                 return -EINVAL;
1980                         }
1981                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1982                         if (!(conf->nb_tcs == ETH_4_TCS ||
1983                                conf->nb_tcs == ETH_8_TCS)) {
1984                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1985                                                 " and nb_tcs != %d.",
1986                                                 ETH_4_TCS, ETH_8_TCS);
1987                                 return -EINVAL;
1988                         }
1989                 }
1990
1991                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1992                         const struct rte_eth_dcb_tx_conf *conf;
1993
1994                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1995                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1996                                                  IXGBE_DCB_NB_QUEUES);
1997                                 return -EINVAL;
1998                         }
1999                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2000                         if (!(conf->nb_tcs == ETH_4_TCS ||
2001                                conf->nb_tcs == ETH_8_TCS)) {
2002                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2003                                                 " and nb_tcs != %d.",
2004                                                 ETH_4_TCS, ETH_8_TCS);
2005                                 return -EINVAL;
2006                         }
2007                 }
2008         }
2009         return 0;
2010 }
2011
2012 static int
2013 ixgbe_dev_configure(struct rte_eth_dev *dev)
2014 {
2015         struct ixgbe_interrupt *intr =
2016                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2017         struct ixgbe_adapter *adapter =
2018                 (struct ixgbe_adapter *)dev->data->dev_private;
2019         int ret;
2020
2021         PMD_INIT_FUNC_TRACE();
2022         /* multipe queue mode checking */
2023         ret  = ixgbe_check_mq_mode(dev);
2024         if (ret != 0) {
2025                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2026                             ret);
2027                 return ret;
2028         }
2029
2030         /* set flag to update link status after init */
2031         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2032
2033         /*
2034          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2035          * allocation or vector Rx preconditions we will reset it.
2036          */
2037         adapter->rx_bulk_alloc_allowed = true;
2038         adapter->rx_vec_allowed = true;
2039
2040         return 0;
2041 }
2042
2043 static void
2044 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2045 {
2046         struct ixgbe_hw *hw =
2047                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048         struct ixgbe_interrupt *intr =
2049                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2050         uint32_t gpie;
2051
2052         /* only set up it on X550EM_X */
2053         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2054                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2055                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2056                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2057                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2058                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2059         }
2060 }
2061
2062 /*
2063  * Configure device link speed and setup link.
2064  * It returns 0 on success.
2065  */
2066 static int
2067 ixgbe_dev_start(struct rte_eth_dev *dev)
2068 {
2069         struct ixgbe_hw *hw =
2070                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2071         struct ixgbe_vf_info *vfinfo =
2072                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2073         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2074         uint32_t intr_vector = 0;
2075         int err, link_up = 0, negotiate = 0;
2076         uint32_t speed = 0;
2077         int mask = 0;
2078         int status;
2079         uint16_t vf, idx;
2080
2081         PMD_INIT_FUNC_TRACE();
2082
2083         /* IXGBE devices don't support half duplex */
2084         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2085                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2086                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2087                              dev->data->dev_conf.link_duplex,
2088                              dev->data->port_id);
2089                 return -EINVAL;
2090         }
2091
2092         /* disable uio/vfio intr/eventfd mapping */
2093         rte_intr_disable(intr_handle);
2094
2095         /* stop adapter */
2096         hw->adapter_stopped = 0;
2097         ixgbe_stop_adapter(hw);
2098
2099         /* reinitialize adapter
2100          * this calls reset and start */
2101         status = ixgbe_pf_reset_hw(hw);
2102         if (status != 0)
2103                 return -1;
2104         hw->mac.ops.start_hw(hw);
2105         hw->mac.get_link_status = true;
2106
2107         /* configure PF module if SRIOV enabled */
2108         ixgbe_pf_host_configure(dev);
2109
2110         ixgbe_dev_phy_intr_setup(dev);
2111
2112         /* check and configure queue intr-vector mapping */
2113         if ((rte_intr_cap_multiple(intr_handle) ||
2114              !RTE_ETH_DEV_SRIOV(dev).active) &&
2115             dev->data->dev_conf.intr_conf.rxq != 0) {
2116                 intr_vector = dev->data->nb_rx_queues;
2117                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2118                         return -1;
2119         }
2120
2121         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2122                 intr_handle->intr_vec =
2123                         rte_zmalloc("intr_vec",
2124                                     dev->data->nb_rx_queues * sizeof(int), 0);
2125                 if (intr_handle->intr_vec == NULL) {
2126                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2127                                      " intr_vec\n", dev->data->nb_rx_queues);
2128                         return -ENOMEM;
2129                 }
2130         }
2131
2132         /* confiugre msix for sleep until rx interrupt */
2133         ixgbe_configure_msix(dev);
2134
2135         /* initialize transmission unit */
2136         ixgbe_dev_tx_init(dev);
2137
2138         /* This can fail when allocating mbufs for descriptor rings */
2139         err = ixgbe_dev_rx_init(dev);
2140         if (err) {
2141                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2142                 goto error;
2143         }
2144
2145         err = ixgbe_dev_rxtx_start(dev);
2146         if (err < 0) {
2147                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2148                 goto error;
2149         }
2150
2151         /* Skip link setup if loopback mode is enabled for 82599. */
2152         if (hw->mac.type == ixgbe_mac_82599EB &&
2153                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2154                 goto skip_link_setup;
2155
2156         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2157                 err = hw->mac.ops.setup_sfp(hw);
2158                 if (err)
2159                         goto error;
2160         }
2161
2162         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2163                 /* Turn on the copper */
2164                 ixgbe_set_phy_power(hw, true);
2165         } else {
2166                 /* Turn on the laser */
2167                 ixgbe_enable_tx_laser(hw);
2168         }
2169
2170         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2171         if (err)
2172                 goto error;
2173         dev->data->dev_link.link_status = link_up;
2174
2175         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2176         if (err)
2177                 goto error;
2178
2179         switch(dev->data->dev_conf.link_speed) {
2180         case ETH_LINK_SPEED_AUTONEG:
2181                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2182                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2183                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2184                 break;
2185         case ETH_LINK_SPEED_100:
2186                 /*
2187                  * Invalid for 82598 but error will be detected by
2188                  * ixgbe_setup_link()
2189                  */
2190                 speed = IXGBE_LINK_SPEED_100_FULL;
2191                 break;
2192         case ETH_LINK_SPEED_1000:
2193                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2194                 break;
2195         case ETH_LINK_SPEED_10000:
2196                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2197                 break;
2198         default:
2199                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2200                              dev->data->dev_conf.link_speed,
2201                              dev->data->port_id);
2202                 goto error;
2203         }
2204
2205         err = ixgbe_setup_link(hw, speed, link_up);
2206         if (err)
2207                 goto error;
2208
2209 skip_link_setup:
2210
2211         if (rte_intr_allow_others(intr_handle)) {
2212                 /* check if lsc interrupt is enabled */
2213                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2214                         ixgbe_dev_lsc_interrupt_setup(dev);
2215         } else {
2216                 rte_intr_callback_unregister(intr_handle,
2217                                              ixgbe_dev_interrupt_handler,
2218                                              (void *)dev);
2219                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2220                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2221                                      " no intr multiplex\n");
2222         }
2223
2224         /* check if rxq interrupt is enabled */
2225         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2226             rte_intr_dp_is_en(intr_handle))
2227                 ixgbe_dev_rxq_interrupt_setup(dev);
2228
2229         /* enable uio/vfio intr/eventfd mapping */
2230         rte_intr_enable(intr_handle);
2231
2232         /* resume enabled intr since hw reset */
2233         ixgbe_enable_intr(dev);
2234
2235         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2236                 ETH_VLAN_EXTEND_MASK;
2237         ixgbe_vlan_offload_set(dev, mask);
2238
2239         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2240                 /* Enable vlan filtering for VMDq */
2241                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2242         }
2243
2244         /* Configure DCB hw */
2245         ixgbe_configure_dcb(dev);
2246
2247         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2248                 err = ixgbe_fdir_configure(dev);
2249                 if (err)
2250                         goto error;
2251         }
2252
2253         /* Restore vf rate limit */
2254         if (vfinfo != NULL) {
2255                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2256                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2257                                 if (vfinfo[vf].tx_rate[idx] != 0)
2258                                         ixgbe_set_vf_rate_limit(dev, vf,
2259                                                 vfinfo[vf].tx_rate[idx],
2260                                                 1 << idx);
2261         }
2262
2263         ixgbe_restore_statistics_mapping(dev);
2264
2265         return 0;
2266
2267 error:
2268         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2269         ixgbe_dev_clear_queues(dev);
2270         return -EIO;
2271 }
2272
2273 /*
2274  * Stop device: disable rx and tx functions to allow for reconfiguring.
2275  */
2276 static void
2277 ixgbe_dev_stop(struct rte_eth_dev *dev)
2278 {
2279         struct rte_eth_link link;
2280         struct ixgbe_hw *hw =
2281                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2282         struct ixgbe_vf_info *vfinfo =
2283                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2284         struct ixgbe_filter_info *filter_info =
2285                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2286         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2287         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2288         int vf;
2289
2290         PMD_INIT_FUNC_TRACE();
2291
2292         /* disable interrupts */
2293         ixgbe_disable_intr(hw);
2294
2295         /* reset the NIC */
2296         ixgbe_pf_reset_hw(hw);
2297         hw->adapter_stopped = 0;
2298
2299         /* stop adapter */
2300         ixgbe_stop_adapter(hw);
2301
2302         for (vf = 0; vfinfo != NULL &&
2303                      vf < dev->pci_dev->max_vfs; vf++)
2304                 vfinfo[vf].clear_to_send = false;
2305
2306         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2307                 /* Turn off the copper */
2308                 ixgbe_set_phy_power(hw, false);
2309         } else {
2310                 /* Turn off the laser */
2311                 ixgbe_disable_tx_laser(hw);
2312         }
2313
2314         ixgbe_dev_clear_queues(dev);
2315
2316         /* Clear stored conf */
2317         dev->data->scattered_rx = 0;
2318         dev->data->lro = 0;
2319
2320         /* Clear recorded link status */
2321         memset(&link, 0, sizeof(link));
2322         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2323
2324         /* Remove all ntuple filters of the device */
2325         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2326              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2327                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2328                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2329                              p_5tuple, entries);
2330                 rte_free(p_5tuple);
2331         }
2332         memset(filter_info->fivetuple_mask, 0,
2333                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2334
2335         if (!rte_intr_allow_others(intr_handle))
2336                 /* resume to the default handler */
2337                 rte_intr_callback_register(intr_handle,
2338                                            ixgbe_dev_interrupt_handler,
2339                                            (void *)dev);
2340
2341         /* Clean datapath event and queue/vec mapping */
2342         rte_intr_efd_disable(intr_handle);
2343         if (intr_handle->intr_vec != NULL) {
2344                 rte_free(intr_handle->intr_vec);
2345                 intr_handle->intr_vec = NULL;
2346         }
2347 }
2348
2349 /*
2350  * Set device link up: enable tx.
2351  */
2352 static int
2353 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2354 {
2355         struct ixgbe_hw *hw =
2356                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2357         if (hw->mac.type == ixgbe_mac_82599EB) {
2358 #ifdef RTE_NIC_BYPASS
2359                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2360                         /* Not suported in bypass mode */
2361                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2362                                      "by device id 0x%x", hw->device_id);
2363                         return -ENOTSUP;
2364                 }
2365 #endif
2366         }
2367
2368         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2369                 /* Turn on the copper */
2370                 ixgbe_set_phy_power(hw, true);
2371         } else {
2372                 /* Turn on the laser */
2373                 ixgbe_enable_tx_laser(hw);
2374         }
2375
2376         return 0;
2377 }
2378
2379 /*
2380  * Set device link down: disable tx.
2381  */
2382 static int
2383 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2384 {
2385         struct ixgbe_hw *hw =
2386                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387         if (hw->mac.type == ixgbe_mac_82599EB) {
2388 #ifdef RTE_NIC_BYPASS
2389                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2390                         /* Not suported in bypass mode */
2391                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2392                                      "by device id 0x%x", hw->device_id);
2393                         return -ENOTSUP;
2394                 }
2395 #endif
2396         }
2397
2398         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2399                 /* Turn off the copper */
2400                 ixgbe_set_phy_power(hw, false);
2401         } else {
2402                 /* Turn off the laser */
2403                 ixgbe_disable_tx_laser(hw);
2404         }
2405
2406         return 0;
2407 }
2408
2409 /*
2410  * Reest and stop device.
2411  */
2412 static void
2413 ixgbe_dev_close(struct rte_eth_dev *dev)
2414 {
2415         struct ixgbe_hw *hw =
2416                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2417
2418         PMD_INIT_FUNC_TRACE();
2419
2420         ixgbe_pf_reset_hw(hw);
2421
2422         ixgbe_dev_stop(dev);
2423         hw->adapter_stopped = 1;
2424
2425         ixgbe_dev_free_queues(dev);
2426
2427         ixgbe_disable_pcie_master(hw);
2428
2429         /* reprogram the RAR[0] in case user changed it. */
2430         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2431 }
2432
2433 static void
2434 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2435                            struct ixgbe_hw_stats *hw_stats,
2436                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2437                            uint64_t *total_qprc, uint64_t *total_qprdc)
2438 {
2439         uint32_t bprc, lxon, lxoff, total;
2440         uint32_t delta_gprc = 0;
2441         unsigned i;
2442         /* Workaround for RX byte count not including CRC bytes when CRC
2443 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2444          * is disabled.
2445 +        */
2446         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2447                         IXGBE_HLREG0_RXCRCSTRP);
2448
2449         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2450         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2451         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2452         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2453
2454         for (i = 0; i < 8; i++) {
2455                 uint32_t mp;
2456                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2457                 /* global total per queue */
2458                 hw_stats->mpc[i] += mp;
2459                 /* Running comprehensive total for stats display */
2460                 *total_missed_rx += hw_stats->mpc[i];
2461                 if (hw->mac.type == ixgbe_mac_82598EB) {
2462                         hw_stats->rnbc[i] +=
2463                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2464                         hw_stats->pxonrxc[i] +=
2465                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2466                         hw_stats->pxoffrxc[i] +=
2467                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2468                 } else {
2469                         hw_stats->pxonrxc[i] +=
2470                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2471                         hw_stats->pxoffrxc[i] +=
2472                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2473                         hw_stats->pxon2offc[i] +=
2474                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2475                 }
2476                 hw_stats->pxontxc[i] +=
2477                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2478                 hw_stats->pxofftxc[i] +=
2479                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2480         }
2481         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2482                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2483                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2484                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2485
2486                 delta_gprc += delta_qprc;
2487
2488                 hw_stats->qprc[i] += delta_qprc;
2489                 hw_stats->qptc[i] += delta_qptc;
2490
2491                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2492                 hw_stats->qbrc[i] +=
2493                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2494                 if (crc_strip == 0)
2495                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2496
2497                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2498                 hw_stats->qbtc[i] +=
2499                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2500
2501                 hw_stats->qprdc[i] += delta_qprdc;
2502                 *total_qprdc += hw_stats->qprdc[i];
2503
2504                 *total_qprc += hw_stats->qprc[i];
2505                 *total_qbrc += hw_stats->qbrc[i];
2506         }
2507         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2508         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2509         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2510
2511         /*
2512          * An errata states that gprc actually counts good + missed packets:
2513          * Workaround to set gprc to summated queue packet receives
2514          */
2515         hw_stats->gprc = *total_qprc;
2516
2517         if (hw->mac.type != ixgbe_mac_82598EB) {
2518                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2519                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2520                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2521                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2522                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2523                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2524                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2525                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2526         } else {
2527                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2528                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2529                 /* 82598 only has a counter in the high register */
2530                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2531                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2532                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2533         }
2534         uint64_t old_tpr = hw_stats->tpr;
2535
2536         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2537         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2538
2539         if (crc_strip == 0)
2540                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2541
2542         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2543         hw_stats->gptc += delta_gptc;
2544         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2545         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2546
2547         /*
2548          * Workaround: mprc hardware is incorrectly counting
2549          * broadcasts, so for now we subtract those.
2550          */
2551         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2552         hw_stats->bprc += bprc;
2553         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2554         if (hw->mac.type == ixgbe_mac_82598EB)
2555                 hw_stats->mprc -= bprc;
2556
2557         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2558         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2559         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2560         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2561         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2562         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2563
2564         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2565         hw_stats->lxontxc += lxon;
2566         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2567         hw_stats->lxofftxc += lxoff;
2568         total = lxon + lxoff;
2569
2570         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2571         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2572         hw_stats->gptc -= total;
2573         hw_stats->mptc -= total;
2574         hw_stats->ptc64 -= total;
2575         hw_stats->gotc -= total * ETHER_MIN_LEN;
2576
2577         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2578         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2579         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2580         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2581         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2582         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2583         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2584         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2585         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2586         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2587         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2588         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2589         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2590         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2591         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2592         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2593         /* Only read FCOE on 82599 */
2594         if (hw->mac.type != ixgbe_mac_82598EB) {
2595                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2596                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2597                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2598                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2599                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2600         }
2601
2602         /* Flow Director Stats registers */
2603         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2604         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2605 }
2606
2607 /*
2608  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2609  */
2610 static void
2611 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2612 {
2613         struct ixgbe_hw *hw =
2614                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615         struct ixgbe_hw_stats *hw_stats =
2616                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2617         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2618         unsigned i;
2619
2620         total_missed_rx = 0;
2621         total_qbrc = 0;
2622         total_qprc = 0;
2623         total_qprdc = 0;
2624
2625         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2626                         &total_qprc, &total_qprdc);
2627
2628         if (stats == NULL)
2629                 return;
2630
2631         /* Fill out the rte_eth_stats statistics structure */
2632         stats->ipackets = total_qprc;
2633         stats->ibytes = total_qbrc;
2634         stats->opackets = hw_stats->gptc;
2635         stats->obytes = hw_stats->gotc;
2636
2637         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2638                 stats->q_ipackets[i] = hw_stats->qprc[i];
2639                 stats->q_opackets[i] = hw_stats->qptc[i];
2640                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2641                 stats->q_obytes[i] = hw_stats->qbtc[i];
2642                 stats->q_errors[i] = hw_stats->qprdc[i];
2643         }
2644
2645         /* Rx Errors */
2646         stats->imissed  = total_missed_rx;
2647         stats->ierrors  = hw_stats->crcerrs +
2648                           hw_stats->mspdc +
2649                           hw_stats->rlec +
2650                           hw_stats->ruc +
2651                           hw_stats->roc +
2652                           hw_stats->illerrc +
2653                           hw_stats->errbc +
2654                           hw_stats->rfc +
2655                           hw_stats->fccrc +
2656                           hw_stats->fclast;
2657
2658         /* Tx Errors */
2659         stats->oerrors  = 0;
2660 }
2661
2662 static void
2663 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2664 {
2665         struct ixgbe_hw_stats *stats =
2666                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2667
2668         /* HW registers are cleared on read */
2669         ixgbe_dev_stats_get(dev, NULL);
2670
2671         /* Reset software totals */
2672         memset(stats, 0, sizeof(*stats));
2673 }
2674
2675 /* This function calculates the number of xstats based on the current config */
2676 static unsigned
2677 ixgbe_xstats_calc_num(void) {
2678         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2679                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2680 }
2681
2682 static int
2683 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2684                                          unsigned n)
2685 {
2686         struct ixgbe_hw *hw =
2687                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688         struct ixgbe_hw_stats *hw_stats =
2689                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2690         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2691         unsigned i, stat, count = 0;
2692
2693         count = ixgbe_xstats_calc_num();
2694
2695         if (n < count)
2696                 return count;
2697
2698         total_missed_rx = 0;
2699         total_qbrc = 0;
2700         total_qprc = 0;
2701         total_qprdc = 0;
2702
2703         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2704                                    &total_qprc, &total_qprdc);
2705
2706         /* If this is a reset xstats is NULL, and we have cleared the
2707          * registers by reading them.
2708          */
2709         if (!xstats)
2710                 return 0;
2711
2712         /* Extended stats from ixgbe_hw_stats */
2713         count = 0;
2714         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2715                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2716                          rte_ixgbe_stats_strings[i].name);
2717                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2718                                 rte_ixgbe_stats_strings[i].offset);
2719                 count++;
2720         }
2721
2722         /* RX Priority Stats */
2723         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2724                 for (i = 0; i < 8; i++) {
2725                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2726                                  "rx_priority%u_%s", i,
2727                                  rte_ixgbe_rxq_strings[stat].name);
2728                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2729                                         rte_ixgbe_rxq_strings[stat].offset +
2730                                         (sizeof(uint64_t) * i));
2731                         count++;
2732                 }
2733         }
2734
2735         /* TX Priority Stats */
2736         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2737                 for (i = 0; i < 8; i++) {
2738                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2739                                  "tx_priority%u_%s", i,
2740                                  rte_ixgbe_txq_strings[stat].name);
2741                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2742                                         rte_ixgbe_txq_strings[stat].offset +
2743                                         (sizeof(uint64_t) * i));
2744                         count++;
2745                 }
2746         }
2747
2748         return count;
2749 }
2750
2751 static void
2752 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2753 {
2754         struct ixgbe_hw_stats *stats =
2755                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2756
2757         unsigned count = ixgbe_xstats_calc_num();
2758
2759         /* HW registers are cleared on read */
2760         ixgbe_dev_xstats_get(dev, NULL, count);
2761
2762         /* Reset software totals */
2763         memset(stats, 0, sizeof(*stats));
2764 }
2765
2766 static void
2767 ixgbevf_update_stats(struct rte_eth_dev *dev)
2768 {
2769         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2770         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2771                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2772
2773         /* Good Rx packet, include VF loopback */
2774         UPDATE_VF_STAT(IXGBE_VFGPRC,
2775             hw_stats->last_vfgprc, hw_stats->vfgprc);
2776
2777         /* Good Rx octets, include VF loopback */
2778         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2779             hw_stats->last_vfgorc, hw_stats->vfgorc);
2780
2781         /* Good Tx packet, include VF loopback */
2782         UPDATE_VF_STAT(IXGBE_VFGPTC,
2783             hw_stats->last_vfgptc, hw_stats->vfgptc);
2784
2785         /* Good Tx octets, include VF loopback */
2786         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2787             hw_stats->last_vfgotc, hw_stats->vfgotc);
2788
2789         /* Rx Multicst Packet */
2790         UPDATE_VF_STAT(IXGBE_VFMPRC,
2791             hw_stats->last_vfmprc, hw_stats->vfmprc);
2792 }
2793
2794 static int
2795 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2796                        unsigned n)
2797 {
2798         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2799                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2800         unsigned i;
2801
2802         if (n < IXGBEVF_NB_XSTATS)
2803                 return IXGBEVF_NB_XSTATS;
2804
2805         ixgbevf_update_stats(dev);
2806
2807         if (!xstats)
2808                 return 0;
2809
2810         /* Extended stats */
2811         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2812                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2813                          "%s", rte_ixgbevf_stats_strings[i].name);
2814                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2815                         rte_ixgbevf_stats_strings[i].offset);
2816         }
2817
2818         return IXGBEVF_NB_XSTATS;
2819 }
2820
2821 static void
2822 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2823 {
2824         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2825                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2826
2827         ixgbevf_update_stats(dev);
2828
2829         if (stats == NULL)
2830                 return;
2831
2832         stats->ipackets = hw_stats->vfgprc;
2833         stats->ibytes = hw_stats->vfgorc;
2834         stats->opackets = hw_stats->vfgptc;
2835         stats->obytes = hw_stats->vfgotc;
2836         stats->imcasts = hw_stats->vfmprc;
2837         /* stats->imcasts should be removed as imcasts is deprecated */
2838 }
2839
2840 static void
2841 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2842 {
2843         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2844                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2845
2846         /* Sync HW register to the last stats */
2847         ixgbevf_dev_stats_get(dev, NULL);
2848
2849         /* reset HW current stats*/
2850         hw_stats->vfgprc = 0;
2851         hw_stats->vfgorc = 0;
2852         hw_stats->vfgptc = 0;
2853         hw_stats->vfgotc = 0;
2854         hw_stats->vfmprc = 0;
2855
2856 }
2857
2858 static void
2859 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2860 {
2861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862
2863         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2864         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2865         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2866         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2867         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2868         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2869         dev_info->max_vfs = dev->pci_dev->max_vfs;
2870         if (hw->mac.type == ixgbe_mac_82598EB)
2871                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2872         else
2873                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2874         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2875         dev_info->rx_offload_capa =
2876                 DEV_RX_OFFLOAD_VLAN_STRIP |
2877                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2878                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2879                 DEV_RX_OFFLOAD_TCP_CKSUM;
2880
2881         /*
2882          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2883          * mode.
2884          */
2885         if ((hw->mac.type == ixgbe_mac_82599EB ||
2886              hw->mac.type == ixgbe_mac_X540) &&
2887             !RTE_ETH_DEV_SRIOV(dev).active)
2888                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2889
2890         if (hw->mac.type == ixgbe_mac_X550 ||
2891             hw->mac.type == ixgbe_mac_X550EM_x)
2892                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2893
2894         dev_info->tx_offload_capa =
2895                 DEV_TX_OFFLOAD_VLAN_INSERT |
2896                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2897                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2898                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2899                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2900                 DEV_TX_OFFLOAD_TCP_TSO;
2901
2902         if (hw->mac.type == ixgbe_mac_X550 ||
2903             hw->mac.type == ixgbe_mac_X550EM_x)
2904                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2905
2906         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2907                 .rx_thresh = {
2908                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2909                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2910                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2911                 },
2912                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2913                 .rx_drop_en = 0,
2914         };
2915
2916         dev_info->default_txconf = (struct rte_eth_txconf) {
2917                 .tx_thresh = {
2918                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2919                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2920                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2921                 },
2922                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2923                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2924                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2925                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2926         };
2927
2928         dev_info->rx_desc_lim = rx_desc_lim;
2929         dev_info->tx_desc_lim = tx_desc_lim;
2930
2931         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2932         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2933         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2934 }
2935
2936 static const uint32_t *
2937 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2938 {
2939         static const uint32_t ptypes[] = {
2940                 /* For non-vec functions,
2941                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
2942                  * for vec functions,
2943                  * refers to _recv_raw_pkts_vec().
2944                  */
2945                 RTE_PTYPE_L2_ETHER,
2946                 RTE_PTYPE_L3_IPV4,
2947                 RTE_PTYPE_L3_IPV4_EXT,
2948                 RTE_PTYPE_L3_IPV6,
2949                 RTE_PTYPE_L3_IPV6_EXT,
2950                 RTE_PTYPE_L4_SCTP,
2951                 RTE_PTYPE_L4_TCP,
2952                 RTE_PTYPE_L4_UDP,
2953                 RTE_PTYPE_TUNNEL_IP,
2954                 RTE_PTYPE_INNER_L3_IPV6,
2955                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2956                 RTE_PTYPE_INNER_L4_TCP,
2957                 RTE_PTYPE_INNER_L4_UDP,
2958                 RTE_PTYPE_UNKNOWN
2959         };
2960
2961         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
2962             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
2963             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
2964             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc ||
2965             dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
2966             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
2967                 return ptypes;
2968         return NULL;
2969 }
2970
2971 static void
2972 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2973                      struct rte_eth_dev_info *dev_info)
2974 {
2975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2976
2977         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2978         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2979         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2980         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2981         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2982         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2983         dev_info->max_vfs = dev->pci_dev->max_vfs;
2984         if (hw->mac.type == ixgbe_mac_82598EB)
2985                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2986         else
2987                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2988         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2989                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2990                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2991                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2992         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2993                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2994                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2995                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2996                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2997                                 DEV_TX_OFFLOAD_TCP_TSO;
2998
2999         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3000                 .rx_thresh = {
3001                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3002                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3003                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3004                 },
3005                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3006                 .rx_drop_en = 0,
3007         };
3008
3009         dev_info->default_txconf = (struct rte_eth_txconf) {
3010                 .tx_thresh = {
3011                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3012                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3013                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3014                 },
3015                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3016                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3017                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3018                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3019         };
3020
3021         dev_info->rx_desc_lim = rx_desc_lim;
3022         dev_info->tx_desc_lim = tx_desc_lim;
3023 }
3024
3025 /* return 0 means link status changed, -1 means not changed */
3026 static int
3027 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3028 {
3029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030         struct rte_eth_link link, old;
3031         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3032         int link_up;
3033         int diag;
3034
3035         link.link_status = 0;
3036         link.link_speed = 0;
3037         link.link_duplex = 0;
3038         memset(&old, 0, sizeof(old));
3039         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3040
3041         hw->mac.get_link_status = true;
3042
3043         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3044         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3045                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3046         else
3047                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3048
3049         if (diag != 0) {
3050                 link.link_speed = ETH_LINK_SPEED_100;
3051                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3052                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3053                 if (link.link_status == old.link_status)
3054                         return -1;
3055                 return 0;
3056         }
3057
3058         if (link_up == 0) {
3059                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3060                 if (link.link_status == old.link_status)
3061                         return -1;
3062                 return 0;
3063         }
3064         link.link_status = 1;
3065         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3066
3067         switch (link_speed) {
3068         default:
3069         case IXGBE_LINK_SPEED_UNKNOWN:
3070                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3071                 link.link_speed = ETH_LINK_SPEED_100;
3072                 break;
3073
3074         case IXGBE_LINK_SPEED_100_FULL:
3075                 link.link_speed = ETH_LINK_SPEED_100;
3076                 break;
3077
3078         case IXGBE_LINK_SPEED_1GB_FULL:
3079                 link.link_speed = ETH_LINK_SPEED_1000;
3080                 break;
3081
3082         case IXGBE_LINK_SPEED_10GB_FULL:
3083                 link.link_speed = ETH_LINK_SPEED_10000;
3084                 break;
3085         }
3086         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3087
3088         if (link.link_status == old.link_status)
3089                 return -1;
3090
3091         return 0;
3092 }
3093
3094 static void
3095 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3096 {
3097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3098         uint32_t fctrl;
3099
3100         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3101         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3102         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3103 }
3104
3105 static void
3106 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3107 {
3108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3109         uint32_t fctrl;
3110
3111         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3112         fctrl &= (~IXGBE_FCTRL_UPE);
3113         if (dev->data->all_multicast == 1)
3114                 fctrl |= IXGBE_FCTRL_MPE;
3115         else
3116                 fctrl &= (~IXGBE_FCTRL_MPE);
3117         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3118 }
3119
3120 static void
3121 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3122 {
3123         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124         uint32_t fctrl;
3125
3126         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3127         fctrl |= IXGBE_FCTRL_MPE;
3128         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3129 }
3130
3131 static void
3132 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3133 {
3134         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135         uint32_t fctrl;
3136
3137         if (dev->data->promiscuous == 1)
3138                 return; /* must remain in all_multicast mode */
3139
3140         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3141         fctrl &= (~IXGBE_FCTRL_MPE);
3142         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3143 }
3144
3145 /**
3146  * It clears the interrupt causes and enables the interrupt.
3147  * It will be called once only during nic initialized.
3148  *
3149  * @param dev
3150  *  Pointer to struct rte_eth_dev.
3151  *
3152  * @return
3153  *  - On success, zero.
3154  *  - On failure, a negative value.
3155  */
3156 static int
3157 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3158 {
3159         struct ixgbe_interrupt *intr =
3160                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3161
3162         ixgbe_dev_link_status_print(dev);
3163         intr->mask |= IXGBE_EICR_LSC;
3164
3165         return 0;
3166 }
3167
3168 /**
3169  * It clears the interrupt causes and enables the interrupt.
3170  * It will be called once only during nic initialized.
3171  *
3172  * @param dev
3173  *  Pointer to struct rte_eth_dev.
3174  *
3175  * @return
3176  *  - On success, zero.
3177  *  - On failure, a negative value.
3178  */
3179 static int
3180 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3181 {
3182         struct ixgbe_interrupt *intr =
3183                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3184
3185         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3186
3187         return 0;
3188 }
3189
3190 /*
3191  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3192  *
3193  * @param dev
3194  *  Pointer to struct rte_eth_dev.
3195  *
3196  * @return
3197  *  - On success, zero.
3198  *  - On failure, a negative value.
3199  */
3200 static int
3201 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3202 {
3203         uint32_t eicr;
3204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3205         struct ixgbe_interrupt *intr =
3206                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3207
3208         /* clear all cause mask */
3209         ixgbe_disable_intr(hw);
3210
3211         /* read-on-clear nic registers here */
3212         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3213         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3214
3215         intr->flags = 0;
3216
3217         /* set flag for async link update */
3218         if (eicr & IXGBE_EICR_LSC)
3219                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3220
3221         if (eicr & IXGBE_EICR_MAILBOX)
3222                 intr->flags |= IXGBE_FLAG_MAILBOX;
3223
3224         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3225             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3226             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3227                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3228
3229         return 0;
3230 }
3231
3232 /**
3233  * It gets and then prints the link status.
3234  *
3235  * @param dev
3236  *  Pointer to struct rte_eth_dev.
3237  *
3238  * @return
3239  *  - On success, zero.
3240  *  - On failure, a negative value.
3241  */
3242 static void
3243 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3244 {
3245         struct rte_eth_link link;
3246
3247         memset(&link, 0, sizeof(link));
3248         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3249         if (link.link_status) {
3250                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3251                                         (int)(dev->data->port_id),
3252                                         (unsigned)link.link_speed,
3253                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3254                                         "full-duplex" : "half-duplex");
3255         } else {
3256                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3257                                 (int)(dev->data->port_id));
3258         }
3259         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3260                                 dev->pci_dev->addr.domain,
3261                                 dev->pci_dev->addr.bus,
3262                                 dev->pci_dev->addr.devid,
3263                                 dev->pci_dev->addr.function);
3264 }
3265
3266 /*
3267  * It executes link_update after knowing an interrupt occurred.
3268  *
3269  * @param dev
3270  *  Pointer to struct rte_eth_dev.
3271  *
3272  * @return
3273  *  - On success, zero.
3274  *  - On failure, a negative value.
3275  */
3276 static int
3277 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3278 {
3279         struct ixgbe_interrupt *intr =
3280                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3281         int64_t timeout;
3282         struct rte_eth_link link;
3283         int intr_enable_delay = false;
3284         struct ixgbe_hw *hw =
3285                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3286
3287         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3288
3289         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3290                 ixgbe_pf_mbx_process(dev);
3291                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3292         }
3293
3294         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3295                 ixgbe_handle_lasi(hw);
3296                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3297         }
3298
3299         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3300                 /* get the link status before link update, for predicting later */
3301                 memset(&link, 0, sizeof(link));
3302                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3303
3304                 ixgbe_dev_link_update(dev, 0);
3305
3306                 /* likely to up */
3307                 if (!link.link_status)
3308                         /* handle it 1 sec later, wait it being stable */
3309                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3310                 /* likely to down */
3311                 else
3312                         /* handle it 4 sec later, wait it being stable */
3313                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3314
3315                 ixgbe_dev_link_status_print(dev);
3316
3317                 intr_enable_delay = true;
3318         }
3319
3320         if (intr_enable_delay) {
3321                 if (rte_eal_alarm_set(timeout * 1000,
3322                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3323                         PMD_DRV_LOG(ERR, "Error setting alarm");
3324         } else {
3325                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3326                 ixgbe_enable_intr(dev);
3327                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3328         }
3329
3330
3331         return 0;
3332 }
3333
3334 /**
3335  * Interrupt handler which shall be registered for alarm callback for delayed
3336  * handling specific interrupt to wait for the stable nic state. As the
3337  * NIC interrupt state is not stable for ixgbe after link is just down,
3338  * it needs to wait 4 seconds to get the stable status.
3339  *
3340  * @param handle
3341  *  Pointer to interrupt handle.
3342  * @param param
3343  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3344  *
3345  * @return
3346  *  void
3347  */
3348 static void
3349 ixgbe_dev_interrupt_delayed_handler(void *param)
3350 {
3351         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3352         struct ixgbe_interrupt *intr =
3353                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3354         struct ixgbe_hw *hw =
3355                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3356         uint32_t eicr;
3357
3358         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3359         if (eicr & IXGBE_EICR_MAILBOX)
3360                 ixgbe_pf_mbx_process(dev);
3361
3362         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3363                 ixgbe_handle_lasi(hw);
3364                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3365         }
3366
3367         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3368                 ixgbe_dev_link_update(dev, 0);
3369                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3370                 ixgbe_dev_link_status_print(dev);
3371                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3372         }
3373
3374         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3375         ixgbe_enable_intr(dev);
3376         rte_intr_enable(&(dev->pci_dev->intr_handle));
3377 }
3378
3379 /**
3380  * Interrupt handler triggered by NIC  for handling
3381  * specific interrupt.
3382  *
3383  * @param handle
3384  *  Pointer to interrupt handle.
3385  * @param param
3386  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3387  *
3388  * @return
3389  *  void
3390  */
3391 static void
3392 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3393                             void *param)
3394 {
3395         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3396
3397         ixgbe_dev_interrupt_get_status(dev);
3398         ixgbe_dev_interrupt_action(dev);
3399 }
3400
3401 static int
3402 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3403 {
3404         struct ixgbe_hw *hw;
3405
3406         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3407         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3408 }
3409
3410 static int
3411 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3412 {
3413         struct ixgbe_hw *hw;
3414
3415         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3416         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3417 }
3418
3419 static int
3420 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3421 {
3422         struct ixgbe_hw *hw;
3423         uint32_t mflcn_reg;
3424         uint32_t fccfg_reg;
3425         int rx_pause;
3426         int tx_pause;
3427
3428         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3429
3430         fc_conf->pause_time = hw->fc.pause_time;
3431         fc_conf->high_water = hw->fc.high_water[0];
3432         fc_conf->low_water = hw->fc.low_water[0];
3433         fc_conf->send_xon = hw->fc.send_xon;
3434         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3435
3436         /*
3437          * Return rx_pause status according to actual setting of
3438          * MFLCN register.
3439          */
3440         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3441         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3442                 rx_pause = 1;
3443         else
3444                 rx_pause = 0;
3445
3446         /*
3447          * Return tx_pause status according to actual setting of
3448          * FCCFG register.
3449          */
3450         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3451         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3452                 tx_pause = 1;
3453         else
3454                 tx_pause = 0;
3455
3456         if (rx_pause && tx_pause)
3457                 fc_conf->mode = RTE_FC_FULL;
3458         else if (rx_pause)
3459                 fc_conf->mode = RTE_FC_RX_PAUSE;
3460         else if (tx_pause)
3461                 fc_conf->mode = RTE_FC_TX_PAUSE;
3462         else
3463                 fc_conf->mode = RTE_FC_NONE;
3464
3465         return 0;
3466 }
3467
3468 static int
3469 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3470 {
3471         struct ixgbe_hw *hw;
3472         int err;
3473         uint32_t rx_buf_size;
3474         uint32_t max_high_water;
3475         uint32_t mflcn;
3476         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3477                 ixgbe_fc_none,
3478                 ixgbe_fc_rx_pause,
3479                 ixgbe_fc_tx_pause,
3480                 ixgbe_fc_full
3481         };
3482
3483         PMD_INIT_FUNC_TRACE();
3484
3485         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3487         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3488
3489         /*
3490          * At least reserve one Ethernet frame for watermark
3491          * high_water/low_water in kilo bytes for ixgbe
3492          */
3493         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3494         if ((fc_conf->high_water > max_high_water) ||
3495                 (fc_conf->high_water < fc_conf->low_water)) {
3496                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3497                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3498                 return -EINVAL;
3499         }
3500
3501         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3502         hw->fc.pause_time     = fc_conf->pause_time;
3503         hw->fc.high_water[0]  = fc_conf->high_water;
3504         hw->fc.low_water[0]   = fc_conf->low_water;
3505         hw->fc.send_xon       = fc_conf->send_xon;
3506         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3507
3508         err = ixgbe_fc_enable(hw);
3509
3510         /* Not negotiated is not an error case */
3511         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3512
3513                 /* check if we want to forward MAC frames - driver doesn't have native
3514                  * capability to do that, so we'll write the registers ourselves */
3515
3516                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3517
3518                 /* set or clear MFLCN.PMCF bit depending on configuration */
3519                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3520                         mflcn |= IXGBE_MFLCN_PMCF;
3521                 else
3522                         mflcn &= ~IXGBE_MFLCN_PMCF;
3523
3524                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3525                 IXGBE_WRITE_FLUSH(hw);
3526
3527                 return 0;
3528         }
3529
3530         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3531         return -EIO;
3532 }
3533
3534 /**
3535  *  ixgbe_pfc_enable_generic - Enable flow control
3536  *  @hw: pointer to hardware structure
3537  *  @tc_num: traffic class number
3538  *  Enable flow control according to the current settings.
3539  */
3540 static int
3541 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3542 {
3543         int ret_val = 0;
3544         uint32_t mflcn_reg, fccfg_reg;
3545         uint32_t reg;
3546         uint32_t fcrtl, fcrth;
3547         uint8_t i;
3548         uint8_t nb_rx_en;
3549
3550         /* Validate the water mark configuration */
3551         if (!hw->fc.pause_time) {
3552                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3553                 goto out;
3554         }
3555
3556         /* Low water mark of zero causes XOFF floods */
3557         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3558                  /* High/Low water can not be 0 */
3559                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3560                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3561                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3562                         goto out;
3563                 }
3564
3565                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3566                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3567                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3568                         goto out;
3569                 }
3570         }
3571         /* Negotiate the fc mode to use */
3572         ixgbe_fc_autoneg(hw);
3573
3574         /* Disable any previous flow control settings */
3575         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3576         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3577
3578         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3579         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3580
3581         switch (hw->fc.current_mode) {
3582         case ixgbe_fc_none:
3583                 /*
3584                  * If the count of enabled RX Priority Flow control >1,
3585                  * and the TX pause can not be disabled
3586                  */
3587                 nb_rx_en = 0;
3588                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3589                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3590                         if (reg & IXGBE_FCRTH_FCEN)
3591                                 nb_rx_en++;
3592                 }
3593                 if (nb_rx_en > 1)
3594                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3595                 break;
3596         case ixgbe_fc_rx_pause:
3597                 /*
3598                  * Rx Flow control is enabled and Tx Flow control is
3599                  * disabled by software override. Since there really
3600                  * isn't a way to advertise that we are capable of RX
3601                  * Pause ONLY, we will advertise that we support both
3602                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3603                  * disable the adapter's ability to send PAUSE frames.
3604                  */
3605                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3606                 /*
3607                  * If the count of enabled RX Priority Flow control >1,
3608                  * and the TX pause can not be disabled
3609                  */
3610                 nb_rx_en = 0;
3611                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3612                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3613                         if (reg & IXGBE_FCRTH_FCEN)
3614                                 nb_rx_en++;
3615                 }
3616                 if (nb_rx_en > 1)
3617                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3618                 break;
3619         case ixgbe_fc_tx_pause:
3620                 /*
3621                  * Tx Flow control is enabled, and Rx Flow control is
3622                  * disabled by software override.
3623                  */
3624                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3625                 break;
3626         case ixgbe_fc_full:
3627                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3628                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3629                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3630                 break;
3631         default:
3632                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3633                 ret_val = IXGBE_ERR_CONFIG;
3634                 goto out;
3635                 break;
3636         }
3637
3638         /* Set 802.3x based flow control settings. */
3639         mflcn_reg |= IXGBE_MFLCN_DPF;
3640         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3641         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3642
3643         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3644         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3645                 hw->fc.high_water[tc_num]) {
3646                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3647                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3648                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3649         } else {
3650                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3651                 /*
3652                  * In order to prevent Tx hangs when the internal Tx
3653                  * switch is enabled we must set the high water mark
3654                  * to the maximum FCRTH value.  This allows the Tx
3655                  * switch to function even under heavy Rx workloads.
3656                  */
3657                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3658         }
3659         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3660
3661         /* Configure pause time (2 TCs per register) */
3662         reg = hw->fc.pause_time * 0x00010001;
3663         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3664                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3665
3666         /* Configure flow control refresh threshold value */
3667         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3668
3669 out:
3670         return ret_val;
3671 }
3672
3673 static int
3674 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3675 {
3676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3677         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3678
3679         if (hw->mac.type != ixgbe_mac_82598EB) {
3680                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3681         }
3682         return ret_val;
3683 }
3684
3685 static int
3686 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3687 {
3688         int err;
3689         uint32_t rx_buf_size;
3690         uint32_t max_high_water;
3691         uint8_t tc_num;
3692         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3693         struct ixgbe_hw *hw =
3694                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3695         struct ixgbe_dcb_config *dcb_config =
3696                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3697
3698         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3699                 ixgbe_fc_none,
3700                 ixgbe_fc_rx_pause,
3701                 ixgbe_fc_tx_pause,
3702                 ixgbe_fc_full
3703         };
3704
3705         PMD_INIT_FUNC_TRACE();
3706
3707         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3708         tc_num = map[pfc_conf->priority];
3709         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3710         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3711         /*
3712          * At least reserve one Ethernet frame for watermark
3713          * high_water/low_water in kilo bytes for ixgbe
3714          */
3715         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3716         if ((pfc_conf->fc.high_water > max_high_water) ||
3717             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3718                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3719                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3720                 return -EINVAL;
3721         }
3722
3723         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3724         hw->fc.pause_time = pfc_conf->fc.pause_time;
3725         hw->fc.send_xon = pfc_conf->fc.send_xon;
3726         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3727         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3728
3729         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3730
3731         /* Not negotiated is not an error case */
3732         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3733                 return 0;
3734
3735         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3736         return -EIO;
3737 }
3738
3739 static int
3740 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3741                           struct rte_eth_rss_reta_entry64 *reta_conf,
3742                           uint16_t reta_size)
3743 {
3744         uint16_t i, sp_reta_size;
3745         uint8_t j, mask;
3746         uint32_t reta, r;
3747         uint16_t idx, shift;
3748         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3749         uint32_t reta_reg;
3750
3751         PMD_INIT_FUNC_TRACE();
3752
3753         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3754                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3755                         "NIC.");
3756                 return -ENOTSUP;
3757         }
3758
3759         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3760         if (reta_size != sp_reta_size) {
3761                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3762                         "(%d) doesn't match the number hardware can supported "
3763                         "(%d)\n", reta_size, sp_reta_size);
3764                 return -EINVAL;
3765         }
3766
3767         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3768                 idx = i / RTE_RETA_GROUP_SIZE;
3769                 shift = i % RTE_RETA_GROUP_SIZE;
3770                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3771                                                 IXGBE_4_BIT_MASK);
3772                 if (!mask)
3773                         continue;
3774                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3775                 if (mask == IXGBE_4_BIT_MASK)
3776                         r = 0;
3777                 else
3778                         r = IXGBE_READ_REG(hw, reta_reg);
3779                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3780                         if (mask & (0x1 << j))
3781                                 reta |= reta_conf[idx].reta[shift + j] <<
3782                                                         (CHAR_BIT * j);
3783                         else
3784                                 reta |= r & (IXGBE_8_BIT_MASK <<
3785                                                 (CHAR_BIT * j));
3786                 }
3787                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3788         }
3789
3790         return 0;
3791 }
3792
3793 static int
3794 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3795                          struct rte_eth_rss_reta_entry64 *reta_conf,
3796                          uint16_t reta_size)
3797 {
3798         uint16_t i, sp_reta_size;
3799         uint8_t j, mask;
3800         uint32_t reta;
3801         uint16_t idx, shift;
3802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3803         uint32_t reta_reg;
3804
3805         PMD_INIT_FUNC_TRACE();
3806         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3807         if (reta_size != sp_reta_size) {
3808                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3809                         "(%d) doesn't match the number hardware can supported "
3810                         "(%d)\n", reta_size, sp_reta_size);
3811                 return -EINVAL;
3812         }
3813
3814         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3815                 idx = i / RTE_RETA_GROUP_SIZE;
3816                 shift = i % RTE_RETA_GROUP_SIZE;
3817                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3818                                                 IXGBE_4_BIT_MASK);
3819                 if (!mask)
3820                         continue;
3821
3822                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3823                 reta = IXGBE_READ_REG(hw, reta_reg);
3824                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3825                         if (mask & (0x1 << j))
3826                                 reta_conf[idx].reta[shift + j] =
3827                                         ((reta >> (CHAR_BIT * j)) &
3828                                                 IXGBE_8_BIT_MASK);
3829                 }
3830         }
3831
3832         return 0;
3833 }
3834
3835 static void
3836 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3837                                 uint32_t index, uint32_t pool)
3838 {
3839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3840         uint32_t enable_addr = 1;
3841
3842         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3843 }
3844
3845 static void
3846 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3847 {
3848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849
3850         ixgbe_clear_rar(hw, index);
3851 }
3852
3853 static void
3854 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3855 {
3856         ixgbe_remove_rar(dev, 0);
3857
3858         ixgbe_add_rar(dev, addr, 0, 0);
3859 }
3860
3861 static int
3862 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3863 {
3864         uint32_t hlreg0;
3865         uint32_t maxfrs;
3866         struct ixgbe_hw *hw;
3867         struct rte_eth_dev_info dev_info;
3868         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3869
3870         ixgbe_dev_info_get(dev, &dev_info);
3871
3872         /* check that mtu is within the allowed range */
3873         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3874                 return -EINVAL;
3875
3876         /* refuse mtu that requires the support of scattered packets when this
3877          * feature has not been enabled before. */
3878         if (!dev->data->scattered_rx &&
3879             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3880              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3881                 return -EINVAL;
3882
3883         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3884         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3885
3886         /* switch to jumbo mode if needed */
3887         if (frame_size > ETHER_MAX_LEN) {
3888                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3889                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3890         } else {
3891                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3892                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3893         }
3894         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3895
3896         /* update max frame size */
3897         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3898
3899         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3900         maxfrs &= 0x0000FFFF;
3901         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3902         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3903
3904         return 0;
3905 }
3906
3907 /*
3908  * Virtual Function operations
3909  */
3910 static void
3911 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3912 {
3913         PMD_INIT_FUNC_TRACE();
3914
3915         /* Clear interrupt mask to stop from interrupts being generated */
3916         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3917
3918         IXGBE_WRITE_FLUSH(hw);
3919 }
3920
3921 static void
3922 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3923 {
3924         PMD_INIT_FUNC_TRACE();
3925
3926         /* VF enable interrupt autoclean */
3927         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3928         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3929         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3930
3931         IXGBE_WRITE_FLUSH(hw);
3932 }
3933
3934 static int
3935 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3936 {
3937         struct rte_eth_conf* conf = &dev->data->dev_conf;
3938         struct ixgbe_adapter *adapter =
3939                         (struct ixgbe_adapter *)dev->data->dev_private;
3940
3941         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3942                      dev->data->port_id);
3943
3944         /*
3945          * VF has no ability to enable/disable HW CRC
3946          * Keep the persistent behavior the same as Host PF
3947          */
3948 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3949         if (!conf->rxmode.hw_strip_crc) {
3950                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3951                 conf->rxmode.hw_strip_crc = 1;
3952         }
3953 #else
3954         if (conf->rxmode.hw_strip_crc) {
3955                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3956                 conf->rxmode.hw_strip_crc = 0;
3957         }
3958 #endif
3959
3960         /*
3961          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3962          * allocation or vector Rx preconditions we will reset it.
3963          */
3964         adapter->rx_bulk_alloc_allowed = true;
3965         adapter->rx_vec_allowed = true;
3966
3967         return 0;
3968 }
3969
3970 static int
3971 ixgbevf_dev_start(struct rte_eth_dev *dev)
3972 {
3973         struct ixgbe_hw *hw =
3974                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3975         uint32_t intr_vector = 0;
3976         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3977
3978         int err, mask = 0;
3979
3980         PMD_INIT_FUNC_TRACE();
3981
3982         hw->mac.ops.reset_hw(hw);
3983         hw->mac.get_link_status = true;
3984
3985         /* negotiate mailbox API version to use with the PF. */
3986         ixgbevf_negotiate_api(hw);
3987
3988         ixgbevf_dev_tx_init(dev);
3989
3990         /* This can fail when allocating mbufs for descriptor rings */
3991         err = ixgbevf_dev_rx_init(dev);
3992         if (err) {
3993                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3994                 ixgbe_dev_clear_queues(dev);
3995                 return err;
3996         }
3997
3998         /* Set vfta */
3999         ixgbevf_set_vfta_all(dev,1);
4000
4001         /* Set HW strip */
4002         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
4003                 ETH_VLAN_EXTEND_MASK;
4004         ixgbevf_vlan_offload_set(dev, mask);
4005
4006         ixgbevf_dev_rxtx_start(dev);
4007
4008         /* check and configure queue intr-vector mapping */
4009         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4010                 intr_vector = dev->data->nb_rx_queues;
4011                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4012                         return -1;
4013         }
4014
4015         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4016                 intr_handle->intr_vec =
4017                         rte_zmalloc("intr_vec",
4018                                     dev->data->nb_rx_queues * sizeof(int), 0);
4019                 if (intr_handle->intr_vec == NULL) {
4020                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4021                                      " intr_vec\n", dev->data->nb_rx_queues);
4022                         return -ENOMEM;
4023                 }
4024         }
4025         ixgbevf_configure_msix(dev);
4026
4027         rte_intr_enable(intr_handle);
4028
4029         /* Re-enable interrupt for VF */
4030         ixgbevf_intr_enable(hw);
4031
4032         return 0;
4033 }
4034
4035 static void
4036 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4037 {
4038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4039         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4040
4041         PMD_INIT_FUNC_TRACE();
4042
4043         hw->adapter_stopped = 1;
4044         ixgbe_stop_adapter(hw);
4045
4046         /*
4047           * Clear what we set, but we still keep shadow_vfta to
4048           * restore after device starts
4049           */
4050         ixgbevf_set_vfta_all(dev,0);
4051
4052         /* Clear stored conf */
4053         dev->data->scattered_rx = 0;
4054
4055         ixgbe_dev_clear_queues(dev);
4056
4057         /* Clean datapath event and queue/vec mapping */
4058         rte_intr_efd_disable(intr_handle);
4059         if (intr_handle->intr_vec != NULL) {
4060                 rte_free(intr_handle->intr_vec);
4061                 intr_handle->intr_vec = NULL;
4062         }
4063 }
4064
4065 static void
4066 ixgbevf_dev_close(struct rte_eth_dev *dev)
4067 {
4068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4069
4070         PMD_INIT_FUNC_TRACE();
4071
4072         ixgbe_reset_hw(hw);
4073
4074         ixgbevf_dev_stop(dev);
4075
4076         ixgbe_dev_free_queues(dev);
4077
4078         /**
4079          * Remove the VF MAC address ro ensure
4080          * that the VF traffic goes to the PF
4081          * after stop, close and detach of the VF
4082          **/
4083         ixgbevf_remove_mac_addr(dev, 0);
4084 }
4085
4086 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4087 {
4088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4089         struct ixgbe_vfta * shadow_vfta =
4090                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4091         int i = 0, j = 0, vfta = 0, mask = 1;
4092
4093         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4094                 vfta = shadow_vfta->vfta[i];
4095                 if (vfta) {
4096                         mask = 1;
4097                         for (j = 0; j < 32; j++){
4098                                 if (vfta & mask)
4099                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4100                                 mask<<=1;
4101                         }
4102                 }
4103         }
4104
4105 }
4106
4107 static int
4108 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4109 {
4110         struct ixgbe_hw *hw =
4111                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4112         struct ixgbe_vfta * shadow_vfta =
4113                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4114         uint32_t vid_idx = 0;
4115         uint32_t vid_bit = 0;
4116         int ret = 0;
4117
4118         PMD_INIT_FUNC_TRACE();
4119
4120         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4121         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4122         if (ret) {
4123                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4124                 return ret;
4125         }
4126         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4127         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4128
4129         /* Save what we set and retore it after device reset */
4130         if (on)
4131                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4132         else
4133                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4134
4135         return 0;
4136 }
4137
4138 static void
4139 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4140 {
4141         struct ixgbe_hw *hw =
4142                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4143         uint32_t ctrl;
4144
4145         PMD_INIT_FUNC_TRACE();
4146
4147         if (queue >= hw->mac.max_rx_queues)
4148                 return;
4149
4150         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4151         if (on)
4152                 ctrl |= IXGBE_RXDCTL_VME;
4153         else
4154                 ctrl &= ~IXGBE_RXDCTL_VME;
4155         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4156
4157         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4158 }
4159
4160 static void
4161 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4162 {
4163         struct ixgbe_hw *hw =
4164                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4165         uint16_t i;
4166         int on = 0;
4167
4168         /* VF function only support hw strip feature, others are not support */
4169         if (mask & ETH_VLAN_STRIP_MASK) {
4170                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4171
4172                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4173                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4174         }
4175 }
4176
4177 static int
4178 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4179 {
4180         uint32_t reg_val;
4181
4182         /* we only need to do this if VMDq is enabled */
4183         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4184         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4185                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4186                 return -1;
4187         }
4188
4189         return 0;
4190 }
4191
4192 static uint32_t
4193 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4194 {
4195         uint32_t vector = 0;
4196         switch (hw->mac.mc_filter_type) {
4197         case 0:   /* use bits [47:36] of the address */
4198                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4199                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4200                 break;
4201         case 1:   /* use bits [46:35] of the address */
4202                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4203                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4204                 break;
4205         case 2:   /* use bits [45:34] of the address */
4206                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4207                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4208                 break;
4209         case 3:   /* use bits [43:32] of the address */
4210                 vector = ((uc_addr->addr_bytes[4]) |
4211                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4212                 break;
4213         default:  /* Invalid mc_filter_type */
4214                 break;
4215         }
4216
4217         /* vector can only be 12-bits or boundary will be exceeded */
4218         vector &= 0xFFF;
4219         return vector;
4220 }
4221
4222 static int
4223 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4224                                uint8_t on)
4225 {
4226         uint32_t vector;
4227         uint32_t uta_idx;
4228         uint32_t reg_val;
4229         uint32_t uta_shift;
4230         uint32_t rc;
4231         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4232         const uint32_t ixgbe_uta_bit_shift = 5;
4233         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4234         const uint32_t bit1 = 0x1;
4235
4236         struct ixgbe_hw *hw =
4237                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4238         struct ixgbe_uta_info *uta_info =
4239                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4240
4241         /* The UTA table only exists on 82599 hardware and newer */
4242         if (hw->mac.type < ixgbe_mac_82599EB)
4243                 return -ENOTSUP;
4244
4245         vector = ixgbe_uta_vector(hw,mac_addr);
4246         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4247         uta_shift = vector & ixgbe_uta_bit_mask;
4248
4249         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4250         if (rc == on)
4251                 return 0;
4252
4253         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4254         if (on) {
4255                 uta_info->uta_in_use++;
4256                 reg_val |= (bit1 << uta_shift);
4257                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4258         } else {
4259                 uta_info->uta_in_use--;
4260                 reg_val &= ~(bit1 << uta_shift);
4261                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4262         }
4263
4264         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4265
4266         if (uta_info->uta_in_use > 0)
4267                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4268                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4269         else
4270                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4271
4272         return 0;
4273 }
4274
4275 static int
4276 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4277 {
4278         int i;
4279         struct ixgbe_hw *hw =
4280                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4281         struct ixgbe_uta_info *uta_info =
4282                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4283
4284         /* The UTA table only exists on 82599 hardware and newer */
4285         if (hw->mac.type < ixgbe_mac_82599EB)
4286                 return -ENOTSUP;
4287
4288         if (on) {
4289                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4290                         uta_info->uta_shadow[i] = ~0;
4291                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4292                 }
4293         } else {
4294                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4295                         uta_info->uta_shadow[i] = 0;
4296                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4297                 }
4298         }
4299         return 0;
4300
4301 }
4302
4303 uint32_t
4304 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4305 {
4306         uint32_t new_val = orig_val;
4307
4308         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4309                 new_val |= IXGBE_VMOLR_AUPE;
4310         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4311                 new_val |= IXGBE_VMOLR_ROMPE;
4312         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4313                 new_val |= IXGBE_VMOLR_ROPE;
4314         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4315                 new_val |= IXGBE_VMOLR_BAM;
4316         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4317                 new_val |= IXGBE_VMOLR_MPE;
4318
4319         return new_val;
4320 }
4321
4322 static int
4323 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4324                                uint16_t rx_mask, uint8_t on)
4325 {
4326         int val = 0;
4327
4328         struct ixgbe_hw *hw =
4329                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4330         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4331
4332         if (hw->mac.type == ixgbe_mac_82598EB) {
4333                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4334                              " on 82599 hardware and newer");
4335                 return -ENOTSUP;
4336         }
4337         if (ixgbe_vmdq_mode_check(hw) < 0)
4338                 return -ENOTSUP;
4339
4340         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4341
4342         if (on)
4343                 vmolr |= val;
4344         else
4345                 vmolr &= ~val;
4346
4347         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4348
4349         return 0;
4350 }
4351
4352 static int
4353 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4354 {
4355         uint32_t reg,addr;
4356         uint32_t val;
4357         const uint8_t bit1 = 0x1;
4358
4359         struct ixgbe_hw *hw =
4360                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4361
4362         if (ixgbe_vmdq_mode_check(hw) < 0)
4363                 return -ENOTSUP;
4364
4365         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4366         reg = IXGBE_READ_REG(hw, addr);
4367         val = bit1 << pool;
4368
4369         if (on)
4370                 reg |= val;
4371         else
4372                 reg &= ~val;
4373
4374         IXGBE_WRITE_REG(hw, addr,reg);
4375
4376         return 0;
4377 }
4378
4379 static int
4380 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4381 {
4382         uint32_t reg,addr;
4383         uint32_t val;
4384         const uint8_t bit1 = 0x1;
4385
4386         struct ixgbe_hw *hw =
4387                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4388
4389         if (ixgbe_vmdq_mode_check(hw) < 0)
4390                 return -ENOTSUP;
4391
4392         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4393         reg = IXGBE_READ_REG(hw, addr);
4394         val = bit1 << pool;
4395
4396         if (on)
4397                 reg |= val;
4398         else
4399                 reg &= ~val;
4400
4401         IXGBE_WRITE_REG(hw, addr,reg);
4402
4403         return 0;
4404 }
4405
4406 static int
4407 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4408                         uint64_t pool_mask, uint8_t vlan_on)
4409 {
4410         int ret = 0;
4411         uint16_t pool_idx;
4412         struct ixgbe_hw *hw =
4413                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4414
4415         if (ixgbe_vmdq_mode_check(hw) < 0)
4416                 return -ENOTSUP;
4417         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4418                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4419                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4420                         if (ret < 0)
4421                                 return ret;
4422         }
4423
4424         return ret;
4425 }
4426
4427 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4428 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4429 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4430 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4431 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4432         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4433         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4434
4435 static int
4436 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4437                         struct rte_eth_mirror_conf *mirror_conf,
4438                         uint8_t rule_id, uint8_t on)
4439 {
4440         uint32_t mr_ctl,vlvf;
4441         uint32_t mp_lsb = 0;
4442         uint32_t mv_msb = 0;
4443         uint32_t mv_lsb = 0;
4444         uint32_t mp_msb = 0;
4445         uint8_t i = 0;
4446         int reg_index = 0;
4447         uint64_t vlan_mask = 0;
4448
4449         const uint8_t pool_mask_offset = 32;
4450         const uint8_t vlan_mask_offset = 32;
4451         const uint8_t dst_pool_offset = 8;
4452         const uint8_t rule_mr_offset  = 4;
4453         const uint8_t mirror_rule_mask= 0x0F;
4454
4455         struct ixgbe_mirror_info *mr_info =
4456                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4457         struct ixgbe_hw *hw =
4458                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4459         uint8_t mirror_type = 0;
4460
4461         if (ixgbe_vmdq_mode_check(hw) < 0)
4462                 return -ENOTSUP;
4463
4464         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4465                 return -EINVAL;
4466
4467         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4468                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4469                         mirror_conf->rule_type);
4470                 return -EINVAL;
4471         }
4472
4473         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4474                 mirror_type |= IXGBE_MRCTL_VLME;
4475                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4476                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4477                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4478                                 /* search vlan id related pool vlan filter index */
4479                                 reg_index = ixgbe_find_vlvf_slot(hw,
4480                                                 mirror_conf->vlan.vlan_id[i]);
4481                                 if (reg_index < 0)
4482                                         return -EINVAL;
4483                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4484                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4485                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4486                                       mirror_conf->vlan.vlan_id[i]))
4487                                         vlan_mask |= (1ULL << reg_index);
4488                                 else
4489                                         return -EINVAL;
4490                         }
4491                 }
4492
4493                 if (on) {
4494                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4495                         mv_msb = vlan_mask >> vlan_mask_offset;
4496
4497                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4498                                                 mirror_conf->vlan.vlan_mask;
4499                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4500                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4501                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4502                                                 mirror_conf->vlan.vlan_id[i];
4503                         }
4504                 } else {
4505                         mv_lsb = 0;
4506                         mv_msb = 0;
4507                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4508                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4509                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4510                 }
4511         }
4512
4513         /*
4514          * if enable pool mirror, write related pool mask register,if disable
4515          * pool mirror, clear PFMRVM register
4516          */
4517         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4518                 mirror_type |= IXGBE_MRCTL_VPME;
4519                 if (on) {
4520                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4521                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4522                         mr_info->mr_conf[rule_id].pool_mask =
4523                                         mirror_conf->pool_mask;
4524
4525                 } else {
4526                         mp_lsb = 0;
4527                         mp_msb = 0;
4528                         mr_info->mr_conf[rule_id].pool_mask = 0;
4529                 }
4530         }
4531         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4532                 mirror_type |= IXGBE_MRCTL_UPME;
4533         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4534                 mirror_type |= IXGBE_MRCTL_DPME;
4535
4536         /* read  mirror control register and recalculate it */
4537         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4538
4539         if (on) {
4540                 mr_ctl |= mirror_type;
4541                 mr_ctl &= mirror_rule_mask;
4542                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4543         } else
4544                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4545
4546         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4547         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4548
4549         /* write mirrror control  register */
4550         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4551
4552         /* write pool mirrror control  register */
4553         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4554                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4555                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4556                                 mp_msb);
4557         }
4558         /* write VLAN mirrror control  register */
4559         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4560                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4561                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4562                                 mv_msb);
4563         }
4564
4565         return 0;
4566 }
4567
4568 static int
4569 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4570 {
4571         int mr_ctl = 0;
4572         uint32_t lsb_val = 0;
4573         uint32_t msb_val = 0;
4574         const uint8_t rule_mr_offset = 4;
4575
4576         struct ixgbe_hw *hw =
4577                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4578         struct ixgbe_mirror_info *mr_info =
4579                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4580
4581         if (ixgbe_vmdq_mode_check(hw) < 0)
4582                 return -ENOTSUP;
4583
4584         memset(&mr_info->mr_conf[rule_id], 0,
4585                 sizeof(struct rte_eth_mirror_conf));
4586
4587         /* clear PFVMCTL register */
4588         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4589
4590         /* clear pool mask register */
4591         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4592         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4593
4594         /* clear vlan mask register */
4595         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4596         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4597
4598         return 0;
4599 }
4600
4601 static int
4602 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4603 {
4604         uint32_t mask;
4605         struct ixgbe_hw *hw =
4606                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4607
4608         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4609         mask |= (1 << IXGBE_MISC_VEC_ID);
4610         RTE_SET_USED(queue_id);
4611         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4612
4613         rte_intr_enable(&dev->pci_dev->intr_handle);
4614
4615         return 0;
4616 }
4617
4618 static int
4619 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4620 {
4621         uint32_t mask;
4622         struct ixgbe_hw *hw =
4623                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4624
4625         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4626         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4627         RTE_SET_USED(queue_id);
4628         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4629
4630         return 0;
4631 }
4632
4633 static int
4634 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4635 {
4636         uint32_t mask;
4637         struct ixgbe_hw *hw =
4638                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4639         struct ixgbe_interrupt *intr =
4640                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4641
4642         if (queue_id < 16) {
4643                 ixgbe_disable_intr(hw);
4644                 intr->mask |= (1 << queue_id);
4645                 ixgbe_enable_intr(dev);
4646         } else if (queue_id < 32) {
4647                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4648                 mask &= (1 << queue_id);
4649                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4650         } else if (queue_id < 64) {
4651                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4652                 mask &= (1 << (queue_id - 32));
4653                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4654         }
4655         rte_intr_enable(&dev->pci_dev->intr_handle);
4656
4657         return 0;
4658 }
4659
4660 static int
4661 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4662 {
4663         uint32_t mask;
4664         struct ixgbe_hw *hw =
4665                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4666         struct ixgbe_interrupt *intr =
4667                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4668
4669         if (queue_id < 16) {
4670                 ixgbe_disable_intr(hw);
4671                 intr->mask &= ~(1 << queue_id);
4672                 ixgbe_enable_intr(dev);
4673         } else if (queue_id < 32) {
4674                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4675                 mask &= ~(1 << queue_id);
4676                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4677         } else if (queue_id < 64) {
4678                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4679                 mask &= ~(1 << (queue_id - 32));
4680                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4681         }
4682
4683         return 0;
4684 }
4685
4686 static void
4687 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4688                      uint8_t queue, uint8_t msix_vector)
4689 {
4690         uint32_t tmp, idx;
4691
4692         if (direction == -1) {
4693                 /* other causes */
4694                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4695                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4696                 tmp &= ~0xFF;
4697                 tmp |= msix_vector;
4698                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4699         } else {
4700                 /* rx or tx cause */
4701                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4702                 idx = ((16 * (queue & 1)) + (8 * direction));
4703                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4704                 tmp &= ~(0xFF << idx);
4705                 tmp |= (msix_vector << idx);
4706                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4707         }
4708 }
4709
4710 /**
4711  * set the IVAR registers, mapping interrupt causes to vectors
4712  * @param hw
4713  *  pointer to ixgbe_hw struct
4714  * @direction
4715  *  0 for Rx, 1 for Tx, -1 for other causes
4716  * @queue
4717  *  queue to map the corresponding interrupt to
4718  * @msix_vector
4719  *  the vector to map to the corresponding queue
4720  */
4721 static void
4722 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4723                    uint8_t queue, uint8_t msix_vector)
4724 {
4725         uint32_t tmp, idx;
4726
4727         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4728         if (hw->mac.type == ixgbe_mac_82598EB) {
4729                 if (direction == -1)
4730                         direction = 0;
4731                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4732                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4733                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4734                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4735                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4736         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4737                         (hw->mac.type == ixgbe_mac_X540)) {
4738                 if (direction == -1) {
4739                         /* other causes */
4740                         idx = ((queue & 1) * 8);
4741                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4742                         tmp &= ~(0xFF << idx);
4743                         tmp |= (msix_vector << idx);
4744                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4745                 } else {
4746                         /* rx or tx causes */
4747                         idx = ((16 * (queue & 1)) + (8 * direction));
4748                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4749                         tmp &= ~(0xFF << idx);
4750                         tmp |= (msix_vector << idx);
4751                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4752                 }
4753         }
4754 }
4755
4756 static void
4757 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4758 {
4759         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4760         struct ixgbe_hw *hw =
4761                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4762         uint32_t q_idx;
4763         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4764
4765         /* won't configure msix register if no mapping is done
4766          * between intr vector and event fd.
4767          */
4768         if (!rte_intr_dp_is_en(intr_handle))
4769                 return;
4770
4771         /* Configure all RX queues of VF */
4772         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4773                 /* Force all queue use vector 0,
4774                  * as IXGBE_VF_MAXMSIVECOTR = 1
4775                  */
4776                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4777                 intr_handle->intr_vec[q_idx] = vector_idx;
4778         }
4779
4780         /* Configure VF other cause ivar */
4781         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4782 }
4783
4784 /**
4785  * Sets up the hardware to properly generate MSI-X interrupts
4786  * @hw
4787  *  board private structure
4788  */
4789 static void
4790 ixgbe_configure_msix(struct rte_eth_dev *dev)
4791 {
4792         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4793         struct ixgbe_hw *hw =
4794                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4795         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4796         uint32_t vec = IXGBE_MISC_VEC_ID;
4797         uint32_t mask;
4798         uint32_t gpie;
4799
4800         /* won't configure msix register if no mapping is done
4801          * between intr vector and event fd
4802          */
4803         if (!rte_intr_dp_is_en(intr_handle))
4804                 return;
4805
4806         if (rte_intr_allow_others(intr_handle))
4807                 vec = base = IXGBE_RX_VEC_START;
4808
4809         /* setup GPIE for MSI-x mode */
4810         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4811         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4812                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4813         /* auto clearing and auto setting corresponding bits in EIMS
4814          * when MSI-X interrupt is triggered
4815          */
4816         if (hw->mac.type == ixgbe_mac_82598EB) {
4817                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4818         } else {
4819                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4820                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4821         }
4822         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4823
4824         /* Populate the IVAR table and set the ITR values to the
4825          * corresponding register.
4826          */
4827         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4828              queue_id++) {
4829                 /* by default, 1:1 mapping */
4830                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4831                 intr_handle->intr_vec[queue_id] = vec;
4832                 if (vec < base + intr_handle->nb_efd - 1)
4833                         vec++;
4834         }
4835
4836         switch (hw->mac.type) {
4837         case ixgbe_mac_82598EB:
4838                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4839                                    IXGBE_MISC_VEC_ID);
4840                 break;
4841         case ixgbe_mac_82599EB:
4842         case ixgbe_mac_X540:
4843                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4844                 break;
4845         default:
4846                 break;
4847         }
4848         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4849                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4850
4851         /* set up to autoclear timer, and the vectors */
4852         mask = IXGBE_EIMS_ENABLE_MASK;
4853         mask &= ~(IXGBE_EIMS_OTHER |
4854                   IXGBE_EIMS_MAILBOX |
4855                   IXGBE_EIMS_LSC);
4856
4857         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4858 }
4859
4860 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4861         uint16_t queue_idx, uint16_t tx_rate)
4862 {
4863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4864         uint32_t rf_dec, rf_int;
4865         uint32_t bcnrc_val;
4866         uint16_t link_speed = dev->data->dev_link.link_speed;
4867
4868         if (queue_idx >= hw->mac.max_tx_queues)
4869                 return -EINVAL;
4870
4871         if (tx_rate != 0) {
4872                 /* Calculate the rate factor values to set */
4873                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4874                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4875                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4876
4877                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4878                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4879                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4880                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4881         } else {
4882                 bcnrc_val = 0;
4883         }
4884
4885         /*
4886          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4887          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4888          * set as 0x4.
4889          */
4890         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4891                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4892                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4893                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4894                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4895         else
4896                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4897                         IXGBE_MMW_SIZE_DEFAULT);
4898
4899         /* Set RTTBCNRC of queue X */
4900         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4901         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4902         IXGBE_WRITE_FLUSH(hw);
4903
4904         return 0;
4905 }
4906
4907 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4908         uint16_t tx_rate, uint64_t q_msk)
4909 {
4910         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4911         struct ixgbe_vf_info *vfinfo =
4912                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4913         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4914         uint32_t queue_stride =
4915                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4916         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4917         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4918         uint16_t total_rate = 0;
4919
4920         if (queue_end >= hw->mac.max_tx_queues)
4921                 return -EINVAL;
4922
4923         if (vfinfo != NULL) {
4924                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4925                         if (vf_idx == vf)
4926                                 continue;
4927                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4928                                 idx++)
4929                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4930                 }
4931         } else
4932                 return -EINVAL;
4933
4934         /* Store tx_rate for this vf. */
4935         for (idx = 0; idx < nb_q_per_pool; idx++) {
4936                 if (((uint64_t)0x1 << idx) & q_msk) {
4937                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4938                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4939                         total_rate += tx_rate;
4940                 }
4941         }
4942
4943         if (total_rate > dev->data->dev_link.link_speed) {
4944                 /*
4945                  * Reset stored TX rate of the VF if it causes exceed
4946                  * link speed.
4947                  */
4948                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4949                 return -EINVAL;
4950         }
4951
4952         /* Set RTTBCNRC of each queue/pool for vf X  */
4953         for (; queue_idx <= queue_end; queue_idx++) {
4954                 if (0x1 & q_msk)
4955                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4956                 q_msk = q_msk >> 1;
4957         }
4958
4959         return 0;
4960 }
4961
4962 static void
4963 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4964                      __attribute__((unused)) uint32_t index,
4965                      __attribute__((unused)) uint32_t pool)
4966 {
4967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4968         int diag;
4969
4970         /*
4971          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4972          * operation. Trap this case to avoid exhausting the [very limited]
4973          * set of PF resources used to store VF MAC addresses.
4974          */
4975         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4976                 return;
4977         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4978         if (diag == 0)
4979                 return;
4980         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4981 }
4982
4983 static void
4984 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4985 {
4986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4987         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4988         struct ether_addr *mac_addr;
4989         uint32_t i;
4990         int diag;
4991
4992         /*
4993          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4994          * not support the deletion of a given MAC address.
4995          * Instead, it imposes to delete all MAC addresses, then to add again
4996          * all MAC addresses with the exception of the one to be deleted.
4997          */
4998         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4999
5000         /*
5001          * Add again all MAC addresses, with the exception of the deleted one
5002          * and of the permanent MAC address.
5003          */
5004         for (i = 0, mac_addr = dev->data->mac_addrs;
5005              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5006                 /* Skip the deleted MAC address */
5007                 if (i == index)
5008                         continue;
5009                 /* Skip NULL MAC addresses */
5010                 if (is_zero_ether_addr(mac_addr))
5011                         continue;
5012                 /* Skip the permanent MAC address */
5013                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5014                         continue;
5015                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5016                 if (diag != 0)
5017                         PMD_DRV_LOG(ERR,
5018                                     "Adding again MAC address "
5019                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5020                                     "diag=%d",
5021                                     mac_addr->addr_bytes[0],
5022                                     mac_addr->addr_bytes[1],
5023                                     mac_addr->addr_bytes[2],
5024                                     mac_addr->addr_bytes[3],
5025                                     mac_addr->addr_bytes[4],
5026                                     mac_addr->addr_bytes[5],
5027                                     diag);
5028         }
5029 }
5030
5031 static void
5032 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5033 {
5034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5035
5036         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5037 }
5038
5039 #define MAC_TYPE_FILTER_SUP(type)    do {\
5040         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5041                 (type) != ixgbe_mac_X550)\
5042                 return -ENOTSUP;\
5043 } while (0)
5044
5045 static int
5046 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5047                         struct rte_eth_syn_filter *filter,
5048                         bool add)
5049 {
5050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051         uint32_t synqf;
5052
5053         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5054                 return -EINVAL;
5055
5056         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5057
5058         if (add) {
5059                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5060                         return -EINVAL;
5061                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5062                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5063
5064                 if (filter->hig_pri)
5065                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5066                 else
5067                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5068         } else {
5069                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5070                         return -ENOENT;
5071                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5072         }
5073         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5074         IXGBE_WRITE_FLUSH(hw);
5075         return 0;
5076 }
5077
5078 static int
5079 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5080                         struct rte_eth_syn_filter *filter)
5081 {
5082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5083         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5084
5085         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5086                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5087                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5088                 return 0;
5089         }
5090         return -ENOENT;
5091 }
5092
5093 static int
5094 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5095                         enum rte_filter_op filter_op,
5096                         void *arg)
5097 {
5098         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5099         int ret;
5100
5101         MAC_TYPE_FILTER_SUP(hw->mac.type);
5102
5103         if (filter_op == RTE_ETH_FILTER_NOP)
5104                 return 0;
5105
5106         if (arg == NULL) {
5107                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5108                             filter_op);
5109                 return -EINVAL;
5110         }
5111
5112         switch (filter_op) {
5113         case RTE_ETH_FILTER_ADD:
5114                 ret = ixgbe_syn_filter_set(dev,
5115                                 (struct rte_eth_syn_filter *)arg,
5116                                 TRUE);
5117                 break;
5118         case RTE_ETH_FILTER_DELETE:
5119                 ret = ixgbe_syn_filter_set(dev,
5120                                 (struct rte_eth_syn_filter *)arg,
5121                                 FALSE);
5122                 break;
5123         case RTE_ETH_FILTER_GET:
5124                 ret = ixgbe_syn_filter_get(dev,
5125                                 (struct rte_eth_syn_filter *)arg);
5126                 break;
5127         default:
5128                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5129                 ret = -EINVAL;
5130                 break;
5131         }
5132
5133         return ret;
5134 }
5135
5136
5137 static inline enum ixgbe_5tuple_protocol
5138 convert_protocol_type(uint8_t protocol_value)
5139 {
5140         if (protocol_value == IPPROTO_TCP)
5141                 return IXGBE_FILTER_PROTOCOL_TCP;
5142         else if (protocol_value == IPPROTO_UDP)
5143                 return IXGBE_FILTER_PROTOCOL_UDP;
5144         else if (protocol_value == IPPROTO_SCTP)
5145                 return IXGBE_FILTER_PROTOCOL_SCTP;
5146         else
5147                 return IXGBE_FILTER_PROTOCOL_NONE;
5148 }
5149
5150 /*
5151  * add a 5tuple filter
5152  *
5153  * @param
5154  * dev: Pointer to struct rte_eth_dev.
5155  * index: the index the filter allocates.
5156  * filter: ponter to the filter that will be added.
5157  * rx_queue: the queue id the filter assigned to.
5158  *
5159  * @return
5160  *    - On success, zero.
5161  *    - On failure, a negative value.
5162  */
5163 static int
5164 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5165                         struct ixgbe_5tuple_filter *filter)
5166 {
5167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5168         struct ixgbe_filter_info *filter_info =
5169                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5170         int i, idx, shift;
5171         uint32_t ftqf, sdpqf;
5172         uint32_t l34timir = 0;
5173         uint8_t mask = 0xff;
5174
5175         /*
5176          * look for an unused 5tuple filter index,
5177          * and insert the filter to list.
5178          */
5179         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5180                 idx = i / (sizeof(uint32_t) * NBBY);
5181                 shift = i % (sizeof(uint32_t) * NBBY);
5182                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5183                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5184                         filter->index = i;
5185                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5186                                           filter,
5187                                           entries);
5188                         break;
5189                 }
5190         }
5191         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5192                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5193                 return -ENOSYS;
5194         }
5195
5196         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5197                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5198         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5199
5200         ftqf = (uint32_t)(filter->filter_info.proto &
5201                 IXGBE_FTQF_PROTOCOL_MASK);
5202         ftqf |= (uint32_t)((filter->filter_info.priority &
5203                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5204         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5205                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5206         if (filter->filter_info.dst_ip_mask == 0)
5207                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5208         if (filter->filter_info.src_port_mask == 0)
5209                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5210         if (filter->filter_info.dst_port_mask == 0)
5211                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5212         if (filter->filter_info.proto_mask == 0)
5213                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5214         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5215         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5216         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5217
5218         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5219         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5220         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5221         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5222
5223         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5224         l34timir |= (uint32_t)(filter->queue <<
5225                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5226         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5227         return 0;
5228 }
5229
5230 /*
5231  * remove a 5tuple filter
5232  *
5233  * @param
5234  * dev: Pointer to struct rte_eth_dev.
5235  * filter: the pointer of the filter will be removed.
5236  */
5237 static void
5238 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5239                         struct ixgbe_5tuple_filter *filter)
5240 {
5241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5242         struct ixgbe_filter_info *filter_info =
5243                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5244         uint16_t index = filter->index;
5245
5246         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5247                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5248         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5249         rte_free(filter);
5250
5251         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5252         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5253         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5254         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5255         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5256 }
5257
5258 static int
5259 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5260 {
5261         struct ixgbe_hw *hw;
5262         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5263
5264         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5265
5266         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5267                 return -EINVAL;
5268
5269         /* refuse mtu that requires the support of scattered packets when this
5270          * feature has not been enabled before. */
5271         if (!dev->data->scattered_rx &&
5272             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5273              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5274                 return -EINVAL;
5275
5276         /*
5277          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5278          * request of the version 2.0 of the mailbox API.
5279          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5280          * of the mailbox API.
5281          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5282          * prior to 3.11.33 which contains the following change:
5283          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5284          */
5285         ixgbevf_rlpml_set_vf(hw, max_frame);
5286
5287         /* update max frame size */
5288         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5289         return 0;
5290 }
5291
5292 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5293         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5294                 return -ENOTSUP;\
5295 } while (0)
5296
5297 static inline struct ixgbe_5tuple_filter *
5298 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5299                         struct ixgbe_5tuple_filter_info *key)
5300 {
5301         struct ixgbe_5tuple_filter *it;
5302
5303         TAILQ_FOREACH(it, filter_list, entries) {
5304                 if (memcmp(key, &it->filter_info,
5305                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5306                         return it;
5307                 }
5308         }
5309         return NULL;
5310 }
5311
5312 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5313 static inline int
5314 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5315                         struct ixgbe_5tuple_filter_info *filter_info)
5316 {
5317         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5318                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5319                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5320                 return -EINVAL;
5321
5322         switch (filter->dst_ip_mask) {
5323         case UINT32_MAX:
5324                 filter_info->dst_ip_mask = 0;
5325                 filter_info->dst_ip = filter->dst_ip;
5326                 break;
5327         case 0:
5328                 filter_info->dst_ip_mask = 1;
5329                 break;
5330         default:
5331                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5332                 return -EINVAL;
5333         }
5334
5335         switch (filter->src_ip_mask) {
5336         case UINT32_MAX:
5337                 filter_info->src_ip_mask = 0;
5338                 filter_info->src_ip = filter->src_ip;
5339                 break;
5340         case 0:
5341                 filter_info->src_ip_mask = 1;
5342                 break;
5343         default:
5344                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5345                 return -EINVAL;
5346         }
5347
5348         switch (filter->dst_port_mask) {
5349         case UINT16_MAX:
5350                 filter_info->dst_port_mask = 0;
5351                 filter_info->dst_port = filter->dst_port;
5352                 break;
5353         case 0:
5354                 filter_info->dst_port_mask = 1;
5355                 break;
5356         default:
5357                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5358                 return -EINVAL;
5359         }
5360
5361         switch (filter->src_port_mask) {
5362         case UINT16_MAX:
5363                 filter_info->src_port_mask = 0;
5364                 filter_info->src_port = filter->src_port;
5365                 break;
5366         case 0:
5367                 filter_info->src_port_mask = 1;
5368                 break;
5369         default:
5370                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5371                 return -EINVAL;
5372         }
5373
5374         switch (filter->proto_mask) {
5375         case UINT8_MAX:
5376                 filter_info->proto_mask = 0;
5377                 filter_info->proto =
5378                         convert_protocol_type(filter->proto);
5379                 break;
5380         case 0:
5381                 filter_info->proto_mask = 1;
5382                 break;
5383         default:
5384                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5385                 return -EINVAL;
5386         }
5387
5388         filter_info->priority = (uint8_t)filter->priority;
5389         return 0;
5390 }
5391
5392 /*
5393  * add or delete a ntuple filter
5394  *
5395  * @param
5396  * dev: Pointer to struct rte_eth_dev.
5397  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5398  * add: if true, add filter, if false, remove filter
5399  *
5400  * @return
5401  *    - On success, zero.
5402  *    - On failure, a negative value.
5403  */
5404 static int
5405 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5406                         struct rte_eth_ntuple_filter *ntuple_filter,
5407                         bool add)
5408 {
5409         struct ixgbe_filter_info *filter_info =
5410                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5411         struct ixgbe_5tuple_filter_info filter_5tuple;
5412         struct ixgbe_5tuple_filter *filter;
5413         int ret;
5414
5415         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5416                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5417                 return -EINVAL;
5418         }
5419
5420         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5421         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5422         if (ret < 0)
5423                 return ret;
5424
5425         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5426                                          &filter_5tuple);
5427         if (filter != NULL && add) {
5428                 PMD_DRV_LOG(ERR, "filter exists.");
5429                 return -EEXIST;
5430         }
5431         if (filter == NULL && !add) {
5432                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5433                 return -ENOENT;
5434         }
5435
5436         if (add) {
5437                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5438                                 sizeof(struct ixgbe_5tuple_filter), 0);
5439                 if (filter == NULL)
5440                         return -ENOMEM;
5441                 (void)rte_memcpy(&filter->filter_info,
5442                                  &filter_5tuple,
5443                                  sizeof(struct ixgbe_5tuple_filter_info));
5444                 filter->queue = ntuple_filter->queue;
5445                 ret = ixgbe_add_5tuple_filter(dev, filter);
5446                 if (ret < 0) {
5447                         rte_free(filter);
5448                         return ret;
5449                 }
5450         } else
5451                 ixgbe_remove_5tuple_filter(dev, filter);
5452
5453         return 0;
5454 }
5455
5456 /*
5457  * get a ntuple filter
5458  *
5459  * @param
5460  * dev: Pointer to struct rte_eth_dev.
5461  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5462  *
5463  * @return
5464  *    - On success, zero.
5465  *    - On failure, a negative value.
5466  */
5467 static int
5468 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5469                         struct rte_eth_ntuple_filter *ntuple_filter)
5470 {
5471         struct ixgbe_filter_info *filter_info =
5472                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5473         struct ixgbe_5tuple_filter_info filter_5tuple;
5474         struct ixgbe_5tuple_filter *filter;
5475         int ret;
5476
5477         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5478                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5479                 return -EINVAL;
5480         }
5481
5482         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5483         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5484         if (ret < 0)
5485                 return ret;
5486
5487         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5488                                          &filter_5tuple);
5489         if (filter == NULL) {
5490                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5491                 return -ENOENT;
5492         }
5493         ntuple_filter->queue = filter->queue;
5494         return 0;
5495 }
5496
5497 /*
5498  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5499  * @dev: pointer to rte_eth_dev structure
5500  * @filter_op:operation will be taken.
5501  * @arg: a pointer to specific structure corresponding to the filter_op
5502  *
5503  * @return
5504  *    - On success, zero.
5505  *    - On failure, a negative value.
5506  */
5507 static int
5508 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5509                                 enum rte_filter_op filter_op,
5510                                 void *arg)
5511 {
5512         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5513         int ret;
5514
5515         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5516
5517         if (filter_op == RTE_ETH_FILTER_NOP)
5518                 return 0;
5519
5520         if (arg == NULL) {
5521                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5522                             filter_op);
5523                 return -EINVAL;
5524         }
5525
5526         switch (filter_op) {
5527         case RTE_ETH_FILTER_ADD:
5528                 ret = ixgbe_add_del_ntuple_filter(dev,
5529                         (struct rte_eth_ntuple_filter *)arg,
5530                         TRUE);
5531                 break;
5532         case RTE_ETH_FILTER_DELETE:
5533                 ret = ixgbe_add_del_ntuple_filter(dev,
5534                         (struct rte_eth_ntuple_filter *)arg,
5535                         FALSE);
5536                 break;
5537         case RTE_ETH_FILTER_GET:
5538                 ret = ixgbe_get_ntuple_filter(dev,
5539                         (struct rte_eth_ntuple_filter *)arg);
5540                 break;
5541         default:
5542                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5543                 ret = -EINVAL;
5544                 break;
5545         }
5546         return ret;
5547 }
5548
5549 static inline int
5550 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5551                         uint16_t ethertype)
5552 {
5553         int i;
5554
5555         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5556                 if (filter_info->ethertype_filters[i] == ethertype &&
5557                     (filter_info->ethertype_mask & (1 << i)))
5558                         return i;
5559         }
5560         return -1;
5561 }
5562
5563 static inline int
5564 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5565                         uint16_t ethertype)
5566 {
5567         int i;
5568
5569         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5570                 if (!(filter_info->ethertype_mask & (1 << i))) {
5571                         filter_info->ethertype_mask |= 1 << i;
5572                         filter_info->ethertype_filters[i] = ethertype;
5573                         return i;
5574                 }
5575         }
5576         return -1;
5577 }
5578
5579 static inline int
5580 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5581                         uint8_t idx)
5582 {
5583         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5584                 return -1;
5585         filter_info->ethertype_mask &= ~(1 << idx);
5586         filter_info->ethertype_filters[idx] = 0;
5587         return idx;
5588 }
5589
5590 static int
5591 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5592                         struct rte_eth_ethertype_filter *filter,
5593                         bool add)
5594 {
5595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5596         struct ixgbe_filter_info *filter_info =
5597                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5598         uint32_t etqf = 0;
5599         uint32_t etqs = 0;
5600         int ret;
5601
5602         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5603                 return -EINVAL;
5604
5605         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5606                 filter->ether_type == ETHER_TYPE_IPv6) {
5607                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5608                         " ethertype filter.", filter->ether_type);
5609                 return -EINVAL;
5610         }
5611
5612         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5613                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5614                 return -EINVAL;
5615         }
5616         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5617                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5618                 return -EINVAL;
5619         }
5620
5621         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5622         if (ret >= 0 && add) {
5623                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5624                             filter->ether_type);
5625                 return -EEXIST;
5626         }
5627         if (ret < 0 && !add) {
5628                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5629                             filter->ether_type);
5630                 return -ENOENT;
5631         }
5632
5633         if (add) {
5634                 ret = ixgbe_ethertype_filter_insert(filter_info,
5635                         filter->ether_type);
5636                 if (ret < 0) {
5637                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5638                         return -ENOSYS;
5639                 }
5640                 etqf = IXGBE_ETQF_FILTER_EN;
5641                 etqf |= (uint32_t)filter->ether_type;
5642                 etqs |= (uint32_t)((filter->queue <<
5643                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5644                                     IXGBE_ETQS_RX_QUEUE);
5645                 etqs |= IXGBE_ETQS_QUEUE_EN;
5646         } else {
5647                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5648                 if (ret < 0)
5649                         return -ENOSYS;
5650         }
5651         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5652         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5653         IXGBE_WRITE_FLUSH(hw);
5654
5655         return 0;
5656 }
5657
5658 static int
5659 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5660                         struct rte_eth_ethertype_filter *filter)
5661 {
5662         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5663         struct ixgbe_filter_info *filter_info =
5664                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5665         uint32_t etqf, etqs;
5666         int ret;
5667
5668         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5669         if (ret < 0) {
5670                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5671                             filter->ether_type);
5672                 return -ENOENT;
5673         }
5674
5675         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5676         if (etqf & IXGBE_ETQF_FILTER_EN) {
5677                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5678                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5679                 filter->flags = 0;
5680                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5681                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5682                 return 0;
5683         }
5684         return -ENOENT;
5685 }
5686
5687 /*
5688  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5689  * @dev: pointer to rte_eth_dev structure
5690  * @filter_op:operation will be taken.
5691  * @arg: a pointer to specific structure corresponding to the filter_op
5692  */
5693 static int
5694 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5695                                 enum rte_filter_op filter_op,
5696                                 void *arg)
5697 {
5698         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5699         int ret;
5700
5701         MAC_TYPE_FILTER_SUP(hw->mac.type);
5702
5703         if (filter_op == RTE_ETH_FILTER_NOP)
5704                 return 0;
5705
5706         if (arg == NULL) {
5707                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5708                             filter_op);
5709                 return -EINVAL;
5710         }
5711
5712         switch (filter_op) {
5713         case RTE_ETH_FILTER_ADD:
5714                 ret = ixgbe_add_del_ethertype_filter(dev,
5715                         (struct rte_eth_ethertype_filter *)arg,
5716                         TRUE);
5717                 break;
5718         case RTE_ETH_FILTER_DELETE:
5719                 ret = ixgbe_add_del_ethertype_filter(dev,
5720                         (struct rte_eth_ethertype_filter *)arg,
5721                         FALSE);
5722                 break;
5723         case RTE_ETH_FILTER_GET:
5724                 ret = ixgbe_get_ethertype_filter(dev,
5725                         (struct rte_eth_ethertype_filter *)arg);
5726                 break;
5727         default:
5728                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5729                 ret = -EINVAL;
5730                 break;
5731         }
5732         return ret;
5733 }
5734
5735 static int
5736 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5737                      enum rte_filter_type filter_type,
5738                      enum rte_filter_op filter_op,
5739                      void *arg)
5740 {
5741         int ret = -EINVAL;
5742
5743         switch (filter_type) {
5744         case RTE_ETH_FILTER_NTUPLE:
5745                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5746                 break;
5747         case RTE_ETH_FILTER_ETHERTYPE:
5748                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5749                 break;
5750         case RTE_ETH_FILTER_SYN:
5751                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5752                 break;
5753         case RTE_ETH_FILTER_FDIR:
5754                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5755                 break;
5756         case RTE_ETH_FILTER_L2_TUNNEL:
5757                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5758                 break;
5759         default:
5760                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5761                                                         filter_type);
5762                 break;
5763         }
5764
5765         return ret;
5766 }
5767
5768 static u8 *
5769 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5770                         u8 **mc_addr_ptr, u32 *vmdq)
5771 {
5772         u8 *mc_addr;
5773
5774         *vmdq = 0;
5775         mc_addr = *mc_addr_ptr;
5776         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5777         return mc_addr;
5778 }
5779
5780 static int
5781 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5782                           struct ether_addr *mc_addr_set,
5783                           uint32_t nb_mc_addr)
5784 {
5785         struct ixgbe_hw *hw;
5786         u8 *mc_addr_list;
5787
5788         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5789         mc_addr_list = (u8 *)mc_addr_set;
5790         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5791                                          ixgbe_dev_addr_list_itr, TRUE);
5792 }
5793
5794 static uint64_t
5795 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5796 {
5797         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5798         uint64_t systime_cycles;
5799
5800         switch (hw->mac.type) {
5801         case ixgbe_mac_X550:
5802                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5803                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5804                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5805                                 * NSEC_PER_SEC;
5806                 break;
5807         default:
5808                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5809                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5810                                 << 32;
5811         }
5812
5813         return systime_cycles;
5814 }
5815
5816 static uint64_t
5817 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5818 {
5819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5820         uint64_t rx_tstamp_cycles;
5821
5822         switch (hw->mac.type) {
5823         case ixgbe_mac_X550:
5824                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5825                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5826                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5827                                 * NSEC_PER_SEC;
5828                 break;
5829         default:
5830                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5831                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5832                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5833                                 << 32;
5834         }
5835
5836         return rx_tstamp_cycles;
5837 }
5838
5839 static uint64_t
5840 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5841 {
5842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5843         uint64_t tx_tstamp_cycles;
5844
5845         switch (hw->mac.type) {
5846         case ixgbe_mac_X550:
5847                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5848                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5849                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5850                                 * NSEC_PER_SEC;
5851                 break;
5852         default:
5853                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5854                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5855                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5856                                 << 32;
5857         }
5858
5859         return tx_tstamp_cycles;
5860 }
5861
5862 static void
5863 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5864 {
5865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5866         struct ixgbe_adapter *adapter =
5867                 (struct ixgbe_adapter *)dev->data->dev_private;
5868         struct rte_eth_link link;
5869         uint32_t incval = 0;
5870         uint32_t shift = 0;
5871
5872         /* Get current link speed. */
5873         memset(&link, 0, sizeof(link));
5874         ixgbe_dev_link_update(dev, 1);
5875         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5876
5877         switch (link.link_speed) {
5878         case ETH_LINK_SPEED_100:
5879                 incval = IXGBE_INCVAL_100;
5880                 shift = IXGBE_INCVAL_SHIFT_100;
5881                 break;
5882         case ETH_LINK_SPEED_1000:
5883                 incval = IXGBE_INCVAL_1GB;
5884                 shift = IXGBE_INCVAL_SHIFT_1GB;
5885                 break;
5886         case ETH_LINK_SPEED_10000:
5887         default:
5888                 incval = IXGBE_INCVAL_10GB;
5889                 shift = IXGBE_INCVAL_SHIFT_10GB;
5890                 break;
5891         }
5892
5893         switch (hw->mac.type) {
5894         case ixgbe_mac_X550:
5895                 /* Independent of link speed. */
5896                 incval = 1;
5897                 /* Cycles read will be interpreted as ns. */
5898                 shift = 0;
5899                 /* Fall-through */
5900         case ixgbe_mac_X540:
5901                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5902                 break;
5903         case ixgbe_mac_82599EB:
5904                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5905                 shift -= IXGBE_INCVAL_SHIFT_82599;
5906                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5907                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5908                 break;
5909         default:
5910                 /* Not supported. */
5911                 return;
5912         }
5913
5914         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5915         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5916         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5917
5918         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5919         adapter->systime_tc.cc_shift = shift;
5920         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5921
5922         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5923         adapter->rx_tstamp_tc.cc_shift = shift;
5924         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5925
5926         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5927         adapter->tx_tstamp_tc.cc_shift = shift;
5928         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5929 }
5930
5931 static int
5932 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5933 {
5934         struct ixgbe_adapter *adapter =
5935                         (struct ixgbe_adapter *)dev->data->dev_private;
5936
5937         adapter->systime_tc.nsec += delta;
5938         adapter->rx_tstamp_tc.nsec += delta;
5939         adapter->tx_tstamp_tc.nsec += delta;
5940
5941         return 0;
5942 }
5943
5944 static int
5945 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5946 {
5947         uint64_t ns;
5948         struct ixgbe_adapter *adapter =
5949                         (struct ixgbe_adapter *)dev->data->dev_private;
5950
5951         ns = rte_timespec_to_ns(ts);
5952         /* Set the timecounters to a new value. */
5953         adapter->systime_tc.nsec = ns;
5954         adapter->rx_tstamp_tc.nsec = ns;
5955         adapter->tx_tstamp_tc.nsec = ns;
5956
5957         return 0;
5958 }
5959
5960 static int
5961 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5962 {
5963         uint64_t ns, systime_cycles;
5964         struct ixgbe_adapter *adapter =
5965                         (struct ixgbe_adapter *)dev->data->dev_private;
5966
5967         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5968         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5969         *ts = rte_ns_to_timespec(ns);
5970
5971         return 0;
5972 }
5973
5974 static int
5975 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5976 {
5977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5978         uint32_t tsync_ctl;
5979         uint32_t tsauxc;
5980
5981         /* Stop the timesync system time. */
5982         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5983         /* Reset the timesync system time value. */
5984         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5985         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5986
5987         /* Enable system time for platforms where it isn't on by default. */
5988         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5989         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5990         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5991
5992         ixgbe_start_timecounters(dev);
5993
5994         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5995         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5996                         (ETHER_TYPE_1588 |
5997                          IXGBE_ETQF_FILTER_EN |
5998                          IXGBE_ETQF_1588));
5999
6000         /* Enable timestamping of received PTP packets. */
6001         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6002         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6003         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6004
6005         /* Enable timestamping of transmitted PTP packets. */
6006         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6007         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6008         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6009
6010         IXGBE_WRITE_FLUSH(hw);
6011
6012         return 0;
6013 }
6014
6015 static int
6016 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6017 {
6018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6019         uint32_t tsync_ctl;
6020
6021         /* Disable timestamping of transmitted PTP packets. */
6022         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6023         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6024         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6025
6026         /* Disable timestamping of received PTP packets. */
6027         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6028         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6029         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6030
6031         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6032         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6033
6034         /* Stop incrementating the System Time registers. */
6035         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6036
6037         return 0;
6038 }
6039
6040 static int
6041 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6042                                  struct timespec *timestamp,
6043                                  uint32_t flags __rte_unused)
6044 {
6045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6046         struct ixgbe_adapter *adapter =
6047                 (struct ixgbe_adapter *)dev->data->dev_private;
6048         uint32_t tsync_rxctl;
6049         uint64_t rx_tstamp_cycles;
6050         uint64_t ns;
6051
6052         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6053         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6054                 return -EINVAL;
6055
6056         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6057         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6058         *timestamp = rte_ns_to_timespec(ns);
6059
6060         return  0;
6061 }
6062
6063 static int
6064 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6065                                  struct timespec *timestamp)
6066 {
6067         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6068         struct ixgbe_adapter *adapter =
6069                 (struct ixgbe_adapter *)dev->data->dev_private;
6070         uint32_t tsync_txctl;
6071         uint64_t tx_tstamp_cycles;
6072         uint64_t ns;
6073
6074         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6075         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6076                 return -EINVAL;
6077
6078         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6079         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6080         *timestamp = rte_ns_to_timespec(ns);
6081
6082         return 0;
6083 }
6084
6085 static int
6086 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6087 {
6088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6089         int count = 0;
6090         int g_ind = 0;
6091         const struct reg_info *reg_group;
6092         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6093                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6094
6095         while ((reg_group = reg_set[g_ind++]))
6096                 count += ixgbe_regs_group_count(reg_group);
6097
6098         return count;
6099 }
6100
6101 static int
6102 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6103 {
6104         int count = 0;
6105         int g_ind = 0;
6106         const struct reg_info *reg_group;
6107
6108         while ((reg_group = ixgbevf_regs[g_ind++]))
6109                 count += ixgbe_regs_group_count(reg_group);
6110
6111         return count;
6112 }
6113
6114 static int
6115 ixgbe_get_regs(struct rte_eth_dev *dev,
6116               struct rte_dev_reg_info *regs)
6117 {
6118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6119         uint32_t *data = regs->data;
6120         int g_ind = 0;
6121         int count = 0;
6122         const struct reg_info *reg_group;
6123         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6124                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6125
6126         /* Support only full register dump */
6127         if ((regs->length == 0) ||
6128             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6129                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6130                         hw->device_id;
6131                 while ((reg_group = reg_set[g_ind++]))
6132                         count += ixgbe_read_regs_group(dev, &data[count],
6133                                 reg_group);
6134                 return 0;
6135         }
6136
6137         return -ENOTSUP;
6138 }
6139
6140 static int
6141 ixgbevf_get_regs(struct rte_eth_dev *dev,
6142                 struct rte_dev_reg_info *regs)
6143 {
6144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6145         uint32_t *data = regs->data;
6146         int g_ind = 0;
6147         int count = 0;
6148         const struct reg_info *reg_group;
6149
6150         /* Support only full register dump */
6151         if ((regs->length == 0) ||
6152             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6153                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6154                         hw->device_id;
6155                 while ((reg_group = ixgbevf_regs[g_ind++]))
6156                         count += ixgbe_read_regs_group(dev, &data[count],
6157                                                       reg_group);
6158                 return 0;
6159         }
6160
6161         return -ENOTSUP;
6162 }
6163
6164 static int
6165 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6166 {
6167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6168
6169         /* Return unit is byte count */
6170         return hw->eeprom.word_size * 2;
6171 }
6172
6173 static int
6174 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6175                 struct rte_dev_eeprom_info *in_eeprom)
6176 {
6177         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6178         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6179         uint16_t *data = in_eeprom->data;
6180         int first, length;
6181
6182         first = in_eeprom->offset >> 1;
6183         length = in_eeprom->length >> 1;
6184         if ((first > hw->eeprom.word_size) ||
6185             ((first + length) > hw->eeprom.word_size))
6186                 return -EINVAL;
6187
6188         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6189
6190         return eeprom->ops.read_buffer(hw, first, length, data);
6191 }
6192
6193 static int
6194 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6195                 struct rte_dev_eeprom_info *in_eeprom)
6196 {
6197         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6198         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6199         uint16_t *data = in_eeprom->data;
6200         int first, length;
6201
6202         first = in_eeprom->offset >> 1;
6203         length = in_eeprom->length >> 1;
6204         if ((first > hw->eeprom.word_size) ||
6205             ((first + length) > hw->eeprom.word_size))
6206                 return -EINVAL;
6207
6208         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6209
6210         return eeprom->ops.write_buffer(hw,  first, length, data);
6211 }
6212
6213 uint16_t
6214 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6215         switch (mac_type) {
6216         case ixgbe_mac_X550:
6217         case ixgbe_mac_X550EM_x:
6218         case ixgbe_mac_X550EM_a:
6219                 return ETH_RSS_RETA_SIZE_512;
6220         case ixgbe_mac_X550_vf:
6221         case ixgbe_mac_X550EM_x_vf:
6222         case ixgbe_mac_X550EM_a_vf:
6223                 return ETH_RSS_RETA_SIZE_64;
6224         default:
6225                 return ETH_RSS_RETA_SIZE_128;
6226         }
6227 }
6228
6229 uint32_t
6230 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6231         switch (mac_type) {
6232         case ixgbe_mac_X550:
6233         case ixgbe_mac_X550EM_x:
6234         case ixgbe_mac_X550EM_a:
6235                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6236                         return IXGBE_RETA(reta_idx >> 2);
6237                 else
6238                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6239         case ixgbe_mac_X550_vf:
6240         case ixgbe_mac_X550EM_x_vf:
6241         case ixgbe_mac_X550EM_a_vf:
6242                 return IXGBE_VFRETA(reta_idx >> 2);
6243         default:
6244                 return IXGBE_RETA(reta_idx >> 2);
6245         }
6246 }
6247
6248 uint32_t
6249 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6250         switch (mac_type) {
6251         case ixgbe_mac_X550_vf:
6252         case ixgbe_mac_X550EM_x_vf:
6253         case ixgbe_mac_X550EM_a_vf:
6254                 return IXGBE_VFMRQC;
6255         default:
6256                 return IXGBE_MRQC;
6257         }
6258 }
6259
6260 uint32_t
6261 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6262         switch (mac_type) {
6263         case ixgbe_mac_X550_vf:
6264         case ixgbe_mac_X550EM_x_vf:
6265         case ixgbe_mac_X550EM_a_vf:
6266                 return IXGBE_VFRSSRK(i);
6267         default:
6268                 return IXGBE_RSSRK(i);
6269         }
6270 }
6271
6272 bool
6273 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6274         switch (mac_type) {
6275         case ixgbe_mac_82599_vf:
6276         case ixgbe_mac_X540_vf:
6277                 return 0;
6278         default:
6279                 return 1;
6280         }
6281 }
6282
6283 static int
6284 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6285                         struct rte_eth_dcb_info *dcb_info)
6286 {
6287         struct ixgbe_dcb_config *dcb_config =
6288                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6289         struct ixgbe_dcb_tc_config *tc;
6290         uint8_t i, j;
6291
6292         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6293                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6294         else
6295                 dcb_info->nb_tcs = 1;
6296
6297         if (dcb_config->vt_mode) { /* vt is enabled*/
6298                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6299                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6300                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6301                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6302                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6303                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6304                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6305                                                 i * dcb_info->nb_tcs + j;
6306                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6307                                 dcb_info->tc_queue.tc_txq[i][j].base =
6308                                                 i * dcb_info->nb_tcs + j;
6309                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6310                         }
6311                 }
6312         } else { /* vt is disabled*/
6313                 struct rte_eth_dcb_rx_conf *rx_conf =
6314                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6315                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6316                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6317                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6318                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6319                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6320                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6321                         }
6322                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6323                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6324                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6325                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6326                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6327                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6328                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6329                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6330                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6331                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6332                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6333                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6334                         }
6335                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6336                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6337                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6338                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6339                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6340                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6341                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6342                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6343                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6344                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6345                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6346                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6347                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6348                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6349                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6350                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6351                 }
6352         }
6353         for (i = 0; i < dcb_info->nb_tcs; i++) {
6354                 tc = &dcb_config->tc_config[i];
6355                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6356         }
6357         return 0;
6358 }
6359
6360 /* Update e-tag ether type */
6361 static int
6362 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6363                             uint16_t ether_type)
6364 {
6365         uint32_t etag_etype;
6366
6367         if (hw->mac.type != ixgbe_mac_X550 &&
6368             hw->mac.type != ixgbe_mac_X550EM_x) {
6369                 return -ENOTSUP;
6370         }
6371
6372         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6373         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6374         etag_etype |= ether_type;
6375         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6376         IXGBE_WRITE_FLUSH(hw);
6377
6378         return 0;
6379 }
6380
6381 /* Config l2 tunnel ether type */
6382 static int
6383 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6384                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6385 {
6386         int ret = 0;
6387         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6388
6389         if (l2_tunnel == NULL)
6390                 return -EINVAL;
6391
6392         switch (l2_tunnel->l2_tunnel_type) {
6393         case RTE_L2_TUNNEL_TYPE_E_TAG:
6394                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6395                 break;
6396         default:
6397                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6398                 ret = -EINVAL;
6399                 break;
6400         }
6401
6402         return ret;
6403 }
6404
6405 /* Enable e-tag tunnel */
6406 static int
6407 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6408 {
6409         uint32_t etag_etype;
6410
6411         if (hw->mac.type != ixgbe_mac_X550 &&
6412             hw->mac.type != ixgbe_mac_X550EM_x) {
6413                 return -ENOTSUP;
6414         }
6415
6416         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6417         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6418         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6419         IXGBE_WRITE_FLUSH(hw);
6420
6421         return 0;
6422 }
6423
6424 /* Enable l2 tunnel */
6425 static int
6426 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6427                            enum rte_eth_tunnel_type l2_tunnel_type)
6428 {
6429         int ret = 0;
6430         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6431
6432         switch (l2_tunnel_type) {
6433         case RTE_L2_TUNNEL_TYPE_E_TAG:
6434                 ret = ixgbe_e_tag_enable(hw);
6435                 break;
6436         default:
6437                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6438                 ret = -EINVAL;
6439                 break;
6440         }
6441
6442         return ret;
6443 }
6444
6445 /* Disable e-tag tunnel */
6446 static int
6447 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6448 {
6449         uint32_t etag_etype;
6450
6451         if (hw->mac.type != ixgbe_mac_X550 &&
6452             hw->mac.type != ixgbe_mac_X550EM_x) {
6453                 return -ENOTSUP;
6454         }
6455
6456         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6457         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6458         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6459         IXGBE_WRITE_FLUSH(hw);
6460
6461         return 0;
6462 }
6463
6464 /* Disable l2 tunnel */
6465 static int
6466 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6467                             enum rte_eth_tunnel_type l2_tunnel_type)
6468 {
6469         int ret = 0;
6470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6471
6472         switch (l2_tunnel_type) {
6473         case RTE_L2_TUNNEL_TYPE_E_TAG:
6474                 ret = ixgbe_e_tag_disable(hw);
6475                 break;
6476         default:
6477                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6478                 ret = -EINVAL;
6479                 break;
6480         }
6481
6482         return ret;
6483 }
6484
6485 static int
6486 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6487                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6488 {
6489         int ret = 0;
6490         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6491         uint32_t i, rar_entries;
6492         uint32_t rar_low, rar_high;
6493
6494         if (hw->mac.type != ixgbe_mac_X550 &&
6495             hw->mac.type != ixgbe_mac_X550EM_x) {
6496                 return -ENOTSUP;
6497         }
6498
6499         rar_entries = ixgbe_get_num_rx_addrs(hw);
6500
6501         for (i = 1; i < rar_entries; i++) {
6502                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6503                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6504                 if ((rar_high & IXGBE_RAH_AV) &&
6505                     (rar_high & IXGBE_RAH_ADTYPE) &&
6506                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6507                      l2_tunnel->tunnel_id)) {
6508                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6509                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6510
6511                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6512
6513                         return ret;
6514                 }
6515         }
6516
6517         return ret;
6518 }
6519
6520 static int
6521 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6522                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6523 {
6524         int ret = 0;
6525         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6526         uint32_t i, rar_entries;
6527         uint32_t rar_low, rar_high;
6528
6529         if (hw->mac.type != ixgbe_mac_X550 &&
6530             hw->mac.type != ixgbe_mac_X550EM_x) {
6531                 return -ENOTSUP;
6532         }
6533
6534         /* One entry for one tunnel. Try to remove potential existing entry. */
6535         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6536
6537         rar_entries = ixgbe_get_num_rx_addrs(hw);
6538
6539         for (i = 1; i < rar_entries; i++) {
6540                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6541                 if (rar_high & IXGBE_RAH_AV) {
6542                         continue;
6543                 } else {
6544                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6545                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6546                         rar_low = l2_tunnel->tunnel_id;
6547
6548                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6549                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6550
6551                         return ret;
6552                 }
6553         }
6554
6555         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6556                      " Please remove a rule before adding a new one.");
6557         return -EINVAL;
6558 }
6559
6560 /* Add l2 tunnel filter */
6561 static int
6562 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6563                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6564 {
6565         int ret = 0;
6566
6567         switch (l2_tunnel->l2_tunnel_type) {
6568         case RTE_L2_TUNNEL_TYPE_E_TAG:
6569                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6570                 break;
6571         default:
6572                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6573                 ret = -EINVAL;
6574                 break;
6575         }
6576
6577         return ret;
6578 }
6579
6580 /* Delete l2 tunnel filter */
6581 static int
6582 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6583                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6584 {
6585         int ret = 0;
6586
6587         switch (l2_tunnel->l2_tunnel_type) {
6588         case RTE_L2_TUNNEL_TYPE_E_TAG:
6589                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6590                 break;
6591         default:
6592                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6593                 ret = -EINVAL;
6594                 break;
6595         }
6596
6597         return ret;
6598 }
6599
6600 /**
6601  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6602  * @dev: pointer to rte_eth_dev structure
6603  * @filter_op:operation will be taken.
6604  * @arg: a pointer to specific structure corresponding to the filter_op
6605  */
6606 static int
6607 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6608                                   enum rte_filter_op filter_op,
6609                                   void *arg)
6610 {
6611         int ret = 0;
6612
6613         if (filter_op == RTE_ETH_FILTER_NOP)
6614                 return 0;
6615
6616         if (arg == NULL) {
6617                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6618                             filter_op);
6619                 return -EINVAL;
6620         }
6621
6622         switch (filter_op) {
6623         case RTE_ETH_FILTER_ADD:
6624                 ret = ixgbe_dev_l2_tunnel_filter_add
6625                         (dev,
6626                          (struct rte_eth_l2_tunnel_conf *)arg);
6627                 break;
6628         case RTE_ETH_FILTER_DELETE:
6629                 ret = ixgbe_dev_l2_tunnel_filter_del
6630                         (dev,
6631                          (struct rte_eth_l2_tunnel_conf *)arg);
6632                 break;
6633         default:
6634                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6635                 ret = -EINVAL;
6636                 break;
6637         }
6638         return ret;
6639 }
6640
6641 static int
6642 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6643 {
6644         int ret = 0;
6645         uint32_t ctrl;
6646         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6647
6648         if (hw->mac.type != ixgbe_mac_X550 &&
6649             hw->mac.type != ixgbe_mac_X550EM_x) {
6650                 return -ENOTSUP;
6651         }
6652
6653         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6654         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6655         if (en)
6656                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6657         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6658
6659         return ret;
6660 }
6661
6662 /* Enable l2 tunnel forwarding */
6663 static int
6664 ixgbe_dev_l2_tunnel_forwarding_enable
6665         (struct rte_eth_dev *dev,
6666          enum rte_eth_tunnel_type l2_tunnel_type)
6667 {
6668         int ret = 0;
6669
6670         switch (l2_tunnel_type) {
6671         case RTE_L2_TUNNEL_TYPE_E_TAG:
6672                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6673                 break;
6674         default:
6675                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6676                 ret = -EINVAL;
6677                 break;
6678         }
6679
6680         return ret;
6681 }
6682
6683 /* Disable l2 tunnel forwarding */
6684 static int
6685 ixgbe_dev_l2_tunnel_forwarding_disable
6686         (struct rte_eth_dev *dev,
6687          enum rte_eth_tunnel_type l2_tunnel_type)
6688 {
6689         int ret = 0;
6690
6691         switch (l2_tunnel_type) {
6692         case RTE_L2_TUNNEL_TYPE_E_TAG:
6693                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6694                 break;
6695         default:
6696                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6697                 ret = -EINVAL;
6698                 break;
6699         }
6700
6701         return ret;
6702 }
6703
6704 static int
6705 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6706                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6707                              bool en)
6708 {
6709         int ret = 0;
6710         uint32_t vmtir, vmvir;
6711         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6712
6713         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6714                 PMD_DRV_LOG(ERR,
6715                             "VF id %u should be less than %u",
6716                             l2_tunnel->vf_id,
6717                             dev->pci_dev->max_vfs);
6718                 return -EINVAL;
6719         }
6720
6721         if (hw->mac.type != ixgbe_mac_X550 &&
6722             hw->mac.type != ixgbe_mac_X550EM_x) {
6723                 return -ENOTSUP;
6724         }
6725
6726         if (en)
6727                 vmtir = l2_tunnel->tunnel_id;
6728         else
6729                 vmtir = 0;
6730
6731         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6732
6733         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6734         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6735         if (en)
6736                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6737         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6738
6739         return ret;
6740 }
6741
6742 /* Enable l2 tunnel tag insertion */
6743 static int
6744 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6745                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6746 {
6747         int ret = 0;
6748
6749         switch (l2_tunnel->l2_tunnel_type) {
6750         case RTE_L2_TUNNEL_TYPE_E_TAG:
6751                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6752                 break;
6753         default:
6754                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6755                 ret = -EINVAL;
6756                 break;
6757         }
6758
6759         return ret;
6760 }
6761
6762 /* Disable l2 tunnel tag insertion */
6763 static int
6764 ixgbe_dev_l2_tunnel_insertion_disable
6765         (struct rte_eth_dev *dev,
6766          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6767 {
6768         int ret = 0;
6769
6770         switch (l2_tunnel->l2_tunnel_type) {
6771         case RTE_L2_TUNNEL_TYPE_E_TAG:
6772                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6773                 break;
6774         default:
6775                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6776                 ret = -EINVAL;
6777                 break;
6778         }
6779
6780         return ret;
6781 }
6782
6783 static int
6784 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6785                              bool en)
6786 {
6787         int ret = 0;
6788         uint32_t qde;
6789         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6790
6791         if (hw->mac.type != ixgbe_mac_X550 &&
6792             hw->mac.type != ixgbe_mac_X550EM_x) {
6793                 return -ENOTSUP;
6794         }
6795
6796         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6797         if (en)
6798                 qde |= IXGBE_QDE_STRIP_TAG;
6799         else
6800                 qde &= ~IXGBE_QDE_STRIP_TAG;
6801         qde &= ~IXGBE_QDE_READ;
6802         qde |= IXGBE_QDE_WRITE;
6803         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6804
6805         return ret;
6806 }
6807
6808 /* Enable l2 tunnel tag stripping */
6809 static int
6810 ixgbe_dev_l2_tunnel_stripping_enable
6811         (struct rte_eth_dev *dev,
6812          enum rte_eth_tunnel_type l2_tunnel_type)
6813 {
6814         int ret = 0;
6815
6816         switch (l2_tunnel_type) {
6817         case RTE_L2_TUNNEL_TYPE_E_TAG:
6818                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6819                 break;
6820         default:
6821                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6822                 ret = -EINVAL;
6823                 break;
6824         }
6825
6826         return ret;
6827 }
6828
6829 /* Disable l2 tunnel tag stripping */
6830 static int
6831 ixgbe_dev_l2_tunnel_stripping_disable
6832         (struct rte_eth_dev *dev,
6833          enum rte_eth_tunnel_type l2_tunnel_type)
6834 {
6835         int ret = 0;
6836
6837         switch (l2_tunnel_type) {
6838         case RTE_L2_TUNNEL_TYPE_E_TAG:
6839                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6840                 break;
6841         default:
6842                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6843                 ret = -EINVAL;
6844                 break;
6845         }
6846
6847         return ret;
6848 }
6849
6850 /* Enable/disable l2 tunnel offload functions */
6851 static int
6852 ixgbe_dev_l2_tunnel_offload_set
6853         (struct rte_eth_dev *dev,
6854          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6855          uint32_t mask,
6856          uint8_t en)
6857 {
6858         int ret = 0;
6859
6860         if (l2_tunnel == NULL)
6861                 return -EINVAL;
6862
6863         ret = -EINVAL;
6864         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6865                 if (en)
6866                         ret = ixgbe_dev_l2_tunnel_enable(
6867                                 dev,
6868                                 l2_tunnel->l2_tunnel_type);
6869                 else
6870                         ret = ixgbe_dev_l2_tunnel_disable(
6871                                 dev,
6872                                 l2_tunnel->l2_tunnel_type);
6873         }
6874
6875         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6876                 if (en)
6877                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6878                                 dev,
6879                                 l2_tunnel);
6880                 else
6881                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6882                                 dev,
6883                                 l2_tunnel);
6884         }
6885
6886         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6887                 if (en)
6888                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6889                                 dev,
6890                                 l2_tunnel->l2_tunnel_type);
6891                 else
6892                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6893                                 dev,
6894                                 l2_tunnel->l2_tunnel_type);
6895         }
6896
6897         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6898                 if (en)
6899                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6900                                 dev,
6901                                 l2_tunnel->l2_tunnel_type);
6902                 else
6903                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6904                                 dev,
6905                                 l2_tunnel->l2_tunnel_type);
6906         }
6907
6908         return ret;
6909 }
6910
6911 static int
6912 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6913                         uint16_t port)
6914 {
6915         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6916         IXGBE_WRITE_FLUSH(hw);
6917
6918         return 0;
6919 }
6920
6921 /* There's only one register for VxLAN UDP port.
6922  * So, we cannot add several ports. Will update it.
6923  */
6924 static int
6925 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6926                      uint16_t port)
6927 {
6928         if (port == 0) {
6929                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6930                 return -EINVAL;
6931         }
6932
6933         return ixgbe_update_vxlan_port(hw, port);
6934 }
6935
6936 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6937  * UDP port, it must have a value.
6938  * So, will reset it to the original value 0.
6939  */
6940 static int
6941 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6942                      uint16_t port)
6943 {
6944         uint16_t cur_port;
6945
6946         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6947
6948         if (cur_port != port) {
6949                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6950                 return -EINVAL;
6951         }
6952
6953         return ixgbe_update_vxlan_port(hw, 0);
6954 }
6955
6956 /* Add UDP tunneling port */
6957 static int
6958 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6959                               struct rte_eth_udp_tunnel *udp_tunnel)
6960 {
6961         int ret = 0;
6962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6963
6964         if (hw->mac.type != ixgbe_mac_X550 &&
6965             hw->mac.type != ixgbe_mac_X550EM_x) {
6966                 return -ENOTSUP;
6967         }
6968
6969         if (udp_tunnel == NULL)
6970                 return -EINVAL;
6971
6972         switch (udp_tunnel->prot_type) {
6973         case RTE_TUNNEL_TYPE_VXLAN:
6974                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6975                 break;
6976
6977         case RTE_TUNNEL_TYPE_GENEVE:
6978         case RTE_TUNNEL_TYPE_TEREDO:
6979                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6980                 ret = -EINVAL;
6981                 break;
6982
6983         default:
6984                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6985                 ret = -EINVAL;
6986                 break;
6987         }
6988
6989         return ret;
6990 }
6991
6992 /* Remove UDP tunneling port */
6993 static int
6994 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6995                               struct rte_eth_udp_tunnel *udp_tunnel)
6996 {
6997         int ret = 0;
6998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6999
7000         if (hw->mac.type != ixgbe_mac_X550 &&
7001             hw->mac.type != ixgbe_mac_X550EM_x) {
7002                 return -ENOTSUP;
7003         }
7004
7005         if (udp_tunnel == NULL)
7006                 return -EINVAL;
7007
7008         switch (udp_tunnel->prot_type) {
7009         case RTE_TUNNEL_TYPE_VXLAN:
7010                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7011                 break;
7012         case RTE_TUNNEL_TYPE_GENEVE:
7013         case RTE_TUNNEL_TYPE_TEREDO:
7014                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7015                 ret = -EINVAL;
7016                 break;
7017         default:
7018                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7019                 ret = -EINVAL;
7020                 break;
7021         }
7022
7023         return ret;
7024 }
7025
7026 /* ixgbevf_update_xcast_mode - Update Multicast mode
7027  * @hw: pointer to the HW structure
7028  * @netdev: pointer to net device structure
7029  * @xcast_mode: new multicast mode
7030  *
7031  * Updates the Multicast Mode of VF.
7032  */
7033 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7034                                      int xcast_mode)
7035 {
7036         struct ixgbe_mbx_info *mbx = &hw->mbx;
7037         u32 msgbuf[2];
7038         s32 err;
7039
7040         switch (hw->api_version) {
7041         case ixgbe_mbox_api_12:
7042                 break;
7043         default:
7044                 return -EOPNOTSUPP;
7045         }
7046
7047         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7048         msgbuf[1] = xcast_mode;
7049
7050         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7051         if (err)
7052                 return err;
7053
7054         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7055         if (err)
7056                 return err;
7057
7058         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7059         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7060                 return -EPERM;
7061
7062         return 0;
7063 }
7064
7065 static void
7066 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7067 {
7068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7069
7070         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7071 }
7072
7073 static void
7074 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7075 {
7076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7077
7078         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7079 }
7080
7081 static struct rte_driver rte_ixgbe_driver = {
7082         .type = PMD_PDEV,
7083         .init = rte_ixgbe_pmd_init,
7084 };
7085
7086 static struct rte_driver rte_ixgbevf_driver = {
7087         .type = PMD_PDEV,
7088         .init = rte_ixgbevf_pmd_init,
7089 };
7090
7091 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7092 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);