drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153 #define IXGBE_VTEICR_MASK                      0x07
 154
 155 enum ixgbevf_xcast_modes {
 156         IXGBEVF_XCAST_MODE_NONE = 0,
 157         IXGBEVF_XCAST_MODE_MULTI,
 158         IXGBEVF_XCAST_MODE_ALLMULTI,
 159 };
 160
 161 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 162 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 163
 164 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 165 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 166 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 167 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 177                                 int wait_to_complete);
 178 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 179                                 struct rte_eth_stats *stats);
 180 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_xstat *xstats, unsigned n);
 182 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 183                                   struct rte_eth_xstat *xstats, unsigned n);
 184 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 185 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 186 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 187         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 188 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 191                                              uint16_t queue_id,
 192                                              uint8_t stat_idx,
 193                                              uint8_t is_rx);
 194 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 195                                struct rte_eth_dev_info *dev_info);
 196 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 197 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 198                                  struct rte_eth_dev_info *dev_info);
 199 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 200
 201 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 202                 uint16_t vlan_id, int on);
 203 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 204                                enum rte_vlan_type vlan_type,
 205                                uint16_t tpid_id);
 206 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 207                 uint16_t queue, bool on);
 208 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 209                 int on);
 210 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 211 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 212 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 213 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 214 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 215
 216 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 218 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 219                                struct rte_eth_fc_conf *fc_conf);
 220 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 223                 struct rte_eth_pfc_conf *pfc_conf);
 224 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 225                         struct rte_eth_rss_reta_entry64 *reta_conf,
 226                         uint16_t reta_size);
 227 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 228                         struct rte_eth_rss_reta_entry64 *reta_conf,
 229                         uint16_t reta_size);
 230 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 231 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 232 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 235 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 236                 void *param);
 237 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 238 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 239                 uint32_t index, uint32_t pool);
 240 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 241 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 242                                            struct ether_addr *mac_addr);
 243 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 244
 245 /* For Virtual Function support */
 246 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 249 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 250 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 251 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 252 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 253 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 254 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 255                 struct rte_eth_stats *stats);
 256 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 257 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 258                 uint16_t vlan_id, int on);
 259 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 260                 uint16_t queue, int on);
 261 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 262 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 263 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 264                                             uint16_t queue_id);
 265 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 266                                              uint16_t queue_id);
 267 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 268                                  uint8_t queue, uint8_t msix_vector);
 269 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 270 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 271 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 272
 273 /* For Eth VMDQ APIs support */
 274 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 275                 ether_addr * mac_addr, uint8_t on);
 276 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 277 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 278                 uint16_t rx_mask, uint8_t on);
 279 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 280 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 281 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 282                 uint64_t pool_mask, uint8_t vlan_on);
 283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 284                 struct rte_eth_mirror_conf *mirror_conf,
 285                 uint8_t rule_id, uint8_t on);
 286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 287                 uint8_t rule_id);
 288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 289                                           uint16_t queue_id);
 290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 291                                            uint16_t queue_id);
 292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 293                                uint8_t queue, uint8_t msix_vector);
 294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 295
 296 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 297                 uint16_t queue_idx, uint16_t tx_rate);
 298 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 299                 uint16_t tx_rate, uint64_t q_msk);
 300
 301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 302                                  struct ether_addr *mac_addr,
 303                                  uint32_t index, uint32_t pool);
 304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 306                                              struct ether_addr *mac_addr);
 307 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 308                         struct rte_eth_syn_filter *filter,
 309                         bool add);
 310 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 311                         struct rte_eth_syn_filter *filter);
 312 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 313                         enum rte_filter_op filter_op,
 314                         void *arg);
 315 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 316                         struct ixgbe_5tuple_filter *filter);
 317 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 318                         struct ixgbe_5tuple_filter *filter);
 319 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ntuple_filter *filter,
 321                         bool add);
 322 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ntuple_filter *filter);
 327 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 328                         struct rte_eth_ethertype_filter *filter,
 329                         bool add);
 330 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 331                                 enum rte_filter_op filter_op,
 332                                 void *arg);
 333 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 334                         struct rte_eth_ethertype_filter *filter);
 335 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 336                      enum rte_filter_type filter_type,
 337                      enum rte_filter_op filter_op,
 338                      void *arg);
 339 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 340
 341 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 342                                       struct ether_addr *mc_addr_set,
 343                                       uint32_t nb_mc_addr);
 344 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 345                                    struct rte_eth_dcb_info *dcb_info);
 346
 347 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 349                             struct rte_dev_reg_info *regs);
 350 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 351 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 354                                 struct rte_dev_eeprom_info *eeprom);
 355
 356 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 357 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 358                                 struct rte_dev_reg_info *regs);
 359
 360 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 361 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 362 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 363                                             struct timespec *timestamp,
 364                                             uint32_t flags);
 365 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 366                                             struct timespec *timestamp);
 367 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 368 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 369                                    struct timespec *timestamp);
 370 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 371                                    const struct timespec *timestamp);
 372 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 373                                           void *param);
 374
 375 static int ixgbe_dev_l2_tunnel_eth_type_conf
 376         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 377 static int ixgbe_dev_l2_tunnel_offload_set
 378         (struct rte_eth_dev *dev,
 379          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 380          uint32_t mask,
 381          uint8_t en);
 382 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 383                                              enum rte_filter_op filter_op,
 384                                              void *arg);
 385
 386 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 387                                          struct rte_eth_udp_tunnel *udp_tunnel);
 388 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 389                                          struct rte_eth_udp_tunnel *udp_tunnel);
 390
 391 /*
 392  * Define VF Stats MACRO for Non "cleared on read" register
 393  */
 394 #define UPDATE_VF_STAT(reg, last, cur)                          \
 395 {                                                               \
 396         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 397         cur += (latest - last) & UINT_MAX;                      \
 398         last = latest;                                          \
 399 }
 400
 401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 402 {                                                                \
 403         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 404         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 405         u64 latest = ((new_msb << 32) | new_lsb);                \
 406         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 407         last = latest;                                           \
 408 }
 409
 410 #define IXGBE_SET_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] |= 1 << bit;\
 414         } while (0)
 415
 416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (h)->bitmap[idx] &= ~(1 << bit);\
 420         } while (0)
 421
 422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 423                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 424                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 425                 (r) = (h)->bitmap[idx] >> bit & 1;\
 426         } while (0)
 427
 428 /*
 429  * The set of PCI devices this driver supports
 430  */
 431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 485 #ifdef RTE_NIC_BYPASS
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 487 #endif
 488         { .vendor_id = 0, /* sentinel */ },
 489 };
 490
 491 /*
 492  * The set of PCI devices this driver supports (for 82599 VF)
 493  */
 494 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 505         { .vendor_id = 0, /* sentinel */ },
 506 };
 507
 508 static const struct rte_eth_desc_lim rx_desc_lim = {
 509         .nb_max = IXGBE_MAX_RING_DESC,
 510         .nb_min = IXGBE_MIN_RING_DESC,
 511         .nb_align = IXGBE_RXD_ALIGN,
 512 };
 513
 514 static const struct rte_eth_desc_lim tx_desc_lim = {
 515         .nb_max = IXGBE_MAX_RING_DESC,
 516         .nb_min = IXGBE_MIN_RING_DESC,
 517         .nb_align = IXGBE_TXD_ALIGN,
 518 };
 519
 520 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 521         .dev_configure        = ixgbe_dev_configure,
 522         .dev_start            = ixgbe_dev_start,
 523         .dev_stop             = ixgbe_dev_stop,
 524         .dev_set_link_up    = ixgbe_dev_set_link_up,
 525         .dev_set_link_down  = ixgbe_dev_set_link_down,
 526         .dev_close            = ixgbe_dev_close,
 527         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 528         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 529         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 530         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 531         .link_update          = ixgbe_dev_link_update,
 532         .stats_get            = ixgbe_dev_stats_get,
 533         .xstats_get           = ixgbe_dev_xstats_get,
 534         .stats_reset          = ixgbe_dev_stats_reset,
 535         .xstats_reset         = ixgbe_dev_xstats_reset,
 536         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 537         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 538         .dev_infos_get        = ixgbe_dev_info_get,
 539         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 540         .mtu_set              = ixgbe_dev_mtu_set,
 541         .vlan_filter_set      = ixgbe_vlan_filter_set,
 542         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 543         .vlan_offload_set     = ixgbe_vlan_offload_set,
 544         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 545         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 546         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 547         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 548         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 549         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 550         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 551         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 552         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 553         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 554         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 555         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 556         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 557         .dev_led_on           = ixgbe_dev_led_on,
 558         .dev_led_off          = ixgbe_dev_led_off,
 559         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 560         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 561         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 562         .mac_addr_add         = ixgbe_add_rar,
 563         .mac_addr_remove      = ixgbe_remove_rar,
 564         .mac_addr_set         = ixgbe_set_default_mac_addr,
 565         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 566         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 567         .mirror_rule_set      = ixgbe_mirror_rule_set,
 568         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 569         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 570         .set_vf_rx            = ixgbe_set_pool_rx,
 571         .set_vf_tx            = ixgbe_set_pool_tx,
 572         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 573         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 574         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 575         .reta_update          = ixgbe_dev_rss_reta_update,
 576         .reta_query           = ixgbe_dev_rss_reta_query,
 577 #ifdef RTE_NIC_BYPASS
 578         .bypass_init          = ixgbe_bypass_init,
 579         .bypass_state_set     = ixgbe_bypass_state_store,
 580         .bypass_state_show    = ixgbe_bypass_state_show,
 581         .bypass_event_set     = ixgbe_bypass_event_store,
 582         .bypass_event_show    = ixgbe_bypass_event_show,
 583         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 584         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 585         .bypass_ver_show      = ixgbe_bypass_ver_show,
 586         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 587 #endif /* RTE_NIC_BYPASS */
 588         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 589         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 590         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 591         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 592         .rxq_info_get         = ixgbe_rxq_info_get,
 593         .txq_info_get         = ixgbe_txq_info_get,
 594         .timesync_enable      = ixgbe_timesync_enable,
 595         .timesync_disable     = ixgbe_timesync_disable,
 596         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 597         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 598         .get_reg              = ixgbe_get_regs,
 599         .get_eeprom_length    = ixgbe_get_eeprom_length,
 600         .get_eeprom           = ixgbe_get_eeprom,
 601         .set_eeprom           = ixgbe_set_eeprom,
 602         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 603         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 604         .timesync_read_time   = ixgbe_timesync_read_time,
 605         .timesync_write_time  = ixgbe_timesync_write_time,
 606         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 607         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 608         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 609         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 610 };
 611
 612 /*
 613  * dev_ops for virtual function, bare necessities for basic vf
 614  * operation have been implemented
 615  */
 616 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 617         .dev_configure        = ixgbevf_dev_configure,
 618         .dev_start            = ixgbevf_dev_start,
 619         .dev_stop             = ixgbevf_dev_stop,
 620         .link_update          = ixgbe_dev_link_update,
 621         .stats_get            = ixgbevf_dev_stats_get,
 622         .xstats_get           = ixgbevf_dev_xstats_get,
 623         .stats_reset          = ixgbevf_dev_stats_reset,
 624         .xstats_reset         = ixgbevf_dev_stats_reset,
 625         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 626         .dev_close            = ixgbevf_dev_close,
 627         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 628         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 629         .dev_infos_get        = ixgbevf_dev_info_get,
 630         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 631         .mtu_set              = ixgbevf_dev_set_mtu,
 632         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 633         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 634         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 635         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 636         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 637         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 638         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 639         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 640         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 641         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 642         .mac_addr_add         = ixgbevf_add_mac_addr,
 643         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 644         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 645         .rxq_info_get         = ixgbe_rxq_info_get,
 646         .txq_info_get         = ixgbe_txq_info_get,
 647         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 648         .get_reg              = ixgbevf_get_regs,
 649         .reta_update          = ixgbe_dev_rss_reta_update,
 650         .reta_query           = ixgbe_dev_rss_reta_query,
 651         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 652         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 653 };
 654
 655 /* store statistics names and its offset in stats structure */
 656 struct rte_ixgbe_xstats_name_off {
 657         char name[RTE_ETH_XSTATS_NAME_SIZE];
 658         unsigned offset;
 659 };
 660
 661 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 662         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 663         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 664         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 665         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 666         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 667         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 668         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 669         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 670         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 671         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 672         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 673         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 674         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 675         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 676         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 677                 prc1023)},
 678         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 679                 prc1522)},
 680         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 681         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 682         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 683         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 684         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 685         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 686         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 687         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 688         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 689         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 690         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 691         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 692         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 693         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 694         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 695         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 696         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 697                 ptc1023)},
 698         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 699                 ptc1522)},
 700         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 701         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 702         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 703         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 704
 705         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirustat_add)},
 707         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirustat_remove)},
 709         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 710                 fdirfstat_fadd)},
 711         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 712                 fdirfstat_fremove)},
 713         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 714                 fdirmatch)},
 715         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 716                 fdirmiss)},
 717
 718         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 719         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 720         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 721                 fclast)},
 722         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 723         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 724         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 725         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 726         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 727                 fcoe_noddp)},
 728         {"rx_fcoe_no_direct_data_placement_ext_buff",
 729                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 730
 731         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 732                 lxontxc)},
 733         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 734                 lxonrxc)},
 735         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 736                 lxofftxc)},
 737         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 738                 lxoffrxc)},
 739         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 740 };
 741
 742 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 743                            sizeof(rte_ixgbe_stats_strings[0]))
 744
 745 /* Per-queue statistics */
 746 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 747         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 748         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 749         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 750         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 751 };
 752
 753 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 754                            sizeof(rte_ixgbe_rxq_strings[0]))
 755 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 756
 757 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 758         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 759         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 760         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 761                 pxon2offc)},
 762 };
 763
 764 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 765                            sizeof(rte_ixgbe_txq_strings[0]))
 766 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 767
 768 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 769         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 770 };
 771
 772 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 773                 sizeof(rte_ixgbevf_stats_strings[0]))
 774
 775 /**
 776  * Atomically reads the link status information from global
 777  * structure rte_eth_dev.
 778  *
 779  * @param dev
 780  *   - Pointer to the structure rte_eth_dev to read from.
 781  *   - Pointer to the buffer to be saved with the link status.
 782  *
 783  * @return
 784  *   - On success, zero.
 785  *   - On failure, negative value.
 786  */
 787 static inline int
 788 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 789                                 struct rte_eth_link *link)
 790 {
 791         struct rte_eth_link *dst = link;
 792         struct rte_eth_link *src = &(dev->data->dev_link);
 793
 794         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 795                                         *(uint64_t *)src) == 0)
 796                 return -1;
 797
 798         return 0;
 799 }
 800
 801 /**
 802  * Atomically writes the link status information into global
 803  * structure rte_eth_dev.
 804  *
 805  * @param dev
 806  *   - Pointer to the structure rte_eth_dev to read from.
 807  *   - Pointer to the buffer to be saved with the link status.
 808  *
 809  * @return
 810  *   - On success, zero.
 811  *   - On failure, negative value.
 812  */
 813 static inline int
 814 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 815                                 struct rte_eth_link *link)
 816 {
 817         struct rte_eth_link *dst = &(dev->data->dev_link);
 818         struct rte_eth_link *src = link;
 819
 820         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 821                                         *(uint64_t *)src) == 0)
 822                 return -1;
 823
 824         return 0;
 825 }
 826
 827 /*
 828  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 829  */
 830 static inline int
 831 ixgbe_is_sfp(struct ixgbe_hw *hw)
 832 {
 833         switch (hw->phy.type) {
 834         case ixgbe_phy_sfp_avago:
 835         case ixgbe_phy_sfp_ftl:
 836         case ixgbe_phy_sfp_intel:
 837         case ixgbe_phy_sfp_unknown:
 838         case ixgbe_phy_sfp_passive_tyco:
 839         case ixgbe_phy_sfp_passive_unknown:
 840                 return 1;
 841         default:
 842                 return 0;
 843         }
 844 }
 845
 846 static inline int32_t
 847 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 848 {
 849         uint32_t ctrl_ext;
 850         int32_t status;
 851
 852         status = ixgbe_reset_hw(hw);
 853
 854         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 855         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 856         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 857         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 858         IXGBE_WRITE_FLUSH(hw);
 859
 860         return status;
 861 }
 862
 863 static inline void
 864 ixgbe_enable_intr(struct rte_eth_dev *dev)
 865 {
 866         struct ixgbe_interrupt *intr =
 867                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 868         struct ixgbe_hw *hw =
 869                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 870
 871         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 872         IXGBE_WRITE_FLUSH(hw);
 873 }
 874
 875 /*
 876  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 877  */
 878 static void
 879 ixgbe_disable_intr(struct ixgbe_hw *hw)
 880 {
 881         PMD_INIT_FUNC_TRACE();
 882
 883         if (hw->mac.type == ixgbe_mac_82598EB) {
 884                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 885         } else {
 886                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 887                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 888                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 889         }
 890         IXGBE_WRITE_FLUSH(hw);
 891 }
 892
 893 /*
 894  * This function resets queue statistics mapping registers.
 895  * From Niantic datasheet, Initialization of Statistics section:
 896  * "...if software requires the queue counters, the RQSMR and TQSM registers
 897  * must be re-programmed following a device reset.
 898  */
 899 static void
 900 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 901 {
 902         uint32_t i;
 903
 904         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 905                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 906                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 907         }
 908 }
 909
 910
 911 static int
 912 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 913                                   uint16_t queue_id,
 914                                   uint8_t stat_idx,
 915                                   uint8_t is_rx)
 916 {
 917 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 918 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 919 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 920
 921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 922         struct ixgbe_stat_mapping_registers *stat_mappings =
 923                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 924         uint32_t qsmr_mask = 0;
 925         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 926         uint32_t q_map;
 927         uint8_t n, offset;
 928
 929         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 930                 (hw->mac.type != ixgbe_mac_X540) &&
 931                 (hw->mac.type != ixgbe_mac_X550) &&
 932                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 933                 (hw->mac.type != ixgbe_mac_X550EM_a))
 934                 return -ENOSYS;
 935
 936         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 937                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 938                      queue_id, stat_idx);
 939
 940         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 941         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 942                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 943                 return -EIO;
 944         }
 945         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 946
 947         /* Now clear any previous stat_idx set */
 948         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 949         if (!is_rx)
 950                 stat_mappings->tqsm[n] &= ~clearing_mask;
 951         else
 952                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 953
 954         q_map = (uint32_t)stat_idx;
 955         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 956         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 957         if (!is_rx)
 958                 stat_mappings->tqsm[n] |= qsmr_mask;
 959         else
 960                 stat_mappings->rqsmr[n] |= qsmr_mask;
 961
 962         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 963                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 964                      queue_id, stat_idx);
 965         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 966                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 967
 968         /* Now write the mapping in the appropriate register */
 969         if (is_rx) {
 970                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 971                              stat_mappings->rqsmr[n], n);
 972                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 973         } else {
 974                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 975                              stat_mappings->tqsm[n], n);
 976                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 977         }
 978         return 0;
 979 }
 980
 981 static void
 982 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 983 {
 984         struct ixgbe_stat_mapping_registers *stat_mappings =
 985                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 987         int i;
 988
 989         /* write whatever was in stat mapping table to the NIC */
 990         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 991                 /* rx */
 992                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 993
 994                 /* tx */
 995                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 996         }
 997 }
 998
 999 static void
1000 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1001 {
1002         uint8_t i;
1003         struct ixgbe_dcb_tc_config *tc;
1004         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1005
1006         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1007         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1008         for (i = 0; i < dcb_max_tc; i++) {
1009                 tc = &dcb_config->tc_config[i];
1010                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1011                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1012                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1013                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1014                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1015                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1016                 tc->pfc = ixgbe_dcb_pfc_disabled;
1017         }
1018
1019         /* Initialize default user to priority mapping, UPx->TC0 */
1020         tc = &dcb_config->tc_config[0];
1021         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1022         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1023         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1024                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1025                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1026         }
1027         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1028         dcb_config->pfc_mode_enable = false;
1029         dcb_config->vt_mode = true;
1030         dcb_config->round_robin_enable = false;
1031         /* support all DCB capabilities in 82599 */
1032         dcb_config->support.capabilities = 0xFF;
1033
1034         /*we only support 4 Tcs for X540, X550 */
1035         if (hw->mac.type == ixgbe_mac_X540 ||
1036                 hw->mac.type == ixgbe_mac_X550 ||
1037                 hw->mac.type == ixgbe_mac_X550EM_x ||
1038                 hw->mac.type == ixgbe_mac_X550EM_a) {
1039                 dcb_config->num_tcs.pg_tcs = 4;
1040                 dcb_config->num_tcs.pfc_tcs = 4;
1041         }
1042 }
1043
1044 /*
1045  * Ensure that all locks are released before first NVM or PHY access
1046  */
1047 static void
1048 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1049 {
1050         uint16_t mask;
1051
1052         /*
1053          * Phy lock should not fail in this early stage. If this is the case,
1054          * it is due to an improper exit of the application.
1055          * So force the release of the faulty lock. Release of common lock
1056          * is done automatically by swfw_sync function.
1057          */
1058         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1059         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1060                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1061         }
1062         ixgbe_release_swfw_semaphore(hw, mask);
1063
1064         /*
1065          * These ones are more tricky since they are common to all ports; but
1066          * swfw_sync retries last long enough (1s) to be almost sure that if
1067          * lock can not be taken it is due to an improper lock of the
1068          * semaphore.
1069          */
1070         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1071         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1072                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1073         }
1074         ixgbe_release_swfw_semaphore(hw, mask);
1075 }
1076
1077 /*
1078  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1079  * It returns 0 on success.
1080  */
1081 static int
1082 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1083 {
1084         struct rte_pci_device *pci_dev;
1085         struct ixgbe_hw *hw =
1086                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1087         struct ixgbe_vfta *shadow_vfta =
1088                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1089         struct ixgbe_hwstrip *hwstrip =
1090                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1091         struct ixgbe_dcb_config *dcb_config =
1092                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1093         struct ixgbe_filter_info *filter_info =
1094                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1095         uint32_t ctrl_ext;
1096         uint16_t csum;
1097         int diag, i;
1098
1099         PMD_INIT_FUNC_TRACE();
1100
1101         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1102         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1103         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1104
1105         /*
1106          * For secondary processes, we don't initialise any further as primary
1107          * has already done this work. Only check we don't need a different
1108          * RX and TX function.
1109          */
1110         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1111                 struct ixgbe_tx_queue *txq;
1112                 /* TX queue function in primary, set by last queue initialized
1113                  * Tx queue may not initialized by primary process
1114                  */
1115                 if (eth_dev->data->tx_queues) {
1116                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1117                         ixgbe_set_tx_function(eth_dev, txq);
1118                 } else {
1119                         /* Use default TX function if we get here */
1120                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1121                                      "Using default TX function.");
1122                 }
1123
1124                 ixgbe_set_rx_function(eth_dev);
1125
1126                 return 0;
1127         }
1128         pci_dev = eth_dev->pci_dev;
1129
1130         rte_eth_copy_pci_info(eth_dev, pci_dev);
1131
1132         /* Vendor and Device ID need to be set before init of shared code */
1133         hw->device_id = pci_dev->id.device_id;
1134         hw->vendor_id = pci_dev->id.vendor_id;
1135         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1136         hw->allow_unsupported_sfp = 1;
1137
1138         /* Initialize the shared code (base driver) */
1139 #ifdef RTE_NIC_BYPASS
1140         diag = ixgbe_bypass_init_shared_code(hw);
1141 #else
1142         diag = ixgbe_init_shared_code(hw);
1143 #endif /* RTE_NIC_BYPASS */
1144
1145         if (diag != IXGBE_SUCCESS) {
1146                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1147                 return -EIO;
1148         }
1149
1150         /* pick up the PCI bus settings for reporting later */
1151         ixgbe_get_bus_info(hw);
1152
1153         /* Unlock any pending hardware semaphore */
1154         ixgbe_swfw_lock_reset(hw);
1155
1156         /* Initialize DCB configuration*/
1157         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1158         ixgbe_dcb_init(hw, dcb_config);
1159         /* Get Hardware Flow Control setting */
1160         hw->fc.requested_mode = ixgbe_fc_full;
1161         hw->fc.current_mode = ixgbe_fc_full;
1162         hw->fc.pause_time = IXGBE_FC_PAUSE;
1163         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1164                 hw->fc.low_water[i] = IXGBE_FC_LO;
1165                 hw->fc.high_water[i] = IXGBE_FC_HI;
1166         }
1167         hw->fc.send_xon = 1;
1168
1169         /* Make sure we have a good EEPROM before we read from it */
1170         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1171         if (diag != IXGBE_SUCCESS) {
1172                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1173                 return -EIO;
1174         }
1175
1176 #ifdef RTE_NIC_BYPASS
1177         diag = ixgbe_bypass_init_hw(hw);
1178 #else
1179         diag = ixgbe_init_hw(hw);
1180 #endif /* RTE_NIC_BYPASS */
1181
1182         /*
1183          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1184          * is called too soon after the kernel driver unbinding/binding occurs.
1185          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1186          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1187          * also called. See ixgbe_identify_phy_82599(). The reason for the
1188          * failure is not known, and only occuts when virtualisation features
1189          * are disabled in the bios. A delay of 100ms  was found to be enough by
1190          * trial-and-error, and is doubled to be safe.
1191          */
1192         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1193                 rte_delay_ms(200);
1194                 diag = ixgbe_init_hw(hw);
1195         }
1196
1197         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1198                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1199                              "LOM.  Please be aware there may be issues associated "
1200                              "with your hardware.");
1201                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1202                              "please contact your Intel or hardware representative "
1203                              "who provided you with this hardware.");
1204         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1205                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1206         if (diag) {
1207                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1208                 return -EIO;
1209         }
1210
1211         /* Reset the hw statistics */
1212         ixgbe_dev_stats_reset(eth_dev);
1213
1214         /* disable interrupt */
1215         ixgbe_disable_intr(hw);
1216
1217         /* reset mappings for queue statistics hw counters*/
1218         ixgbe_reset_qstat_mappings(hw);
1219
1220         /* Allocate memory for storing MAC addresses */
1221         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1222                                                hw->mac.num_rar_entries, 0);
1223         if (eth_dev->data->mac_addrs == NULL) {
1224                 PMD_INIT_LOG(ERR,
1225                              "Failed to allocate %u bytes needed to store "
1226                              "MAC addresses",
1227                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1228                 return -ENOMEM;
1229         }
1230         /* Copy the permanent MAC address */
1231         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1232                         &eth_dev->data->mac_addrs[0]);
1233
1234         /* Allocate memory for storing hash filter MAC addresses */
1235         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1236                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1237         if (eth_dev->data->hash_mac_addrs == NULL) {
1238                 PMD_INIT_LOG(ERR,
1239                              "Failed to allocate %d bytes needed to store MAC addresses",
1240                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1241                 return -ENOMEM;
1242         }
1243
1244         /* initialize the vfta */
1245         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1246
1247         /* initialize the hw strip bitmap*/
1248         memset(hwstrip, 0, sizeof(*hwstrip));
1249
1250         /* initialize PF if max_vfs not zero */
1251         ixgbe_pf_host_init(eth_dev);
1252
1253         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1254         /* let hardware know driver is loaded */
1255         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1256         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1257         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1258         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1259         IXGBE_WRITE_FLUSH(hw);
1260
1261         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1262                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1263                              (int) hw->mac.type, (int) hw->phy.type,
1264                              (int) hw->phy.sfp_type);
1265         else
1266                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1267                              (int) hw->mac.type, (int) hw->phy.type);
1268
1269         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1270                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1271                      pci_dev->id.device_id);
1272
1273         rte_intr_callback_register(&pci_dev->intr_handle,
1274                                    ixgbe_dev_interrupt_handler,
1275                                    (void *)eth_dev);
1276
1277         /* enable uio/vfio intr/eventfd mapping */
1278         rte_intr_enable(&pci_dev->intr_handle);
1279
1280         /* enable support intr */
1281         ixgbe_enable_intr(eth_dev);
1282
1283         /* initialize 5tuple filter list */
1284         TAILQ_INIT(&filter_info->fivetuple_list);
1285         memset(filter_info->fivetuple_mask, 0,
1286                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1287
1288         return 0;
1289 }
1290
1291 static int
1292 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1293 {
1294         struct rte_pci_device *pci_dev;
1295         struct ixgbe_hw *hw;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1300                 return -EPERM;
1301
1302         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1303         pci_dev = eth_dev->pci_dev;
1304
1305         if (hw->adapter_stopped == 0)
1306                 ixgbe_dev_close(eth_dev);
1307
1308         eth_dev->dev_ops = NULL;
1309         eth_dev->rx_pkt_burst = NULL;
1310         eth_dev->tx_pkt_burst = NULL;
1311
1312         /* Unlock any pending hardware semaphore */
1313         ixgbe_swfw_lock_reset(hw);
1314
1315         /* disable uio intr before callback unregister */
1316         rte_intr_disable(&(pci_dev->intr_handle));
1317         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1318                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1319
1320         /* uninitialize PF if max_vfs not zero */
1321         ixgbe_pf_host_uninit(eth_dev);
1322
1323         rte_free(eth_dev->data->mac_addrs);
1324         eth_dev->data->mac_addrs = NULL;
1325
1326         rte_free(eth_dev->data->hash_mac_addrs);
1327         eth_dev->data->hash_mac_addrs = NULL;
1328
1329         return 0;
1330 }
1331
1332 /*
1333  * Negotiate mailbox API version with the PF.
1334  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1335  * Then we try to negotiate starting with the most recent one.
1336  * If all negotiation attempts fail, then we will proceed with
1337  * the default one (ixgbe_mbox_api_10).
1338  */
1339 static void
1340 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1341 {
1342         int32_t i;
1343
1344         /* start with highest supported, proceed down */
1345         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1346                 ixgbe_mbox_api_12,
1347                 ixgbe_mbox_api_11,
1348                 ixgbe_mbox_api_10,
1349         };
1350
1351         for (i = 0;
1352                         i != RTE_DIM(sup_ver) &&
1353                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1354                         i++)
1355                 ;
1356 }
1357
1358 static void
1359 generate_random_mac_addr(struct ether_addr *mac_addr)
1360 {
1361         uint64_t random;
1362
1363         /* Set Organizationally Unique Identifier (OUI) prefix. */
1364         mac_addr->addr_bytes[0] = 0x00;
1365         mac_addr->addr_bytes[1] = 0x09;
1366         mac_addr->addr_bytes[2] = 0xC0;
1367         /* Force indication of locally assigned MAC address. */
1368         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1369         /* Generate the last 3 bytes of the MAC address with a random number. */
1370         random = rte_rand();
1371         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1372 }
1373
1374 /*
1375  * Virtual Function device init
1376  */
1377 static int
1378 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1379 {
1380         int diag;
1381         uint32_t tc, tcs;
1382         struct rte_pci_device *pci_dev;
1383         struct ixgbe_hw *hw =
1384                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1385         struct ixgbe_vfta *shadow_vfta =
1386                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1387         struct ixgbe_hwstrip *hwstrip =
1388                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1389         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1390
1391         PMD_INIT_FUNC_TRACE();
1392
1393         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1394         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1395         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1396
1397         /* for secondary processes, we don't initialise any further as primary
1398          * has already done this work. Only check we don't need a different
1399          * RX function
1400          */
1401         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1402                 struct ixgbe_tx_queue *txq;
1403                 /* TX queue function in primary, set by last queue initialized
1404                  * Tx queue may not initialized by primary process
1405                  */
1406                 if (eth_dev->data->tx_queues) {
1407                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1408                         ixgbe_set_tx_function(eth_dev, txq);
1409                 } else {
1410                         /* Use default TX function if we get here */
1411                         PMD_INIT_LOG(NOTICE,
1412                                      "No TX queues configured yet. Using default TX function.");
1413                 }
1414
1415                 ixgbe_set_rx_function(eth_dev);
1416
1417                 return 0;
1418         }
1419
1420         pci_dev = eth_dev->pci_dev;
1421
1422         rte_eth_copy_pci_info(eth_dev, pci_dev);
1423
1424         hw->device_id = pci_dev->id.device_id;
1425         hw->vendor_id = pci_dev->id.vendor_id;
1426         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1427
1428         /* initialize the vfta */
1429         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1430
1431         /* initialize the hw strip bitmap*/
1432         memset(hwstrip, 0, sizeof(*hwstrip));
1433
1434         /* Initialize the shared code (base driver) */
1435         diag = ixgbe_init_shared_code(hw);
1436         if (diag != IXGBE_SUCCESS) {
1437                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1438                 return -EIO;
1439         }
1440
1441         /* init_mailbox_params */
1442         hw->mbx.ops.init_params(hw);
1443
1444         /* Reset the hw statistics */
1445         ixgbevf_dev_stats_reset(eth_dev);
1446
1447         /* Disable the interrupts for VF */
1448         ixgbevf_intr_disable(hw);
1449
1450         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1451         diag = hw->mac.ops.reset_hw(hw);
1452
1453         /*
1454          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1455          * the underlying PF driver has not assigned a MAC address to the VF.
1456          * In this case, assign a random MAC address.
1457          */
1458         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1459                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1460                 return diag;
1461         }
1462
1463         /* negotiate mailbox API version to use with the PF. */
1464         ixgbevf_negotiate_api(hw);
1465
1466         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1467         ixgbevf_get_queues(hw, &tcs, &tc);
1468
1469         /* Allocate memory for storing MAC addresses */
1470         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1471                                                hw->mac.num_rar_entries, 0);
1472         if (eth_dev->data->mac_addrs == NULL) {
1473                 PMD_INIT_LOG(ERR,
1474                              "Failed to allocate %u bytes needed to store "
1475                              "MAC addresses",
1476                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1477                 return -ENOMEM;
1478         }
1479
1480         /* Generate a random MAC address, if none was assigned by PF. */
1481         if (is_zero_ether_addr(perm_addr)) {
1482                 generate_random_mac_addr(perm_addr);
1483                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1484                 if (diag) {
1485                         rte_free(eth_dev->data->mac_addrs);
1486                         eth_dev->data->mac_addrs = NULL;
1487                         return diag;
1488                 }
1489                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1490                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1491                              "%02x:%02x:%02x:%02x:%02x:%02x",
1492                              perm_addr->addr_bytes[0],
1493                              perm_addr->addr_bytes[1],
1494                              perm_addr->addr_bytes[2],
1495                              perm_addr->addr_bytes[3],
1496                              perm_addr->addr_bytes[4],
1497                              perm_addr->addr_bytes[5]);
1498         }
1499
1500         /* Copy the permanent MAC address */
1501         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1502
1503         /* reset the hardware with the new settings */
1504         diag = hw->mac.ops.start_hw(hw);
1505         switch (diag) {
1506         case  0:
1507                 break;
1508
1509         default:
1510                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1511                 return -EIO;
1512         }
1513
1514         rte_intr_callback_register(&pci_dev->intr_handle,
1515                                    ixgbevf_dev_interrupt_handler,
1516                                    (void *)eth_dev);
1517         rte_intr_enable(&pci_dev->intr_handle);
1518         ixgbevf_intr_enable(hw);
1519
1520         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1521                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1522                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1523
1524         return 0;
1525 }
1526
1527 /* Virtual Function device uninit */
1528
1529 static int
1530 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1531 {
1532         struct ixgbe_hw *hw;
1533         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1534
1535         PMD_INIT_FUNC_TRACE();
1536
1537         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1538                 return -EPERM;
1539
1540         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1541
1542         if (hw->adapter_stopped == 0)
1543                 ixgbevf_dev_close(eth_dev);
1544
1545         eth_dev->dev_ops = NULL;
1546         eth_dev->rx_pkt_burst = NULL;
1547         eth_dev->tx_pkt_burst = NULL;
1548
1549         /* Disable the interrupts for VF */
1550         ixgbevf_intr_disable(hw);
1551
1552         rte_free(eth_dev->data->mac_addrs);
1553         eth_dev->data->mac_addrs = NULL;
1554
1555         rte_intr_disable(&pci_dev->intr_handle);
1556         rte_intr_callback_unregister(&pci_dev->intr_handle,
1557                                      ixgbevf_dev_interrupt_handler,
1558                                      (void *)eth_dev);
1559
1560         return 0;
1561 }
1562
1563 static struct eth_driver rte_ixgbe_pmd = {
1564         .pci_drv = {
1565                 .id_table = pci_id_ixgbe_map,
1566                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1567                         RTE_PCI_DRV_DETACHABLE,
1568                 .probe = rte_eth_dev_pci_probe,
1569                 .remove = rte_eth_dev_pci_remove,
1570         },
1571         .eth_dev_init = eth_ixgbe_dev_init,
1572         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1573         .dev_private_size = sizeof(struct ixgbe_adapter),
1574 };
1575
1576 /*
1577  * virtual function driver struct
1578  */
1579 static struct eth_driver rte_ixgbevf_pmd = {
1580         .pci_drv = {
1581                 .id_table = pci_id_ixgbevf_map,
1582                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1583                 .probe = rte_eth_dev_pci_probe,
1584                 .remove = rte_eth_dev_pci_remove,
1585         },
1586         .eth_dev_init = eth_ixgbevf_dev_init,
1587         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1588         .dev_private_size = sizeof(struct ixgbe_adapter),
1589 };
1590
1591 static int
1592 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1593 {
1594         struct ixgbe_hw *hw =
1595                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596         struct ixgbe_vfta *shadow_vfta =
1597                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1598         uint32_t vfta;
1599         uint32_t vid_idx;
1600         uint32_t vid_bit;
1601
1602         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1603         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1604         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1605         if (on)
1606                 vfta |= vid_bit;
1607         else
1608                 vfta &= ~vid_bit;
1609         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1610
1611         /* update local VFTA copy */
1612         shadow_vfta->vfta[vid_idx] = vfta;
1613
1614         return 0;
1615 }
1616
1617 static void
1618 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1619 {
1620         if (on)
1621                 ixgbe_vlan_hw_strip_enable(dev, queue);
1622         else
1623                 ixgbe_vlan_hw_strip_disable(dev, queue);
1624 }
1625
1626 static int
1627 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1628                     enum rte_vlan_type vlan_type,
1629                     uint16_t tpid)
1630 {
1631         struct ixgbe_hw *hw =
1632                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         int ret = 0;
1634         uint32_t reg;
1635         uint32_t qinq;
1636
1637         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1638         qinq &= IXGBE_DMATXCTL_GDV;
1639
1640         switch (vlan_type) {
1641         case ETH_VLAN_TYPE_INNER:
1642                 if (qinq) {
1643                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1644                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1645                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1646                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1647                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1648                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1649                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1650                 } else {
1651                         ret = -ENOTSUP;
1652                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1653                                     " by single VLAN");
1654                 }
1655                 break;
1656         case ETH_VLAN_TYPE_OUTER:
1657                 if (qinq) {
1658                         /* Only the high 16-bits is valid */
1659                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1660                                         IXGBE_EXVET_VET_EXT_SHIFT);
1661                 } else {
1662                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1663                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1664                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1665                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1666                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1667                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1668                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1669                 }
1670
1671                 break;
1672         default:
1673                 ret = -EINVAL;
1674                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1675                 break;
1676         }
1677
1678         return ret;
1679 }
1680
1681 void
1682 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1683 {
1684         struct ixgbe_hw *hw =
1685                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686         uint32_t vlnctrl;
1687
1688         PMD_INIT_FUNC_TRACE();
1689
1690         /* Filter Table Disable */
1691         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1692         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1693
1694         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1695 }
1696
1697 void
1698 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1699 {
1700         struct ixgbe_hw *hw =
1701                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1702         struct ixgbe_vfta *shadow_vfta =
1703                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1704         uint32_t vlnctrl;
1705         uint16_t i;
1706
1707         PMD_INIT_FUNC_TRACE();
1708
1709         /* Filter Table Enable */
1710         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1711         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1712         vlnctrl |= IXGBE_VLNCTRL_VFE;
1713
1714         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1715
1716         /* write whatever is in local vfta copy */
1717         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1718                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1719 }
1720
1721 static void
1722 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1723 {
1724         struct ixgbe_hwstrip *hwstrip =
1725                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1726         struct ixgbe_rx_queue *rxq;
1727
1728         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1729                 return;
1730
1731         if (on)
1732                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1733         else
1734                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1735
1736         if (queue >= dev->data->nb_rx_queues)
1737                 return;
1738
1739         rxq = dev->data->rx_queues[queue];
1740
1741         if (on)
1742                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1743         else
1744                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1745 }
1746
1747 static void
1748 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1749 {
1750         struct ixgbe_hw *hw =
1751                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752         uint32_t ctrl;
1753
1754         PMD_INIT_FUNC_TRACE();
1755
1756         if (hw->mac.type == ixgbe_mac_82598EB) {
1757                 /* No queue level support */
1758                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1759                 return;
1760         }
1761
1762         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1763         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1764         ctrl &= ~IXGBE_RXDCTL_VME;
1765         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1766
1767         /* record those setting for HW strip per queue */
1768         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1769 }
1770
1771 static void
1772 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1773 {
1774         struct ixgbe_hw *hw =
1775                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776         uint32_t ctrl;
1777
1778         PMD_INIT_FUNC_TRACE();
1779
1780         if (hw->mac.type == ixgbe_mac_82598EB) {
1781                 /* No queue level supported */
1782                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1783                 return;
1784         }
1785
1786         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1787         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1788         ctrl |= IXGBE_RXDCTL_VME;
1789         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1790
1791         /* record those setting for HW strip per queue */
1792         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1793 }
1794
1795 void
1796 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1797 {
1798         struct ixgbe_hw *hw =
1799                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800         uint32_t ctrl;
1801         uint16_t i;
1802
1803         PMD_INIT_FUNC_TRACE();
1804
1805         if (hw->mac.type == ixgbe_mac_82598EB) {
1806                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1807                 ctrl &= ~IXGBE_VLNCTRL_VME;
1808                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1809         } else {
1810                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1811                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1812                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1813                         ctrl &= ~IXGBE_RXDCTL_VME;
1814                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1815
1816                         /* record those setting for HW strip per queue */
1817                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1818                 }
1819         }
1820 }
1821
1822 void
1823 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1824 {
1825         struct ixgbe_hw *hw =
1826                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827         uint32_t ctrl;
1828         uint16_t i;
1829
1830         PMD_INIT_FUNC_TRACE();
1831
1832         if (hw->mac.type == ixgbe_mac_82598EB) {
1833                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1834                 ctrl |= IXGBE_VLNCTRL_VME;
1835                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1836         } else {
1837                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1838                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1839                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1840                         ctrl |= IXGBE_RXDCTL_VME;
1841                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1842
1843                         /* record those setting for HW strip per queue */
1844                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1845                 }
1846         }
1847 }
1848
1849 static void
1850 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1851 {
1852         struct ixgbe_hw *hw =
1853                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1854         uint32_t ctrl;
1855
1856         PMD_INIT_FUNC_TRACE();
1857
1858         /* DMATXCTRL: Geric Double VLAN Disable */
1859         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1860         ctrl &= ~IXGBE_DMATXCTL_GDV;
1861         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1862
1863         /* CTRL_EXT: Global Double VLAN Disable */
1864         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1865         ctrl &= ~IXGBE_EXTENDED_VLAN;
1866         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1867
1868 }
1869
1870 static void
1871 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1872 {
1873         struct ixgbe_hw *hw =
1874                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1875         uint32_t ctrl;
1876
1877         PMD_INIT_FUNC_TRACE();
1878
1879         /* DMATXCTRL: Geric Double VLAN Enable */
1880         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1881         ctrl |= IXGBE_DMATXCTL_GDV;
1882         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1883
1884         /* CTRL_EXT: Global Double VLAN Enable */
1885         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1886         ctrl |= IXGBE_EXTENDED_VLAN;
1887         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1888
1889         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1890         if (hw->mac.type == ixgbe_mac_X550 ||
1891             hw->mac.type == ixgbe_mac_X550EM_x ||
1892             hw->mac.type == ixgbe_mac_X550EM_a) {
1893                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1894                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1895                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1896         }
1897
1898         /*
1899          * VET EXT field in the EXVET register = 0x8100 by default
1900          * So no need to change. Same to VT field of DMATXCTL register
1901          */
1902 }
1903
1904 static void
1905 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1906 {
1907         if (mask & ETH_VLAN_STRIP_MASK) {
1908                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1909                         ixgbe_vlan_hw_strip_enable_all(dev);
1910                 else
1911                         ixgbe_vlan_hw_strip_disable_all(dev);
1912         }
1913
1914         if (mask & ETH_VLAN_FILTER_MASK) {
1915                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1916                         ixgbe_vlan_hw_filter_enable(dev);
1917                 else
1918                         ixgbe_vlan_hw_filter_disable(dev);
1919         }
1920
1921         if (mask & ETH_VLAN_EXTEND_MASK) {
1922                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1923                         ixgbe_vlan_hw_extend_enable(dev);
1924                 else
1925                         ixgbe_vlan_hw_extend_disable(dev);
1926         }
1927 }
1928
1929 static void
1930 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1931 {
1932         struct ixgbe_hw *hw =
1933                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1935         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1936
1937         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1938         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1939 }
1940
1941 static int
1942 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1943 {
1944         switch (nb_rx_q) {
1945         case 1:
1946         case 2:
1947                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1948                 break;
1949         case 4:
1950                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1951                 break;
1952         default:
1953                 return -EINVAL;
1954         }
1955
1956         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1957         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1958
1959         return 0;
1960 }
1961
1962 static int
1963 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1964 {
1965         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1967         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1968         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1969
1970         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1971                 /* check multi-queue mode */
1972                 switch (dev_conf->rxmode.mq_mode) {
1973                 case ETH_MQ_RX_VMDQ_DCB:
1974                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1975                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1976                         PMD_INIT_LOG(ERR, "SRIOV active,"
1977                                         " unsupported mq_mode rx %d.",
1978                                         dev_conf->rxmode.mq_mode);
1979                         return -EINVAL;
1980                 case ETH_MQ_RX_RSS:
1981                 case ETH_MQ_RX_VMDQ_RSS:
1982                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1983                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1984                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1985                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1986                                                 " invalid queue number"
1987                                                 " for VMDQ RSS, allowed"
1988                                                 " value are 1, 2 or 4.");
1989                                         return -EINVAL;
1990                                 }
1991                         break;
1992                 case ETH_MQ_RX_VMDQ_ONLY:
1993                 case ETH_MQ_RX_NONE:
1994                         /* if nothing mq mode configure, use default scheme */
1995                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1996                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1997                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1998                         break;
1999                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2000                         /* SRIOV only works in VMDq enable mode */
2001                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2002                                         " wrong mq_mode rx %d.",
2003                                         dev_conf->rxmode.mq_mode);
2004                         return -EINVAL;
2005                 }
2006
2007                 switch (dev_conf->txmode.mq_mode) {
2008                 case ETH_MQ_TX_VMDQ_DCB:
2009                         /* DCB VMDQ in SRIOV mode, not implement yet */
2010                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2011                                         " unsupported VMDQ mq_mode tx %d.",
2012                                         dev_conf->txmode.mq_mode);
2013                         return -EINVAL;
2014                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2015                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2016                         break;
2017                 }
2018
2019                 /* check valid queue number */
2020                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2021                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2022                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2023                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2024                                         " must be less than or equal to %d.",
2025                                         nb_rx_q, nb_tx_q,
2026                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2027                         return -EINVAL;
2028                 }
2029         } else {
2030                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2031                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2032                                           " not supported.");
2033                         return -EINVAL;
2034                 }
2035                 /* check configuration for vmdb+dcb mode */
2036                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2037                         const struct rte_eth_vmdq_dcb_conf *conf;
2038
2039                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2040                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2041                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2042                                 return -EINVAL;
2043                         }
2044                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2045                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2046                                conf->nb_queue_pools == ETH_32_POOLS)) {
2047                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2048                                                 " nb_queue_pools must be %d or %d.",
2049                                                 ETH_16_POOLS, ETH_32_POOLS);
2050                                 return -EINVAL;
2051                         }
2052                 }
2053                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2054                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2055
2056                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2057                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2058                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2059                                 return -EINVAL;
2060                         }
2061                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2062                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2063                                conf->nb_queue_pools == ETH_32_POOLS)) {
2064                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2065                                                 " nb_queue_pools != %d and"
2066                                                 " nb_queue_pools != %d.",
2067                                                 ETH_16_POOLS, ETH_32_POOLS);
2068                                 return -EINVAL;
2069                         }
2070                 }
2071
2072                 /* For DCB mode check our configuration before we go further */
2073                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2074                         const struct rte_eth_dcb_rx_conf *conf;
2075
2076                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2077                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2078                                                  IXGBE_DCB_NB_QUEUES);
2079                                 return -EINVAL;
2080                         }
2081                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2082                         if (!(conf->nb_tcs == ETH_4_TCS ||
2083                                conf->nb_tcs == ETH_8_TCS)) {
2084                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2085                                                 " and nb_tcs != %d.",
2086                                                 ETH_4_TCS, ETH_8_TCS);
2087                                 return -EINVAL;
2088                         }
2089                 }
2090
2091                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2092                         const struct rte_eth_dcb_tx_conf *conf;
2093
2094                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2095                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2096                                                  IXGBE_DCB_NB_QUEUES);
2097                                 return -EINVAL;
2098                         }
2099                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2100                         if (!(conf->nb_tcs == ETH_4_TCS ||
2101                                conf->nb_tcs == ETH_8_TCS)) {
2102                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2103                                                 " and nb_tcs != %d.",
2104                                                 ETH_4_TCS, ETH_8_TCS);
2105                                 return -EINVAL;
2106                         }
2107                 }
2108
2109                 /*
2110                  * When DCB/VT is off, maximum number of queues changes,
2111                  * except for 82598EB, which remains constant.
2112                  */
2113                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2114                                 hw->mac.type != ixgbe_mac_82598EB) {
2115                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2116                                 PMD_INIT_LOG(ERR,
2117                                              "Neither VT nor DCB are enabled, "
2118                                              "nb_tx_q > %d.",
2119                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2120                                 return -EINVAL;
2121                         }
2122                 }
2123         }
2124         return 0;
2125 }
2126
2127 static int
2128 ixgbe_dev_configure(struct rte_eth_dev *dev)
2129 {
2130         struct ixgbe_interrupt *intr =
2131                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2132         struct ixgbe_adapter *adapter =
2133                 (struct ixgbe_adapter *)dev->data->dev_private;
2134         int ret;
2135
2136         PMD_INIT_FUNC_TRACE();
2137         /* multipe queue mode checking */
2138         ret  = ixgbe_check_mq_mode(dev);
2139         if (ret != 0) {
2140                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2141                             ret);
2142                 return ret;
2143         }
2144
2145         /* set flag to update link status after init */
2146         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2147
2148         /*
2149          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2150          * allocation or vector Rx preconditions we will reset it.
2151          */
2152         adapter->rx_bulk_alloc_allowed = true;
2153         adapter->rx_vec_allowed = true;
2154
2155         return 0;
2156 }
2157
2158 static void
2159 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2160 {
2161         struct ixgbe_hw *hw =
2162                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163         struct ixgbe_interrupt *intr =
2164                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2165         uint32_t gpie;
2166
2167         /* only set up it on X550EM_X */
2168         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2169                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2170                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2171                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2172                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2173                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2174         }
2175 }
2176
2177 /*
2178  * Configure device link speed and setup link.
2179  * It returns 0 on success.
2180  */
2181 static int
2182 ixgbe_dev_start(struct rte_eth_dev *dev)
2183 {
2184         struct ixgbe_hw *hw =
2185                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186         struct ixgbe_vf_info *vfinfo =
2187                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2188         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2189         uint32_t intr_vector = 0;
2190         int err, link_up = 0, negotiate = 0;
2191         uint32_t speed = 0;
2192         int mask = 0;
2193         int status;
2194         uint16_t vf, idx;
2195         uint32_t *link_speeds;
2196
2197         PMD_INIT_FUNC_TRACE();
2198
2199         /* IXGBE devices don't support:
2200         *    - half duplex (checked afterwards for valid speeds)
2201         *    - fixed speed: TODO implement
2202         */
2203         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2204                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2205                              dev->data->port_id);
2206                 return -EINVAL;
2207         }
2208
2209         /* disable uio/vfio intr/eventfd mapping */
2210         rte_intr_disable(intr_handle);
2211
2212         /* stop adapter */
2213         hw->adapter_stopped = 0;
2214         ixgbe_stop_adapter(hw);
2215
2216         /* reinitialize adapter
2217          * this calls reset and start
2218          */
2219         status = ixgbe_pf_reset_hw(hw);
2220         if (status != 0)
2221                 return -1;
2222         hw->mac.ops.start_hw(hw);
2223         hw->mac.get_link_status = true;
2224
2225         /* configure PF module if SRIOV enabled */
2226         ixgbe_pf_host_configure(dev);
2227
2228         ixgbe_dev_phy_intr_setup(dev);
2229
2230         /* check and configure queue intr-vector mapping */
2231         if ((rte_intr_cap_multiple(intr_handle) ||
2232              !RTE_ETH_DEV_SRIOV(dev).active) &&
2233             dev->data->dev_conf.intr_conf.rxq != 0) {
2234                 intr_vector = dev->data->nb_rx_queues;
2235                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2236                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2237                                         IXGBE_MAX_INTR_QUEUE_NUM);
2238                         return -ENOTSUP;
2239                 }
2240                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2241                         return -1;
2242         }
2243
2244         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2245                 intr_handle->intr_vec =
2246                         rte_zmalloc("intr_vec",
2247                                     dev->data->nb_rx_queues * sizeof(int), 0);
2248                 if (intr_handle->intr_vec == NULL) {
2249                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2250                                      " intr_vec\n", dev->data->nb_rx_queues);
2251                         return -ENOMEM;
2252                 }
2253         }
2254
2255         /* confiugre msix for sleep until rx interrupt */
2256         ixgbe_configure_msix(dev);
2257
2258         /* initialize transmission unit */
2259         ixgbe_dev_tx_init(dev);
2260
2261         /* This can fail when allocating mbufs for descriptor rings */
2262         err = ixgbe_dev_rx_init(dev);
2263         if (err) {
2264                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2265                 goto error;
2266         }
2267
2268         err = ixgbe_dev_rxtx_start(dev);
2269         if (err < 0) {
2270                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2271                 goto error;
2272         }
2273
2274         /* Skip link setup if loopback mode is enabled for 82599. */
2275         if (hw->mac.type == ixgbe_mac_82599EB &&
2276                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2277                 goto skip_link_setup;
2278
2279         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2280                 err = hw->mac.ops.setup_sfp(hw);
2281                 if (err)
2282                         goto error;
2283         }
2284
2285         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2286                 /* Turn on the copper */
2287                 ixgbe_set_phy_power(hw, true);
2288         } else {
2289                 /* Turn on the laser */
2290                 ixgbe_enable_tx_laser(hw);
2291         }
2292
2293         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2294         if (err)
2295                 goto error;
2296         dev->data->dev_link.link_status = link_up;
2297
2298         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2299         if (err)
2300                 goto error;
2301
2302         link_speeds = &dev->data->dev_conf.link_speeds;
2303         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2304                         ETH_LINK_SPEED_10G)) {
2305                 PMD_INIT_LOG(ERR, "Invalid link setting");
2306                 goto error;
2307         }
2308
2309         speed = 0x0;
2310         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2311                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2312                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2313                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2314         } else {
2315                 if (*link_speeds & ETH_LINK_SPEED_10G)
2316                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2317                 if (*link_speeds & ETH_LINK_SPEED_1G)
2318                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2319                 if (*link_speeds & ETH_LINK_SPEED_100M)
2320                         speed |= IXGBE_LINK_SPEED_100_FULL;
2321         }
2322
2323         err = ixgbe_setup_link(hw, speed, link_up);
2324         if (err)
2325                 goto error;
2326
2327 skip_link_setup:
2328
2329         if (rte_intr_allow_others(intr_handle)) {
2330                 /* check if lsc interrupt is enabled */
2331                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2332                         ixgbe_dev_lsc_interrupt_setup(dev);
2333         } else {
2334                 rte_intr_callback_unregister(intr_handle,
2335                                              ixgbe_dev_interrupt_handler,
2336                                              (void *)dev);
2337                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2338                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2339                                      " no intr multiplex\n");
2340         }
2341
2342         /* check if rxq interrupt is enabled */
2343         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2344             rte_intr_dp_is_en(intr_handle))
2345                 ixgbe_dev_rxq_interrupt_setup(dev);
2346
2347         /* enable uio/vfio intr/eventfd mapping */
2348         rte_intr_enable(intr_handle);
2349
2350         /* resume enabled intr since hw reset */
2351         ixgbe_enable_intr(dev);
2352
2353         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2354                 ETH_VLAN_EXTEND_MASK;
2355         ixgbe_vlan_offload_set(dev, mask);
2356
2357         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2358                 /* Enable vlan filtering for VMDq */
2359                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2360         }
2361
2362         /* Configure DCB hw */
2363         ixgbe_configure_dcb(dev);
2364
2365         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2366                 err = ixgbe_fdir_configure(dev);
2367                 if (err)
2368                         goto error;
2369         }
2370
2371         /* Restore vf rate limit */
2372         if (vfinfo != NULL) {
2373                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2374                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2375                                 if (vfinfo[vf].tx_rate[idx] != 0)
2376                                         ixgbe_set_vf_rate_limit(dev, vf,
2377                                                 vfinfo[vf].tx_rate[idx],
2378                                                 1 << idx);
2379         }
2380
2381         ixgbe_restore_statistics_mapping(dev);
2382
2383         return 0;
2384
2385 error:
2386         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2387         ixgbe_dev_clear_queues(dev);
2388         return -EIO;
2389 }
2390
2391 /*
2392  * Stop device: disable rx and tx functions to allow for reconfiguring.
2393  */
2394 static void
2395 ixgbe_dev_stop(struct rte_eth_dev *dev)
2396 {
2397         struct rte_eth_link link;
2398         struct ixgbe_hw *hw =
2399                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400         struct ixgbe_vf_info *vfinfo =
2401                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2402         struct ixgbe_filter_info *filter_info =
2403                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2404         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2405         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2406         int vf;
2407
2408         PMD_INIT_FUNC_TRACE();
2409
2410         /* disable interrupts */
2411         ixgbe_disable_intr(hw);
2412
2413         /* reset the NIC */
2414         ixgbe_pf_reset_hw(hw);
2415         hw->adapter_stopped = 0;
2416
2417         /* stop adapter */
2418         ixgbe_stop_adapter(hw);
2419
2420         for (vf = 0; vfinfo != NULL &&
2421                      vf < dev->pci_dev->max_vfs; vf++)
2422                 vfinfo[vf].clear_to_send = false;
2423
2424         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2425                 /* Turn off the copper */
2426                 ixgbe_set_phy_power(hw, false);
2427         } else {
2428                 /* Turn off the laser */
2429                 ixgbe_disable_tx_laser(hw);
2430         }
2431
2432         ixgbe_dev_clear_queues(dev);
2433
2434         /* Clear stored conf */
2435         dev->data->scattered_rx = 0;
2436         dev->data->lro = 0;
2437
2438         /* Clear recorded link status */
2439         memset(&link, 0, sizeof(link));
2440         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2441
2442         /* Remove all ntuple filters of the device */
2443         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2444              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2445                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2446                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2447                              p_5tuple, entries);
2448                 rte_free(p_5tuple);
2449         }
2450         memset(filter_info->fivetuple_mask, 0,
2451                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2452
2453         if (!rte_intr_allow_others(intr_handle))
2454                 /* resume to the default handler */
2455                 rte_intr_callback_register(intr_handle,
2456                                            ixgbe_dev_interrupt_handler,
2457                                            (void *)dev);
2458
2459         /* Clean datapath event and queue/vec mapping */
2460         rte_intr_efd_disable(intr_handle);
2461         if (intr_handle->intr_vec != NULL) {
2462                 rte_free(intr_handle->intr_vec);
2463                 intr_handle->intr_vec = NULL;
2464         }
2465 }
2466
2467 /*
2468  * Set device link up: enable tx.
2469  */
2470 static int
2471 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2472 {
2473         struct ixgbe_hw *hw =
2474                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475         if (hw->mac.type == ixgbe_mac_82599EB) {
2476 #ifdef RTE_NIC_BYPASS
2477                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2478                         /* Not suported in bypass mode */
2479                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2480                                      "by device id 0x%x", hw->device_id);
2481                         return -ENOTSUP;
2482                 }
2483 #endif
2484         }
2485
2486         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2487                 /* Turn on the copper */
2488                 ixgbe_set_phy_power(hw, true);
2489         } else {
2490                 /* Turn on the laser */
2491                 ixgbe_enable_tx_laser(hw);
2492         }
2493
2494         return 0;
2495 }
2496
2497 /*
2498  * Set device link down: disable tx.
2499  */
2500 static int
2501 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2502 {
2503         struct ixgbe_hw *hw =
2504                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2505         if (hw->mac.type == ixgbe_mac_82599EB) {
2506 #ifdef RTE_NIC_BYPASS
2507                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2508                         /* Not suported in bypass mode */
2509                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2510                                      "by device id 0x%x", hw->device_id);
2511                         return -ENOTSUP;
2512                 }
2513 #endif
2514         }
2515
2516         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2517                 /* Turn off the copper */
2518                 ixgbe_set_phy_power(hw, false);
2519         } else {
2520                 /* Turn off the laser */
2521                 ixgbe_disable_tx_laser(hw);
2522         }
2523
2524         return 0;
2525 }
2526
2527 /*
2528  * Reest and stop device.
2529  */
2530 static void
2531 ixgbe_dev_close(struct rte_eth_dev *dev)
2532 {
2533         struct ixgbe_hw *hw =
2534                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535
2536         PMD_INIT_FUNC_TRACE();
2537
2538         ixgbe_pf_reset_hw(hw);
2539
2540         ixgbe_dev_stop(dev);
2541         hw->adapter_stopped = 1;
2542
2543         ixgbe_dev_free_queues(dev);
2544
2545         ixgbe_disable_pcie_master(hw);
2546
2547         /* reprogram the RAR[0] in case user changed it. */
2548         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2549 }
2550
2551 static void
2552 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2553                            struct ixgbe_hw_stats *hw_stats,
2554                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2555                            uint64_t *total_qprc, uint64_t *total_qprdc)
2556 {
2557         uint32_t bprc, lxon, lxoff, total;
2558         uint32_t delta_gprc = 0;
2559         unsigned i;
2560         /* Workaround for RX byte count not including CRC bytes when CRC
2561 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2562          * is disabled.
2563 +        */
2564         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2565                         IXGBE_HLREG0_RXCRCSTRP);
2566
2567         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2568         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2569         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2570         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2571
2572         for (i = 0; i < 8; i++) {
2573                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2574
2575                 /* global total per queue */
2576                 hw_stats->mpc[i] += mp;
2577                 /* Running comprehensive total for stats display */
2578                 *total_missed_rx += hw_stats->mpc[i];
2579                 if (hw->mac.type == ixgbe_mac_82598EB) {
2580                         hw_stats->rnbc[i] +=
2581                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2582                         hw_stats->pxonrxc[i] +=
2583                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2584                         hw_stats->pxoffrxc[i] +=
2585                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2586                 } else {
2587                         hw_stats->pxonrxc[i] +=
2588                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2589                         hw_stats->pxoffrxc[i] +=
2590                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2591                         hw_stats->pxon2offc[i] +=
2592                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2593                 }
2594                 hw_stats->pxontxc[i] +=
2595                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2596                 hw_stats->pxofftxc[i] +=
2597                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2598         }
2599         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2600                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2601                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2602                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2603
2604                 delta_gprc += delta_qprc;
2605
2606                 hw_stats->qprc[i] += delta_qprc;
2607                 hw_stats->qptc[i] += delta_qptc;
2608
2609                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2610                 hw_stats->qbrc[i] +=
2611                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2612                 if (crc_strip == 0)
2613                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2614
2615                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2616                 hw_stats->qbtc[i] +=
2617                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2618
2619                 hw_stats->qprdc[i] += delta_qprdc;
2620                 *total_qprdc += hw_stats->qprdc[i];
2621
2622                 *total_qprc += hw_stats->qprc[i];
2623                 *total_qbrc += hw_stats->qbrc[i];
2624         }
2625         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2626         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2627         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2628
2629         /*
2630          * An errata states that gprc actually counts good + missed packets:
2631          * Workaround to set gprc to summated queue packet receives
2632          */
2633         hw_stats->gprc = *total_qprc;
2634
2635         if (hw->mac.type != ixgbe_mac_82598EB) {
2636                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2637                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2638                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2639                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2640                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2641                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2642                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2643                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2644         } else {
2645                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2646                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2647                 /* 82598 only has a counter in the high register */
2648                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2649                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2650                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2651         }
2652         uint64_t old_tpr = hw_stats->tpr;
2653
2654         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2655         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2656
2657         if (crc_strip == 0)
2658                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2659
2660         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2661         hw_stats->gptc += delta_gptc;
2662         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2663         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2664
2665         /*
2666          * Workaround: mprc hardware is incorrectly counting
2667          * broadcasts, so for now we subtract those.
2668          */
2669         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2670         hw_stats->bprc += bprc;
2671         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2672         if (hw->mac.type == ixgbe_mac_82598EB)
2673                 hw_stats->mprc -= bprc;
2674
2675         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2676         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2677         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2678         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2679         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2680         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2681
2682         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2683         hw_stats->lxontxc += lxon;
2684         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2685         hw_stats->lxofftxc += lxoff;
2686         total = lxon + lxoff;
2687
2688         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2689         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2690         hw_stats->gptc -= total;
2691         hw_stats->mptc -= total;
2692         hw_stats->ptc64 -= total;
2693         hw_stats->gotc -= total * ETHER_MIN_LEN;
2694
2695         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2696         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2697         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2698         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2699         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2700         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2701         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2702         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2703         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2704         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2705         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2706         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2707         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2708         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2709         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2710         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2711         /* Only read FCOE on 82599 */
2712         if (hw->mac.type != ixgbe_mac_82598EB) {
2713                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2714                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2715                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2716                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2717                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2718         }
2719
2720         /* Flow Director Stats registers */
2721         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2722         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2723 }
2724
2725 /*
2726  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2727  */
2728 static void
2729 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2730 {
2731         struct ixgbe_hw *hw =
2732                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2733         struct ixgbe_hw_stats *hw_stats =
2734                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2735         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2736         unsigned i;
2737
2738         total_missed_rx = 0;
2739         total_qbrc = 0;
2740         total_qprc = 0;
2741         total_qprdc = 0;
2742
2743         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2744                         &total_qprc, &total_qprdc);
2745
2746         if (stats == NULL)
2747                 return;
2748
2749         /* Fill out the rte_eth_stats statistics structure */
2750         stats->ipackets = total_qprc;
2751         stats->ibytes = total_qbrc;
2752         stats->opackets = hw_stats->gptc;
2753         stats->obytes = hw_stats->gotc;
2754
2755         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2756                 stats->q_ipackets[i] = hw_stats->qprc[i];
2757                 stats->q_opackets[i] = hw_stats->qptc[i];
2758                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2759                 stats->q_obytes[i] = hw_stats->qbtc[i];
2760                 stats->q_errors[i] = hw_stats->qprdc[i];
2761         }
2762
2763         /* Rx Errors */
2764         stats->imissed  = total_missed_rx;
2765         stats->ierrors  = hw_stats->crcerrs +
2766                           hw_stats->mspdc +
2767                           hw_stats->rlec +
2768                           hw_stats->ruc +
2769                           hw_stats->roc +
2770                           hw_stats->illerrc +
2771                           hw_stats->errbc +
2772                           hw_stats->rfc +
2773                           hw_stats->fccrc +
2774                           hw_stats->fclast;
2775
2776         /* Tx Errors */
2777         stats->oerrors  = 0;
2778 }
2779
2780 static void
2781 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2782 {
2783         struct ixgbe_hw_stats *stats =
2784                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2785
2786         /* HW registers are cleared on read */
2787         ixgbe_dev_stats_get(dev, NULL);
2788
2789         /* Reset software totals */
2790         memset(stats, 0, sizeof(*stats));
2791 }
2792
2793 /* This function calculates the number of xstats based on the current config */
2794 static unsigned
2795 ixgbe_xstats_calc_num(void) {
2796         return IXGBE_NB_HW_STATS +
2797                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2798                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2799 }
2800
2801 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2802         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2803 {
2804         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2805         unsigned stat, i, count;
2806
2807         if (xstats_names != NULL) {
2808                 count = 0;
2809
2810                 /* Note: limit >= cnt_stats checked upstream
2811                  * in rte_eth_xstats_names()
2812                  */
2813
2814                 /* Extended stats from ixgbe_hw_stats */
2815                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2816                         snprintf(xstats_names[count].name,
2817                                 sizeof(xstats_names[count].name),
2818                                 "%s",
2819                                 rte_ixgbe_stats_strings[i].name);
2820                         count++;
2821                 }
2822
2823                 /* RX Priority Stats */
2824                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2825                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2826                                 snprintf(xstats_names[count].name,
2827                                         sizeof(xstats_names[count].name),
2828                                         "rx_priority%u_%s", i,
2829                                         rte_ixgbe_rxq_strings[stat].name);
2830                                 count++;
2831                         }
2832                 }
2833
2834                 /* TX Priority Stats */
2835                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2836                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2837                                 snprintf(xstats_names[count].name,
2838                                         sizeof(xstats_names[count].name),
2839                                         "tx_priority%u_%s", i,
2840                                         rte_ixgbe_txq_strings[stat].name);
2841                                 count++;
2842                         }
2843                 }
2844         }
2845         return cnt_stats;
2846 }
2847
2848 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2849         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2850 {
2851         unsigned i;
2852
2853         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2854                 return -ENOMEM;
2855
2856         if (xstats_names != NULL)
2857                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2858                         snprintf(xstats_names[i].name,
2859                                 sizeof(xstats_names[i].name),
2860                                 "%s", rte_ixgbevf_stats_strings[i].name);
2861         return IXGBEVF_NB_XSTATS;
2862 }
2863
2864 static int
2865 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2866                                          unsigned n)
2867 {
2868         struct ixgbe_hw *hw =
2869                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870         struct ixgbe_hw_stats *hw_stats =
2871                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2872         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2873         unsigned i, stat, count = 0;
2874
2875         count = ixgbe_xstats_calc_num();
2876
2877         if (n < count)
2878                 return count;
2879
2880         total_missed_rx = 0;
2881         total_qbrc = 0;
2882         total_qprc = 0;
2883         total_qprdc = 0;
2884
2885         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2886                                    &total_qprc, &total_qprdc);
2887
2888         /* If this is a reset xstats is NULL, and we have cleared the
2889          * registers by reading them.
2890          */
2891         if (!xstats)
2892                 return 0;
2893
2894         /* Extended stats from ixgbe_hw_stats */
2895         count = 0;
2896         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2897                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2898                                 rte_ixgbe_stats_strings[i].offset);
2899                 count++;
2900         }
2901
2902         /* RX Priority Stats */
2903         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2904                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2905                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2906                                         rte_ixgbe_rxq_strings[stat].offset +
2907                                         (sizeof(uint64_t) * i));
2908                         count++;
2909                 }
2910         }
2911
2912         /* TX Priority Stats */
2913         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2914                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2915                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2916                                         rte_ixgbe_txq_strings[stat].offset +
2917                                         (sizeof(uint64_t) * i));
2918                         count++;
2919                 }
2920         }
2921         return count;
2922 }
2923
2924 static void
2925 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2926 {
2927         struct ixgbe_hw_stats *stats =
2928                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2929
2930         unsigned count = ixgbe_xstats_calc_num();
2931
2932         /* HW registers are cleared on read */
2933         ixgbe_dev_xstats_get(dev, NULL, count);
2934
2935         /* Reset software totals */
2936         memset(stats, 0, sizeof(*stats));
2937 }
2938
2939 static void
2940 ixgbevf_update_stats(struct rte_eth_dev *dev)
2941 {
2942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2943         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2944                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2945
2946         /* Good Rx packet, include VF loopback */
2947         UPDATE_VF_STAT(IXGBE_VFGPRC,
2948             hw_stats->last_vfgprc, hw_stats->vfgprc);
2949
2950         /* Good Rx octets, include VF loopback */
2951         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2952             hw_stats->last_vfgorc, hw_stats->vfgorc);
2953
2954         /* Good Tx packet, include VF loopback */
2955         UPDATE_VF_STAT(IXGBE_VFGPTC,
2956             hw_stats->last_vfgptc, hw_stats->vfgptc);
2957
2958         /* Good Tx octets, include VF loopback */
2959         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2960             hw_stats->last_vfgotc, hw_stats->vfgotc);
2961
2962         /* Rx Multicst Packet */
2963         UPDATE_VF_STAT(IXGBE_VFMPRC,
2964             hw_stats->last_vfmprc, hw_stats->vfmprc);
2965 }
2966
2967 static int
2968 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2969                        unsigned n)
2970 {
2971         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2972                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2973         unsigned i;
2974
2975         if (n < IXGBEVF_NB_XSTATS)
2976                 return IXGBEVF_NB_XSTATS;
2977
2978         ixgbevf_update_stats(dev);
2979
2980         if (!xstats)
2981                 return 0;
2982
2983         /* Extended stats */
2984         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2985                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2986                         rte_ixgbevf_stats_strings[i].offset);
2987         }
2988
2989         return IXGBEVF_NB_XSTATS;
2990 }
2991
2992 static void
2993 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2994 {
2995         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2996                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2997
2998         ixgbevf_update_stats(dev);
2999
3000         if (stats == NULL)
3001                 return;
3002
3003         stats->ipackets = hw_stats->vfgprc;
3004         stats->ibytes = hw_stats->vfgorc;
3005         stats->opackets = hw_stats->vfgptc;
3006         stats->obytes = hw_stats->vfgotc;
3007 }
3008
3009 static void
3010 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3011 {
3012         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3013                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3014
3015         /* Sync HW register to the last stats */
3016         ixgbevf_dev_stats_get(dev, NULL);
3017
3018         /* reset HW current stats*/
3019         hw_stats->vfgprc = 0;
3020         hw_stats->vfgorc = 0;
3021         hw_stats->vfgptc = 0;
3022         hw_stats->vfgotc = 0;
3023 }
3024
3025 static void
3026 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3027 {
3028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3029         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3030
3031         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3032         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3033         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3034                 /*
3035                  * When DCB/VT is off, maximum number of queues changes,
3036                  * except for 82598EB, which remains constant.
3037                  */
3038                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3039                                 hw->mac.type != ixgbe_mac_82598EB)
3040                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3041         }
3042         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3043         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3044         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3045         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3046         dev_info->max_vfs = dev->pci_dev->max_vfs;
3047         if (hw->mac.type == ixgbe_mac_82598EB)
3048                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3049         else
3050                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3051         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3052         dev_info->rx_offload_capa =
3053                 DEV_RX_OFFLOAD_VLAN_STRIP |
3054                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3055                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3056                 DEV_RX_OFFLOAD_TCP_CKSUM;
3057
3058         /*
3059          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3060          * mode.
3061          */
3062         if ((hw->mac.type == ixgbe_mac_82599EB ||
3063              hw->mac.type == ixgbe_mac_X540) &&
3064             !RTE_ETH_DEV_SRIOV(dev).active)
3065                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3066
3067         if (hw->mac.type == ixgbe_mac_X550 ||
3068             hw->mac.type == ixgbe_mac_X550EM_x ||
3069             hw->mac.type == ixgbe_mac_X550EM_a)
3070                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3071
3072         dev_info->tx_offload_capa =
3073                 DEV_TX_OFFLOAD_VLAN_INSERT |
3074                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3075                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3076                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3077                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3078                 DEV_TX_OFFLOAD_TCP_TSO;
3079
3080         if (hw->mac.type == ixgbe_mac_X550 ||
3081             hw->mac.type == ixgbe_mac_X550EM_x ||
3082             hw->mac.type == ixgbe_mac_X550EM_a)
3083                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3084
3085         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3086                 .rx_thresh = {
3087                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3088                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3089                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3090                 },
3091                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3092                 .rx_drop_en = 0,
3093         };
3094
3095         dev_info->default_txconf = (struct rte_eth_txconf) {
3096                 .tx_thresh = {
3097                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3098                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3099                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3100                 },
3101                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3102                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3103                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3104                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3105         };
3106
3107         dev_info->rx_desc_lim = rx_desc_lim;
3108         dev_info->tx_desc_lim = tx_desc_lim;
3109
3110         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3111         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3112         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3113
3114         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3115         if (hw->mac.type == ixgbe_mac_X540 ||
3116             hw->mac.type == ixgbe_mac_X540_vf ||
3117             hw->mac.type == ixgbe_mac_X550 ||
3118             hw->mac.type == ixgbe_mac_X550_vf) {
3119                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3120         }
3121 }
3122
3123 static const uint32_t *
3124 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3125 {
3126         static const uint32_t ptypes[] = {
3127                 /* For non-vec functions,
3128                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3129                  * for vec functions,
3130                  * refers to _recv_raw_pkts_vec().
3131                  */
3132                 RTE_PTYPE_L2_ETHER,
3133                 RTE_PTYPE_L3_IPV4,
3134                 RTE_PTYPE_L3_IPV4_EXT,
3135                 RTE_PTYPE_L3_IPV6,
3136                 RTE_PTYPE_L3_IPV6_EXT,
3137                 RTE_PTYPE_L4_SCTP,
3138                 RTE_PTYPE_L4_TCP,
3139                 RTE_PTYPE_L4_UDP,
3140                 RTE_PTYPE_TUNNEL_IP,
3141                 RTE_PTYPE_INNER_L3_IPV6,
3142                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3143                 RTE_PTYPE_INNER_L4_TCP,
3144                 RTE_PTYPE_INNER_L4_UDP,
3145                 RTE_PTYPE_UNKNOWN
3146         };
3147
3148         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3149             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3150             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3151             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3152                 return ptypes;
3153         return NULL;
3154 }
3155
3156 static void
3157 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3158                      struct rte_eth_dev_info *dev_info)
3159 {
3160         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161
3162         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3163         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3164         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3165         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3166         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3167         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3168         dev_info->max_vfs = dev->pci_dev->max_vfs;
3169         if (hw->mac.type == ixgbe_mac_82598EB)
3170                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3171         else
3172                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3173         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3174                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3175                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3176                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3177         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3178                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3179                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3180                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3181                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3182                                 DEV_TX_OFFLOAD_TCP_TSO;
3183
3184         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3185                 .rx_thresh = {
3186                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3187                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3188                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3189                 },
3190                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3191                 .rx_drop_en = 0,
3192         };
3193
3194         dev_info->default_txconf = (struct rte_eth_txconf) {
3195                 .tx_thresh = {
3196                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3197                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3198                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3199                 },
3200                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3201                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3202                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3203                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3204         };
3205
3206         dev_info->rx_desc_lim = rx_desc_lim;
3207         dev_info->tx_desc_lim = tx_desc_lim;
3208 }
3209
3210 /* return 0 means link status changed, -1 means not changed */
3211 static int
3212 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3213 {
3214         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3215         struct rte_eth_link link, old;
3216         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3217         int link_up;
3218         int diag;
3219
3220         link.link_status = ETH_LINK_DOWN;
3221         link.link_speed = 0;
3222         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3223         memset(&old, 0, sizeof(old));
3224         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3225
3226         hw->mac.get_link_status = true;
3227
3228         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3229         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3230                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3231         else
3232                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3233
3234         if (diag != 0) {
3235                 link.link_speed = ETH_SPEED_NUM_100M;
3236                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3237                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3238                 if (link.link_status == old.link_status)
3239                         return -1;
3240                 return 0;
3241         }
3242
3243         if (link_up == 0) {
3244                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3245                 if (link.link_status == old.link_status)
3246                         return -1;
3247                 return 0;
3248         }
3249         link.link_status = ETH_LINK_UP;
3250         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3251
3252         switch (link_speed) {
3253         default:
3254         case IXGBE_LINK_SPEED_UNKNOWN:
3255                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3256                 link.link_speed = ETH_SPEED_NUM_100M;
3257                 break;
3258
3259         case IXGBE_LINK_SPEED_100_FULL:
3260                 link.link_speed = ETH_SPEED_NUM_100M;
3261                 break;
3262
3263         case IXGBE_LINK_SPEED_1GB_FULL:
3264                 link.link_speed = ETH_SPEED_NUM_1G;
3265                 break;
3266
3267         case IXGBE_LINK_SPEED_10GB_FULL:
3268                 link.link_speed = ETH_SPEED_NUM_10G;
3269                 break;
3270         }
3271         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3272
3273         if (link.link_status == old.link_status)
3274                 return -1;
3275
3276         return 0;
3277 }
3278
3279 static void
3280 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3281 {
3282         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3283         uint32_t fctrl;
3284
3285         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3286         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3287         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3288 }
3289
3290 static void
3291 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3292 {
3293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3294         uint32_t fctrl;
3295
3296         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3297         fctrl &= (~IXGBE_FCTRL_UPE);
3298         if (dev->data->all_multicast == 1)
3299                 fctrl |= IXGBE_FCTRL_MPE;
3300         else
3301                 fctrl &= (~IXGBE_FCTRL_MPE);
3302         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3303 }
3304
3305 static void
3306 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3307 {
3308         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3309         uint32_t fctrl;
3310
3311         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3312         fctrl |= IXGBE_FCTRL_MPE;
3313         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3314 }
3315
3316 static void
3317 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3318 {
3319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3320         uint32_t fctrl;
3321
3322         if (dev->data->promiscuous == 1)
3323                 return; /* must remain in all_multicast mode */
3324
3325         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3326         fctrl &= (~IXGBE_FCTRL_MPE);
3327         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3328 }
3329
3330 /**
3331  * It clears the interrupt causes and enables the interrupt.
3332  * It will be called once only during nic initialized.
3333  *
3334  * @param dev
3335  *  Pointer to struct rte_eth_dev.
3336  *
3337  * @return
3338  *  - On success, zero.
3339  *  - On failure, a negative value.
3340  */
3341 static int
3342 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3343 {
3344         struct ixgbe_interrupt *intr =
3345                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3346
3347         ixgbe_dev_link_status_print(dev);
3348         intr->mask |= IXGBE_EICR_LSC;
3349
3350         return 0;
3351 }
3352
3353 /**
3354  * It clears the interrupt causes and enables the interrupt.
3355  * It will be called once only during nic initialized.
3356  *
3357  * @param dev
3358  *  Pointer to struct rte_eth_dev.
3359  *
3360  * @return
3361  *  - On success, zero.
3362  *  - On failure, a negative value.
3363  */
3364 static int
3365 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3366 {
3367         struct ixgbe_interrupt *intr =
3368                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3369
3370         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3371
3372         return 0;
3373 }
3374
3375 /*
3376  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3377  *
3378  * @param dev
3379  *  Pointer to struct rte_eth_dev.
3380  *
3381  * @return
3382  *  - On success, zero.
3383  *  - On failure, a negative value.
3384  */
3385 static int
3386 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3387 {
3388         uint32_t eicr;
3389         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3390         struct ixgbe_interrupt *intr =
3391                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3392
3393         /* clear all cause mask */
3394         ixgbe_disable_intr(hw);
3395
3396         /* read-on-clear nic registers here */
3397         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3398         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3399
3400         intr->flags = 0;
3401
3402         /* set flag for async link update */
3403         if (eicr & IXGBE_EICR_LSC)
3404                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3405
3406         if (eicr & IXGBE_EICR_MAILBOX)
3407                 intr->flags |= IXGBE_FLAG_MAILBOX;
3408
3409         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3410             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3411             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3412                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3413
3414         return 0;
3415 }
3416
3417 /**
3418  * It gets and then prints the link status.
3419  *
3420  * @param dev
3421  *  Pointer to struct rte_eth_dev.
3422  *
3423  * @return
3424  *  - On success, zero.
3425  *  - On failure, a negative value.
3426  */
3427 static void
3428 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3429 {
3430         struct rte_eth_link link;
3431
3432         memset(&link, 0, sizeof(link));
3433         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3434         if (link.link_status) {
3435                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3436                                         (int)(dev->data->port_id),
3437                                         (unsigned)link.link_speed,
3438                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3439                                         "full-duplex" : "half-duplex");
3440         } else {
3441                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3442                                 (int)(dev->data->port_id));
3443         }
3444         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3445                                 dev->pci_dev->addr.domain,
3446                                 dev->pci_dev->addr.bus,
3447                                 dev->pci_dev->addr.devid,
3448                                 dev->pci_dev->addr.function);
3449 }
3450
3451 /*
3452  * It executes link_update after knowing an interrupt occurred.
3453  *
3454  * @param dev
3455  *  Pointer to struct rte_eth_dev.
3456  *
3457  * @return
3458  *  - On success, zero.
3459  *  - On failure, a negative value.
3460  */
3461 static int
3462 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3463 {
3464         struct ixgbe_interrupt *intr =
3465                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3466         int64_t timeout;
3467         struct rte_eth_link link;
3468         int intr_enable_delay = false;
3469         struct ixgbe_hw *hw =
3470                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3471
3472         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3473
3474         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3475                 ixgbe_pf_mbx_process(dev);
3476                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3477         }
3478
3479         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3480                 ixgbe_handle_lasi(hw);
3481                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3482         }
3483
3484         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3485                 /* get the link status before link update, for predicting later */
3486                 memset(&link, 0, sizeof(link));
3487                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3488
3489                 ixgbe_dev_link_update(dev, 0);
3490
3491                 /* likely to up */
3492                 if (!link.link_status)
3493                         /* handle it 1 sec later, wait it being stable */
3494                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3495                 /* likely to down */
3496                 else
3497                         /* handle it 4 sec later, wait it being stable */
3498                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3499
3500                 ixgbe_dev_link_status_print(dev);
3501
3502                 intr_enable_delay = true;
3503         }
3504
3505         if (intr_enable_delay) {
3506                 if (rte_eal_alarm_set(timeout * 1000,
3507                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3508                         PMD_DRV_LOG(ERR, "Error setting alarm");
3509         } else {
3510                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3511                 ixgbe_enable_intr(dev);
3512                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3513         }
3514
3515
3516         return 0;
3517 }
3518
3519 /**
3520  * Interrupt handler which shall be registered for alarm callback for delayed
3521  * handling specific interrupt to wait for the stable nic state. As the
3522  * NIC interrupt state is not stable for ixgbe after link is just down,
3523  * it needs to wait 4 seconds to get the stable status.
3524  *
3525  * @param handle
3526  *  Pointer to interrupt handle.
3527  * @param param
3528  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3529  *
3530  * @return
3531  *  void
3532  */
3533 static void
3534 ixgbe_dev_interrupt_delayed_handler(void *param)
3535 {
3536         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3537         struct ixgbe_interrupt *intr =
3538                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3539         struct ixgbe_hw *hw =
3540                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3541         uint32_t eicr;
3542
3543         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3544         if (eicr & IXGBE_EICR_MAILBOX)
3545                 ixgbe_pf_mbx_process(dev);
3546
3547         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3548                 ixgbe_handle_lasi(hw);
3549                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3550         }
3551
3552         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3553                 ixgbe_dev_link_update(dev, 0);
3554                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3555                 ixgbe_dev_link_status_print(dev);
3556                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3557         }
3558
3559         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3560         ixgbe_enable_intr(dev);
3561         rte_intr_enable(&(dev->pci_dev->intr_handle));
3562 }
3563
3564 /**
3565  * Interrupt handler triggered by NIC  for handling
3566  * specific interrupt.
3567  *
3568  * @param handle
3569  *  Pointer to interrupt handle.
3570  * @param param
3571  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3572  *
3573  * @return
3574  *  void
3575  */
3576 static void
3577 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3578                             void *param)
3579 {
3580         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3581
3582         ixgbe_dev_interrupt_get_status(dev);
3583         ixgbe_dev_interrupt_action(dev);
3584 }
3585
3586 static int
3587 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3588 {
3589         struct ixgbe_hw *hw;
3590
3591         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3592         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3593 }
3594
3595 static int
3596 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3597 {
3598         struct ixgbe_hw *hw;
3599
3600         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3602 }
3603
3604 static int
3605 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3606 {
3607         struct ixgbe_hw *hw;
3608         uint32_t mflcn_reg;
3609         uint32_t fccfg_reg;
3610         int rx_pause;
3611         int tx_pause;
3612
3613         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3614
3615         fc_conf->pause_time = hw->fc.pause_time;
3616         fc_conf->high_water = hw->fc.high_water[0];
3617         fc_conf->low_water = hw->fc.low_water[0];
3618         fc_conf->send_xon = hw->fc.send_xon;
3619         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3620
3621         /*
3622          * Return rx_pause status according to actual setting of
3623          * MFLCN register.
3624          */
3625         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3626         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3627                 rx_pause = 1;
3628         else
3629                 rx_pause = 0;
3630
3631         /*
3632          * Return tx_pause status according to actual setting of
3633          * FCCFG register.
3634          */
3635         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3636         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3637                 tx_pause = 1;
3638         else
3639                 tx_pause = 0;
3640
3641         if (rx_pause && tx_pause)
3642                 fc_conf->mode = RTE_FC_FULL;
3643         else if (rx_pause)
3644                 fc_conf->mode = RTE_FC_RX_PAUSE;
3645         else if (tx_pause)
3646                 fc_conf->mode = RTE_FC_TX_PAUSE;
3647         else
3648                 fc_conf->mode = RTE_FC_NONE;
3649
3650         return 0;
3651 }
3652
3653 static int
3654 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3655 {
3656         struct ixgbe_hw *hw;
3657         int err;
3658         uint32_t rx_buf_size;
3659         uint32_t max_high_water;
3660         uint32_t mflcn;
3661         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3662                 ixgbe_fc_none,
3663                 ixgbe_fc_rx_pause,
3664                 ixgbe_fc_tx_pause,
3665                 ixgbe_fc_full
3666         };
3667
3668         PMD_INIT_FUNC_TRACE();
3669
3670         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3671         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3672         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3673
3674         /*
3675          * At least reserve one Ethernet frame for watermark
3676          * high_water/low_water in kilo bytes for ixgbe
3677          */
3678         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3679         if ((fc_conf->high_water > max_high_water) ||
3680                 (fc_conf->high_water < fc_conf->low_water)) {
3681                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3682                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3683                 return -EINVAL;
3684         }
3685
3686         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3687         hw->fc.pause_time     = fc_conf->pause_time;
3688         hw->fc.high_water[0]  = fc_conf->high_water;
3689         hw->fc.low_water[0]   = fc_conf->low_water;
3690         hw->fc.send_xon       = fc_conf->send_xon;
3691         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3692
3693         err = ixgbe_fc_enable(hw);
3694
3695         /* Not negotiated is not an error case */
3696         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3697
3698                 /* check if we want to forward MAC frames - driver doesn't have native
3699                  * capability to do that, so we'll write the registers ourselves */
3700
3701                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3702
3703                 /* set or clear MFLCN.PMCF bit depending on configuration */
3704                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3705                         mflcn |= IXGBE_MFLCN_PMCF;
3706                 else
3707                         mflcn &= ~IXGBE_MFLCN_PMCF;
3708
3709                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3710                 IXGBE_WRITE_FLUSH(hw);
3711
3712                 return 0;
3713         }
3714
3715         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3716         return -EIO;
3717 }
3718
3719 /**
3720  *  ixgbe_pfc_enable_generic - Enable flow control
3721  *  @hw: pointer to hardware structure
3722  *  @tc_num: traffic class number
3723  *  Enable flow control according to the current settings.
3724  */
3725 static int
3726 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3727 {
3728         int ret_val = 0;
3729         uint32_t mflcn_reg, fccfg_reg;
3730         uint32_t reg;
3731         uint32_t fcrtl, fcrth;
3732         uint8_t i;
3733         uint8_t nb_rx_en;
3734
3735         /* Validate the water mark configuration */
3736         if (!hw->fc.pause_time) {
3737                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3738                 goto out;
3739         }
3740
3741         /* Low water mark of zero causes XOFF floods */
3742         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3743                  /* High/Low water can not be 0 */
3744                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3745                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3746                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3747                         goto out;
3748                 }
3749
3750                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3751                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3752                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3753                         goto out;
3754                 }
3755         }
3756         /* Negotiate the fc mode to use */
3757         ixgbe_fc_autoneg(hw);
3758
3759         /* Disable any previous flow control settings */
3760         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3761         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3762
3763         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3764         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3765
3766         switch (hw->fc.current_mode) {
3767         case ixgbe_fc_none:
3768                 /*
3769                  * If the count of enabled RX Priority Flow control >1,
3770                  * and the TX pause can not be disabled
3771                  */
3772                 nb_rx_en = 0;
3773                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3774                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3775                         if (reg & IXGBE_FCRTH_FCEN)
3776                                 nb_rx_en++;
3777                 }
3778                 if (nb_rx_en > 1)
3779                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3780                 break;
3781         case ixgbe_fc_rx_pause:
3782                 /*
3783                  * Rx Flow control is enabled and Tx Flow control is
3784                  * disabled by software override. Since there really
3785                  * isn't a way to advertise that we are capable of RX
3786                  * Pause ONLY, we will advertise that we support both
3787                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3788                  * disable the adapter's ability to send PAUSE frames.
3789                  */
3790                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3791                 /*
3792                  * If the count of enabled RX Priority Flow control >1,
3793                  * and the TX pause can not be disabled
3794                  */
3795                 nb_rx_en = 0;
3796                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3797                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3798                         if (reg & IXGBE_FCRTH_FCEN)
3799                                 nb_rx_en++;
3800                 }
3801                 if (nb_rx_en > 1)
3802                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3803                 break;
3804         case ixgbe_fc_tx_pause:
3805                 /*
3806                  * Tx Flow control is enabled, and Rx Flow control is
3807                  * disabled by software override.
3808                  */
3809                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3810                 break;
3811         case ixgbe_fc_full:
3812                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3813                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3814                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3815                 break;
3816         default:
3817                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3818                 ret_val = IXGBE_ERR_CONFIG;
3819                 goto out;
3820         }
3821
3822         /* Set 802.3x based flow control settings. */
3823         mflcn_reg |= IXGBE_MFLCN_DPF;
3824         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3825         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3826
3827         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3828         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3829                 hw->fc.high_water[tc_num]) {
3830                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3831                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3832                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3833         } else {
3834                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3835                 /*
3836                  * In order to prevent Tx hangs when the internal Tx
3837                  * switch is enabled we must set the high water mark
3838                  * to the maximum FCRTH value.  This allows the Tx
3839                  * switch to function even under heavy Rx workloads.
3840                  */
3841                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3842         }
3843         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3844
3845         /* Configure pause time (2 TCs per register) */
3846         reg = hw->fc.pause_time * 0x00010001;
3847         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3848                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3849
3850         /* Configure flow control refresh threshold value */
3851         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3852
3853 out:
3854         return ret_val;
3855 }
3856
3857 static int
3858 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3859 {
3860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3861         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3862
3863         if (hw->mac.type != ixgbe_mac_82598EB) {
3864                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3865         }
3866         return ret_val;
3867 }
3868
3869 static int
3870 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3871 {
3872         int err;
3873         uint32_t rx_buf_size;
3874         uint32_t max_high_water;
3875         uint8_t tc_num;
3876         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3877         struct ixgbe_hw *hw =
3878                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879         struct ixgbe_dcb_config *dcb_config =
3880                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3881
3882         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3883                 ixgbe_fc_none,
3884                 ixgbe_fc_rx_pause,
3885                 ixgbe_fc_tx_pause,
3886                 ixgbe_fc_full
3887         };
3888
3889         PMD_INIT_FUNC_TRACE();
3890
3891         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3892         tc_num = map[pfc_conf->priority];
3893         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3894         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3895         /*
3896          * At least reserve one Ethernet frame for watermark
3897          * high_water/low_water in kilo bytes for ixgbe
3898          */
3899         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3900         if ((pfc_conf->fc.high_water > max_high_water) ||
3901             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3902                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3903                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3904                 return -EINVAL;
3905         }
3906
3907         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3908         hw->fc.pause_time = pfc_conf->fc.pause_time;
3909         hw->fc.send_xon = pfc_conf->fc.send_xon;
3910         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3911         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3912
3913         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3914
3915         /* Not negotiated is not an error case */
3916         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3917                 return 0;
3918
3919         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3920         return -EIO;
3921 }
3922
3923 static int
3924 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3925                           struct rte_eth_rss_reta_entry64 *reta_conf,
3926                           uint16_t reta_size)
3927 {
3928         uint16_t i, sp_reta_size;
3929         uint8_t j, mask;
3930         uint32_t reta, r;
3931         uint16_t idx, shift;
3932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3933         uint32_t reta_reg;
3934
3935         PMD_INIT_FUNC_TRACE();
3936
3937         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3938                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3939                         "NIC.");
3940                 return -ENOTSUP;
3941         }
3942
3943         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3944         if (reta_size != sp_reta_size) {
3945                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3946                         "(%d) doesn't match the number hardware can supported "
3947                         "(%d)\n", reta_size, sp_reta_size);
3948                 return -EINVAL;
3949         }
3950
3951         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3952                 idx = i / RTE_RETA_GROUP_SIZE;
3953                 shift = i % RTE_RETA_GROUP_SIZE;
3954                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3955                                                 IXGBE_4_BIT_MASK);
3956                 if (!mask)
3957                         continue;
3958                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3959                 if (mask == IXGBE_4_BIT_MASK)
3960                         r = 0;
3961                 else
3962                         r = IXGBE_READ_REG(hw, reta_reg);
3963                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3964                         if (mask & (0x1 << j))
3965                                 reta |= reta_conf[idx].reta[shift + j] <<
3966                                                         (CHAR_BIT * j);
3967                         else
3968                                 reta |= r & (IXGBE_8_BIT_MASK <<
3969                                                 (CHAR_BIT * j));
3970                 }
3971                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3972         }
3973
3974         return 0;
3975 }
3976
3977 static int
3978 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3979                          struct rte_eth_rss_reta_entry64 *reta_conf,
3980                          uint16_t reta_size)
3981 {
3982         uint16_t i, sp_reta_size;
3983         uint8_t j, mask;
3984         uint32_t reta;
3985         uint16_t idx, shift;
3986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3987         uint32_t reta_reg;
3988
3989         PMD_INIT_FUNC_TRACE();
3990         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3991         if (reta_size != sp_reta_size) {
3992                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3993                         "(%d) doesn't match the number hardware can supported "
3994                         "(%d)\n", reta_size, sp_reta_size);
3995                 return -EINVAL;
3996         }
3997
3998         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3999                 idx = i / RTE_RETA_GROUP_SIZE;
4000                 shift = i % RTE_RETA_GROUP_SIZE;
4001                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4002                                                 IXGBE_4_BIT_MASK);
4003                 if (!mask)
4004                         continue;
4005
4006                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4007                 reta = IXGBE_READ_REG(hw, reta_reg);
4008                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4009                         if (mask & (0x1 << j))
4010                                 reta_conf[idx].reta[shift + j] =
4011                                         ((reta >> (CHAR_BIT * j)) &
4012                                                 IXGBE_8_BIT_MASK);
4013                 }
4014         }
4015
4016         return 0;
4017 }
4018
4019 static void
4020 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4021                                 uint32_t index, uint32_t pool)
4022 {
4023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4024         uint32_t enable_addr = 1;
4025
4026         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4027 }
4028
4029 static void
4030 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4031 {
4032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4033
4034         ixgbe_clear_rar(hw, index);
4035 }
4036
4037 static void
4038 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4039 {
4040         ixgbe_remove_rar(dev, 0);
4041
4042         ixgbe_add_rar(dev, addr, 0, 0);
4043 }
4044
4045 static int
4046 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4047 {
4048         uint32_t hlreg0;
4049         uint32_t maxfrs;
4050         struct ixgbe_hw *hw;
4051         struct rte_eth_dev_info dev_info;
4052         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4053
4054         ixgbe_dev_info_get(dev, &dev_info);
4055
4056         /* check that mtu is within the allowed range */
4057         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4058                 return -EINVAL;
4059
4060         /* refuse mtu that requires the support of scattered packets when this
4061          * feature has not been enabled before.
4062          */
4063         if (!dev->data->scattered_rx &&
4064             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4065              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4066                 return -EINVAL;
4067
4068         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4069         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4070
4071         /* switch to jumbo mode if needed */
4072         if (frame_size > ETHER_MAX_LEN) {
4073                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4074                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4075         } else {
4076                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4077                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4078         }
4079         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4080
4081         /* update max frame size */
4082         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4083
4084         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4085         maxfrs &= 0x0000FFFF;
4086         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4087         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4088
4089         return 0;
4090 }
4091
4092 /*
4093  * Virtual Function operations
4094  */
4095 static void
4096 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4097 {
4098         PMD_INIT_FUNC_TRACE();
4099
4100         /* Clear interrupt mask to stop from interrupts being generated */
4101         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4102
4103         IXGBE_WRITE_FLUSH(hw);
4104 }
4105
4106 static void
4107 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4108 {
4109         PMD_INIT_FUNC_TRACE();
4110
4111         /* VF enable interrupt autoclean */
4112         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4113         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4114         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4115
4116         IXGBE_WRITE_FLUSH(hw);
4117 }
4118
4119 static int
4120 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4121 {
4122         struct rte_eth_conf *conf = &dev->data->dev_conf;
4123         struct ixgbe_adapter *adapter =
4124                         (struct ixgbe_adapter *)dev->data->dev_private;
4125
4126         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4127                      dev->data->port_id);
4128
4129         /*
4130          * VF has no ability to enable/disable HW CRC
4131          * Keep the persistent behavior the same as Host PF
4132          */
4133 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4134         if (!conf->rxmode.hw_strip_crc) {
4135                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4136                 conf->rxmode.hw_strip_crc = 1;
4137         }
4138 #else
4139         if (conf->rxmode.hw_strip_crc) {
4140                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4141                 conf->rxmode.hw_strip_crc = 0;
4142         }
4143 #endif
4144
4145         /*
4146          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4147          * allocation or vector Rx preconditions we will reset it.
4148          */
4149         adapter->rx_bulk_alloc_allowed = true;
4150         adapter->rx_vec_allowed = true;
4151
4152         return 0;
4153 }
4154
4155 static int
4156 ixgbevf_dev_start(struct rte_eth_dev *dev)
4157 {
4158         struct ixgbe_hw *hw =
4159                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4160         uint32_t intr_vector = 0;
4161         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4162
4163         int err, mask = 0;
4164
4165         PMD_INIT_FUNC_TRACE();
4166
4167         hw->mac.ops.reset_hw(hw);
4168         hw->mac.get_link_status = true;
4169
4170         /* negotiate mailbox API version to use with the PF. */
4171         ixgbevf_negotiate_api(hw);
4172
4173         ixgbevf_dev_tx_init(dev);
4174
4175         /* This can fail when allocating mbufs for descriptor rings */
4176         err = ixgbevf_dev_rx_init(dev);
4177         if (err) {
4178                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4179                 ixgbe_dev_clear_queues(dev);
4180                 return err;
4181         }
4182
4183         /* Set vfta */
4184         ixgbevf_set_vfta_all(dev, 1);
4185
4186         /* Set HW strip */
4187         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4188                 ETH_VLAN_EXTEND_MASK;
4189         ixgbevf_vlan_offload_set(dev, mask);
4190
4191         ixgbevf_dev_rxtx_start(dev);
4192
4193         /* check and configure queue intr-vector mapping */
4194         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4195                 intr_vector = dev->data->nb_rx_queues;
4196                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4197                         return -1;
4198         }
4199
4200         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4201                 intr_handle->intr_vec =
4202                         rte_zmalloc("intr_vec",
4203                                     dev->data->nb_rx_queues * sizeof(int), 0);
4204                 if (intr_handle->intr_vec == NULL) {
4205                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4206                                      " intr_vec\n", dev->data->nb_rx_queues);
4207                         return -ENOMEM;
4208                 }
4209         }
4210         ixgbevf_configure_msix(dev);
4211
4212         rte_intr_enable(intr_handle);
4213
4214         /* Re-enable interrupt for VF */
4215         ixgbevf_intr_enable(hw);
4216
4217         return 0;
4218 }
4219
4220 static void
4221 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4222 {
4223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4224         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4225
4226         PMD_INIT_FUNC_TRACE();
4227
4228         ixgbevf_intr_disable(hw);
4229
4230         hw->adapter_stopped = 1;
4231         ixgbe_stop_adapter(hw);
4232
4233         /*
4234           * Clear what we set, but we still keep shadow_vfta to
4235           * restore after device starts
4236           */
4237         ixgbevf_set_vfta_all(dev, 0);
4238
4239         /* Clear stored conf */
4240         dev->data->scattered_rx = 0;
4241
4242         ixgbe_dev_clear_queues(dev);
4243
4244         /* Clean datapath event and queue/vec mapping */
4245         rte_intr_efd_disable(intr_handle);
4246         if (intr_handle->intr_vec != NULL) {
4247                 rte_free(intr_handle->intr_vec);
4248                 intr_handle->intr_vec = NULL;
4249         }
4250 }
4251
4252 static void
4253 ixgbevf_dev_close(struct rte_eth_dev *dev)
4254 {
4255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4256
4257         PMD_INIT_FUNC_TRACE();
4258
4259         ixgbe_reset_hw(hw);
4260
4261         ixgbevf_dev_stop(dev);
4262
4263         ixgbe_dev_free_queues(dev);
4264
4265         /**
4266          * Remove the VF MAC address ro ensure
4267          * that the VF traffic goes to the PF
4268          * after stop, close and detach of the VF
4269          **/
4270         ixgbevf_remove_mac_addr(dev, 0);
4271 }
4272
4273 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4274 {
4275         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4276         struct ixgbe_vfta *shadow_vfta =
4277                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4278         int i = 0, j = 0, vfta = 0, mask = 1;
4279
4280         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4281                 vfta = shadow_vfta->vfta[i];
4282                 if (vfta) {
4283                         mask = 1;
4284                         for (j = 0; j < 32; j++) {
4285                                 if (vfta & mask)
4286                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4287                                                        on, false);
4288                                 mask <<= 1;
4289                         }
4290                 }
4291         }
4292
4293 }
4294
4295 static int
4296 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4297 {
4298         struct ixgbe_hw *hw =
4299                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4300         struct ixgbe_vfta *shadow_vfta =
4301                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4302         uint32_t vid_idx = 0;
4303         uint32_t vid_bit = 0;
4304         int ret = 0;
4305
4306         PMD_INIT_FUNC_TRACE();
4307
4308         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4309         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4310         if (ret) {
4311                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4312                 return ret;
4313         }
4314         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4315         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4316
4317         /* Save what we set and retore it after device reset */
4318         if (on)
4319                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4320         else
4321                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4322
4323         return 0;
4324 }
4325
4326 static void
4327 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4328 {
4329         struct ixgbe_hw *hw =
4330                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4331         uint32_t ctrl;
4332
4333         PMD_INIT_FUNC_TRACE();
4334
4335         if (queue >= hw->mac.max_rx_queues)
4336                 return;
4337
4338         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4339         if (on)
4340                 ctrl |= IXGBE_RXDCTL_VME;
4341         else
4342                 ctrl &= ~IXGBE_RXDCTL_VME;
4343         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4344
4345         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4346 }
4347
4348 static void
4349 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4350 {
4351         struct ixgbe_hw *hw =
4352                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4353         uint16_t i;
4354         int on = 0;
4355
4356         /* VF function only support hw strip feature, others are not support */
4357         if (mask & ETH_VLAN_STRIP_MASK) {
4358                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4359
4360                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4361                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4362         }
4363 }
4364
4365 static int
4366 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4367 {
4368         uint32_t reg_val;
4369
4370         /* we only need to do this if VMDq is enabled */
4371         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4372         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4373                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4374                 return -1;
4375         }
4376
4377         return 0;
4378 }
4379
4380 static uint32_t
4381 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4382 {
4383         uint32_t vector = 0;
4384
4385         switch (hw->mac.mc_filter_type) {
4386         case 0:   /* use bits [47:36] of the address */
4387                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4388                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4389                 break;
4390         case 1:   /* use bits [46:35] of the address */
4391                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4392                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4393                 break;
4394         case 2:   /* use bits [45:34] of the address */
4395                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4396                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4397                 break;
4398         case 3:   /* use bits [43:32] of the address */
4399                 vector = ((uc_addr->addr_bytes[4]) |
4400                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4401                 break;
4402         default:  /* Invalid mc_filter_type */
4403                 break;
4404         }
4405
4406         /* vector can only be 12-bits or boundary will be exceeded */
4407         vector &= 0xFFF;
4408         return vector;
4409 }
4410
4411 static int
4412 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4413                         uint8_t on)
4414 {
4415         uint32_t vector;
4416         uint32_t uta_idx;
4417         uint32_t reg_val;
4418         uint32_t uta_shift;
4419         uint32_t rc;
4420         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4421         const uint32_t ixgbe_uta_bit_shift = 5;
4422         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4423         const uint32_t bit1 = 0x1;
4424
4425         struct ixgbe_hw *hw =
4426                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4427         struct ixgbe_uta_info *uta_info =
4428                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4429
4430         /* The UTA table only exists on 82599 hardware and newer */
4431         if (hw->mac.type < ixgbe_mac_82599EB)
4432                 return -ENOTSUP;
4433
4434         vector = ixgbe_uta_vector(hw, mac_addr);
4435         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4436         uta_shift = vector & ixgbe_uta_bit_mask;
4437
4438         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4439         if (rc == on)
4440                 return 0;
4441
4442         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4443         if (on) {
4444                 uta_info->uta_in_use++;
4445                 reg_val |= (bit1 << uta_shift);
4446                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4447         } else {
4448                 uta_info->uta_in_use--;
4449                 reg_val &= ~(bit1 << uta_shift);
4450                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4451         }
4452
4453         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4454
4455         if (uta_info->uta_in_use > 0)
4456                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4457                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4458         else
4459                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4460
4461         return 0;
4462 }
4463
4464 static int
4465 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4466 {
4467         int i;
4468         struct ixgbe_hw *hw =
4469                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4470         struct ixgbe_uta_info *uta_info =
4471                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4472
4473         /* The UTA table only exists on 82599 hardware and newer */
4474         if (hw->mac.type < ixgbe_mac_82599EB)
4475                 return -ENOTSUP;
4476
4477         if (on) {
4478                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4479                         uta_info->uta_shadow[i] = ~0;
4480                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4481                 }
4482         } else {
4483                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4484                         uta_info->uta_shadow[i] = 0;
4485                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4486                 }
4487         }
4488         return 0;
4489
4490 }
4491
4492 uint32_t
4493 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4494 {
4495         uint32_t new_val = orig_val;
4496
4497         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4498                 new_val |= IXGBE_VMOLR_AUPE;
4499         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4500                 new_val |= IXGBE_VMOLR_ROMPE;
4501         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4502                 new_val |= IXGBE_VMOLR_ROPE;
4503         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4504                 new_val |= IXGBE_VMOLR_BAM;
4505         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4506                 new_val |= IXGBE_VMOLR_MPE;
4507
4508         return new_val;
4509 }
4510
4511 static int
4512 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4513                                uint16_t rx_mask, uint8_t on)
4514 {
4515         int val = 0;
4516
4517         struct ixgbe_hw *hw =
4518                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4519         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4520
4521         if (hw->mac.type == ixgbe_mac_82598EB) {
4522                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4523                              " on 82599 hardware and newer");
4524                 return -ENOTSUP;
4525         }
4526         if (ixgbe_vmdq_mode_check(hw) < 0)
4527                 return -ENOTSUP;
4528
4529         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4530
4531         if (on)
4532                 vmolr |= val;
4533         else
4534                 vmolr &= ~val;
4535
4536         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4537
4538         return 0;
4539 }
4540
4541 static int
4542 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4543 {
4544         uint32_t reg, addr;
4545         uint32_t val;
4546         const uint8_t bit1 = 0x1;
4547
4548         struct ixgbe_hw *hw =
4549                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4550
4551         if (ixgbe_vmdq_mode_check(hw) < 0)
4552                 return -ENOTSUP;
4553
4554         if (pool >= ETH_64_POOLS)
4555                 return -EINVAL;
4556
4557         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4558         if (pool >= 32) {
4559                 addr = IXGBE_VFRE(1);
4560                 val = bit1 << (pool - 32);
4561         } else {
4562                 addr = IXGBE_VFRE(0);
4563                 val = bit1 << pool;
4564         }
4565
4566         reg = IXGBE_READ_REG(hw, addr);
4567
4568         if (on)
4569                 reg |= val;
4570         else
4571                 reg &= ~val;
4572
4573         IXGBE_WRITE_REG(hw, addr, reg);
4574
4575         return 0;
4576 }
4577
4578 static int
4579 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4580 {
4581         uint32_t reg, addr;
4582         uint32_t val;
4583         const uint8_t bit1 = 0x1;
4584
4585         struct ixgbe_hw *hw =
4586                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4587
4588         if (ixgbe_vmdq_mode_check(hw) < 0)
4589                 return -ENOTSUP;
4590
4591         if (pool >= ETH_64_POOLS)
4592                 return -EINVAL;
4593
4594         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4595         if (pool >= 32) {
4596                 addr = IXGBE_VFTE(1);
4597                 val = bit1 << (pool - 32);
4598         } else {
4599                 addr = IXGBE_VFTE(0);
4600                 val = bit1 << pool;
4601         }
4602
4603         reg = IXGBE_READ_REG(hw, addr);
4604
4605         if (on)
4606                 reg |= val;
4607         else
4608                 reg &= ~val;
4609
4610         IXGBE_WRITE_REG(hw, addr, reg);
4611
4612         return 0;
4613 }
4614
4615 static int
4616 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4617                         uint64_t pool_mask, uint8_t vlan_on)
4618 {
4619         int ret = 0;
4620         uint16_t pool_idx;
4621         struct ixgbe_hw *hw =
4622                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4623
4624         if (ixgbe_vmdq_mode_check(hw) < 0)
4625                 return -ENOTSUP;
4626         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4627                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4628                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4629                                                    vlan_on, false);
4630                         if (ret < 0)
4631                                 return ret;
4632                 }
4633         }
4634
4635         return ret;
4636 }
4637
4638 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4639 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4640 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4641 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4642 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4643         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4644         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4645
4646 static int
4647 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4648                         struct rte_eth_mirror_conf *mirror_conf,
4649                         uint8_t rule_id, uint8_t on)
4650 {
4651         uint32_t mr_ctl, vlvf;
4652         uint32_t mp_lsb = 0;
4653         uint32_t mv_msb = 0;
4654         uint32_t mv_lsb = 0;
4655         uint32_t mp_msb = 0;
4656         uint8_t i = 0;
4657         int reg_index = 0;
4658         uint64_t vlan_mask = 0;
4659
4660         const uint8_t pool_mask_offset = 32;
4661         const uint8_t vlan_mask_offset = 32;
4662         const uint8_t dst_pool_offset = 8;
4663         const uint8_t rule_mr_offset  = 4;
4664         const uint8_t mirror_rule_mask = 0x0F;
4665
4666         struct ixgbe_mirror_info *mr_info =
4667                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4668         struct ixgbe_hw *hw =
4669                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4670         uint8_t mirror_type = 0;
4671
4672         if (ixgbe_vmdq_mode_check(hw) < 0)
4673                 return -ENOTSUP;
4674
4675         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4676                 return -EINVAL;
4677
4678         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4679                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4680                         mirror_conf->rule_type);
4681                 return -EINVAL;
4682         }
4683
4684         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4685                 mirror_type |= IXGBE_MRCTL_VLME;
4686                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4687                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4688                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4689                                 /* search vlan id related pool vlan filter index */
4690                                 reg_index = ixgbe_find_vlvf_slot(hw,
4691                                                  mirror_conf->vlan.vlan_id[i],
4692                                                  false);
4693                                 if (reg_index < 0)
4694                                         return -EINVAL;
4695                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4696                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4697                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4698                                       mirror_conf->vlan.vlan_id[i]))
4699                                         vlan_mask |= (1ULL << reg_index);
4700                                 else
4701                                         return -EINVAL;
4702                         }
4703                 }
4704
4705                 if (on) {
4706                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4707                         mv_msb = vlan_mask >> vlan_mask_offset;
4708
4709                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4710                                                 mirror_conf->vlan.vlan_mask;
4711                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4712                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4713                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4714                                                 mirror_conf->vlan.vlan_id[i];
4715                         }
4716                 } else {
4717                         mv_lsb = 0;
4718                         mv_msb = 0;
4719                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4720                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4721                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4722                 }
4723         }
4724
4725         /*
4726          * if enable pool mirror, write related pool mask register,if disable
4727          * pool mirror, clear PFMRVM register
4728          */
4729         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4730                 mirror_type |= IXGBE_MRCTL_VPME;
4731                 if (on) {
4732                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4733                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4734                         mr_info->mr_conf[rule_id].pool_mask =
4735                                         mirror_conf->pool_mask;
4736
4737                 } else {
4738                         mp_lsb = 0;
4739                         mp_msb = 0;
4740                         mr_info->mr_conf[rule_id].pool_mask = 0;
4741                 }
4742         }
4743         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4744                 mirror_type |= IXGBE_MRCTL_UPME;
4745         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4746                 mirror_type |= IXGBE_MRCTL_DPME;
4747
4748         /* read  mirror control register and recalculate it */
4749         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4750
4751         if (on) {
4752                 mr_ctl |= mirror_type;
4753                 mr_ctl &= mirror_rule_mask;
4754                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4755         } else
4756                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4757
4758         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4759         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4760
4761         /* write mirrror control  register */
4762         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4763
4764         /* write pool mirrror control  register */
4765         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4766                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4767                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4768                                 mp_msb);
4769         }
4770         /* write VLAN mirrror control  register */
4771         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4772                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4773                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4774                                 mv_msb);
4775         }
4776
4777         return 0;
4778 }
4779
4780 static int
4781 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4782 {
4783         int mr_ctl = 0;
4784         uint32_t lsb_val = 0;
4785         uint32_t msb_val = 0;
4786         const uint8_t rule_mr_offset = 4;
4787
4788         struct ixgbe_hw *hw =
4789                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4790         struct ixgbe_mirror_info *mr_info =
4791                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4792
4793         if (ixgbe_vmdq_mode_check(hw) < 0)
4794                 return -ENOTSUP;
4795
4796         memset(&mr_info->mr_conf[rule_id], 0,
4797                 sizeof(struct rte_eth_mirror_conf));
4798
4799         /* clear PFVMCTL register */
4800         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4801
4802         /* clear pool mask register */
4803         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4804         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4805
4806         /* clear vlan mask register */
4807         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4808         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4809
4810         return 0;
4811 }
4812
4813 static int
4814 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4815 {
4816         uint32_t mask;
4817         struct ixgbe_hw *hw =
4818                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4819
4820         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4821         mask |= (1 << IXGBE_MISC_VEC_ID);
4822         RTE_SET_USED(queue_id);
4823         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4824
4825         rte_intr_enable(&dev->pci_dev->intr_handle);
4826
4827         return 0;
4828 }
4829
4830 static int
4831 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4832 {
4833         uint32_t mask;
4834         struct ixgbe_hw *hw =
4835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4836
4837         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4838         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4839         RTE_SET_USED(queue_id);
4840         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4841
4842         return 0;
4843 }
4844
4845 static int
4846 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4847 {
4848         uint32_t mask;
4849         struct ixgbe_hw *hw =
4850                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4851         struct ixgbe_interrupt *intr =
4852                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4853
4854         if (queue_id < 16) {
4855                 ixgbe_disable_intr(hw);
4856                 intr->mask |= (1 << queue_id);
4857                 ixgbe_enable_intr(dev);
4858         } else if (queue_id < 32) {
4859                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4860                 mask &= (1 << queue_id);
4861                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4862         } else if (queue_id < 64) {
4863                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4864                 mask &= (1 << (queue_id - 32));
4865                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4866         }
4867         rte_intr_enable(&dev->pci_dev->intr_handle);
4868
4869         return 0;
4870 }
4871
4872 static int
4873 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4874 {
4875         uint32_t mask;
4876         struct ixgbe_hw *hw =
4877                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4878         struct ixgbe_interrupt *intr =
4879                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4880
4881         if (queue_id < 16) {
4882                 ixgbe_disable_intr(hw);
4883                 intr->mask &= ~(1 << queue_id);
4884                 ixgbe_enable_intr(dev);
4885         } else if (queue_id < 32) {
4886                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4887                 mask &= ~(1 << queue_id);
4888                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4889         } else if (queue_id < 64) {
4890                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4891                 mask &= ~(1 << (queue_id - 32));
4892                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4893         }
4894
4895         return 0;
4896 }
4897
4898 static void
4899 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4900                      uint8_t queue, uint8_t msix_vector)
4901 {
4902         uint32_t tmp, idx;
4903
4904         if (direction == -1) {
4905                 /* other causes */
4906                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4907                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4908                 tmp &= ~0xFF;
4909                 tmp |= msix_vector;
4910                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4911         } else {
4912                 /* rx or tx cause */
4913                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4914                 idx = ((16 * (queue & 1)) + (8 * direction));
4915                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4916                 tmp &= ~(0xFF << idx);
4917                 tmp |= (msix_vector << idx);
4918                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4919         }
4920 }
4921
4922 /**
4923  * set the IVAR registers, mapping interrupt causes to vectors
4924  * @param hw
4925  *  pointer to ixgbe_hw struct
4926  * @direction
4927  *  0 for Rx, 1 for Tx, -1 for other causes
4928  * @queue
4929  *  queue to map the corresponding interrupt to
4930  * @msix_vector
4931  *  the vector to map to the corresponding queue
4932  */
4933 static void
4934 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4935                    uint8_t queue, uint8_t msix_vector)
4936 {
4937         uint32_t tmp, idx;
4938
4939         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4940         if (hw->mac.type == ixgbe_mac_82598EB) {
4941                 if (direction == -1)
4942                         direction = 0;
4943                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4944                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4945                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4946                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4947                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4948         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4949                         (hw->mac.type == ixgbe_mac_X540)) {
4950                 if (direction == -1) {
4951                         /* other causes */
4952                         idx = ((queue & 1) * 8);
4953                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4954                         tmp &= ~(0xFF << idx);
4955                         tmp |= (msix_vector << idx);
4956                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4957                 } else {
4958                         /* rx or tx causes */
4959                         idx = ((16 * (queue & 1)) + (8 * direction));
4960                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4961                         tmp &= ~(0xFF << idx);
4962                         tmp |= (msix_vector << idx);
4963                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4964                 }
4965         }
4966 }
4967
4968 static void
4969 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4970 {
4971         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4972         struct ixgbe_hw *hw =
4973                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4974         uint32_t q_idx;
4975         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4976
4977         /* Configure VF other cause ivar */
4978         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4979
4980         /* won't configure msix register if no mapping is done
4981          * between intr vector and event fd.
4982          */
4983         if (!rte_intr_dp_is_en(intr_handle))
4984                 return;
4985
4986         /* Configure all RX queues of VF */
4987         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4988                 /* Force all queue use vector 0,
4989                  * as IXGBE_VF_MAXMSIVECOTR = 1
4990                  */
4991                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4992                 intr_handle->intr_vec[q_idx] = vector_idx;
4993         }
4994 }
4995
4996 /**
4997  * Sets up the hardware to properly generate MSI-X interrupts
4998  * @hw
4999  *  board private structure
5000  */
5001 static void
5002 ixgbe_configure_msix(struct rte_eth_dev *dev)
5003 {
5004         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5005         struct ixgbe_hw *hw =
5006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5007         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5008         uint32_t vec = IXGBE_MISC_VEC_ID;
5009         uint32_t mask;
5010         uint32_t gpie;
5011
5012         /* won't configure msix register if no mapping is done
5013          * between intr vector and event fd
5014          */
5015         if (!rte_intr_dp_is_en(intr_handle))
5016                 return;
5017
5018         if (rte_intr_allow_others(intr_handle))
5019                 vec = base = IXGBE_RX_VEC_START;
5020
5021         /* setup GPIE for MSI-x mode */
5022         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5023         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5024                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5025         /* auto clearing and auto setting corresponding bits in EIMS
5026          * when MSI-X interrupt is triggered
5027          */
5028         if (hw->mac.type == ixgbe_mac_82598EB) {
5029                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5030         } else {
5031                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5032                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5033         }
5034         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5035
5036         /* Populate the IVAR table and set the ITR values to the
5037          * corresponding register.
5038          */
5039         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5040              queue_id++) {
5041                 /* by default, 1:1 mapping */
5042                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5043                 intr_handle->intr_vec[queue_id] = vec;
5044                 if (vec < base + intr_handle->nb_efd - 1)
5045                         vec++;
5046         }
5047
5048         switch (hw->mac.type) {
5049         case ixgbe_mac_82598EB:
5050                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5051                                    IXGBE_MISC_VEC_ID);
5052                 break;
5053         case ixgbe_mac_82599EB:
5054         case ixgbe_mac_X540:
5055                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5056                 break;
5057         default:
5058                 break;
5059         }
5060         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5061                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5062
5063         /* set up to autoclear timer, and the vectors */
5064         mask = IXGBE_EIMS_ENABLE_MASK;
5065         mask &= ~(IXGBE_EIMS_OTHER |
5066                   IXGBE_EIMS_MAILBOX |
5067                   IXGBE_EIMS_LSC);
5068
5069         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5070 }
5071
5072 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5073         uint16_t queue_idx, uint16_t tx_rate)
5074 {
5075         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5076         uint32_t rf_dec, rf_int;
5077         uint32_t bcnrc_val;
5078         uint16_t link_speed = dev->data->dev_link.link_speed;
5079
5080         if (queue_idx >= hw->mac.max_tx_queues)
5081                 return -EINVAL;
5082
5083         if (tx_rate != 0) {
5084                 /* Calculate the rate factor values to set */
5085                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5086                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5087                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5088
5089                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5090                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5091                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5092                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5093         } else {
5094                 bcnrc_val = 0;
5095         }
5096
5097         /*
5098          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5099          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5100          * set as 0x4.
5101          */
5102         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5103                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5104                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5105                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5106                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5107         else
5108                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5109                         IXGBE_MMW_SIZE_DEFAULT);
5110
5111         /* Set RTTBCNRC of queue X */
5112         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5113         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5114         IXGBE_WRITE_FLUSH(hw);
5115
5116         return 0;
5117 }
5118
5119 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5120         uint16_t tx_rate, uint64_t q_msk)
5121 {
5122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123         struct ixgbe_vf_info *vfinfo =
5124                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5125         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5126         uint32_t queue_stride =
5127                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5128         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5129         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5130         uint16_t total_rate = 0;
5131
5132         if (queue_end >= hw->mac.max_tx_queues)
5133                 return -EINVAL;
5134
5135         if (vfinfo != NULL) {
5136                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5137                         if (vf_idx == vf)
5138                                 continue;
5139                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5140                                 idx++)
5141                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5142                 }
5143         } else
5144                 return -EINVAL;
5145
5146         /* Store tx_rate for this vf. */
5147         for (idx = 0; idx < nb_q_per_pool; idx++) {
5148                 if (((uint64_t)0x1 << idx) & q_msk) {
5149                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5150                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5151                         total_rate += tx_rate;
5152                 }
5153         }
5154
5155         if (total_rate > dev->data->dev_link.link_speed) {
5156                 /*
5157                  * Reset stored TX rate of the VF if it causes exceed
5158                  * link speed.
5159                  */
5160                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5161                 return -EINVAL;
5162         }
5163
5164         /* Set RTTBCNRC of each queue/pool for vf X  */
5165         for (; queue_idx <= queue_end; queue_idx++) {
5166                 if (0x1 & q_msk)
5167                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5168                 q_msk = q_msk >> 1;
5169         }
5170
5171         return 0;
5172 }
5173
5174 static void
5175 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5176                      __attribute__((unused)) uint32_t index,
5177                      __attribute__((unused)) uint32_t pool)
5178 {
5179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5180         int diag;
5181
5182         /*
5183          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5184          * operation. Trap this case to avoid exhausting the [very limited]
5185          * set of PF resources used to store VF MAC addresses.
5186          */
5187         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5188                 return;
5189         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5190         if (diag == 0)
5191                 return;
5192         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5193 }
5194
5195 static void
5196 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5197 {
5198         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5199         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5200         struct ether_addr *mac_addr;
5201         uint32_t i;
5202         int diag;
5203
5204         /*
5205          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5206          * not support the deletion of a given MAC address.
5207          * Instead, it imposes to delete all MAC addresses, then to add again
5208          * all MAC addresses with the exception of the one to be deleted.
5209          */
5210         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5211
5212         /*
5213          * Add again all MAC addresses, with the exception of the deleted one
5214          * and of the permanent MAC address.
5215          */
5216         for (i = 0, mac_addr = dev->data->mac_addrs;
5217              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5218                 /* Skip the deleted MAC address */
5219                 if (i == index)
5220                         continue;
5221                 /* Skip NULL MAC addresses */
5222                 if (is_zero_ether_addr(mac_addr))
5223                         continue;
5224                 /* Skip the permanent MAC address */
5225                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5226                         continue;
5227                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5228                 if (diag != 0)
5229                         PMD_DRV_LOG(ERR,
5230                                     "Adding again MAC address "
5231                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5232                                     "diag=%d",
5233                                     mac_addr->addr_bytes[0],
5234                                     mac_addr->addr_bytes[1],
5235                                     mac_addr->addr_bytes[2],
5236                                     mac_addr->addr_bytes[3],
5237                                     mac_addr->addr_bytes[4],
5238                                     mac_addr->addr_bytes[5],
5239                                     diag);
5240         }
5241 }
5242
5243 static void
5244 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5245 {
5246         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5247
5248         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5249 }
5250
5251 #define MAC_TYPE_FILTER_SUP(type)    do {\
5252         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5253                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5254                 (type) != ixgbe_mac_X550EM_a)\
5255                 return -ENOTSUP;\
5256 } while (0)
5257
5258 static int
5259 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5260                         struct rte_eth_syn_filter *filter,
5261                         bool add)
5262 {
5263         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5264         uint32_t synqf;
5265
5266         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5267                 return -EINVAL;
5268
5269         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5270
5271         if (add) {
5272                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5273                         return -EINVAL;
5274                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5275                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5276
5277                 if (filter->hig_pri)
5278                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5279                 else
5280                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5281         } else {
5282                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5283                         return -ENOENT;
5284                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5285         }
5286         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5287         IXGBE_WRITE_FLUSH(hw);
5288         return 0;
5289 }
5290
5291 static int
5292 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5293                         struct rte_eth_syn_filter *filter)
5294 {
5295         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5296         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5297
5298         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5299                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5300                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5301                 return 0;
5302         }
5303         return -ENOENT;
5304 }
5305
5306 static int
5307 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5308                         enum rte_filter_op filter_op,
5309                         void *arg)
5310 {
5311         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5312         int ret;
5313
5314         MAC_TYPE_FILTER_SUP(hw->mac.type);
5315
5316         if (filter_op == RTE_ETH_FILTER_NOP)
5317                 return 0;
5318
5319         if (arg == NULL) {
5320                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5321                             filter_op);
5322                 return -EINVAL;
5323         }
5324
5325         switch (filter_op) {
5326         case RTE_ETH_FILTER_ADD:
5327                 ret = ixgbe_syn_filter_set(dev,
5328                                 (struct rte_eth_syn_filter *)arg,
5329                                 TRUE);
5330                 break;
5331         case RTE_ETH_FILTER_DELETE:
5332                 ret = ixgbe_syn_filter_set(dev,
5333                                 (struct rte_eth_syn_filter *)arg,
5334                                 FALSE);
5335                 break;
5336         case RTE_ETH_FILTER_GET:
5337                 ret = ixgbe_syn_filter_get(dev,
5338                                 (struct rte_eth_syn_filter *)arg);
5339                 break;
5340         default:
5341                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5342                 ret = -EINVAL;
5343                 break;
5344         }
5345
5346         return ret;
5347 }
5348
5349
5350 static inline enum ixgbe_5tuple_protocol
5351 convert_protocol_type(uint8_t protocol_value)
5352 {
5353         if (protocol_value == IPPROTO_TCP)
5354                 return IXGBE_FILTER_PROTOCOL_TCP;
5355         else if (protocol_value == IPPROTO_UDP)
5356                 return IXGBE_FILTER_PROTOCOL_UDP;
5357         else if (protocol_value == IPPROTO_SCTP)
5358                 return IXGBE_FILTER_PROTOCOL_SCTP;
5359         else
5360                 return IXGBE_FILTER_PROTOCOL_NONE;
5361 }
5362
5363 /*
5364  * add a 5tuple filter
5365  *
5366  * @param
5367  * dev: Pointer to struct rte_eth_dev.
5368  * index: the index the filter allocates.
5369  * filter: ponter to the filter that will be added.
5370  * rx_queue: the queue id the filter assigned to.
5371  *
5372  * @return
5373  *    - On success, zero.
5374  *    - On failure, a negative value.
5375  */
5376 static int
5377 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5378                         struct ixgbe_5tuple_filter *filter)
5379 {
5380         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5381         struct ixgbe_filter_info *filter_info =
5382                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5383         int i, idx, shift;
5384         uint32_t ftqf, sdpqf;
5385         uint32_t l34timir = 0;
5386         uint8_t mask = 0xff;
5387
5388         /*
5389          * look for an unused 5tuple filter index,
5390          * and insert the filter to list.
5391          */
5392         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5393                 idx = i / (sizeof(uint32_t) * NBBY);
5394                 shift = i % (sizeof(uint32_t) * NBBY);
5395                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5396                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5397                         filter->index = i;
5398                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5399                                           filter,
5400                                           entries);
5401                         break;
5402                 }
5403         }
5404         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5405                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5406                 return -ENOSYS;
5407         }
5408
5409         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5410                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5411         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5412
5413         ftqf = (uint32_t)(filter->filter_info.proto &
5414                 IXGBE_FTQF_PROTOCOL_MASK);
5415         ftqf |= (uint32_t)((filter->filter_info.priority &
5416                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5417         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5418                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5419         if (filter->filter_info.dst_ip_mask == 0)
5420                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5421         if (filter->filter_info.src_port_mask == 0)
5422                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5423         if (filter->filter_info.dst_port_mask == 0)
5424                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5425         if (filter->filter_info.proto_mask == 0)
5426                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5427         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5428         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5429         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5430
5431         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5432         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5433         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5434         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5435
5436         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5437         l34timir |= (uint32_t)(filter->queue <<
5438                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5439         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5440         return 0;
5441 }
5442
5443 /*
5444  * remove a 5tuple filter
5445  *
5446  * @param
5447  * dev: Pointer to struct rte_eth_dev.
5448  * filter: the pointer of the filter will be removed.
5449  */
5450 static void
5451 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5452                         struct ixgbe_5tuple_filter *filter)
5453 {
5454         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5455         struct ixgbe_filter_info *filter_info =
5456                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5457         uint16_t index = filter->index;
5458
5459         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5460                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5461         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5462         rte_free(filter);
5463
5464         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5465         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5466         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5467         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5468         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5469 }
5470
5471 static int
5472 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5473 {
5474         struct ixgbe_hw *hw;
5475         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5476
5477         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5478
5479         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5480                 return -EINVAL;
5481
5482         /* refuse mtu that requires the support of scattered packets when this
5483          * feature has not been enabled before.
5484          */
5485         if (!dev->data->scattered_rx &&
5486             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5487              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5488                 return -EINVAL;
5489
5490         /*
5491          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5492          * request of the version 2.0 of the mailbox API.
5493          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5494          * of the mailbox API.
5495          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5496          * prior to 3.11.33 which contains the following change:
5497          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5498          */
5499         ixgbevf_rlpml_set_vf(hw, max_frame);
5500
5501         /* update max frame size */
5502         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5503         return 0;
5504 }
5505
5506 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5507         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5508                 return -ENOTSUP;\
5509 } while (0)
5510
5511 static inline struct ixgbe_5tuple_filter *
5512 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5513                         struct ixgbe_5tuple_filter_info *key)
5514 {
5515         struct ixgbe_5tuple_filter *it;
5516
5517         TAILQ_FOREACH(it, filter_list, entries) {
5518                 if (memcmp(key, &it->filter_info,
5519                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5520                         return it;
5521                 }
5522         }
5523         return NULL;
5524 }
5525
5526 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5527 static inline int
5528 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5529                         struct ixgbe_5tuple_filter_info *filter_info)
5530 {
5531         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5532                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5533                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5534                 return -EINVAL;
5535
5536         switch (filter->dst_ip_mask) {
5537         case UINT32_MAX:
5538                 filter_info->dst_ip_mask = 0;
5539                 filter_info->dst_ip = filter->dst_ip;
5540                 break;
5541         case 0:
5542                 filter_info->dst_ip_mask = 1;
5543                 break;
5544         default:
5545                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5546                 return -EINVAL;
5547         }
5548
5549         switch (filter->src_ip_mask) {
5550         case UINT32_MAX:
5551                 filter_info->src_ip_mask = 0;
5552                 filter_info->src_ip = filter->src_ip;
5553                 break;
5554         case 0:
5555                 filter_info->src_ip_mask = 1;
5556                 break;
5557         default:
5558                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5559                 return -EINVAL;
5560         }
5561
5562         switch (filter->dst_port_mask) {
5563         case UINT16_MAX:
5564                 filter_info->dst_port_mask = 0;
5565                 filter_info->dst_port = filter->dst_port;
5566                 break;
5567         case 0:
5568                 filter_info->dst_port_mask = 1;
5569                 break;
5570         default:
5571                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5572                 return -EINVAL;
5573         }
5574
5575         switch (filter->src_port_mask) {
5576         case UINT16_MAX:
5577                 filter_info->src_port_mask = 0;
5578                 filter_info->src_port = filter->src_port;
5579                 break;
5580         case 0:
5581                 filter_info->src_port_mask = 1;
5582                 break;
5583         default:
5584                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5585                 return -EINVAL;
5586         }
5587
5588         switch (filter->proto_mask) {
5589         case UINT8_MAX:
5590                 filter_info->proto_mask = 0;
5591                 filter_info->proto =
5592                         convert_protocol_type(filter->proto);
5593                 break;
5594         case 0:
5595                 filter_info->proto_mask = 1;
5596                 break;
5597         default:
5598                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5599                 return -EINVAL;
5600         }
5601
5602         filter_info->priority = (uint8_t)filter->priority;
5603         return 0;
5604 }
5605
5606 /*
5607  * add or delete a ntuple filter
5608  *
5609  * @param
5610  * dev: Pointer to struct rte_eth_dev.
5611  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5612  * add: if true, add filter, if false, remove filter
5613  *
5614  * @return
5615  *    - On success, zero.
5616  *    - On failure, a negative value.
5617  */
5618 static int
5619 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5620                         struct rte_eth_ntuple_filter *ntuple_filter,
5621                         bool add)
5622 {
5623         struct ixgbe_filter_info *filter_info =
5624                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5625         struct ixgbe_5tuple_filter_info filter_5tuple;
5626         struct ixgbe_5tuple_filter *filter;
5627         int ret;
5628
5629         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5630                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5631                 return -EINVAL;
5632         }
5633
5634         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5635         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5636         if (ret < 0)
5637                 return ret;
5638
5639         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5640                                          &filter_5tuple);
5641         if (filter != NULL && add) {
5642                 PMD_DRV_LOG(ERR, "filter exists.");
5643                 return -EEXIST;
5644         }
5645         if (filter == NULL && !add) {
5646                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5647                 return -ENOENT;
5648         }
5649
5650         if (add) {
5651                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5652                                 sizeof(struct ixgbe_5tuple_filter), 0);
5653                 if (filter == NULL)
5654                         return -ENOMEM;
5655                 (void)rte_memcpy(&filter->filter_info,
5656                                  &filter_5tuple,
5657                                  sizeof(struct ixgbe_5tuple_filter_info));
5658                 filter->queue = ntuple_filter->queue;
5659                 ret = ixgbe_add_5tuple_filter(dev, filter);
5660                 if (ret < 0) {
5661                         rte_free(filter);
5662                         return ret;
5663                 }
5664         } else
5665                 ixgbe_remove_5tuple_filter(dev, filter);
5666
5667         return 0;
5668 }
5669
5670 /*
5671  * get a ntuple filter
5672  *
5673  * @param
5674  * dev: Pointer to struct rte_eth_dev.
5675  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5676  *
5677  * @return
5678  *    - On success, zero.
5679  *    - On failure, a negative value.
5680  */
5681 static int
5682 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5683                         struct rte_eth_ntuple_filter *ntuple_filter)
5684 {
5685         struct ixgbe_filter_info *filter_info =
5686                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5687         struct ixgbe_5tuple_filter_info filter_5tuple;
5688         struct ixgbe_5tuple_filter *filter;
5689         int ret;
5690
5691         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5692                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5693                 return -EINVAL;
5694         }
5695
5696         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5697         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5698         if (ret < 0)
5699                 return ret;
5700
5701         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5702                                          &filter_5tuple);
5703         if (filter == NULL) {
5704                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5705                 return -ENOENT;
5706         }
5707         ntuple_filter->queue = filter->queue;
5708         return 0;
5709 }
5710
5711 /*
5712  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5713  * @dev: pointer to rte_eth_dev structure
5714  * @filter_op:operation will be taken.
5715  * @arg: a pointer to specific structure corresponding to the filter_op
5716  *
5717  * @return
5718  *    - On success, zero.
5719  *    - On failure, a negative value.
5720  */
5721 static int
5722 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5723                                 enum rte_filter_op filter_op,
5724                                 void *arg)
5725 {
5726         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5727         int ret;
5728
5729         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5730
5731         if (filter_op == RTE_ETH_FILTER_NOP)
5732                 return 0;
5733
5734         if (arg == NULL) {
5735                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5736                             filter_op);
5737                 return -EINVAL;
5738         }
5739
5740         switch (filter_op) {
5741         case RTE_ETH_FILTER_ADD:
5742                 ret = ixgbe_add_del_ntuple_filter(dev,
5743                         (struct rte_eth_ntuple_filter *)arg,
5744                         TRUE);
5745                 break;
5746         case RTE_ETH_FILTER_DELETE:
5747                 ret = ixgbe_add_del_ntuple_filter(dev,
5748                         (struct rte_eth_ntuple_filter *)arg,
5749                         FALSE);
5750                 break;
5751         case RTE_ETH_FILTER_GET:
5752                 ret = ixgbe_get_ntuple_filter(dev,
5753                         (struct rte_eth_ntuple_filter *)arg);
5754                 break;
5755         default:
5756                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5757                 ret = -EINVAL;
5758                 break;
5759         }
5760         return ret;
5761 }
5762
5763 static inline int
5764 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5765                         uint16_t ethertype)
5766 {
5767         int i;
5768
5769         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5770                 if (filter_info->ethertype_filters[i] == ethertype &&
5771                     (filter_info->ethertype_mask & (1 << i)))
5772                         return i;
5773         }
5774         return -1;
5775 }
5776
5777 static inline int
5778 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5779                         uint16_t ethertype)
5780 {
5781         int i;
5782
5783         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5784                 if (!(filter_info->ethertype_mask & (1 << i))) {
5785                         filter_info->ethertype_mask |= 1 << i;
5786                         filter_info->ethertype_filters[i] = ethertype;
5787                         return i;
5788                 }
5789         }
5790         return -1;
5791 }
5792
5793 static inline int
5794 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5795                         uint8_t idx)
5796 {
5797         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5798                 return -1;
5799         filter_info->ethertype_mask &= ~(1 << idx);
5800         filter_info->ethertype_filters[idx] = 0;
5801         return idx;
5802 }
5803
5804 static int
5805 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5806                         struct rte_eth_ethertype_filter *filter,
5807                         bool add)
5808 {
5809         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5810         struct ixgbe_filter_info *filter_info =
5811                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5812         uint32_t etqf = 0;
5813         uint32_t etqs = 0;
5814         int ret;
5815
5816         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5817                 return -EINVAL;
5818
5819         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5820                 filter->ether_type == ETHER_TYPE_IPv6) {
5821                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5822                         " ethertype filter.", filter->ether_type);
5823                 return -EINVAL;
5824         }
5825
5826         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5827                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5828                 return -EINVAL;
5829         }
5830         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5831                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5832                 return -EINVAL;
5833         }
5834
5835         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5836         if (ret >= 0 && add) {
5837                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5838                             filter->ether_type);
5839                 return -EEXIST;
5840         }
5841         if (ret < 0 && !add) {
5842                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5843                             filter->ether_type);
5844                 return -ENOENT;
5845         }
5846
5847         if (add) {
5848                 ret = ixgbe_ethertype_filter_insert(filter_info,
5849                         filter->ether_type);
5850                 if (ret < 0) {
5851                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5852                         return -ENOSYS;
5853                 }
5854                 etqf = IXGBE_ETQF_FILTER_EN;
5855                 etqf |= (uint32_t)filter->ether_type;
5856                 etqs |= (uint32_t)((filter->queue <<
5857                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5858                                     IXGBE_ETQS_RX_QUEUE);
5859                 etqs |= IXGBE_ETQS_QUEUE_EN;
5860         } else {
5861                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5862                 if (ret < 0)
5863                         return -ENOSYS;
5864         }
5865         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5866         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5867         IXGBE_WRITE_FLUSH(hw);
5868
5869         return 0;
5870 }
5871
5872 static int
5873 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5874                         struct rte_eth_ethertype_filter *filter)
5875 {
5876         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5877         struct ixgbe_filter_info *filter_info =
5878                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5879         uint32_t etqf, etqs;
5880         int ret;
5881
5882         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5883         if (ret < 0) {
5884                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5885                             filter->ether_type);
5886                 return -ENOENT;
5887         }
5888
5889         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5890         if (etqf & IXGBE_ETQF_FILTER_EN) {
5891                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5892                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5893                 filter->flags = 0;
5894                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5895                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5896                 return 0;
5897         }
5898         return -ENOENT;
5899 }
5900
5901 /*
5902  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5903  * @dev: pointer to rte_eth_dev structure
5904  * @filter_op:operation will be taken.
5905  * @arg: a pointer to specific structure corresponding to the filter_op
5906  */
5907 static int
5908 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5909                                 enum rte_filter_op filter_op,
5910                                 void *arg)
5911 {
5912         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5913         int ret;
5914
5915         MAC_TYPE_FILTER_SUP(hw->mac.type);
5916
5917         if (filter_op == RTE_ETH_FILTER_NOP)
5918                 return 0;
5919
5920         if (arg == NULL) {
5921                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5922                             filter_op);
5923                 return -EINVAL;
5924         }
5925
5926         switch (filter_op) {
5927         case RTE_ETH_FILTER_ADD:
5928                 ret = ixgbe_add_del_ethertype_filter(dev,
5929                         (struct rte_eth_ethertype_filter *)arg,
5930                         TRUE);
5931                 break;
5932         case RTE_ETH_FILTER_DELETE:
5933                 ret = ixgbe_add_del_ethertype_filter(dev,
5934                         (struct rte_eth_ethertype_filter *)arg,
5935                         FALSE);
5936                 break;
5937         case RTE_ETH_FILTER_GET:
5938                 ret = ixgbe_get_ethertype_filter(dev,
5939                         (struct rte_eth_ethertype_filter *)arg);
5940                 break;
5941         default:
5942                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5943                 ret = -EINVAL;
5944                 break;
5945         }
5946         return ret;
5947 }
5948
5949 static int
5950 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5951                      enum rte_filter_type filter_type,
5952                      enum rte_filter_op filter_op,
5953                      void *arg)
5954 {
5955         int ret = -EINVAL;
5956
5957         switch (filter_type) {
5958         case RTE_ETH_FILTER_NTUPLE:
5959                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5960                 break;
5961         case RTE_ETH_FILTER_ETHERTYPE:
5962                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5963                 break;
5964         case RTE_ETH_FILTER_SYN:
5965                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5966                 break;
5967         case RTE_ETH_FILTER_FDIR:
5968                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5969                 break;
5970         case RTE_ETH_FILTER_L2_TUNNEL:
5971                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5972                 break;
5973         default:
5974                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5975                                                         filter_type);
5976                 break;
5977         }
5978
5979         return ret;
5980 }
5981
5982 static u8 *
5983 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5984                         u8 **mc_addr_ptr, u32 *vmdq)
5985 {
5986         u8 *mc_addr;
5987
5988         *vmdq = 0;
5989         mc_addr = *mc_addr_ptr;
5990         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5991         return mc_addr;
5992 }
5993
5994 static int
5995 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5996                           struct ether_addr *mc_addr_set,
5997                           uint32_t nb_mc_addr)
5998 {
5999         struct ixgbe_hw *hw;
6000         u8 *mc_addr_list;
6001
6002         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6003         mc_addr_list = (u8 *)mc_addr_set;
6004         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6005                                          ixgbe_dev_addr_list_itr, TRUE);
6006 }
6007
6008 static uint64_t
6009 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6010 {
6011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6012         uint64_t systime_cycles;
6013
6014         switch (hw->mac.type) {
6015         case ixgbe_mac_X550:
6016         case ixgbe_mac_X550EM_x:
6017         case ixgbe_mac_X550EM_a:
6018                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6019                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6020                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6021                                 * NSEC_PER_SEC;
6022                 break;
6023         default:
6024                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6025                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6026                                 << 32;
6027         }
6028
6029         return systime_cycles;
6030 }
6031
6032 static uint64_t
6033 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6034 {
6035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6036         uint64_t rx_tstamp_cycles;
6037
6038         switch (hw->mac.type) {
6039         case ixgbe_mac_X550:
6040         case ixgbe_mac_X550EM_x:
6041         case ixgbe_mac_X550EM_a:
6042                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6043                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6044                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6045                                 * NSEC_PER_SEC;
6046                 break;
6047         default:
6048                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6049                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6050                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6051                                 << 32;
6052         }
6053
6054         return rx_tstamp_cycles;
6055 }
6056
6057 static uint64_t
6058 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6059 {
6060         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6061         uint64_t tx_tstamp_cycles;
6062
6063         switch (hw->mac.type) {
6064         case ixgbe_mac_X550:
6065         case ixgbe_mac_X550EM_x:
6066         case ixgbe_mac_X550EM_a:
6067                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6068                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6069                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6070                                 * NSEC_PER_SEC;
6071                 break;
6072         default:
6073                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6074                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6075                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6076                                 << 32;
6077         }
6078
6079         return tx_tstamp_cycles;
6080 }
6081
6082 static void
6083 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6084 {
6085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6086         struct ixgbe_adapter *adapter =
6087                 (struct ixgbe_adapter *)dev->data->dev_private;
6088         struct rte_eth_link link;
6089         uint32_t incval = 0;
6090         uint32_t shift = 0;
6091
6092         /* Get current link speed. */
6093         memset(&link, 0, sizeof(link));
6094         ixgbe_dev_link_update(dev, 1);
6095         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6096
6097         switch (link.link_speed) {
6098         case ETH_SPEED_NUM_100M:
6099                 incval = IXGBE_INCVAL_100;
6100                 shift = IXGBE_INCVAL_SHIFT_100;
6101                 break;
6102         case ETH_SPEED_NUM_1G:
6103                 incval = IXGBE_INCVAL_1GB;
6104                 shift = IXGBE_INCVAL_SHIFT_1GB;
6105                 break;
6106         case ETH_SPEED_NUM_10G:
6107         default:
6108                 incval = IXGBE_INCVAL_10GB;
6109                 shift = IXGBE_INCVAL_SHIFT_10GB;
6110                 break;
6111         }
6112
6113         switch (hw->mac.type) {
6114         case ixgbe_mac_X550:
6115         case ixgbe_mac_X550EM_x:
6116         case ixgbe_mac_X550EM_a:
6117                 /* Independent of link speed. */
6118                 incval = 1;
6119                 /* Cycles read will be interpreted as ns. */
6120                 shift = 0;
6121                 /* Fall-through */
6122         case ixgbe_mac_X540:
6123                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6124                 break;
6125         case ixgbe_mac_82599EB:
6126                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6127                 shift -= IXGBE_INCVAL_SHIFT_82599;
6128                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6129                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6130                 break;
6131         default:
6132                 /* Not supported. */
6133                 return;
6134         }
6135
6136         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6137         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6138         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6139
6140         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6141         adapter->systime_tc.cc_shift = shift;
6142         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6143
6144         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6145         adapter->rx_tstamp_tc.cc_shift = shift;
6146         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6147
6148         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6149         adapter->tx_tstamp_tc.cc_shift = shift;
6150         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6151 }
6152
6153 static int
6154 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6155 {
6156         struct ixgbe_adapter *adapter =
6157                         (struct ixgbe_adapter *)dev->data->dev_private;
6158
6159         adapter->systime_tc.nsec += delta;
6160         adapter->rx_tstamp_tc.nsec += delta;
6161         adapter->tx_tstamp_tc.nsec += delta;
6162
6163         return 0;
6164 }
6165
6166 static int
6167 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6168 {
6169         uint64_t ns;
6170         struct ixgbe_adapter *adapter =
6171                         (struct ixgbe_adapter *)dev->data->dev_private;
6172
6173         ns = rte_timespec_to_ns(ts);
6174         /* Set the timecounters to a new value. */
6175         adapter->systime_tc.nsec = ns;
6176         adapter->rx_tstamp_tc.nsec = ns;
6177         adapter->tx_tstamp_tc.nsec = ns;
6178
6179         return 0;
6180 }
6181
6182 static int
6183 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6184 {
6185         uint64_t ns, systime_cycles;
6186         struct ixgbe_adapter *adapter =
6187                         (struct ixgbe_adapter *)dev->data->dev_private;
6188
6189         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6190         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6191         *ts = rte_ns_to_timespec(ns);
6192
6193         return 0;
6194 }
6195
6196 static int
6197 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6198 {
6199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6200         uint32_t tsync_ctl;
6201         uint32_t tsauxc;
6202
6203         /* Stop the timesync system time. */
6204         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6205         /* Reset the timesync system time value. */
6206         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6207         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6208
6209         /* Enable system time for platforms where it isn't on by default. */
6210         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6211         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6212         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6213
6214         ixgbe_start_timecounters(dev);
6215
6216         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6217         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6218                         (ETHER_TYPE_1588 |
6219                          IXGBE_ETQF_FILTER_EN |
6220                          IXGBE_ETQF_1588));
6221
6222         /* Enable timestamping of received PTP packets. */
6223         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6224         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6225         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6226
6227         /* Enable timestamping of transmitted PTP packets. */
6228         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6229         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6230         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6231
6232         IXGBE_WRITE_FLUSH(hw);
6233
6234         return 0;
6235 }
6236
6237 static int
6238 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6239 {
6240         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6241         uint32_t tsync_ctl;
6242
6243         /* Disable timestamping of transmitted PTP packets. */
6244         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6245         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6246         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6247
6248         /* Disable timestamping of received PTP packets. */
6249         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6250         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6251         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6252
6253         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6254         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6255
6256         /* Stop incrementating the System Time registers. */
6257         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6258
6259         return 0;
6260 }
6261
6262 static int
6263 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6264                                  struct timespec *timestamp,
6265                                  uint32_t flags __rte_unused)
6266 {
6267         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6268         struct ixgbe_adapter *adapter =
6269                 (struct ixgbe_adapter *)dev->data->dev_private;
6270         uint32_t tsync_rxctl;
6271         uint64_t rx_tstamp_cycles;
6272         uint64_t ns;
6273
6274         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6275         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6276                 return -EINVAL;
6277
6278         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6279         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6280         *timestamp = rte_ns_to_timespec(ns);
6281
6282         return  0;
6283 }
6284
6285 static int
6286 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6287                                  struct timespec *timestamp)
6288 {
6289         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6290         struct ixgbe_adapter *adapter =
6291                 (struct ixgbe_adapter *)dev->data->dev_private;
6292         uint32_t tsync_txctl;
6293         uint64_t tx_tstamp_cycles;
6294         uint64_t ns;
6295
6296         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6297         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6298                 return -EINVAL;
6299
6300         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6301         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6302         *timestamp = rte_ns_to_timespec(ns);
6303
6304         return 0;
6305 }
6306
6307 static int
6308 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6309 {
6310         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6311         int count = 0;
6312         int g_ind = 0;
6313         const struct reg_info *reg_group;
6314         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6315                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6316
6317         while ((reg_group = reg_set[g_ind++]))
6318                 count += ixgbe_regs_group_count(reg_group);
6319
6320         return count;
6321 }
6322
6323 static int
6324 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6325 {
6326         int count = 0;
6327         int g_ind = 0;
6328         const struct reg_info *reg_group;
6329
6330         while ((reg_group = ixgbevf_regs[g_ind++]))
6331                 count += ixgbe_regs_group_count(reg_group);
6332
6333         return count;
6334 }
6335
6336 static int
6337 ixgbe_get_regs(struct rte_eth_dev *dev,
6338               struct rte_dev_reg_info *regs)
6339 {
6340         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6341         uint32_t *data = regs->data;
6342         int g_ind = 0;
6343         int count = 0;
6344         const struct reg_info *reg_group;
6345         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6346                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6347
6348         if (data == NULL) {
6349                 regs->length = ixgbe_get_reg_length(dev);
6350                 regs->width = sizeof(uint32_t);
6351                 return 0;
6352         }
6353
6354         /* Support only full register dump */
6355         if ((regs->length == 0) ||
6356             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6357                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6358                         hw->device_id;
6359                 while ((reg_group = reg_set[g_ind++]))
6360                         count += ixgbe_read_regs_group(dev, &data[count],
6361                                 reg_group);
6362                 return 0;
6363         }
6364
6365         return -ENOTSUP;
6366 }
6367
6368 static int
6369 ixgbevf_get_regs(struct rte_eth_dev *dev,
6370                 struct rte_dev_reg_info *regs)
6371 {
6372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6373         uint32_t *data = regs->data;
6374         int g_ind = 0;
6375         int count = 0;
6376         const struct reg_info *reg_group;
6377
6378         if (data == NULL) {
6379                 regs->length = ixgbevf_get_reg_length(dev);
6380                 regs->width = sizeof(uint32_t);
6381                 return 0;
6382         }
6383
6384         /* Support only full register dump */
6385         if ((regs->length == 0) ||
6386             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6387                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6388                         hw->device_id;
6389                 while ((reg_group = ixgbevf_regs[g_ind++]))
6390                         count += ixgbe_read_regs_group(dev, &data[count],
6391                                                       reg_group);
6392                 return 0;
6393         }
6394
6395         return -ENOTSUP;
6396 }
6397
6398 static int
6399 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6400 {
6401         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6402
6403         /* Return unit is byte count */
6404         return hw->eeprom.word_size * 2;
6405 }
6406
6407 static int
6408 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6409                 struct rte_dev_eeprom_info *in_eeprom)
6410 {
6411         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6412         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6413         uint16_t *data = in_eeprom->data;
6414         int first, length;
6415
6416         first = in_eeprom->offset >> 1;
6417         length = in_eeprom->length >> 1;
6418         if ((first > hw->eeprom.word_size) ||
6419             ((first + length) > hw->eeprom.word_size))
6420                 return -EINVAL;
6421
6422         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6423
6424         return eeprom->ops.read_buffer(hw, first, length, data);
6425 }
6426
6427 static int
6428 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6429                 struct rte_dev_eeprom_info *in_eeprom)
6430 {
6431         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6432         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6433         uint16_t *data = in_eeprom->data;
6434         int first, length;
6435
6436         first = in_eeprom->offset >> 1;
6437         length = in_eeprom->length >> 1;
6438         if ((first > hw->eeprom.word_size) ||
6439             ((first + length) > hw->eeprom.word_size))
6440                 return -EINVAL;
6441
6442         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6443
6444         return eeprom->ops.write_buffer(hw,  first, length, data);
6445 }
6446
6447 uint16_t
6448 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6449         switch (mac_type) {
6450         case ixgbe_mac_X550:
6451         case ixgbe_mac_X550EM_x:
6452         case ixgbe_mac_X550EM_a:
6453                 return ETH_RSS_RETA_SIZE_512;
6454         case ixgbe_mac_X550_vf:
6455         case ixgbe_mac_X550EM_x_vf:
6456         case ixgbe_mac_X550EM_a_vf:
6457                 return ETH_RSS_RETA_SIZE_64;
6458         default:
6459                 return ETH_RSS_RETA_SIZE_128;
6460         }
6461 }
6462
6463 uint32_t
6464 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6465         switch (mac_type) {
6466         case ixgbe_mac_X550:
6467         case ixgbe_mac_X550EM_x:
6468         case ixgbe_mac_X550EM_a:
6469                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6470                         return IXGBE_RETA(reta_idx >> 2);
6471                 else
6472                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6473         case ixgbe_mac_X550_vf:
6474         case ixgbe_mac_X550EM_x_vf:
6475         case ixgbe_mac_X550EM_a_vf:
6476                 return IXGBE_VFRETA(reta_idx >> 2);
6477         default:
6478                 return IXGBE_RETA(reta_idx >> 2);
6479         }
6480 }
6481
6482 uint32_t
6483 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6484         switch (mac_type) {
6485         case ixgbe_mac_X550_vf:
6486         case ixgbe_mac_X550EM_x_vf:
6487         case ixgbe_mac_X550EM_a_vf:
6488                 return IXGBE_VFMRQC;
6489         default:
6490                 return IXGBE_MRQC;
6491         }
6492 }
6493
6494 uint32_t
6495 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6496         switch (mac_type) {
6497         case ixgbe_mac_X550_vf:
6498         case ixgbe_mac_X550EM_x_vf:
6499         case ixgbe_mac_X550EM_a_vf:
6500                 return IXGBE_VFRSSRK(i);
6501         default:
6502                 return IXGBE_RSSRK(i);
6503         }
6504 }
6505
6506 bool
6507 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6508         switch (mac_type) {
6509         case ixgbe_mac_82599_vf:
6510         case ixgbe_mac_X540_vf:
6511                 return 0;
6512         default:
6513                 return 1;
6514         }
6515 }
6516
6517 static int
6518 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6519                         struct rte_eth_dcb_info *dcb_info)
6520 {
6521         struct ixgbe_dcb_config *dcb_config =
6522                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6523         struct ixgbe_dcb_tc_config *tc;
6524         uint8_t i, j;
6525
6526         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6527                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6528         else
6529                 dcb_info->nb_tcs = 1;
6530
6531         if (dcb_config->vt_mode) { /* vt is enabled*/
6532                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6533                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6534                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6535                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6536                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6537                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6538                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6539                                                 i * dcb_info->nb_tcs + j;
6540                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6541                                 dcb_info->tc_queue.tc_txq[i][j].base =
6542                                                 i * dcb_info->nb_tcs + j;
6543                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6544                         }
6545                 }
6546         } else { /* vt is disabled*/
6547                 struct rte_eth_dcb_rx_conf *rx_conf =
6548                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6549                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6550                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6551                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6552                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6553                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6554                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6555                         }
6556                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6557                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6558                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6559                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6560                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6561                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6562                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6563                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6564                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6565                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6566                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6567                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6568                         }
6569                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6570                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6571                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6572                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6573                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6574                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6575                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6576                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6577                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6578                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6579                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6580                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6581                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6582                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6583                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6584                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6585                 }
6586         }
6587         for (i = 0; i < dcb_info->nb_tcs; i++) {
6588                 tc = &dcb_config->tc_config[i];
6589                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6590         }
6591         return 0;
6592 }
6593
6594 /* Update e-tag ether type */
6595 static int
6596 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6597                             uint16_t ether_type)
6598 {
6599         uint32_t etag_etype;
6600
6601         if (hw->mac.type != ixgbe_mac_X550 &&
6602             hw->mac.type != ixgbe_mac_X550EM_x &&
6603             hw->mac.type != ixgbe_mac_X550EM_a) {
6604                 return -ENOTSUP;
6605         }
6606
6607         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6608         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6609         etag_etype |= ether_type;
6610         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6611         IXGBE_WRITE_FLUSH(hw);
6612
6613         return 0;
6614 }
6615
6616 /* Config l2 tunnel ether type */
6617 static int
6618 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6619                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6620 {
6621         int ret = 0;
6622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6623
6624         if (l2_tunnel == NULL)
6625                 return -EINVAL;
6626
6627         switch (l2_tunnel->l2_tunnel_type) {
6628         case RTE_L2_TUNNEL_TYPE_E_TAG:
6629                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6630                 break;
6631         default:
6632                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6633                 ret = -EINVAL;
6634                 break;
6635         }
6636
6637         return ret;
6638 }
6639
6640 /* Enable e-tag tunnel */
6641 static int
6642 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6643 {
6644         uint32_t etag_etype;
6645
6646         if (hw->mac.type != ixgbe_mac_X550 &&
6647             hw->mac.type != ixgbe_mac_X550EM_x &&
6648             hw->mac.type != ixgbe_mac_X550EM_a) {
6649                 return -ENOTSUP;
6650         }
6651
6652         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6653         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6654         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6655         IXGBE_WRITE_FLUSH(hw);
6656
6657         return 0;
6658 }
6659
6660 /* Enable l2 tunnel */
6661 static int
6662 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6663                            enum rte_eth_tunnel_type l2_tunnel_type)
6664 {
6665         int ret = 0;
6666         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6667
6668         switch (l2_tunnel_type) {
6669         case RTE_L2_TUNNEL_TYPE_E_TAG:
6670                 ret = ixgbe_e_tag_enable(hw);
6671                 break;
6672         default:
6673                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6674                 ret = -EINVAL;
6675                 break;
6676         }
6677
6678         return ret;
6679 }
6680
6681 /* Disable e-tag tunnel */
6682 static int
6683 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6684 {
6685         uint32_t etag_etype;
6686
6687         if (hw->mac.type != ixgbe_mac_X550 &&
6688             hw->mac.type != ixgbe_mac_X550EM_x &&
6689             hw->mac.type != ixgbe_mac_X550EM_a) {
6690                 return -ENOTSUP;
6691         }
6692
6693         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6694         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6695         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6696         IXGBE_WRITE_FLUSH(hw);
6697
6698         return 0;
6699 }
6700
6701 /* Disable l2 tunnel */
6702 static int
6703 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6704                             enum rte_eth_tunnel_type l2_tunnel_type)
6705 {
6706         int ret = 0;
6707         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6708
6709         switch (l2_tunnel_type) {
6710         case RTE_L2_TUNNEL_TYPE_E_TAG:
6711                 ret = ixgbe_e_tag_disable(hw);
6712                 break;
6713         default:
6714                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6715                 ret = -EINVAL;
6716                 break;
6717         }
6718
6719         return ret;
6720 }
6721
6722 static int
6723 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6724                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6725 {
6726         int ret = 0;
6727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6728         uint32_t i, rar_entries;
6729         uint32_t rar_low, rar_high;
6730
6731         if (hw->mac.type != ixgbe_mac_X550 &&
6732             hw->mac.type != ixgbe_mac_X550EM_x &&
6733             hw->mac.type != ixgbe_mac_X550EM_a) {
6734                 return -ENOTSUP;
6735         }
6736
6737         rar_entries = ixgbe_get_num_rx_addrs(hw);
6738
6739         for (i = 1; i < rar_entries; i++) {
6740                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6741                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6742                 if ((rar_high & IXGBE_RAH_AV) &&
6743                     (rar_high & IXGBE_RAH_ADTYPE) &&
6744                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6745                      l2_tunnel->tunnel_id)) {
6746                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6747                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6748
6749                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6750
6751                         return ret;
6752                 }
6753         }
6754
6755         return ret;
6756 }
6757
6758 static int
6759 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6760                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6761 {
6762         int ret = 0;
6763         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6764         uint32_t i, rar_entries;
6765         uint32_t rar_low, rar_high;
6766
6767         if (hw->mac.type != ixgbe_mac_X550 &&
6768             hw->mac.type != ixgbe_mac_X550EM_x &&
6769             hw->mac.type != ixgbe_mac_X550EM_a) {
6770                 return -ENOTSUP;
6771         }
6772
6773         /* One entry for one tunnel. Try to remove potential existing entry. */
6774         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6775
6776         rar_entries = ixgbe_get_num_rx_addrs(hw);
6777
6778         for (i = 1; i < rar_entries; i++) {
6779                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6780                 if (rar_high & IXGBE_RAH_AV) {
6781                         continue;
6782                 } else {
6783                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6784                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6785                         rar_low = l2_tunnel->tunnel_id;
6786
6787                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6788                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6789
6790                         return ret;
6791                 }
6792         }
6793
6794         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6795                      " Please remove a rule before adding a new one.");
6796         return -EINVAL;
6797 }
6798
6799 /* Add l2 tunnel filter */
6800 static int
6801 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6802                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6803 {
6804         int ret = 0;
6805
6806         switch (l2_tunnel->l2_tunnel_type) {
6807         case RTE_L2_TUNNEL_TYPE_E_TAG:
6808                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6809                 break;
6810         default:
6811                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6812                 ret = -EINVAL;
6813                 break;
6814         }
6815
6816         return ret;
6817 }
6818
6819 /* Delete l2 tunnel filter */
6820 static int
6821 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6822                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6823 {
6824         int ret = 0;
6825
6826         switch (l2_tunnel->l2_tunnel_type) {
6827         case RTE_L2_TUNNEL_TYPE_E_TAG:
6828                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6829                 break;
6830         default:
6831                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6832                 ret = -EINVAL;
6833                 break;
6834         }
6835
6836         return ret;
6837 }
6838
6839 /**
6840  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6841  * @dev: pointer to rte_eth_dev structure
6842  * @filter_op:operation will be taken.
6843  * @arg: a pointer to specific structure corresponding to the filter_op
6844  */
6845 static int
6846 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6847                                   enum rte_filter_op filter_op,
6848                                   void *arg)
6849 {
6850         int ret = 0;
6851
6852         if (filter_op == RTE_ETH_FILTER_NOP)
6853                 return 0;
6854
6855         if (arg == NULL) {
6856                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6857                             filter_op);
6858                 return -EINVAL;
6859         }
6860
6861         switch (filter_op) {
6862         case RTE_ETH_FILTER_ADD:
6863                 ret = ixgbe_dev_l2_tunnel_filter_add
6864                         (dev,
6865                          (struct rte_eth_l2_tunnel_conf *)arg);
6866                 break;
6867         case RTE_ETH_FILTER_DELETE:
6868                 ret = ixgbe_dev_l2_tunnel_filter_del
6869                         (dev,
6870                          (struct rte_eth_l2_tunnel_conf *)arg);
6871                 break;
6872         default:
6873                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6874                 ret = -EINVAL;
6875                 break;
6876         }
6877         return ret;
6878 }
6879
6880 static int
6881 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6882 {
6883         int ret = 0;
6884         uint32_t ctrl;
6885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6886
6887         if (hw->mac.type != ixgbe_mac_X550 &&
6888             hw->mac.type != ixgbe_mac_X550EM_x &&
6889             hw->mac.type != ixgbe_mac_X550EM_a) {
6890                 return -ENOTSUP;
6891         }
6892
6893         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6894         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6895         if (en)
6896                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6897         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6898
6899         return ret;
6900 }
6901
6902 /* Enable l2 tunnel forwarding */
6903 static int
6904 ixgbe_dev_l2_tunnel_forwarding_enable
6905         (struct rte_eth_dev *dev,
6906          enum rte_eth_tunnel_type l2_tunnel_type)
6907 {
6908         int ret = 0;
6909
6910         switch (l2_tunnel_type) {
6911         case RTE_L2_TUNNEL_TYPE_E_TAG:
6912                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6913                 break;
6914         default:
6915                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6916                 ret = -EINVAL;
6917                 break;
6918         }
6919
6920         return ret;
6921 }
6922
6923 /* Disable l2 tunnel forwarding */
6924 static int
6925 ixgbe_dev_l2_tunnel_forwarding_disable
6926         (struct rte_eth_dev *dev,
6927          enum rte_eth_tunnel_type l2_tunnel_type)
6928 {
6929         int ret = 0;
6930
6931         switch (l2_tunnel_type) {
6932         case RTE_L2_TUNNEL_TYPE_E_TAG:
6933                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6934                 break;
6935         default:
6936                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6937                 ret = -EINVAL;
6938                 break;
6939         }
6940
6941         return ret;
6942 }
6943
6944 static int
6945 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6946                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6947                              bool en)
6948 {
6949         int ret = 0;
6950         uint32_t vmtir, vmvir;
6951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6952
6953         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6954                 PMD_DRV_LOG(ERR,
6955                             "VF id %u should be less than %u",
6956                             l2_tunnel->vf_id,
6957                             dev->pci_dev->max_vfs);
6958                 return -EINVAL;
6959         }
6960
6961         if (hw->mac.type != ixgbe_mac_X550 &&
6962             hw->mac.type != ixgbe_mac_X550EM_x &&
6963             hw->mac.type != ixgbe_mac_X550EM_a) {
6964                 return -ENOTSUP;
6965         }
6966
6967         if (en)
6968                 vmtir = l2_tunnel->tunnel_id;
6969         else
6970                 vmtir = 0;
6971
6972         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6973
6974         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6975         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6976         if (en)
6977                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6978         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6979
6980         return ret;
6981 }
6982
6983 /* Enable l2 tunnel tag insertion */
6984 static int
6985 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6986                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6987 {
6988         int ret = 0;
6989
6990         switch (l2_tunnel->l2_tunnel_type) {
6991         case RTE_L2_TUNNEL_TYPE_E_TAG:
6992                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6993                 break;
6994         default:
6995                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6996                 ret = -EINVAL;
6997                 break;
6998         }
6999
7000         return ret;
7001 }
7002
7003 /* Disable l2 tunnel tag insertion */
7004 static int
7005 ixgbe_dev_l2_tunnel_insertion_disable
7006         (struct rte_eth_dev *dev,
7007          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7008 {
7009         int ret = 0;
7010
7011         switch (l2_tunnel->l2_tunnel_type) {
7012         case RTE_L2_TUNNEL_TYPE_E_TAG:
7013                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7014                 break;
7015         default:
7016                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7017                 ret = -EINVAL;
7018                 break;
7019         }
7020
7021         return ret;
7022 }
7023
7024 static int
7025 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7026                              bool en)
7027 {
7028         int ret = 0;
7029         uint32_t qde;
7030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7031
7032         if (hw->mac.type != ixgbe_mac_X550 &&
7033             hw->mac.type != ixgbe_mac_X550EM_x &&
7034             hw->mac.type != ixgbe_mac_X550EM_a) {
7035                 return -ENOTSUP;
7036         }
7037
7038         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7039         if (en)
7040                 qde |= IXGBE_QDE_STRIP_TAG;
7041         else
7042                 qde &= ~IXGBE_QDE_STRIP_TAG;
7043         qde &= ~IXGBE_QDE_READ;
7044         qde |= IXGBE_QDE_WRITE;
7045         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7046
7047         return ret;
7048 }
7049
7050 /* Enable l2 tunnel tag stripping */
7051 static int
7052 ixgbe_dev_l2_tunnel_stripping_enable
7053         (struct rte_eth_dev *dev,
7054          enum rte_eth_tunnel_type l2_tunnel_type)
7055 {
7056         int ret = 0;
7057
7058         switch (l2_tunnel_type) {
7059         case RTE_L2_TUNNEL_TYPE_E_TAG:
7060                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7061                 break;
7062         default:
7063                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7064                 ret = -EINVAL;
7065                 break;
7066         }
7067
7068         return ret;
7069 }
7070
7071 /* Disable l2 tunnel tag stripping */
7072 static int
7073 ixgbe_dev_l2_tunnel_stripping_disable
7074         (struct rte_eth_dev *dev,
7075          enum rte_eth_tunnel_type l2_tunnel_type)
7076 {
7077         int ret = 0;
7078
7079         switch (l2_tunnel_type) {
7080         case RTE_L2_TUNNEL_TYPE_E_TAG:
7081                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7082                 break;
7083         default:
7084                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7085                 ret = -EINVAL;
7086                 break;
7087         }
7088
7089         return ret;
7090 }
7091
7092 /* Enable/disable l2 tunnel offload functions */
7093 static int
7094 ixgbe_dev_l2_tunnel_offload_set
7095         (struct rte_eth_dev *dev,
7096          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7097          uint32_t mask,
7098          uint8_t en)
7099 {
7100         int ret = 0;
7101
7102         if (l2_tunnel == NULL)
7103                 return -EINVAL;
7104
7105         ret = -EINVAL;
7106         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7107                 if (en)
7108                         ret = ixgbe_dev_l2_tunnel_enable(
7109                                 dev,
7110                                 l2_tunnel->l2_tunnel_type);
7111                 else
7112                         ret = ixgbe_dev_l2_tunnel_disable(
7113                                 dev,
7114                                 l2_tunnel->l2_tunnel_type);
7115         }
7116
7117         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7118                 if (en)
7119                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7120                                 dev,
7121                                 l2_tunnel);
7122                 else
7123                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7124                                 dev,
7125                                 l2_tunnel);
7126         }
7127
7128         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7129                 if (en)
7130                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7131                                 dev,
7132                                 l2_tunnel->l2_tunnel_type);
7133                 else
7134                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7135                                 dev,
7136                                 l2_tunnel->l2_tunnel_type);
7137         }
7138
7139         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7140                 if (en)
7141                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7142                                 dev,
7143                                 l2_tunnel->l2_tunnel_type);
7144                 else
7145                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7146                                 dev,
7147                                 l2_tunnel->l2_tunnel_type);
7148         }
7149
7150         return ret;
7151 }
7152
7153 static int
7154 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7155                         uint16_t port)
7156 {
7157         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7158         IXGBE_WRITE_FLUSH(hw);
7159
7160         return 0;
7161 }
7162
7163 /* There's only one register for VxLAN UDP port.
7164  * So, we cannot add several ports. Will update it.
7165  */
7166 static int
7167 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7168                      uint16_t port)
7169 {
7170         if (port == 0) {
7171                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7172                 return -EINVAL;
7173         }
7174
7175         return ixgbe_update_vxlan_port(hw, port);
7176 }
7177
7178 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7179  * UDP port, it must have a value.
7180  * So, will reset it to the original value 0.
7181  */
7182 static int
7183 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7184                      uint16_t port)
7185 {
7186         uint16_t cur_port;
7187
7188         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7189
7190         if (cur_port != port) {
7191                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7192                 return -EINVAL;
7193         }
7194
7195         return ixgbe_update_vxlan_port(hw, 0);
7196 }
7197
7198 /* Add UDP tunneling port */
7199 static int
7200 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7201                               struct rte_eth_udp_tunnel *udp_tunnel)
7202 {
7203         int ret = 0;
7204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7205
7206         if (hw->mac.type != ixgbe_mac_X550 &&
7207             hw->mac.type != ixgbe_mac_X550EM_x &&
7208             hw->mac.type != ixgbe_mac_X550EM_a) {
7209                 return -ENOTSUP;
7210         }
7211
7212         if (udp_tunnel == NULL)
7213                 return -EINVAL;
7214
7215         switch (udp_tunnel->prot_type) {
7216         case RTE_TUNNEL_TYPE_VXLAN:
7217                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7218                 break;
7219
7220         case RTE_TUNNEL_TYPE_GENEVE:
7221         case RTE_TUNNEL_TYPE_TEREDO:
7222                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7223                 ret = -EINVAL;
7224                 break;
7225
7226         default:
7227                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7228                 ret = -EINVAL;
7229                 break;
7230         }
7231
7232         return ret;
7233 }
7234
7235 /* Remove UDP tunneling port */
7236 static int
7237 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7238                               struct rte_eth_udp_tunnel *udp_tunnel)
7239 {
7240         int ret = 0;
7241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7242
7243         if (hw->mac.type != ixgbe_mac_X550 &&
7244             hw->mac.type != ixgbe_mac_X550EM_x &&
7245             hw->mac.type != ixgbe_mac_X550EM_a) {
7246                 return -ENOTSUP;
7247         }
7248
7249         if (udp_tunnel == NULL)
7250                 return -EINVAL;
7251
7252         switch (udp_tunnel->prot_type) {
7253         case RTE_TUNNEL_TYPE_VXLAN:
7254                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7255                 break;
7256         case RTE_TUNNEL_TYPE_GENEVE:
7257         case RTE_TUNNEL_TYPE_TEREDO:
7258                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7259                 ret = -EINVAL;
7260                 break;
7261         default:
7262                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7263                 ret = -EINVAL;
7264                 break;
7265         }
7266
7267         return ret;
7268 }
7269
7270 /* ixgbevf_update_xcast_mode - Update Multicast mode
7271  * @hw: pointer to the HW structure
7272  * @netdev: pointer to net device structure
7273  * @xcast_mode: new multicast mode
7274  *
7275  * Updates the Multicast Mode of VF.
7276  */
7277 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7278                                      int xcast_mode)
7279 {
7280         struct ixgbe_mbx_info *mbx = &hw->mbx;
7281         u32 msgbuf[2];
7282         s32 err;
7283
7284         switch (hw->api_version) {
7285         case ixgbe_mbox_api_12:
7286                 break;
7287         default:
7288                 return -EOPNOTSUPP;
7289         }
7290
7291         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7292         msgbuf[1] = xcast_mode;
7293
7294         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7295         if (err)
7296                 return err;
7297
7298         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7299         if (err)
7300                 return err;
7301
7302         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7303         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7304                 return -EPERM;
7305
7306         return 0;
7307 }
7308
7309 static void
7310 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7311 {
7312         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7313
7314         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7315 }
7316
7317 static void
7318 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7319 {
7320         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7321
7322         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7323 }
7324
7325 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7326 {
7327         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7328         u32 in_msg = 0;
7329
7330         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7331                 return;
7332
7333         /* PF reset VF event */
7334         if (in_msg == IXGBE_PF_CONTROL_MSG)
7335                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
7336 }
7337
7338 static int
7339 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7340 {
7341         uint32_t eicr;
7342         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7343         struct ixgbe_interrupt *intr =
7344                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7345         ixgbevf_intr_disable(hw);
7346
7347         /* read-on-clear nic registers here */
7348         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7349         intr->flags = 0;
7350
7351         /* only one misc vector supported - mailbox */
7352         eicr &= IXGBE_VTEICR_MASK;
7353         if (eicr == IXGBE_MISC_VEC_ID)
7354                 intr->flags |= IXGBE_FLAG_MAILBOX;
7355
7356         return 0;
7357 }
7358
7359 static int
7360 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7361 {
7362         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7363         struct ixgbe_interrupt *intr =
7364                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7365
7366         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7367                 ixgbevf_mbx_process(dev);
7368                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7369         }
7370
7371         ixgbevf_intr_enable(hw);
7372
7373         return 0;
7374 }
7375
7376 static void
7377 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7378                               void *param)
7379 {
7380         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7381
7382         ixgbevf_dev_interrupt_get_status(dev);
7383         ixgbevf_dev_interrupt_action(dev);
7384 }
7385
7386 DRIVER_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7387 DRIVER_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7388 DRIVER_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7389 DRIVER_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);