drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 155 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 156 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 157 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 158 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 159 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 160 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 161 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 163 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 167                                 int wait_to_complete);
 168 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 169                                 struct rte_eth_stats *stats);
 170 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 171                                 struct rte_eth_xstats *xstats, unsigned n);
 172 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 173                                   struct rte_eth_xstats *xstats, unsigned n);
 174 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 181                                struct rte_eth_dev_info *dev_info);
 182 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 183                                  struct rte_eth_dev_info *dev_info);
 184 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 185
 186 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 187                 uint16_t vlan_id, int on);
 188 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 189                                enum rte_vlan_type vlan_type,
 190                                uint16_t tpid_id);
 191 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 192                 uint16_t queue, bool on);
 193 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 194                 int on);
 195 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 220 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 221                 void *param);
 222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 223 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 224                 uint32_t index, uint32_t pool);
 225 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 226 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 227                                            struct ether_addr *mac_addr);
 228 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 229
 230 /* For Virtual Function support */
 231 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 232 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 233 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 234 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 235 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 236 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 237 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 238 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 239 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 240                 struct rte_eth_stats *stats);
 241 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 242 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 243                 uint16_t vlan_id, int on);
 244 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 245                 uint16_t queue, int on);
 246 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 247 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 248 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                             uint16_t queue_id);
 250 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                              uint16_t queue_id);
 252 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 253                                  uint8_t queue, uint8_t msix_vector);
 254 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 255
 256 /* For Eth VMDQ APIs support */
 257 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 258                 ether_addr* mac_addr,uint8_t on);
 259 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 260 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 261                 uint16_t rx_mask, uint8_t on);
 262 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 263 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 264 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 265                 uint64_t pool_mask,uint8_t vlan_on);
 266 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 267                 struct rte_eth_mirror_conf *mirror_conf,
 268                 uint8_t rule_id, uint8_t on);
 269 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 270                 uint8_t rule_id);
 271 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                           uint16_t queue_id);
 273 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                            uint16_t queue_id);
 275 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 276                                uint8_t queue, uint8_t msix_vector);
 277 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 278
 279 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 280                 uint16_t queue_idx, uint16_t tx_rate);
 281 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 282                 uint16_t tx_rate, uint64_t q_msk);
 283
 284 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                  struct ether_addr *mac_addr,
 286                                  uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter,
 292                         bool add);
 293 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 294                         struct rte_eth_syn_filter *filter);
 295 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 296                         enum rte_filter_op filter_op,
 297                         void *arg);
 298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 301                         struct ixgbe_5tuple_filter *filter);
 302 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter,
 304                         bool add);
 305 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 306                                 enum rte_filter_op filter_op,
 307                                 void *arg);
 308 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 309                         struct rte_eth_ntuple_filter *filter);
 310 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ethertype_filter *filter,
 312                         bool add);
 313 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 314                                 enum rte_filter_op filter_op,
 315                                 void *arg);
 316 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 317                         struct rte_eth_ethertype_filter *filter);
 318 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 319                      enum rte_filter_type filter_type,
 320                      enum rte_filter_op filter_op,
 321                      void *arg);
 322 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 323
 324 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 325                                       struct ether_addr *mc_addr_set,
 326                                       uint32_t nb_mc_addr);
 327 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                    struct rte_eth_dcb_info *dcb_info);
 329
 330 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 331 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 332                             struct rte_dev_reg_info *regs);
 333 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 334 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 335                                 struct rte_dev_eeprom_info *eeprom);
 336 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338
 339 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 340 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 341                                 struct rte_dev_reg_info *regs);
 342
 343 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 344 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 345 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                             struct timespec *timestamp,
 347                                             uint32_t flags);
 348 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                             struct timespec *timestamp);
 350 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 351 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 352                                    struct timespec *timestamp);
 353 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 354                                    const struct timespec *timestamp);
 355
 356 static int ixgbe_dev_l2_tunnel_eth_type_conf
 357         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 358 static int ixgbe_dev_l2_tunnel_offload_set
 359         (struct rte_eth_dev *dev,
 360          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 361          uint32_t mask,
 362          uint8_t en);
 363 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 364                                              enum rte_filter_op filter_op,
 365                                              void *arg);
 366
 367 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 368                                          struct rte_eth_udp_tunnel *udp_tunnel);
 369 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 370                                          struct rte_eth_udp_tunnel *udp_tunnel);
 371
 372 /*
 373  * Define VF Stats MACRO for Non "cleared on read" register
 374  */
 375 #define UPDATE_VF_STAT(reg, last, cur)                          \
 376 {                                                               \
 377         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 378         cur += (latest - last) & UINT_MAX;                      \
 379         last = latest;                                          \
 380 }
 381
 382 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 383 {                                                                \
 384         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 385         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 386         u64 latest = ((new_msb << 32) | new_lsb);                \
 387         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 388         last = latest;                                           \
 389 }
 390
 391 #define IXGBE_SET_HWSTRIP(h, q) do{\
 392                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] |= 1 << bit;\
 395         } while (0)
 396
 397 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 398                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 400                 (h)->bitmap[idx] &= ~(1 << bit);\
 401         } while (0)
 402
 403 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 404                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 405                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 406                 (r) = (h)->bitmap[idx] >> bit & 1;\
 407         } while (0)
 408
 409 /*
 410  * The set of PCI devices this driver supports
 411  */
 412 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 413
 414 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 415 #include "rte_pci_dev_ids.h"
 416
 417 { .vendor_id = 0, /* sentinel */ },
 418 };
 419
 420
 421 /*
 422  * The set of PCI devices this driver supports (for 82599 VF)
 423  */
 424 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 425
 426 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 427 #include "rte_pci_dev_ids.h"
 428 { .vendor_id = 0, /* sentinel */ },
 429
 430 };
 431
 432 static const struct rte_eth_desc_lim rx_desc_lim = {
 433         .nb_max = IXGBE_MAX_RING_DESC,
 434         .nb_min = IXGBE_MIN_RING_DESC,
 435         .nb_align = IXGBE_RXD_ALIGN,
 436 };
 437
 438 static const struct rte_eth_desc_lim tx_desc_lim = {
 439         .nb_max = IXGBE_MAX_RING_DESC,
 440         .nb_min = IXGBE_MIN_RING_DESC,
 441         .nb_align = IXGBE_TXD_ALIGN,
 442 };
 443
 444 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 445         .dev_configure        = ixgbe_dev_configure,
 446         .dev_start            = ixgbe_dev_start,
 447         .dev_stop             = ixgbe_dev_stop,
 448         .dev_set_link_up    = ixgbe_dev_set_link_up,
 449         .dev_set_link_down  = ixgbe_dev_set_link_down,
 450         .dev_close            = ixgbe_dev_close,
 451         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 452         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 453         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 454         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 455         .link_update          = ixgbe_dev_link_update,
 456         .stats_get            = ixgbe_dev_stats_get,
 457         .xstats_get           = ixgbe_dev_xstats_get,
 458         .stats_reset          = ixgbe_dev_stats_reset,
 459         .xstats_reset         = ixgbe_dev_xstats_reset,
 460         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 461         .dev_infos_get        = ixgbe_dev_info_get,
 462         .mtu_set              = ixgbe_dev_mtu_set,
 463         .vlan_filter_set      = ixgbe_vlan_filter_set,
 464         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 465         .vlan_offload_set     = ixgbe_vlan_offload_set,
 466         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 467         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 468         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 469         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 470         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 471         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 472         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 473         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 474         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 475         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 476         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 477         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 478         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 479         .dev_led_on           = ixgbe_dev_led_on,
 480         .dev_led_off          = ixgbe_dev_led_off,
 481         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 482         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 483         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 484         .mac_addr_add         = ixgbe_add_rar,
 485         .mac_addr_remove      = ixgbe_remove_rar,
 486         .mac_addr_set         = ixgbe_set_default_mac_addr,
 487         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 488         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 489         .mirror_rule_set      = ixgbe_mirror_rule_set,
 490         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 491         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 492         .set_vf_rx            = ixgbe_set_pool_rx,
 493         .set_vf_tx            = ixgbe_set_pool_tx,
 494         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 495         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 496         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 497         .reta_update          = ixgbe_dev_rss_reta_update,
 498         .reta_query           = ixgbe_dev_rss_reta_query,
 499 #ifdef RTE_NIC_BYPASS
 500         .bypass_init          = ixgbe_bypass_init,
 501         .bypass_state_set     = ixgbe_bypass_state_store,
 502         .bypass_state_show    = ixgbe_bypass_state_show,
 503         .bypass_event_set     = ixgbe_bypass_event_store,
 504         .bypass_event_show    = ixgbe_bypass_event_show,
 505         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 506         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 507         .bypass_ver_show      = ixgbe_bypass_ver_show,
 508         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 509 #endif /* RTE_NIC_BYPASS */
 510         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 511         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 512         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 513         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 514         .rxq_info_get         = ixgbe_rxq_info_get,
 515         .txq_info_get         = ixgbe_txq_info_get,
 516         .timesync_enable      = ixgbe_timesync_enable,
 517         .timesync_disable     = ixgbe_timesync_disable,
 518         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 519         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 520         .get_reg_length       = ixgbe_get_reg_length,
 521         .get_reg              = ixgbe_get_regs,
 522         .get_eeprom_length    = ixgbe_get_eeprom_length,
 523         .get_eeprom           = ixgbe_get_eeprom,
 524         .set_eeprom           = ixgbe_set_eeprom,
 525         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 526         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 527         .timesync_read_time   = ixgbe_timesync_read_time,
 528         .timesync_write_time  = ixgbe_timesync_write_time,
 529         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 530         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 531         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 532         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 533 };
 534
 535 /*
 536  * dev_ops for virtual function, bare necessities for basic vf
 537  * operation have been implemented
 538  */
 539 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 540         .dev_configure        = ixgbevf_dev_configure,
 541         .dev_start            = ixgbevf_dev_start,
 542         .dev_stop             = ixgbevf_dev_stop,
 543         .link_update          = ixgbe_dev_link_update,
 544         .stats_get            = ixgbevf_dev_stats_get,
 545         .xstats_get           = ixgbevf_dev_xstats_get,
 546         .stats_reset          = ixgbevf_dev_stats_reset,
 547         .xstats_reset         = ixgbevf_dev_stats_reset,
 548         .dev_close            = ixgbevf_dev_close,
 549         .dev_infos_get        = ixgbevf_dev_info_get,
 550         .mtu_set              = ixgbevf_dev_set_mtu,
 551         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 552         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 553         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 554         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 555         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 556         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 557         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 558         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 559         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 560         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 561         .mac_addr_add         = ixgbevf_add_mac_addr,
 562         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 563         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 564         .rxq_info_get         = ixgbe_rxq_info_get,
 565         .txq_info_get         = ixgbe_txq_info_get,
 566         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 567         .get_reg_length       = ixgbevf_get_reg_length,
 568         .get_reg              = ixgbevf_get_regs,
 569         .reta_update          = ixgbe_dev_rss_reta_update,
 570         .reta_query           = ixgbe_dev_rss_reta_query,
 571         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 572         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 573 };
 574
 575 /* store statistics names and its offset in stats structure */
 576 struct rte_ixgbe_xstats_name_off {
 577         char name[RTE_ETH_XSTATS_NAME_SIZE];
 578         unsigned offset;
 579 };
 580
 581 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 582         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 583         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 584         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 585         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 586         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 587         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 588         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 589         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 590         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 591         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 592         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 593         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 594         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 596         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 597                 prc1023)},
 598         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 599                 prc1522)},
 600         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 601         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 602         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 603         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 604         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 605         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 606         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 607         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 608         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 609         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 610         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 611         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 612         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 614         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 615         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 616         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 617                 ptc1023)},
 618         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 619                 ptc1522)},
 620         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 621         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 622         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 623         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 624
 625         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 626                 fdirustat_add)},
 627         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 628                 fdirustat_remove)},
 629         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 630                 fdirfstat_fadd)},
 631         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 632                 fdirfstat_fremove)},
 633         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 634                 fdirmatch)},
 635         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 636                 fdirmiss)},
 637
 638         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 639         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 640         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 641                 fclast)},
 642         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 643         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 644         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 645         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 646         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 647                 fcoe_noddp)},
 648         {"rx_fcoe_no_direct_data_placement_ext_buff",
 649                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 650
 651         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 652                 lxontxc)},
 653         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 654                 lxonrxc)},
 655         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 656                 lxofftxc)},
 657         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 658                 lxoffrxc)},
 659         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 660 };
 661
 662 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 663                            sizeof(rte_ixgbe_stats_strings[0]))
 664
 665 /* Per-queue statistics */
 666 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 667         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 668         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 669         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 670         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 671 };
 672
 673 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 674                            sizeof(rte_ixgbe_rxq_strings[0]))
 675
 676 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 677         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 678         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 679         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 680                 pxon2offc)},
 681 };
 682
 683 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 684                            sizeof(rte_ixgbe_txq_strings[0]))
 685
 686 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 687         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 688 };
 689
 690 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 691                 sizeof(rte_ixgbevf_stats_strings[0]))
 692
 693 /**
 694  * Atomically reads the link status information from global
 695  * structure rte_eth_dev.
 696  *
 697  * @param dev
 698  *   - Pointer to the structure rte_eth_dev to read from.
 699  *   - Pointer to the buffer to be saved with the link status.
 700  *
 701  * @return
 702  *   - On success, zero.
 703  *   - On failure, negative value.
 704  */
 705 static inline int
 706 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 707                                 struct rte_eth_link *link)
 708 {
 709         struct rte_eth_link *dst = link;
 710         struct rte_eth_link *src = &(dev->data->dev_link);
 711
 712         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 713                                         *(uint64_t *)src) == 0)
 714                 return -1;
 715
 716         return 0;
 717 }
 718
 719 /**
 720  * Atomically writes the link status information into global
 721  * structure rte_eth_dev.
 722  *
 723  * @param dev
 724  *   - Pointer to the structure rte_eth_dev to read from.
 725  *   - Pointer to the buffer to be saved with the link status.
 726  *
 727  * @return
 728  *   - On success, zero.
 729  *   - On failure, negative value.
 730  */
 731 static inline int
 732 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 733                                 struct rte_eth_link *link)
 734 {
 735         struct rte_eth_link *dst = &(dev->data->dev_link);
 736         struct rte_eth_link *src = link;
 737
 738         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 739                                         *(uint64_t *)src) == 0)
 740                 return -1;
 741
 742         return 0;
 743 }
 744
 745 /*
 746  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 747  */
 748 static inline int
 749 ixgbe_is_sfp(struct ixgbe_hw *hw)
 750 {
 751         switch (hw->phy.type) {
 752         case ixgbe_phy_sfp_avago:
 753         case ixgbe_phy_sfp_ftl:
 754         case ixgbe_phy_sfp_intel:
 755         case ixgbe_phy_sfp_unknown:
 756         case ixgbe_phy_sfp_passive_tyco:
 757         case ixgbe_phy_sfp_passive_unknown:
 758                 return 1;
 759         default:
 760                 return 0;
 761         }
 762 }
 763
 764 static inline int32_t
 765 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 766 {
 767         uint32_t ctrl_ext;
 768         int32_t status;
 769
 770         status = ixgbe_reset_hw(hw);
 771
 772         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 773         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 774         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 775         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 776         IXGBE_WRITE_FLUSH(hw);
 777
 778         return status;
 779 }
 780
 781 static inline void
 782 ixgbe_enable_intr(struct rte_eth_dev *dev)
 783 {
 784         struct ixgbe_interrupt *intr =
 785                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 786         struct ixgbe_hw *hw =
 787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 788
 789         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 790         IXGBE_WRITE_FLUSH(hw);
 791 }
 792
 793 /*
 794  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 795  */
 796 static void
 797 ixgbe_disable_intr(struct ixgbe_hw *hw)
 798 {
 799         PMD_INIT_FUNC_TRACE();
 800
 801         if (hw->mac.type == ixgbe_mac_82598EB) {
 802                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 803         } else {
 804                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 805                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 806                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 807         }
 808         IXGBE_WRITE_FLUSH(hw);
 809 }
 810
 811 /*
 812  * This function resets queue statistics mapping registers.
 813  * From Niantic datasheet, Initialization of Statistics section:
 814  * "...if software requires the queue counters, the RQSMR and TQSM registers
 815  * must be re-programmed following a device reset.
 816  */
 817 static void
 818 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 819 {
 820         uint32_t i;
 821
 822         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 823                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 824                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 825         }
 826 }
 827
 828
 829 static int
 830 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 831                                   uint16_t queue_id,
 832                                   uint8_t stat_idx,
 833                                   uint8_t is_rx)
 834 {
 835 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 836 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 837 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 838
 839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 840         struct ixgbe_stat_mapping_registers *stat_mappings =
 841                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 842         uint32_t qsmr_mask = 0;
 843         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 844         uint32_t q_map;
 845         uint8_t n, offset;
 846
 847         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 848                 (hw->mac.type != ixgbe_mac_X540) &&
 849                 (hw->mac.type != ixgbe_mac_X550) &&
 850                 (hw->mac.type != ixgbe_mac_X550EM_x))
 851                 return -ENOSYS;
 852
 853         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 854                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 855                      queue_id, stat_idx);
 856
 857         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 858         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 859                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 860                 return -EIO;
 861         }
 862         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 863
 864         /* Now clear any previous stat_idx set */
 865         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 866         if (!is_rx)
 867                 stat_mappings->tqsm[n] &= ~clearing_mask;
 868         else
 869                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 870
 871         q_map = (uint32_t)stat_idx;
 872         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 873         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 874         if (!is_rx)
 875                 stat_mappings->tqsm[n] |= qsmr_mask;
 876         else
 877                 stat_mappings->rqsmr[n] |= qsmr_mask;
 878
 879         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 880                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 881                      queue_id, stat_idx);
 882         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 883                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 884
 885         /* Now write the mapping in the appropriate register */
 886         if (is_rx) {
 887                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 888                              stat_mappings->rqsmr[n], n);
 889                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 890         }
 891         else {
 892                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 893                              stat_mappings->tqsm[n], n);
 894                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 895         }
 896         return 0;
 897 }
 898
 899 static void
 900 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 901 {
 902         struct ixgbe_stat_mapping_registers *stat_mappings =
 903                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 905         int i;
 906
 907         /* write whatever was in stat mapping table to the NIC */
 908         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 909                 /* rx */
 910                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 911
 912                 /* tx */
 913                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 914         }
 915 }
 916
 917 static void
 918 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 919 {
 920         uint8_t i;
 921         struct ixgbe_dcb_tc_config *tc;
 922         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 923
 924         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 925         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 926         for (i = 0; i < dcb_max_tc; i++) {
 927                 tc = &dcb_config->tc_config[i];
 928                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 929                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 930                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 931                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 932                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 933                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 934                 tc->pfc = ixgbe_dcb_pfc_disabled;
 935         }
 936
 937         /* Initialize default user to priority mapping, UPx->TC0 */
 938         tc = &dcb_config->tc_config[0];
 939         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 940         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 941         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 942                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 943                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 944         }
 945         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 946         dcb_config->pfc_mode_enable = false;
 947         dcb_config->vt_mode = true;
 948         dcb_config->round_robin_enable = false;
 949         /* support all DCB capabilities in 82599 */
 950         dcb_config->support.capabilities = 0xFF;
 951
 952         /*we only support 4 Tcs for X540, X550 */
 953         if (hw->mac.type == ixgbe_mac_X540 ||
 954                 hw->mac.type == ixgbe_mac_X550 ||
 955                 hw->mac.type == ixgbe_mac_X550EM_x) {
 956                 dcb_config->num_tcs.pg_tcs = 4;
 957                 dcb_config->num_tcs.pfc_tcs = 4;
 958         }
 959 }
 960
 961 /*
 962  * Ensure that all locks are released before first NVM or PHY access
 963  */
 964 static void
 965 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 966 {
 967         uint16_t mask;
 968
 969         /*
 970          * Phy lock should not fail in this early stage. If this is the case,
 971          * it is due to an improper exit of the application.
 972          * So force the release of the faulty lock. Release of common lock
 973          * is done automatically by swfw_sync function.
 974          */
 975         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 976         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 977                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 978         }
 979         ixgbe_release_swfw_semaphore(hw, mask);
 980
 981         /*
 982          * These ones are more tricky since they are common to all ports; but
 983          * swfw_sync retries last long enough (1s) to be almost sure that if
 984          * lock can not be taken it is due to an improper lock of the
 985          * semaphore.
 986          */
 987         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 988         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 989                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 990         }
 991         ixgbe_release_swfw_semaphore(hw, mask);
 992 }
 993
 994 /*
 995  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 996  * It returns 0 on success.
 997  */
 998 static int
 999 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1000 {
1001         struct rte_pci_device *pci_dev;
1002         struct ixgbe_hw *hw =
1003                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1004         struct ixgbe_vfta * shadow_vfta =
1005                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1006         struct ixgbe_hwstrip *hwstrip =
1007                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1008         struct ixgbe_dcb_config *dcb_config =
1009                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1010         struct ixgbe_filter_info *filter_info =
1011                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1012         uint32_t ctrl_ext;
1013         uint16_t csum;
1014         int diag, i;
1015
1016         PMD_INIT_FUNC_TRACE();
1017
1018         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1019         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1020         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1021
1022         /*
1023          * For secondary processes, we don't initialise any further as primary
1024          * has already done this work. Only check we don't need a different
1025          * RX and TX function.
1026          */
1027         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1028                 struct ixgbe_tx_queue *txq;
1029                 /* TX queue function in primary, set by last queue initialized
1030                  * Tx queue may not initialized by primary process */
1031                 if (eth_dev->data->tx_queues) {
1032                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1033                         ixgbe_set_tx_function(eth_dev, txq);
1034                 } else {
1035                         /* Use default TX function if we get here */
1036                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1037                                              "Using default TX function.");
1038                 }
1039
1040                 ixgbe_set_rx_function(eth_dev);
1041
1042                 return 0;
1043         }
1044         pci_dev = eth_dev->pci_dev;
1045
1046         rte_eth_copy_pci_info(eth_dev, pci_dev);
1047
1048         /* Vendor and Device ID need to be set before init of shared code */
1049         hw->device_id = pci_dev->id.device_id;
1050         hw->vendor_id = pci_dev->id.vendor_id;
1051         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1052         hw->allow_unsupported_sfp = 1;
1053
1054         /* Initialize the shared code (base driver) */
1055 #ifdef RTE_NIC_BYPASS
1056         diag = ixgbe_bypass_init_shared_code(hw);
1057 #else
1058         diag = ixgbe_init_shared_code(hw);
1059 #endif /* RTE_NIC_BYPASS */
1060
1061         if (diag != IXGBE_SUCCESS) {
1062                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1063                 return -EIO;
1064         }
1065
1066         /* pick up the PCI bus settings for reporting later */
1067         ixgbe_get_bus_info(hw);
1068
1069         /* Unlock any pending hardware semaphore */
1070         ixgbe_swfw_lock_reset(hw);
1071
1072         /* Initialize DCB configuration*/
1073         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1074         ixgbe_dcb_init(hw,dcb_config);
1075         /* Get Hardware Flow Control setting */
1076         hw->fc.requested_mode = ixgbe_fc_full;
1077         hw->fc.current_mode = ixgbe_fc_full;
1078         hw->fc.pause_time = IXGBE_FC_PAUSE;
1079         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1080                 hw->fc.low_water[i] = IXGBE_FC_LO;
1081                 hw->fc.high_water[i] = IXGBE_FC_HI;
1082         }
1083         hw->fc.send_xon = 1;
1084
1085         /* Make sure we have a good EEPROM before we read from it */
1086         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1087         if (diag != IXGBE_SUCCESS) {
1088                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1089                 return -EIO;
1090         }
1091
1092 #ifdef RTE_NIC_BYPASS
1093         diag = ixgbe_bypass_init_hw(hw);
1094 #else
1095         diag = ixgbe_init_hw(hw);
1096 #endif /* RTE_NIC_BYPASS */
1097
1098         /*
1099          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1100          * is called too soon after the kernel driver unbinding/binding occurs.
1101          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1102          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1103          * also called. See ixgbe_identify_phy_82599(). The reason for the
1104          * failure is not known, and only occuts when virtualisation features
1105          * are disabled in the bios. A delay of 100ms  was found to be enough by
1106          * trial-and-error, and is doubled to be safe.
1107          */
1108         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1109                 rte_delay_ms(200);
1110                 diag = ixgbe_init_hw(hw);
1111         }
1112
1113         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1114                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1115                     "LOM.  Please be aware there may be issues associated "
1116                     "with your hardware.");
1117                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1118                     "please contact your Intel or hardware representative "
1119                     "who provided you with this hardware.");
1120         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1121                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1122         if (diag) {
1123                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1124                 return -EIO;
1125         }
1126
1127         /* Reset the hw statistics */
1128         ixgbe_dev_stats_reset(eth_dev);
1129
1130         /* disable interrupt */
1131         ixgbe_disable_intr(hw);
1132
1133         /* reset mappings for queue statistics hw counters*/
1134         ixgbe_reset_qstat_mappings(hw);
1135
1136         /* Allocate memory for storing MAC addresses */
1137         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1138                         hw->mac.num_rar_entries, 0);
1139         if (eth_dev->data->mac_addrs == NULL) {
1140                 PMD_INIT_LOG(ERR,
1141                         "Failed to allocate %u bytes needed to store "
1142                         "MAC addresses",
1143                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1144                 return -ENOMEM;
1145         }
1146         /* Copy the permanent MAC address */
1147         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1148                         &eth_dev->data->mac_addrs[0]);
1149
1150         /* Allocate memory for storing hash filter MAC addresses */
1151         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1152                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1153         if (eth_dev->data->hash_mac_addrs == NULL) {
1154                 PMD_INIT_LOG(ERR,
1155                         "Failed to allocate %d bytes needed to store MAC addresses",
1156                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1157                 return -ENOMEM;
1158         }
1159
1160         /* initialize the vfta */
1161         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1162
1163         /* initialize the hw strip bitmap*/
1164         memset(hwstrip, 0, sizeof(*hwstrip));
1165
1166         /* initialize PF if max_vfs not zero */
1167         ixgbe_pf_host_init(eth_dev);
1168
1169         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1170         /* let hardware know driver is loaded */
1171         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1172         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1173         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1174         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1175         IXGBE_WRITE_FLUSH(hw);
1176
1177         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1178                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1179                              (int) hw->mac.type, (int) hw->phy.type,
1180                              (int) hw->phy.sfp_type);
1181         else
1182                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1183                              (int) hw->mac.type, (int) hw->phy.type);
1184
1185         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1186                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1187                         pci_dev->id.device_id);
1188
1189         rte_intr_callback_register(&pci_dev->intr_handle,
1190                                    ixgbe_dev_interrupt_handler,
1191                                    (void *)eth_dev);
1192
1193         /* enable uio/vfio intr/eventfd mapping */
1194         rte_intr_enable(&pci_dev->intr_handle);
1195
1196         /* enable support intr */
1197         ixgbe_enable_intr(eth_dev);
1198
1199         /* initialize 5tuple filter list */
1200         TAILQ_INIT(&filter_info->fivetuple_list);
1201         memset(filter_info->fivetuple_mask, 0,
1202                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1203
1204         return 0;
1205 }
1206
1207 static int
1208 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1209 {
1210         struct rte_pci_device *pci_dev;
1211         struct ixgbe_hw *hw;
1212
1213         PMD_INIT_FUNC_TRACE();
1214
1215         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1216                 return -EPERM;
1217
1218         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1219         pci_dev = eth_dev->pci_dev;
1220
1221         if (hw->adapter_stopped == 0)
1222                 ixgbe_dev_close(eth_dev);
1223
1224         eth_dev->dev_ops = NULL;
1225         eth_dev->rx_pkt_burst = NULL;
1226         eth_dev->tx_pkt_burst = NULL;
1227
1228         /* Unlock any pending hardware semaphore */
1229         ixgbe_swfw_lock_reset(hw);
1230
1231         /* disable uio intr before callback unregister */
1232         rte_intr_disable(&(pci_dev->intr_handle));
1233         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1234                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1235
1236         /* uninitialize PF if max_vfs not zero */
1237         ixgbe_pf_host_uninit(eth_dev);
1238
1239         rte_free(eth_dev->data->mac_addrs);
1240         eth_dev->data->mac_addrs = NULL;
1241
1242         rte_free(eth_dev->data->hash_mac_addrs);
1243         eth_dev->data->hash_mac_addrs = NULL;
1244
1245         return 0;
1246 }
1247
1248 /*
1249  * Negotiate mailbox API version with the PF.
1250  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1251  * Then we try to negotiate starting with the most recent one.
1252  * If all negotiation attempts fail, then we will proceed with
1253  * the default one (ixgbe_mbox_api_10).
1254  */
1255 static void
1256 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1257 {
1258         int32_t i;
1259
1260         /* start with highest supported, proceed down */
1261         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1262                 ixgbe_mbox_api_11,
1263                 ixgbe_mbox_api_10,
1264         };
1265
1266         for (i = 0;
1267                         i != RTE_DIM(sup_ver) &&
1268                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1269                         i++)
1270                 ;
1271 }
1272
1273 static void
1274 generate_random_mac_addr(struct ether_addr *mac_addr)
1275 {
1276         uint64_t random;
1277
1278         /* Set Organizationally Unique Identifier (OUI) prefix. */
1279         mac_addr->addr_bytes[0] = 0x00;
1280         mac_addr->addr_bytes[1] = 0x09;
1281         mac_addr->addr_bytes[2] = 0xC0;
1282         /* Force indication of locally assigned MAC address. */
1283         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1284         /* Generate the last 3 bytes of the MAC address with a random number. */
1285         random = rte_rand();
1286         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1287 }
1288
1289 /*
1290  * Virtual Function device init
1291  */
1292 static int
1293 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1294 {
1295         int diag;
1296         uint32_t tc, tcs;
1297         struct rte_pci_device *pci_dev;
1298         struct ixgbe_hw *hw =
1299                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1300         struct ixgbe_vfta * shadow_vfta =
1301                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1302         struct ixgbe_hwstrip *hwstrip =
1303                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1304         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1305
1306         PMD_INIT_FUNC_TRACE();
1307
1308         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1309         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1310         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1311
1312         /* for secondary processes, we don't initialise any further as primary
1313          * has already done this work. Only check we don't need a different
1314          * RX function */
1315         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1316                 if (eth_dev->data->scattered_rx)
1317                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1318                 return 0;
1319         }
1320
1321         pci_dev = eth_dev->pci_dev;
1322
1323         rte_eth_copy_pci_info(eth_dev, pci_dev);
1324
1325         hw->device_id = pci_dev->id.device_id;
1326         hw->vendor_id = pci_dev->id.vendor_id;
1327         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1328
1329         /* initialize the vfta */
1330         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1331
1332         /* initialize the hw strip bitmap*/
1333         memset(hwstrip, 0, sizeof(*hwstrip));
1334
1335         /* Initialize the shared code (base driver) */
1336         diag = ixgbe_init_shared_code(hw);
1337         if (diag != IXGBE_SUCCESS) {
1338                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1339                 return -EIO;
1340         }
1341
1342         /* init_mailbox_params */
1343         hw->mbx.ops.init_params(hw);
1344
1345         /* Reset the hw statistics */
1346         ixgbevf_dev_stats_reset(eth_dev);
1347
1348         /* Disable the interrupts for VF */
1349         ixgbevf_intr_disable(hw);
1350
1351         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1352         diag = hw->mac.ops.reset_hw(hw);
1353
1354         /*
1355          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1356          * the underlying PF driver has not assigned a MAC address to the VF.
1357          * In this case, assign a random MAC address.
1358          */
1359         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1360                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1361                 return diag;
1362         }
1363
1364         /* negotiate mailbox API version to use with the PF. */
1365         ixgbevf_negotiate_api(hw);
1366
1367         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1368         ixgbevf_get_queues(hw, &tcs, &tc);
1369
1370         /* Allocate memory for storing MAC addresses */
1371         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1372                         hw->mac.num_rar_entries, 0);
1373         if (eth_dev->data->mac_addrs == NULL) {
1374                 PMD_INIT_LOG(ERR,
1375                         "Failed to allocate %u bytes needed to store "
1376                         "MAC addresses",
1377                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1378                 return -ENOMEM;
1379         }
1380
1381         /* Generate a random MAC address, if none was assigned by PF. */
1382         if (is_zero_ether_addr(perm_addr)) {
1383                 generate_random_mac_addr(perm_addr);
1384                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1385                 if (diag) {
1386                         rte_free(eth_dev->data->mac_addrs);
1387                         eth_dev->data->mac_addrs = NULL;
1388                         return diag;
1389                 }
1390                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1391                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1392                              "%02x:%02x:%02x:%02x:%02x:%02x",
1393                              perm_addr->addr_bytes[0],
1394                              perm_addr->addr_bytes[1],
1395                              perm_addr->addr_bytes[2],
1396                              perm_addr->addr_bytes[3],
1397                              perm_addr->addr_bytes[4],
1398                              perm_addr->addr_bytes[5]);
1399         }
1400
1401         /* Copy the permanent MAC address */
1402         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1403
1404         /* reset the hardware with the new settings */
1405         diag = hw->mac.ops.start_hw(hw);
1406         switch (diag) {
1407                 case  0:
1408                         break;
1409
1410                 default:
1411                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1412                         return -EIO;
1413         }
1414
1415         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1416                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1417                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1418
1419         return 0;
1420 }
1421
1422 /* Virtual Function device uninit */
1423
1424 static int
1425 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1426 {
1427         struct ixgbe_hw *hw;
1428         unsigned i;
1429
1430         PMD_INIT_FUNC_TRACE();
1431
1432         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1433                 return -EPERM;
1434
1435         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1436
1437         if (hw->adapter_stopped == 0)
1438                 ixgbevf_dev_close(eth_dev);
1439
1440         eth_dev->dev_ops = NULL;
1441         eth_dev->rx_pkt_burst = NULL;
1442         eth_dev->tx_pkt_burst = NULL;
1443
1444         /* Disable the interrupts for VF */
1445         ixgbevf_intr_disable(hw);
1446
1447         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1448                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1449                 eth_dev->data->rx_queues[i] = NULL;
1450         }
1451         eth_dev->data->nb_rx_queues = 0;
1452
1453         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1454                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1455                 eth_dev->data->tx_queues[i] = NULL;
1456         }
1457         eth_dev->data->nb_tx_queues = 0;
1458
1459         rte_free(eth_dev->data->mac_addrs);
1460         eth_dev->data->mac_addrs = NULL;
1461
1462         return 0;
1463 }
1464
1465 static struct eth_driver rte_ixgbe_pmd = {
1466         .pci_drv = {
1467                 .name = "rte_ixgbe_pmd",
1468                 .id_table = pci_id_ixgbe_map,
1469                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1470                         RTE_PCI_DRV_DETACHABLE,
1471         },
1472         .eth_dev_init = eth_ixgbe_dev_init,
1473         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1474         .dev_private_size = sizeof(struct ixgbe_adapter),
1475 };
1476
1477 /*
1478  * virtual function driver struct
1479  */
1480 static struct eth_driver rte_ixgbevf_pmd = {
1481         .pci_drv = {
1482                 .name = "rte_ixgbevf_pmd",
1483                 .id_table = pci_id_ixgbevf_map,
1484                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1485         },
1486         .eth_dev_init = eth_ixgbevf_dev_init,
1487         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1488         .dev_private_size = sizeof(struct ixgbe_adapter),
1489 };
1490
1491 /*
1492  * Driver initialization routine.
1493  * Invoked once at EAL init time.
1494  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1495  */
1496 static int
1497 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1498 {
1499         PMD_INIT_FUNC_TRACE();
1500
1501         rte_eth_driver_register(&rte_ixgbe_pmd);
1502         return 0;
1503 }
1504
1505 /*
1506  * VF Driver initialization routine.
1507  * Invoked one at EAL init time.
1508  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1509  */
1510 static int
1511 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1512 {
1513         PMD_INIT_FUNC_TRACE();
1514
1515         rte_eth_driver_register(&rte_ixgbevf_pmd);
1516         return 0;
1517 }
1518
1519 static int
1520 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1521 {
1522         struct ixgbe_hw *hw =
1523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         struct ixgbe_vfta * shadow_vfta =
1525                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1526         uint32_t vfta;
1527         uint32_t vid_idx;
1528         uint32_t vid_bit;
1529
1530         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1531         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1532         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1533         if (on)
1534                 vfta |= vid_bit;
1535         else
1536                 vfta &= ~vid_bit;
1537         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1538
1539         /* update local VFTA copy */
1540         shadow_vfta->vfta[vid_idx] = vfta;
1541
1542         return 0;
1543 }
1544
1545 static void
1546 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1547 {
1548         if (on)
1549                 ixgbe_vlan_hw_strip_enable(dev, queue);
1550         else
1551                 ixgbe_vlan_hw_strip_disable(dev, queue);
1552 }
1553
1554 static int
1555 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1556                     enum rte_vlan_type vlan_type,
1557                     uint16_t tpid)
1558 {
1559         struct ixgbe_hw *hw =
1560                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561         int ret = 0;
1562
1563         switch (vlan_type) {
1564         case ETH_VLAN_TYPE_INNER:
1565                 /* Only the high 16-bits is valid */
1566                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1567                 break;
1568         default:
1569                 ret = -EINVAL;
1570                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1571                 break;
1572         }
1573
1574         return ret;
1575 }
1576
1577 void
1578 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1579 {
1580         struct ixgbe_hw *hw =
1581                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582         uint32_t vlnctrl;
1583
1584         PMD_INIT_FUNC_TRACE();
1585
1586         /* Filter Table Disable */
1587         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1588         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1589
1590         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1591 }
1592
1593 void
1594 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1595 {
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         struct ixgbe_vfta * shadow_vfta =
1599                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1600         uint32_t vlnctrl;
1601         uint16_t i;
1602
1603         PMD_INIT_FUNC_TRACE();
1604
1605         /* Filter Table Enable */
1606         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1607         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1608         vlnctrl |= IXGBE_VLNCTRL_VFE;
1609
1610         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1611
1612         /* write whatever is in local vfta copy */
1613         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1614                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1615 }
1616
1617 static void
1618 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1619 {
1620         struct ixgbe_hwstrip *hwstrip =
1621                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1622
1623         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1624                 return;
1625
1626         if (on)
1627                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1628         else
1629                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1630 }
1631
1632 static void
1633 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1634 {
1635         struct ixgbe_hw *hw =
1636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         uint32_t ctrl;
1638
1639         PMD_INIT_FUNC_TRACE();
1640
1641         if (hw->mac.type == ixgbe_mac_82598EB) {
1642                 /* No queue level support */
1643                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1644                 return;
1645         }
1646         else {
1647                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1648                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1649                 ctrl &= ~IXGBE_RXDCTL_VME;
1650                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1651         }
1652         /* record those setting for HW strip per queue */
1653         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1654 }
1655
1656 static void
1657 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1658 {
1659         struct ixgbe_hw *hw =
1660                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661         uint32_t ctrl;
1662
1663         PMD_INIT_FUNC_TRACE();
1664
1665         if (hw->mac.type == ixgbe_mac_82598EB) {
1666                 /* No queue level supported */
1667                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1668                 return;
1669         }
1670         else {
1671                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1672                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1673                 ctrl |= IXGBE_RXDCTL_VME;
1674                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1675         }
1676         /* record those setting for HW strip per queue */
1677         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1678 }
1679
1680 void
1681 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1682 {
1683         struct ixgbe_hw *hw =
1684                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         uint32_t ctrl;
1686         uint16_t i;
1687
1688         PMD_INIT_FUNC_TRACE();
1689
1690         if (hw->mac.type == ixgbe_mac_82598EB) {
1691                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1692                 ctrl &= ~IXGBE_VLNCTRL_VME;
1693                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1694         }
1695         else {
1696                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1697                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1698                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1699                         ctrl &= ~IXGBE_RXDCTL_VME;
1700                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1701
1702                         /* record those setting for HW strip per queue */
1703                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1704                 }
1705         }
1706 }
1707
1708 void
1709 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1710 {
1711         struct ixgbe_hw *hw =
1712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1713         uint32_t ctrl;
1714         uint16_t i;
1715
1716         PMD_INIT_FUNC_TRACE();
1717
1718         if (hw->mac.type == ixgbe_mac_82598EB) {
1719                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1720                 ctrl |= IXGBE_VLNCTRL_VME;
1721                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1722         }
1723         else {
1724                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1725                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1726                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1727                         ctrl |= IXGBE_RXDCTL_VME;
1728                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1729
1730                         /* record those setting for HW strip per queue */
1731                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1732                 }
1733         }
1734 }
1735
1736 static void
1737 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1738 {
1739         struct ixgbe_hw *hw =
1740                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1741         uint32_t ctrl;
1742
1743         PMD_INIT_FUNC_TRACE();
1744
1745         /* DMATXCTRL: Geric Double VLAN Disable */
1746         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1747         ctrl &= ~IXGBE_DMATXCTL_GDV;
1748         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1749
1750         /* CTRL_EXT: Global Double VLAN Disable */
1751         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1752         ctrl &= ~IXGBE_EXTENDED_VLAN;
1753         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1754
1755 }
1756
1757 static void
1758 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1759 {
1760         struct ixgbe_hw *hw =
1761                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1762         uint32_t ctrl;
1763
1764         PMD_INIT_FUNC_TRACE();
1765
1766         /* DMATXCTRL: Geric Double VLAN Enable */
1767         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1768         ctrl |= IXGBE_DMATXCTL_GDV;
1769         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1770
1771         /* CTRL_EXT: Global Double VLAN Enable */
1772         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1773         ctrl |= IXGBE_EXTENDED_VLAN;
1774         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1775
1776         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1777         if (hw->mac.type == ixgbe_mac_X550 ||
1778             hw->mac.type == ixgbe_mac_X550EM_x) {
1779                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1780                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1781                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1782         }
1783
1784         /*
1785          * VET EXT field in the EXVET register = 0x8100 by default
1786          * So no need to change. Same to VT field of DMATXCTL register
1787          */
1788 }
1789
1790 static void
1791 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1792 {
1793         if (mask & ETH_VLAN_STRIP_MASK) {
1794                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1795                         ixgbe_vlan_hw_strip_enable_all(dev);
1796                 else
1797                         ixgbe_vlan_hw_strip_disable_all(dev);
1798         }
1799
1800         if (mask & ETH_VLAN_FILTER_MASK) {
1801                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1802                         ixgbe_vlan_hw_filter_enable(dev);
1803                 else
1804                         ixgbe_vlan_hw_filter_disable(dev);
1805         }
1806
1807         if (mask & ETH_VLAN_EXTEND_MASK) {
1808                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1809                         ixgbe_vlan_hw_extend_enable(dev);
1810                 else
1811                         ixgbe_vlan_hw_extend_disable(dev);
1812         }
1813 }
1814
1815 static void
1816 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1817 {
1818         struct ixgbe_hw *hw =
1819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1821         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1822         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1823         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1824 }
1825
1826 static int
1827 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1828 {
1829         switch (nb_rx_q) {
1830         case 1:
1831         case 2:
1832                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1833                 break;
1834         case 4:
1835                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1836                 break;
1837         default:
1838                 return -EINVAL;
1839         }
1840
1841         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1842         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1843
1844         return 0;
1845 }
1846
1847 static int
1848 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1849 {
1850         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1851         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1852         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1853
1854         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1855                 /* check multi-queue mode */
1856                 switch (dev_conf->rxmode.mq_mode) {
1857                 case ETH_MQ_RX_VMDQ_DCB:
1858                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1859                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1860                         PMD_INIT_LOG(ERR, "SRIOV active,"
1861                                         " unsupported mq_mode rx %d.",
1862                                         dev_conf->rxmode.mq_mode);
1863                         return -EINVAL;
1864                 case ETH_MQ_RX_RSS:
1865                 case ETH_MQ_RX_VMDQ_RSS:
1866                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1867                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1868                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1869                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1870                                                 " invalid queue number"
1871                                                 " for VMDQ RSS, allowed"
1872                                                 " value are 1, 2 or 4.");
1873                                         return -EINVAL;
1874                                 }
1875                         break;
1876                 case ETH_MQ_RX_VMDQ_ONLY:
1877                 case ETH_MQ_RX_NONE:
1878                         /* if nothing mq mode configure, use default scheme */
1879                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1880                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1881                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1882                         break;
1883                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1884                         /* SRIOV only works in VMDq enable mode */
1885                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1886                                         " wrong mq_mode rx %d.",
1887                                         dev_conf->rxmode.mq_mode);
1888                         return -EINVAL;
1889                 }
1890
1891                 switch (dev_conf->txmode.mq_mode) {
1892                 case ETH_MQ_TX_VMDQ_DCB:
1893                         /* DCB VMDQ in SRIOV mode, not implement yet */
1894                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1895                                         " unsupported VMDQ mq_mode tx %d.",
1896                                         dev_conf->txmode.mq_mode);
1897                         return -EINVAL;
1898                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1899                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1900                         break;
1901                 }
1902
1903                 /* check valid queue number */
1904                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1905                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1906                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1907                                         " queue number must less equal to %d.",
1908                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1909                         return -EINVAL;
1910                 }
1911         } else {
1912                 /* check configuration for vmdb+dcb mode */
1913                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1914                         const struct rte_eth_vmdq_dcb_conf *conf;
1915
1916                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1917                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1918                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1919                                 return -EINVAL;
1920                         }
1921                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1922                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1923                                conf->nb_queue_pools == ETH_32_POOLS)) {
1924                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1925                                                 " nb_queue_pools must be %d or %d.",
1926                                                 ETH_16_POOLS, ETH_32_POOLS);
1927                                 return -EINVAL;
1928                         }
1929                 }
1930                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1931                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1932
1933                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1934                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1935                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1936                                 return -EINVAL;
1937                         }
1938                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1939                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1940                                conf->nb_queue_pools == ETH_32_POOLS)) {
1941                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1942                                                 " nb_queue_pools != %d and"
1943                                                 " nb_queue_pools != %d.",
1944                                                 ETH_16_POOLS, ETH_32_POOLS);
1945                                 return -EINVAL;
1946                         }
1947                 }
1948
1949                 /* For DCB mode check our configuration before we go further */
1950                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1951                         const struct rte_eth_dcb_rx_conf *conf;
1952
1953                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1954                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1955                                                  IXGBE_DCB_NB_QUEUES);
1956                                 return -EINVAL;
1957                         }
1958                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1959                         if (!(conf->nb_tcs == ETH_4_TCS ||
1960                                conf->nb_tcs == ETH_8_TCS)) {
1961                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1962                                                 " and nb_tcs != %d.",
1963                                                 ETH_4_TCS, ETH_8_TCS);
1964                                 return -EINVAL;
1965                         }
1966                 }
1967
1968                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1969                         const struct rte_eth_dcb_tx_conf *conf;
1970
1971                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1972                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1973                                                  IXGBE_DCB_NB_QUEUES);
1974                                 return -EINVAL;
1975                         }
1976                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1977                         if (!(conf->nb_tcs == ETH_4_TCS ||
1978                                conf->nb_tcs == ETH_8_TCS)) {
1979                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1980                                                 " and nb_tcs != %d.",
1981                                                 ETH_4_TCS, ETH_8_TCS);
1982                                 return -EINVAL;
1983                         }
1984                 }
1985         }
1986         return 0;
1987 }
1988
1989 static int
1990 ixgbe_dev_configure(struct rte_eth_dev *dev)
1991 {
1992         struct ixgbe_interrupt *intr =
1993                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1994         struct ixgbe_adapter *adapter =
1995                 (struct ixgbe_adapter *)dev->data->dev_private;
1996         int ret;
1997
1998         PMD_INIT_FUNC_TRACE();
1999         /* multipe queue mode checking */
2000         ret  = ixgbe_check_mq_mode(dev);
2001         if (ret != 0) {
2002                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2003                             ret);
2004                 return ret;
2005         }
2006
2007         /* set flag to update link status after init */
2008         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2009
2010         /*
2011          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2012          * allocation or vector Rx preconditions we will reset it.
2013          */
2014         adapter->rx_bulk_alloc_allowed = true;
2015         adapter->rx_vec_allowed = true;
2016
2017         return 0;
2018 }
2019
2020 /*
2021  * Configure device link speed and setup link.
2022  * It returns 0 on success.
2023  */
2024 static int
2025 ixgbe_dev_start(struct rte_eth_dev *dev)
2026 {
2027         struct ixgbe_hw *hw =
2028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         struct ixgbe_vf_info *vfinfo =
2030                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2031         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2032         uint32_t intr_vector = 0;
2033         int err, link_up = 0, negotiate = 0;
2034         uint32_t speed = 0;
2035         int mask = 0;
2036         int status;
2037         uint16_t vf, idx;
2038
2039         PMD_INIT_FUNC_TRACE();
2040
2041         /* IXGBE devices don't support half duplex */
2042         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2043                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2044                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2045                              dev->data->dev_conf.link_duplex,
2046                              dev->data->port_id);
2047                 return -EINVAL;
2048         }
2049
2050         /* disable uio/vfio intr/eventfd mapping */
2051         rte_intr_disable(intr_handle);
2052
2053         /* stop adapter */
2054         hw->adapter_stopped = 0;
2055         ixgbe_stop_adapter(hw);
2056
2057         /* reinitialize adapter
2058          * this calls reset and start */
2059         status = ixgbe_pf_reset_hw(hw);
2060         if (status != 0)
2061                 return -1;
2062         hw->mac.ops.start_hw(hw);
2063         hw->mac.get_link_status = true;
2064
2065         /* configure PF module if SRIOV enabled */
2066         ixgbe_pf_host_configure(dev);
2067
2068         /* check and configure queue intr-vector mapping */
2069         if ((rte_intr_cap_multiple(intr_handle) ||
2070              !RTE_ETH_DEV_SRIOV(dev).active) &&
2071             dev->data->dev_conf.intr_conf.rxq != 0) {
2072                 intr_vector = dev->data->nb_rx_queues;
2073                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2074                         return -1;
2075         }
2076
2077         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2078                 intr_handle->intr_vec =
2079                         rte_zmalloc("intr_vec",
2080                                     dev->data->nb_rx_queues * sizeof(int), 0);
2081                 if (intr_handle->intr_vec == NULL) {
2082                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2083                                      " intr_vec\n", dev->data->nb_rx_queues);
2084                         return -ENOMEM;
2085                 }
2086         }
2087
2088         /* confiugre msix for sleep until rx interrupt */
2089         ixgbe_configure_msix(dev);
2090
2091         /* initialize transmission unit */
2092         ixgbe_dev_tx_init(dev);
2093
2094         /* This can fail when allocating mbufs for descriptor rings */
2095         err = ixgbe_dev_rx_init(dev);
2096         if (err) {
2097                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2098                 goto error;
2099         }
2100
2101         err = ixgbe_dev_rxtx_start(dev);
2102         if (err < 0) {
2103                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2104                 goto error;
2105         }
2106
2107         /* Skip link setup if loopback mode is enabled for 82599. */
2108         if (hw->mac.type == ixgbe_mac_82599EB &&
2109                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2110                 goto skip_link_setup;
2111
2112         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2113                 err = hw->mac.ops.setup_sfp(hw);
2114                 if (err)
2115                         goto error;
2116         }
2117
2118         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2119                 /* Turn on the copper */
2120                 ixgbe_set_phy_power(hw, true);
2121         } else {
2122                 /* Turn on the laser */
2123                 ixgbe_enable_tx_laser(hw);
2124         }
2125
2126         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2127         if (err)
2128                 goto error;
2129         dev->data->dev_link.link_status = link_up;
2130
2131         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2132         if (err)
2133                 goto error;
2134
2135         switch(dev->data->dev_conf.link_speed) {
2136         case ETH_LINK_SPEED_AUTONEG:
2137                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2138                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2139                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2140                 break;
2141         case ETH_LINK_SPEED_100:
2142                 /*
2143                  * Invalid for 82598 but error will be detected by
2144                  * ixgbe_setup_link()
2145                  */
2146                 speed = IXGBE_LINK_SPEED_100_FULL;
2147                 break;
2148         case ETH_LINK_SPEED_1000:
2149                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2150                 break;
2151         case ETH_LINK_SPEED_10000:
2152                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2153                 break;
2154         default:
2155                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2156                              dev->data->dev_conf.link_speed,
2157                              dev->data->port_id);
2158                 goto error;
2159         }
2160
2161         err = ixgbe_setup_link(hw, speed, link_up);
2162         if (err)
2163                 goto error;
2164
2165 skip_link_setup:
2166
2167         if (rte_intr_allow_others(intr_handle)) {
2168                 /* check if lsc interrupt is enabled */
2169                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2170                         ixgbe_dev_lsc_interrupt_setup(dev);
2171         } else {
2172                 rte_intr_callback_unregister(intr_handle,
2173                                              ixgbe_dev_interrupt_handler,
2174                                              (void *)dev);
2175                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2176                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2177                                      " no intr multiplex\n");
2178         }
2179
2180         /* check if rxq interrupt is enabled */
2181         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2182             rte_intr_dp_is_en(intr_handle))
2183                 ixgbe_dev_rxq_interrupt_setup(dev);
2184
2185         /* enable uio/vfio intr/eventfd mapping */
2186         rte_intr_enable(intr_handle);
2187
2188         /* resume enabled intr since hw reset */
2189         ixgbe_enable_intr(dev);
2190
2191         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2192                 ETH_VLAN_EXTEND_MASK;
2193         ixgbe_vlan_offload_set(dev, mask);
2194
2195         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2196                 /* Enable vlan filtering for VMDq */
2197                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2198         }
2199
2200         /* Configure DCB hw */
2201         ixgbe_configure_dcb(dev);
2202
2203         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2204                 err = ixgbe_fdir_configure(dev);
2205                 if (err)
2206                         goto error;
2207         }
2208
2209         /* Restore vf rate limit */
2210         if (vfinfo != NULL) {
2211                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2212                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2213                                 if (vfinfo[vf].tx_rate[idx] != 0)
2214                                         ixgbe_set_vf_rate_limit(dev, vf,
2215                                                 vfinfo[vf].tx_rate[idx],
2216                                                 1 << idx);
2217         }
2218
2219         ixgbe_restore_statistics_mapping(dev);
2220
2221         return 0;
2222
2223 error:
2224         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2225         ixgbe_dev_clear_queues(dev);
2226         return -EIO;
2227 }
2228
2229 /*
2230  * Stop device: disable rx and tx functions to allow for reconfiguring.
2231  */
2232 static void
2233 ixgbe_dev_stop(struct rte_eth_dev *dev)
2234 {
2235         struct rte_eth_link link;
2236         struct ixgbe_hw *hw =
2237                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         struct ixgbe_vf_info *vfinfo =
2239                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2240         struct ixgbe_filter_info *filter_info =
2241                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2242         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2243         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2244         int vf;
2245
2246         PMD_INIT_FUNC_TRACE();
2247
2248         /* disable interrupts */
2249         ixgbe_disable_intr(hw);
2250
2251         /* disable intr eventfd mapping */
2252         rte_intr_disable(intr_handle);
2253
2254         /* reset the NIC */
2255         ixgbe_pf_reset_hw(hw);
2256         hw->adapter_stopped = 0;
2257
2258         /* stop adapter */
2259         ixgbe_stop_adapter(hw);
2260
2261         for (vf = 0; vfinfo != NULL &&
2262                      vf < dev->pci_dev->max_vfs; vf++)
2263                 vfinfo[vf].clear_to_send = false;
2264
2265         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2266                 /* Turn off the copper */
2267                 ixgbe_set_phy_power(hw, false);
2268         } else {
2269                 /* Turn off the laser */
2270                 ixgbe_disable_tx_laser(hw);
2271         }
2272
2273         ixgbe_dev_clear_queues(dev);
2274
2275         /* Clear stored conf */
2276         dev->data->scattered_rx = 0;
2277         dev->data->lro = 0;
2278
2279         /* Clear recorded link status */
2280         memset(&link, 0, sizeof(link));
2281         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2282
2283         /* Remove all ntuple filters of the device */
2284         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2285              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2286                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2287                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2288                              p_5tuple, entries);
2289                 rte_free(p_5tuple);
2290         }
2291         memset(filter_info->fivetuple_mask, 0,
2292                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2293
2294         if (!rte_intr_allow_others(intr_handle))
2295                 /* resume to the default handler */
2296                 rte_intr_callback_register(intr_handle,
2297                                            ixgbe_dev_interrupt_handler,
2298                                            (void *)dev);
2299
2300         /* Clean datapath event and queue/vec mapping */
2301         rte_intr_efd_disable(intr_handle);
2302         if (intr_handle->intr_vec != NULL) {
2303                 rte_free(intr_handle->intr_vec);
2304                 intr_handle->intr_vec = NULL;
2305         }
2306 }
2307
2308 /*
2309  * Set device link up: enable tx.
2310  */
2311 static int
2312 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2313 {
2314         struct ixgbe_hw *hw =
2315                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316         if (hw->mac.type == ixgbe_mac_82599EB) {
2317 #ifdef RTE_NIC_BYPASS
2318                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2319                         /* Not suported in bypass mode */
2320                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2321                                      "by device id 0x%x", hw->device_id);
2322                         return -ENOTSUP;
2323                 }
2324 #endif
2325         }
2326
2327         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2328                 /* Turn on the copper */
2329                 ixgbe_set_phy_power(hw, true);
2330         } else {
2331                 /* Turn on the laser */
2332                 ixgbe_enable_tx_laser(hw);
2333         }
2334
2335         return 0;
2336 }
2337
2338 /*
2339  * Set device link down: disable tx.
2340  */
2341 static int
2342 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2343 {
2344         struct ixgbe_hw *hw =
2345                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2346         if (hw->mac.type == ixgbe_mac_82599EB) {
2347 #ifdef RTE_NIC_BYPASS
2348                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2349                         /* Not suported in bypass mode */
2350                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2351                                      "by device id 0x%x", hw->device_id);
2352                         return -ENOTSUP;
2353                 }
2354 #endif
2355         }
2356
2357         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2358                 /* Turn off the copper */
2359                 ixgbe_set_phy_power(hw, false);
2360         } else {
2361                 /* Turn off the laser */
2362                 ixgbe_disable_tx_laser(hw);
2363         }
2364
2365         return 0;
2366 }
2367
2368 /*
2369  * Reest and stop device.
2370  */
2371 static void
2372 ixgbe_dev_close(struct rte_eth_dev *dev)
2373 {
2374         struct ixgbe_hw *hw =
2375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376
2377         PMD_INIT_FUNC_TRACE();
2378
2379         ixgbe_pf_reset_hw(hw);
2380
2381         ixgbe_dev_stop(dev);
2382         hw->adapter_stopped = 1;
2383
2384         ixgbe_dev_free_queues(dev);
2385
2386         ixgbe_disable_pcie_master(hw);
2387
2388         /* reprogram the RAR[0] in case user changed it. */
2389         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2390 }
2391
2392 static void
2393 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2394                            struct ixgbe_hw_stats *hw_stats,
2395                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2396                            uint64_t *total_qprc, uint64_t *total_qprdc)
2397 {
2398         uint32_t bprc, lxon, lxoff, total;
2399         uint32_t delta_gprc = 0;
2400         unsigned i;
2401         /* Workaround for RX byte count not including CRC bytes when CRC
2402 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2403          * is disabled.
2404 +        */
2405         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2406                         IXGBE_HLREG0_RXCRCSTRP);
2407
2408         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2409         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2410         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2411         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2412
2413         for (i = 0; i < 8; i++) {
2414                 uint32_t mp;
2415                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2416                 /* global total per queue */
2417                 hw_stats->mpc[i] += mp;
2418                 /* Running comprehensive total for stats display */
2419                 *total_missed_rx += hw_stats->mpc[i];
2420                 if (hw->mac.type == ixgbe_mac_82598EB) {
2421                         hw_stats->rnbc[i] +=
2422                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2423                         hw_stats->pxonrxc[i] +=
2424                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2425                         hw_stats->pxoffrxc[i] +=
2426                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2427                 } else {
2428                         hw_stats->pxonrxc[i] +=
2429                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2430                         hw_stats->pxoffrxc[i] +=
2431                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2432                         hw_stats->pxon2offc[i] +=
2433                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2434                 }
2435                 hw_stats->pxontxc[i] +=
2436                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2437                 hw_stats->pxofftxc[i] +=
2438                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2439         }
2440         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2441                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2442                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2443                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2444
2445                 delta_gprc += delta_qprc;
2446
2447                 hw_stats->qprc[i] += delta_qprc;
2448                 hw_stats->qptc[i] += delta_qptc;
2449
2450                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2451                 hw_stats->qbrc[i] +=
2452                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2453                 if (crc_strip == 0)
2454                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2455
2456                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2457                 hw_stats->qbtc[i] +=
2458                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2459
2460                 hw_stats->qprdc[i] += delta_qprdc;
2461                 *total_qprdc += hw_stats->qprdc[i];
2462
2463                 *total_qprc += hw_stats->qprc[i];
2464                 *total_qbrc += hw_stats->qbrc[i];
2465         }
2466         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2467         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2468         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2469
2470         /*
2471          * An errata states that gprc actually counts good + missed packets:
2472          * Workaround to set gprc to summated queue packet receives
2473          */
2474         hw_stats->gprc = *total_qprc;
2475
2476         if (hw->mac.type != ixgbe_mac_82598EB) {
2477                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2478                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2479                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2480                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2481                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2482                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2483                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2484                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2485         } else {
2486                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2487                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2488                 /* 82598 only has a counter in the high register */
2489                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2490                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2491                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2492         }
2493         uint64_t old_tpr = hw_stats->tpr;
2494
2495         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2496         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2497
2498         if (crc_strip == 0)
2499                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2500
2501         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2502         hw_stats->gptc += delta_gptc;
2503         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2504         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2505
2506         /*
2507          * Workaround: mprc hardware is incorrectly counting
2508          * broadcasts, so for now we subtract those.
2509          */
2510         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2511         hw_stats->bprc += bprc;
2512         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2513         if (hw->mac.type == ixgbe_mac_82598EB)
2514                 hw_stats->mprc -= bprc;
2515
2516         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2517         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2518         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2519         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2520         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2521         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2522
2523         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2524         hw_stats->lxontxc += lxon;
2525         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2526         hw_stats->lxofftxc += lxoff;
2527         total = lxon + lxoff;
2528
2529         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2530         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2531         hw_stats->gptc -= total;
2532         hw_stats->mptc -= total;
2533         hw_stats->ptc64 -= total;
2534         hw_stats->gotc -= total * ETHER_MIN_LEN;
2535
2536         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2537         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2538         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2539         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2540         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2541         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2542         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2543         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2544         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2545         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2546         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2547         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2548         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2549         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2550         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2551         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2552         /* Only read FCOE on 82599 */
2553         if (hw->mac.type != ixgbe_mac_82598EB) {
2554                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2555                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2556                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2557                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2558                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2559         }
2560
2561         /* Flow Director Stats registers */
2562         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2563         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2564 }
2565
2566 /*
2567  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2568  */
2569 static void
2570 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2571 {
2572         struct ixgbe_hw *hw =
2573                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2574         struct ixgbe_hw_stats *hw_stats =
2575                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2576         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2577         unsigned i;
2578
2579         total_missed_rx = 0;
2580         total_qbrc = 0;
2581         total_qprc = 0;
2582         total_qprdc = 0;
2583
2584         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2585                         &total_qprc, &total_qprdc);
2586
2587         if (stats == NULL)
2588                 return;
2589
2590         /* Fill out the rte_eth_stats statistics structure */
2591         stats->ipackets = total_qprc;
2592         stats->ibytes = total_qbrc;
2593         stats->opackets = hw_stats->gptc;
2594         stats->obytes = hw_stats->gotc;
2595
2596         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2597                 stats->q_ipackets[i] = hw_stats->qprc[i];
2598                 stats->q_opackets[i] = hw_stats->qptc[i];
2599                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2600                 stats->q_obytes[i] = hw_stats->qbtc[i];
2601                 stats->q_errors[i] = hw_stats->qprdc[i];
2602         }
2603
2604         /* Rx Errors */
2605         stats->imissed  = total_missed_rx;
2606         stats->ierrors  = hw_stats->crcerrs +
2607                           hw_stats->mspdc +
2608                           hw_stats->rlec +
2609                           hw_stats->ruc +
2610                           hw_stats->roc +
2611                           total_missed_rx +
2612                           hw_stats->illerrc +
2613                           hw_stats->errbc +
2614                           hw_stats->rfc +
2615                           hw_stats->fccrc +
2616                           hw_stats->fclast;
2617
2618         /* Tx Errors */
2619         stats->oerrors  = 0;
2620 }
2621
2622 static void
2623 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2624 {
2625         struct ixgbe_hw_stats *stats =
2626                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2627
2628         /* HW registers are cleared on read */
2629         ixgbe_dev_stats_get(dev, NULL);
2630
2631         /* Reset software totals */
2632         memset(stats, 0, sizeof(*stats));
2633 }
2634
2635 /* This function calculates the number of xstats based on the current config */
2636 static unsigned
2637 ixgbe_xstats_calc_num(void) {
2638         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2639                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2640 }
2641
2642 static int
2643 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2644                                          unsigned n)
2645 {
2646         struct ixgbe_hw *hw =
2647                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2648         struct ixgbe_hw_stats *hw_stats =
2649                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2650         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2651         unsigned i, stat, count = 0;
2652
2653         count = ixgbe_xstats_calc_num();
2654
2655         if (n < count)
2656                 return count;
2657
2658         total_missed_rx = 0;
2659         total_qbrc = 0;
2660         total_qprc = 0;
2661         total_qprdc = 0;
2662
2663         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2664                                    &total_qprc, &total_qprdc);
2665
2666         /* If this is a reset xstats is NULL, and we have cleared the
2667          * registers by reading them.
2668          */
2669         if (!xstats)
2670                 return 0;
2671
2672         /* Extended stats from ixgbe_hw_stats */
2673         count = 0;
2674         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2675                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2676                          rte_ixgbe_stats_strings[i].name);
2677                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2678                                 rte_ixgbe_stats_strings[i].offset);
2679                 count++;
2680         }
2681
2682         /* RX Priority Stats */
2683         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2684                 for (i = 0; i < 8; i++) {
2685                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2686                                  "rx_priority%u_%s", i,
2687                                  rte_ixgbe_rxq_strings[stat].name);
2688                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2689                                         rte_ixgbe_rxq_strings[stat].offset +
2690                                         (sizeof(uint64_t) * i));
2691                         count++;
2692                 }
2693         }
2694
2695         /* TX Priority Stats */
2696         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2697                 for (i = 0; i < 8; i++) {
2698                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2699                                  "tx_priority%u_%s", i,
2700                                  rte_ixgbe_txq_strings[stat].name);
2701                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2702                                         rte_ixgbe_txq_strings[stat].offset +
2703                                         (sizeof(uint64_t) * i));
2704                         count++;
2705                 }
2706         }
2707
2708         return count;
2709 }
2710
2711 static void
2712 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2713 {
2714         struct ixgbe_hw_stats *stats =
2715                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2716
2717         unsigned count = ixgbe_xstats_calc_num();
2718
2719         /* HW registers are cleared on read */
2720         ixgbe_dev_xstats_get(dev, NULL, count);
2721
2722         /* Reset software totals */
2723         memset(stats, 0, sizeof(*stats));
2724 }
2725
2726 static void
2727 ixgbevf_update_stats(struct rte_eth_dev *dev)
2728 {
2729         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2730         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2731                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2732
2733         /* Good Rx packet, include VF loopback */
2734         UPDATE_VF_STAT(IXGBE_VFGPRC,
2735             hw_stats->last_vfgprc, hw_stats->vfgprc);
2736
2737         /* Good Rx octets, include VF loopback */
2738         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2739             hw_stats->last_vfgorc, hw_stats->vfgorc);
2740
2741         /* Good Tx packet, include VF loopback */
2742         UPDATE_VF_STAT(IXGBE_VFGPTC,
2743             hw_stats->last_vfgptc, hw_stats->vfgptc);
2744
2745         /* Good Tx octets, include VF loopback */
2746         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2747             hw_stats->last_vfgotc, hw_stats->vfgotc);
2748
2749         /* Rx Multicst Packet */
2750         UPDATE_VF_STAT(IXGBE_VFMPRC,
2751             hw_stats->last_vfmprc, hw_stats->vfmprc);
2752 }
2753
2754 static int
2755 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2756                        unsigned n)
2757 {
2758         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2759                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2760         unsigned i;
2761
2762         if (n < IXGBEVF_NB_XSTATS)
2763                 return IXGBEVF_NB_XSTATS;
2764
2765         ixgbevf_update_stats(dev);
2766
2767         if (!xstats)
2768                 return 0;
2769
2770         /* Extended stats */
2771         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2772                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2773                          "%s", rte_ixgbevf_stats_strings[i].name);
2774                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2775                         rte_ixgbevf_stats_strings[i].offset);
2776         }
2777
2778         return IXGBEVF_NB_XSTATS;
2779 }
2780
2781 static void
2782 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2783 {
2784         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2785                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2786
2787         ixgbevf_update_stats(dev);
2788
2789         if (stats == NULL)
2790                 return;
2791
2792         stats->ipackets = hw_stats->vfgprc;
2793         stats->ibytes = hw_stats->vfgorc;
2794         stats->opackets = hw_stats->vfgptc;
2795         stats->obytes = hw_stats->vfgotc;
2796         stats->imcasts = hw_stats->vfmprc;
2797         /* stats->imcasts should be removed as imcasts is deprecated */
2798 }
2799
2800 static void
2801 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2802 {
2803         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2804                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2805
2806         /* Sync HW register to the last stats */
2807         ixgbevf_dev_stats_get(dev, NULL);
2808
2809         /* reset HW current stats*/
2810         hw_stats->vfgprc = 0;
2811         hw_stats->vfgorc = 0;
2812         hw_stats->vfgptc = 0;
2813         hw_stats->vfgotc = 0;
2814         hw_stats->vfmprc = 0;
2815
2816 }
2817
2818 static void
2819 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2820 {
2821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822
2823         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2824         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2825         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2826         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2827         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2828         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2829         dev_info->max_vfs = dev->pci_dev->max_vfs;
2830         if (hw->mac.type == ixgbe_mac_82598EB)
2831                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2832         else
2833                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2834         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2835         dev_info->rx_offload_capa =
2836                 DEV_RX_OFFLOAD_VLAN_STRIP |
2837                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2838                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2839                 DEV_RX_OFFLOAD_TCP_CKSUM;
2840
2841         /*
2842          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2843          * mode.
2844          */
2845         if ((hw->mac.type == ixgbe_mac_82599EB ||
2846              hw->mac.type == ixgbe_mac_X540) &&
2847             !RTE_ETH_DEV_SRIOV(dev).active)
2848                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2849
2850         if (hw->mac.type == ixgbe_mac_X550 ||
2851             hw->mac.type == ixgbe_mac_X550EM_x)
2852                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2853
2854         dev_info->tx_offload_capa =
2855                 DEV_TX_OFFLOAD_VLAN_INSERT |
2856                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2857                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2858                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2859                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2860                 DEV_TX_OFFLOAD_TCP_TSO;
2861
2862         if (hw->mac.type == ixgbe_mac_X550 ||
2863             hw->mac.type == ixgbe_mac_X550EM_x)
2864                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2865
2866         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2867                 .rx_thresh = {
2868                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2869                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2870                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2871                 },
2872                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2873                 .rx_drop_en = 0,
2874         };
2875
2876         dev_info->default_txconf = (struct rte_eth_txconf) {
2877                 .tx_thresh = {
2878                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2879                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2880                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2881                 },
2882                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2883                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2884                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2885                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2886         };
2887
2888         dev_info->rx_desc_lim = rx_desc_lim;
2889         dev_info->tx_desc_lim = tx_desc_lim;
2890
2891         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2892         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2893         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2894 }
2895
2896 static void
2897 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2898                      struct rte_eth_dev_info *dev_info)
2899 {
2900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2901
2902         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2903         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2904         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2905         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2906         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2907         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2908         dev_info->max_vfs = dev->pci_dev->max_vfs;
2909         if (hw->mac.type == ixgbe_mac_82598EB)
2910                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2911         else
2912                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2913         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2914                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2915                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2916                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2917         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2918                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2919                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2920                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2921                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2922                                 DEV_TX_OFFLOAD_TCP_TSO;
2923
2924         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2925                 .rx_thresh = {
2926                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2927                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2928                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2929                 },
2930                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2931                 .rx_drop_en = 0,
2932         };
2933
2934         dev_info->default_txconf = (struct rte_eth_txconf) {
2935                 .tx_thresh = {
2936                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2937                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2938                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2939                 },
2940                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2941                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2942                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2943                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2944         };
2945
2946         dev_info->rx_desc_lim = rx_desc_lim;
2947         dev_info->tx_desc_lim = tx_desc_lim;
2948 }
2949
2950 /* return 0 means link status changed, -1 means not changed */
2951 static int
2952 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2953 {
2954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955         struct rte_eth_link link, old;
2956         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2957         int link_up;
2958         int diag;
2959
2960         link.link_status = 0;
2961         link.link_speed = 0;
2962         link.link_duplex = 0;
2963         memset(&old, 0, sizeof(old));
2964         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2965
2966         hw->mac.get_link_status = true;
2967
2968         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2969         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2970                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2971         else
2972                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2973
2974         if (diag != 0) {
2975                 link.link_speed = ETH_LINK_SPEED_100;
2976                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2977                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2978                 if (link.link_status == old.link_status)
2979                         return -1;
2980                 return 0;
2981         }
2982
2983         if (link_up == 0) {
2984                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2985                 if (link.link_status == old.link_status)
2986                         return -1;
2987                 return 0;
2988         }
2989         link.link_status = 1;
2990         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2991
2992         switch (link_speed) {
2993         default:
2994         case IXGBE_LINK_SPEED_UNKNOWN:
2995                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2996                 link.link_speed = ETH_LINK_SPEED_100;
2997                 break;
2998
2999         case IXGBE_LINK_SPEED_100_FULL:
3000                 link.link_speed = ETH_LINK_SPEED_100;
3001                 break;
3002
3003         case IXGBE_LINK_SPEED_1GB_FULL:
3004                 link.link_speed = ETH_LINK_SPEED_1000;
3005                 break;
3006
3007         case IXGBE_LINK_SPEED_10GB_FULL:
3008                 link.link_speed = ETH_LINK_SPEED_10000;
3009                 break;
3010         }
3011         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3012
3013         if (link.link_status == old.link_status)
3014                 return -1;
3015
3016         return 0;
3017 }
3018
3019 static void
3020 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3021 {
3022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3023         uint32_t fctrl;
3024
3025         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3026         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3027         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3028 }
3029
3030 static void
3031 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3032 {
3033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3034         uint32_t fctrl;
3035
3036         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3037         fctrl &= (~IXGBE_FCTRL_UPE);
3038         if (dev->data->all_multicast == 1)
3039                 fctrl |= IXGBE_FCTRL_MPE;
3040         else
3041                 fctrl &= (~IXGBE_FCTRL_MPE);
3042         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3043 }
3044
3045 static void
3046 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3047 {
3048         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3049         uint32_t fctrl;
3050
3051         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3052         fctrl |= IXGBE_FCTRL_MPE;
3053         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3054 }
3055
3056 static void
3057 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3058 {
3059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3060         uint32_t fctrl;
3061
3062         if (dev->data->promiscuous == 1)
3063                 return; /* must remain in all_multicast mode */
3064
3065         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3066         fctrl &= (~IXGBE_FCTRL_MPE);
3067         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3068 }
3069
3070 /**
3071  * It clears the interrupt causes and enables the interrupt.
3072  * It will be called once only during nic initialized.
3073  *
3074  * @param dev
3075  *  Pointer to struct rte_eth_dev.
3076  *
3077  * @return
3078  *  - On success, zero.
3079  *  - On failure, a negative value.
3080  */
3081 static int
3082 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3083 {
3084         struct ixgbe_interrupt *intr =
3085                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3086
3087         ixgbe_dev_link_status_print(dev);
3088         intr->mask |= IXGBE_EICR_LSC;
3089
3090         return 0;
3091 }
3092
3093 /**
3094  * It clears the interrupt causes and enables the interrupt.
3095  * It will be called once only during nic initialized.
3096  *
3097  * @param dev
3098  *  Pointer to struct rte_eth_dev.
3099  *
3100  * @return
3101  *  - On success, zero.
3102  *  - On failure, a negative value.
3103  */
3104 static int
3105 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3106 {
3107         struct ixgbe_interrupt *intr =
3108                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3109
3110         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3111
3112         return 0;
3113 }
3114
3115 /*
3116  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3117  *
3118  * @param dev
3119  *  Pointer to struct rte_eth_dev.
3120  *
3121  * @return
3122  *  - On success, zero.
3123  *  - On failure, a negative value.
3124  */
3125 static int
3126 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3127 {
3128         uint32_t eicr;
3129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3130         struct ixgbe_interrupt *intr =
3131                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3132
3133         /* clear all cause mask */
3134         ixgbe_disable_intr(hw);
3135
3136         /* read-on-clear nic registers here */
3137         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3138         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3139
3140         intr->flags = 0;
3141
3142         /* set flag for async link update */
3143         if (eicr & IXGBE_EICR_LSC)
3144                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3145
3146         if (eicr & IXGBE_EICR_MAILBOX)
3147                 intr->flags |= IXGBE_FLAG_MAILBOX;
3148
3149         return 0;
3150 }
3151
3152 /**
3153  * It gets and then prints the link status.
3154  *
3155  * @param dev
3156  *  Pointer to struct rte_eth_dev.
3157  *
3158  * @return
3159  *  - On success, zero.
3160  *  - On failure, a negative value.
3161  */
3162 static void
3163 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3164 {
3165         struct rte_eth_link link;
3166
3167         memset(&link, 0, sizeof(link));
3168         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3169         if (link.link_status) {
3170                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3171                                         (int)(dev->data->port_id),
3172                                         (unsigned)link.link_speed,
3173                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3174                                         "full-duplex" : "half-duplex");
3175         } else {
3176                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3177                                 (int)(dev->data->port_id));
3178         }
3179         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3180                                 dev->pci_dev->addr.domain,
3181                                 dev->pci_dev->addr.bus,
3182                                 dev->pci_dev->addr.devid,
3183                                 dev->pci_dev->addr.function);
3184 }
3185
3186 /*
3187  * It executes link_update after knowing an interrupt occurred.
3188  *
3189  * @param dev
3190  *  Pointer to struct rte_eth_dev.
3191  *
3192  * @return
3193  *  - On success, zero.
3194  *  - On failure, a negative value.
3195  */
3196 static int
3197 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3198 {
3199         struct ixgbe_interrupt *intr =
3200                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3201         int64_t timeout;
3202         struct rte_eth_link link;
3203         int intr_enable_delay = false;
3204
3205         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3206
3207         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3208                 ixgbe_pf_mbx_process(dev);
3209                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3210         }
3211
3212         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3213                 /* get the link status before link update, for predicting later */
3214                 memset(&link, 0, sizeof(link));
3215                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3216
3217                 ixgbe_dev_link_update(dev, 0);
3218
3219                 /* likely to up */
3220                 if (!link.link_status)
3221                         /* handle it 1 sec later, wait it being stable */
3222                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3223                 /* likely to down */
3224                 else
3225                         /* handle it 4 sec later, wait it being stable */
3226                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3227
3228                 ixgbe_dev_link_status_print(dev);
3229
3230                 intr_enable_delay = true;
3231         }
3232
3233         if (intr_enable_delay) {
3234                 if (rte_eal_alarm_set(timeout * 1000,
3235                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3236                         PMD_DRV_LOG(ERR, "Error setting alarm");
3237         } else {
3238                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3239                 ixgbe_enable_intr(dev);
3240                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3241         }
3242
3243
3244         return 0;
3245 }
3246
3247 /**
3248  * Interrupt handler which shall be registered for alarm callback for delayed
3249  * handling specific interrupt to wait for the stable nic state. As the
3250  * NIC interrupt state is not stable for ixgbe after link is just down,
3251  * it needs to wait 4 seconds to get the stable status.
3252  *
3253  * @param handle
3254  *  Pointer to interrupt handle.
3255  * @param param
3256  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3257  *
3258  * @return
3259  *  void
3260  */
3261 static void
3262 ixgbe_dev_interrupt_delayed_handler(void *param)
3263 {
3264         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3265         struct ixgbe_interrupt *intr =
3266                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3267         struct ixgbe_hw *hw =
3268                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269         uint32_t eicr;
3270
3271         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3272         if (eicr & IXGBE_EICR_MAILBOX)
3273                 ixgbe_pf_mbx_process(dev);
3274
3275         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3276                 ixgbe_dev_link_update(dev, 0);
3277                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3278                 ixgbe_dev_link_status_print(dev);
3279                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3280         }
3281
3282         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3283         ixgbe_enable_intr(dev);
3284         rte_intr_enable(&(dev->pci_dev->intr_handle));
3285 }
3286
3287 /**
3288  * Interrupt handler triggered by NIC  for handling
3289  * specific interrupt.
3290  *
3291  * @param handle
3292  *  Pointer to interrupt handle.
3293  * @param param
3294  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3295  *
3296  * @return
3297  *  void
3298  */
3299 static void
3300 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3301                             void *param)
3302 {
3303         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3304
3305         ixgbe_dev_interrupt_get_status(dev);
3306         ixgbe_dev_interrupt_action(dev);
3307 }
3308
3309 static int
3310 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3311 {
3312         struct ixgbe_hw *hw;
3313
3314         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3315         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3316 }
3317
3318 static int
3319 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3320 {
3321         struct ixgbe_hw *hw;
3322
3323         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3324         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3325 }
3326
3327 static int
3328 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3329 {
3330         struct ixgbe_hw *hw;
3331         uint32_t mflcn_reg;
3332         uint32_t fccfg_reg;
3333         int rx_pause;
3334         int tx_pause;
3335
3336         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337
3338         fc_conf->pause_time = hw->fc.pause_time;
3339         fc_conf->high_water = hw->fc.high_water[0];
3340         fc_conf->low_water = hw->fc.low_water[0];
3341         fc_conf->send_xon = hw->fc.send_xon;
3342         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3343
3344         /*
3345          * Return rx_pause status according to actual setting of
3346          * MFLCN register.
3347          */
3348         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3349         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3350                 rx_pause = 1;
3351         else
3352                 rx_pause = 0;
3353
3354         /*
3355          * Return tx_pause status according to actual setting of
3356          * FCCFG register.
3357          */
3358         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3359         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3360                 tx_pause = 1;
3361         else
3362                 tx_pause = 0;
3363
3364         if (rx_pause && tx_pause)
3365                 fc_conf->mode = RTE_FC_FULL;
3366         else if (rx_pause)
3367                 fc_conf->mode = RTE_FC_RX_PAUSE;
3368         else if (tx_pause)
3369                 fc_conf->mode = RTE_FC_TX_PAUSE;
3370         else
3371                 fc_conf->mode = RTE_FC_NONE;
3372
3373         return 0;
3374 }
3375
3376 static int
3377 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3378 {
3379         struct ixgbe_hw *hw;
3380         int err;
3381         uint32_t rx_buf_size;
3382         uint32_t max_high_water;
3383         uint32_t mflcn;
3384         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3385                 ixgbe_fc_none,
3386                 ixgbe_fc_rx_pause,
3387                 ixgbe_fc_tx_pause,
3388                 ixgbe_fc_full
3389         };
3390
3391         PMD_INIT_FUNC_TRACE();
3392
3393         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3394         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3395         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3396
3397         /*
3398          * At least reserve one Ethernet frame for watermark
3399          * high_water/low_water in kilo bytes for ixgbe
3400          */
3401         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3402         if ((fc_conf->high_water > max_high_water) ||
3403                 (fc_conf->high_water < fc_conf->low_water)) {
3404                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3405                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3406                 return -EINVAL;
3407         }
3408
3409         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3410         hw->fc.pause_time     = fc_conf->pause_time;
3411         hw->fc.high_water[0]  = fc_conf->high_water;
3412         hw->fc.low_water[0]   = fc_conf->low_water;
3413         hw->fc.send_xon       = fc_conf->send_xon;
3414         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3415
3416         err = ixgbe_fc_enable(hw);
3417
3418         /* Not negotiated is not an error case */
3419         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3420
3421                 /* check if we want to forward MAC frames - driver doesn't have native
3422                  * capability to do that, so we'll write the registers ourselves */
3423
3424                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3425
3426                 /* set or clear MFLCN.PMCF bit depending on configuration */
3427                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3428                         mflcn |= IXGBE_MFLCN_PMCF;
3429                 else
3430                         mflcn &= ~IXGBE_MFLCN_PMCF;
3431
3432                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3433                 IXGBE_WRITE_FLUSH(hw);
3434
3435                 return 0;
3436         }
3437
3438         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3439         return -EIO;
3440 }
3441
3442 /**
3443  *  ixgbe_pfc_enable_generic - Enable flow control
3444  *  @hw: pointer to hardware structure
3445  *  @tc_num: traffic class number
3446  *  Enable flow control according to the current settings.
3447  */
3448 static int
3449 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3450 {
3451         int ret_val = 0;
3452         uint32_t mflcn_reg, fccfg_reg;
3453         uint32_t reg;
3454         uint32_t fcrtl, fcrth;
3455         uint8_t i;
3456         uint8_t nb_rx_en;
3457
3458         /* Validate the water mark configuration */
3459         if (!hw->fc.pause_time) {
3460                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3461                 goto out;
3462         }
3463
3464         /* Low water mark of zero causes XOFF floods */
3465         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3466                  /* High/Low water can not be 0 */
3467                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3468                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3469                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3470                         goto out;
3471                 }
3472
3473                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3474                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3475                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3476                         goto out;
3477                 }
3478         }
3479         /* Negotiate the fc mode to use */
3480         ixgbe_fc_autoneg(hw);
3481
3482         /* Disable any previous flow control settings */
3483         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3484         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3485
3486         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3487         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3488
3489         switch (hw->fc.current_mode) {
3490         case ixgbe_fc_none:
3491                 /*
3492                  * If the count of enabled RX Priority Flow control >1,
3493                  * and the TX pause can not be disabled
3494                  */
3495                 nb_rx_en = 0;
3496                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3497                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3498                         if (reg & IXGBE_FCRTH_FCEN)
3499                                 nb_rx_en++;
3500                 }
3501                 if (nb_rx_en > 1)
3502                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3503                 break;
3504         case ixgbe_fc_rx_pause:
3505                 /*
3506                  * Rx Flow control is enabled and Tx Flow control is
3507                  * disabled by software override. Since there really
3508                  * isn't a way to advertise that we are capable of RX
3509                  * Pause ONLY, we will advertise that we support both
3510                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3511                  * disable the adapter's ability to send PAUSE frames.
3512                  */
3513                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3514                 /*
3515                  * If the count of enabled RX Priority Flow control >1,
3516                  * and the TX pause can not be disabled
3517                  */
3518                 nb_rx_en = 0;
3519                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3520                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3521                         if (reg & IXGBE_FCRTH_FCEN)
3522                                 nb_rx_en++;
3523                 }
3524                 if (nb_rx_en > 1)
3525                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3526                 break;
3527         case ixgbe_fc_tx_pause:
3528                 /*
3529                  * Tx Flow control is enabled, and Rx Flow control is
3530                  * disabled by software override.
3531                  */
3532                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3533                 break;
3534         case ixgbe_fc_full:
3535                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3536                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3537                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3538                 break;
3539         default:
3540                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3541                 ret_val = IXGBE_ERR_CONFIG;
3542                 goto out;
3543                 break;
3544         }
3545
3546         /* Set 802.3x based flow control settings. */
3547         mflcn_reg |= IXGBE_MFLCN_DPF;
3548         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3549         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3550
3551         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3552         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3553                 hw->fc.high_water[tc_num]) {
3554                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3555                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3556                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3557         } else {
3558                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3559                 /*
3560                  * In order to prevent Tx hangs when the internal Tx
3561                  * switch is enabled we must set the high water mark
3562                  * to the maximum FCRTH value.  This allows the Tx
3563                  * switch to function even under heavy Rx workloads.
3564                  */
3565                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3566         }
3567         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3568
3569         /* Configure pause time (2 TCs per register) */
3570         reg = hw->fc.pause_time * 0x00010001;
3571         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3572                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3573
3574         /* Configure flow control refresh threshold value */
3575         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3576
3577 out:
3578         return ret_val;
3579 }
3580
3581 static int
3582 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3583 {
3584         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3585         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3586
3587         if (hw->mac.type != ixgbe_mac_82598EB) {
3588                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3589         }
3590         return ret_val;
3591 }
3592
3593 static int
3594 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3595 {
3596         int err;
3597         uint32_t rx_buf_size;
3598         uint32_t max_high_water;
3599         uint8_t tc_num;
3600         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3601         struct ixgbe_hw *hw =
3602                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3603         struct ixgbe_dcb_config *dcb_config =
3604                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3605
3606         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3607                 ixgbe_fc_none,
3608                 ixgbe_fc_rx_pause,
3609                 ixgbe_fc_tx_pause,
3610                 ixgbe_fc_full
3611         };
3612
3613         PMD_INIT_FUNC_TRACE();
3614
3615         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3616         tc_num = map[pfc_conf->priority];
3617         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3618         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3619         /*
3620          * At least reserve one Ethernet frame for watermark
3621          * high_water/low_water in kilo bytes for ixgbe
3622          */
3623         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3624         if ((pfc_conf->fc.high_water > max_high_water) ||
3625             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3626                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3627                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3628                 return -EINVAL;
3629         }
3630
3631         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3632         hw->fc.pause_time = pfc_conf->fc.pause_time;
3633         hw->fc.send_xon = pfc_conf->fc.send_xon;
3634         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3635         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3636
3637         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3638
3639         /* Not negotiated is not an error case */
3640         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3641                 return 0;
3642
3643         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3644         return -EIO;
3645 }
3646
3647 static int
3648 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3649                           struct rte_eth_rss_reta_entry64 *reta_conf,
3650                           uint16_t reta_size)
3651 {
3652         uint8_t i, j, mask;
3653         uint32_t reta, r;
3654         uint16_t idx, shift;
3655         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3656         uint16_t sp_reta_size;
3657         uint32_t reta_reg;
3658
3659         PMD_INIT_FUNC_TRACE();
3660
3661         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3662                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3663                         "NIC.");
3664                 return -ENOTSUP;
3665         }
3666
3667         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3668         if (reta_size != sp_reta_size) {
3669                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3670                         "(%d) doesn't match the number hardware can supported "
3671                         "(%d)\n", reta_size, sp_reta_size);
3672                 return -EINVAL;
3673         }
3674
3675         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3676                 idx = i / RTE_RETA_GROUP_SIZE;
3677                 shift = i % RTE_RETA_GROUP_SIZE;
3678                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3679                                                 IXGBE_4_BIT_MASK);
3680                 if (!mask)
3681                         continue;
3682                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3683                 if (mask == IXGBE_4_BIT_MASK)
3684                         r = 0;
3685                 else
3686                         r = IXGBE_READ_REG(hw, reta_reg);
3687                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3688                         if (mask & (0x1 << j))
3689                                 reta |= reta_conf[idx].reta[shift + j] <<
3690                                                         (CHAR_BIT * j);
3691                         else
3692                                 reta |= r & (IXGBE_8_BIT_MASK <<
3693                                                 (CHAR_BIT * j));
3694                 }
3695                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3696         }
3697
3698         return 0;
3699 }
3700
3701 static int
3702 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3703                          struct rte_eth_rss_reta_entry64 *reta_conf,
3704                          uint16_t reta_size)
3705 {
3706         uint8_t i, j, mask;
3707         uint32_t reta;
3708         uint16_t idx, shift;
3709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710         uint16_t sp_reta_size;
3711         uint32_t reta_reg;
3712
3713         PMD_INIT_FUNC_TRACE();
3714         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3715         if (reta_size != sp_reta_size) {
3716                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3717                         "(%d) doesn't match the number hardware can supported "
3718                         "(%d)\n", reta_size, sp_reta_size);
3719                 return -EINVAL;
3720         }
3721
3722         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3723                 idx = i / RTE_RETA_GROUP_SIZE;
3724                 shift = i % RTE_RETA_GROUP_SIZE;
3725                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3726                                                 IXGBE_4_BIT_MASK);
3727                 if (!mask)
3728                         continue;
3729
3730                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3731                 reta = IXGBE_READ_REG(hw, reta_reg);
3732                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3733                         if (mask & (0x1 << j))
3734                                 reta_conf[idx].reta[shift + j] =
3735                                         ((reta >> (CHAR_BIT * j)) &
3736                                                 IXGBE_8_BIT_MASK);
3737                 }
3738         }
3739
3740         return 0;
3741 }
3742
3743 static void
3744 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3745                                 uint32_t index, uint32_t pool)
3746 {
3747         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3748         uint32_t enable_addr = 1;
3749
3750         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3751 }
3752
3753 static void
3754 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3755 {
3756         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3757
3758         ixgbe_clear_rar(hw, index);
3759 }
3760
3761 static void
3762 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3763 {
3764         ixgbe_remove_rar(dev, 0);
3765
3766         ixgbe_add_rar(dev, addr, 0, 0);
3767 }
3768
3769 static int
3770 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3771 {
3772         uint32_t hlreg0;
3773         uint32_t maxfrs;
3774         struct ixgbe_hw *hw;
3775         struct rte_eth_dev_info dev_info;
3776         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3777
3778         ixgbe_dev_info_get(dev, &dev_info);
3779
3780         /* check that mtu is within the allowed range */
3781         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3782                 return -EINVAL;
3783
3784         /* refuse mtu that requires the support of scattered packets when this
3785          * feature has not been enabled before. */
3786         if (!dev->data->scattered_rx &&
3787             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3788              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3789                 return -EINVAL;
3790
3791         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3792         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3793
3794         /* switch to jumbo mode if needed */
3795         if (frame_size > ETHER_MAX_LEN) {
3796                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3797                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3798         } else {
3799                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3800                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3801         }
3802         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3803
3804         /* update max frame size */
3805         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3806
3807         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3808         maxfrs &= 0x0000FFFF;
3809         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3810         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3811
3812         return 0;
3813 }
3814
3815 /*
3816  * Virtual Function operations
3817  */
3818 static void
3819 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3820 {
3821         PMD_INIT_FUNC_TRACE();
3822
3823         /* Clear interrupt mask to stop from interrupts being generated */
3824         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3825
3826         IXGBE_WRITE_FLUSH(hw);
3827 }
3828
3829 static void
3830 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3831 {
3832         PMD_INIT_FUNC_TRACE();
3833
3834         /* VF enable interrupt autoclean */
3835         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3836         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3837         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3838
3839         IXGBE_WRITE_FLUSH(hw);
3840 }
3841
3842 static int
3843 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3844 {
3845         struct rte_eth_conf* conf = &dev->data->dev_conf;
3846         struct ixgbe_adapter *adapter =
3847                         (struct ixgbe_adapter *)dev->data->dev_private;
3848
3849         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3850                      dev->data->port_id);
3851
3852         /*
3853          * VF has no ability to enable/disable HW CRC
3854          * Keep the persistent behavior the same as Host PF
3855          */
3856 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3857         if (!conf->rxmode.hw_strip_crc) {
3858                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3859                 conf->rxmode.hw_strip_crc = 1;
3860         }
3861 #else
3862         if (conf->rxmode.hw_strip_crc) {
3863                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3864                 conf->rxmode.hw_strip_crc = 0;
3865         }
3866 #endif
3867
3868         /*
3869          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3870          * allocation or vector Rx preconditions we will reset it.
3871          */
3872         adapter->rx_bulk_alloc_allowed = true;
3873         adapter->rx_vec_allowed = true;
3874
3875         return 0;
3876 }
3877
3878 static int
3879 ixgbevf_dev_start(struct rte_eth_dev *dev)
3880 {
3881         struct ixgbe_hw *hw =
3882                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3883         uint32_t intr_vector = 0;
3884         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3885
3886         int err, mask = 0;
3887
3888         PMD_INIT_FUNC_TRACE();
3889
3890         hw->mac.ops.reset_hw(hw);
3891         hw->mac.get_link_status = true;
3892
3893         /* negotiate mailbox API version to use with the PF. */
3894         ixgbevf_negotiate_api(hw);
3895
3896         ixgbevf_dev_tx_init(dev);
3897
3898         /* This can fail when allocating mbufs for descriptor rings */
3899         err = ixgbevf_dev_rx_init(dev);
3900         if (err) {
3901                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3902                 ixgbe_dev_clear_queues(dev);
3903                 return err;
3904         }
3905
3906         /* Set vfta */
3907         ixgbevf_set_vfta_all(dev,1);
3908
3909         /* Set HW strip */
3910         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3911                 ETH_VLAN_EXTEND_MASK;
3912         ixgbevf_vlan_offload_set(dev, mask);
3913
3914         ixgbevf_dev_rxtx_start(dev);
3915
3916         /* check and configure queue intr-vector mapping */
3917         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3918                 intr_vector = dev->data->nb_rx_queues;
3919                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3920                         return -1;
3921         }
3922
3923         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3924                 intr_handle->intr_vec =
3925                         rte_zmalloc("intr_vec",
3926                                     dev->data->nb_rx_queues * sizeof(int), 0);
3927                 if (intr_handle->intr_vec == NULL) {
3928                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3929                                      " intr_vec\n", dev->data->nb_rx_queues);
3930                         return -ENOMEM;
3931                 }
3932         }
3933         ixgbevf_configure_msix(dev);
3934
3935         rte_intr_enable(intr_handle);
3936
3937         /* Re-enable interrupt for VF */
3938         ixgbevf_intr_enable(hw);
3939
3940         return 0;
3941 }
3942
3943 static void
3944 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3945 {
3946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3948
3949         PMD_INIT_FUNC_TRACE();
3950
3951         hw->adapter_stopped = 1;
3952         ixgbe_stop_adapter(hw);
3953
3954         /*
3955           * Clear what we set, but we still keep shadow_vfta to
3956           * restore after device starts
3957           */
3958         ixgbevf_set_vfta_all(dev,0);
3959
3960         /* Clear stored conf */
3961         dev->data->scattered_rx = 0;
3962
3963         ixgbe_dev_clear_queues(dev);
3964
3965         /* disable intr eventfd mapping */
3966         rte_intr_disable(intr_handle);
3967
3968         /* Clean datapath event and queue/vec mapping */
3969         rte_intr_efd_disable(intr_handle);
3970         if (intr_handle->intr_vec != NULL) {
3971                 rte_free(intr_handle->intr_vec);
3972                 intr_handle->intr_vec = NULL;
3973         }
3974 }
3975
3976 static void
3977 ixgbevf_dev_close(struct rte_eth_dev *dev)
3978 {
3979         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3980
3981         PMD_INIT_FUNC_TRACE();
3982
3983         ixgbe_reset_hw(hw);
3984
3985         ixgbevf_dev_stop(dev);
3986
3987         ixgbe_dev_free_queues(dev);
3988
3989         /* reprogram the RAR[0] in case user changed it. */
3990         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3991 }
3992
3993 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3994 {
3995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3996         struct ixgbe_vfta * shadow_vfta =
3997                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3998         int i = 0, j = 0, vfta = 0, mask = 1;
3999
4000         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4001                 vfta = shadow_vfta->vfta[i];
4002                 if (vfta) {
4003                         mask = 1;
4004                         for (j = 0; j < 32; j++){
4005                                 if (vfta & mask)
4006                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4007                                 mask<<=1;
4008                         }
4009                 }
4010         }
4011
4012 }
4013
4014 static int
4015 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4016 {
4017         struct ixgbe_hw *hw =
4018                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4019         struct ixgbe_vfta * shadow_vfta =
4020                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4021         uint32_t vid_idx = 0;
4022         uint32_t vid_bit = 0;
4023         int ret = 0;
4024
4025         PMD_INIT_FUNC_TRACE();
4026
4027         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4028         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4029         if (ret) {
4030                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4031                 return ret;
4032         }
4033         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4034         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4035
4036         /* Save what we set and retore it after device reset */
4037         if (on)
4038                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4039         else
4040                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4041
4042         return 0;
4043 }
4044
4045 static void
4046 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4047 {
4048         struct ixgbe_hw *hw =
4049                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4050         uint32_t ctrl;
4051
4052         PMD_INIT_FUNC_TRACE();
4053
4054         if (queue >= hw->mac.max_rx_queues)
4055                 return;
4056
4057         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4058         if (on)
4059                 ctrl |= IXGBE_RXDCTL_VME;
4060         else
4061                 ctrl &= ~IXGBE_RXDCTL_VME;
4062         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4063
4064         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4065 }
4066
4067 static void
4068 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4069 {
4070         struct ixgbe_hw *hw =
4071                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4072         uint16_t i;
4073         int on = 0;
4074
4075         /* VF function only support hw strip feature, others are not support */
4076         if (mask & ETH_VLAN_STRIP_MASK) {
4077                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4078
4079                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4080                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4081         }
4082 }
4083
4084 static int
4085 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4086 {
4087         uint32_t reg_val;
4088
4089         /* we only need to do this if VMDq is enabled */
4090         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4091         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4092                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4093                 return -1;
4094         }
4095
4096         return 0;
4097 }
4098
4099 static uint32_t
4100 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4101 {
4102         uint32_t vector = 0;
4103         switch (hw->mac.mc_filter_type) {
4104         case 0:   /* use bits [47:36] of the address */
4105                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4106                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4107                 break;
4108         case 1:   /* use bits [46:35] of the address */
4109                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4110                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4111                 break;
4112         case 2:   /* use bits [45:34] of the address */
4113                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4114                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4115                 break;
4116         case 3:   /* use bits [43:32] of the address */
4117                 vector = ((uc_addr->addr_bytes[4]) |
4118                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4119                 break;
4120         default:  /* Invalid mc_filter_type */
4121                 break;
4122         }
4123
4124         /* vector can only be 12-bits or boundary will be exceeded */
4125         vector &= 0xFFF;
4126         return vector;
4127 }
4128
4129 static int
4130 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4131                                uint8_t on)
4132 {
4133         uint32_t vector;
4134         uint32_t uta_idx;
4135         uint32_t reg_val;
4136         uint32_t uta_shift;
4137         uint32_t rc;
4138         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4139         const uint32_t ixgbe_uta_bit_shift = 5;
4140         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4141         const uint32_t bit1 = 0x1;
4142
4143         struct ixgbe_hw *hw =
4144                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4145         struct ixgbe_uta_info *uta_info =
4146                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4147
4148         /* The UTA table only exists on 82599 hardware and newer */
4149         if (hw->mac.type < ixgbe_mac_82599EB)
4150                 return -ENOTSUP;
4151
4152         vector = ixgbe_uta_vector(hw,mac_addr);
4153         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4154         uta_shift = vector & ixgbe_uta_bit_mask;
4155
4156         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4157         if (rc == on)
4158                 return 0;
4159
4160         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4161         if (on) {
4162                 uta_info->uta_in_use++;
4163                 reg_val |= (bit1 << uta_shift);
4164                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4165         } else {
4166                 uta_info->uta_in_use--;
4167                 reg_val &= ~(bit1 << uta_shift);
4168                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4169         }
4170
4171         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4172
4173         if (uta_info->uta_in_use > 0)
4174                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4175                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4176         else
4177                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4178
4179         return 0;
4180 }
4181
4182 static int
4183 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4184 {
4185         int i;
4186         struct ixgbe_hw *hw =
4187                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188         struct ixgbe_uta_info *uta_info =
4189                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4190
4191         /* The UTA table only exists on 82599 hardware and newer */
4192         if (hw->mac.type < ixgbe_mac_82599EB)
4193                 return -ENOTSUP;
4194
4195         if (on) {
4196                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4197                         uta_info->uta_shadow[i] = ~0;
4198                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4199                 }
4200         } else {
4201                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4202                         uta_info->uta_shadow[i] = 0;
4203                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4204                 }
4205         }
4206         return 0;
4207
4208 }
4209
4210 uint32_t
4211 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4212 {
4213         uint32_t new_val = orig_val;
4214
4215         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4216                 new_val |= IXGBE_VMOLR_AUPE;
4217         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4218                 new_val |= IXGBE_VMOLR_ROMPE;
4219         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4220                 new_val |= IXGBE_VMOLR_ROPE;
4221         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4222                 new_val |= IXGBE_VMOLR_BAM;
4223         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4224                 new_val |= IXGBE_VMOLR_MPE;
4225
4226         return new_val;
4227 }
4228
4229 static int
4230 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4231                                uint16_t rx_mask, uint8_t on)
4232 {
4233         int val = 0;
4234
4235         struct ixgbe_hw *hw =
4236                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4237         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4238
4239         if (hw->mac.type == ixgbe_mac_82598EB) {
4240                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4241                              " on 82599 hardware and newer");
4242                 return -ENOTSUP;
4243         }
4244         if (ixgbe_vmdq_mode_check(hw) < 0)
4245                 return -ENOTSUP;
4246
4247         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4248
4249         if (on)
4250                 vmolr |= val;
4251         else
4252                 vmolr &= ~val;
4253
4254         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4255
4256         return 0;
4257 }
4258
4259 static int
4260 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4261 {
4262         uint32_t reg,addr;
4263         uint32_t val;
4264         const uint8_t bit1 = 0x1;
4265
4266         struct ixgbe_hw *hw =
4267                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4268
4269         if (ixgbe_vmdq_mode_check(hw) < 0)
4270                 return -ENOTSUP;
4271
4272         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4273         reg = IXGBE_READ_REG(hw, addr);
4274         val = bit1 << pool;
4275
4276         if (on)
4277                 reg |= val;
4278         else
4279                 reg &= ~val;
4280
4281         IXGBE_WRITE_REG(hw, addr,reg);
4282
4283         return 0;
4284 }
4285
4286 static int
4287 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4288 {
4289         uint32_t reg,addr;
4290         uint32_t val;
4291         const uint8_t bit1 = 0x1;
4292
4293         struct ixgbe_hw *hw =
4294                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4295
4296         if (ixgbe_vmdq_mode_check(hw) < 0)
4297                 return -ENOTSUP;
4298
4299         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4300         reg = IXGBE_READ_REG(hw, addr);
4301         val = bit1 << pool;
4302
4303         if (on)
4304                 reg |= val;
4305         else
4306                 reg &= ~val;
4307
4308         IXGBE_WRITE_REG(hw, addr,reg);
4309
4310         return 0;
4311 }
4312
4313 static int
4314 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4315                         uint64_t pool_mask, uint8_t vlan_on)
4316 {
4317         int ret = 0;
4318         uint16_t pool_idx;
4319         struct ixgbe_hw *hw =
4320                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4321
4322         if (ixgbe_vmdq_mode_check(hw) < 0)
4323                 return -ENOTSUP;
4324         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4325                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4326                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4327                         if (ret < 0)
4328                                 return ret;
4329         }
4330
4331         return ret;
4332 }
4333
4334 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4335 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4336 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4337 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4338 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4339         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4340         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4341
4342 static int
4343 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4344                         struct rte_eth_mirror_conf *mirror_conf,
4345                         uint8_t rule_id, uint8_t on)
4346 {
4347         uint32_t mr_ctl,vlvf;
4348         uint32_t mp_lsb = 0;
4349         uint32_t mv_msb = 0;
4350         uint32_t mv_lsb = 0;
4351         uint32_t mp_msb = 0;
4352         uint8_t i = 0;
4353         int reg_index = 0;
4354         uint64_t vlan_mask = 0;
4355
4356         const uint8_t pool_mask_offset = 32;
4357         const uint8_t vlan_mask_offset = 32;
4358         const uint8_t dst_pool_offset = 8;
4359         const uint8_t rule_mr_offset  = 4;
4360         const uint8_t mirror_rule_mask= 0x0F;
4361
4362         struct ixgbe_mirror_info *mr_info =
4363                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4364         struct ixgbe_hw *hw =
4365                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4366         uint8_t mirror_type = 0;
4367
4368         if (ixgbe_vmdq_mode_check(hw) < 0)
4369                 return -ENOTSUP;
4370
4371         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4372                 return -EINVAL;
4373
4374         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4375                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4376                         mirror_conf->rule_type);
4377                 return -EINVAL;
4378         }
4379
4380         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4381                 mirror_type |= IXGBE_MRCTL_VLME;
4382                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4383                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4384                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4385                                 /* search vlan id related pool vlan filter index */
4386                                 reg_index = ixgbe_find_vlvf_slot(hw,
4387                                                 mirror_conf->vlan.vlan_id[i]);
4388                                 if (reg_index < 0)
4389                                         return -EINVAL;
4390                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4391                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4392                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4393                                       mirror_conf->vlan.vlan_id[i]))
4394                                         vlan_mask |= (1ULL << reg_index);
4395                                 else
4396                                         return -EINVAL;
4397                         }
4398                 }
4399
4400                 if (on) {
4401                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4402                         mv_msb = vlan_mask >> vlan_mask_offset;
4403
4404                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4405                                                 mirror_conf->vlan.vlan_mask;
4406                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4407                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4408                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4409                                                 mirror_conf->vlan.vlan_id[i];
4410                         }
4411                 } else {
4412                         mv_lsb = 0;
4413                         mv_msb = 0;
4414                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4415                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4416                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4417                 }
4418         }
4419
4420         /*
4421          * if enable pool mirror, write related pool mask register,if disable
4422          * pool mirror, clear PFMRVM register
4423          */
4424         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4425                 mirror_type |= IXGBE_MRCTL_VPME;
4426                 if (on) {
4427                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4428                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4429                         mr_info->mr_conf[rule_id].pool_mask =
4430                                         mirror_conf->pool_mask;
4431
4432                 } else {
4433                         mp_lsb = 0;
4434                         mp_msb = 0;
4435                         mr_info->mr_conf[rule_id].pool_mask = 0;
4436                 }
4437         }
4438         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4439                 mirror_type |= IXGBE_MRCTL_UPME;
4440         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4441                 mirror_type |= IXGBE_MRCTL_DPME;
4442
4443         /* read  mirror control register and recalculate it */
4444         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4445
4446         if (on) {
4447                 mr_ctl |= mirror_type;
4448                 mr_ctl &= mirror_rule_mask;
4449                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4450         } else
4451                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4452
4453         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4454         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4455
4456         /* write mirrror control  register */
4457         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4458
4459         /* write pool mirrror control  register */
4460         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4461                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4462                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4463                                 mp_msb);
4464         }
4465         /* write VLAN mirrror control  register */
4466         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4467                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4468                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4469                                 mv_msb);
4470         }
4471
4472         return 0;
4473 }
4474
4475 static int
4476 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4477 {
4478         int mr_ctl = 0;
4479         uint32_t lsb_val = 0;
4480         uint32_t msb_val = 0;
4481         const uint8_t rule_mr_offset = 4;
4482
4483         struct ixgbe_hw *hw =
4484                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4485         struct ixgbe_mirror_info *mr_info =
4486                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4487
4488         if (ixgbe_vmdq_mode_check(hw) < 0)
4489                 return -ENOTSUP;
4490
4491         memset(&mr_info->mr_conf[rule_id], 0,
4492                 sizeof(struct rte_eth_mirror_conf));
4493
4494         /* clear PFVMCTL register */
4495         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4496
4497         /* clear pool mask register */
4498         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4499         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4500
4501         /* clear vlan mask register */
4502         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4503         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4504
4505         return 0;
4506 }
4507
4508 static int
4509 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4510 {
4511         uint32_t mask;
4512         struct ixgbe_hw *hw =
4513                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4514
4515         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4516         mask |= (1 << IXGBE_MISC_VEC_ID);
4517         RTE_SET_USED(queue_id);
4518         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4519
4520         rte_intr_enable(&dev->pci_dev->intr_handle);
4521
4522         return 0;
4523 }
4524
4525 static int
4526 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4527 {
4528         uint32_t mask;
4529         struct ixgbe_hw *hw =
4530                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4531
4532         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4533         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4534         RTE_SET_USED(queue_id);
4535         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4536
4537         return 0;
4538 }
4539
4540 static int
4541 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4542 {
4543         uint32_t mask;
4544         struct ixgbe_hw *hw =
4545                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4546         struct ixgbe_interrupt *intr =
4547                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4548
4549         if (queue_id < 16) {
4550                 ixgbe_disable_intr(hw);
4551                 intr->mask |= (1 << queue_id);
4552                 ixgbe_enable_intr(dev);
4553         } else if (queue_id < 32) {
4554                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4555                 mask &= (1 << queue_id);
4556                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4557         } else if (queue_id < 64) {
4558                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4559                 mask &= (1 << (queue_id - 32));
4560                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4561         }
4562         rte_intr_enable(&dev->pci_dev->intr_handle);
4563
4564         return 0;
4565 }
4566
4567 static int
4568 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4569 {
4570         uint32_t mask;
4571         struct ixgbe_hw *hw =
4572                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4573         struct ixgbe_interrupt *intr =
4574                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4575
4576         if (queue_id < 16) {
4577                 ixgbe_disable_intr(hw);
4578                 intr->mask &= ~(1 << queue_id);
4579                 ixgbe_enable_intr(dev);
4580         } else if (queue_id < 32) {
4581                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4582                 mask &= ~(1 << queue_id);
4583                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4584         } else if (queue_id < 64) {
4585                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4586                 mask &= ~(1 << (queue_id - 32));
4587                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4588         }
4589
4590         return 0;
4591 }
4592
4593 static void
4594 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4595                      uint8_t queue, uint8_t msix_vector)
4596 {
4597         uint32_t tmp, idx;
4598
4599         if (direction == -1) {
4600                 /* other causes */
4601                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4602                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4603                 tmp &= ~0xFF;
4604                 tmp |= msix_vector;
4605                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4606         } else {
4607                 /* rx or tx cause */
4608                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4609                 idx = ((16 * (queue & 1)) + (8 * direction));
4610                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4611                 tmp &= ~(0xFF << idx);
4612                 tmp |= (msix_vector << idx);
4613                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4614         }
4615 }
4616
4617 /**
4618  * set the IVAR registers, mapping interrupt causes to vectors
4619  * @param hw
4620  *  pointer to ixgbe_hw struct
4621  * @direction
4622  *  0 for Rx, 1 for Tx, -1 for other causes
4623  * @queue
4624  *  queue to map the corresponding interrupt to
4625  * @msix_vector
4626  *  the vector to map to the corresponding queue
4627  */
4628 static void
4629 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4630                    uint8_t queue, uint8_t msix_vector)
4631 {
4632         uint32_t tmp, idx;
4633
4634         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4635         if (hw->mac.type == ixgbe_mac_82598EB) {
4636                 if (direction == -1)
4637                         direction = 0;
4638                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4639                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4640                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4641                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4642                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4643         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4644                         (hw->mac.type == ixgbe_mac_X540)) {
4645                 if (direction == -1) {
4646                         /* other causes */
4647                         idx = ((queue & 1) * 8);
4648                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4649                         tmp &= ~(0xFF << idx);
4650                         tmp |= (msix_vector << idx);
4651                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4652                 } else {
4653                         /* rx or tx causes */
4654                         idx = ((16 * (queue & 1)) + (8 * direction));
4655                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4656                         tmp &= ~(0xFF << idx);
4657                         tmp |= (msix_vector << idx);
4658                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4659                 }
4660         }
4661 }
4662
4663 static void
4664 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4665 {
4666         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4667         struct ixgbe_hw *hw =
4668                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4669         uint32_t q_idx;
4670         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4671
4672         /* won't configure msix register if no mapping is done
4673          * between intr vector and event fd.
4674          */
4675         if (!rte_intr_dp_is_en(intr_handle))
4676                 return;
4677
4678         /* Configure all RX queues of VF */
4679         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4680                 /* Force all queue use vector 0,
4681                  * as IXGBE_VF_MAXMSIVECOTR = 1
4682                  */
4683                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4684                 intr_handle->intr_vec[q_idx] = vector_idx;
4685         }
4686
4687         /* Configure VF other cause ivar */
4688         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4689 }
4690
4691 /**
4692  * Sets up the hardware to properly generate MSI-X interrupts
4693  * @hw
4694  *  board private structure
4695  */
4696 static void
4697 ixgbe_configure_msix(struct rte_eth_dev *dev)
4698 {
4699         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4700         struct ixgbe_hw *hw =
4701                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4703         uint32_t vec = IXGBE_MISC_VEC_ID;
4704         uint32_t mask;
4705         uint32_t gpie;
4706
4707         /* won't configure msix register if no mapping is done
4708          * between intr vector and event fd
4709          */
4710         if (!rte_intr_dp_is_en(intr_handle))
4711                 return;
4712
4713         if (rte_intr_allow_others(intr_handle))
4714                 vec = base = IXGBE_RX_VEC_START;
4715
4716         /* setup GPIE for MSI-x mode */
4717         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4718         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4719                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4720         /* auto clearing and auto setting corresponding bits in EIMS
4721          * when MSI-X interrupt is triggered
4722          */
4723         if (hw->mac.type == ixgbe_mac_82598EB) {
4724                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4725         } else {
4726                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4727                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4728         }
4729         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4730
4731         /* Populate the IVAR table and set the ITR values to the
4732          * corresponding register.
4733          */
4734         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4735              queue_id++) {
4736                 /* by default, 1:1 mapping */
4737                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4738                 intr_handle->intr_vec[queue_id] = vec;
4739                 if (vec < base + intr_handle->nb_efd - 1)
4740                         vec++;
4741         }
4742
4743         switch (hw->mac.type) {
4744         case ixgbe_mac_82598EB:
4745                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4746                                    IXGBE_MISC_VEC_ID);
4747                 break;
4748         case ixgbe_mac_82599EB:
4749         case ixgbe_mac_X540:
4750                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4751                 break;
4752         default:
4753                 break;
4754         }
4755         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4756                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4757
4758         /* set up to autoclear timer, and the vectors */
4759         mask = IXGBE_EIMS_ENABLE_MASK;
4760         mask &= ~(IXGBE_EIMS_OTHER |
4761                   IXGBE_EIMS_MAILBOX |
4762                   IXGBE_EIMS_LSC);
4763
4764         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4765 }
4766
4767 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4768         uint16_t queue_idx, uint16_t tx_rate)
4769 {
4770         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4771         uint32_t rf_dec, rf_int;
4772         uint32_t bcnrc_val;
4773         uint16_t link_speed = dev->data->dev_link.link_speed;
4774
4775         if (queue_idx >= hw->mac.max_tx_queues)
4776                 return -EINVAL;
4777
4778         if (tx_rate != 0) {
4779                 /* Calculate the rate factor values to set */
4780                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4781                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4782                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4783
4784                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4785                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4786                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4787                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4788         } else {
4789                 bcnrc_val = 0;
4790         }
4791
4792         /*
4793          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4794          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4795          * set as 0x4.
4796          */
4797         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4798                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4799                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4800                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4801                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4802         else
4803                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4804                         IXGBE_MMW_SIZE_DEFAULT);
4805
4806         /* Set RTTBCNRC of queue X */
4807         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4808         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4809         IXGBE_WRITE_FLUSH(hw);
4810
4811         return 0;
4812 }
4813
4814 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4815         uint16_t tx_rate, uint64_t q_msk)
4816 {
4817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4818         struct ixgbe_vf_info *vfinfo =
4819                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4820         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4821         uint32_t queue_stride =
4822                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4823         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4824         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4825         uint16_t total_rate = 0;
4826
4827         if (queue_end >= hw->mac.max_tx_queues)
4828                 return -EINVAL;
4829
4830         if (vfinfo != NULL) {
4831                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4832                         if (vf_idx == vf)
4833                                 continue;
4834                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4835                                 idx++)
4836                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4837                 }
4838         } else
4839                 return -EINVAL;
4840
4841         /* Store tx_rate for this vf. */
4842         for (idx = 0; idx < nb_q_per_pool; idx++) {
4843                 if (((uint64_t)0x1 << idx) & q_msk) {
4844                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4845                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4846                         total_rate += tx_rate;
4847                 }
4848         }
4849
4850         if (total_rate > dev->data->dev_link.link_speed) {
4851                 /*
4852                  * Reset stored TX rate of the VF if it causes exceed
4853                  * link speed.
4854                  */
4855                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4856                 return -EINVAL;
4857         }
4858
4859         /* Set RTTBCNRC of each queue/pool for vf X  */
4860         for (; queue_idx <= queue_end; queue_idx++) {
4861                 if (0x1 & q_msk)
4862                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4863                 q_msk = q_msk >> 1;
4864         }
4865
4866         return 0;
4867 }
4868
4869 static void
4870 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4871                      __attribute__((unused)) uint32_t index,
4872                      __attribute__((unused)) uint32_t pool)
4873 {
4874         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4875         int diag;
4876
4877         /*
4878          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4879          * operation. Trap this case to avoid exhausting the [very limited]
4880          * set of PF resources used to store VF MAC addresses.
4881          */
4882         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4883                 return;
4884         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4885         if (diag == 0)
4886                 return;
4887         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4888 }
4889
4890 static void
4891 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4892 {
4893         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4894         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4895         struct ether_addr *mac_addr;
4896         uint32_t i;
4897         int diag;
4898
4899         /*
4900          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4901          * not support the deletion of a given MAC address.
4902          * Instead, it imposes to delete all MAC addresses, then to add again
4903          * all MAC addresses with the exception of the one to be deleted.
4904          */
4905         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4906
4907         /*
4908          * Add again all MAC addresses, with the exception of the deleted one
4909          * and of the permanent MAC address.
4910          */
4911         for (i = 0, mac_addr = dev->data->mac_addrs;
4912              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4913                 /* Skip the deleted MAC address */
4914                 if (i == index)
4915                         continue;
4916                 /* Skip NULL MAC addresses */
4917                 if (is_zero_ether_addr(mac_addr))
4918                         continue;
4919                 /* Skip the permanent MAC address */
4920                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4921                         continue;
4922                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4923                 if (diag != 0)
4924                         PMD_DRV_LOG(ERR,
4925                                     "Adding again MAC address "
4926                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4927                                     "diag=%d",
4928                                     mac_addr->addr_bytes[0],
4929                                     mac_addr->addr_bytes[1],
4930                                     mac_addr->addr_bytes[2],
4931                                     mac_addr->addr_bytes[3],
4932                                     mac_addr->addr_bytes[4],
4933                                     mac_addr->addr_bytes[5],
4934                                     diag);
4935         }
4936 }
4937
4938 static void
4939 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4940 {
4941         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4942
4943         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4944 }
4945
4946 #define MAC_TYPE_FILTER_SUP(type)    do {\
4947         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4948                 (type) != ixgbe_mac_X550)\
4949                 return -ENOTSUP;\
4950 } while (0)
4951
4952 static int
4953 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4954                         struct rte_eth_syn_filter *filter,
4955                         bool add)
4956 {
4957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4958         uint32_t synqf;
4959
4960         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4961                 return -EINVAL;
4962
4963         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4964
4965         if (add) {
4966                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4967                         return -EINVAL;
4968                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4969                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4970
4971                 if (filter->hig_pri)
4972                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4973                 else
4974                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4975         } else {
4976                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4977                         return -ENOENT;
4978                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4979         }
4980         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4981         IXGBE_WRITE_FLUSH(hw);
4982         return 0;
4983 }
4984
4985 static int
4986 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4987                         struct rte_eth_syn_filter *filter)
4988 {
4989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4990         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4991
4992         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4993                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4994                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4995                 return 0;
4996         }
4997         return -ENOENT;
4998 }
4999
5000 static int
5001 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5002                         enum rte_filter_op filter_op,
5003                         void *arg)
5004 {
5005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5006         int ret;
5007
5008         MAC_TYPE_FILTER_SUP(hw->mac.type);
5009
5010         if (filter_op == RTE_ETH_FILTER_NOP)
5011                 return 0;
5012
5013         if (arg == NULL) {
5014                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5015                             filter_op);
5016                 return -EINVAL;
5017         }
5018
5019         switch (filter_op) {
5020         case RTE_ETH_FILTER_ADD:
5021                 ret = ixgbe_syn_filter_set(dev,
5022                                 (struct rte_eth_syn_filter *)arg,
5023                                 TRUE);
5024                 break;
5025         case RTE_ETH_FILTER_DELETE:
5026                 ret = ixgbe_syn_filter_set(dev,
5027                                 (struct rte_eth_syn_filter *)arg,
5028                                 FALSE);
5029                 break;
5030         case RTE_ETH_FILTER_GET:
5031                 ret = ixgbe_syn_filter_get(dev,
5032                                 (struct rte_eth_syn_filter *)arg);
5033                 break;
5034         default:
5035                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5036                 ret = -EINVAL;
5037                 break;
5038         }
5039
5040         return ret;
5041 }
5042
5043
5044 static inline enum ixgbe_5tuple_protocol
5045 convert_protocol_type(uint8_t protocol_value)
5046 {
5047         if (protocol_value == IPPROTO_TCP)
5048                 return IXGBE_FILTER_PROTOCOL_TCP;
5049         else if (protocol_value == IPPROTO_UDP)
5050                 return IXGBE_FILTER_PROTOCOL_UDP;
5051         else if (protocol_value == IPPROTO_SCTP)
5052                 return IXGBE_FILTER_PROTOCOL_SCTP;
5053         else
5054                 return IXGBE_FILTER_PROTOCOL_NONE;
5055 }
5056
5057 /*
5058  * add a 5tuple filter
5059  *
5060  * @param
5061  * dev: Pointer to struct rte_eth_dev.
5062  * index: the index the filter allocates.
5063  * filter: ponter to the filter that will be added.
5064  * rx_queue: the queue id the filter assigned to.
5065  *
5066  * @return
5067  *    - On success, zero.
5068  *    - On failure, a negative value.
5069  */
5070 static int
5071 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5072                         struct ixgbe_5tuple_filter *filter)
5073 {
5074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075         struct ixgbe_filter_info *filter_info =
5076                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5077         int i, idx, shift;
5078         uint32_t ftqf, sdpqf;
5079         uint32_t l34timir = 0;
5080         uint8_t mask = 0xff;
5081
5082         /*
5083          * look for an unused 5tuple filter index,
5084          * and insert the filter to list.
5085          */
5086         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5087                 idx = i / (sizeof(uint32_t) * NBBY);
5088                 shift = i % (sizeof(uint32_t) * NBBY);
5089                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5090                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5091                         filter->index = i;
5092                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5093                                           filter,
5094                                           entries);
5095                         break;
5096                 }
5097         }
5098         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5099                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5100                 return -ENOSYS;
5101         }
5102
5103         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5104                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5105         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5106
5107         ftqf = (uint32_t)(filter->filter_info.proto &
5108                 IXGBE_FTQF_PROTOCOL_MASK);
5109         ftqf |= (uint32_t)((filter->filter_info.priority &
5110                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5111         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5112                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5113         if (filter->filter_info.dst_ip_mask == 0)
5114                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5115         if (filter->filter_info.src_port_mask == 0)
5116                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5117         if (filter->filter_info.dst_port_mask == 0)
5118                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5119         if (filter->filter_info.proto_mask == 0)
5120                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5121         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5122         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5123         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5124
5125         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5126         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5127         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5128         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5129
5130         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5131         l34timir |= (uint32_t)(filter->queue <<
5132                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5133         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5134         return 0;
5135 }
5136
5137 /*
5138  * remove a 5tuple filter
5139  *
5140  * @param
5141  * dev: Pointer to struct rte_eth_dev.
5142  * filter: the pointer of the filter will be removed.
5143  */
5144 static void
5145 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5146                         struct ixgbe_5tuple_filter *filter)
5147 {
5148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5149         struct ixgbe_filter_info *filter_info =
5150                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5151         uint16_t index = filter->index;
5152
5153         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5154                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5155         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5156         rte_free(filter);
5157
5158         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5159         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5160         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5161         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5162         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5163 }
5164
5165 static int
5166 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5167 {
5168         struct ixgbe_hw *hw;
5169         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5170
5171         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5172
5173         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5174                 return -EINVAL;
5175
5176         /* refuse mtu that requires the support of scattered packets when this
5177          * feature has not been enabled before. */
5178         if (!dev->data->scattered_rx &&
5179             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5180              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5181                 return -EINVAL;
5182
5183         /*
5184          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5185          * request of the version 2.0 of the mailbox API.
5186          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5187          * of the mailbox API.
5188          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5189          * prior to 3.11.33 which contains the following change:
5190          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5191          */
5192         ixgbevf_rlpml_set_vf(hw, max_frame);
5193
5194         /* update max frame size */
5195         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5196         return 0;
5197 }
5198
5199 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5200         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5201                 return -ENOTSUP;\
5202 } while (0)
5203
5204 static inline struct ixgbe_5tuple_filter *
5205 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5206                         struct ixgbe_5tuple_filter_info *key)
5207 {
5208         struct ixgbe_5tuple_filter *it;
5209
5210         TAILQ_FOREACH(it, filter_list, entries) {
5211                 if (memcmp(key, &it->filter_info,
5212                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5213                         return it;
5214                 }
5215         }
5216         return NULL;
5217 }
5218
5219 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5220 static inline int
5221 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5222                         struct ixgbe_5tuple_filter_info *filter_info)
5223 {
5224         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5225                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5226                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5227                 return -EINVAL;
5228
5229         switch (filter->dst_ip_mask) {
5230         case UINT32_MAX:
5231                 filter_info->dst_ip_mask = 0;
5232                 filter_info->dst_ip = filter->dst_ip;
5233                 break;
5234         case 0:
5235                 filter_info->dst_ip_mask = 1;
5236                 break;
5237         default:
5238                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5239                 return -EINVAL;
5240         }
5241
5242         switch (filter->src_ip_mask) {
5243         case UINT32_MAX:
5244                 filter_info->src_ip_mask = 0;
5245                 filter_info->src_ip = filter->src_ip;
5246                 break;
5247         case 0:
5248                 filter_info->src_ip_mask = 1;
5249                 break;
5250         default:
5251                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5252                 return -EINVAL;
5253         }
5254
5255         switch (filter->dst_port_mask) {
5256         case UINT16_MAX:
5257                 filter_info->dst_port_mask = 0;
5258                 filter_info->dst_port = filter->dst_port;
5259                 break;
5260         case 0:
5261                 filter_info->dst_port_mask = 1;
5262                 break;
5263         default:
5264                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5265                 return -EINVAL;
5266         }
5267
5268         switch (filter->src_port_mask) {
5269         case UINT16_MAX:
5270                 filter_info->src_port_mask = 0;
5271                 filter_info->src_port = filter->src_port;
5272                 break;
5273         case 0:
5274                 filter_info->src_port_mask = 1;
5275                 break;
5276         default:
5277                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5278                 return -EINVAL;
5279         }
5280
5281         switch (filter->proto_mask) {
5282         case UINT8_MAX:
5283                 filter_info->proto_mask = 0;
5284                 filter_info->proto =
5285                         convert_protocol_type(filter->proto);
5286                 break;
5287         case 0:
5288                 filter_info->proto_mask = 1;
5289                 break;
5290         default:
5291                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5292                 return -EINVAL;
5293         }
5294
5295         filter_info->priority = (uint8_t)filter->priority;
5296         return 0;
5297 }
5298
5299 /*
5300  * add or delete a ntuple filter
5301  *
5302  * @param
5303  * dev: Pointer to struct rte_eth_dev.
5304  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5305  * add: if true, add filter, if false, remove filter
5306  *
5307  * @return
5308  *    - On success, zero.
5309  *    - On failure, a negative value.
5310  */
5311 static int
5312 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5313                         struct rte_eth_ntuple_filter *ntuple_filter,
5314                         bool add)
5315 {
5316         struct ixgbe_filter_info *filter_info =
5317                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5318         struct ixgbe_5tuple_filter_info filter_5tuple;
5319         struct ixgbe_5tuple_filter *filter;
5320         int ret;
5321
5322         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5323                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5324                 return -EINVAL;
5325         }
5326
5327         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5328         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5329         if (ret < 0)
5330                 return ret;
5331
5332         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5333                                          &filter_5tuple);
5334         if (filter != NULL && add) {
5335                 PMD_DRV_LOG(ERR, "filter exists.");
5336                 return -EEXIST;
5337         }
5338         if (filter == NULL && !add) {
5339                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5340                 return -ENOENT;
5341         }
5342
5343         if (add) {
5344                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5345                                 sizeof(struct ixgbe_5tuple_filter), 0);
5346                 if (filter == NULL)
5347                         return -ENOMEM;
5348                 (void)rte_memcpy(&filter->filter_info,
5349                                  &filter_5tuple,
5350                                  sizeof(struct ixgbe_5tuple_filter_info));
5351                 filter->queue = ntuple_filter->queue;
5352                 ret = ixgbe_add_5tuple_filter(dev, filter);
5353                 if (ret < 0) {
5354                         rte_free(filter);
5355                         return ret;
5356                 }
5357         } else
5358                 ixgbe_remove_5tuple_filter(dev, filter);
5359
5360         return 0;
5361 }
5362
5363 /*
5364  * get a ntuple filter
5365  *
5366  * @param
5367  * dev: Pointer to struct rte_eth_dev.
5368  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5369  *
5370  * @return
5371  *    - On success, zero.
5372  *    - On failure, a negative value.
5373  */
5374 static int
5375 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5376                         struct rte_eth_ntuple_filter *ntuple_filter)
5377 {
5378         struct ixgbe_filter_info *filter_info =
5379                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5380         struct ixgbe_5tuple_filter_info filter_5tuple;
5381         struct ixgbe_5tuple_filter *filter;
5382         int ret;
5383
5384         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5385                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5386                 return -EINVAL;
5387         }
5388
5389         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5390         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5391         if (ret < 0)
5392                 return ret;
5393
5394         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5395                                          &filter_5tuple);
5396         if (filter == NULL) {
5397                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5398                 return -ENOENT;
5399         }
5400         ntuple_filter->queue = filter->queue;
5401         return 0;
5402 }
5403
5404 /*
5405  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5406  * @dev: pointer to rte_eth_dev structure
5407  * @filter_op:operation will be taken.
5408  * @arg: a pointer to specific structure corresponding to the filter_op
5409  *
5410  * @return
5411  *    - On success, zero.
5412  *    - On failure, a negative value.
5413  */
5414 static int
5415 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5416                                 enum rte_filter_op filter_op,
5417                                 void *arg)
5418 {
5419         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5420         int ret;
5421
5422         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5423
5424         if (filter_op == RTE_ETH_FILTER_NOP)
5425                 return 0;
5426
5427         if (arg == NULL) {
5428                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5429                             filter_op);
5430                 return -EINVAL;
5431         }
5432
5433         switch (filter_op) {
5434         case RTE_ETH_FILTER_ADD:
5435                 ret = ixgbe_add_del_ntuple_filter(dev,
5436                         (struct rte_eth_ntuple_filter *)arg,
5437                         TRUE);
5438                 break;
5439         case RTE_ETH_FILTER_DELETE:
5440                 ret = ixgbe_add_del_ntuple_filter(dev,
5441                         (struct rte_eth_ntuple_filter *)arg,
5442                         FALSE);
5443                 break;
5444         case RTE_ETH_FILTER_GET:
5445                 ret = ixgbe_get_ntuple_filter(dev,
5446                         (struct rte_eth_ntuple_filter *)arg);
5447                 break;
5448         default:
5449                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5450                 ret = -EINVAL;
5451                 break;
5452         }
5453         return ret;
5454 }
5455
5456 static inline int
5457 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5458                         uint16_t ethertype)
5459 {
5460         int i;
5461
5462         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5463                 if (filter_info->ethertype_filters[i] == ethertype &&
5464                     (filter_info->ethertype_mask & (1 << i)))
5465                         return i;
5466         }
5467         return -1;
5468 }
5469
5470 static inline int
5471 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5472                         uint16_t ethertype)
5473 {
5474         int i;
5475
5476         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5477                 if (!(filter_info->ethertype_mask & (1 << i))) {
5478                         filter_info->ethertype_mask |= 1 << i;
5479                         filter_info->ethertype_filters[i] = ethertype;
5480                         return i;
5481                 }
5482         }
5483         return -1;
5484 }
5485
5486 static inline int
5487 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5488                         uint8_t idx)
5489 {
5490         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5491                 return -1;
5492         filter_info->ethertype_mask &= ~(1 << idx);
5493         filter_info->ethertype_filters[idx] = 0;
5494         return idx;
5495 }
5496
5497 static int
5498 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5499                         struct rte_eth_ethertype_filter *filter,
5500                         bool add)
5501 {
5502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5503         struct ixgbe_filter_info *filter_info =
5504                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5505         uint32_t etqf = 0;
5506         uint32_t etqs = 0;
5507         int ret;
5508
5509         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5510                 return -EINVAL;
5511
5512         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5513                 filter->ether_type == ETHER_TYPE_IPv6) {
5514                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5515                         " ethertype filter.", filter->ether_type);
5516                 return -EINVAL;
5517         }
5518
5519         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5520                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5521                 return -EINVAL;
5522         }
5523         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5524                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5525                 return -EINVAL;
5526         }
5527
5528         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5529         if (ret >= 0 && add) {
5530                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5531                             filter->ether_type);
5532                 return -EEXIST;
5533         }
5534         if (ret < 0 && !add) {
5535                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5536                             filter->ether_type);
5537                 return -ENOENT;
5538         }
5539
5540         if (add) {
5541                 ret = ixgbe_ethertype_filter_insert(filter_info,
5542                         filter->ether_type);
5543                 if (ret < 0) {
5544                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5545                         return -ENOSYS;
5546                 }
5547                 etqf = IXGBE_ETQF_FILTER_EN;
5548                 etqf |= (uint32_t)filter->ether_type;
5549                 etqs |= (uint32_t)((filter->queue <<
5550                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5551                                     IXGBE_ETQS_RX_QUEUE);
5552                 etqs |= IXGBE_ETQS_QUEUE_EN;
5553         } else {
5554                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5555                 if (ret < 0)
5556                         return -ENOSYS;
5557         }
5558         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5559         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5560         IXGBE_WRITE_FLUSH(hw);
5561
5562         return 0;
5563 }
5564
5565 static int
5566 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5567                         struct rte_eth_ethertype_filter *filter)
5568 {
5569         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5570         struct ixgbe_filter_info *filter_info =
5571                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5572         uint32_t etqf, etqs;
5573         int ret;
5574
5575         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5576         if (ret < 0) {
5577                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5578                             filter->ether_type);
5579                 return -ENOENT;
5580         }
5581
5582         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5583         if (etqf & IXGBE_ETQF_FILTER_EN) {
5584                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5585                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5586                 filter->flags = 0;
5587                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5588                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5589                 return 0;
5590         }
5591         return -ENOENT;
5592 }
5593
5594 /*
5595  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5596  * @dev: pointer to rte_eth_dev structure
5597  * @filter_op:operation will be taken.
5598  * @arg: a pointer to specific structure corresponding to the filter_op
5599  */
5600 static int
5601 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5602                                 enum rte_filter_op filter_op,
5603                                 void *arg)
5604 {
5605         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5606         int ret;
5607
5608         MAC_TYPE_FILTER_SUP(hw->mac.type);
5609
5610         if (filter_op == RTE_ETH_FILTER_NOP)
5611                 return 0;
5612
5613         if (arg == NULL) {
5614                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5615                             filter_op);
5616                 return -EINVAL;
5617         }
5618
5619         switch (filter_op) {
5620         case RTE_ETH_FILTER_ADD:
5621                 ret = ixgbe_add_del_ethertype_filter(dev,
5622                         (struct rte_eth_ethertype_filter *)arg,
5623                         TRUE);
5624                 break;
5625         case RTE_ETH_FILTER_DELETE:
5626                 ret = ixgbe_add_del_ethertype_filter(dev,
5627                         (struct rte_eth_ethertype_filter *)arg,
5628                         FALSE);
5629                 break;
5630         case RTE_ETH_FILTER_GET:
5631                 ret = ixgbe_get_ethertype_filter(dev,
5632                         (struct rte_eth_ethertype_filter *)arg);
5633                 break;
5634         default:
5635                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5636                 ret = -EINVAL;
5637                 break;
5638         }
5639         return ret;
5640 }
5641
5642 static int
5643 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5644                      enum rte_filter_type filter_type,
5645                      enum rte_filter_op filter_op,
5646                      void *arg)
5647 {
5648         int ret = -EINVAL;
5649
5650         switch (filter_type) {
5651         case RTE_ETH_FILTER_NTUPLE:
5652                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5653                 break;
5654         case RTE_ETH_FILTER_ETHERTYPE:
5655                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5656                 break;
5657         case RTE_ETH_FILTER_SYN:
5658                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5659                 break;
5660         case RTE_ETH_FILTER_FDIR:
5661                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5662                 break;
5663         case RTE_ETH_FILTER_L2_TUNNEL:
5664                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5665                 break;
5666         default:
5667                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5668                                                         filter_type);
5669                 break;
5670         }
5671
5672         return ret;
5673 }
5674
5675 static u8 *
5676 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5677                         u8 **mc_addr_ptr, u32 *vmdq)
5678 {
5679         u8 *mc_addr;
5680
5681         *vmdq = 0;
5682         mc_addr = *mc_addr_ptr;
5683         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5684         return mc_addr;
5685 }
5686
5687 static int
5688 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5689                           struct ether_addr *mc_addr_set,
5690                           uint32_t nb_mc_addr)
5691 {
5692         struct ixgbe_hw *hw;
5693         u8 *mc_addr_list;
5694
5695         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5696         mc_addr_list = (u8 *)mc_addr_set;
5697         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5698                                          ixgbe_dev_addr_list_itr, TRUE);
5699 }
5700
5701 static uint64_t
5702 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5703 {
5704         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5705         uint64_t systime_cycles;
5706
5707         switch (hw->mac.type) {
5708         case ixgbe_mac_X550:
5709                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5710                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5711                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5712                                 * NSEC_PER_SEC;
5713                 break;
5714         default:
5715                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5716                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5717                                 << 32;
5718         }
5719
5720         return systime_cycles;
5721 }
5722
5723 static uint64_t
5724 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5725 {
5726         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5727         uint64_t rx_tstamp_cycles;
5728
5729         switch (hw->mac.type) {
5730         case ixgbe_mac_X550:
5731                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5732                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5733                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5734                                 * NSEC_PER_SEC;
5735                 break;
5736         default:
5737                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5738                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5739                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5740                                 << 32;
5741         }
5742
5743         return rx_tstamp_cycles;
5744 }
5745
5746 static uint64_t
5747 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5748 {
5749         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5750         uint64_t tx_tstamp_cycles;
5751
5752         switch (hw->mac.type) {
5753         case ixgbe_mac_X550:
5754                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5755                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5756                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5757                                 * NSEC_PER_SEC;
5758                 break;
5759         default:
5760                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5761                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5762                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5763                                 << 32;
5764         }
5765
5766         return tx_tstamp_cycles;
5767 }
5768
5769 static void
5770 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5771 {
5772         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5773         struct ixgbe_adapter *adapter =
5774                 (struct ixgbe_adapter *)dev->data->dev_private;
5775         struct rte_eth_link link;
5776         uint32_t incval = 0;
5777         uint32_t shift = 0;
5778
5779         /* Get current link speed. */
5780         memset(&link, 0, sizeof(link));
5781         ixgbe_dev_link_update(dev, 1);
5782         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5783
5784         switch (link.link_speed) {
5785         case ETH_LINK_SPEED_100:
5786                 incval = IXGBE_INCVAL_100;
5787                 shift = IXGBE_INCVAL_SHIFT_100;
5788                 break;
5789         case ETH_LINK_SPEED_1000:
5790                 incval = IXGBE_INCVAL_1GB;
5791                 shift = IXGBE_INCVAL_SHIFT_1GB;
5792                 break;
5793         case ETH_LINK_SPEED_10000:
5794         default:
5795                 incval = IXGBE_INCVAL_10GB;
5796                 shift = IXGBE_INCVAL_SHIFT_10GB;
5797                 break;
5798         }
5799
5800         switch (hw->mac.type) {
5801         case ixgbe_mac_X550:
5802                 /* Independent of link speed. */
5803                 incval = 1;
5804                 /* Cycles read will be interpreted as ns. */
5805                 shift = 0;
5806                 /* Fall-through */
5807         case ixgbe_mac_X540:
5808                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5809                 break;
5810         case ixgbe_mac_82599EB:
5811                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5812                 shift -= IXGBE_INCVAL_SHIFT_82599;
5813                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5814                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5815                 break;
5816         default:
5817                 /* Not supported. */
5818                 return;
5819         }
5820
5821         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5822         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5823         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5824
5825         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5826         adapter->systime_tc.cc_shift = shift;
5827         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5828
5829         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5830         adapter->rx_tstamp_tc.cc_shift = shift;
5831         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5832
5833         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5834         adapter->tx_tstamp_tc.cc_shift = shift;
5835         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5836 }
5837
5838 static int
5839 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5840 {
5841         struct ixgbe_adapter *adapter =
5842                         (struct ixgbe_adapter *)dev->data->dev_private;
5843
5844         adapter->systime_tc.nsec += delta;
5845         adapter->rx_tstamp_tc.nsec += delta;
5846         adapter->tx_tstamp_tc.nsec += delta;
5847
5848         return 0;
5849 }
5850
5851 static int
5852 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5853 {
5854         uint64_t ns;
5855         struct ixgbe_adapter *adapter =
5856                         (struct ixgbe_adapter *)dev->data->dev_private;
5857
5858         ns = rte_timespec_to_ns(ts);
5859         /* Set the timecounters to a new value. */
5860         adapter->systime_tc.nsec = ns;
5861         adapter->rx_tstamp_tc.nsec = ns;
5862         adapter->tx_tstamp_tc.nsec = ns;
5863
5864         return 0;
5865 }
5866
5867 static int
5868 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5869 {
5870         uint64_t ns, systime_cycles;
5871         struct ixgbe_adapter *adapter =
5872                         (struct ixgbe_adapter *)dev->data->dev_private;
5873
5874         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5875         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5876         *ts = rte_ns_to_timespec(ns);
5877
5878         return 0;
5879 }
5880
5881 static int
5882 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5883 {
5884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5885         uint32_t tsync_ctl;
5886         uint32_t tsauxc;
5887
5888         /* Stop the timesync system time. */
5889         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5890         /* Reset the timesync system time value. */
5891         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5892         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5893
5894         /* Enable system time for platforms where it isn't on by default. */
5895         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5896         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5897         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5898
5899         ixgbe_start_timecounters(dev);
5900
5901         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5902         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5903                         (ETHER_TYPE_1588 |
5904                          IXGBE_ETQF_FILTER_EN |
5905                          IXGBE_ETQF_1588));
5906
5907         /* Enable timestamping of received PTP packets. */
5908         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5909         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5910         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5911
5912         /* Enable timestamping of transmitted PTP packets. */
5913         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5914         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5915         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5916
5917         IXGBE_WRITE_FLUSH(hw);
5918
5919         return 0;
5920 }
5921
5922 static int
5923 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5924 {
5925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5926         uint32_t tsync_ctl;
5927
5928         /* Disable timestamping of transmitted PTP packets. */
5929         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5930         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5931         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5932
5933         /* Disable timestamping of received PTP packets. */
5934         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5935         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5936         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5937
5938         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5939         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5940
5941         /* Stop incrementating the System Time registers. */
5942         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5943
5944         return 0;
5945 }
5946
5947 static int
5948 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5949                                  struct timespec *timestamp,
5950                                  uint32_t flags __rte_unused)
5951 {
5952         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5953         struct ixgbe_adapter *adapter =
5954                 (struct ixgbe_adapter *)dev->data->dev_private;
5955         uint32_t tsync_rxctl;
5956         uint64_t rx_tstamp_cycles;
5957         uint64_t ns;
5958
5959         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5960         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5961                 return -EINVAL;
5962
5963         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
5964         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5965         *timestamp = rte_ns_to_timespec(ns);
5966
5967         return  0;
5968 }
5969
5970 static int
5971 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5972                                  struct timespec *timestamp)
5973 {
5974         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5975         struct ixgbe_adapter *adapter =
5976                 (struct ixgbe_adapter *)dev->data->dev_private;
5977         uint32_t tsync_txctl;
5978         uint64_t tx_tstamp_cycles;
5979         uint64_t ns;
5980
5981         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5982         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5983                 return -EINVAL;
5984
5985         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
5986         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5987         *timestamp = rte_ns_to_timespec(ns);
5988
5989         return 0;
5990 }
5991
5992 static int
5993 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5994 {
5995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5996         int count = 0;
5997         int g_ind = 0;
5998         const struct reg_info *reg_group;
5999         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6000                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6001
6002         while ((reg_group = reg_set[g_ind++]))
6003                 count += ixgbe_regs_group_count(reg_group);
6004
6005         return count;
6006 }
6007
6008 static int
6009 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6010 {
6011         int count = 0;
6012         int g_ind = 0;
6013         const struct reg_info *reg_group;
6014
6015         while ((reg_group = ixgbevf_regs[g_ind++]))
6016                 count += ixgbe_regs_group_count(reg_group);
6017
6018         return count;
6019 }
6020
6021 static int
6022 ixgbe_get_regs(struct rte_eth_dev *dev,
6023               struct rte_dev_reg_info *regs)
6024 {
6025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6026         uint32_t *data = regs->data;
6027         int g_ind = 0;
6028         int count = 0;
6029         const struct reg_info *reg_group;
6030         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6031                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6032
6033         /* Support only full register dump */
6034         if ((regs->length == 0) ||
6035             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6036                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6037                         hw->device_id;
6038                 while ((reg_group = reg_set[g_ind++]))
6039                         count += ixgbe_read_regs_group(dev, &data[count],
6040                                 reg_group);
6041                 return 0;
6042         }
6043
6044         return -ENOTSUP;
6045 }
6046
6047 static int
6048 ixgbevf_get_regs(struct rte_eth_dev *dev,
6049                 struct rte_dev_reg_info *regs)
6050 {
6051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6052         uint32_t *data = regs->data;
6053         int g_ind = 0;
6054         int count = 0;
6055         const struct reg_info *reg_group;
6056
6057         /* Support only full register dump */
6058         if ((regs->length == 0) ||
6059             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6060                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6061                         hw->device_id;
6062                 while ((reg_group = ixgbevf_regs[g_ind++]))
6063                         count += ixgbe_read_regs_group(dev, &data[count],
6064                                                       reg_group);
6065                 return 0;
6066         }
6067
6068         return -ENOTSUP;
6069 }
6070
6071 static int
6072 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6073 {
6074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6075
6076         /* Return unit is byte count */
6077         return hw->eeprom.word_size * 2;
6078 }
6079
6080 static int
6081 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6082                 struct rte_dev_eeprom_info *in_eeprom)
6083 {
6084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6085         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6086         uint16_t *data = in_eeprom->data;
6087         int first, length;
6088
6089         first = in_eeprom->offset >> 1;
6090         length = in_eeprom->length >> 1;
6091         if ((first > hw->eeprom.word_size) ||
6092             ((first + length) > hw->eeprom.word_size))
6093                 return -EINVAL;
6094
6095         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6096
6097         return eeprom->ops.read_buffer(hw, first, length, data);
6098 }
6099
6100 static int
6101 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6102                 struct rte_dev_eeprom_info *in_eeprom)
6103 {
6104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6105         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6106         uint16_t *data = in_eeprom->data;
6107         int first, length;
6108
6109         first = in_eeprom->offset >> 1;
6110         length = in_eeprom->length >> 1;
6111         if ((first > hw->eeprom.word_size) ||
6112             ((first + length) > hw->eeprom.word_size))
6113                 return -EINVAL;
6114
6115         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6116
6117         return eeprom->ops.write_buffer(hw,  first, length, data);
6118 }
6119
6120 uint16_t
6121 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6122         switch (mac_type) {
6123         case ixgbe_mac_X550:
6124         case ixgbe_mac_X550EM_x:
6125                 return ETH_RSS_RETA_SIZE_512;
6126         case ixgbe_mac_X550_vf:
6127         case ixgbe_mac_X550EM_x_vf:
6128                 return ETH_RSS_RETA_SIZE_64;
6129         default:
6130                 return ETH_RSS_RETA_SIZE_128;
6131         }
6132 }
6133
6134 uint32_t
6135 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6136         switch (mac_type) {
6137         case ixgbe_mac_X550:
6138         case ixgbe_mac_X550EM_x:
6139                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6140                         return IXGBE_RETA(reta_idx >> 2);
6141                 else
6142                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6143         case ixgbe_mac_X550_vf:
6144         case ixgbe_mac_X550EM_x_vf:
6145                 return IXGBE_VFRETA(reta_idx >> 2);
6146         default:
6147                 return IXGBE_RETA(reta_idx >> 2);
6148         }
6149 }
6150
6151 uint32_t
6152 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6153         switch (mac_type) {
6154         case ixgbe_mac_X550_vf:
6155         case ixgbe_mac_X550EM_x_vf:
6156                 return IXGBE_VFMRQC;
6157         default:
6158                 return IXGBE_MRQC;
6159         }
6160 }
6161
6162 uint32_t
6163 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6164         switch (mac_type) {
6165         case ixgbe_mac_X550_vf:
6166         case ixgbe_mac_X550EM_x_vf:
6167                 return IXGBE_VFRSSRK(i);
6168         default:
6169                 return IXGBE_RSSRK(i);
6170         }
6171 }
6172
6173 bool
6174 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6175         switch (mac_type) {
6176         case ixgbe_mac_82599_vf:
6177         case ixgbe_mac_X540_vf:
6178                 return 0;
6179         default:
6180                 return 1;
6181         }
6182 }
6183
6184 static int
6185 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6186                         struct rte_eth_dcb_info *dcb_info)
6187 {
6188         struct ixgbe_dcb_config *dcb_config =
6189                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6190         struct ixgbe_dcb_tc_config *tc;
6191         uint8_t i, j;
6192
6193         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6194                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6195         else
6196                 dcb_info->nb_tcs = 1;
6197
6198         if (dcb_config->vt_mode) { /* vt is enabled*/
6199                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6200                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6201                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6202                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6203                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6204                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6205                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6206                                                 i * dcb_info->nb_tcs + j;
6207                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6208                                 dcb_info->tc_queue.tc_txq[i][j].base =
6209                                                 i * dcb_info->nb_tcs + j;
6210                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6211                         }
6212                 }
6213         } else { /* vt is disabled*/
6214                 struct rte_eth_dcb_rx_conf *rx_conf =
6215                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6216                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6217                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6218                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6219                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6220                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6221                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6222                         }
6223                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6224                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6225                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6226                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6227                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6228                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6229                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6230                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6231                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6232                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6233                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6234                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6235                         }
6236                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6237                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6238                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6239                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6240                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6241                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6242                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6243                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6244                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6245                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6246                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6247                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6248                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6249                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6250                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6251                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6252                 }
6253         }
6254         for (i = 0; i < dcb_info->nb_tcs; i++) {
6255                 tc = &dcb_config->tc_config[i];
6256                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6257         }
6258         return 0;
6259 }
6260
6261 /* Update e-tag ether type */
6262 static int
6263 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6264                             uint16_t ether_type)
6265 {
6266         uint32_t etag_etype;
6267
6268         if (hw->mac.type != ixgbe_mac_X550 &&
6269             hw->mac.type != ixgbe_mac_X550EM_x) {
6270                 return -ENOTSUP;
6271         }
6272
6273         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6274         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6275         etag_etype |= ether_type;
6276         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6277         IXGBE_WRITE_FLUSH(hw);
6278
6279         return 0;
6280 }
6281
6282 /* Config l2 tunnel ether type */
6283 static int
6284 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6285                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6286 {
6287         int ret = 0;
6288         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6289
6290         if (l2_tunnel == NULL)
6291                 return -EINVAL;
6292
6293         switch (l2_tunnel->l2_tunnel_type) {
6294         case RTE_L2_TUNNEL_TYPE_E_TAG:
6295                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6296                 break;
6297         default:
6298                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6299                 ret = -EINVAL;
6300                 break;
6301         }
6302
6303         return ret;
6304 }
6305
6306 /* Enable e-tag tunnel */
6307 static int
6308 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6309 {
6310         uint32_t etag_etype;
6311
6312         if (hw->mac.type != ixgbe_mac_X550 &&
6313             hw->mac.type != ixgbe_mac_X550EM_x) {
6314                 return -ENOTSUP;
6315         }
6316
6317         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6318         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6319         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6320         IXGBE_WRITE_FLUSH(hw);
6321
6322         return 0;
6323 }
6324
6325 /* Enable l2 tunnel */
6326 static int
6327 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6328                            enum rte_eth_tunnel_type l2_tunnel_type)
6329 {
6330         int ret = 0;
6331         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6332
6333         switch (l2_tunnel_type) {
6334         case RTE_L2_TUNNEL_TYPE_E_TAG:
6335                 ret = ixgbe_e_tag_enable(hw);
6336                 break;
6337         default:
6338                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6339                 ret = -EINVAL;
6340                 break;
6341         }
6342
6343         return ret;
6344 }
6345
6346 /* Disable e-tag tunnel */
6347 static int
6348 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6349 {
6350         uint32_t etag_etype;
6351
6352         if (hw->mac.type != ixgbe_mac_X550 &&
6353             hw->mac.type != ixgbe_mac_X550EM_x) {
6354                 return -ENOTSUP;
6355         }
6356
6357         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6358         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6359         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6360         IXGBE_WRITE_FLUSH(hw);
6361
6362         return 0;
6363 }
6364
6365 /* Disable l2 tunnel */
6366 static int
6367 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6368                             enum rte_eth_tunnel_type l2_tunnel_type)
6369 {
6370         int ret = 0;
6371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6372
6373         switch (l2_tunnel_type) {
6374         case RTE_L2_TUNNEL_TYPE_E_TAG:
6375                 ret = ixgbe_e_tag_disable(hw);
6376                 break;
6377         default:
6378                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6379                 ret = -EINVAL;
6380                 break;
6381         }
6382
6383         return ret;
6384 }
6385
6386 static int
6387 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6388                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6389 {
6390         int ret = 0;
6391         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6392         uint32_t i, rar_entries;
6393         uint32_t rar_low, rar_high;
6394
6395         if (hw->mac.type != ixgbe_mac_X550 &&
6396             hw->mac.type != ixgbe_mac_X550EM_x) {
6397                 return -ENOTSUP;
6398         }
6399
6400         rar_entries = ixgbe_get_num_rx_addrs(hw);
6401
6402         for (i = 1; i < rar_entries; i++) {
6403                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6404                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6405                 if ((rar_high & IXGBE_RAH_AV) &&
6406                     (rar_high & IXGBE_RAH_ADTYPE) &&
6407                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6408                      l2_tunnel->tunnel_id)) {
6409                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6410                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6411
6412                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6413
6414                         return ret;
6415                 }
6416         }
6417
6418         return ret;
6419 }
6420
6421 static int
6422 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6423                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6424 {
6425         int ret = 0;
6426         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6427         uint32_t i, rar_entries;
6428         uint32_t rar_low, rar_high;
6429
6430         if (hw->mac.type != ixgbe_mac_X550 &&
6431             hw->mac.type != ixgbe_mac_X550EM_x) {
6432                 return -ENOTSUP;
6433         }
6434
6435         /* One entry for one tunnel. Try to remove potential existing entry. */
6436         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6437
6438         rar_entries = ixgbe_get_num_rx_addrs(hw);
6439
6440         for (i = 1; i < rar_entries; i++) {
6441                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6442                 if (rar_high & IXGBE_RAH_AV) {
6443                         continue;
6444                 } else {
6445                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6446                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6447                         rar_low = l2_tunnel->tunnel_id;
6448
6449                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6450                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6451
6452                         return ret;
6453                 }
6454         }
6455
6456         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6457                      " Please remove a rule before adding a new one.");
6458         return -EINVAL;
6459 }
6460
6461 /* Add l2 tunnel filter */
6462 static int
6463 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6464                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6465 {
6466         int ret = 0;
6467
6468         switch (l2_tunnel->l2_tunnel_type) {
6469         case RTE_L2_TUNNEL_TYPE_E_TAG:
6470                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6471                 break;
6472         default:
6473                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6474                 ret = -EINVAL;
6475                 break;
6476         }
6477
6478         return ret;
6479 }
6480
6481 /* Delete l2 tunnel filter */
6482 static int
6483 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6484                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6485 {
6486         int ret = 0;
6487
6488         switch (l2_tunnel->l2_tunnel_type) {
6489         case RTE_L2_TUNNEL_TYPE_E_TAG:
6490                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6491                 break;
6492         default:
6493                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6494                 ret = -EINVAL;
6495                 break;
6496         }
6497
6498         return ret;
6499 }
6500
6501 /**
6502  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6503  * @dev: pointer to rte_eth_dev structure
6504  * @filter_op:operation will be taken.
6505  * @arg: a pointer to specific structure corresponding to the filter_op
6506  */
6507 static int
6508 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6509                                   enum rte_filter_op filter_op,
6510                                   void *arg)
6511 {
6512         int ret = 0;
6513
6514         if (filter_op == RTE_ETH_FILTER_NOP)
6515                 return 0;
6516
6517         if (arg == NULL) {
6518                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6519                             filter_op);
6520                 return -EINVAL;
6521         }
6522
6523         switch (filter_op) {
6524         case RTE_ETH_FILTER_ADD:
6525                 ret = ixgbe_dev_l2_tunnel_filter_add
6526                         (dev,
6527                          (struct rte_eth_l2_tunnel_conf *)arg);
6528                 break;
6529         case RTE_ETH_FILTER_DELETE:
6530                 ret = ixgbe_dev_l2_tunnel_filter_del
6531                         (dev,
6532                          (struct rte_eth_l2_tunnel_conf *)arg);
6533                 break;
6534         default:
6535                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6536                 ret = -EINVAL;
6537                 break;
6538         }
6539         return ret;
6540 }
6541
6542 static int
6543 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6544 {
6545         int ret = 0;
6546         uint32_t ctrl;
6547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6548
6549         if (hw->mac.type != ixgbe_mac_X550 &&
6550             hw->mac.type != ixgbe_mac_X550EM_x) {
6551                 return -ENOTSUP;
6552         }
6553
6554         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6555         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6556         if (en)
6557                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6558         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6559
6560         return ret;
6561 }
6562
6563 /* Enable l2 tunnel forwarding */
6564 static int
6565 ixgbe_dev_l2_tunnel_forwarding_enable
6566         (struct rte_eth_dev *dev,
6567          enum rte_eth_tunnel_type l2_tunnel_type)
6568 {
6569         int ret = 0;
6570
6571         switch (l2_tunnel_type) {
6572         case RTE_L2_TUNNEL_TYPE_E_TAG:
6573                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6574                 break;
6575         default:
6576                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6577                 ret = -EINVAL;
6578                 break;
6579         }
6580
6581         return ret;
6582 }
6583
6584 /* Disable l2 tunnel forwarding */
6585 static int
6586 ixgbe_dev_l2_tunnel_forwarding_disable
6587         (struct rte_eth_dev *dev,
6588          enum rte_eth_tunnel_type l2_tunnel_type)
6589 {
6590         int ret = 0;
6591
6592         switch (l2_tunnel_type) {
6593         case RTE_L2_TUNNEL_TYPE_E_TAG:
6594                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6595                 break;
6596         default:
6597                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6598                 ret = -EINVAL;
6599                 break;
6600         }
6601
6602         return ret;
6603 }
6604
6605 static int
6606 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6607                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6608                              bool en)
6609 {
6610         int ret = 0;
6611         uint32_t vmtir, vmvir;
6612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6613
6614         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6615                 PMD_DRV_LOG(ERR,
6616                             "VF id %u should be less than %u",
6617                             l2_tunnel->vf_id,
6618                             dev->pci_dev->max_vfs);
6619                 return -EINVAL;
6620         }
6621
6622         if (hw->mac.type != ixgbe_mac_X550 &&
6623             hw->mac.type != ixgbe_mac_X550EM_x) {
6624                 return -ENOTSUP;
6625         }
6626
6627         if (en)
6628                 vmtir = l2_tunnel->tunnel_id;
6629         else
6630                 vmtir = 0;
6631
6632         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6633
6634         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6635         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6636         if (en)
6637                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6638         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6639
6640         return ret;
6641 }
6642
6643 /* Enable l2 tunnel tag insertion */
6644 static int
6645 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6646                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6647 {
6648         int ret = 0;
6649
6650         switch (l2_tunnel->l2_tunnel_type) {
6651         case RTE_L2_TUNNEL_TYPE_E_TAG:
6652                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6653                 break;
6654         default:
6655                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6656                 ret = -EINVAL;
6657                 break;
6658         }
6659
6660         return ret;
6661 }
6662
6663 /* Disable l2 tunnel tag insertion */
6664 static int
6665 ixgbe_dev_l2_tunnel_insertion_disable
6666         (struct rte_eth_dev *dev,
6667          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6668 {
6669         int ret = 0;
6670
6671         switch (l2_tunnel->l2_tunnel_type) {
6672         case RTE_L2_TUNNEL_TYPE_E_TAG:
6673                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6674                 break;
6675         default:
6676                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6677                 ret = -EINVAL;
6678                 break;
6679         }
6680
6681         return ret;
6682 }
6683
6684 static int
6685 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6686                              bool en)
6687 {
6688         int ret = 0;
6689         uint32_t qde;
6690         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6691
6692         if (hw->mac.type != ixgbe_mac_X550 &&
6693             hw->mac.type != ixgbe_mac_X550EM_x) {
6694                 return -ENOTSUP;
6695         }
6696
6697         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6698         if (en)
6699                 qde |= IXGBE_QDE_STRIP_TAG;
6700         else
6701                 qde &= ~IXGBE_QDE_STRIP_TAG;
6702         qde &= ~IXGBE_QDE_READ;
6703         qde |= IXGBE_QDE_WRITE;
6704         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6705
6706         return ret;
6707 }
6708
6709 /* Enable l2 tunnel tag stripping */
6710 static int
6711 ixgbe_dev_l2_tunnel_stripping_enable
6712         (struct rte_eth_dev *dev,
6713          enum rte_eth_tunnel_type l2_tunnel_type)
6714 {
6715         int ret = 0;
6716
6717         switch (l2_tunnel_type) {
6718         case RTE_L2_TUNNEL_TYPE_E_TAG:
6719                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6720                 break;
6721         default:
6722                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6723                 ret = -EINVAL;
6724                 break;
6725         }
6726
6727         return ret;
6728 }
6729
6730 /* Disable l2 tunnel tag stripping */
6731 static int
6732 ixgbe_dev_l2_tunnel_stripping_disable
6733         (struct rte_eth_dev *dev,
6734          enum rte_eth_tunnel_type l2_tunnel_type)
6735 {
6736         int ret = 0;
6737
6738         switch (l2_tunnel_type) {
6739         case RTE_L2_TUNNEL_TYPE_E_TAG:
6740                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6741                 break;
6742         default:
6743                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6744                 ret = -EINVAL;
6745                 break;
6746         }
6747
6748         return ret;
6749 }
6750
6751 /* Enable/disable l2 tunnel offload functions */
6752 static int
6753 ixgbe_dev_l2_tunnel_offload_set
6754         (struct rte_eth_dev *dev,
6755          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6756          uint32_t mask,
6757          uint8_t en)
6758 {
6759         int ret = 0;
6760
6761         if (l2_tunnel == NULL)
6762                 return -EINVAL;
6763
6764         ret = -EINVAL;
6765         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6766                 if (en)
6767                         ret = ixgbe_dev_l2_tunnel_enable(
6768                                 dev,
6769                                 l2_tunnel->l2_tunnel_type);
6770                 else
6771                         ret = ixgbe_dev_l2_tunnel_disable(
6772                                 dev,
6773                                 l2_tunnel->l2_tunnel_type);
6774         }
6775
6776         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6777                 if (en)
6778                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6779                                 dev,
6780                                 l2_tunnel);
6781                 else
6782                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6783                                 dev,
6784                                 l2_tunnel);
6785         }
6786
6787         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6788                 if (en)
6789                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6790                                 dev,
6791                                 l2_tunnel->l2_tunnel_type);
6792                 else
6793                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6794                                 dev,
6795                                 l2_tunnel->l2_tunnel_type);
6796         }
6797
6798         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6799                 if (en)
6800                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6801                                 dev,
6802                                 l2_tunnel->l2_tunnel_type);
6803                 else
6804                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6805                                 dev,
6806                                 l2_tunnel->l2_tunnel_type);
6807         }
6808
6809         return ret;
6810 }
6811
6812 static int
6813 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6814                         uint16_t port)
6815 {
6816         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6817         IXGBE_WRITE_FLUSH(hw);
6818
6819         return 0;
6820 }
6821
6822 /* There's only one register for VxLAN UDP port.
6823  * So, we cannot add several ports. Will update it.
6824  */
6825 static int
6826 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6827                      uint16_t port)
6828 {
6829         if (port == 0) {
6830                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6831                 return -EINVAL;
6832         }
6833
6834         return ixgbe_update_vxlan_port(hw, port);
6835 }
6836
6837 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6838  * UDP port, it must have a value.
6839  * So, will reset it to the original value 0.
6840  */
6841 static int
6842 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6843                      uint16_t port)
6844 {
6845         uint16_t cur_port;
6846
6847         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6848
6849         if (cur_port != port) {
6850                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6851                 return -EINVAL;
6852         }
6853
6854         return ixgbe_update_vxlan_port(hw, 0);
6855 }
6856
6857 /* Add UDP tunneling port */
6858 static int
6859 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6860                               struct rte_eth_udp_tunnel *udp_tunnel)
6861 {
6862         int ret = 0;
6863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6864
6865         if (hw->mac.type != ixgbe_mac_X550 &&
6866             hw->mac.type != ixgbe_mac_X550EM_x) {
6867                 return -ENOTSUP;
6868         }
6869
6870         if (udp_tunnel == NULL)
6871                 return -EINVAL;
6872
6873         switch (udp_tunnel->prot_type) {
6874         case RTE_TUNNEL_TYPE_VXLAN:
6875                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6876                 break;
6877
6878         case RTE_TUNNEL_TYPE_GENEVE:
6879         case RTE_TUNNEL_TYPE_TEREDO:
6880                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6881                 ret = -EINVAL;
6882                 break;
6883
6884         default:
6885                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6886                 ret = -EINVAL;
6887                 break;
6888         }
6889
6890         return ret;
6891 }
6892
6893 /* Remove UDP tunneling port */
6894 static int
6895 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6896                               struct rte_eth_udp_tunnel *udp_tunnel)
6897 {
6898         int ret = 0;
6899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6900
6901         if (hw->mac.type != ixgbe_mac_X550 &&
6902             hw->mac.type != ixgbe_mac_X550EM_x) {
6903                 return -ENOTSUP;
6904         }
6905
6906         if (udp_tunnel == NULL)
6907                 return -EINVAL;
6908
6909         switch (udp_tunnel->prot_type) {
6910         case RTE_TUNNEL_TYPE_VXLAN:
6911                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
6912                 break;
6913         case RTE_TUNNEL_TYPE_GENEVE:
6914         case RTE_TUNNEL_TYPE_TEREDO:
6915                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6916                 ret = -EINVAL;
6917                 break;
6918         default:
6919                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6920                 ret = -EINVAL;
6921                 break;
6922         }
6923
6924         return ret;
6925 }
6926
6927 static struct rte_driver rte_ixgbe_driver = {
6928         .type = PMD_PDEV,
6929         .init = rte_ixgbe_pmd_init,
6930 };
6931
6932 static struct rte_driver rte_ixgbevf_driver = {
6933         .type = PMD_PDEV,
6934         .init = rte_ixgbevf_pmd_init,
6935 };
6936
6937 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6938 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);