drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 /* Additional timesync values. */
 104 #define NSEC_PER_SEC             1000000000L
 105 #define IXGBE_INCVAL_10GB        0x66666666
 106 #define IXGBE_INCVAL_1GB         0x40000000
 107 #define IXGBE_INCVAL_100         0x50000000
 108 #define IXGBE_INCVAL_SHIFT_10GB  28
 109 #define IXGBE_INCVAL_SHIFT_1GB   24
 110 #define IXGBE_INCVAL_SHIFT_100   21
 111 #define IXGBE_INCVAL_SHIFT_82599 7
 112 #define IXGBE_INCPER_SHIFT_82599 24
 113
 114 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 117 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 118 #define IXGBE_ETAG_ETYPE                       0x00005084
 119 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 120 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 121 #define IXGBE_RAH_ADTYPE                       0x40000000
 122 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 123 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 124 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 125 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 126 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 127 #define IXGBE_VTEICR_MASK                      0x07
 128
 129 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 130 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 131
 132 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 133 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 151                                 int wait_to_complete);
 152 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 153                                 struct rte_eth_stats *stats);
 154 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 155                                 struct rte_eth_xstat *xstats, unsigned n);
 156 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 157                                   struct rte_eth_xstat *xstats, unsigned n);
 158 static int
 159 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 160                 uint64_t *values, unsigned int n);
 161 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 163 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names,
 165         unsigned int size);
 166 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 168 static int ixgbe_dev_xstats_get_names_by_id(
 169         struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         const uint64_t *ids,
 172         unsigned int limit);
 173 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 174                                              uint16_t queue_id,
 175                                              uint8_t stat_idx,
 176                                              uint8_t is_rx);
 177 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 178                                  size_t fw_size);
 179 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 180                                struct rte_eth_dev_info *dev_info);
 181 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 182 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 183                                  struct rte_eth_dev_info *dev_info);
 184 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 185
 186 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 187                 uint16_t vlan_id, int on);
 188 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 189                                enum rte_vlan_type vlan_type,
 190                                uint16_t tpid_id);
 191 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 192                 uint16_t queue, bool on);
 193 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 194                 int on);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 221                                       struct rte_intr_handle *handle);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 225                          uint32_t index, uint32_t pool);
 226 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 227 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 228                                            struct ether_addr *mac_addr);
 229 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 230 static bool is_device_supported(struct rte_eth_dev *dev,
 231                                 struct rte_pci_driver *drv);
 232
 233 /* For Virtual Function support */
 234 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 235 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 236 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 237 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 238 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 239                                    int wait_to_complete);
 240 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 242 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 245 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 255                                             uint16_t queue_id);
 256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 257                                              uint16_t queue_id);
 258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 259                                  uint8_t queue, uint8_t msix_vector);
 260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 263
 264 /* For Eth VMDQ APIs support */
 265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 266                 ether_addr * mac_addr, uint8_t on);
 267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 268 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 269                 struct rte_eth_mirror_conf *mirror_conf,
 270                 uint8_t rule_id, uint8_t on);
 271 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 272                 uint8_t rule_id);
 273 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 274                                           uint16_t queue_id);
 275 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 276                                            uint16_t queue_id);
 277 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 278                                uint8_t queue, uint8_t msix_vector);
 279 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 280
 281 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 282                                 struct ether_addr *mac_addr,
 283                                 uint32_t index, uint32_t pool);
 284 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 285 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 286                                              struct ether_addr *mac_addr);
 287 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 288                         struct rte_eth_syn_filter *filter);
 289 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 290                         enum rte_filter_op filter_op,
 291                         void *arg);
 292 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 293                         struct ixgbe_5tuple_filter *filter);
 294 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 295                         struct ixgbe_5tuple_filter *filter);
 296 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 297                                 enum rte_filter_op filter_op,
 298                                 void *arg);
 299 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 300                         struct rte_eth_ntuple_filter *filter);
 301 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 302                                 enum rte_filter_op filter_op,
 303                                 void *arg);
 304 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 305                         struct rte_eth_ethertype_filter *filter);
 306 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 307                      enum rte_filter_type filter_type,
 308                      enum rte_filter_op filter_op,
 309                      void *arg);
 310 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 311
 312 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 313                                       struct ether_addr *mc_addr_set,
 314                                       uint32_t nb_mc_addr);
 315 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 316                                    struct rte_eth_dcb_info *dcb_info);
 317
 318 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 319 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 320                             struct rte_dev_reg_info *regs);
 321 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 323                                 struct rte_dev_eeprom_info *eeprom);
 324 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 325                                 struct rte_dev_eeprom_info *eeprom);
 326
 327 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 328                                  struct rte_eth_dev_module_info *modinfo);
 329 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 330                                    struct rte_dev_eeprom_info *info);
 331
 332 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 334                                 struct rte_dev_reg_info *regs);
 335
 336 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 339                                             struct timespec *timestamp,
 340                                             uint32_t flags);
 341 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 342                                             struct timespec *timestamp);
 343 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 344 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 345                                    struct timespec *timestamp);
 346 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 347                                    const struct timespec *timestamp);
 348 static void ixgbevf_dev_interrupt_handler(void *param);
 349
 350 static int ixgbe_dev_l2_tunnel_eth_type_conf
 351         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 352 static int ixgbe_dev_l2_tunnel_offload_set
 353         (struct rte_eth_dev *dev,
 354          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 355          uint32_t mask,
 356          uint8_t en);
 357 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 358                                              enum rte_filter_op filter_op,
 359                                              void *arg);
 360
 361 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 364                                          struct rte_eth_udp_tunnel *udp_tunnel);
 365 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 366 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 367
 368 /*
 369  * Define VF Stats MACRO for Non "cleared on read" register
 370  */
 371 #define UPDATE_VF_STAT(reg, last, cur)                          \
 372 {                                                               \
 373         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 374         cur += (latest - last) & UINT_MAX;                      \
 375         last = latest;                                          \
 376 }
 377
 378 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 379 {                                                                \
 380         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 381         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 382         u64 latest = ((new_msb << 32) | new_lsb);                \
 383         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 384         last = latest;                                           \
 385 }
 386
 387 #define IXGBE_SET_HWSTRIP(h, q) do {\
 388                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 389                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 390                 (h)->bitmap[idx] |= 1 << bit;\
 391         } while (0)
 392
 393 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 394                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 395                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 396                 (h)->bitmap[idx] &= ~(1 << bit);\
 397         } while (0)
 398
 399 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 400                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 402                 (r) = (h)->bitmap[idx] >> bit & 1;\
 403         } while (0)
 404
 405 int ixgbe_logtype_init;
 406 int ixgbe_logtype_driver;
 407
 408 /*
 409  * The set of PCI devices this driver supports
 410  */
 411 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 460 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 462 #endif
 463         { .vendor_id = 0, /* sentinel */ },
 464 };
 465
 466 /*
 467  * The set of PCI devices this driver supports (for 82599 VF)
 468  */
 469 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 480         { .vendor_id = 0, /* sentinel */ },
 481 };
 482
 483 static const struct rte_eth_desc_lim rx_desc_lim = {
 484         .nb_max = IXGBE_MAX_RING_DESC,
 485         .nb_min = IXGBE_MIN_RING_DESC,
 486         .nb_align = IXGBE_RXD_ALIGN,
 487 };
 488
 489 static const struct rte_eth_desc_lim tx_desc_lim = {
 490         .nb_max = IXGBE_MAX_RING_DESC,
 491         .nb_min = IXGBE_MIN_RING_DESC,
 492         .nb_align = IXGBE_TXD_ALIGN,
 493         .nb_seg_max = IXGBE_TX_MAX_SEG,
 494         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 495 };
 496
 497 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 498         .dev_configure        = ixgbe_dev_configure,
 499         .dev_start            = ixgbe_dev_start,
 500         .dev_stop             = ixgbe_dev_stop,
 501         .dev_set_link_up    = ixgbe_dev_set_link_up,
 502         .dev_set_link_down  = ixgbe_dev_set_link_down,
 503         .dev_close            = ixgbe_dev_close,
 504         .dev_reset            = ixgbe_dev_reset,
 505         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 506         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 507         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 508         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 509         .link_update          = ixgbe_dev_link_update,
 510         .stats_get            = ixgbe_dev_stats_get,
 511         .xstats_get           = ixgbe_dev_xstats_get,
 512         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 513         .stats_reset          = ixgbe_dev_stats_reset,
 514         .xstats_reset         = ixgbe_dev_xstats_reset,
 515         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 516         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 517         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 518         .fw_version_get       = ixgbe_fw_version_get,
 519         .dev_infos_get        = ixgbe_dev_info_get,
 520         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 521         .mtu_set              = ixgbe_dev_mtu_set,
 522         .vlan_filter_set      = ixgbe_vlan_filter_set,
 523         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 524         .vlan_offload_set     = ixgbe_vlan_offload_set,
 525         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 526         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 527         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 528         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 529         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 530         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 531         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 532         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 533         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 534         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 535         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 536         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 537         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 538         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 539         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 540         .dev_led_on           = ixgbe_dev_led_on,
 541         .dev_led_off          = ixgbe_dev_led_off,
 542         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 543         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 544         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 545         .mac_addr_add         = ixgbe_add_rar,
 546         .mac_addr_remove      = ixgbe_remove_rar,
 547         .mac_addr_set         = ixgbe_set_default_mac_addr,
 548         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 549         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 550         .mirror_rule_set      = ixgbe_mirror_rule_set,
 551         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 552         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 553         .reta_update          = ixgbe_dev_rss_reta_update,
 554         .reta_query           = ixgbe_dev_rss_reta_query,
 555         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 556         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 557         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 558         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 559         .rxq_info_get         = ixgbe_rxq_info_get,
 560         .txq_info_get         = ixgbe_txq_info_get,
 561         .timesync_enable      = ixgbe_timesync_enable,
 562         .timesync_disable     = ixgbe_timesync_disable,
 563         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 564         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 565         .get_reg              = ixgbe_get_regs,
 566         .get_eeprom_length    = ixgbe_get_eeprom_length,
 567         .get_eeprom           = ixgbe_get_eeprom,
 568         .set_eeprom           = ixgbe_set_eeprom,
 569         .get_module_info      = ixgbe_get_module_info,
 570         .get_module_eeprom    = ixgbe_get_module_eeprom,
 571         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 572         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 573         .timesync_read_time   = ixgbe_timesync_read_time,
 574         .timesync_write_time  = ixgbe_timesync_write_time,
 575         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 576         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 577         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 578         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 579         .tm_ops_get           = ixgbe_tm_ops_get,
 580 };
 581
 582 /*
 583  * dev_ops for virtual function, bare necessities for basic vf
 584  * operation have been implemented
 585  */
 586 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 587         .dev_configure        = ixgbevf_dev_configure,
 588         .dev_start            = ixgbevf_dev_start,
 589         .dev_stop             = ixgbevf_dev_stop,
 590         .link_update          = ixgbevf_dev_link_update,
 591         .stats_get            = ixgbevf_dev_stats_get,
 592         .xstats_get           = ixgbevf_dev_xstats_get,
 593         .stats_reset          = ixgbevf_dev_stats_reset,
 594         .xstats_reset         = ixgbevf_dev_stats_reset,
 595         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 596         .dev_close            = ixgbevf_dev_close,
 597         .dev_reset            = ixgbevf_dev_reset,
 598         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 599         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 600         .dev_infos_get        = ixgbevf_dev_info_get,
 601         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 602         .mtu_set              = ixgbevf_dev_set_mtu,
 603         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 604         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 605         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 606         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 607         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 608         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 609         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 610         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 611         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 612         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 613         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 614         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 615         .mac_addr_add         = ixgbevf_add_mac_addr,
 616         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 617         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 618         .rxq_info_get         = ixgbe_rxq_info_get,
 619         .txq_info_get         = ixgbe_txq_info_get,
 620         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 621         .get_reg              = ixgbevf_get_regs,
 622         .reta_update          = ixgbe_dev_rss_reta_update,
 623         .reta_query           = ixgbe_dev_rss_reta_query,
 624         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 625         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 626 };
 627
 628 /* store statistics names and its offset in stats structure */
 629 struct rte_ixgbe_xstats_name_off {
 630         char name[RTE_ETH_XSTATS_NAME_SIZE];
 631         unsigned offset;
 632 };
 633
 634 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 635         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 636         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 637         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 638         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 639         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 640         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 641         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 642         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 643         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 644         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 645         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 646         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 647         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 648         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 649         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 650                 prc1023)},
 651         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 652                 prc1522)},
 653         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 654         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 655         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 656         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 657         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 658         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 659         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 660         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 661         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 662         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 663         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 664         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 665         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 666         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 667         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 668         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 669         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 670                 ptc1023)},
 671         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 672                 ptc1522)},
 673         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 674         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 675         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 676         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 677
 678         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 679                 fdirustat_add)},
 680         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 681                 fdirustat_remove)},
 682         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 683                 fdirfstat_fadd)},
 684         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 685                 fdirfstat_fremove)},
 686         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 687                 fdirmatch)},
 688         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 689                 fdirmiss)},
 690
 691         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 692         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 693         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 694                 fclast)},
 695         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 696         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 697         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 698         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 699         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 700                 fcoe_noddp)},
 701         {"rx_fcoe_no_direct_data_placement_ext_buff",
 702                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 703
 704         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxontxc)},
 706         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxonrxc)},
 708         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 709                 lxofftxc)},
 710         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 711                 lxoffrxc)},
 712         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 713 };
 714
 715 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 716                            sizeof(rte_ixgbe_stats_strings[0]))
 717
 718 /* MACsec statistics */
 719 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 720         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_untagged)},
 722         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_pkts_encrypted)},
 724         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_pkts_protected)},
 726         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 727                 out_octets_encrypted)},
 728         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 729                 out_octets_protected)},
 730         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_untagged)},
 732         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_badtag)},
 734         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 735                 in_pkts_nosci)},
 736         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_unknownsci)},
 738         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 739                 in_octets_decrypted)},
 740         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 741                 in_octets_validated)},
 742         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_unchecked)},
 744         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_delayed)},
 746         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_late)},
 748         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_ok)},
 750         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_invalid)},
 752         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notvalid)},
 754         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_unusedsa)},
 756         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_notusingsa)},
 758 };
 759
 760 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 761                            sizeof(rte_ixgbe_macsec_strings[0]))
 762
 763 /* Per-queue statistics */
 764 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 765         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 766         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 767         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 768         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 769 };
 770
 771 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 772                            sizeof(rte_ixgbe_rxq_strings[0]))
 773 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 774
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 776         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 777         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 778         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 779                 pxon2offc)},
 780 };
 781
 782 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 783                            sizeof(rte_ixgbe_txq_strings[0]))
 784 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 785
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 787         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 788 };
 789
 790 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 791                 sizeof(rte_ixgbevf_stats_strings[0]))
 792
 793 /*
 794  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 795  */
 796 static inline int
 797 ixgbe_is_sfp(struct ixgbe_hw *hw)
 798 {
 799         switch (hw->phy.type) {
 800         case ixgbe_phy_sfp_avago:
 801         case ixgbe_phy_sfp_ftl:
 802         case ixgbe_phy_sfp_intel:
 803         case ixgbe_phy_sfp_unknown:
 804         case ixgbe_phy_sfp_passive_tyco:
 805         case ixgbe_phy_sfp_passive_unknown:
 806                 return 1;
 807         default:
 808                 return 0;
 809         }
 810 }
 811
 812 static inline int32_t
 813 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 814 {
 815         uint32_t ctrl_ext;
 816         int32_t status;
 817
 818         status = ixgbe_reset_hw(hw);
 819
 820         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 821         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 822         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 823         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 824         IXGBE_WRITE_FLUSH(hw);
 825
 826         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 827                 status = IXGBE_SUCCESS;
 828         return status;
 829 }
 830
 831 static inline void
 832 ixgbe_enable_intr(struct rte_eth_dev *dev)
 833 {
 834         struct ixgbe_interrupt *intr =
 835                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 836         struct ixgbe_hw *hw =
 837                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 838
 839         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 840         IXGBE_WRITE_FLUSH(hw);
 841 }
 842
 843 /*
 844  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 845  */
 846 static void
 847 ixgbe_disable_intr(struct ixgbe_hw *hw)
 848 {
 849         PMD_INIT_FUNC_TRACE();
 850
 851         if (hw->mac.type == ixgbe_mac_82598EB) {
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 853         } else {
 854                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 857         }
 858         IXGBE_WRITE_FLUSH(hw);
 859 }
 860
 861 /*
 862  * This function resets queue statistics mapping registers.
 863  * From Niantic datasheet, Initialization of Statistics section:
 864  * "...if software requires the queue counters, the RQSMR and TQSM registers
 865  * must be re-programmed following a device reset.
 866  */
 867 static void
 868 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 869 {
 870         uint32_t i;
 871
 872         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 873                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 874                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 875         }
 876 }
 877
 878
 879 static int
 880 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 881                                   uint16_t queue_id,
 882                                   uint8_t stat_idx,
 883                                   uint8_t is_rx)
 884 {
 885 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 886 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 887 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 888
 889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 890         struct ixgbe_stat_mapping_registers *stat_mappings =
 891                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 892         uint32_t qsmr_mask = 0;
 893         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 894         uint32_t q_map;
 895         uint8_t n, offset;
 896
 897         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 898                 (hw->mac.type != ixgbe_mac_X540) &&
 899                 (hw->mac.type != ixgbe_mac_X550) &&
 900                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_a))
 902                 return -ENOSYS;
 903
 904         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 905                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 906                      queue_id, stat_idx);
 907
 908         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 909         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 910                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 911                 return -EIO;
 912         }
 913         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 914
 915         /* Now clear any previous stat_idx set */
 916         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 917         if (!is_rx)
 918                 stat_mappings->tqsm[n] &= ~clearing_mask;
 919         else
 920                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 921
 922         q_map = (uint32_t)stat_idx;
 923         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 924         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 925         if (!is_rx)
 926                 stat_mappings->tqsm[n] |= qsmr_mask;
 927         else
 928                 stat_mappings->rqsmr[n] |= qsmr_mask;
 929
 930         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 931                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 932                      queue_id, stat_idx);
 933         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 934                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 935
 936         /* Now write the mapping in the appropriate register */
 937         if (is_rx) {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 939                              stat_mappings->rqsmr[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 941         } else {
 942                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 943                              stat_mappings->tqsm[n], n);
 944                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 945         }
 946         return 0;
 947 }
 948
 949 static void
 950 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 951 {
 952         struct ixgbe_stat_mapping_registers *stat_mappings =
 953                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 955         int i;
 956
 957         /* write whatever was in stat mapping table to the NIC */
 958         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 959                 /* rx */
 960                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 961
 962                 /* tx */
 963                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 964         }
 965 }
 966
 967 static void
 968 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 969 {
 970         uint8_t i;
 971         struct ixgbe_dcb_tc_config *tc;
 972         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 973
 974         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 975         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 976         for (i = 0; i < dcb_max_tc; i++) {
 977                 tc = &dcb_config->tc_config[i];
 978                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 980                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 981                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 983                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 984                 tc->pfc = ixgbe_dcb_pfc_disabled;
 985         }
 986
 987         /* Initialize default user to priority mapping, UPx->TC0 */
 988         tc = &dcb_config->tc_config[0];
 989         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 990         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 992                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 993                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 994         }
 995         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 996         dcb_config->pfc_mode_enable = false;
 997         dcb_config->vt_mode = true;
 998         dcb_config->round_robin_enable = false;
 999         /* support all DCB capabilities in 82599 */
1000         dcb_config->support.capabilities = 0xFF;
1001
1002         /*we only support 4 Tcs for X540, X550 */
1003         if (hw->mac.type == ixgbe_mac_X540 ||
1004                 hw->mac.type == ixgbe_mac_X550 ||
1005                 hw->mac.type == ixgbe_mac_X550EM_x ||
1006                 hw->mac.type == ixgbe_mac_X550EM_a) {
1007                 dcb_config->num_tcs.pg_tcs = 4;
1008                 dcb_config->num_tcs.pfc_tcs = 4;
1009         }
1010 }
1011
1012 /*
1013  * Ensure that all locks are released before first NVM or PHY access
1014  */
1015 static void
1016 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1017 {
1018         uint16_t mask;
1019
1020         /*
1021          * Phy lock should not fail in this early stage. If this is the case,
1022          * it is due to an improper exit of the application.
1023          * So force the release of the faulty lock. Release of common lock
1024          * is done automatically by swfw_sync function.
1025          */
1026         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1027         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1028                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1029         }
1030         ixgbe_release_swfw_semaphore(hw, mask);
1031
1032         /*
1033          * These ones are more tricky since they are common to all ports; but
1034          * swfw_sync retries last long enough (1s) to be almost sure that if
1035          * lock can not be taken it is due to an improper lock of the
1036          * semaphore.
1037          */
1038         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1039         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1040                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1041         }
1042         ixgbe_release_swfw_semaphore(hw, mask);
1043 }
1044
1045 /*
1046  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1047  * It returns 0 on success.
1048  */
1049 static int
1050 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1051 {
1052         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1053         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1054         struct ixgbe_hw *hw =
1055                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1056         struct ixgbe_vfta *shadow_vfta =
1057                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1058         struct ixgbe_hwstrip *hwstrip =
1059                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1060         struct ixgbe_dcb_config *dcb_config =
1061                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1062         struct ixgbe_filter_info *filter_info =
1063                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1064         struct ixgbe_bw_conf *bw_conf =
1065                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1066         uint32_t ctrl_ext;
1067         uint16_t csum;
1068         int diag, i;
1069
1070         PMD_INIT_FUNC_TRACE();
1071
1072         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1073         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1074         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1075         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1076
1077         /*
1078          * For secondary processes, we don't initialise any further as primary
1079          * has already done this work. Only check we don't need a different
1080          * RX and TX function.
1081          */
1082         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1083                 struct ixgbe_tx_queue *txq;
1084                 /* TX queue function in primary, set by last queue initialized
1085                  * Tx queue may not initialized by primary process
1086                  */
1087                 if (eth_dev->data->tx_queues) {
1088                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1089                         ixgbe_set_tx_function(eth_dev, txq);
1090                 } else {
1091                         /* Use default TX function if we get here */
1092                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1093                                      "Using default TX function.");
1094                 }
1095
1096                 ixgbe_set_rx_function(eth_dev);
1097
1098                 return 0;
1099         }
1100
1101         rte_eth_copy_pci_info(eth_dev, pci_dev);
1102
1103         /* Vendor and Device ID need to be set before init of shared code */
1104         hw->device_id = pci_dev->id.device_id;
1105         hw->vendor_id = pci_dev->id.vendor_id;
1106         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1107         hw->allow_unsupported_sfp = 1;
1108
1109         /* Initialize the shared code (base driver) */
1110 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1111         diag = ixgbe_bypass_init_shared_code(hw);
1112 #else
1113         diag = ixgbe_init_shared_code(hw);
1114 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1115
1116         if (diag != IXGBE_SUCCESS) {
1117                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1118                 return -EIO;
1119         }
1120
1121         /* pick up the PCI bus settings for reporting later */
1122         ixgbe_get_bus_info(hw);
1123
1124         /* Unlock any pending hardware semaphore */
1125         ixgbe_swfw_lock_reset(hw);
1126
1127 #ifdef RTE_LIBRTE_SECURITY
1128         /* Initialize security_ctx only for primary process*/
1129         if (ixgbe_ipsec_ctx_create(eth_dev))
1130                 return -ENOMEM;
1131 #endif
1132
1133         /* Initialize DCB configuration*/
1134         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1135         ixgbe_dcb_init(hw, dcb_config);
1136         /* Get Hardware Flow Control setting */
1137         hw->fc.requested_mode = ixgbe_fc_full;
1138         hw->fc.current_mode = ixgbe_fc_full;
1139         hw->fc.pause_time = IXGBE_FC_PAUSE;
1140         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1141                 hw->fc.low_water[i] = IXGBE_FC_LO;
1142                 hw->fc.high_water[i] = IXGBE_FC_HI;
1143         }
1144         hw->fc.send_xon = 1;
1145
1146         /* Make sure we have a good EEPROM before we read from it */
1147         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1150                 return -EIO;
1151         }
1152
1153 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1154         diag = ixgbe_bypass_init_hw(hw);
1155 #else
1156         diag = ixgbe_init_hw(hw);
1157 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1158
1159         /*
1160          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1161          * is called too soon after the kernel driver unbinding/binding occurs.
1162          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1163          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1164          * also called. See ixgbe_identify_phy_82599(). The reason for the
1165          * failure is not known, and only occuts when virtualisation features
1166          * are disabled in the bios. A delay of 100ms  was found to be enough by
1167          * trial-and-error, and is doubled to be safe.
1168          */
1169         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1170                 rte_delay_ms(200);
1171                 diag = ixgbe_init_hw(hw);
1172         }
1173
1174         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1175                 diag = IXGBE_SUCCESS;
1176
1177         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1178                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1179                              "LOM.  Please be aware there may be issues associated "
1180                              "with your hardware.");
1181                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1182                              "please contact your Intel or hardware representative "
1183                              "who provided you with this hardware.");
1184         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1185                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1186         if (diag) {
1187                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1188                 return -EIO;
1189         }
1190
1191         /* Reset the hw statistics */
1192         ixgbe_dev_stats_reset(eth_dev);
1193
1194         /* disable interrupt */
1195         ixgbe_disable_intr(hw);
1196
1197         /* reset mappings for queue statistics hw counters*/
1198         ixgbe_reset_qstat_mappings(hw);
1199
1200         /* Allocate memory for storing MAC addresses */
1201         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1202                                                hw->mac.num_rar_entries, 0);
1203         if (eth_dev->data->mac_addrs == NULL) {
1204                 PMD_INIT_LOG(ERR,
1205                              "Failed to allocate %u bytes needed to store "
1206                              "MAC addresses",
1207                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1208                 return -ENOMEM;
1209         }
1210         /* Copy the permanent MAC address */
1211         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1212                         &eth_dev->data->mac_addrs[0]);
1213
1214         /* Allocate memory for storing hash filter MAC addresses */
1215         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1216                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1217         if (eth_dev->data->hash_mac_addrs == NULL) {
1218                 PMD_INIT_LOG(ERR,
1219                              "Failed to allocate %d bytes needed to store MAC addresses",
1220                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1221                 return -ENOMEM;
1222         }
1223
1224         /* initialize the vfta */
1225         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1226
1227         /* initialize the hw strip bitmap*/
1228         memset(hwstrip, 0, sizeof(*hwstrip));
1229
1230         /* initialize PF if max_vfs not zero */
1231         ixgbe_pf_host_init(eth_dev);
1232
1233         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1234         /* let hardware know driver is loaded */
1235         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1236         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1237         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1238         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1239         IXGBE_WRITE_FLUSH(hw);
1240
1241         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type,
1244                              (int) hw->phy.sfp_type);
1245         else
1246                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1247                              (int) hw->mac.type, (int) hw->phy.type);
1248
1249         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1250                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1251                      pci_dev->id.device_id);
1252
1253         rte_intr_callback_register(intr_handle,
1254                                    ixgbe_dev_interrupt_handler, eth_dev);
1255
1256         /* enable uio/vfio intr/eventfd mapping */
1257         rte_intr_enable(intr_handle);
1258
1259         /* enable support intr */
1260         ixgbe_enable_intr(eth_dev);
1261
1262         /* initialize filter info */
1263         memset(filter_info, 0,
1264                sizeof(struct ixgbe_filter_info));
1265
1266         /* initialize 5tuple filter list */
1267         TAILQ_INIT(&filter_info->fivetuple_list);
1268
1269         /* initialize flow director filter list & hash */
1270         ixgbe_fdir_filter_init(eth_dev);
1271
1272         /* initialize l2 tunnel filter list & hash */
1273         ixgbe_l2_tn_filter_init(eth_dev);
1274
1275         /* initialize flow filter lists */
1276         ixgbe_filterlist_init();
1277
1278         /* initialize bandwidth configuration info */
1279         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1280
1281         /* initialize Traffic Manager configuration */
1282         ixgbe_tm_conf_init(eth_dev);
1283
1284         return 0;
1285 }
1286
1287 static int
1288 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1289 {
1290         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1291         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1292         struct ixgbe_hw *hw;
1293         int retries = 0;
1294         int ret;
1295
1296         PMD_INIT_FUNC_TRACE();
1297
1298         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1299                 return -EPERM;
1300
1301         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1302
1303         if (hw->adapter_stopped == 0)
1304                 ixgbe_dev_close(eth_dev);
1305
1306         eth_dev->dev_ops = NULL;
1307         eth_dev->rx_pkt_burst = NULL;
1308         eth_dev->tx_pkt_burst = NULL;
1309
1310         /* Unlock any pending hardware semaphore */
1311         ixgbe_swfw_lock_reset(hw);
1312
1313         /* disable uio intr before callback unregister */
1314         rte_intr_disable(intr_handle);
1315
1316         do {
1317                 ret = rte_intr_callback_unregister(intr_handle,
1318                                 ixgbe_dev_interrupt_handler, eth_dev);
1319                 if (ret >= 0) {
1320                         break;
1321                 } else if (ret != -EAGAIN) {
1322                         PMD_INIT_LOG(ERR,
1323                                 "intr callback unregister failed: %d",
1324                                 ret);
1325                         return ret;
1326                 }
1327                 rte_delay_ms(100);
1328         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1329
1330         /* uninitialize PF if max_vfs not zero */
1331         ixgbe_pf_host_uninit(eth_dev);
1332
1333         rte_free(eth_dev->data->mac_addrs);
1334         eth_dev->data->mac_addrs = NULL;
1335
1336         rte_free(eth_dev->data->hash_mac_addrs);
1337         eth_dev->data->hash_mac_addrs = NULL;
1338
1339         /* remove all the fdir filters & hash */
1340         ixgbe_fdir_filter_uninit(eth_dev);
1341
1342         /* remove all the L2 tunnel filters & hash */
1343         ixgbe_l2_tn_filter_uninit(eth_dev);
1344
1345         /* Remove all ntuple filters of the device */
1346         ixgbe_ntuple_filter_uninit(eth_dev);
1347
1348         /* clear all the filters list */
1349         ixgbe_filterlist_flush();
1350
1351         /* Remove all Traffic Manager configuration */
1352         ixgbe_tm_conf_uninit(eth_dev);
1353
1354 #ifdef RTE_LIBRTE_SECURITY
1355         rte_free(eth_dev->security_ctx);
1356 #endif
1357
1358         return 0;
1359 }
1360
1361 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1362 {
1363         struct ixgbe_filter_info *filter_info =
1364                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1365         struct ixgbe_5tuple_filter *p_5tuple;
1366
1367         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1368                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1369                              p_5tuple,
1370                              entries);
1371                 rte_free(p_5tuple);
1372         }
1373         memset(filter_info->fivetuple_mask, 0,
1374                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1375
1376         return 0;
1377 }
1378
1379 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1380 {
1381         struct ixgbe_hw_fdir_info *fdir_info =
1382                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1383         struct ixgbe_fdir_filter *fdir_filter;
1384
1385                 if (fdir_info->hash_map)
1386                 rte_free(fdir_info->hash_map);
1387         if (fdir_info->hash_handle)
1388                 rte_hash_free(fdir_info->hash_handle);
1389
1390         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1391                 TAILQ_REMOVE(&fdir_info->fdir_list,
1392                              fdir_filter,
1393                              entries);
1394                 rte_free(fdir_filter);
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1401 {
1402         struct ixgbe_l2_tn_info *l2_tn_info =
1403                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1404         struct ixgbe_l2_tn_filter *l2_tn_filter;
1405
1406         if (l2_tn_info->hash_map)
1407                 rte_free(l2_tn_info->hash_map);
1408         if (l2_tn_info->hash_handle)
1409                 rte_hash_free(l2_tn_info->hash_handle);
1410
1411         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1412                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1413                              l2_tn_filter,
1414                              entries);
1415                 rte_free(l2_tn_filter);
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1422 {
1423         struct ixgbe_hw_fdir_info *fdir_info =
1424                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1425         char fdir_hash_name[RTE_HASH_NAMESIZE];
1426         struct rte_hash_parameters fdir_hash_params = {
1427                 .name = fdir_hash_name,
1428                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1429                 .key_len = sizeof(union ixgbe_atr_input),
1430                 .hash_func = rte_hash_crc,
1431                 .hash_func_init_val = 0,
1432                 .socket_id = rte_socket_id(),
1433         };
1434
1435         TAILQ_INIT(&fdir_info->fdir_list);
1436         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1437                  "fdir_%s", eth_dev->device->name);
1438         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1439         if (!fdir_info->hash_handle) {
1440                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1441                 return -EINVAL;
1442         }
1443         fdir_info->hash_map = rte_zmalloc("ixgbe",
1444                                           sizeof(struct ixgbe_fdir_filter *) *
1445                                           IXGBE_MAX_FDIR_FILTER_NUM,
1446                                           0);
1447         if (!fdir_info->hash_map) {
1448                 PMD_INIT_LOG(ERR,
1449                              "Failed to allocate memory for fdir hash map!");
1450                 return -ENOMEM;
1451         }
1452         fdir_info->mask_added = FALSE;
1453
1454         return 0;
1455 }
1456
1457 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1458 {
1459         struct ixgbe_l2_tn_info *l2_tn_info =
1460                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1461         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1462         struct rte_hash_parameters l2_tn_hash_params = {
1463                 .name = l2_tn_hash_name,
1464                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1465                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1466                 .hash_func = rte_hash_crc,
1467                 .hash_func_init_val = 0,
1468                 .socket_id = rte_socket_id(),
1469         };
1470
1471         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1472         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1473                  "l2_tn_%s", eth_dev->device->name);
1474         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1475         if (!l2_tn_info->hash_handle) {
1476                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1477                 return -EINVAL;
1478         }
1479         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1480                                    sizeof(struct ixgbe_l2_tn_filter *) *
1481                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1482                                    0);
1483         if (!l2_tn_info->hash_map) {
1484                 PMD_INIT_LOG(ERR,
1485                         "Failed to allocate memory for L2 TN hash map!");
1486                 return -ENOMEM;
1487         }
1488         l2_tn_info->e_tag_en = FALSE;
1489         l2_tn_info->e_tag_fwd_en = FALSE;
1490         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1491
1492         return 0;
1493 }
1494 /*
1495  * Negotiate mailbox API version with the PF.
1496  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1497  * Then we try to negotiate starting with the most recent one.
1498  * If all negotiation attempts fail, then we will proceed with
1499  * the default one (ixgbe_mbox_api_10).
1500  */
1501 static void
1502 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1503 {
1504         int32_t i;
1505
1506         /* start with highest supported, proceed down */
1507         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1508                 ixgbe_mbox_api_12,
1509                 ixgbe_mbox_api_11,
1510                 ixgbe_mbox_api_10,
1511         };
1512
1513         for (i = 0;
1514                         i != RTE_DIM(sup_ver) &&
1515                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1516                         i++)
1517                 ;
1518 }
1519
1520 static void
1521 generate_random_mac_addr(struct ether_addr *mac_addr)
1522 {
1523         uint64_t random;
1524
1525         /* Set Organizationally Unique Identifier (OUI) prefix. */
1526         mac_addr->addr_bytes[0] = 0x00;
1527         mac_addr->addr_bytes[1] = 0x09;
1528         mac_addr->addr_bytes[2] = 0xC0;
1529         /* Force indication of locally assigned MAC address. */
1530         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1531         /* Generate the last 3 bytes of the MAC address with a random number. */
1532         random = rte_rand();
1533         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1534 }
1535
1536 /*
1537  * Virtual Function device init
1538  */
1539 static int
1540 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1541 {
1542         int diag;
1543         uint32_t tc, tcs;
1544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1546         struct ixgbe_hw *hw =
1547                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1548         struct ixgbe_vfta *shadow_vfta =
1549                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1550         struct ixgbe_hwstrip *hwstrip =
1551                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1552         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1553
1554         PMD_INIT_FUNC_TRACE();
1555
1556         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1557         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1558         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1559
1560         /* for secondary processes, we don't initialise any further as primary
1561          * has already done this work. Only check we don't need a different
1562          * RX function
1563          */
1564         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1565                 struct ixgbe_tx_queue *txq;
1566                 /* TX queue function in primary, set by last queue initialized
1567                  * Tx queue may not initialized by primary process
1568                  */
1569                 if (eth_dev->data->tx_queues) {
1570                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1571                         ixgbe_set_tx_function(eth_dev, txq);
1572                 } else {
1573                         /* Use default TX function if we get here */
1574                         PMD_INIT_LOG(NOTICE,
1575                                      "No TX queues configured yet. Using default TX function.");
1576                 }
1577
1578                 ixgbe_set_rx_function(eth_dev);
1579
1580                 return 0;
1581         }
1582
1583         rte_eth_copy_pci_info(eth_dev, pci_dev);
1584
1585         hw->device_id = pci_dev->id.device_id;
1586         hw->vendor_id = pci_dev->id.vendor_id;
1587         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1588
1589         /* initialize the vfta */
1590         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1591
1592         /* initialize the hw strip bitmap*/
1593         memset(hwstrip, 0, sizeof(*hwstrip));
1594
1595         /* Initialize the shared code (base driver) */
1596         diag = ixgbe_init_shared_code(hw);
1597         if (diag != IXGBE_SUCCESS) {
1598                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1599                 return -EIO;
1600         }
1601
1602         /* init_mailbox_params */
1603         hw->mbx.ops.init_params(hw);
1604
1605         /* Reset the hw statistics */
1606         ixgbevf_dev_stats_reset(eth_dev);
1607
1608         /* Disable the interrupts for VF */
1609         ixgbevf_intr_disable(hw);
1610
1611         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1612         diag = hw->mac.ops.reset_hw(hw);
1613
1614         /*
1615          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1616          * the underlying PF driver has not assigned a MAC address to the VF.
1617          * In this case, assign a random MAC address.
1618          */
1619         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1620                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1621                 return diag;
1622         }
1623
1624         /* negotiate mailbox API version to use with the PF. */
1625         ixgbevf_negotiate_api(hw);
1626
1627         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1628         ixgbevf_get_queues(hw, &tcs, &tc);
1629
1630         /* Allocate memory for storing MAC addresses */
1631         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1632                                                hw->mac.num_rar_entries, 0);
1633         if (eth_dev->data->mac_addrs == NULL) {
1634                 PMD_INIT_LOG(ERR,
1635                              "Failed to allocate %u bytes needed to store "
1636                              "MAC addresses",
1637                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1638                 return -ENOMEM;
1639         }
1640
1641         /* Generate a random MAC address, if none was assigned by PF. */
1642         if (is_zero_ether_addr(perm_addr)) {
1643                 generate_random_mac_addr(perm_addr);
1644                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1645                 if (diag) {
1646                         rte_free(eth_dev->data->mac_addrs);
1647                         eth_dev->data->mac_addrs = NULL;
1648                         return diag;
1649                 }
1650                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1651                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1652                              "%02x:%02x:%02x:%02x:%02x:%02x",
1653                              perm_addr->addr_bytes[0],
1654                              perm_addr->addr_bytes[1],
1655                              perm_addr->addr_bytes[2],
1656                              perm_addr->addr_bytes[3],
1657                              perm_addr->addr_bytes[4],
1658                              perm_addr->addr_bytes[5]);
1659         }
1660
1661         /* Copy the permanent MAC address */
1662         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1663
1664         /* reset the hardware with the new settings */
1665         diag = hw->mac.ops.start_hw(hw);
1666         switch (diag) {
1667         case  0:
1668                 break;
1669
1670         default:
1671                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1672                 return -EIO;
1673         }
1674
1675         rte_intr_callback_register(intr_handle,
1676                                    ixgbevf_dev_interrupt_handler, eth_dev);
1677         rte_intr_enable(intr_handle);
1678         ixgbevf_intr_enable(hw);
1679
1680         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1681                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1682                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1683
1684         return 0;
1685 }
1686
1687 /* Virtual Function device uninit */
1688
1689 static int
1690 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1691 {
1692         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1693         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1694         struct ixgbe_hw *hw;
1695
1696         PMD_INIT_FUNC_TRACE();
1697
1698         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1699                 return -EPERM;
1700
1701         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1702
1703         if (hw->adapter_stopped == 0)
1704                 ixgbevf_dev_close(eth_dev);
1705
1706         eth_dev->dev_ops = NULL;
1707         eth_dev->rx_pkt_burst = NULL;
1708         eth_dev->tx_pkt_burst = NULL;
1709
1710         /* Disable the interrupts for VF */
1711         ixgbevf_intr_disable(hw);
1712
1713         rte_free(eth_dev->data->mac_addrs);
1714         eth_dev->data->mac_addrs = NULL;
1715
1716         rte_intr_disable(intr_handle);
1717         rte_intr_callback_unregister(intr_handle,
1718                                      ixgbevf_dev_interrupt_handler, eth_dev);
1719
1720         return 0;
1721 }
1722
1723 static int
1724 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1725                 struct rte_pci_device *pci_dev)
1726 {
1727         char name[RTE_ETH_NAME_MAX_LEN];
1728         struct rte_eth_dev *pf_ethdev;
1729         struct rte_eth_devargs eth_da;
1730         int i, retval;
1731
1732         if (pci_dev->device.devargs) {
1733                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1734                                 &eth_da);
1735                 if (retval)
1736                         return retval;
1737         }
1738
1739         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1740                 sizeof(struct ixgbe_adapter),
1741                 eth_dev_pci_specific_init, pci_dev,
1742                 eth_ixgbe_dev_init, NULL);
1743
1744         if (retval || eth_da.nb_representor_ports < 1)
1745                 return retval;
1746
1747         /* probe VF representor ports */
1748         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1749
1750         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1751                 struct ixgbe_vf_info *vfinfo;
1752                 struct ixgbe_vf_representor representor;
1753
1754                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1755                         pf_ethdev->data->dev_private);
1756                 if (vfinfo == NULL) {
1757                         PMD_DRV_LOG(ERR,
1758                                 "no virtual functions supported by PF");
1759                         break;
1760                 }
1761
1762                 representor.vf_id = eth_da.representor_ports[i];
1763                 representor.switch_domain_id = vfinfo->switch_domain_id;
1764                 representor.pf_ethdev = pf_ethdev;
1765
1766                 /* representor port net_bdf_port */
1767                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1768                         pci_dev->device.name,
1769                         eth_da.representor_ports[i]);
1770
1771                 retval = rte_eth_dev_create(&pci_dev->device, name,
1772                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1773                         ixgbe_vf_representor_init, &representor);
1774
1775                 if (retval)
1776                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1777                                 "representor %s.", name);
1778         }
1779
1780         return 0;
1781 }
1782
1783 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1784 {
1785         struct rte_eth_dev *ethdev;
1786
1787         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1788         if (!ethdev)
1789                 return -ENODEV;
1790
1791         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1792                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1793         else
1794                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1795 }
1796
1797 static struct rte_pci_driver rte_ixgbe_pmd = {
1798         .id_table = pci_id_ixgbe_map,
1799         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1800                      RTE_PCI_DRV_IOVA_AS_VA,
1801         .probe = eth_ixgbe_pci_probe,
1802         .remove = eth_ixgbe_pci_remove,
1803 };
1804
1805 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1806         struct rte_pci_device *pci_dev)
1807 {
1808         return rte_eth_dev_pci_generic_probe(pci_dev,
1809                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1810 }
1811
1812 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1813 {
1814         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1815 }
1816
1817 /*
1818  * virtual function driver struct
1819  */
1820 static struct rte_pci_driver rte_ixgbevf_pmd = {
1821         .id_table = pci_id_ixgbevf_map,
1822         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1823         .probe = eth_ixgbevf_pci_probe,
1824         .remove = eth_ixgbevf_pci_remove,
1825 };
1826
1827 static int
1828 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1829 {
1830         struct ixgbe_hw *hw =
1831                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832         struct ixgbe_vfta *shadow_vfta =
1833                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1834         uint32_t vfta;
1835         uint32_t vid_idx;
1836         uint32_t vid_bit;
1837
1838         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1839         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1840         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1841         if (on)
1842                 vfta |= vid_bit;
1843         else
1844                 vfta &= ~vid_bit;
1845         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1846
1847         /* update local VFTA copy */
1848         shadow_vfta->vfta[vid_idx] = vfta;
1849
1850         return 0;
1851 }
1852
1853 static void
1854 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1855 {
1856         if (on)
1857                 ixgbe_vlan_hw_strip_enable(dev, queue);
1858         else
1859                 ixgbe_vlan_hw_strip_disable(dev, queue);
1860 }
1861
1862 static int
1863 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1864                     enum rte_vlan_type vlan_type,
1865                     uint16_t tpid)
1866 {
1867         struct ixgbe_hw *hw =
1868                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         int ret = 0;
1870         uint32_t reg;
1871         uint32_t qinq;
1872
1873         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1874         qinq &= IXGBE_DMATXCTL_GDV;
1875
1876         switch (vlan_type) {
1877         case ETH_VLAN_TYPE_INNER:
1878                 if (qinq) {
1879                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1880                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1881                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1882                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1883                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1884                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1885                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1886                 } else {
1887                         ret = -ENOTSUP;
1888                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1889                                     " by single VLAN");
1890                 }
1891                 break;
1892         case ETH_VLAN_TYPE_OUTER:
1893                 if (qinq) {
1894                         /* Only the high 16-bits is valid */
1895                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1896                                         IXGBE_EXVET_VET_EXT_SHIFT);
1897                 } else {
1898                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1899                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1900                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1901                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1902                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1903                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1904                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1905                 }
1906
1907                 break;
1908         default:
1909                 ret = -EINVAL;
1910                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1911                 break;
1912         }
1913
1914         return ret;
1915 }
1916
1917 void
1918 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint32_t vlnctrl;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         /* Filter Table Disable */
1927         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1928         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1929
1930         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1931 }
1932
1933 void
1934 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_hw *hw =
1937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         struct ixgbe_vfta *shadow_vfta =
1939                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1940         uint32_t vlnctrl;
1941         uint16_t i;
1942
1943         PMD_INIT_FUNC_TRACE();
1944
1945         /* Filter Table Enable */
1946         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1947         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1948         vlnctrl |= IXGBE_VLNCTRL_VFE;
1949
1950         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1951
1952         /* write whatever is in local vfta copy */
1953         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1954                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1955 }
1956
1957 static void
1958 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1959 {
1960         struct ixgbe_hwstrip *hwstrip =
1961                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1962         struct ixgbe_rx_queue *rxq;
1963
1964         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1965                 return;
1966
1967         if (on)
1968                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1969         else
1970                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1971
1972         if (queue >= dev->data->nb_rx_queues)
1973                 return;
1974
1975         rxq = dev->data->rx_queues[queue];
1976
1977         if (on)
1978                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1979         else
1980                 rxq->vlan_flags = PKT_RX_VLAN;
1981 }
1982
1983 static void
1984 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1985 {
1986         struct ixgbe_hw *hw =
1987                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1988         uint32_t ctrl;
1989
1990         PMD_INIT_FUNC_TRACE();
1991
1992         if (hw->mac.type == ixgbe_mac_82598EB) {
1993                 /* No queue level support */
1994                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1995                 return;
1996         }
1997
1998         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1999         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2000         ctrl &= ~IXGBE_RXDCTL_VME;
2001         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2002
2003         /* record those setting for HW strip per queue */
2004         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2005 }
2006
2007 static void
2008 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2009 {
2010         struct ixgbe_hw *hw =
2011                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012         uint32_t ctrl;
2013
2014         PMD_INIT_FUNC_TRACE();
2015
2016         if (hw->mac.type == ixgbe_mac_82598EB) {
2017                 /* No queue level supported */
2018                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2019                 return;
2020         }
2021
2022         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2023         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2024         ctrl |= IXGBE_RXDCTL_VME;
2025         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2026
2027         /* record those setting for HW strip per queue */
2028         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2029 }
2030
2031 static void
2032 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2033 {
2034         struct ixgbe_hw *hw =
2035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         uint32_t ctrl;
2037
2038         PMD_INIT_FUNC_TRACE();
2039
2040         /* DMATXCTRL: Geric Double VLAN Disable */
2041         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2042         ctrl &= ~IXGBE_DMATXCTL_GDV;
2043         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2044
2045         /* CTRL_EXT: Global Double VLAN Disable */
2046         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2047         ctrl &= ~IXGBE_EXTENDED_VLAN;
2048         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2049
2050 }
2051
2052 static void
2053 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2054 {
2055         struct ixgbe_hw *hw =
2056                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057         uint32_t ctrl;
2058
2059         PMD_INIT_FUNC_TRACE();
2060
2061         /* DMATXCTRL: Geric Double VLAN Enable */
2062         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2063         ctrl |= IXGBE_DMATXCTL_GDV;
2064         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2065
2066         /* CTRL_EXT: Global Double VLAN Enable */
2067         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2068         ctrl |= IXGBE_EXTENDED_VLAN;
2069         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2070
2071         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2072         if (hw->mac.type == ixgbe_mac_X550 ||
2073             hw->mac.type == ixgbe_mac_X550EM_x ||
2074             hw->mac.type == ixgbe_mac_X550EM_a) {
2075                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2076                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2077                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2078         }
2079
2080         /*
2081          * VET EXT field in the EXVET register = 0x8100 by default
2082          * So no need to change. Same to VT field of DMATXCTL register
2083          */
2084 }
2085
2086 void
2087 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2088 {
2089         struct ixgbe_hw *hw =
2090                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2092         uint32_t ctrl;
2093         uint16_t i;
2094         struct ixgbe_rx_queue *rxq;
2095         bool on;
2096
2097         PMD_INIT_FUNC_TRACE();
2098
2099         if (hw->mac.type == ixgbe_mac_82598EB) {
2100                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2101                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2102                         ctrl |= IXGBE_VLNCTRL_VME;
2103                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2104                 } else {
2105                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2106                         ctrl &= ~IXGBE_VLNCTRL_VME;
2107                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2108                 }
2109         } else {
2110                 /*
2111                  * Other 10G NIC, the VLAN strip can be setup
2112                  * per queue in RXDCTL
2113                  */
2114                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2115                         rxq = dev->data->rx_queues[i];
2116                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2117                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2118                                 ctrl |= IXGBE_RXDCTL_VME;
2119                                 on = TRUE;
2120                         } else {
2121                                 ctrl &= ~IXGBE_RXDCTL_VME;
2122                                 on = FALSE;
2123                         }
2124                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2125
2126                         /* record those setting for HW strip per queue */
2127                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2128                 }
2129         }
2130 }
2131
2132 static int
2133 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2134 {
2135         struct rte_eth_rxmode *rxmode;
2136         rxmode = &dev->data->dev_conf.rxmode;
2137
2138         if (mask & ETH_VLAN_STRIP_MASK) {
2139                 ixgbe_vlan_hw_strip_config(dev);
2140         }
2141
2142         if (mask & ETH_VLAN_FILTER_MASK) {
2143                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2144                         ixgbe_vlan_hw_filter_enable(dev);
2145                 else
2146                         ixgbe_vlan_hw_filter_disable(dev);
2147         }
2148
2149         if (mask & ETH_VLAN_EXTEND_MASK) {
2150                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2151                         ixgbe_vlan_hw_extend_enable(dev);
2152                 else
2153                         ixgbe_vlan_hw_extend_disable(dev);
2154         }
2155
2156         return 0;
2157 }
2158
2159 static void
2160 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2161 {
2162         struct ixgbe_hw *hw =
2163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2165         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2166
2167         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2168         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2169 }
2170
2171 static int
2172 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2173 {
2174         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2175
2176         switch (nb_rx_q) {
2177         case 1:
2178         case 2:
2179                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2180                 break;
2181         case 4:
2182                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2183                 break;
2184         default:
2185                 return -EINVAL;
2186         }
2187
2188         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2189                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2190         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2191                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2192         return 0;
2193 }
2194
2195 static int
2196 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2197 {
2198         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2201         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2202
2203         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2204                 /* check multi-queue mode */
2205                 switch (dev_conf->rxmode.mq_mode) {
2206                 case ETH_MQ_RX_VMDQ_DCB:
2207                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2208                         break;
2209                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2210                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2211                         PMD_INIT_LOG(ERR, "SRIOV active,"
2212                                         " unsupported mq_mode rx %d.",
2213                                         dev_conf->rxmode.mq_mode);
2214                         return -EINVAL;
2215                 case ETH_MQ_RX_RSS:
2216                 case ETH_MQ_RX_VMDQ_RSS:
2217                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2218                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2219                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2220                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2221                                                 " invalid queue number"
2222                                                 " for VMDQ RSS, allowed"
2223                                                 " value are 1, 2 or 4.");
2224                                         return -EINVAL;
2225                                 }
2226                         break;
2227                 case ETH_MQ_RX_VMDQ_ONLY:
2228                 case ETH_MQ_RX_NONE:
2229                         /* if nothing mq mode configure, use default scheme */
2230                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2231                         break;
2232                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2233                         /* SRIOV only works in VMDq enable mode */
2234                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2235                                         " wrong mq_mode rx %d.",
2236                                         dev_conf->rxmode.mq_mode);
2237                         return -EINVAL;
2238                 }
2239
2240                 switch (dev_conf->txmode.mq_mode) {
2241                 case ETH_MQ_TX_VMDQ_DCB:
2242                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2243                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2244                         break;
2245                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2246                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2247                         break;
2248                 }
2249
2250                 /* check valid queue number */
2251                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2252                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2253                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2254                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2255                                         " must be less than or equal to %d.",
2256                                         nb_rx_q, nb_tx_q,
2257                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2258                         return -EINVAL;
2259                 }
2260         } else {
2261                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2262                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2263                                           " not supported.");
2264                         return -EINVAL;
2265                 }
2266                 /* check configuration for vmdb+dcb mode */
2267                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2268                         const struct rte_eth_vmdq_dcb_conf *conf;
2269
2270                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2271                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2272                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2273                                 return -EINVAL;
2274                         }
2275                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2276                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2277                                conf->nb_queue_pools == ETH_32_POOLS)) {
2278                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2279                                                 " nb_queue_pools must be %d or %d.",
2280                                                 ETH_16_POOLS, ETH_32_POOLS);
2281                                 return -EINVAL;
2282                         }
2283                 }
2284                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2285                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2286
2287                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2288                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2289                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2290                                 return -EINVAL;
2291                         }
2292                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2293                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2294                                conf->nb_queue_pools == ETH_32_POOLS)) {
2295                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2296                                                 " nb_queue_pools != %d and"
2297                                                 " nb_queue_pools != %d.",
2298                                                 ETH_16_POOLS, ETH_32_POOLS);
2299                                 return -EINVAL;
2300                         }
2301                 }
2302
2303                 /* For DCB mode check our configuration before we go further */
2304                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2305                         const struct rte_eth_dcb_rx_conf *conf;
2306
2307                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2308                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2309                                                  IXGBE_DCB_NB_QUEUES);
2310                                 return -EINVAL;
2311                         }
2312                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2313                         if (!(conf->nb_tcs == ETH_4_TCS ||
2314                                conf->nb_tcs == ETH_8_TCS)) {
2315                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2316                                                 " and nb_tcs != %d.",
2317                                                 ETH_4_TCS, ETH_8_TCS);
2318                                 return -EINVAL;
2319                         }
2320                 }
2321
2322                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2323                         const struct rte_eth_dcb_tx_conf *conf;
2324
2325                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2326                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2327                                                  IXGBE_DCB_NB_QUEUES);
2328                                 return -EINVAL;
2329                         }
2330                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2331                         if (!(conf->nb_tcs == ETH_4_TCS ||
2332                                conf->nb_tcs == ETH_8_TCS)) {
2333                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2334                                                 " and nb_tcs != %d.",
2335                                                 ETH_4_TCS, ETH_8_TCS);
2336                                 return -EINVAL;
2337                         }
2338                 }
2339
2340                 /*
2341                  * When DCB/VT is off, maximum number of queues changes,
2342                  * except for 82598EB, which remains constant.
2343                  */
2344                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2345                                 hw->mac.type != ixgbe_mac_82598EB) {
2346                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2347                                 PMD_INIT_LOG(ERR,
2348                                              "Neither VT nor DCB are enabled, "
2349                                              "nb_tx_q > %d.",
2350                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2351                                 return -EINVAL;
2352                         }
2353                 }
2354         }
2355         return 0;
2356 }
2357
2358 static int
2359 ixgbe_dev_configure(struct rte_eth_dev *dev)
2360 {
2361         struct ixgbe_interrupt *intr =
2362                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2363         struct ixgbe_adapter *adapter =
2364                 (struct ixgbe_adapter *)dev->data->dev_private;
2365         struct rte_eth_dev_info dev_info;
2366         uint64_t rx_offloads;
2367         uint64_t tx_offloads;
2368         int ret;
2369
2370         PMD_INIT_FUNC_TRACE();
2371         /* multipe queue mode checking */
2372         ret  = ixgbe_check_mq_mode(dev);
2373         if (ret != 0) {
2374                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2375                             ret);
2376                 return ret;
2377         }
2378
2379         ixgbe_dev_info_get(dev, &dev_info);
2380         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2381         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2382                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2383                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2384                             rx_offloads, dev_info.rx_offload_capa);
2385                 return -ENOTSUP;
2386         }
2387         tx_offloads = dev->data->dev_conf.txmode.offloads;
2388         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2389                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2390                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2391                             tx_offloads, dev_info.tx_offload_capa);
2392                 return -ENOTSUP;
2393         }
2394
2395         /* set flag to update link status after init */
2396         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2397
2398         /*
2399          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2400          * allocation or vector Rx preconditions we will reset it.
2401          */
2402         adapter->rx_bulk_alloc_allowed = true;
2403         adapter->rx_vec_allowed = true;
2404
2405         return 0;
2406 }
2407
2408 static void
2409 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2410 {
2411         struct ixgbe_hw *hw =
2412                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413         struct ixgbe_interrupt *intr =
2414                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2415         uint32_t gpie;
2416
2417         /* only set up it on X550EM_X */
2418         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2419                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2420                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2421                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2422                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2423                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2424         }
2425 }
2426
2427 int
2428 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2429                         uint16_t tx_rate, uint64_t q_msk)
2430 {
2431         struct ixgbe_hw *hw;
2432         struct ixgbe_vf_info *vfinfo;
2433         struct rte_eth_link link;
2434         uint8_t  nb_q_per_pool;
2435         uint32_t queue_stride;
2436         uint32_t queue_idx, idx = 0, vf_idx;
2437         uint32_t queue_end;
2438         uint16_t total_rate = 0;
2439         struct rte_pci_device *pci_dev;
2440
2441         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2442         rte_eth_link_get_nowait(dev->data->port_id, &link);
2443
2444         if (vf >= pci_dev->max_vfs)
2445                 return -EINVAL;
2446
2447         if (tx_rate > link.link_speed)
2448                 return -EINVAL;
2449
2450         if (q_msk == 0)
2451                 return 0;
2452
2453         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2454         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2455         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2456         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2457         queue_idx = vf * queue_stride;
2458         queue_end = queue_idx + nb_q_per_pool - 1;
2459         if (queue_end >= hw->mac.max_tx_queues)
2460                 return -EINVAL;
2461
2462         if (vfinfo) {
2463                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2464                         if (vf_idx == vf)
2465                                 continue;
2466                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2467                                 idx++)
2468                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2469                 }
2470         } else {
2471                 return -EINVAL;
2472         }
2473
2474         /* Store tx_rate for this vf. */
2475         for (idx = 0; idx < nb_q_per_pool; idx++) {
2476                 if (((uint64_t)0x1 << idx) & q_msk) {
2477                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2478                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2479                         total_rate += tx_rate;
2480                 }
2481         }
2482
2483         if (total_rate > dev->data->dev_link.link_speed) {
2484                 /* Reset stored TX rate of the VF if it causes exceed
2485                  * link speed.
2486                  */
2487                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2488                 return -EINVAL;
2489         }
2490
2491         /* Set RTTBCNRC of each queue/pool for vf X  */
2492         for (; queue_idx <= queue_end; queue_idx++) {
2493                 if (0x1 & q_msk)
2494                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2495                 q_msk = q_msk >> 1;
2496         }
2497
2498         return 0;
2499 }
2500
2501 /*
2502  * Configure device link speed and setup link.
2503  * It returns 0 on success.
2504  */
2505 static int
2506 ixgbe_dev_start(struct rte_eth_dev *dev)
2507 {
2508         struct ixgbe_hw *hw =
2509                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2510         struct ixgbe_vf_info *vfinfo =
2511                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2512         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2513         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2514         uint32_t intr_vector = 0;
2515         int err, link_up = 0, negotiate = 0;
2516         uint32_t speed = 0;
2517         uint32_t allowed_speeds = 0;
2518         int mask = 0;
2519         int status;
2520         uint16_t vf, idx;
2521         uint32_t *link_speeds;
2522         struct ixgbe_tm_conf *tm_conf =
2523                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2524
2525         PMD_INIT_FUNC_TRACE();
2526
2527         /* IXGBE devices don't support:
2528         *    - half duplex (checked afterwards for valid speeds)
2529         *    - fixed speed: TODO implement
2530         */
2531         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2532                 PMD_INIT_LOG(ERR,
2533                 "Invalid link_speeds for port %u, fix speed not supported",
2534                                 dev->data->port_id);
2535                 return -EINVAL;
2536         }
2537
2538         /* disable uio/vfio intr/eventfd mapping */
2539         rte_intr_disable(intr_handle);
2540
2541         /* stop adapter */
2542         hw->adapter_stopped = 0;
2543         ixgbe_stop_adapter(hw);
2544
2545         /* reinitialize adapter
2546          * this calls reset and start
2547          */
2548         status = ixgbe_pf_reset_hw(hw);
2549         if (status != 0)
2550                 return -1;
2551         hw->mac.ops.start_hw(hw);
2552         hw->mac.get_link_status = true;
2553
2554         /* configure PF module if SRIOV enabled */
2555         ixgbe_pf_host_configure(dev);
2556
2557         ixgbe_dev_phy_intr_setup(dev);
2558
2559         /* check and configure queue intr-vector mapping */
2560         if ((rte_intr_cap_multiple(intr_handle) ||
2561              !RTE_ETH_DEV_SRIOV(dev).active) &&
2562             dev->data->dev_conf.intr_conf.rxq != 0) {
2563                 intr_vector = dev->data->nb_rx_queues;
2564                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2565                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2566                                         IXGBE_MAX_INTR_QUEUE_NUM);
2567                         return -ENOTSUP;
2568                 }
2569                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2570                         return -1;
2571         }
2572
2573         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2574                 intr_handle->intr_vec =
2575                         rte_zmalloc("intr_vec",
2576                                     dev->data->nb_rx_queues * sizeof(int), 0);
2577                 if (intr_handle->intr_vec == NULL) {
2578                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2579                                      " intr_vec", dev->data->nb_rx_queues);
2580                         return -ENOMEM;
2581                 }
2582         }
2583
2584         /* confiugre msix for sleep until rx interrupt */
2585         ixgbe_configure_msix(dev);
2586
2587         /* initialize transmission unit */
2588         ixgbe_dev_tx_init(dev);
2589
2590         /* This can fail when allocating mbufs for descriptor rings */
2591         err = ixgbe_dev_rx_init(dev);
2592         if (err) {
2593                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2594                 goto error;
2595         }
2596
2597         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2598                 ETH_VLAN_EXTEND_MASK;
2599         err = ixgbe_vlan_offload_set(dev, mask);
2600         if (err) {
2601                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2602                 goto error;
2603         }
2604
2605         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2606                 /* Enable vlan filtering for VMDq */
2607                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2608         }
2609
2610         /* Configure DCB hw */
2611         ixgbe_configure_dcb(dev);
2612
2613         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2614                 err = ixgbe_fdir_configure(dev);
2615                 if (err)
2616                         goto error;
2617         }
2618
2619         /* Restore vf rate limit */
2620         if (vfinfo != NULL) {
2621                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2622                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2623                                 if (vfinfo[vf].tx_rate[idx] != 0)
2624                                         ixgbe_set_vf_rate_limit(
2625                                                 dev, vf,
2626                                                 vfinfo[vf].tx_rate[idx],
2627                                                 1 << idx);
2628         }
2629
2630         ixgbe_restore_statistics_mapping(dev);
2631
2632         err = ixgbe_dev_rxtx_start(dev);
2633         if (err < 0) {
2634                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2635                 goto error;
2636         }
2637
2638         /* Skip link setup if loopback mode is enabled for 82599. */
2639         if (hw->mac.type == ixgbe_mac_82599EB &&
2640                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2641                 goto skip_link_setup;
2642
2643         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2644                 err = hw->mac.ops.setup_sfp(hw);
2645                 if (err)
2646                         goto error;
2647         }
2648
2649         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2650                 /* Turn on the copper */
2651                 ixgbe_set_phy_power(hw, true);
2652         } else {
2653                 /* Turn on the laser */
2654                 ixgbe_enable_tx_laser(hw);
2655         }
2656
2657         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2658         if (err)
2659                 goto error;
2660         dev->data->dev_link.link_status = link_up;
2661
2662         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2663         if (err)
2664                 goto error;
2665
2666         switch (hw->mac.type) {
2667         case ixgbe_mac_X550:
2668         case ixgbe_mac_X550EM_x:
2669         case ixgbe_mac_X550EM_a:
2670                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2671                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2672                         ETH_LINK_SPEED_10G;
2673                 break;
2674         default:
2675                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2676                         ETH_LINK_SPEED_10G;
2677         }
2678
2679         link_speeds = &dev->data->dev_conf.link_speeds;
2680         if (*link_speeds & ~allowed_speeds) {
2681                 PMD_INIT_LOG(ERR, "Invalid link setting");
2682                 goto error;
2683         }
2684
2685         speed = 0x0;
2686         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2687                 switch (hw->mac.type) {
2688                 case ixgbe_mac_82598EB:
2689                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2690                         break;
2691                 case ixgbe_mac_82599EB:
2692                 case ixgbe_mac_X540:
2693                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2694                         break;
2695                 case ixgbe_mac_X550:
2696                 case ixgbe_mac_X550EM_x:
2697                 case ixgbe_mac_X550EM_a:
2698                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2699                         break;
2700                 default:
2701                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2702                 }
2703         } else {
2704                 if (*link_speeds & ETH_LINK_SPEED_10G)
2705                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2706                 if (*link_speeds & ETH_LINK_SPEED_5G)
2707                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2708                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2709                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2710                 if (*link_speeds & ETH_LINK_SPEED_1G)
2711                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2712                 if (*link_speeds & ETH_LINK_SPEED_100M)
2713                         speed |= IXGBE_LINK_SPEED_100_FULL;
2714         }
2715
2716         err = ixgbe_setup_link(hw, speed, link_up);
2717         if (err)
2718                 goto error;
2719
2720         ixgbe_dev_link_update(dev, 0);
2721
2722 skip_link_setup:
2723
2724         if (rte_intr_allow_others(intr_handle)) {
2725                 /* check if lsc interrupt is enabled */
2726                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2727                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2728                 else
2729                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2730                 ixgbe_dev_macsec_interrupt_setup(dev);
2731         } else {
2732                 rte_intr_callback_unregister(intr_handle,
2733                                              ixgbe_dev_interrupt_handler, dev);
2734                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2735                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2736                                      " no intr multiplex");
2737         }
2738
2739         /* check if rxq interrupt is enabled */
2740         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2741             rte_intr_dp_is_en(intr_handle))
2742                 ixgbe_dev_rxq_interrupt_setup(dev);
2743
2744         /* enable uio/vfio intr/eventfd mapping */
2745         rte_intr_enable(intr_handle);
2746
2747         /* resume enabled intr since hw reset */
2748         ixgbe_enable_intr(dev);
2749         ixgbe_l2_tunnel_conf(dev);
2750         ixgbe_filter_restore(dev);
2751
2752         if (tm_conf->root && !tm_conf->committed)
2753                 PMD_DRV_LOG(WARNING,
2754                             "please call hierarchy_commit() "
2755                             "before starting the port");
2756
2757         return 0;
2758
2759 error:
2760         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2761         ixgbe_dev_clear_queues(dev);
2762         return -EIO;
2763 }
2764
2765 /*
2766  * Stop device: disable rx and tx functions to allow for reconfiguring.
2767  */
2768 static void
2769 ixgbe_dev_stop(struct rte_eth_dev *dev)
2770 {
2771         struct rte_eth_link link;
2772         struct ixgbe_hw *hw =
2773                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774         struct ixgbe_vf_info *vfinfo =
2775                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2777         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2778         int vf;
2779         struct ixgbe_tm_conf *tm_conf =
2780                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2781
2782         PMD_INIT_FUNC_TRACE();
2783
2784         /* disable interrupts */
2785         ixgbe_disable_intr(hw);
2786
2787         /* reset the NIC */
2788         ixgbe_pf_reset_hw(hw);
2789         hw->adapter_stopped = 0;
2790
2791         /* stop adapter */
2792         ixgbe_stop_adapter(hw);
2793
2794         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2795                 vfinfo[vf].clear_to_send = false;
2796
2797         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2798                 /* Turn off the copper */
2799                 ixgbe_set_phy_power(hw, false);
2800         } else {
2801                 /* Turn off the laser */
2802                 ixgbe_disable_tx_laser(hw);
2803         }
2804
2805         ixgbe_dev_clear_queues(dev);
2806
2807         /* Clear stored conf */
2808         dev->data->scattered_rx = 0;
2809         dev->data->lro = 0;
2810
2811         /* Clear recorded link status */
2812         memset(&link, 0, sizeof(link));
2813         rte_eth_linkstatus_set(dev, &link);
2814
2815         if (!rte_intr_allow_others(intr_handle))
2816                 /* resume to the default handler */
2817                 rte_intr_callback_register(intr_handle,
2818                                            ixgbe_dev_interrupt_handler,
2819                                            (void *)dev);
2820
2821         /* Clean datapath event and queue/vec mapping */
2822         rte_intr_efd_disable(intr_handle);
2823         if (intr_handle->intr_vec != NULL) {
2824                 rte_free(intr_handle->intr_vec);
2825                 intr_handle->intr_vec = NULL;
2826         }
2827
2828         /* reset hierarchy commit */
2829         tm_conf->committed = false;
2830 }
2831
2832 /*
2833  * Set device link up: enable tx.
2834  */
2835 static int
2836 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2837 {
2838         struct ixgbe_hw *hw =
2839                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840         if (hw->mac.type == ixgbe_mac_82599EB) {
2841 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2842                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2843                         /* Not suported in bypass mode */
2844                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2845                                      "by device id 0x%x", hw->device_id);
2846                         return -ENOTSUP;
2847                 }
2848 #endif
2849         }
2850
2851         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2852                 /* Turn on the copper */
2853                 ixgbe_set_phy_power(hw, true);
2854         } else {
2855                 /* Turn on the laser */
2856                 ixgbe_enable_tx_laser(hw);
2857         }
2858
2859         return 0;
2860 }
2861
2862 /*
2863  * Set device link down: disable tx.
2864  */
2865 static int
2866 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2867 {
2868         struct ixgbe_hw *hw =
2869                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870         if (hw->mac.type == ixgbe_mac_82599EB) {
2871 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2872                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2873                         /* Not suported in bypass mode */
2874                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2875                                      "by device id 0x%x", hw->device_id);
2876                         return -ENOTSUP;
2877                 }
2878 #endif
2879         }
2880
2881         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2882                 /* Turn off the copper */
2883                 ixgbe_set_phy_power(hw, false);
2884         } else {
2885                 /* Turn off the laser */
2886                 ixgbe_disable_tx_laser(hw);
2887         }
2888
2889         return 0;
2890 }
2891
2892 /*
2893  * Reset and stop device.
2894  */
2895 static void
2896 ixgbe_dev_close(struct rte_eth_dev *dev)
2897 {
2898         struct ixgbe_hw *hw =
2899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900
2901         PMD_INIT_FUNC_TRACE();
2902
2903         ixgbe_pf_reset_hw(hw);
2904
2905         ixgbe_dev_stop(dev);
2906         hw->adapter_stopped = 1;
2907
2908         ixgbe_dev_free_queues(dev);
2909
2910         ixgbe_disable_pcie_master(hw);
2911
2912         /* reprogram the RAR[0] in case user changed it. */
2913         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2914 }
2915
2916 /*
2917  * Reset PF device.
2918  */
2919 static int
2920 ixgbe_dev_reset(struct rte_eth_dev *dev)
2921 {
2922         int ret;
2923
2924         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2925          * its VF to make them align with it. The detailed notification
2926          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2927          * To avoid unexpected behavior in VF, currently reset of PF with
2928          * SR-IOV activation is not supported. It might be supported later.
2929          */
2930         if (dev->data->sriov.active)
2931                 return -ENOTSUP;
2932
2933         ret = eth_ixgbe_dev_uninit(dev);
2934         if (ret)
2935                 return ret;
2936
2937         ret = eth_ixgbe_dev_init(dev, NULL);
2938
2939         return ret;
2940 }
2941
2942 static void
2943 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2944                            struct ixgbe_hw_stats *hw_stats,
2945                            struct ixgbe_macsec_stats *macsec_stats,
2946                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2947                            uint64_t *total_qprc, uint64_t *total_qprdc)
2948 {
2949         uint32_t bprc, lxon, lxoff, total;
2950         uint32_t delta_gprc = 0;
2951         unsigned i;
2952         /* Workaround for RX byte count not including CRC bytes when CRC
2953          * strip is enabled. CRC bytes are removed from counters when crc_strip
2954          * is disabled.
2955          */
2956         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2957                         IXGBE_HLREG0_RXCRCSTRP);
2958
2959         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2960         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2961         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2962         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2963
2964         for (i = 0; i < 8; i++) {
2965                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2966
2967                 /* global total per queue */
2968                 hw_stats->mpc[i] += mp;
2969                 /* Running comprehensive total for stats display */
2970                 *total_missed_rx += hw_stats->mpc[i];
2971                 if (hw->mac.type == ixgbe_mac_82598EB) {
2972                         hw_stats->rnbc[i] +=
2973                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2974                         hw_stats->pxonrxc[i] +=
2975                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2976                         hw_stats->pxoffrxc[i] +=
2977                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2978                 } else {
2979                         hw_stats->pxonrxc[i] +=
2980                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2981                         hw_stats->pxoffrxc[i] +=
2982                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2983                         hw_stats->pxon2offc[i] +=
2984                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2985                 }
2986                 hw_stats->pxontxc[i] +=
2987                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2988                 hw_stats->pxofftxc[i] +=
2989                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2990         }
2991         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2992                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2993                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2994                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2995
2996                 delta_gprc += delta_qprc;
2997
2998                 hw_stats->qprc[i] += delta_qprc;
2999                 hw_stats->qptc[i] += delta_qptc;
3000
3001                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3002                 hw_stats->qbrc[i] +=
3003                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3004                 if (crc_strip == 0)
3005                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3006
3007                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3008                 hw_stats->qbtc[i] +=
3009                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3010
3011                 hw_stats->qprdc[i] += delta_qprdc;
3012                 *total_qprdc += hw_stats->qprdc[i];
3013
3014                 *total_qprc += hw_stats->qprc[i];
3015                 *total_qbrc += hw_stats->qbrc[i];
3016         }
3017         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3018         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3019         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3020
3021         /*
3022          * An errata states that gprc actually counts good + missed packets:
3023          * Workaround to set gprc to summated queue packet receives
3024          */
3025         hw_stats->gprc = *total_qprc;
3026
3027         if (hw->mac.type != ixgbe_mac_82598EB) {
3028                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3029                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3030                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3031                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3032                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3033                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3034                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3035                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3036         } else {
3037                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3038                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3039                 /* 82598 only has a counter in the high register */
3040                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3041                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3042                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3043         }
3044         uint64_t old_tpr = hw_stats->tpr;
3045
3046         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3047         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3048
3049         if (crc_strip == 0)
3050                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3051
3052         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3053         hw_stats->gptc += delta_gptc;
3054         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3055         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3056
3057         /*
3058          * Workaround: mprc hardware is incorrectly counting
3059          * broadcasts, so for now we subtract those.
3060          */
3061         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3062         hw_stats->bprc += bprc;
3063         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3064         if (hw->mac.type == ixgbe_mac_82598EB)
3065                 hw_stats->mprc -= bprc;
3066
3067         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3068         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3069         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3070         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3071         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3072         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3073
3074         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3075         hw_stats->lxontxc += lxon;
3076         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3077         hw_stats->lxofftxc += lxoff;
3078         total = lxon + lxoff;
3079
3080         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3081         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3082         hw_stats->gptc -= total;
3083         hw_stats->mptc -= total;
3084         hw_stats->ptc64 -= total;
3085         hw_stats->gotc -= total * ETHER_MIN_LEN;
3086
3087         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3088         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3089         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3090         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3091         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3092         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3093         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3094         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3095         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3096         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3097         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3098         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3099         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3100         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3101         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3102         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3103         /* Only read FCOE on 82599 */
3104         if (hw->mac.type != ixgbe_mac_82598EB) {
3105                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3106                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3107                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3108                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3109                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3110         }
3111
3112         /* Flow Director Stats registers */
3113         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3114         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3115
3116         /* MACsec Stats registers */
3117         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3118         macsec_stats->out_pkts_encrypted +=
3119                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3120         macsec_stats->out_pkts_protected +=
3121                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3122         macsec_stats->out_octets_encrypted +=
3123                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3124         macsec_stats->out_octets_protected +=
3125                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3126         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3127         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3128         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3129         macsec_stats->in_pkts_unknownsci +=
3130                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3131         macsec_stats->in_octets_decrypted +=
3132                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3133         macsec_stats->in_octets_validated +=
3134                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3135         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3136         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3137         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3138         for (i = 0; i < 2; i++) {
3139                 macsec_stats->in_pkts_ok +=
3140                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3141                 macsec_stats->in_pkts_invalid +=
3142                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3143                 macsec_stats->in_pkts_notvalid +=
3144                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3145         }
3146         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3147         macsec_stats->in_pkts_notusingsa +=
3148                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3149 }
3150
3151 /*
3152  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3153  */
3154 static int
3155 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3156 {
3157         struct ixgbe_hw *hw =
3158                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3159         struct ixgbe_hw_stats *hw_stats =
3160                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3161         struct ixgbe_macsec_stats *macsec_stats =
3162                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3163                                 dev->data->dev_private);
3164         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3165         unsigned i;
3166
3167         total_missed_rx = 0;
3168         total_qbrc = 0;
3169         total_qprc = 0;
3170         total_qprdc = 0;
3171
3172         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3173                         &total_qbrc, &total_qprc, &total_qprdc);
3174
3175         if (stats == NULL)
3176                 return -EINVAL;
3177
3178         /* Fill out the rte_eth_stats statistics structure */
3179         stats->ipackets = total_qprc;
3180         stats->ibytes = total_qbrc;
3181         stats->opackets = hw_stats->gptc;
3182         stats->obytes = hw_stats->gotc;
3183
3184         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3185                 stats->q_ipackets[i] = hw_stats->qprc[i];
3186                 stats->q_opackets[i] = hw_stats->qptc[i];
3187                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3188                 stats->q_obytes[i] = hw_stats->qbtc[i];
3189                 stats->q_errors[i] = hw_stats->qprdc[i];
3190         }
3191
3192         /* Rx Errors */
3193         stats->imissed  = total_missed_rx;
3194         stats->ierrors  = hw_stats->crcerrs +
3195                           hw_stats->mspdc +
3196                           hw_stats->rlec +
3197                           hw_stats->ruc +
3198                           hw_stats->roc +
3199                           hw_stats->illerrc +
3200                           hw_stats->errbc +
3201                           hw_stats->rfc +
3202                           hw_stats->fccrc +
3203                           hw_stats->fclast;
3204
3205         /* Tx Errors */
3206         stats->oerrors  = 0;
3207         return 0;
3208 }
3209
3210 static void
3211 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3212 {
3213         struct ixgbe_hw_stats *stats =
3214                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3215
3216         /* HW registers are cleared on read */
3217         ixgbe_dev_stats_get(dev, NULL);
3218
3219         /* Reset software totals */
3220         memset(stats, 0, sizeof(*stats));
3221 }
3222
3223 /* This function calculates the number of xstats based on the current config */
3224 static unsigned
3225 ixgbe_xstats_calc_num(void) {
3226         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3227                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3228                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3229 }
3230
3231 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3232         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3233 {
3234         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3235         unsigned stat, i, count;
3236
3237         if (xstats_names != NULL) {
3238                 count = 0;
3239
3240                 /* Note: limit >= cnt_stats checked upstream
3241                  * in rte_eth_xstats_names()
3242                  */
3243
3244                 /* Extended stats from ixgbe_hw_stats */
3245                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3246                         snprintf(xstats_names[count].name,
3247                                 sizeof(xstats_names[count].name),
3248                                 "%s",
3249                                 rte_ixgbe_stats_strings[i].name);
3250                         count++;
3251                 }
3252
3253                 /* MACsec Stats */
3254                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3255                         snprintf(xstats_names[count].name,
3256                                 sizeof(xstats_names[count].name),
3257                                 "%s",
3258                                 rte_ixgbe_macsec_strings[i].name);
3259                         count++;
3260                 }
3261
3262                 /* RX Priority Stats */
3263                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3264                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3265                                 snprintf(xstats_names[count].name,
3266                                         sizeof(xstats_names[count].name),
3267                                         "rx_priority%u_%s", i,
3268                                         rte_ixgbe_rxq_strings[stat].name);
3269                                 count++;
3270                         }
3271                 }
3272
3273                 /* TX Priority Stats */
3274                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3275                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3276                                 snprintf(xstats_names[count].name,
3277                                         sizeof(xstats_names[count].name),
3278                                         "tx_priority%u_%s", i,
3279                                         rte_ixgbe_txq_strings[stat].name);
3280                                 count++;
3281                         }
3282                 }
3283         }
3284         return cnt_stats;
3285 }
3286
3287 static int ixgbe_dev_xstats_get_names_by_id(
3288         struct rte_eth_dev *dev,
3289         struct rte_eth_xstat_name *xstats_names,
3290         const uint64_t *ids,
3291         unsigned int limit)
3292 {
3293         if (!ids) {
3294                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3295                 unsigned int stat, i, count;
3296
3297                 if (xstats_names != NULL) {
3298                         count = 0;
3299
3300                         /* Note: limit >= cnt_stats checked upstream
3301                          * in rte_eth_xstats_names()
3302                          */
3303
3304                         /* Extended stats from ixgbe_hw_stats */
3305                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3306                                 snprintf(xstats_names[count].name,
3307                                         sizeof(xstats_names[count].name),
3308                                         "%s",
3309                                         rte_ixgbe_stats_strings[i].name);
3310                                 count++;
3311                         }
3312
3313                         /* MACsec Stats */
3314                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3315                                 snprintf(xstats_names[count].name,
3316                                         sizeof(xstats_names[count].name),
3317                                         "%s",
3318                                         rte_ixgbe_macsec_strings[i].name);
3319                                 count++;
3320                         }
3321
3322                         /* RX Priority Stats */
3323                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3324                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3325                                         snprintf(xstats_names[count].name,
3326                                             sizeof(xstats_names[count].name),
3327                                             "rx_priority%u_%s", i,
3328                                             rte_ixgbe_rxq_strings[stat].name);
3329                                         count++;
3330                                 }
3331                         }
3332
3333                         /* TX Priority Stats */
3334                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3335                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3336                                         snprintf(xstats_names[count].name,
3337                                             sizeof(xstats_names[count].name),
3338                                             "tx_priority%u_%s", i,
3339                                             rte_ixgbe_txq_strings[stat].name);
3340                                         count++;
3341                                 }
3342                         }
3343                 }
3344                 return cnt_stats;
3345         }
3346
3347         uint16_t i;
3348         uint16_t size = ixgbe_xstats_calc_num();
3349         struct rte_eth_xstat_name xstats_names_copy[size];
3350
3351         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3352                         size);
3353
3354         for (i = 0; i < limit; i++) {
3355                 if (ids[i] >= size) {
3356                         PMD_INIT_LOG(ERR, "id value isn't valid");
3357                         return -1;
3358                 }
3359                 strcpy(xstats_names[i].name,
3360                                 xstats_names_copy[ids[i]].name);
3361         }
3362         return limit;
3363 }
3364
3365 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3366         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3367 {
3368         unsigned i;
3369
3370         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3371                 return -ENOMEM;
3372
3373         if (xstats_names != NULL)
3374                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3375                         snprintf(xstats_names[i].name,
3376                                 sizeof(xstats_names[i].name),
3377                                 "%s", rte_ixgbevf_stats_strings[i].name);
3378         return IXGBEVF_NB_XSTATS;
3379 }
3380
3381 static int
3382 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3383                                          unsigned n)
3384 {
3385         struct ixgbe_hw *hw =
3386                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3387         struct ixgbe_hw_stats *hw_stats =
3388                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3389         struct ixgbe_macsec_stats *macsec_stats =
3390                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3391                                 dev->data->dev_private);
3392         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3393         unsigned i, stat, count = 0;
3394
3395         count = ixgbe_xstats_calc_num();
3396
3397         if (n < count)
3398                 return count;
3399
3400         total_missed_rx = 0;
3401         total_qbrc = 0;
3402         total_qprc = 0;
3403         total_qprdc = 0;
3404
3405         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3406                         &total_qbrc, &total_qprc, &total_qprdc);
3407
3408         /* If this is a reset xstats is NULL, and we have cleared the
3409          * registers by reading them.
3410          */
3411         if (!xstats)
3412                 return 0;
3413
3414         /* Extended stats from ixgbe_hw_stats */
3415         count = 0;
3416         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3417                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3418                                 rte_ixgbe_stats_strings[i].offset);
3419                 xstats[count].id = count;
3420                 count++;
3421         }
3422
3423         /* MACsec Stats */
3424         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3425                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3426                                 rte_ixgbe_macsec_strings[i].offset);
3427                 xstats[count].id = count;
3428                 count++;
3429         }
3430
3431         /* RX Priority Stats */
3432         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3433                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3434                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3435                                         rte_ixgbe_rxq_strings[stat].offset +
3436                                         (sizeof(uint64_t) * i));
3437                         xstats[count].id = count;
3438                         count++;
3439                 }
3440         }
3441
3442         /* TX Priority Stats */
3443         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3444                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3445                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3446                                         rte_ixgbe_txq_strings[stat].offset +
3447                                         (sizeof(uint64_t) * i));
3448                         xstats[count].id = count;
3449                         count++;
3450                 }
3451         }
3452         return count;
3453 }
3454
3455 static int
3456 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3457                 uint64_t *values, unsigned int n)
3458 {
3459         if (!ids) {
3460                 struct ixgbe_hw *hw =
3461                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462                 struct ixgbe_hw_stats *hw_stats =
3463                                 IXGBE_DEV_PRIVATE_TO_STATS(
3464                                                 dev->data->dev_private);
3465                 struct ixgbe_macsec_stats *macsec_stats =
3466                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3467                                         dev->data->dev_private);
3468                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3469                 unsigned int i, stat, count = 0;
3470
3471                 count = ixgbe_xstats_calc_num();
3472
3473                 if (!ids && n < count)
3474                         return count;
3475
3476                 total_missed_rx = 0;
3477                 total_qbrc = 0;
3478                 total_qprc = 0;
3479                 total_qprdc = 0;
3480
3481                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3482                                 &total_missed_rx, &total_qbrc, &total_qprc,
3483                                 &total_qprdc);
3484
3485                 /* If this is a reset xstats is NULL, and we have cleared the
3486                  * registers by reading them.
3487                  */
3488                 if (!ids && !values)
3489                         return 0;
3490
3491                 /* Extended stats from ixgbe_hw_stats */
3492                 count = 0;
3493                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3494                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3495                                         rte_ixgbe_stats_strings[i].offset);
3496                         count++;
3497                 }
3498
3499                 /* MACsec Stats */
3500                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3501                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3502                                         rte_ixgbe_macsec_strings[i].offset);
3503                         count++;
3504                 }
3505
3506                 /* RX Priority Stats */
3507                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3508                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3509                                 values[count] =
3510                                         *(uint64_t *)(((char *)hw_stats) +
3511                                         rte_ixgbe_rxq_strings[stat].offset +
3512                                         (sizeof(uint64_t) * i));
3513                                 count++;
3514                         }
3515                 }
3516
3517                 /* TX Priority Stats */
3518                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3519                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3520                                 values[count] =
3521                                         *(uint64_t *)(((char *)hw_stats) +
3522                                         rte_ixgbe_txq_strings[stat].offset +
3523                                         (sizeof(uint64_t) * i));
3524                                 count++;
3525                         }
3526                 }
3527                 return count;
3528         }
3529
3530         uint16_t i;
3531         uint16_t size = ixgbe_xstats_calc_num();
3532         uint64_t values_copy[size];
3533
3534         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3535
3536         for (i = 0; i < n; i++) {
3537                 if (ids[i] >= size) {
3538                         PMD_INIT_LOG(ERR, "id value isn't valid");
3539                         return -1;
3540                 }
3541                 values[i] = values_copy[ids[i]];
3542         }
3543         return n;
3544 }
3545
3546 static void
3547 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3548 {
3549         struct ixgbe_hw_stats *stats =
3550                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3551         struct ixgbe_macsec_stats *macsec_stats =
3552                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3553                                 dev->data->dev_private);
3554
3555         unsigned count = ixgbe_xstats_calc_num();
3556
3557         /* HW registers are cleared on read */
3558         ixgbe_dev_xstats_get(dev, NULL, count);
3559
3560         /* Reset software totals */
3561         memset(stats, 0, sizeof(*stats));
3562         memset(macsec_stats, 0, sizeof(*macsec_stats));
3563 }
3564
3565 static void
3566 ixgbevf_update_stats(struct rte_eth_dev *dev)
3567 {
3568         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3569         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3570                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3571
3572         /* Good Rx packet, include VF loopback */
3573         UPDATE_VF_STAT(IXGBE_VFGPRC,
3574             hw_stats->last_vfgprc, hw_stats->vfgprc);
3575
3576         /* Good Rx octets, include VF loopback */
3577         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3578             hw_stats->last_vfgorc, hw_stats->vfgorc);
3579
3580         /* Good Tx packet, include VF loopback */
3581         UPDATE_VF_STAT(IXGBE_VFGPTC,
3582             hw_stats->last_vfgptc, hw_stats->vfgptc);
3583
3584         /* Good Tx octets, include VF loopback */
3585         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3586             hw_stats->last_vfgotc, hw_stats->vfgotc);
3587
3588         /* Rx Multicst Packet */
3589         UPDATE_VF_STAT(IXGBE_VFMPRC,
3590             hw_stats->last_vfmprc, hw_stats->vfmprc);
3591 }
3592
3593 static int
3594 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3595                        unsigned n)
3596 {
3597         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3598                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3599         unsigned i;
3600
3601         if (n < IXGBEVF_NB_XSTATS)
3602                 return IXGBEVF_NB_XSTATS;
3603
3604         ixgbevf_update_stats(dev);
3605
3606         if (!xstats)
3607                 return 0;
3608
3609         /* Extended stats */
3610         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3611                 xstats[i].id = i;
3612                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3613                         rte_ixgbevf_stats_strings[i].offset);
3614         }
3615
3616         return IXGBEVF_NB_XSTATS;
3617 }
3618
3619 static int
3620 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3621 {
3622         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3623                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3624
3625         ixgbevf_update_stats(dev);
3626
3627         if (stats == NULL)
3628                 return -EINVAL;
3629
3630         stats->ipackets = hw_stats->vfgprc;
3631         stats->ibytes = hw_stats->vfgorc;
3632         stats->opackets = hw_stats->vfgptc;
3633         stats->obytes = hw_stats->vfgotc;
3634         return 0;
3635 }
3636
3637 static void
3638 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3639 {
3640         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3641                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3642
3643         /* Sync HW register to the last stats */
3644         ixgbevf_dev_stats_get(dev, NULL);
3645
3646         /* reset HW current stats*/
3647         hw_stats->vfgprc = 0;
3648         hw_stats->vfgorc = 0;
3649         hw_stats->vfgptc = 0;
3650         hw_stats->vfgotc = 0;
3651 }
3652
3653 static int
3654 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3655 {
3656         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3657         u16 eeprom_verh, eeprom_verl;
3658         u32 etrack_id;
3659         int ret;
3660
3661         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3662         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3663
3664         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3665         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3666
3667         ret += 1; /* add the size of '\0' */
3668         if (fw_size < (u32)ret)
3669                 return ret;
3670         else
3671                 return 0;
3672 }
3673
3674 static void
3675 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3676 {
3677         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3678         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3679         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3680
3681         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3682         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3683         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3684                 /*
3685                  * When DCB/VT is off, maximum number of queues changes,
3686                  * except for 82598EB, which remains constant.
3687                  */
3688                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3689                                 hw->mac.type != ixgbe_mac_82598EB)
3690                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3691         }
3692         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3693         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3694         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3695         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3696         dev_info->max_vfs = pci_dev->max_vfs;
3697         if (hw->mac.type == ixgbe_mac_82598EB)
3698                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3699         else
3700                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3701         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3702         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3703         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3704                                      dev_info->rx_queue_offload_capa);
3705         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3706         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3707
3708         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3709                 .rx_thresh = {
3710                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3711                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3712                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3713                 },
3714                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3715                 .rx_drop_en = 0,
3716                 .offloads = 0,
3717         };
3718
3719         dev_info->default_txconf = (struct rte_eth_txconf) {
3720                 .tx_thresh = {
3721                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3722                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3723                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3724                 },
3725                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3726                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3727                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3728                              ETH_TXQ_FLAGS_NOOFFLOADS |
3729                              ETH_TXQ_FLAGS_IGNORE,
3730                 .offloads = 0,
3731         };
3732
3733         dev_info->rx_desc_lim = rx_desc_lim;
3734         dev_info->tx_desc_lim = tx_desc_lim;
3735
3736         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3737         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3738         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3739
3740         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3741         if (hw->mac.type == ixgbe_mac_X540 ||
3742             hw->mac.type == ixgbe_mac_X540_vf ||
3743             hw->mac.type == ixgbe_mac_X550 ||
3744             hw->mac.type == ixgbe_mac_X550_vf) {
3745                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3746         }
3747         if (hw->mac.type == ixgbe_mac_X550) {
3748                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3749                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3750         }
3751 }
3752
3753 static const uint32_t *
3754 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3755 {
3756         static const uint32_t ptypes[] = {
3757                 /* For non-vec functions,
3758                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3759                  * for vec functions,
3760                  * refers to _recv_raw_pkts_vec().
3761                  */
3762                 RTE_PTYPE_L2_ETHER,
3763                 RTE_PTYPE_L3_IPV4,
3764                 RTE_PTYPE_L3_IPV4_EXT,
3765                 RTE_PTYPE_L3_IPV6,
3766                 RTE_PTYPE_L3_IPV6_EXT,
3767                 RTE_PTYPE_L4_SCTP,
3768                 RTE_PTYPE_L4_TCP,
3769                 RTE_PTYPE_L4_UDP,
3770                 RTE_PTYPE_TUNNEL_IP,
3771                 RTE_PTYPE_INNER_L3_IPV6,
3772                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3773                 RTE_PTYPE_INNER_L4_TCP,
3774                 RTE_PTYPE_INNER_L4_UDP,
3775                 RTE_PTYPE_UNKNOWN
3776         };
3777
3778         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3779             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3780             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3781             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3782                 return ptypes;
3783
3784 #if defined(RTE_ARCH_X86)
3785         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3786             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3787                 return ptypes;
3788 #endif
3789         return NULL;
3790 }
3791
3792 static void
3793 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3794                      struct rte_eth_dev_info *dev_info)
3795 {
3796         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3797         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3798
3799         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3800         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3801         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3802         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3803         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3804         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3805         dev_info->max_vfs = pci_dev->max_vfs;
3806         if (hw->mac.type == ixgbe_mac_82598EB)
3807                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3808         else
3809                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3810         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3811         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3812                                      dev_info->rx_queue_offload_capa);
3813         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3814         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3815
3816         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3817                 .rx_thresh = {
3818                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3819                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3820                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3821                 },
3822                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3823                 .rx_drop_en = 0,
3824                 .offloads = 0,
3825         };
3826
3827         dev_info->default_txconf = (struct rte_eth_txconf) {
3828                 .tx_thresh = {
3829                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3830                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3831                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3832                 },
3833                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3834                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3835                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3836                              ETH_TXQ_FLAGS_NOOFFLOADS |
3837                              ETH_TXQ_FLAGS_IGNORE,
3838                 .offloads = 0,
3839         };
3840
3841         dev_info->rx_desc_lim = rx_desc_lim;
3842         dev_info->tx_desc_lim = tx_desc_lim;
3843 }
3844
3845 static int
3846 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3847                    int *link_up, int wait_to_complete)
3848 {
3849         /**
3850          * for a quick link status checking, wait_to_compelet == 0,
3851          * skip PF link status checking
3852          */
3853         bool no_pflink_check = wait_to_complete == 0;
3854         struct ixgbe_mbx_info *mbx = &hw->mbx;
3855         struct ixgbe_mac_info *mac = &hw->mac;
3856         uint32_t links_reg, in_msg;
3857         int ret_val = 0;
3858
3859         /* If we were hit with a reset drop the link */
3860         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3861                 mac->get_link_status = true;
3862
3863         if (!mac->get_link_status)
3864                 goto out;
3865
3866         /* if link status is down no point in checking to see if pf is up */
3867         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3868         if (!(links_reg & IXGBE_LINKS_UP))
3869                 goto out;
3870
3871         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3872          * before the link status is correct
3873          */
3874         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3875                 int i;
3876
3877                 for (i = 0; i < 5; i++) {
3878                         rte_delay_us(100);
3879                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3880
3881                         if (!(links_reg & IXGBE_LINKS_UP))
3882                                 goto out;
3883                 }
3884         }
3885
3886         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3887         case IXGBE_LINKS_SPEED_10G_82599:
3888                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3889                 if (hw->mac.type >= ixgbe_mac_X550) {
3890                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3891                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3892                 }
3893                 break;
3894         case IXGBE_LINKS_SPEED_1G_82599:
3895                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3896                 break;
3897         case IXGBE_LINKS_SPEED_100_82599:
3898                 *speed = IXGBE_LINK_SPEED_100_FULL;
3899                 if (hw->mac.type == ixgbe_mac_X550) {
3900                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3901                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3902                 }
3903                 break;
3904         case IXGBE_LINKS_SPEED_10_X550EM_A:
3905                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3906                 /* Since Reserved in older MAC's */
3907                 if (hw->mac.type >= ixgbe_mac_X550)
3908                         *speed = IXGBE_LINK_SPEED_10_FULL;
3909                 break;
3910         default:
3911                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3912         }
3913
3914         if (no_pflink_check) {
3915                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3916                         mac->get_link_status = true;
3917                 else
3918                         mac->get_link_status = false;
3919
3920                 goto out;
3921         }
3922         /* if the read failed it could just be a mailbox collision, best wait
3923          * until we are called again and don't report an error
3924          */
3925         if (mbx->ops.read(hw, &in_msg, 1, 0))
3926                 goto out;
3927
3928         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3929                 /* msg is not CTS and is NACK we must have lost CTS status */
3930                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3931                         ret_val = -1;
3932                 goto out;
3933         }
3934
3935         /* the pf is talking, if we timed out in the past we reinit */
3936         if (!mbx->timeout) {
3937                 ret_val = -1;
3938                 goto out;
3939         }
3940
3941         /* if we passed all the tests above then the link is up and we no
3942          * longer need to check for link
3943          */
3944         mac->get_link_status = false;
3945
3946 out:
3947         *link_up = !mac->get_link_status;
3948         return ret_val;
3949 }
3950
3951 /* return 0 means link status changed, -1 means not changed */
3952 int
3953 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3954                             int wait_to_complete, int vf)
3955 {
3956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3957         struct rte_eth_link link;
3958         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3959         struct ixgbe_interrupt *intr =
3960                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3961         int link_up;
3962         int diag;
3963         u32 speed = 0;
3964         int wait = 1;
3965         bool autoneg = false;
3966
3967         memset(&link, 0, sizeof(link));
3968         link.link_status = ETH_LINK_DOWN;
3969         link.link_speed = ETH_SPEED_NUM_NONE;
3970         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3971         link.link_autoneg = ETH_LINK_AUTONEG;
3972
3973         hw->mac.get_link_status = true;
3974
3975         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3976                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3977                 speed = hw->phy.autoneg_advertised;
3978                 if (!speed)
3979                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3980                 ixgbe_setup_link(hw, speed, true);
3981         }
3982
3983         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3984         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3985                 wait = 0;
3986
3987         if (vf)
3988                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3989         else
3990                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3991
3992         if (diag != 0) {
3993                 link.link_speed = ETH_SPEED_NUM_100M;
3994                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3995                 return rte_eth_linkstatus_set(dev, &link);
3996         }
3997
3998         if (link_up == 0) {
3999                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4000                 return rte_eth_linkstatus_set(dev, &link);
4001         }
4002
4003         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4004         link.link_status = ETH_LINK_UP;
4005         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4006
4007         switch (link_speed) {
4008         default:
4009         case IXGBE_LINK_SPEED_UNKNOWN:
4010                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4011                 link.link_speed = ETH_SPEED_NUM_100M;
4012                 break;
4013
4014         case IXGBE_LINK_SPEED_100_FULL:
4015                 link.link_speed = ETH_SPEED_NUM_100M;
4016                 break;
4017
4018         case IXGBE_LINK_SPEED_1GB_FULL:
4019                 link.link_speed = ETH_SPEED_NUM_1G;
4020                 break;
4021
4022         case IXGBE_LINK_SPEED_2_5GB_FULL:
4023                 link.link_speed = ETH_SPEED_NUM_2_5G;
4024                 break;
4025
4026         case IXGBE_LINK_SPEED_5GB_FULL:
4027                 link.link_speed = ETH_SPEED_NUM_5G;
4028                 break;
4029
4030         case IXGBE_LINK_SPEED_10GB_FULL:
4031                 link.link_speed = ETH_SPEED_NUM_10G;
4032                 break;
4033         }
4034
4035         return rte_eth_linkstatus_set(dev, &link);
4036 }
4037
4038 static int
4039 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4040 {
4041         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4042 }
4043
4044 static int
4045 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4046 {
4047         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4048 }
4049
4050 static void
4051 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4052 {
4053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4054         uint32_t fctrl;
4055
4056         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4057         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4058         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4059 }
4060
4061 static void
4062 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4063 {
4064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4065         uint32_t fctrl;
4066
4067         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4068         fctrl &= (~IXGBE_FCTRL_UPE);
4069         if (dev->data->all_multicast == 1)
4070                 fctrl |= IXGBE_FCTRL_MPE;
4071         else
4072                 fctrl &= (~IXGBE_FCTRL_MPE);
4073         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4074 }
4075
4076 static void
4077 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4078 {
4079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4080         uint32_t fctrl;
4081
4082         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4083         fctrl |= IXGBE_FCTRL_MPE;
4084         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4085 }
4086
4087 static void
4088 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4089 {
4090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4091         uint32_t fctrl;
4092
4093         if (dev->data->promiscuous == 1)
4094                 return; /* must remain in all_multicast mode */
4095
4096         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4097         fctrl &= (~IXGBE_FCTRL_MPE);
4098         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4099 }
4100
4101 /**
4102  * It clears the interrupt causes and enables the interrupt.
4103  * It will be called once only during nic initialized.
4104  *
4105  * @param dev
4106  *  Pointer to struct rte_eth_dev.
4107  * @param on
4108  *  Enable or Disable.
4109  *
4110  * @return
4111  *  - On success, zero.
4112  *  - On failure, a negative value.
4113  */
4114 static int
4115 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4116 {
4117         struct ixgbe_interrupt *intr =
4118                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4119
4120         ixgbe_dev_link_status_print(dev);
4121         if (on)
4122                 intr->mask |= IXGBE_EICR_LSC;
4123         else
4124                 intr->mask &= ~IXGBE_EICR_LSC;
4125
4126         return 0;
4127 }
4128
4129 /**
4130  * It clears the interrupt causes and enables the interrupt.
4131  * It will be called once only during nic initialized.
4132  *
4133  * @param dev
4134  *  Pointer to struct rte_eth_dev.
4135  *
4136  * @return
4137  *  - On success, zero.
4138  *  - On failure, a negative value.
4139  */
4140 static int
4141 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4142 {
4143         struct ixgbe_interrupt *intr =
4144                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4145
4146         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4147
4148         return 0;
4149 }
4150
4151 /**
4152  * It clears the interrupt causes and enables the interrupt.
4153  * It will be called once only during nic initialized.
4154  *
4155  * @param dev
4156  *  Pointer to struct rte_eth_dev.
4157  *
4158  * @return
4159  *  - On success, zero.
4160  *  - On failure, a negative value.
4161  */
4162 static int
4163 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4164 {
4165         struct ixgbe_interrupt *intr =
4166                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4167
4168         intr->mask |= IXGBE_EICR_LINKSEC;
4169
4170         return 0;
4171 }
4172
4173 /*
4174  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4175  *
4176  * @param dev
4177  *  Pointer to struct rte_eth_dev.
4178  *
4179  * @return
4180  *  - On success, zero.
4181  *  - On failure, a negative value.
4182  */
4183 static int
4184 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4185 {
4186         uint32_t eicr;
4187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188         struct ixgbe_interrupt *intr =
4189                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4190
4191         /* clear all cause mask */
4192         ixgbe_disable_intr(hw);
4193
4194         /* read-on-clear nic registers here */
4195         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4196         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4197
4198         intr->flags = 0;
4199
4200         /* set flag for async link update */
4201         if (eicr & IXGBE_EICR_LSC)
4202                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4203
4204         if (eicr & IXGBE_EICR_MAILBOX)
4205                 intr->flags |= IXGBE_FLAG_MAILBOX;
4206
4207         if (eicr & IXGBE_EICR_LINKSEC)
4208                 intr->flags |= IXGBE_FLAG_MACSEC;
4209
4210         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4211             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4212             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4213                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4214
4215         return 0;
4216 }
4217
4218 /**
4219  * It gets and then prints the link status.
4220  *
4221  * @param dev
4222  *  Pointer to struct rte_eth_dev.
4223  *
4224  * @return
4225  *  - On success, zero.
4226  *  - On failure, a negative value.
4227  */
4228 static void
4229 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4230 {
4231         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4232         struct rte_eth_link link;
4233
4234         rte_eth_linkstatus_get(dev, &link);
4235
4236         if (link.link_status) {
4237                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4238                                         (int)(dev->data->port_id),
4239                                         (unsigned)link.link_speed,
4240                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4241                                         "full-duplex" : "half-duplex");
4242         } else {
4243                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4244                                 (int)(dev->data->port_id));
4245         }
4246         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4247                                 pci_dev->addr.domain,
4248                                 pci_dev->addr.bus,
4249                                 pci_dev->addr.devid,
4250                                 pci_dev->addr.function);
4251 }
4252
4253 /*
4254  * It executes link_update after knowing an interrupt occurred.
4255  *
4256  * @param dev
4257  *  Pointer to struct rte_eth_dev.
4258  *
4259  * @return
4260  *  - On success, zero.
4261  *  - On failure, a negative value.
4262  */
4263 static int
4264 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4265                            struct rte_intr_handle *intr_handle)
4266 {
4267         struct ixgbe_interrupt *intr =
4268                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4269         int64_t timeout;
4270         struct ixgbe_hw *hw =
4271                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4272
4273         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4274
4275         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4276                 ixgbe_pf_mbx_process(dev);
4277                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4278         }
4279
4280         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4281                 ixgbe_handle_lasi(hw);
4282                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4283         }
4284
4285         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4286                 struct rte_eth_link link;
4287
4288                 /* get the link status before link update, for predicting later */
4289                 rte_eth_linkstatus_get(dev, &link);
4290
4291                 ixgbe_dev_link_update(dev, 0);
4292
4293                 /* likely to up */
4294                 if (!link.link_status)
4295                         /* handle it 1 sec later, wait it being stable */
4296                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4297                 /* likely to down */
4298                 else
4299                         /* handle it 4 sec later, wait it being stable */
4300                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4301
4302                 ixgbe_dev_link_status_print(dev);
4303                 if (rte_eal_alarm_set(timeout * 1000,
4304                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4305                         PMD_DRV_LOG(ERR, "Error setting alarm");
4306                 else {
4307                         /* remember original mask */
4308                         intr->mask_original = intr->mask;
4309                         /* only disable lsc interrupt */
4310                         intr->mask &= ~IXGBE_EIMS_LSC;
4311                 }
4312         }
4313
4314         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4315         ixgbe_enable_intr(dev);
4316         rte_intr_enable(intr_handle);
4317
4318         return 0;
4319 }
4320
4321 /**
4322  * Interrupt handler which shall be registered for alarm callback for delayed
4323  * handling specific interrupt to wait for the stable nic state. As the
4324  * NIC interrupt state is not stable for ixgbe after link is just down,
4325  * it needs to wait 4 seconds to get the stable status.
4326  *
4327  * @param handle
4328  *  Pointer to interrupt handle.
4329  * @param param
4330  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4331  *
4332  * @return
4333  *  void
4334  */
4335 static void
4336 ixgbe_dev_interrupt_delayed_handler(void *param)
4337 {
4338         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4339         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4341         struct ixgbe_interrupt *intr =
4342                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4343         struct ixgbe_hw *hw =
4344                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4345         uint32_t eicr;
4346
4347         ixgbe_disable_intr(hw);
4348
4349         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4350         if (eicr & IXGBE_EICR_MAILBOX)
4351                 ixgbe_pf_mbx_process(dev);
4352
4353         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4354                 ixgbe_handle_lasi(hw);
4355                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4356         }
4357
4358         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4359                 ixgbe_dev_link_update(dev, 0);
4360                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4361                 ixgbe_dev_link_status_print(dev);
4362                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4363                                               NULL);
4364         }
4365
4366         if (intr->flags & IXGBE_FLAG_MACSEC) {
4367                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4368                                               NULL);
4369                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4370         }
4371
4372         /* restore original mask */
4373         intr->mask = intr->mask_original;
4374         intr->mask_original = 0;
4375
4376         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4377         ixgbe_enable_intr(dev);
4378         rte_intr_enable(intr_handle);
4379 }
4380
4381 /**
4382  * Interrupt handler triggered by NIC  for handling
4383  * specific interrupt.
4384  *
4385  * @param handle
4386  *  Pointer to interrupt handle.
4387  * @param param
4388  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4389  *
4390  * @return
4391  *  void
4392  */
4393 static void
4394 ixgbe_dev_interrupt_handler(void *param)
4395 {
4396         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4397
4398         ixgbe_dev_interrupt_get_status(dev);
4399         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4400 }
4401
4402 static int
4403 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4404 {
4405         struct ixgbe_hw *hw;
4406
4407         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4408         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4409 }
4410
4411 static int
4412 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4413 {
4414         struct ixgbe_hw *hw;
4415
4416         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4417         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4418 }
4419
4420 static int
4421 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4422 {
4423         struct ixgbe_hw *hw;
4424         uint32_t mflcn_reg;
4425         uint32_t fccfg_reg;
4426         int rx_pause;
4427         int tx_pause;
4428
4429         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4430
4431         fc_conf->pause_time = hw->fc.pause_time;
4432         fc_conf->high_water = hw->fc.high_water[0];
4433         fc_conf->low_water = hw->fc.low_water[0];
4434         fc_conf->send_xon = hw->fc.send_xon;
4435         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4436
4437         /*
4438          * Return rx_pause status according to actual setting of
4439          * MFLCN register.
4440          */
4441         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4442         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4443                 rx_pause = 1;
4444         else
4445                 rx_pause = 0;
4446
4447         /*
4448          * Return tx_pause status according to actual setting of
4449          * FCCFG register.
4450          */
4451         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4452         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4453                 tx_pause = 1;
4454         else
4455                 tx_pause = 0;
4456
4457         if (rx_pause && tx_pause)
4458                 fc_conf->mode = RTE_FC_FULL;
4459         else if (rx_pause)
4460                 fc_conf->mode = RTE_FC_RX_PAUSE;
4461         else if (tx_pause)
4462                 fc_conf->mode = RTE_FC_TX_PAUSE;
4463         else
4464                 fc_conf->mode = RTE_FC_NONE;
4465
4466         return 0;
4467 }
4468
4469 static int
4470 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4471 {
4472         struct ixgbe_hw *hw;
4473         int err;
4474         uint32_t rx_buf_size;
4475         uint32_t max_high_water;
4476         uint32_t mflcn;
4477         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4478                 ixgbe_fc_none,
4479                 ixgbe_fc_rx_pause,
4480                 ixgbe_fc_tx_pause,
4481                 ixgbe_fc_full
4482         };
4483
4484         PMD_INIT_FUNC_TRACE();
4485
4486         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4487         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4488         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4489
4490         /*
4491          * At least reserve one Ethernet frame for watermark
4492          * high_water/low_water in kilo bytes for ixgbe
4493          */
4494         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4495         if ((fc_conf->high_water > max_high_water) ||
4496                 (fc_conf->high_water < fc_conf->low_water)) {
4497                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4498                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4499                 return -EINVAL;
4500         }
4501
4502         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4503         hw->fc.pause_time     = fc_conf->pause_time;
4504         hw->fc.high_water[0]  = fc_conf->high_water;
4505         hw->fc.low_water[0]   = fc_conf->low_water;
4506         hw->fc.send_xon       = fc_conf->send_xon;
4507         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4508
4509         err = ixgbe_fc_enable(hw);
4510
4511         /* Not negotiated is not an error case */
4512         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4513
4514                 /* check if we want to forward MAC frames - driver doesn't have native
4515                  * capability to do that, so we'll write the registers ourselves */
4516
4517                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4518
4519                 /* set or clear MFLCN.PMCF bit depending on configuration */
4520                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4521                         mflcn |= IXGBE_MFLCN_PMCF;
4522                 else
4523                         mflcn &= ~IXGBE_MFLCN_PMCF;
4524
4525                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4526                 IXGBE_WRITE_FLUSH(hw);
4527
4528                 return 0;
4529         }
4530
4531         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4532         return -EIO;
4533 }
4534
4535 /**
4536  *  ixgbe_pfc_enable_generic - Enable flow control
4537  *  @hw: pointer to hardware structure
4538  *  @tc_num: traffic class number
4539  *  Enable flow control according to the current settings.
4540  */
4541 static int
4542 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4543 {
4544         int ret_val = 0;
4545         uint32_t mflcn_reg, fccfg_reg;
4546         uint32_t reg;
4547         uint32_t fcrtl, fcrth;
4548         uint8_t i;
4549         uint8_t nb_rx_en;
4550
4551         /* Validate the water mark configuration */
4552         if (!hw->fc.pause_time) {
4553                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4554                 goto out;
4555         }
4556
4557         /* Low water mark of zero causes XOFF floods */
4558         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4559                  /* High/Low water can not be 0 */
4560                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4561                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4562                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4563                         goto out;
4564                 }
4565
4566                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4567                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4568                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4569                         goto out;
4570                 }
4571         }
4572         /* Negotiate the fc mode to use */
4573         ixgbe_fc_autoneg(hw);
4574
4575         /* Disable any previous flow control settings */
4576         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4577         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4578
4579         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4580         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4581
4582         switch (hw->fc.current_mode) {
4583         case ixgbe_fc_none:
4584                 /*
4585                  * If the count of enabled RX Priority Flow control >1,
4586                  * and the TX pause can not be disabled
4587                  */
4588                 nb_rx_en = 0;
4589                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4590                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4591                         if (reg & IXGBE_FCRTH_FCEN)
4592                                 nb_rx_en++;
4593                 }
4594                 if (nb_rx_en > 1)
4595                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4596                 break;
4597         case ixgbe_fc_rx_pause:
4598                 /*
4599                  * Rx Flow control is enabled and Tx Flow control is
4600                  * disabled by software override. Since there really
4601                  * isn't a way to advertise that we are capable of RX
4602                  * Pause ONLY, we will advertise that we support both
4603                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4604                  * disable the adapter's ability to send PAUSE frames.
4605                  */
4606                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4607                 /*
4608                  * If the count of enabled RX Priority Flow control >1,
4609                  * and the TX pause can not be disabled
4610                  */
4611                 nb_rx_en = 0;
4612                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4613                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4614                         if (reg & IXGBE_FCRTH_FCEN)
4615                                 nb_rx_en++;
4616                 }
4617                 if (nb_rx_en > 1)
4618                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4619                 break;
4620         case ixgbe_fc_tx_pause:
4621                 /*
4622                  * Tx Flow control is enabled, and Rx Flow control is
4623                  * disabled by software override.
4624                  */
4625                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4626                 break;
4627         case ixgbe_fc_full:
4628                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4629                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4630                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4631                 break;
4632         default:
4633                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4634                 ret_val = IXGBE_ERR_CONFIG;
4635                 goto out;
4636         }
4637
4638         /* Set 802.3x based flow control settings. */
4639         mflcn_reg |= IXGBE_MFLCN_DPF;
4640         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4641         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4642
4643         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4644         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4645                 hw->fc.high_water[tc_num]) {
4646                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4647                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4648                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4649         } else {
4650                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4651                 /*
4652                  * In order to prevent Tx hangs when the internal Tx
4653                  * switch is enabled we must set the high water mark
4654                  * to the maximum FCRTH value.  This allows the Tx
4655                  * switch to function even under heavy Rx workloads.
4656                  */
4657                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4658         }
4659         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4660
4661         /* Configure pause time (2 TCs per register) */
4662         reg = hw->fc.pause_time * 0x00010001;
4663         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4664                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4665
4666         /* Configure flow control refresh threshold value */
4667         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4668
4669 out:
4670         return ret_val;
4671 }
4672
4673 static int
4674 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4675 {
4676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4678
4679         if (hw->mac.type != ixgbe_mac_82598EB) {
4680                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4681         }
4682         return ret_val;
4683 }
4684
4685 static int
4686 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4687 {
4688         int err;
4689         uint32_t rx_buf_size;
4690         uint32_t max_high_water;
4691         uint8_t tc_num;
4692         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4693         struct ixgbe_hw *hw =
4694                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695         struct ixgbe_dcb_config *dcb_config =
4696                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4697
4698         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4699                 ixgbe_fc_none,
4700                 ixgbe_fc_rx_pause,
4701                 ixgbe_fc_tx_pause,
4702                 ixgbe_fc_full
4703         };
4704
4705         PMD_INIT_FUNC_TRACE();
4706
4707         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4708         tc_num = map[pfc_conf->priority];
4709         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4710         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4711         /*
4712          * At least reserve one Ethernet frame for watermark
4713          * high_water/low_water in kilo bytes for ixgbe
4714          */
4715         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4716         if ((pfc_conf->fc.high_water > max_high_water) ||
4717             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4718                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4719                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4720                 return -EINVAL;
4721         }
4722
4723         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4724         hw->fc.pause_time = pfc_conf->fc.pause_time;
4725         hw->fc.send_xon = pfc_conf->fc.send_xon;
4726         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4727         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4728
4729         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4730
4731         /* Not negotiated is not an error case */
4732         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4733                 return 0;
4734
4735         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4736         return -EIO;
4737 }
4738
4739 static int
4740 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4741                           struct rte_eth_rss_reta_entry64 *reta_conf,
4742                           uint16_t reta_size)
4743 {
4744         uint16_t i, sp_reta_size;
4745         uint8_t j, mask;
4746         uint32_t reta, r;
4747         uint16_t idx, shift;
4748         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4749         uint32_t reta_reg;
4750
4751         PMD_INIT_FUNC_TRACE();
4752
4753         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4754                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4755                         "NIC.");
4756                 return -ENOTSUP;
4757         }
4758
4759         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4760         if (reta_size != sp_reta_size) {
4761                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4762                         "(%d) doesn't match the number hardware can supported "
4763                         "(%d)", reta_size, sp_reta_size);
4764                 return -EINVAL;
4765         }
4766
4767         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4768                 idx = i / RTE_RETA_GROUP_SIZE;
4769                 shift = i % RTE_RETA_GROUP_SIZE;
4770                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4771                                                 IXGBE_4_BIT_MASK);
4772                 if (!mask)
4773                         continue;
4774                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4775                 if (mask == IXGBE_4_BIT_MASK)
4776                         r = 0;
4777                 else
4778                         r = IXGBE_READ_REG(hw, reta_reg);
4779                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4780                         if (mask & (0x1 << j))
4781                                 reta |= reta_conf[idx].reta[shift + j] <<
4782                                                         (CHAR_BIT * j);
4783                         else
4784                                 reta |= r & (IXGBE_8_BIT_MASK <<
4785                                                 (CHAR_BIT * j));
4786                 }
4787                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4788         }
4789
4790         return 0;
4791 }
4792
4793 static int
4794 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4795                          struct rte_eth_rss_reta_entry64 *reta_conf,
4796                          uint16_t reta_size)
4797 {
4798         uint16_t i, sp_reta_size;
4799         uint8_t j, mask;
4800         uint32_t reta;
4801         uint16_t idx, shift;
4802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4803         uint32_t reta_reg;
4804
4805         PMD_INIT_FUNC_TRACE();
4806         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4807         if (reta_size != sp_reta_size) {
4808                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4809                         "(%d) doesn't match the number hardware can supported "
4810                         "(%d)", reta_size, sp_reta_size);
4811                 return -EINVAL;
4812         }
4813
4814         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4815                 idx = i / RTE_RETA_GROUP_SIZE;
4816                 shift = i % RTE_RETA_GROUP_SIZE;
4817                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4818                                                 IXGBE_4_BIT_MASK);
4819                 if (!mask)
4820                         continue;
4821
4822                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4823                 reta = IXGBE_READ_REG(hw, reta_reg);
4824                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4825                         if (mask & (0x1 << j))
4826                                 reta_conf[idx].reta[shift + j] =
4827                                         ((reta >> (CHAR_BIT * j)) &
4828                                                 IXGBE_8_BIT_MASK);
4829                 }
4830         }
4831
4832         return 0;
4833 }
4834
4835 static int
4836 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4837                                 uint32_t index, uint32_t pool)
4838 {
4839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4840         uint32_t enable_addr = 1;
4841
4842         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4843                              pool, enable_addr);
4844 }
4845
4846 static void
4847 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4848 {
4849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850
4851         ixgbe_clear_rar(hw, index);
4852 }
4853
4854 static int
4855 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4856 {
4857         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4858
4859         ixgbe_remove_rar(dev, 0);
4860         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4861
4862         return 0;
4863 }
4864
4865 static bool
4866 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4867 {
4868         if (strcmp(dev->device->driver->name, drv->driver.name))
4869                 return false;
4870
4871         return true;
4872 }
4873
4874 bool
4875 is_ixgbe_supported(struct rte_eth_dev *dev)
4876 {
4877         return is_device_supported(dev, &rte_ixgbe_pmd);
4878 }
4879
4880 static int
4881 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4882 {
4883         uint32_t hlreg0;
4884         uint32_t maxfrs;
4885         struct ixgbe_hw *hw;
4886         struct rte_eth_dev_info dev_info;
4887         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4888         struct rte_eth_dev_data *dev_data = dev->data;
4889
4890         ixgbe_dev_info_get(dev, &dev_info);
4891
4892         /* check that mtu is within the allowed range */
4893         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4894                 return -EINVAL;
4895
4896         /* If device is started, refuse mtu that requires the support of
4897          * scattered packets when this feature has not been enabled before.
4898          */
4899         if (dev_data->dev_started && !dev_data->scattered_rx &&
4900             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4901              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4902                 PMD_INIT_LOG(ERR, "Stop port first.");
4903                 return -EINVAL;
4904         }
4905
4906         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4907         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4908
4909         /* switch to jumbo mode if needed */
4910         if (frame_size > ETHER_MAX_LEN) {
4911                 dev->data->dev_conf.rxmode.offloads |=
4912                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4913                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4914         } else {
4915                 dev->data->dev_conf.rxmode.offloads &=
4916                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4917                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4918         }
4919         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4920
4921         /* update max frame size */
4922         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4923
4924         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4925         maxfrs &= 0x0000FFFF;
4926         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4927         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4928
4929         return 0;
4930 }
4931
4932 /*
4933  * Virtual Function operations
4934  */
4935 static void
4936 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4937 {
4938         PMD_INIT_FUNC_TRACE();
4939
4940         /* Clear interrupt mask to stop from interrupts being generated */
4941         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4942
4943         IXGBE_WRITE_FLUSH(hw);
4944 }
4945
4946 static void
4947 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4948 {
4949         PMD_INIT_FUNC_TRACE();
4950
4951         /* VF enable interrupt autoclean */
4952         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4953         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4954         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4955
4956         IXGBE_WRITE_FLUSH(hw);
4957 }
4958
4959 static int
4960 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4961 {
4962         struct rte_eth_conf *conf = &dev->data->dev_conf;
4963         struct ixgbe_adapter *adapter =
4964                         (struct ixgbe_adapter *)dev->data->dev_private;
4965         struct rte_eth_dev_info dev_info;
4966         uint64_t rx_offloads;
4967         uint64_t tx_offloads;
4968
4969         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4970                      dev->data->port_id);
4971
4972         ixgbevf_dev_info_get(dev, &dev_info);
4973         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4974         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4975                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4976                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4977                             rx_offloads, dev_info.rx_offload_capa);
4978                 return -ENOTSUP;
4979         }
4980         tx_offloads = dev->data->dev_conf.txmode.offloads;
4981         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4982                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4983                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4984                             tx_offloads, dev_info.tx_offload_capa);
4985                 return -ENOTSUP;
4986         }
4987
4988         /*
4989          * VF has no ability to enable/disable HW CRC
4990          * Keep the persistent behavior the same as Host PF
4991          */
4992 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4993         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4994                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4995                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4996         }
4997 #else
4998         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4999                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5000                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
5001         }
5002 #endif
5003
5004         /*
5005          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5006          * allocation or vector Rx preconditions we will reset it.
5007          */
5008         adapter->rx_bulk_alloc_allowed = true;
5009         adapter->rx_vec_allowed = true;
5010
5011         return 0;
5012 }
5013
5014 static int
5015 ixgbevf_dev_start(struct rte_eth_dev *dev)
5016 {
5017         struct ixgbe_hw *hw =
5018                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5019         uint32_t intr_vector = 0;
5020         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5021         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5022
5023         int err, mask = 0;
5024
5025         PMD_INIT_FUNC_TRACE();
5026
5027         err = hw->mac.ops.reset_hw(hw);
5028         if (err) {
5029                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5030                 return err;
5031         }
5032         hw->mac.get_link_status = true;
5033
5034         /* negotiate mailbox API version to use with the PF. */
5035         ixgbevf_negotiate_api(hw);
5036
5037         ixgbevf_dev_tx_init(dev);
5038
5039         /* This can fail when allocating mbufs for descriptor rings */
5040         err = ixgbevf_dev_rx_init(dev);
5041         if (err) {
5042                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5043                 ixgbe_dev_clear_queues(dev);
5044                 return err;
5045         }
5046
5047         /* Set vfta */
5048         ixgbevf_set_vfta_all(dev, 1);
5049
5050         /* Set HW strip */
5051         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5052                 ETH_VLAN_EXTEND_MASK;
5053         err = ixgbevf_vlan_offload_set(dev, mask);
5054         if (err) {
5055                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5056                 ixgbe_dev_clear_queues(dev);
5057                 return err;
5058         }
5059
5060         ixgbevf_dev_rxtx_start(dev);
5061
5062         ixgbevf_dev_link_update(dev, 0);
5063
5064         /* check and configure queue intr-vector mapping */
5065         if (rte_intr_cap_multiple(intr_handle) &&
5066             dev->data->dev_conf.intr_conf.rxq) {
5067                 /* According to datasheet, only vector 0/1/2 can be used,
5068                  * now only one vector is used for Rx queue
5069                  */
5070                 intr_vector = 1;
5071                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5072                         return -1;
5073         }
5074
5075         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5076                 intr_handle->intr_vec =
5077                         rte_zmalloc("intr_vec",
5078                                     dev->data->nb_rx_queues * sizeof(int), 0);
5079                 if (intr_handle->intr_vec == NULL) {
5080                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5081                                      " intr_vec", dev->data->nb_rx_queues);
5082                         return -ENOMEM;
5083                 }
5084         }
5085         ixgbevf_configure_msix(dev);
5086
5087         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5088          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5089          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5090          * is not cleared, it will fail when following rte_intr_enable( ) tries
5091          * to map Rx queue interrupt to other VFIO vectors.
5092          * So clear uio/vfio intr/evevnfd first to avoid failure.
5093          */
5094         rte_intr_disable(intr_handle);
5095
5096         rte_intr_enable(intr_handle);
5097
5098         /* Re-enable interrupt for VF */
5099         ixgbevf_intr_enable(hw);
5100
5101         return 0;
5102 }
5103
5104 static void
5105 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5106 {
5107         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5108         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5109         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5110
5111         PMD_INIT_FUNC_TRACE();
5112
5113         ixgbevf_intr_disable(hw);
5114
5115         hw->adapter_stopped = 1;
5116         ixgbe_stop_adapter(hw);
5117
5118         /*
5119           * Clear what we set, but we still keep shadow_vfta to
5120           * restore after device starts
5121           */
5122         ixgbevf_set_vfta_all(dev, 0);
5123
5124         /* Clear stored conf */
5125         dev->data->scattered_rx = 0;
5126
5127         ixgbe_dev_clear_queues(dev);
5128
5129         /* Clean datapath event and queue/vec mapping */
5130         rte_intr_efd_disable(intr_handle);
5131         if (intr_handle->intr_vec != NULL) {
5132                 rte_free(intr_handle->intr_vec);
5133                 intr_handle->intr_vec = NULL;
5134         }
5135 }
5136
5137 static void
5138 ixgbevf_dev_close(struct rte_eth_dev *dev)
5139 {
5140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5141
5142         PMD_INIT_FUNC_TRACE();
5143
5144         ixgbe_reset_hw(hw);
5145
5146         ixgbevf_dev_stop(dev);
5147
5148         ixgbe_dev_free_queues(dev);
5149
5150         /**
5151          * Remove the VF MAC address ro ensure
5152          * that the VF traffic goes to the PF
5153          * after stop, close and detach of the VF
5154          **/
5155         ixgbevf_remove_mac_addr(dev, 0);
5156 }
5157
5158 /*
5159  * Reset VF device
5160  */
5161 static int
5162 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5163 {
5164         int ret;
5165
5166         ret = eth_ixgbevf_dev_uninit(dev);
5167         if (ret)
5168                 return ret;
5169
5170         ret = eth_ixgbevf_dev_init(dev);
5171
5172         return ret;
5173 }
5174
5175 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5176 {
5177         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5178         struct ixgbe_vfta *shadow_vfta =
5179                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5180         int i = 0, j = 0, vfta = 0, mask = 1;
5181
5182         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5183                 vfta = shadow_vfta->vfta[i];
5184                 if (vfta) {
5185                         mask = 1;
5186                         for (j = 0; j < 32; j++) {
5187                                 if (vfta & mask)
5188                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5189                                                        on, false);
5190                                 mask <<= 1;
5191                         }
5192                 }
5193         }
5194
5195 }
5196
5197 static int
5198 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5199 {
5200         struct ixgbe_hw *hw =
5201                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5202         struct ixgbe_vfta *shadow_vfta =
5203                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5204         uint32_t vid_idx = 0;
5205         uint32_t vid_bit = 0;
5206         int ret = 0;
5207
5208         PMD_INIT_FUNC_TRACE();
5209
5210         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5211         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5212         if (ret) {
5213                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5214                 return ret;
5215         }
5216         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5217         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5218
5219         /* Save what we set and retore it after device reset */
5220         if (on)
5221                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5222         else
5223                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5224
5225         return 0;
5226 }
5227
5228 static void
5229 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5230 {
5231         struct ixgbe_hw *hw =
5232                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5233         uint32_t ctrl;
5234
5235         PMD_INIT_FUNC_TRACE();
5236
5237         if (queue >= hw->mac.max_rx_queues)
5238                 return;
5239
5240         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5241         if (on)
5242                 ctrl |= IXGBE_RXDCTL_VME;
5243         else
5244                 ctrl &= ~IXGBE_RXDCTL_VME;
5245         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5246
5247         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5248 }
5249
5250 static int
5251 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5252 {
5253         struct ixgbe_rx_queue *rxq;
5254         uint16_t i;
5255         int on = 0;
5256
5257         /* VF function only support hw strip feature, others are not support */
5258         if (mask & ETH_VLAN_STRIP_MASK) {
5259                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5260                         rxq = dev->data->rx_queues[i];
5261                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5262                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5263                 }
5264         }
5265
5266         return 0;
5267 }
5268
5269 int
5270 ixgbe_vt_check(struct ixgbe_hw *hw)
5271 {
5272         uint32_t reg_val;
5273
5274         /* if Virtualization Technology is enabled */
5275         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5276         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5277                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5278                 return -1;
5279         }
5280
5281         return 0;
5282 }
5283
5284 static uint32_t
5285 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5286 {
5287         uint32_t vector = 0;
5288
5289         switch (hw->mac.mc_filter_type) {
5290         case 0:   /* use bits [47:36] of the address */
5291                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5292                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5293                 break;
5294         case 1:   /* use bits [46:35] of the address */
5295                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5296                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5297                 break;
5298         case 2:   /* use bits [45:34] of the address */
5299                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5300                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5301                 break;
5302         case 3:   /* use bits [43:32] of the address */
5303                 vector = ((uc_addr->addr_bytes[4]) |
5304                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5305                 break;
5306         default:  /* Invalid mc_filter_type */
5307                 break;
5308         }
5309
5310         /* vector can only be 12-bits or boundary will be exceeded */
5311         vector &= 0xFFF;
5312         return vector;
5313 }
5314
5315 static int
5316 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5317                         uint8_t on)
5318 {
5319         uint32_t vector;
5320         uint32_t uta_idx;
5321         uint32_t reg_val;
5322         uint32_t uta_shift;
5323         uint32_t rc;
5324         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5325         const uint32_t ixgbe_uta_bit_shift = 5;
5326         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5327         const uint32_t bit1 = 0x1;
5328
5329         struct ixgbe_hw *hw =
5330                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5331         struct ixgbe_uta_info *uta_info =
5332                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5333
5334         /* The UTA table only exists on 82599 hardware and newer */
5335         if (hw->mac.type < ixgbe_mac_82599EB)
5336                 return -ENOTSUP;
5337
5338         vector = ixgbe_uta_vector(hw, mac_addr);
5339         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5340         uta_shift = vector & ixgbe_uta_bit_mask;
5341
5342         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5343         if (rc == on)
5344                 return 0;
5345
5346         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5347         if (on) {
5348                 uta_info->uta_in_use++;
5349                 reg_val |= (bit1 << uta_shift);
5350                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5351         } else {
5352                 uta_info->uta_in_use--;
5353                 reg_val &= ~(bit1 << uta_shift);
5354                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5355         }
5356
5357         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5358
5359         if (uta_info->uta_in_use > 0)
5360                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5361                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5362         else
5363                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5364
5365         return 0;
5366 }
5367
5368 static int
5369 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5370 {
5371         int i;
5372         struct ixgbe_hw *hw =
5373                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5374         struct ixgbe_uta_info *uta_info =
5375                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5376
5377         /* The UTA table only exists on 82599 hardware and newer */
5378         if (hw->mac.type < ixgbe_mac_82599EB)
5379                 return -ENOTSUP;
5380
5381         if (on) {
5382                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5383                         uta_info->uta_shadow[i] = ~0;
5384                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5385                 }
5386         } else {
5387                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5388                         uta_info->uta_shadow[i] = 0;
5389                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5390                 }
5391         }
5392         return 0;
5393
5394 }
5395
5396 uint32_t
5397 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5398 {
5399         uint32_t new_val = orig_val;
5400
5401         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5402                 new_val |= IXGBE_VMOLR_AUPE;
5403         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5404                 new_val |= IXGBE_VMOLR_ROMPE;
5405         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5406                 new_val |= IXGBE_VMOLR_ROPE;
5407         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5408                 new_val |= IXGBE_VMOLR_BAM;
5409         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5410                 new_val |= IXGBE_VMOLR_MPE;
5411
5412         return new_val;
5413 }
5414
5415 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5416 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5417 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5418 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5419 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5420         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5421         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5422
5423 static int
5424 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5425                       struct rte_eth_mirror_conf *mirror_conf,
5426                       uint8_t rule_id, uint8_t on)
5427 {
5428         uint32_t mr_ctl, vlvf;
5429         uint32_t mp_lsb = 0;
5430         uint32_t mv_msb = 0;
5431         uint32_t mv_lsb = 0;
5432         uint32_t mp_msb = 0;
5433         uint8_t i = 0;
5434         int reg_index = 0;
5435         uint64_t vlan_mask = 0;
5436
5437         const uint8_t pool_mask_offset = 32;
5438         const uint8_t vlan_mask_offset = 32;
5439         const uint8_t dst_pool_offset = 8;
5440         const uint8_t rule_mr_offset  = 4;
5441         const uint8_t mirror_rule_mask = 0x0F;
5442
5443         struct ixgbe_mirror_info *mr_info =
5444                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5445         struct ixgbe_hw *hw =
5446                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5447         uint8_t mirror_type = 0;
5448
5449         if (ixgbe_vt_check(hw) < 0)
5450                 return -ENOTSUP;
5451
5452         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5453                 return -EINVAL;
5454
5455         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5456                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5457                             mirror_conf->rule_type);
5458                 return -EINVAL;
5459         }
5460
5461         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5462                 mirror_type |= IXGBE_MRCTL_VLME;
5463                 /* Check if vlan id is valid and find conresponding VLAN ID
5464                  * index in VLVF
5465                  */
5466                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5467                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5468                                 /* search vlan id related pool vlan filter
5469                                  * index
5470                                  */
5471                                 reg_index = ixgbe_find_vlvf_slot(
5472                                                 hw,
5473                                                 mirror_conf->vlan.vlan_id[i],
5474                                                 false);
5475                                 if (reg_index < 0)
5476                                         return -EINVAL;
5477                                 vlvf = IXGBE_READ_REG(hw,
5478                                                       IXGBE_VLVF(reg_index));
5479                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5480                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5481                                       mirror_conf->vlan.vlan_id[i]))
5482                                         vlan_mask |= (1ULL << reg_index);
5483                                 else
5484                                         return -EINVAL;
5485                         }
5486                 }
5487
5488                 if (on) {
5489                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5490                         mv_msb = vlan_mask >> vlan_mask_offset;
5491
5492                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5493                                                 mirror_conf->vlan.vlan_mask;
5494                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5495                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5496                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5497                                                 mirror_conf->vlan.vlan_id[i];
5498                         }
5499                 } else {
5500                         mv_lsb = 0;
5501                         mv_msb = 0;
5502                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5503                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5504                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5505                 }
5506         }
5507
5508         /**
5509          * if enable pool mirror, write related pool mask register,if disable
5510          * pool mirror, clear PFMRVM register
5511          */
5512         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5513                 mirror_type |= IXGBE_MRCTL_VPME;
5514                 if (on) {
5515                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5516                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5517                         mr_info->mr_conf[rule_id].pool_mask =
5518                                         mirror_conf->pool_mask;
5519
5520                 } else {
5521                         mp_lsb = 0;
5522                         mp_msb = 0;
5523                         mr_info->mr_conf[rule_id].pool_mask = 0;
5524                 }
5525         }
5526         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5527                 mirror_type |= IXGBE_MRCTL_UPME;
5528         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5529                 mirror_type |= IXGBE_MRCTL_DPME;
5530
5531         /* read  mirror control register and recalculate it */
5532         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5533
5534         if (on) {
5535                 mr_ctl |= mirror_type;
5536                 mr_ctl &= mirror_rule_mask;
5537                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5538         } else {
5539                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5540         }
5541
5542         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5543         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5544
5545         /* write mirrror control  register */
5546         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5547
5548         /* write pool mirrror control  register */
5549         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5550                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5551                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5552                                 mp_msb);
5553         }
5554         /* write VLAN mirrror control  register */
5555         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5556                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5557                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5558                                 mv_msb);
5559         }
5560
5561         return 0;
5562 }
5563
5564 static int
5565 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5566 {
5567         int mr_ctl = 0;
5568         uint32_t lsb_val = 0;
5569         uint32_t msb_val = 0;
5570         const uint8_t rule_mr_offset = 4;
5571
5572         struct ixgbe_hw *hw =
5573                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5574         struct ixgbe_mirror_info *mr_info =
5575                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5576
5577         if (ixgbe_vt_check(hw) < 0)
5578                 return -ENOTSUP;
5579
5580         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5581                 return -EINVAL;
5582
5583         memset(&mr_info->mr_conf[rule_id], 0,
5584                sizeof(struct rte_eth_mirror_conf));
5585
5586         /* clear PFVMCTL register */
5587         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5588
5589         /* clear pool mask register */
5590         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5591         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5592
5593         /* clear vlan mask register */
5594         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5595         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5596
5597         return 0;
5598 }
5599
5600 static int
5601 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5602 {
5603         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5604         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5605         uint32_t mask;
5606         struct ixgbe_hw *hw =
5607                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5608         uint32_t vec = IXGBE_MISC_VEC_ID;
5609
5610         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5611         if (rte_intr_allow_others(intr_handle))
5612                 vec = IXGBE_RX_VEC_START;
5613         mask |= (1 << vec);
5614         RTE_SET_USED(queue_id);
5615         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5616
5617         rte_intr_enable(intr_handle);
5618
5619         return 0;
5620 }
5621
5622 static int
5623 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5624 {
5625         uint32_t mask;
5626         struct ixgbe_hw *hw =
5627                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5628         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5629         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5630         uint32_t vec = IXGBE_MISC_VEC_ID;
5631
5632         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5633         if (rte_intr_allow_others(intr_handle))
5634                 vec = IXGBE_RX_VEC_START;
5635         mask &= ~(1 << vec);
5636         RTE_SET_USED(queue_id);
5637         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5638
5639         return 0;
5640 }
5641
5642 static int
5643 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5644 {
5645         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5646         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5647         uint32_t mask;
5648         struct ixgbe_hw *hw =
5649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5650         struct ixgbe_interrupt *intr =
5651                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5652
5653         if (queue_id < 16) {
5654                 ixgbe_disable_intr(hw);
5655                 intr->mask |= (1 << queue_id);
5656                 ixgbe_enable_intr(dev);
5657         } else if (queue_id < 32) {
5658                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5659                 mask &= (1 << queue_id);
5660                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5661         } else if (queue_id < 64) {
5662                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5663                 mask &= (1 << (queue_id - 32));
5664                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5665         }
5666         rte_intr_enable(intr_handle);
5667
5668         return 0;
5669 }
5670
5671 static int
5672 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5673 {
5674         uint32_t mask;
5675         struct ixgbe_hw *hw =
5676                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5677         struct ixgbe_interrupt *intr =
5678                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5679
5680         if (queue_id < 16) {
5681                 ixgbe_disable_intr(hw);
5682                 intr->mask &= ~(1 << queue_id);
5683                 ixgbe_enable_intr(dev);
5684         } else if (queue_id < 32) {
5685                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5686                 mask &= ~(1 << queue_id);
5687                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5688         } else if (queue_id < 64) {
5689                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5690                 mask &= ~(1 << (queue_id - 32));
5691                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5692         }
5693
5694         return 0;
5695 }
5696
5697 static void
5698 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5699                      uint8_t queue, uint8_t msix_vector)
5700 {
5701         uint32_t tmp, idx;
5702
5703         if (direction == -1) {
5704                 /* other causes */
5705                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5706                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5707                 tmp &= ~0xFF;
5708                 tmp |= msix_vector;
5709                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5710         } else {
5711                 /* rx or tx cause */
5712                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5713                 idx = ((16 * (queue & 1)) + (8 * direction));
5714                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5715                 tmp &= ~(0xFF << idx);
5716                 tmp |= (msix_vector << idx);
5717                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5718         }
5719 }
5720
5721 /**
5722  * set the IVAR registers, mapping interrupt causes to vectors
5723  * @param hw
5724  *  pointer to ixgbe_hw struct
5725  * @direction
5726  *  0 for Rx, 1 for Tx, -1 for other causes
5727  * @queue
5728  *  queue to map the corresponding interrupt to
5729  * @msix_vector
5730  *  the vector to map to the corresponding queue
5731  */
5732 static void
5733 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5734                    uint8_t queue, uint8_t msix_vector)
5735 {
5736         uint32_t tmp, idx;
5737
5738         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5739         if (hw->mac.type == ixgbe_mac_82598EB) {
5740                 if (direction == -1)
5741                         direction = 0;
5742                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5743                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5744                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5745                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5746                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5747         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5748                         (hw->mac.type == ixgbe_mac_X540) ||
5749                         (hw->mac.type == ixgbe_mac_X550)) {
5750                 if (direction == -1) {
5751                         /* other causes */
5752                         idx = ((queue & 1) * 8);
5753                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5754                         tmp &= ~(0xFF << idx);
5755                         tmp |= (msix_vector << idx);
5756                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5757                 } else {
5758                         /* rx or tx causes */
5759                         idx = ((16 * (queue & 1)) + (8 * direction));
5760                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5761                         tmp &= ~(0xFF << idx);
5762                         tmp |= (msix_vector << idx);
5763                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5764                 }
5765         }
5766 }
5767
5768 static void
5769 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5770 {
5771         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5772         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5773         struct ixgbe_hw *hw =
5774                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5775         uint32_t q_idx;
5776         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5777         uint32_t base = IXGBE_MISC_VEC_ID;
5778
5779         /* Configure VF other cause ivar */
5780         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5781
5782         /* won't configure msix register if no mapping is done
5783          * between intr vector and event fd.
5784          */
5785         if (!rte_intr_dp_is_en(intr_handle))
5786                 return;
5787
5788         if (rte_intr_allow_others(intr_handle)) {
5789                 base = IXGBE_RX_VEC_START;
5790                 vector_idx = IXGBE_RX_VEC_START;
5791         }
5792
5793         /* Configure all RX queues of VF */
5794         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5795                 /* Force all queue use vector 0,
5796                  * as IXGBE_VF_MAXMSIVECOTR = 1
5797                  */
5798                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5799                 intr_handle->intr_vec[q_idx] = vector_idx;
5800                 if (vector_idx < base + intr_handle->nb_efd - 1)
5801                         vector_idx++;
5802         }
5803 }
5804
5805 /**
5806  * Sets up the hardware to properly generate MSI-X interrupts
5807  * @hw
5808  *  board private structure
5809  */
5810 static void
5811 ixgbe_configure_msix(struct rte_eth_dev *dev)
5812 {
5813         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5814         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5815         struct ixgbe_hw *hw =
5816                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5817         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5818         uint32_t vec = IXGBE_MISC_VEC_ID;
5819         uint32_t mask;
5820         uint32_t gpie;
5821
5822         /* won't configure msix register if no mapping is done
5823          * between intr vector and event fd
5824          */
5825         if (!rte_intr_dp_is_en(intr_handle))
5826                 return;
5827
5828         if (rte_intr_allow_others(intr_handle))
5829                 vec = base = IXGBE_RX_VEC_START;
5830
5831         /* setup GPIE for MSI-x mode */
5832         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5833         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5834                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5835         /* auto clearing and auto setting corresponding bits in EIMS
5836          * when MSI-X interrupt is triggered
5837          */
5838         if (hw->mac.type == ixgbe_mac_82598EB) {
5839                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5840         } else {
5841                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5842                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5843         }
5844         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5845
5846         /* Populate the IVAR table and set the ITR values to the
5847          * corresponding register.
5848          */
5849         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5850              queue_id++) {
5851                 /* by default, 1:1 mapping */
5852                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5853                 intr_handle->intr_vec[queue_id] = vec;
5854                 if (vec < base + intr_handle->nb_efd - 1)
5855                         vec++;
5856         }
5857
5858         switch (hw->mac.type) {
5859         case ixgbe_mac_82598EB:
5860                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5861                                    IXGBE_MISC_VEC_ID);
5862                 break;
5863         case ixgbe_mac_82599EB:
5864         case ixgbe_mac_X540:
5865         case ixgbe_mac_X550:
5866                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5867                 break;
5868         default:
5869                 break;
5870         }
5871         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5872                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5873
5874         /* set up to autoclear timer, and the vectors */
5875         mask = IXGBE_EIMS_ENABLE_MASK;
5876         mask &= ~(IXGBE_EIMS_OTHER |
5877                   IXGBE_EIMS_MAILBOX |
5878                   IXGBE_EIMS_LSC);
5879
5880         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5881 }
5882
5883 int
5884 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5885                            uint16_t queue_idx, uint16_t tx_rate)
5886 {
5887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5888         struct rte_eth_rxmode *rxmode;
5889         uint32_t rf_dec, rf_int;
5890         uint32_t bcnrc_val;
5891         uint16_t link_speed = dev->data->dev_link.link_speed;
5892
5893         if (queue_idx >= hw->mac.max_tx_queues)
5894                 return -EINVAL;
5895
5896         if (tx_rate != 0) {
5897                 /* Calculate the rate factor values to set */
5898                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5899                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5900                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5901
5902                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5903                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5904                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5905                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5906         } else {
5907                 bcnrc_val = 0;
5908         }
5909
5910         rxmode = &dev->data->dev_conf.rxmode;
5911         /*
5912          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5913          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5914          * set as 0x4.
5915          */
5916         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5917             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5918                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5919                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5920         else
5921                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5922                         IXGBE_MMW_SIZE_DEFAULT);
5923
5924         /* Set RTTBCNRC of queue X */
5925         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5926         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5927         IXGBE_WRITE_FLUSH(hw);
5928
5929         return 0;
5930 }
5931
5932 static int
5933 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5934                      __attribute__((unused)) uint32_t index,
5935                      __attribute__((unused)) uint32_t pool)
5936 {
5937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5938         int diag;
5939
5940         /*
5941          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5942          * operation. Trap this case to avoid exhausting the [very limited]
5943          * set of PF resources used to store VF MAC addresses.
5944          */
5945         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5946                 return -1;
5947         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5948         if (diag != 0)
5949                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5950                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5951                             mac_addr->addr_bytes[0],
5952                             mac_addr->addr_bytes[1],
5953                             mac_addr->addr_bytes[2],
5954                             mac_addr->addr_bytes[3],
5955                             mac_addr->addr_bytes[4],
5956                             mac_addr->addr_bytes[5],
5957                             diag);
5958         return diag;
5959 }
5960
5961 static void
5962 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5963 {
5964         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5965         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5966         struct ether_addr *mac_addr;
5967         uint32_t i;
5968         int diag;
5969
5970         /*
5971          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5972          * not support the deletion of a given MAC address.
5973          * Instead, it imposes to delete all MAC addresses, then to add again
5974          * all MAC addresses with the exception of the one to be deleted.
5975          */
5976         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5977
5978         /*
5979          * Add again all MAC addresses, with the exception of the deleted one
5980          * and of the permanent MAC address.
5981          */
5982         for (i = 0, mac_addr = dev->data->mac_addrs;
5983              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5984                 /* Skip the deleted MAC address */
5985                 if (i == index)
5986                         continue;
5987                 /* Skip NULL MAC addresses */
5988                 if (is_zero_ether_addr(mac_addr))
5989                         continue;
5990                 /* Skip the permanent MAC address */
5991                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5992                         continue;
5993                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5994                 if (diag != 0)
5995                         PMD_DRV_LOG(ERR,
5996                                     "Adding again MAC address "
5997                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5998                                     "diag=%d",
5999                                     mac_addr->addr_bytes[0],
6000                                     mac_addr->addr_bytes[1],
6001                                     mac_addr->addr_bytes[2],
6002                                     mac_addr->addr_bytes[3],
6003                                     mac_addr->addr_bytes[4],
6004                                     mac_addr->addr_bytes[5],
6005                                     diag);
6006         }
6007 }
6008
6009 static int
6010 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6011 {
6012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6013
6014         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6015
6016         return 0;
6017 }
6018
6019 int
6020 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6021                         struct rte_eth_syn_filter *filter,
6022                         bool add)
6023 {
6024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6025         struct ixgbe_filter_info *filter_info =
6026                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6027         uint32_t syn_info;
6028         uint32_t synqf;
6029
6030         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6031                 return -EINVAL;
6032
6033         syn_info = filter_info->syn_info;
6034
6035         if (add) {
6036                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6037                         return -EINVAL;
6038                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6039                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6040
6041                 if (filter->hig_pri)
6042                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6043                 else
6044                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6045         } else {
6046                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6047                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6048                         return -ENOENT;
6049                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6050         }
6051
6052         filter_info->syn_info = synqf;
6053         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6054         IXGBE_WRITE_FLUSH(hw);
6055         return 0;
6056 }
6057
6058 static int
6059 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6060                         struct rte_eth_syn_filter *filter)
6061 {
6062         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6063         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6064
6065         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6066                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6067                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6068                 return 0;
6069         }
6070         return -ENOENT;
6071 }
6072
6073 static int
6074 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6075                         enum rte_filter_op filter_op,
6076                         void *arg)
6077 {
6078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6079         int ret;
6080
6081         MAC_TYPE_FILTER_SUP(hw->mac.type);
6082
6083         if (filter_op == RTE_ETH_FILTER_NOP)
6084                 return 0;
6085
6086         if (arg == NULL) {
6087                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6088                             filter_op);
6089                 return -EINVAL;
6090         }
6091
6092         switch (filter_op) {
6093         case RTE_ETH_FILTER_ADD:
6094                 ret = ixgbe_syn_filter_set(dev,
6095                                 (struct rte_eth_syn_filter *)arg,
6096                                 TRUE);
6097                 break;
6098         case RTE_ETH_FILTER_DELETE:
6099                 ret = ixgbe_syn_filter_set(dev,
6100                                 (struct rte_eth_syn_filter *)arg,
6101                                 FALSE);
6102                 break;
6103         case RTE_ETH_FILTER_GET:
6104                 ret = ixgbe_syn_filter_get(dev,
6105                                 (struct rte_eth_syn_filter *)arg);
6106                 break;
6107         default:
6108                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6109                 ret = -EINVAL;
6110                 break;
6111         }
6112
6113         return ret;
6114 }
6115
6116
6117 static inline enum ixgbe_5tuple_protocol
6118 convert_protocol_type(uint8_t protocol_value)
6119 {
6120         if (protocol_value == IPPROTO_TCP)
6121                 return IXGBE_FILTER_PROTOCOL_TCP;
6122         else if (protocol_value == IPPROTO_UDP)
6123                 return IXGBE_FILTER_PROTOCOL_UDP;
6124         else if (protocol_value == IPPROTO_SCTP)
6125                 return IXGBE_FILTER_PROTOCOL_SCTP;
6126         else
6127                 return IXGBE_FILTER_PROTOCOL_NONE;
6128 }
6129
6130 /* inject a 5-tuple filter to HW */
6131 static inline void
6132 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6133                            struct ixgbe_5tuple_filter *filter)
6134 {
6135         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6136         int i;
6137         uint32_t ftqf, sdpqf;
6138         uint32_t l34timir = 0;
6139         uint8_t mask = 0xff;
6140
6141         i = filter->index;
6142
6143         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6144                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6145         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6146
6147         ftqf = (uint32_t)(filter->filter_info.proto &
6148                 IXGBE_FTQF_PROTOCOL_MASK);
6149         ftqf |= (uint32_t)((filter->filter_info.priority &
6150                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6151         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6152                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6153         if (filter->filter_info.dst_ip_mask == 0)
6154                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6155         if (filter->filter_info.src_port_mask == 0)
6156                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6157         if (filter->filter_info.dst_port_mask == 0)
6158                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6159         if (filter->filter_info.proto_mask == 0)
6160                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6161         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6162         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6163         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6164
6165         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6166         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6167         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6168         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6169
6170         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6171         l34timir |= (uint32_t)(filter->queue <<
6172                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6173         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6174 }
6175
6176 /*
6177  * add a 5tuple filter
6178  *
6179  * @param
6180  * dev: Pointer to struct rte_eth_dev.
6181  * index: the index the filter allocates.
6182  * filter: ponter to the filter that will be added.
6183  * rx_queue: the queue id the filter assigned to.
6184  *
6185  * @return
6186  *    - On success, zero.
6187  *    - On failure, a negative value.
6188  */
6189 static int
6190 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6191                         struct ixgbe_5tuple_filter *filter)
6192 {
6193         struct ixgbe_filter_info *filter_info =
6194                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6195         int i, idx, shift;
6196
6197         /*
6198          * look for an unused 5tuple filter index,
6199          * and insert the filter to list.
6200          */
6201         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6202                 idx = i / (sizeof(uint32_t) * NBBY);
6203                 shift = i % (sizeof(uint32_t) * NBBY);
6204                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6205                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6206                         filter->index = i;
6207                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6208                                           filter,
6209                                           entries);
6210                         break;
6211                 }
6212         }
6213         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6214                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6215                 return -ENOSYS;
6216         }
6217
6218         ixgbe_inject_5tuple_filter(dev, filter);
6219
6220         return 0;
6221 }
6222
6223 /*
6224  * remove a 5tuple filter
6225  *
6226  * @param
6227  * dev: Pointer to struct rte_eth_dev.
6228  * filter: the pointer of the filter will be removed.
6229  */
6230 static void
6231 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6232                         struct ixgbe_5tuple_filter *filter)
6233 {
6234         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6235         struct ixgbe_filter_info *filter_info =
6236                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6237         uint16_t index = filter->index;
6238
6239         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6240                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6241         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6242         rte_free(filter);
6243
6244         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6245         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6246         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6247         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6248         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6249 }
6250
6251 static int
6252 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6253 {
6254         struct ixgbe_hw *hw;
6255         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6256         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6257
6258         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6259
6260         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6261                 return -EINVAL;
6262
6263         /* refuse mtu that requires the support of scattered packets when this
6264          * feature has not been enabled before.
6265          */
6266         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6267             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6268              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6269                 return -EINVAL;
6270
6271         /*
6272          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6273          * request of the version 2.0 of the mailbox API.
6274          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6275          * of the mailbox API.
6276          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6277          * prior to 3.11.33 which contains the following change:
6278          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6279          */
6280         ixgbevf_rlpml_set_vf(hw, max_frame);
6281
6282         /* update max frame size */
6283         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6284         return 0;
6285 }
6286
6287 static inline struct ixgbe_5tuple_filter *
6288 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6289                         struct ixgbe_5tuple_filter_info *key)
6290 {
6291         struct ixgbe_5tuple_filter *it;
6292
6293         TAILQ_FOREACH(it, filter_list, entries) {
6294                 if (memcmp(key, &it->filter_info,
6295                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6296                         return it;
6297                 }
6298         }
6299         return NULL;
6300 }
6301
6302 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6303 static inline int
6304 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6305                         struct ixgbe_5tuple_filter_info *filter_info)
6306 {
6307         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6308                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6309                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6310                 return -EINVAL;
6311
6312         switch (filter->dst_ip_mask) {
6313         case UINT32_MAX:
6314                 filter_info->dst_ip_mask = 0;
6315                 filter_info->dst_ip = filter->dst_ip;
6316                 break;
6317         case 0:
6318                 filter_info->dst_ip_mask = 1;
6319                 break;
6320         default:
6321                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6322                 return -EINVAL;
6323         }
6324
6325         switch (filter->src_ip_mask) {
6326         case UINT32_MAX:
6327                 filter_info->src_ip_mask = 0;
6328                 filter_info->src_ip = filter->src_ip;
6329                 break;
6330         case 0:
6331                 filter_info->src_ip_mask = 1;
6332                 break;
6333         default:
6334                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6335                 return -EINVAL;
6336         }
6337
6338         switch (filter->dst_port_mask) {
6339         case UINT16_MAX:
6340                 filter_info->dst_port_mask = 0;
6341                 filter_info->dst_port = filter->dst_port;
6342                 break;
6343         case 0:
6344                 filter_info->dst_port_mask = 1;
6345                 break;
6346         default:
6347                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6348                 return -EINVAL;
6349         }
6350
6351         switch (filter->src_port_mask) {
6352         case UINT16_MAX:
6353                 filter_info->src_port_mask = 0;
6354                 filter_info->src_port = filter->src_port;
6355                 break;
6356         case 0:
6357                 filter_info->src_port_mask = 1;
6358                 break;
6359         default:
6360                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6361                 return -EINVAL;
6362         }
6363
6364         switch (filter->proto_mask) {
6365         case UINT8_MAX:
6366                 filter_info->proto_mask = 0;
6367                 filter_info->proto =
6368                         convert_protocol_type(filter->proto);
6369                 break;
6370         case 0:
6371                 filter_info->proto_mask = 1;
6372                 break;
6373         default:
6374                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6375                 return -EINVAL;
6376         }
6377
6378         filter_info->priority = (uint8_t)filter->priority;
6379         return 0;
6380 }
6381
6382 /*
6383  * add or delete a ntuple filter
6384  *
6385  * @param
6386  * dev: Pointer to struct rte_eth_dev.
6387  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6388  * add: if true, add filter, if false, remove filter
6389  *
6390  * @return
6391  *    - On success, zero.
6392  *    - On failure, a negative value.
6393  */
6394 int
6395 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6396                         struct rte_eth_ntuple_filter *ntuple_filter,
6397                         bool add)
6398 {
6399         struct ixgbe_filter_info *filter_info =
6400                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6401         struct ixgbe_5tuple_filter_info filter_5tuple;
6402         struct ixgbe_5tuple_filter *filter;
6403         int ret;
6404
6405         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6406                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6407                 return -EINVAL;
6408         }
6409
6410         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6411         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6412         if (ret < 0)
6413                 return ret;
6414
6415         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6416                                          &filter_5tuple);
6417         if (filter != NULL && add) {
6418                 PMD_DRV_LOG(ERR, "filter exists.");
6419                 return -EEXIST;
6420         }
6421         if (filter == NULL && !add) {
6422                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6423                 return -ENOENT;
6424         }
6425
6426         if (add) {
6427                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6428                                 sizeof(struct ixgbe_5tuple_filter), 0);
6429                 if (filter == NULL)
6430                         return -ENOMEM;
6431                 rte_memcpy(&filter->filter_info,
6432                                  &filter_5tuple,
6433                                  sizeof(struct ixgbe_5tuple_filter_info));
6434                 filter->queue = ntuple_filter->queue;
6435                 ret = ixgbe_add_5tuple_filter(dev, filter);
6436                 if (ret < 0) {
6437                         rte_free(filter);
6438                         return ret;
6439                 }
6440         } else
6441                 ixgbe_remove_5tuple_filter(dev, filter);
6442
6443         return 0;
6444 }
6445
6446 /*
6447  * get a ntuple filter
6448  *
6449  * @param
6450  * dev: Pointer to struct rte_eth_dev.
6451  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6452  *
6453  * @return
6454  *    - On success, zero.
6455  *    - On failure, a negative value.
6456  */
6457 static int
6458 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6459                         struct rte_eth_ntuple_filter *ntuple_filter)
6460 {
6461         struct ixgbe_filter_info *filter_info =
6462                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6463         struct ixgbe_5tuple_filter_info filter_5tuple;
6464         struct ixgbe_5tuple_filter *filter;
6465         int ret;
6466
6467         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6468                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6469                 return -EINVAL;
6470         }
6471
6472         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6473         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6474         if (ret < 0)
6475                 return ret;
6476
6477         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6478                                          &filter_5tuple);
6479         if (filter == NULL) {
6480                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6481                 return -ENOENT;
6482         }
6483         ntuple_filter->queue = filter->queue;
6484         return 0;
6485 }
6486
6487 /*
6488  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6489  * @dev: pointer to rte_eth_dev structure
6490  * @filter_op:operation will be taken.
6491  * @arg: a pointer to specific structure corresponding to the filter_op
6492  *
6493  * @return
6494  *    - On success, zero.
6495  *    - On failure, a negative value.
6496  */
6497 static int
6498 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6499                                 enum rte_filter_op filter_op,
6500                                 void *arg)
6501 {
6502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6503         int ret;
6504
6505         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6506
6507         if (filter_op == RTE_ETH_FILTER_NOP)
6508                 return 0;
6509
6510         if (arg == NULL) {
6511                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6512                             filter_op);
6513                 return -EINVAL;
6514         }
6515
6516         switch (filter_op) {
6517         case RTE_ETH_FILTER_ADD:
6518                 ret = ixgbe_add_del_ntuple_filter(dev,
6519                         (struct rte_eth_ntuple_filter *)arg,
6520                         TRUE);
6521                 break;
6522         case RTE_ETH_FILTER_DELETE:
6523                 ret = ixgbe_add_del_ntuple_filter(dev,
6524                         (struct rte_eth_ntuple_filter *)arg,
6525                         FALSE);
6526                 break;
6527         case RTE_ETH_FILTER_GET:
6528                 ret = ixgbe_get_ntuple_filter(dev,
6529                         (struct rte_eth_ntuple_filter *)arg);
6530                 break;
6531         default:
6532                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6533                 ret = -EINVAL;
6534                 break;
6535         }
6536         return ret;
6537 }
6538
6539 int
6540 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6541                         struct rte_eth_ethertype_filter *filter,
6542                         bool add)
6543 {
6544         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6545         struct ixgbe_filter_info *filter_info =
6546                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6547         uint32_t etqf = 0;
6548         uint32_t etqs = 0;
6549         int ret;
6550         struct ixgbe_ethertype_filter ethertype_filter;
6551
6552         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6553                 return -EINVAL;
6554
6555         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6556                 filter->ether_type == ETHER_TYPE_IPv6) {
6557                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6558                         " ethertype filter.", filter->ether_type);
6559                 return -EINVAL;
6560         }
6561
6562         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6563                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6564                 return -EINVAL;
6565         }
6566         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6567                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6568                 return -EINVAL;
6569         }
6570
6571         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6572         if (ret >= 0 && add) {
6573                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6574                             filter->ether_type);
6575                 return -EEXIST;
6576         }
6577         if (ret < 0 && !add) {
6578                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6579                             filter->ether_type);
6580                 return -ENOENT;
6581         }
6582
6583         if (add) {
6584                 etqf = IXGBE_ETQF_FILTER_EN;
6585                 etqf |= (uint32_t)filter->ether_type;
6586                 etqs |= (uint32_t)((filter->queue <<
6587                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6588                                     IXGBE_ETQS_RX_QUEUE);
6589                 etqs |= IXGBE_ETQS_QUEUE_EN;
6590
6591                 ethertype_filter.ethertype = filter->ether_type;
6592                 ethertype_filter.etqf = etqf;
6593                 ethertype_filter.etqs = etqs;
6594                 ethertype_filter.conf = FALSE;
6595                 ret = ixgbe_ethertype_filter_insert(filter_info,
6596                                                     &ethertype_filter);
6597                 if (ret < 0) {
6598                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6599                         return -ENOSPC;
6600                 }
6601         } else {
6602                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6603                 if (ret < 0)
6604                         return -ENOSYS;
6605         }
6606         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6607         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6608         IXGBE_WRITE_FLUSH(hw);
6609
6610         return 0;
6611 }
6612
6613 static int
6614 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6615                         struct rte_eth_ethertype_filter *filter)
6616 {
6617         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6618         struct ixgbe_filter_info *filter_info =
6619                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6620         uint32_t etqf, etqs;
6621         int ret;
6622
6623         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6624         if (ret < 0) {
6625                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6626                             filter->ether_type);
6627                 return -ENOENT;
6628         }
6629
6630         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6631         if (etqf & IXGBE_ETQF_FILTER_EN) {
6632                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6633                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6634                 filter->flags = 0;
6635                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6636                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6637                 return 0;
6638         }
6639         return -ENOENT;
6640 }
6641
6642 /*
6643  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6644  * @dev: pointer to rte_eth_dev structure
6645  * @filter_op:operation will be taken.
6646  * @arg: a pointer to specific structure corresponding to the filter_op
6647  */
6648 static int
6649 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6650                                 enum rte_filter_op filter_op,
6651                                 void *arg)
6652 {
6653         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6654         int ret;
6655
6656         MAC_TYPE_FILTER_SUP(hw->mac.type);
6657
6658         if (filter_op == RTE_ETH_FILTER_NOP)
6659                 return 0;
6660
6661         if (arg == NULL) {
6662                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6663                             filter_op);
6664                 return -EINVAL;
6665         }
6666
6667         switch (filter_op) {
6668         case RTE_ETH_FILTER_ADD:
6669                 ret = ixgbe_add_del_ethertype_filter(dev,
6670                         (struct rte_eth_ethertype_filter *)arg,
6671                         TRUE);
6672                 break;
6673         case RTE_ETH_FILTER_DELETE:
6674                 ret = ixgbe_add_del_ethertype_filter(dev,
6675                         (struct rte_eth_ethertype_filter *)arg,
6676                         FALSE);
6677                 break;
6678         case RTE_ETH_FILTER_GET:
6679                 ret = ixgbe_get_ethertype_filter(dev,
6680                         (struct rte_eth_ethertype_filter *)arg);
6681                 break;
6682         default:
6683                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6684                 ret = -EINVAL;
6685                 break;
6686         }
6687         return ret;
6688 }
6689
6690 static int
6691 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6692                      enum rte_filter_type filter_type,
6693                      enum rte_filter_op filter_op,
6694                      void *arg)
6695 {
6696         int ret = 0;
6697
6698         switch (filter_type) {
6699         case RTE_ETH_FILTER_NTUPLE:
6700                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6701                 break;
6702         case RTE_ETH_FILTER_ETHERTYPE:
6703                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6704                 break;
6705         case RTE_ETH_FILTER_SYN:
6706                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6707                 break;
6708         case RTE_ETH_FILTER_FDIR:
6709                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6710                 break;
6711         case RTE_ETH_FILTER_L2_TUNNEL:
6712                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6713                 break;
6714         case RTE_ETH_FILTER_GENERIC:
6715                 if (filter_op != RTE_ETH_FILTER_GET)
6716                         return -EINVAL;
6717                 *(const void **)arg = &ixgbe_flow_ops;
6718                 break;
6719         default:
6720                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6721                                                         filter_type);
6722                 ret = -EINVAL;
6723                 break;
6724         }
6725
6726         return ret;
6727 }
6728
6729 static u8 *
6730 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6731                         u8 **mc_addr_ptr, u32 *vmdq)
6732 {
6733         u8 *mc_addr;
6734
6735         *vmdq = 0;
6736         mc_addr = *mc_addr_ptr;
6737         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6738         return mc_addr;
6739 }
6740
6741 static int
6742 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6743                           struct ether_addr *mc_addr_set,
6744                           uint32_t nb_mc_addr)
6745 {
6746         struct ixgbe_hw *hw;
6747         u8 *mc_addr_list;
6748
6749         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6750         mc_addr_list = (u8 *)mc_addr_set;
6751         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6752                                          ixgbe_dev_addr_list_itr, TRUE);
6753 }
6754
6755 static uint64_t
6756 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6757 {
6758         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6759         uint64_t systime_cycles;
6760
6761         switch (hw->mac.type) {
6762         case ixgbe_mac_X550:
6763         case ixgbe_mac_X550EM_x:
6764         case ixgbe_mac_X550EM_a:
6765                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6766                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6767                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6768                                 * NSEC_PER_SEC;
6769                 break;
6770         default:
6771                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6772                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6773                                 << 32;
6774         }
6775
6776         return systime_cycles;
6777 }
6778
6779 static uint64_t
6780 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6781 {
6782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783         uint64_t rx_tstamp_cycles;
6784
6785         switch (hw->mac.type) {
6786         case ixgbe_mac_X550:
6787         case ixgbe_mac_X550EM_x:
6788         case ixgbe_mac_X550EM_a:
6789                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6790                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6791                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6792                                 * NSEC_PER_SEC;
6793                 break;
6794         default:
6795                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6796                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6797                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6798                                 << 32;
6799         }
6800
6801         return rx_tstamp_cycles;
6802 }
6803
6804 static uint64_t
6805 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6806 {
6807         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6808         uint64_t tx_tstamp_cycles;
6809
6810         switch (hw->mac.type) {
6811         case ixgbe_mac_X550:
6812         case ixgbe_mac_X550EM_x:
6813         case ixgbe_mac_X550EM_a:
6814                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6815                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6816                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6817                                 * NSEC_PER_SEC;
6818                 break;
6819         default:
6820                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6821                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6822                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6823                                 << 32;
6824         }
6825
6826         return tx_tstamp_cycles;
6827 }
6828
6829 static void
6830 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6831 {
6832         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6833         struct ixgbe_adapter *adapter =
6834                 (struct ixgbe_adapter *)dev->data->dev_private;
6835         struct rte_eth_link link;
6836         uint32_t incval = 0;
6837         uint32_t shift = 0;
6838
6839         /* Get current link speed. */
6840         ixgbe_dev_link_update(dev, 1);
6841         rte_eth_linkstatus_get(dev, &link);
6842
6843         switch (link.link_speed) {
6844         case ETH_SPEED_NUM_100M:
6845                 incval = IXGBE_INCVAL_100;
6846                 shift = IXGBE_INCVAL_SHIFT_100;
6847                 break;
6848         case ETH_SPEED_NUM_1G:
6849                 incval = IXGBE_INCVAL_1GB;
6850                 shift = IXGBE_INCVAL_SHIFT_1GB;
6851                 break;
6852         case ETH_SPEED_NUM_10G:
6853         default:
6854                 incval = IXGBE_INCVAL_10GB;
6855                 shift = IXGBE_INCVAL_SHIFT_10GB;
6856                 break;
6857         }
6858
6859         switch (hw->mac.type) {
6860         case ixgbe_mac_X550:
6861         case ixgbe_mac_X550EM_x:
6862         case ixgbe_mac_X550EM_a:
6863                 /* Independent of link speed. */
6864                 incval = 1;
6865                 /* Cycles read will be interpreted as ns. */
6866                 shift = 0;
6867                 /* Fall-through */
6868         case ixgbe_mac_X540:
6869                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6870                 break;
6871         case ixgbe_mac_82599EB:
6872                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6873                 shift -= IXGBE_INCVAL_SHIFT_82599;
6874                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6875                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6876                 break;
6877         default:
6878                 /* Not supported. */
6879                 return;
6880         }
6881
6882         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6883         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6884         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6885
6886         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6887         adapter->systime_tc.cc_shift = shift;
6888         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6889
6890         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6891         adapter->rx_tstamp_tc.cc_shift = shift;
6892         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6893
6894         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6895         adapter->tx_tstamp_tc.cc_shift = shift;
6896         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6897 }
6898
6899 static int
6900 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6901 {
6902         struct ixgbe_adapter *adapter =
6903                         (struct ixgbe_adapter *)dev->data->dev_private;
6904
6905         adapter->systime_tc.nsec += delta;
6906         adapter->rx_tstamp_tc.nsec += delta;
6907         adapter->tx_tstamp_tc.nsec += delta;
6908
6909         return 0;
6910 }
6911
6912 static int
6913 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6914 {
6915         uint64_t ns;
6916         struct ixgbe_adapter *adapter =
6917                         (struct ixgbe_adapter *)dev->data->dev_private;
6918
6919         ns = rte_timespec_to_ns(ts);
6920         /* Set the timecounters to a new value. */
6921         adapter->systime_tc.nsec = ns;
6922         adapter->rx_tstamp_tc.nsec = ns;
6923         adapter->tx_tstamp_tc.nsec = ns;
6924
6925         return 0;
6926 }
6927
6928 static int
6929 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6930 {
6931         uint64_t ns, systime_cycles;
6932         struct ixgbe_adapter *adapter =
6933                         (struct ixgbe_adapter *)dev->data->dev_private;
6934
6935         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6936         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6937         *ts = rte_ns_to_timespec(ns);
6938
6939         return 0;
6940 }
6941
6942 static int
6943 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6944 {
6945         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6946         uint32_t tsync_ctl;
6947         uint32_t tsauxc;
6948
6949         /* Stop the timesync system time. */
6950         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6951         /* Reset the timesync system time value. */
6952         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6953         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6954
6955         /* Enable system time for platforms where it isn't on by default. */
6956         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6957         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6958         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6959
6960         ixgbe_start_timecounters(dev);
6961
6962         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6963         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6964                         (ETHER_TYPE_1588 |
6965                          IXGBE_ETQF_FILTER_EN |
6966                          IXGBE_ETQF_1588));
6967
6968         /* Enable timestamping of received PTP packets. */
6969         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6970         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6971         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6972
6973         /* Enable timestamping of transmitted PTP packets. */
6974         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6975         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6976         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6977
6978         IXGBE_WRITE_FLUSH(hw);
6979
6980         return 0;
6981 }
6982
6983 static int
6984 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6985 {
6986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6987         uint32_t tsync_ctl;
6988
6989         /* Disable timestamping of transmitted PTP packets. */
6990         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6991         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6992         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6993
6994         /* Disable timestamping of received PTP packets. */
6995         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6996         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6997         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6998
6999         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7000         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7001
7002         /* Stop incrementating the System Time registers. */
7003         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7004
7005         return 0;
7006 }
7007
7008 static int
7009 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7010                                  struct timespec *timestamp,
7011                                  uint32_t flags __rte_unused)
7012 {
7013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7014         struct ixgbe_adapter *adapter =
7015                 (struct ixgbe_adapter *)dev->data->dev_private;
7016         uint32_t tsync_rxctl;
7017         uint64_t rx_tstamp_cycles;
7018         uint64_t ns;
7019
7020         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7021         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7022                 return -EINVAL;
7023
7024         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7025         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7026         *timestamp = rte_ns_to_timespec(ns);
7027
7028         return  0;
7029 }
7030
7031 static int
7032 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7033                                  struct timespec *timestamp)
7034 {
7035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7036         struct ixgbe_adapter *adapter =
7037                 (struct ixgbe_adapter *)dev->data->dev_private;
7038         uint32_t tsync_txctl;
7039         uint64_t tx_tstamp_cycles;
7040         uint64_t ns;
7041
7042         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7043         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7044                 return -EINVAL;
7045
7046         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7047         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7048         *timestamp = rte_ns_to_timespec(ns);
7049
7050         return 0;
7051 }
7052
7053 static int
7054 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7055 {
7056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7057         int count = 0;
7058         int g_ind = 0;
7059         const struct reg_info *reg_group;
7060         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7061                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7062
7063         while ((reg_group = reg_set[g_ind++]))
7064                 count += ixgbe_regs_group_count(reg_group);
7065
7066         return count;
7067 }
7068
7069 static int
7070 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7071 {
7072         int count = 0;
7073         int g_ind = 0;
7074         const struct reg_info *reg_group;
7075
7076         while ((reg_group = ixgbevf_regs[g_ind++]))
7077                 count += ixgbe_regs_group_count(reg_group);
7078
7079         return count;
7080 }
7081
7082 static int
7083 ixgbe_get_regs(struct rte_eth_dev *dev,
7084               struct rte_dev_reg_info *regs)
7085 {
7086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7087         uint32_t *data = regs->data;
7088         int g_ind = 0;
7089         int count = 0;
7090         const struct reg_info *reg_group;
7091         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7092                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7093
7094         if (data == NULL) {
7095                 regs->length = ixgbe_get_reg_length(dev);
7096                 regs->width = sizeof(uint32_t);
7097                 return 0;
7098         }
7099
7100         /* Support only full register dump */
7101         if ((regs->length == 0) ||
7102             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7103                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7104                         hw->device_id;
7105                 while ((reg_group = reg_set[g_ind++]))
7106                         count += ixgbe_read_regs_group(dev, &data[count],
7107                                 reg_group);
7108                 return 0;
7109         }
7110
7111         return -ENOTSUP;
7112 }
7113
7114 static int
7115 ixgbevf_get_regs(struct rte_eth_dev *dev,
7116                 struct rte_dev_reg_info *regs)
7117 {
7118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7119         uint32_t *data = regs->data;
7120         int g_ind = 0;
7121         int count = 0;
7122         const struct reg_info *reg_group;
7123
7124         if (data == NULL) {
7125                 regs->length = ixgbevf_get_reg_length(dev);
7126                 regs->width = sizeof(uint32_t);
7127                 return 0;
7128         }
7129
7130         /* Support only full register dump */
7131         if ((regs->length == 0) ||
7132             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7133                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7134                         hw->device_id;
7135                 while ((reg_group = ixgbevf_regs[g_ind++]))
7136                         count += ixgbe_read_regs_group(dev, &data[count],
7137                                                       reg_group);
7138                 return 0;
7139         }
7140
7141         return -ENOTSUP;
7142 }
7143
7144 static int
7145 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7146 {
7147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7148
7149         /* Return unit is byte count */
7150         return hw->eeprom.word_size * 2;
7151 }
7152
7153 static int
7154 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7155                 struct rte_dev_eeprom_info *in_eeprom)
7156 {
7157         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7158         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7159         uint16_t *data = in_eeprom->data;
7160         int first, length;
7161
7162         first = in_eeprom->offset >> 1;
7163         length = in_eeprom->length >> 1;
7164         if ((first > hw->eeprom.word_size) ||
7165             ((first + length) > hw->eeprom.word_size))
7166                 return -EINVAL;
7167
7168         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7169
7170         return eeprom->ops.read_buffer(hw, first, length, data);
7171 }
7172
7173 static int
7174 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7175                 struct rte_dev_eeprom_info *in_eeprom)
7176 {
7177         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7178         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7179         uint16_t *data = in_eeprom->data;
7180         int first, length;
7181
7182         first = in_eeprom->offset >> 1;
7183         length = in_eeprom->length >> 1;
7184         if ((first > hw->eeprom.word_size) ||
7185             ((first + length) > hw->eeprom.word_size))
7186                 return -EINVAL;
7187
7188         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7189
7190         return eeprom->ops.write_buffer(hw,  first, length, data);
7191 }
7192
7193 static int
7194 ixgbe_get_module_info(struct rte_eth_dev *dev,
7195                       struct rte_eth_dev_module_info *modinfo)
7196 {
7197         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7198         uint32_t status;
7199         uint8_t sff8472_rev, addr_mode;
7200         bool page_swap = false;
7201
7202         /* Check whether we support SFF-8472 or not */
7203         status = hw->phy.ops.read_i2c_eeprom(hw,
7204                                              IXGBE_SFF_SFF_8472_COMP,
7205                                              &sff8472_rev);
7206         if (status != 0)
7207                 return -EIO;
7208
7209         /* addressing mode is not supported */
7210         status = hw->phy.ops.read_i2c_eeprom(hw,
7211                                              IXGBE_SFF_SFF_8472_SWAP,
7212                                              &addr_mode);
7213         if (status != 0)
7214                 return -EIO;
7215
7216         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7217                 PMD_DRV_LOG(ERR,
7218                             "Address change required to access page 0xA2, "
7219                             "but not supported. Please report the module "
7220                             "type to the driver maintainers.");
7221                 page_swap = true;
7222         }
7223
7224         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7225                 /* We have a SFP, but it does not support SFF-8472 */
7226                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7227                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7228         } else {
7229                 /* We have a SFP which supports a revision of SFF-8472. */
7230                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7231                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7232         }
7233
7234         return 0;
7235 }
7236
7237 static int
7238 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7239                         struct rte_dev_eeprom_info *info)
7240 {
7241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7242         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7243         uint8_t databyte = 0xFF;
7244         uint8_t *data = info->data;
7245         uint32_t i = 0;
7246
7247         if (info->length == 0)
7248                 return -EINVAL;
7249
7250         for (i = info->offset; i < info->offset + info->length; i++) {
7251                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7252                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7253                 else
7254                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7255
7256                 if (status != 0)
7257                         return -EIO;
7258
7259                 data[i - info->offset] = databyte;
7260         }
7261
7262         return 0;
7263 }
7264
7265 uint16_t
7266 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7267         switch (mac_type) {
7268         case ixgbe_mac_X550:
7269         case ixgbe_mac_X550EM_x:
7270         case ixgbe_mac_X550EM_a:
7271                 return ETH_RSS_RETA_SIZE_512;
7272         case ixgbe_mac_X550_vf:
7273         case ixgbe_mac_X550EM_x_vf:
7274         case ixgbe_mac_X550EM_a_vf:
7275                 return ETH_RSS_RETA_SIZE_64;
7276         default:
7277                 return ETH_RSS_RETA_SIZE_128;
7278         }
7279 }
7280
7281 uint32_t
7282 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7283         switch (mac_type) {
7284         case ixgbe_mac_X550:
7285         case ixgbe_mac_X550EM_x:
7286         case ixgbe_mac_X550EM_a:
7287                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7288                         return IXGBE_RETA(reta_idx >> 2);
7289                 else
7290                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7291         case ixgbe_mac_X550_vf:
7292         case ixgbe_mac_X550EM_x_vf:
7293         case ixgbe_mac_X550EM_a_vf:
7294                 return IXGBE_VFRETA(reta_idx >> 2);
7295         default:
7296                 return IXGBE_RETA(reta_idx >> 2);
7297         }
7298 }
7299
7300 uint32_t
7301 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7302         switch (mac_type) {
7303         case ixgbe_mac_X550_vf:
7304         case ixgbe_mac_X550EM_x_vf:
7305         case ixgbe_mac_X550EM_a_vf:
7306                 return IXGBE_VFMRQC;
7307         default:
7308                 return IXGBE_MRQC;
7309         }
7310 }
7311
7312 uint32_t
7313 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7314         switch (mac_type) {
7315         case ixgbe_mac_X550_vf:
7316         case ixgbe_mac_X550EM_x_vf:
7317         case ixgbe_mac_X550EM_a_vf:
7318                 return IXGBE_VFRSSRK(i);
7319         default:
7320                 return IXGBE_RSSRK(i);
7321         }
7322 }
7323
7324 bool
7325 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7326         switch (mac_type) {
7327         case ixgbe_mac_82599_vf:
7328         case ixgbe_mac_X540_vf:
7329                 return 0;
7330         default:
7331                 return 1;
7332         }
7333 }
7334
7335 static int
7336 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7337                         struct rte_eth_dcb_info *dcb_info)
7338 {
7339         struct ixgbe_dcb_config *dcb_config =
7340                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7341         struct ixgbe_dcb_tc_config *tc;
7342         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7343         uint8_t nb_tcs;
7344         uint8_t i, j;
7345
7346         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7347                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7348         else
7349                 dcb_info->nb_tcs = 1;
7350
7351         tc_queue = &dcb_info->tc_queue;
7352         nb_tcs = dcb_info->nb_tcs;
7353
7354         if (dcb_config->vt_mode) { /* vt is enabled*/
7355                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7356                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7357                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7358                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7359                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7360                         for (j = 0; j < nb_tcs; j++) {
7361                                 tc_queue->tc_rxq[0][j].base = j;
7362                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7363                                 tc_queue->tc_txq[0][j].base = j;
7364                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7365                         }
7366                 } else {
7367                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7368                                 for (j = 0; j < nb_tcs; j++) {
7369                                         tc_queue->tc_rxq[i][j].base =
7370                                                 i * nb_tcs + j;
7371                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7372                                         tc_queue->tc_txq[i][j].base =
7373                                                 i * nb_tcs + j;
7374                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7375                                 }
7376                         }
7377                 }
7378         } else { /* vt is disabled*/
7379                 struct rte_eth_dcb_rx_conf *rx_conf =
7380                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7381                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7382                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7383                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7384                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7385                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7386                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7387                         }
7388                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7389                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7390                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7391                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7392                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7393                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7394                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7395                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7396                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7397                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7398                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7399                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7400                         }
7401                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7402                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7403                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7404                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7405                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7406                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7407                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7408                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7409                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7410                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7411                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7412                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7413                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7414                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7415                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7416                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7417                 }
7418         }
7419         for (i = 0; i < dcb_info->nb_tcs; i++) {
7420                 tc = &dcb_config->tc_config[i];
7421                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7422         }
7423         return 0;
7424 }
7425
7426 /* Update e-tag ether type */
7427 static int
7428 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7429                             uint16_t ether_type)
7430 {
7431         uint32_t etag_etype;
7432
7433         if (hw->mac.type != ixgbe_mac_X550 &&
7434             hw->mac.type != ixgbe_mac_X550EM_x &&
7435             hw->mac.type != ixgbe_mac_X550EM_a) {
7436                 return -ENOTSUP;
7437         }
7438
7439         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7440         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7441         etag_etype |= ether_type;
7442         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7443         IXGBE_WRITE_FLUSH(hw);
7444
7445         return 0;
7446 }
7447
7448 /* Config l2 tunnel ether type */
7449 static int
7450 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7451                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7452 {
7453         int ret = 0;
7454         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7455         struct ixgbe_l2_tn_info *l2_tn_info =
7456                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7457
7458         if (l2_tunnel == NULL)
7459                 return -EINVAL;
7460
7461         switch (l2_tunnel->l2_tunnel_type) {
7462         case RTE_L2_TUNNEL_TYPE_E_TAG:
7463                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7464                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7465                 break;
7466         default:
7467                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7468                 ret = -EINVAL;
7469                 break;
7470         }
7471
7472         return ret;
7473 }
7474
7475 /* Enable e-tag tunnel */
7476 static int
7477 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7478 {
7479         uint32_t etag_etype;
7480
7481         if (hw->mac.type != ixgbe_mac_X550 &&
7482             hw->mac.type != ixgbe_mac_X550EM_x &&
7483             hw->mac.type != ixgbe_mac_X550EM_a) {
7484                 return -ENOTSUP;
7485         }
7486
7487         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7488         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7489         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7490         IXGBE_WRITE_FLUSH(hw);
7491
7492         return 0;
7493 }
7494
7495 /* Enable l2 tunnel */
7496 static int
7497 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7498                            enum rte_eth_tunnel_type l2_tunnel_type)
7499 {
7500         int ret = 0;
7501         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7502         struct ixgbe_l2_tn_info *l2_tn_info =
7503                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7504
7505         switch (l2_tunnel_type) {
7506         case RTE_L2_TUNNEL_TYPE_E_TAG:
7507                 l2_tn_info->e_tag_en = TRUE;
7508                 ret = ixgbe_e_tag_enable(hw);
7509                 break;
7510         default:
7511                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7512                 ret = -EINVAL;
7513                 break;
7514         }
7515
7516         return ret;
7517 }
7518
7519 /* Disable e-tag tunnel */
7520 static int
7521 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7522 {
7523         uint32_t etag_etype;
7524
7525         if (hw->mac.type != ixgbe_mac_X550 &&
7526             hw->mac.type != ixgbe_mac_X550EM_x &&
7527             hw->mac.type != ixgbe_mac_X550EM_a) {
7528                 return -ENOTSUP;
7529         }
7530
7531         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7532         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7533         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7534         IXGBE_WRITE_FLUSH(hw);
7535
7536         return 0;
7537 }
7538
7539 /* Disable l2 tunnel */
7540 static int
7541 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7542                             enum rte_eth_tunnel_type l2_tunnel_type)
7543 {
7544         int ret = 0;
7545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7546         struct ixgbe_l2_tn_info *l2_tn_info =
7547                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7548
7549         switch (l2_tunnel_type) {
7550         case RTE_L2_TUNNEL_TYPE_E_TAG:
7551                 l2_tn_info->e_tag_en = FALSE;
7552                 ret = ixgbe_e_tag_disable(hw);
7553                 break;
7554         default:
7555                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7556                 ret = -EINVAL;
7557                 break;
7558         }
7559
7560         return ret;
7561 }
7562
7563 static int
7564 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7565                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7566 {
7567         int ret = 0;
7568         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7569         uint32_t i, rar_entries;
7570         uint32_t rar_low, rar_high;
7571
7572         if (hw->mac.type != ixgbe_mac_X550 &&
7573             hw->mac.type != ixgbe_mac_X550EM_x &&
7574             hw->mac.type != ixgbe_mac_X550EM_a) {
7575                 return -ENOTSUP;
7576         }
7577
7578         rar_entries = ixgbe_get_num_rx_addrs(hw);
7579
7580         for (i = 1; i < rar_entries; i++) {
7581                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7582                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7583                 if ((rar_high & IXGBE_RAH_AV) &&
7584                     (rar_high & IXGBE_RAH_ADTYPE) &&
7585                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7586                      l2_tunnel->tunnel_id)) {
7587                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7588                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7589
7590                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7591
7592                         return ret;
7593                 }
7594         }
7595
7596         return ret;
7597 }
7598
7599 static int
7600 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7601                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7602 {
7603         int ret = 0;
7604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7605         uint32_t i, rar_entries;
7606         uint32_t rar_low, rar_high;
7607
7608         if (hw->mac.type != ixgbe_mac_X550 &&
7609             hw->mac.type != ixgbe_mac_X550EM_x &&
7610             hw->mac.type != ixgbe_mac_X550EM_a) {
7611                 return -ENOTSUP;
7612         }
7613
7614         /* One entry for one tunnel. Try to remove potential existing entry. */
7615         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7616
7617         rar_entries = ixgbe_get_num_rx_addrs(hw);
7618
7619         for (i = 1; i < rar_entries; i++) {
7620                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7621                 if (rar_high & IXGBE_RAH_AV) {
7622                         continue;
7623                 } else {
7624                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7625                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7626                         rar_low = l2_tunnel->tunnel_id;
7627
7628                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7629                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7630
7631                         return ret;
7632                 }
7633         }
7634
7635         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7636                      " Please remove a rule before adding a new one.");
7637         return -EINVAL;
7638 }
7639
7640 static inline struct ixgbe_l2_tn_filter *
7641 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7642                           struct ixgbe_l2_tn_key *key)
7643 {
7644         int ret;
7645
7646         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7647         if (ret < 0)
7648                 return NULL;
7649
7650         return l2_tn_info->hash_map[ret];
7651 }
7652
7653 static inline int
7654 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7655                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7656 {
7657         int ret;
7658
7659         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7660                                &l2_tn_filter->key);
7661
7662         if (ret < 0) {
7663                 PMD_DRV_LOG(ERR,
7664                             "Failed to insert L2 tunnel filter"
7665                             " to hash table %d!",
7666                             ret);
7667                 return ret;
7668         }
7669
7670         l2_tn_info->hash_map[ret] = l2_tn_filter;
7671
7672         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7673
7674         return 0;
7675 }
7676
7677 static inline int
7678 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7679                           struct ixgbe_l2_tn_key *key)
7680 {
7681         int ret;
7682         struct ixgbe_l2_tn_filter *l2_tn_filter;
7683
7684         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7685
7686         if (ret < 0) {
7687                 PMD_DRV_LOG(ERR,
7688                             "No such L2 tunnel filter to delete %d!",
7689                             ret);
7690                 return ret;
7691         }
7692
7693         l2_tn_filter = l2_tn_info->hash_map[ret];
7694         l2_tn_info->hash_map[ret] = NULL;
7695
7696         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7697         rte_free(l2_tn_filter);
7698
7699         return 0;
7700 }
7701
7702 /* Add l2 tunnel filter */
7703 int
7704 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7705                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7706                                bool restore)
7707 {
7708         int ret;
7709         struct ixgbe_l2_tn_info *l2_tn_info =
7710                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7711         struct ixgbe_l2_tn_key key;
7712         struct ixgbe_l2_tn_filter *node;
7713
7714         if (!restore) {
7715                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7716                 key.tn_id = l2_tunnel->tunnel_id;
7717
7718                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7719
7720                 if (node) {
7721                         PMD_DRV_LOG(ERR,
7722                                     "The L2 tunnel filter already exists!");
7723                         return -EINVAL;
7724                 }
7725
7726                 node = rte_zmalloc("ixgbe_l2_tn",
7727                                    sizeof(struct ixgbe_l2_tn_filter),
7728                                    0);
7729                 if (!node)
7730                         return -ENOMEM;
7731
7732                 rte_memcpy(&node->key,
7733                                  &key,
7734                                  sizeof(struct ixgbe_l2_tn_key));
7735                 node->pool = l2_tunnel->pool;
7736                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7737                 if (ret < 0) {
7738                         rte_free(node);
7739                         return ret;
7740                 }
7741         }
7742
7743         switch (l2_tunnel->l2_tunnel_type) {
7744         case RTE_L2_TUNNEL_TYPE_E_TAG:
7745                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7746                 break;
7747         default:
7748                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7749                 ret = -EINVAL;
7750                 break;
7751         }
7752
7753         if ((!restore) && (ret < 0))
7754                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7755
7756         return ret;
7757 }
7758
7759 /* Delete l2 tunnel filter */
7760 int
7761 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7762                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7763 {
7764         int ret;
7765         struct ixgbe_l2_tn_info *l2_tn_info =
7766                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7767         struct ixgbe_l2_tn_key key;
7768
7769         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7770         key.tn_id = l2_tunnel->tunnel_id;
7771         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7772         if (ret < 0)
7773                 return ret;
7774
7775         switch (l2_tunnel->l2_tunnel_type) {
7776         case RTE_L2_TUNNEL_TYPE_E_TAG:
7777                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7778                 break;
7779         default:
7780                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7781                 ret = -EINVAL;
7782                 break;
7783         }
7784
7785         return ret;
7786 }
7787
7788 /**
7789  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7790  * @dev: pointer to rte_eth_dev structure
7791  * @filter_op:operation will be taken.
7792  * @arg: a pointer to specific structure corresponding to the filter_op
7793  */
7794 static int
7795 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7796                                   enum rte_filter_op filter_op,
7797                                   void *arg)
7798 {
7799         int ret;
7800
7801         if (filter_op == RTE_ETH_FILTER_NOP)
7802                 return 0;
7803
7804         if (arg == NULL) {
7805                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7806                             filter_op);
7807                 return -EINVAL;
7808         }
7809
7810         switch (filter_op) {
7811         case RTE_ETH_FILTER_ADD:
7812                 ret = ixgbe_dev_l2_tunnel_filter_add
7813                         (dev,
7814                          (struct rte_eth_l2_tunnel_conf *)arg,
7815                          FALSE);
7816                 break;
7817         case RTE_ETH_FILTER_DELETE:
7818                 ret = ixgbe_dev_l2_tunnel_filter_del
7819                         (dev,
7820                          (struct rte_eth_l2_tunnel_conf *)arg);
7821                 break;
7822         default:
7823                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7824                 ret = -EINVAL;
7825                 break;
7826         }
7827         return ret;
7828 }
7829
7830 static int
7831 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7832 {
7833         int ret = 0;
7834         uint32_t ctrl;
7835         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7836
7837         if (hw->mac.type != ixgbe_mac_X550 &&
7838             hw->mac.type != ixgbe_mac_X550EM_x &&
7839             hw->mac.type != ixgbe_mac_X550EM_a) {
7840                 return -ENOTSUP;
7841         }
7842
7843         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7844         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7845         if (en)
7846                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7847         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7848
7849         return ret;
7850 }
7851
7852 /* Enable l2 tunnel forwarding */
7853 static int
7854 ixgbe_dev_l2_tunnel_forwarding_enable
7855         (struct rte_eth_dev *dev,
7856          enum rte_eth_tunnel_type l2_tunnel_type)
7857 {
7858         struct ixgbe_l2_tn_info *l2_tn_info =
7859                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7860         int ret = 0;
7861
7862         switch (l2_tunnel_type) {
7863         case RTE_L2_TUNNEL_TYPE_E_TAG:
7864                 l2_tn_info->e_tag_fwd_en = TRUE;
7865                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7866                 break;
7867         default:
7868                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7869                 ret = -EINVAL;
7870                 break;
7871         }
7872
7873         return ret;
7874 }
7875
7876 /* Disable l2 tunnel forwarding */
7877 static int
7878 ixgbe_dev_l2_tunnel_forwarding_disable
7879         (struct rte_eth_dev *dev,
7880          enum rte_eth_tunnel_type l2_tunnel_type)
7881 {
7882         struct ixgbe_l2_tn_info *l2_tn_info =
7883                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7884         int ret = 0;
7885
7886         switch (l2_tunnel_type) {
7887         case RTE_L2_TUNNEL_TYPE_E_TAG:
7888                 l2_tn_info->e_tag_fwd_en = FALSE;
7889                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7890                 break;
7891         default:
7892                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7893                 ret = -EINVAL;
7894                 break;
7895         }
7896
7897         return ret;
7898 }
7899
7900 static int
7901 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7902                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7903                              bool en)
7904 {
7905         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7906         int ret = 0;
7907         uint32_t vmtir, vmvir;
7908         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7909
7910         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7911                 PMD_DRV_LOG(ERR,
7912                             "VF id %u should be less than %u",
7913                             l2_tunnel->vf_id,
7914                             pci_dev->max_vfs);
7915                 return -EINVAL;
7916         }
7917
7918         if (hw->mac.type != ixgbe_mac_X550 &&
7919             hw->mac.type != ixgbe_mac_X550EM_x &&
7920             hw->mac.type != ixgbe_mac_X550EM_a) {
7921                 return -ENOTSUP;
7922         }
7923
7924         if (en)
7925                 vmtir = l2_tunnel->tunnel_id;
7926         else
7927                 vmtir = 0;
7928
7929         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7930
7931         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7932         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7933         if (en)
7934                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7935         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7936
7937         return ret;
7938 }
7939
7940 /* Enable l2 tunnel tag insertion */
7941 static int
7942 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7943                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7944 {
7945         int ret = 0;
7946
7947         switch (l2_tunnel->l2_tunnel_type) {
7948         case RTE_L2_TUNNEL_TYPE_E_TAG:
7949                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7950                 break;
7951         default:
7952                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7953                 ret = -EINVAL;
7954                 break;
7955         }
7956
7957         return ret;
7958 }
7959
7960 /* Disable l2 tunnel tag insertion */
7961 static int
7962 ixgbe_dev_l2_tunnel_insertion_disable
7963         (struct rte_eth_dev *dev,
7964          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7965 {
7966         int ret = 0;
7967
7968         switch (l2_tunnel->l2_tunnel_type) {
7969         case RTE_L2_TUNNEL_TYPE_E_TAG:
7970                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7971                 break;
7972         default:
7973                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7974                 ret = -EINVAL;
7975                 break;
7976         }
7977
7978         return ret;
7979 }
7980
7981 static int
7982 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7983                              bool en)
7984 {
7985         int ret = 0;
7986         uint32_t qde;
7987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7988
7989         if (hw->mac.type != ixgbe_mac_X550 &&
7990             hw->mac.type != ixgbe_mac_X550EM_x &&
7991             hw->mac.type != ixgbe_mac_X550EM_a) {
7992                 return -ENOTSUP;
7993         }
7994
7995         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7996         if (en)
7997                 qde |= IXGBE_QDE_STRIP_TAG;
7998         else
7999                 qde &= ~IXGBE_QDE_STRIP_TAG;
8000         qde &= ~IXGBE_QDE_READ;
8001         qde |= IXGBE_QDE_WRITE;
8002         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8003
8004         return ret;
8005 }
8006
8007 /* Enable l2 tunnel tag stripping */
8008 static int
8009 ixgbe_dev_l2_tunnel_stripping_enable
8010         (struct rte_eth_dev *dev,
8011          enum rte_eth_tunnel_type l2_tunnel_type)
8012 {
8013         int ret = 0;
8014
8015         switch (l2_tunnel_type) {
8016         case RTE_L2_TUNNEL_TYPE_E_TAG:
8017                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8018                 break;
8019         default:
8020                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8021                 ret = -EINVAL;
8022                 break;
8023         }
8024
8025         return ret;
8026 }
8027
8028 /* Disable l2 tunnel tag stripping */
8029 static int
8030 ixgbe_dev_l2_tunnel_stripping_disable
8031         (struct rte_eth_dev *dev,
8032          enum rte_eth_tunnel_type l2_tunnel_type)
8033 {
8034         int ret = 0;
8035
8036         switch (l2_tunnel_type) {
8037         case RTE_L2_TUNNEL_TYPE_E_TAG:
8038                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8039                 break;
8040         default:
8041                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8042                 ret = -EINVAL;
8043                 break;
8044         }
8045
8046         return ret;
8047 }
8048
8049 /* Enable/disable l2 tunnel offload functions */
8050 static int
8051 ixgbe_dev_l2_tunnel_offload_set
8052         (struct rte_eth_dev *dev,
8053          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8054          uint32_t mask,
8055          uint8_t en)
8056 {
8057         int ret = 0;
8058
8059         if (l2_tunnel == NULL)
8060                 return -EINVAL;
8061
8062         ret = -EINVAL;
8063         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8064                 if (en)
8065                         ret = ixgbe_dev_l2_tunnel_enable(
8066                                 dev,
8067                                 l2_tunnel->l2_tunnel_type);
8068                 else
8069                         ret = ixgbe_dev_l2_tunnel_disable(
8070                                 dev,
8071                                 l2_tunnel->l2_tunnel_type);
8072         }
8073
8074         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8075                 if (en)
8076                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8077                                 dev,
8078                                 l2_tunnel);
8079                 else
8080                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8081                                 dev,
8082                                 l2_tunnel);
8083         }
8084
8085         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8086                 if (en)
8087                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8088                                 dev,
8089                                 l2_tunnel->l2_tunnel_type);
8090                 else
8091                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8092                                 dev,
8093                                 l2_tunnel->l2_tunnel_type);
8094         }
8095
8096         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8097                 if (en)
8098                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8099                                 dev,
8100                                 l2_tunnel->l2_tunnel_type);
8101                 else
8102                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8103                                 dev,
8104                                 l2_tunnel->l2_tunnel_type);
8105         }
8106
8107         return ret;
8108 }
8109
8110 static int
8111 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8112                         uint16_t port)
8113 {
8114         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8115         IXGBE_WRITE_FLUSH(hw);
8116
8117         return 0;
8118 }
8119
8120 /* There's only one register for VxLAN UDP port.
8121  * So, we cannot add several ports. Will update it.
8122  */
8123 static int
8124 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8125                      uint16_t port)
8126 {
8127         if (port == 0) {
8128                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8129                 return -EINVAL;
8130         }
8131
8132         return ixgbe_update_vxlan_port(hw, port);
8133 }
8134
8135 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8136  * UDP port, it must have a value.
8137  * So, will reset it to the original value 0.
8138  */
8139 static int
8140 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8141                      uint16_t port)
8142 {
8143         uint16_t cur_port;
8144
8145         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8146
8147         if (cur_port != port) {
8148                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8149                 return -EINVAL;
8150         }
8151
8152         return ixgbe_update_vxlan_port(hw, 0);
8153 }
8154
8155 /* Add UDP tunneling port */
8156 static int
8157 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8158                               struct rte_eth_udp_tunnel *udp_tunnel)
8159 {
8160         int ret = 0;
8161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8162
8163         if (hw->mac.type != ixgbe_mac_X550 &&
8164             hw->mac.type != ixgbe_mac_X550EM_x &&
8165             hw->mac.type != ixgbe_mac_X550EM_a) {
8166                 return -ENOTSUP;
8167         }
8168
8169         if (udp_tunnel == NULL)
8170                 return -EINVAL;
8171
8172         switch (udp_tunnel->prot_type) {
8173         case RTE_TUNNEL_TYPE_VXLAN:
8174                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8175                 break;
8176
8177         case RTE_TUNNEL_TYPE_GENEVE:
8178         case RTE_TUNNEL_TYPE_TEREDO:
8179                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8180                 ret = -EINVAL;
8181                 break;
8182
8183         default:
8184                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8185                 ret = -EINVAL;
8186                 break;
8187         }
8188
8189         return ret;
8190 }
8191
8192 /* Remove UDP tunneling port */
8193 static int
8194 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8195                               struct rte_eth_udp_tunnel *udp_tunnel)
8196 {
8197         int ret = 0;
8198         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8199
8200         if (hw->mac.type != ixgbe_mac_X550 &&
8201             hw->mac.type != ixgbe_mac_X550EM_x &&
8202             hw->mac.type != ixgbe_mac_X550EM_a) {
8203                 return -ENOTSUP;
8204         }
8205
8206         if (udp_tunnel == NULL)
8207                 return -EINVAL;
8208
8209         switch (udp_tunnel->prot_type) {
8210         case RTE_TUNNEL_TYPE_VXLAN:
8211                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8212                 break;
8213         case RTE_TUNNEL_TYPE_GENEVE:
8214         case RTE_TUNNEL_TYPE_TEREDO:
8215                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8216                 ret = -EINVAL;
8217                 break;
8218         default:
8219                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8220                 ret = -EINVAL;
8221                 break;
8222         }
8223
8224         return ret;
8225 }
8226
8227 static void
8228 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8229 {
8230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8231
8232         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8233 }
8234
8235 static void
8236 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8237 {
8238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8239
8240         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8241 }
8242
8243 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8244 {
8245         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8246         u32 in_msg = 0;
8247
8248         /* peek the message first */
8249         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8250
8251         /* PF reset VF event */
8252         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8253                 /* dummy mbx read to ack pf */
8254                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8255                         return;
8256                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8257                                               NULL);
8258         }
8259 }
8260
8261 static int
8262 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8263 {
8264         uint32_t eicr;
8265         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8266         struct ixgbe_interrupt *intr =
8267                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8268         ixgbevf_intr_disable(hw);
8269
8270         /* read-on-clear nic registers here */
8271         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8272         intr->flags = 0;
8273
8274         /* only one misc vector supported - mailbox */
8275         eicr &= IXGBE_VTEICR_MASK;
8276         if (eicr == IXGBE_MISC_VEC_ID)
8277                 intr->flags |= IXGBE_FLAG_MAILBOX;
8278
8279         return 0;
8280 }
8281
8282 static int
8283 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8284 {
8285         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8286         struct ixgbe_interrupt *intr =
8287                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8288
8289         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8290                 ixgbevf_mbx_process(dev);
8291                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8292         }
8293
8294         ixgbevf_intr_enable(hw);
8295
8296         return 0;
8297 }
8298
8299 static void
8300 ixgbevf_dev_interrupt_handler(void *param)
8301 {
8302         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8303
8304         ixgbevf_dev_interrupt_get_status(dev);
8305         ixgbevf_dev_interrupt_action(dev);
8306 }
8307
8308 /**
8309  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8310  *  @hw: pointer to hardware structure
8311  *
8312  *  Stops the transmit data path and waits for the HW to internally empty
8313  *  the Tx security block
8314  **/
8315 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8316 {
8317 #define IXGBE_MAX_SECTX_POLL 40
8318
8319         int i;
8320         int sectxreg;
8321
8322         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8323         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8324         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8325         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8326                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8327                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8328                         break;
8329                 /* Use interrupt-safe sleep just in case */
8330                 usec_delay(1000);
8331         }
8332
8333         /* For informational purposes only */
8334         if (i >= IXGBE_MAX_SECTX_POLL)
8335                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8336                          "path fully disabled.  Continuing with init.");
8337
8338         return IXGBE_SUCCESS;
8339 }
8340
8341 /**
8342  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8343  *  @hw: pointer to hardware structure
8344  *
8345  *  Enables the transmit data path.
8346  **/
8347 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8348 {
8349         uint32_t sectxreg;
8350
8351         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8352         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8353         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8354         IXGBE_WRITE_FLUSH(hw);
8355
8356         return IXGBE_SUCCESS;
8357 }
8358
8359 /* restore n-tuple filter */
8360 static inline void
8361 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8362 {
8363         struct ixgbe_filter_info *filter_info =
8364                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8365         struct ixgbe_5tuple_filter *node;
8366
8367         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8368                 ixgbe_inject_5tuple_filter(dev, node);
8369         }
8370 }
8371
8372 /* restore ethernet type filter */
8373 static inline void
8374 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8375 {
8376         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8377         struct ixgbe_filter_info *filter_info =
8378                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8379         int i;
8380
8381         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8382                 if (filter_info->ethertype_mask & (1 << i)) {
8383                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8384                                         filter_info->ethertype_filters[i].etqf);
8385                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8386                                         filter_info->ethertype_filters[i].etqs);
8387                         IXGBE_WRITE_FLUSH(hw);
8388                 }
8389         }
8390 }
8391
8392 /* restore SYN filter */
8393 static inline void
8394 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8395 {
8396         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8397         struct ixgbe_filter_info *filter_info =
8398                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8399         uint32_t synqf;
8400
8401         synqf = filter_info->syn_info;
8402
8403         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8404                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8405                 IXGBE_WRITE_FLUSH(hw);
8406         }
8407 }
8408
8409 /* restore L2 tunnel filter */
8410 static inline void
8411 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8412 {
8413         struct ixgbe_l2_tn_info *l2_tn_info =
8414                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8415         struct ixgbe_l2_tn_filter *node;
8416         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8417
8418         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8419                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8420                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8421                 l2_tn_conf.pool           = node->pool;
8422                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8423         }
8424 }
8425
8426 /* restore rss filter */
8427 static inline void
8428 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8429 {
8430         struct ixgbe_filter_info *filter_info =
8431                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8432
8433         if (filter_info->rss_info.conf.queue_num)
8434                 ixgbe_config_rss_filter(dev,
8435                         &filter_info->rss_info, TRUE);
8436 }
8437
8438 static int
8439 ixgbe_filter_restore(struct rte_eth_dev *dev)
8440 {
8441         ixgbe_ntuple_filter_restore(dev);
8442         ixgbe_ethertype_filter_restore(dev);
8443         ixgbe_syn_filter_restore(dev);
8444         ixgbe_fdir_filter_restore(dev);
8445         ixgbe_l2_tn_filter_restore(dev);
8446         ixgbe_rss_filter_restore(dev);
8447
8448         return 0;
8449 }
8450
8451 static void
8452 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8453 {
8454         struct ixgbe_l2_tn_info *l2_tn_info =
8455                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8456         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8457
8458         if (l2_tn_info->e_tag_en)
8459                 (void)ixgbe_e_tag_enable(hw);
8460
8461         if (l2_tn_info->e_tag_fwd_en)
8462                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8463
8464         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8465 }
8466
8467 /* remove all the n-tuple filters */
8468 void
8469 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8470 {
8471         struct ixgbe_filter_info *filter_info =
8472                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8473         struct ixgbe_5tuple_filter *p_5tuple;
8474
8475         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8476                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8477 }
8478
8479 /* remove all the ether type filters */
8480 void
8481 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8482 {
8483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8484         struct ixgbe_filter_info *filter_info =
8485                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8486         int i;
8487
8488         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8489                 if (filter_info->ethertype_mask & (1 << i) &&
8490                     !filter_info->ethertype_filters[i].conf) {
8491                         (void)ixgbe_ethertype_filter_remove(filter_info,
8492                                                             (uint8_t)i);
8493                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8494                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8495                         IXGBE_WRITE_FLUSH(hw);
8496                 }
8497         }
8498 }
8499
8500 /* remove the SYN filter */
8501 void
8502 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8503 {
8504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8505         struct ixgbe_filter_info *filter_info =
8506                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8507
8508         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8509                 filter_info->syn_info = 0;
8510
8511                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8512                 IXGBE_WRITE_FLUSH(hw);
8513         }
8514 }
8515
8516 /* remove all the L2 tunnel filters */
8517 int
8518 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8519 {
8520         struct ixgbe_l2_tn_info *l2_tn_info =
8521                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8522         struct ixgbe_l2_tn_filter *l2_tn_filter;
8523         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8524         int ret = 0;
8525
8526         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8527                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8528                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8529                 l2_tn_conf.pool           = l2_tn_filter->pool;
8530                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8531                 if (ret < 0)
8532                         return ret;
8533         }
8534
8535         return 0;
8536 }
8537
8538 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8539 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8540 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8541 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8542 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8543 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8544
8545 RTE_INIT(ixgbe_init_log);
8546 static void
8547 ixgbe_init_log(void)
8548 {
8549         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8550         if (ixgbe_logtype_init >= 0)
8551                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8552         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8553         if (ixgbe_logtype_driver >= 0)
8554                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8555 }