drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Timer value included in XOFF frames. */
  63 #define IXGBE_FC_PAUSE 0x680
  64
  65 /*Default value of Max Rx Queue*/
  66 #define IXGBE_MAX_RX_QUEUE_NUM 128
  67
  68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  71
  72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  75
  76 /*
  77  *  Default values for RX/TX configuration
  78  */
  79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  80 #define IXGBE_DEFAULT_RX_PTHRESH      8
  81 #define IXGBE_DEFAULT_RX_HTHRESH      8
  82 #define IXGBE_DEFAULT_RX_WTHRESH      0
  83
  84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  85 #define IXGBE_DEFAULT_TX_PTHRESH      32
  86 #define IXGBE_DEFAULT_TX_HTHRESH      0
  87 #define IXGBE_DEFAULT_TX_WTHRESH      0
  88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  89
  90 /* Bit shift and mask */
  91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  94 #define IXGBE_8_BIT_MASK   UINT8_MAX
  95
  96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  97
  98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  99
 100 /* Additional timesync values. */
 101 #define NSEC_PER_SEC             1000000000L
 102 #define IXGBE_INCVAL_10GB        0x66666666
 103 #define IXGBE_INCVAL_1GB         0x40000000
 104 #define IXGBE_INCVAL_100         0x50000000
 105 #define IXGBE_INCVAL_SHIFT_10GB  28
 106 #define IXGBE_INCVAL_SHIFT_1GB   24
 107 #define IXGBE_INCVAL_SHIFT_100   21
 108 #define IXGBE_INCVAL_SHIFT_82599 7
 109 #define IXGBE_INCPER_SHIFT_82599 24
 110
 111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 115 #define IXGBE_ETAG_ETYPE                       0x00005084
 116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 118 #define IXGBE_RAH_ADTYPE                       0x40000000
 119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 124 #define IXGBE_VTEICR_MASK                      0x07
 125
 126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 128
 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 148                                 int wait_to_complete);
 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 150                                 struct rte_eth_stats *stats);
 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 152                                 struct rte_eth_xstat *xstats, unsigned n);
 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 154                                   struct rte_eth_xstat *xstats, unsigned n);
 155 static int
 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 157                 uint64_t *values, unsigned int n);
 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 161         struct rte_eth_xstat_name *xstats_names,
 162         unsigned int size);
 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 165 static int ixgbe_dev_xstats_get_names_by_id(
 166         struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         const uint64_t *ids,
 169         unsigned int limit);
 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 171                                              uint16_t queue_id,
 172                                              uint8_t stat_idx,
 173                                              uint8_t is_rx);
 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 175                                  size_t fw_size);
 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_dev_info *dev_info);
 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 180                                  struct rte_eth_dev_info *dev_info);
 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 182
 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 184                 uint16_t vlan_id, int on);
 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 186                                enum rte_vlan_type vlan_type,
 187                                uint16_t tpid_id);
 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 189                 uint16_t queue, bool on);
 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 191                 int on);
 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 193                                                   int mask);
 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 221 static void ixgbe_dev_interrupt_handler(void *param);
 222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 223 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 224
 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 226                          uint32_t index, uint32_t pool);
 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 228 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 229                                            struct ether_addr *mac_addr);
 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 231 static bool is_device_supported(struct rte_eth_dev *dev,
 232                                 struct rte_pci_driver *drv);
 233
 234 /* For Virtual Function support */
 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 237 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 238 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 240                                    int wait_to_complete);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 245 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 254 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 256 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 257                                             uint16_t queue_id);
 258 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 259                                              uint16_t queue_id);
 260 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 261                                  uint8_t queue, uint8_t msix_vector);
 262 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 267
 268 /* For Eth VMDQ APIs support */
 269 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 270                 ether_addr * mac_addr, uint8_t on);
 271 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 272 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 273                 struct rte_eth_mirror_conf *mirror_conf,
 274                 uint8_t rule_id, uint8_t on);
 275 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 276                 uint8_t rule_id);
 277 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 278                                           uint16_t queue_id);
 279 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 280                                            uint16_t queue_id);
 281 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 282                                uint8_t queue, uint8_t msix_vector);
 283 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 284
 285 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 286                                 struct ether_addr *mac_addr,
 287                                 uint32_t index, uint32_t pool);
 288 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 289 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 290                                              struct ether_addr *mac_addr);
 291 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 292                         struct rte_eth_syn_filter *filter);
 293 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 294                         enum rte_filter_op filter_op,
 295                         void *arg);
 296 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 297                         struct ixgbe_5tuple_filter *filter);
 298 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 301                                 enum rte_filter_op filter_op,
 302                                 void *arg);
 303 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 304                         struct rte_eth_ntuple_filter *filter);
 305 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 306                                 enum rte_filter_op filter_op,
 307                                 void *arg);
 308 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 309                         struct rte_eth_ethertype_filter *filter);
 310 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 311                      enum rte_filter_type filter_type,
 312                      enum rte_filter_op filter_op,
 313                      void *arg);
 314 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 315
 316 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 317                                       struct ether_addr *mc_addr_set,
 318                                       uint32_t nb_mc_addr);
 319 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 320                                    struct rte_eth_dcb_info *dcb_info);
 321
 322 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 324                             struct rte_dev_reg_info *regs);
 325 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 326 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 327                                 struct rte_dev_eeprom_info *eeprom);
 328 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 329                                 struct rte_dev_eeprom_info *eeprom);
 330
 331 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 332                                  struct rte_eth_dev_module_info *modinfo);
 333 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 334                                    struct rte_dev_eeprom_info *info);
 335
 336 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 337 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 338                                 struct rte_dev_reg_info *regs);
 339
 340 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 341 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 342 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 343                                             struct timespec *timestamp,
 344                                             uint32_t flags);
 345 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 346                                             struct timespec *timestamp);
 347 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 348 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 349                                    struct timespec *timestamp);
 350 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 351                                    const struct timespec *timestamp);
 352 static void ixgbevf_dev_interrupt_handler(void *param);
 353
 354 static int ixgbe_dev_l2_tunnel_eth_type_conf
 355         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 356 static int ixgbe_dev_l2_tunnel_offload_set
 357         (struct rte_eth_dev *dev,
 358          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 359          uint32_t mask,
 360          uint8_t en);
 361 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 362                                              enum rte_filter_op filter_op,
 363                                              void *arg);
 364
 365 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 366                                          struct rte_eth_udp_tunnel *udp_tunnel);
 367 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 368                                          struct rte_eth_udp_tunnel *udp_tunnel);
 369 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 370 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 371
 372 /*
 373  * Define VF Stats MACRO for Non "cleared on read" register
 374  */
 375 #define UPDATE_VF_STAT(reg, last, cur)                          \
 376 {                                                               \
 377         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 378         cur += (latest - last) & UINT_MAX;                      \
 379         last = latest;                                          \
 380 }
 381
 382 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 383 {                                                                \
 384         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 385         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 386         u64 latest = ((new_msb << 32) | new_lsb);                \
 387         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 388         last = latest;                                           \
 389 }
 390
 391 #define IXGBE_SET_HWSTRIP(h, q) do {\
 392                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] |= 1 << bit;\
 395         } while (0)
 396
 397 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 398                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 400                 (h)->bitmap[idx] &= ~(1 << bit);\
 401         } while (0)
 402
 403 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 404                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 405                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 406                 (r) = (h)->bitmap[idx] >> bit & 1;\
 407         } while (0)
 408
 409 int ixgbe_logtype_init;
 410 int ixgbe_logtype_driver;
 411
 412 /*
 413  * The set of PCI devices this driver supports
 414  */
 415 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 463 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 465 #endif
 466         { .vendor_id = 0, /* sentinel */ },
 467 };
 468
 469 /*
 470  * The set of PCI devices this driver supports (for 82599 VF)
 471  */
 472 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 483         { .vendor_id = 0, /* sentinel */ },
 484 };
 485
 486 static const struct rte_eth_desc_lim rx_desc_lim = {
 487         .nb_max = IXGBE_MAX_RING_DESC,
 488         .nb_min = IXGBE_MIN_RING_DESC,
 489         .nb_align = IXGBE_RXD_ALIGN,
 490 };
 491
 492 static const struct rte_eth_desc_lim tx_desc_lim = {
 493         .nb_max = IXGBE_MAX_RING_DESC,
 494         .nb_min = IXGBE_MIN_RING_DESC,
 495         .nb_align = IXGBE_TXD_ALIGN,
 496         .nb_seg_max = IXGBE_TX_MAX_SEG,
 497         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 498 };
 499
 500 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 501         .dev_configure        = ixgbe_dev_configure,
 502         .dev_start            = ixgbe_dev_start,
 503         .dev_stop             = ixgbe_dev_stop,
 504         .dev_set_link_up    = ixgbe_dev_set_link_up,
 505         .dev_set_link_down  = ixgbe_dev_set_link_down,
 506         .dev_close            = ixgbe_dev_close,
 507         .dev_reset            = ixgbe_dev_reset,
 508         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 509         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 510         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 511         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 512         .link_update          = ixgbe_dev_link_update,
 513         .stats_get            = ixgbe_dev_stats_get,
 514         .xstats_get           = ixgbe_dev_xstats_get,
 515         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 516         .stats_reset          = ixgbe_dev_stats_reset,
 517         .xstats_reset         = ixgbe_dev_xstats_reset,
 518         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 519         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 520         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 521         .fw_version_get       = ixgbe_fw_version_get,
 522         .dev_infos_get        = ixgbe_dev_info_get,
 523         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 524         .mtu_set              = ixgbe_dev_mtu_set,
 525         .vlan_filter_set      = ixgbe_vlan_filter_set,
 526         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 527         .vlan_offload_set     = ixgbe_vlan_offload_set,
 528         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 529         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 530         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 531         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 532         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 533         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 534         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 535         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 536         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 537         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 538         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 539         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 540         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 541         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 542         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 543         .dev_led_on           = ixgbe_dev_led_on,
 544         .dev_led_off          = ixgbe_dev_led_off,
 545         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 546         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 547         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 548         .mac_addr_add         = ixgbe_add_rar,
 549         .mac_addr_remove      = ixgbe_remove_rar,
 550         .mac_addr_set         = ixgbe_set_default_mac_addr,
 551         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 552         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 553         .mirror_rule_set      = ixgbe_mirror_rule_set,
 554         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 555         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 556         .reta_update          = ixgbe_dev_rss_reta_update,
 557         .reta_query           = ixgbe_dev_rss_reta_query,
 558         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 559         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 560         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 561         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 562         .rxq_info_get         = ixgbe_rxq_info_get,
 563         .txq_info_get         = ixgbe_txq_info_get,
 564         .timesync_enable      = ixgbe_timesync_enable,
 565         .timesync_disable     = ixgbe_timesync_disable,
 566         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 567         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 568         .get_reg              = ixgbe_get_regs,
 569         .get_eeprom_length    = ixgbe_get_eeprom_length,
 570         .get_eeprom           = ixgbe_get_eeprom,
 571         .set_eeprom           = ixgbe_set_eeprom,
 572         .get_module_info      = ixgbe_get_module_info,
 573         .get_module_eeprom    = ixgbe_get_module_eeprom,
 574         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 575         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 576         .timesync_read_time   = ixgbe_timesync_read_time,
 577         .timesync_write_time  = ixgbe_timesync_write_time,
 578         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 579         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 580         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 581         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 582         .tm_ops_get           = ixgbe_tm_ops_get,
 583 };
 584
 585 /*
 586  * dev_ops for virtual function, bare necessities for basic vf
 587  * operation have been implemented
 588  */
 589 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 590         .dev_configure        = ixgbevf_dev_configure,
 591         .dev_start            = ixgbevf_dev_start,
 592         .dev_stop             = ixgbevf_dev_stop,
 593         .link_update          = ixgbevf_dev_link_update,
 594         .stats_get            = ixgbevf_dev_stats_get,
 595         .xstats_get           = ixgbevf_dev_xstats_get,
 596         .stats_reset          = ixgbevf_dev_stats_reset,
 597         .xstats_reset         = ixgbevf_dev_stats_reset,
 598         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 599         .dev_close            = ixgbevf_dev_close,
 600         .dev_reset            = ixgbevf_dev_reset,
 601         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 602         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 603         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 604         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 605         .dev_infos_get        = ixgbevf_dev_info_get,
 606         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 607         .mtu_set              = ixgbevf_dev_set_mtu,
 608         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 609         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 610         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 611         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 612         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 613         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 614         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 615         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 616         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 617         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 618         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 619         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 620         .mac_addr_add         = ixgbevf_add_mac_addr,
 621         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 622         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 623         .rxq_info_get         = ixgbe_rxq_info_get,
 624         .txq_info_get         = ixgbe_txq_info_get,
 625         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 626         .get_reg              = ixgbevf_get_regs,
 627         .reta_update          = ixgbe_dev_rss_reta_update,
 628         .reta_query           = ixgbe_dev_rss_reta_query,
 629         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 630         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 631 };
 632
 633 /* store statistics names and its offset in stats structure */
 634 struct rte_ixgbe_xstats_name_off {
 635         char name[RTE_ETH_XSTATS_NAME_SIZE];
 636         unsigned offset;
 637 };
 638
 639 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 640         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 641         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 642         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 643         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 644         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 645         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 646         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 647         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 648         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 649         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 650         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 651         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 652         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 653         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 654         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 655                 prc1023)},
 656         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 657                 prc1522)},
 658         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 659         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 660         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 661         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 662         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 663         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 664         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 665         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 666         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 667         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 668         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 669         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 670         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 671         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 672         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 673         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 674         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 675                 ptc1023)},
 676         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 677                 ptc1522)},
 678         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 679         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 680         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 681         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 682
 683         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 684                 fdirustat_add)},
 685         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 686                 fdirustat_remove)},
 687         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 688                 fdirfstat_fadd)},
 689         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 690                 fdirfstat_fremove)},
 691         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 692                 fdirmatch)},
 693         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 694                 fdirmiss)},
 695
 696         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 697         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 698         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 699                 fclast)},
 700         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 701         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 702         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 703         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 704         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 705                 fcoe_noddp)},
 706         {"rx_fcoe_no_direct_data_placement_ext_buff",
 707                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 708
 709         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxontxc)},
 711         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxonrxc)},
 713         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 714                 lxofftxc)},
 715         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 716                 lxoffrxc)},
 717         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 718 };
 719
 720 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 721                            sizeof(rte_ixgbe_stats_strings[0]))
 722
 723 /* MACsec statistics */
 724 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 725         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_untagged)},
 727         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 728                 out_pkts_encrypted)},
 729         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 730                 out_pkts_protected)},
 731         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 732                 out_octets_encrypted)},
 733         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 734                 out_octets_protected)},
 735         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_untagged)},
 737         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_badtag)},
 739         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_nosci)},
 741         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_unknownsci)},
 743         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 744                 in_octets_decrypted)},
 745         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 746                 in_octets_validated)},
 747         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_unchecked)},
 749         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_delayed)},
 751         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_late)},
 753         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_ok)},
 755         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_invalid)},
 757         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_notvalid)},
 759         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_unusedsa)},
 761         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_notusingsa)},
 763 };
 764
 765 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 766                            sizeof(rte_ixgbe_macsec_strings[0]))
 767
 768 /* Per-queue statistics */
 769 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 770         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 771         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 772         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 773         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 774 };
 775
 776 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 777                            sizeof(rte_ixgbe_rxq_strings[0]))
 778 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 779
 780 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 781         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 782         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 783         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 784                 pxon2offc)},
 785 };
 786
 787 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 788                            sizeof(rte_ixgbe_txq_strings[0]))
 789 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 790
 791 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 792         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 793 };
 794
 795 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 796                 sizeof(rte_ixgbevf_stats_strings[0]))
 797
 798 /*
 799  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 800  */
 801 static inline int
 802 ixgbe_is_sfp(struct ixgbe_hw *hw)
 803 {
 804         switch (hw->phy.type) {
 805         case ixgbe_phy_sfp_avago:
 806         case ixgbe_phy_sfp_ftl:
 807         case ixgbe_phy_sfp_intel:
 808         case ixgbe_phy_sfp_unknown:
 809         case ixgbe_phy_sfp_passive_tyco:
 810         case ixgbe_phy_sfp_passive_unknown:
 811                 return 1;
 812         default:
 813                 return 0;
 814         }
 815 }
 816
 817 static inline int32_t
 818 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 819 {
 820         uint32_t ctrl_ext;
 821         int32_t status;
 822
 823         status = ixgbe_reset_hw(hw);
 824
 825         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 826         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 827         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 828         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 829         IXGBE_WRITE_FLUSH(hw);
 830
 831         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 832                 status = IXGBE_SUCCESS;
 833         return status;
 834 }
 835
 836 static inline void
 837 ixgbe_enable_intr(struct rte_eth_dev *dev)
 838 {
 839         struct ixgbe_interrupt *intr =
 840                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 841         struct ixgbe_hw *hw =
 842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 843
 844         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 845         IXGBE_WRITE_FLUSH(hw);
 846 }
 847
 848 /*
 849  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 850  */
 851 static void
 852 ixgbe_disable_intr(struct ixgbe_hw *hw)
 853 {
 854         PMD_INIT_FUNC_TRACE();
 855
 856         if (hw->mac.type == ixgbe_mac_82598EB) {
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 858         } else {
 859                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 860                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 861                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 862         }
 863         IXGBE_WRITE_FLUSH(hw);
 864 }
 865
 866 /*
 867  * This function resets queue statistics mapping registers.
 868  * From Niantic datasheet, Initialization of Statistics section:
 869  * "...if software requires the queue counters, the RQSMR and TQSM registers
 870  * must be re-programmed following a device reset.
 871  */
 872 static void
 873 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 874 {
 875         uint32_t i;
 876
 877         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 878                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 879                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 880         }
 881 }
 882
 883
 884 static int
 885 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 886                                   uint16_t queue_id,
 887                                   uint8_t stat_idx,
 888                                   uint8_t is_rx)
 889 {
 890 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 891 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 892 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 893
 894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 895         struct ixgbe_stat_mapping_registers *stat_mappings =
 896                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 897         uint32_t qsmr_mask = 0;
 898         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 899         uint32_t q_map;
 900         uint8_t n, offset;
 901
 902         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 903                 (hw->mac.type != ixgbe_mac_X540) &&
 904                 (hw->mac.type != ixgbe_mac_X550) &&
 905                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 906                 (hw->mac.type != ixgbe_mac_X550EM_a))
 907                 return -ENOSYS;
 908
 909         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 910                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 911                      queue_id, stat_idx);
 912
 913         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 914         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 915                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 916                 return -EIO;
 917         }
 918         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 919
 920         /* Now clear any previous stat_idx set */
 921         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 922         if (!is_rx)
 923                 stat_mappings->tqsm[n] &= ~clearing_mask;
 924         else
 925                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 926
 927         q_map = (uint32_t)stat_idx;
 928         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 929         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 930         if (!is_rx)
 931                 stat_mappings->tqsm[n] |= qsmr_mask;
 932         else
 933                 stat_mappings->rqsmr[n] |= qsmr_mask;
 934
 935         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 936                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 937                      queue_id, stat_idx);
 938         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 939                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 940
 941         /* Now write the mapping in the appropriate register */
 942         if (is_rx) {
 943                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 944                              stat_mappings->rqsmr[n], n);
 945                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 946         } else {
 947                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 948                              stat_mappings->tqsm[n], n);
 949                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 950         }
 951         return 0;
 952 }
 953
 954 static void
 955 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 956 {
 957         struct ixgbe_stat_mapping_registers *stat_mappings =
 958                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 960         int i;
 961
 962         /* write whatever was in stat mapping table to the NIC */
 963         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 964                 /* rx */
 965                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 966
 967                 /* tx */
 968                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 969         }
 970 }
 971
 972 static void
 973 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 974 {
 975         uint8_t i;
 976         struct ixgbe_dcb_tc_config *tc;
 977         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 978
 979         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 980         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 981         for (i = 0; i < dcb_max_tc; i++) {
 982                 tc = &dcb_config->tc_config[i];
 983                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 984                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 985                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 986                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 987                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 988                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 989                 tc->pfc = ixgbe_dcb_pfc_disabled;
 990         }
 991
 992         /* Initialize default user to priority mapping, UPx->TC0 */
 993         tc = &dcb_config->tc_config[0];
 994         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 995         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 996         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 997                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 998                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 999         }
1000         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1001         dcb_config->pfc_mode_enable = false;
1002         dcb_config->vt_mode = true;
1003         dcb_config->round_robin_enable = false;
1004         /* support all DCB capabilities in 82599 */
1005         dcb_config->support.capabilities = 0xFF;
1006
1007         /*we only support 4 Tcs for X540, X550 */
1008         if (hw->mac.type == ixgbe_mac_X540 ||
1009                 hw->mac.type == ixgbe_mac_X550 ||
1010                 hw->mac.type == ixgbe_mac_X550EM_x ||
1011                 hw->mac.type == ixgbe_mac_X550EM_a) {
1012                 dcb_config->num_tcs.pg_tcs = 4;
1013                 dcb_config->num_tcs.pfc_tcs = 4;
1014         }
1015 }
1016
1017 /*
1018  * Ensure that all locks are released before first NVM or PHY access
1019  */
1020 static void
1021 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1022 {
1023         uint16_t mask;
1024
1025         /*
1026          * Phy lock should not fail in this early stage. If this is the case,
1027          * it is due to an improper exit of the application.
1028          * So force the release of the faulty lock. Release of common lock
1029          * is done automatically by swfw_sync function.
1030          */
1031         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1032         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1033                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1034         }
1035         ixgbe_release_swfw_semaphore(hw, mask);
1036
1037         /*
1038          * These ones are more tricky since they are common to all ports; but
1039          * swfw_sync retries last long enough (1s) to be almost sure that if
1040          * lock can not be taken it is due to an improper lock of the
1041          * semaphore.
1042          */
1043         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1044         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1045                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1046         }
1047         ixgbe_release_swfw_semaphore(hw, mask);
1048 }
1049
1050 /*
1051  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1052  * It returns 0 on success.
1053  */
1054 static int
1055 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1056 {
1057         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1058         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1059         struct ixgbe_hw *hw =
1060                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1061         struct ixgbe_vfta *shadow_vfta =
1062                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1063         struct ixgbe_hwstrip *hwstrip =
1064                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1065         struct ixgbe_dcb_config *dcb_config =
1066                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1067         struct ixgbe_filter_info *filter_info =
1068                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1069         struct ixgbe_bw_conf *bw_conf =
1070                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1071         uint32_t ctrl_ext;
1072         uint16_t csum;
1073         int diag, i;
1074
1075         PMD_INIT_FUNC_TRACE();
1076
1077         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1078         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1079         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1080         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1081
1082         /*
1083          * For secondary processes, we don't initialise any further as primary
1084          * has already done this work. Only check we don't need a different
1085          * RX and TX function.
1086          */
1087         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1088                 struct ixgbe_tx_queue *txq;
1089                 /* TX queue function in primary, set by last queue initialized
1090                  * Tx queue may not initialized by primary process
1091                  */
1092                 if (eth_dev->data->tx_queues) {
1093                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1094                         ixgbe_set_tx_function(eth_dev, txq);
1095                 } else {
1096                         /* Use default TX function if we get here */
1097                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1098                                      "Using default TX function.");
1099                 }
1100
1101                 ixgbe_set_rx_function(eth_dev);
1102
1103                 return 0;
1104         }
1105
1106         rte_eth_copy_pci_info(eth_dev, pci_dev);
1107
1108         /* Vendor and Device ID need to be set before init of shared code */
1109         hw->device_id = pci_dev->id.device_id;
1110         hw->vendor_id = pci_dev->id.vendor_id;
1111         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1112         hw->allow_unsupported_sfp = 1;
1113
1114         /* Initialize the shared code (base driver) */
1115 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1116         diag = ixgbe_bypass_init_shared_code(hw);
1117 #else
1118         diag = ixgbe_init_shared_code(hw);
1119 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1120
1121         if (diag != IXGBE_SUCCESS) {
1122                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1123                 return -EIO;
1124         }
1125
1126         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1127                 PMD_INIT_LOG(ERR, "\nERROR: "
1128                         "Firmware recovery mode detected. Limiting functionality.\n"
1129                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1130                         "User Guide for details on firmware recovery mode.");
1131                 return -EIO;
1132         }
1133
1134         /* pick up the PCI bus settings for reporting later */
1135         ixgbe_get_bus_info(hw);
1136
1137         /* Unlock any pending hardware semaphore */
1138         ixgbe_swfw_lock_reset(hw);
1139
1140 #ifdef RTE_LIBRTE_SECURITY
1141         /* Initialize security_ctx only for primary process*/
1142         if (ixgbe_ipsec_ctx_create(eth_dev))
1143                 return -ENOMEM;
1144 #endif
1145
1146         /* Initialize DCB configuration*/
1147         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1148         ixgbe_dcb_init(hw, dcb_config);
1149         /* Get Hardware Flow Control setting */
1150         hw->fc.requested_mode = ixgbe_fc_full;
1151         hw->fc.current_mode = ixgbe_fc_full;
1152         hw->fc.pause_time = IXGBE_FC_PAUSE;
1153         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1154                 hw->fc.low_water[i] = IXGBE_FC_LO;
1155                 hw->fc.high_water[i] = IXGBE_FC_HI;
1156         }
1157         hw->fc.send_xon = 1;
1158
1159         /* Make sure we have a good EEPROM before we read from it */
1160         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1161         if (diag != IXGBE_SUCCESS) {
1162                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1163                 return -EIO;
1164         }
1165
1166 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1167         diag = ixgbe_bypass_init_hw(hw);
1168 #else
1169         diag = ixgbe_init_hw(hw);
1170 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1171
1172         /*
1173          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1174          * is called too soon after the kernel driver unbinding/binding occurs.
1175          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1176          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1177          * also called. See ixgbe_identify_phy_82599(). The reason for the
1178          * failure is not known, and only occuts when virtualisation features
1179          * are disabled in the bios. A delay of 100ms  was found to be enough by
1180          * trial-and-error, and is doubled to be safe.
1181          */
1182         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1183                 rte_delay_ms(200);
1184                 diag = ixgbe_init_hw(hw);
1185         }
1186
1187         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1188                 diag = IXGBE_SUCCESS;
1189
1190         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1191                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1192                              "LOM.  Please be aware there may be issues associated "
1193                              "with your hardware.");
1194                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1195                              "please contact your Intel or hardware representative "
1196                              "who provided you with this hardware.");
1197         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1198                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1199         if (diag) {
1200                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1201                 return -EIO;
1202         }
1203
1204         /* Reset the hw statistics */
1205         ixgbe_dev_stats_reset(eth_dev);
1206
1207         /* disable interrupt */
1208         ixgbe_disable_intr(hw);
1209
1210         /* reset mappings for queue statistics hw counters*/
1211         ixgbe_reset_qstat_mappings(hw);
1212
1213         /* Allocate memory for storing MAC addresses */
1214         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1215                                                hw->mac.num_rar_entries, 0);
1216         if (eth_dev->data->mac_addrs == NULL) {
1217                 PMD_INIT_LOG(ERR,
1218                              "Failed to allocate %u bytes needed to store "
1219                              "MAC addresses",
1220                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1221                 return -ENOMEM;
1222         }
1223         /* Copy the permanent MAC address */
1224         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1225                         &eth_dev->data->mac_addrs[0]);
1226
1227         /* Allocate memory for storing hash filter MAC addresses */
1228         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1229                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1230         if (eth_dev->data->hash_mac_addrs == NULL) {
1231                 PMD_INIT_LOG(ERR,
1232                              "Failed to allocate %d bytes needed to store MAC addresses",
1233                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1234                 return -ENOMEM;
1235         }
1236
1237         /* initialize the vfta */
1238         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1239
1240         /* initialize the hw strip bitmap*/
1241         memset(hwstrip, 0, sizeof(*hwstrip));
1242
1243         /* initialize PF if max_vfs not zero */
1244         ixgbe_pf_host_init(eth_dev);
1245
1246         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1247         /* let hardware know driver is loaded */
1248         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1249         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1250         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1251         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1252         IXGBE_WRITE_FLUSH(hw);
1253
1254         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1255                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1256                              (int) hw->mac.type, (int) hw->phy.type,
1257                              (int) hw->phy.sfp_type);
1258         else
1259                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1260                              (int) hw->mac.type, (int) hw->phy.type);
1261
1262         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1263                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1264                      pci_dev->id.device_id);
1265
1266         rte_intr_callback_register(intr_handle,
1267                                    ixgbe_dev_interrupt_handler, eth_dev);
1268
1269         /* enable uio/vfio intr/eventfd mapping */
1270         rte_intr_enable(intr_handle);
1271
1272         /* enable support intr */
1273         ixgbe_enable_intr(eth_dev);
1274
1275         /* initialize filter info */
1276         memset(filter_info, 0,
1277                sizeof(struct ixgbe_filter_info));
1278
1279         /* initialize 5tuple filter list */
1280         TAILQ_INIT(&filter_info->fivetuple_list);
1281
1282         /* initialize flow director filter list & hash */
1283         ixgbe_fdir_filter_init(eth_dev);
1284
1285         /* initialize l2 tunnel filter list & hash */
1286         ixgbe_l2_tn_filter_init(eth_dev);
1287
1288         /* initialize flow filter lists */
1289         ixgbe_filterlist_init();
1290
1291         /* initialize bandwidth configuration info */
1292         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1293
1294         /* initialize Traffic Manager configuration */
1295         ixgbe_tm_conf_init(eth_dev);
1296
1297         return 0;
1298 }
1299
1300 static int
1301 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1302 {
1303         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1304         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1305         struct ixgbe_hw *hw;
1306         int retries = 0;
1307         int ret;
1308
1309         PMD_INIT_FUNC_TRACE();
1310
1311         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1312                 return 0;
1313
1314         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1315
1316         if (hw->adapter_stopped == 0)
1317                 ixgbe_dev_close(eth_dev);
1318
1319         eth_dev->dev_ops = NULL;
1320         eth_dev->rx_pkt_burst = NULL;
1321         eth_dev->tx_pkt_burst = NULL;
1322
1323         /* Unlock any pending hardware semaphore */
1324         ixgbe_swfw_lock_reset(hw);
1325
1326         /* disable uio intr before callback unregister */
1327         rte_intr_disable(intr_handle);
1328
1329         do {
1330                 ret = rte_intr_callback_unregister(intr_handle,
1331                                 ixgbe_dev_interrupt_handler, eth_dev);
1332                 if (ret >= 0) {
1333                         break;
1334                 } else if (ret != -EAGAIN) {
1335                         PMD_INIT_LOG(ERR,
1336                                 "intr callback unregister failed: %d",
1337                                 ret);
1338                         return ret;
1339                 }
1340                 rte_delay_ms(100);
1341         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1342
1343         /* cancel the delay handler before remove dev */
1344         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1345
1346         /* uninitialize PF if max_vfs not zero */
1347         ixgbe_pf_host_uninit(eth_dev);
1348
1349         /* remove all the fdir filters & hash */
1350         ixgbe_fdir_filter_uninit(eth_dev);
1351
1352         /* remove all the L2 tunnel filters & hash */
1353         ixgbe_l2_tn_filter_uninit(eth_dev);
1354
1355         /* Remove all ntuple filters of the device */
1356         ixgbe_ntuple_filter_uninit(eth_dev);
1357
1358         /* clear all the filters list */
1359         ixgbe_filterlist_flush();
1360
1361         /* Remove all Traffic Manager configuration */
1362         ixgbe_tm_conf_uninit(eth_dev);
1363
1364 #ifdef RTE_LIBRTE_SECURITY
1365         rte_free(eth_dev->security_ctx);
1366 #endif
1367
1368         return 0;
1369 }
1370
1371 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1372 {
1373         struct ixgbe_filter_info *filter_info =
1374                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1375         struct ixgbe_5tuple_filter *p_5tuple;
1376
1377         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1378                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1379                              p_5tuple,
1380                              entries);
1381                 rte_free(p_5tuple);
1382         }
1383         memset(filter_info->fivetuple_mask, 0,
1384                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1385
1386         return 0;
1387 }
1388
1389 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1390 {
1391         struct ixgbe_hw_fdir_info *fdir_info =
1392                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1393         struct ixgbe_fdir_filter *fdir_filter;
1394
1395                 if (fdir_info->hash_map)
1396                 rte_free(fdir_info->hash_map);
1397         if (fdir_info->hash_handle)
1398                 rte_hash_free(fdir_info->hash_handle);
1399
1400         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1401                 TAILQ_REMOVE(&fdir_info->fdir_list,
1402                              fdir_filter,
1403                              entries);
1404                 rte_free(fdir_filter);
1405         }
1406
1407         return 0;
1408 }
1409
1410 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1411 {
1412         struct ixgbe_l2_tn_info *l2_tn_info =
1413                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1414         struct ixgbe_l2_tn_filter *l2_tn_filter;
1415
1416         if (l2_tn_info->hash_map)
1417                 rte_free(l2_tn_info->hash_map);
1418         if (l2_tn_info->hash_handle)
1419                 rte_hash_free(l2_tn_info->hash_handle);
1420
1421         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1422                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1423                              l2_tn_filter,
1424                              entries);
1425                 rte_free(l2_tn_filter);
1426         }
1427
1428         return 0;
1429 }
1430
1431 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1432 {
1433         struct ixgbe_hw_fdir_info *fdir_info =
1434                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1435         char fdir_hash_name[RTE_HASH_NAMESIZE];
1436         struct rte_hash_parameters fdir_hash_params = {
1437                 .name = fdir_hash_name,
1438                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1439                 .key_len = sizeof(union ixgbe_atr_input),
1440                 .hash_func = rte_hash_crc,
1441                 .hash_func_init_val = 0,
1442                 .socket_id = rte_socket_id(),
1443         };
1444
1445         TAILQ_INIT(&fdir_info->fdir_list);
1446         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1447                  "fdir_%s", eth_dev->device->name);
1448         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1449         if (!fdir_info->hash_handle) {
1450                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1451                 return -EINVAL;
1452         }
1453         fdir_info->hash_map = rte_zmalloc("ixgbe",
1454                                           sizeof(struct ixgbe_fdir_filter *) *
1455                                           IXGBE_MAX_FDIR_FILTER_NUM,
1456                                           0);
1457         if (!fdir_info->hash_map) {
1458                 PMD_INIT_LOG(ERR,
1459                              "Failed to allocate memory for fdir hash map!");
1460                 return -ENOMEM;
1461         }
1462         fdir_info->mask_added = FALSE;
1463
1464         return 0;
1465 }
1466
1467 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1468 {
1469         struct ixgbe_l2_tn_info *l2_tn_info =
1470                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1471         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1472         struct rte_hash_parameters l2_tn_hash_params = {
1473                 .name = l2_tn_hash_name,
1474                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1475                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1476                 .hash_func = rte_hash_crc,
1477                 .hash_func_init_val = 0,
1478                 .socket_id = rte_socket_id(),
1479         };
1480
1481         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1482         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1483                  "l2_tn_%s", eth_dev->device->name);
1484         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1485         if (!l2_tn_info->hash_handle) {
1486                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1487                 return -EINVAL;
1488         }
1489         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1490                                    sizeof(struct ixgbe_l2_tn_filter *) *
1491                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1492                                    0);
1493         if (!l2_tn_info->hash_map) {
1494                 PMD_INIT_LOG(ERR,
1495                         "Failed to allocate memory for L2 TN hash map!");
1496                 return -ENOMEM;
1497         }
1498         l2_tn_info->e_tag_en = FALSE;
1499         l2_tn_info->e_tag_fwd_en = FALSE;
1500         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1501
1502         return 0;
1503 }
1504 /*
1505  * Negotiate mailbox API version with the PF.
1506  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1507  * Then we try to negotiate starting with the most recent one.
1508  * If all negotiation attempts fail, then we will proceed with
1509  * the default one (ixgbe_mbox_api_10).
1510  */
1511 static void
1512 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1513 {
1514         int32_t i;
1515
1516         /* start with highest supported, proceed down */
1517         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1518                 ixgbe_mbox_api_13,
1519                 ixgbe_mbox_api_12,
1520                 ixgbe_mbox_api_11,
1521                 ixgbe_mbox_api_10,
1522         };
1523
1524         for (i = 0;
1525                         i != RTE_DIM(sup_ver) &&
1526                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1527                         i++)
1528                 ;
1529 }
1530
1531 static void
1532 generate_random_mac_addr(struct ether_addr *mac_addr)
1533 {
1534         uint64_t random;
1535
1536         /* Set Organizationally Unique Identifier (OUI) prefix. */
1537         mac_addr->addr_bytes[0] = 0x00;
1538         mac_addr->addr_bytes[1] = 0x09;
1539         mac_addr->addr_bytes[2] = 0xC0;
1540         /* Force indication of locally assigned MAC address. */
1541         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1542         /* Generate the last 3 bytes of the MAC address with a random number. */
1543         random = rte_rand();
1544         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1545 }
1546
1547 /*
1548  * Virtual Function device init
1549  */
1550 static int
1551 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1552 {
1553         int diag;
1554         uint32_t tc, tcs;
1555         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1556         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1557         struct ixgbe_hw *hw =
1558                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1559         struct ixgbe_vfta *shadow_vfta =
1560                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1561         struct ixgbe_hwstrip *hwstrip =
1562                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1563         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1564
1565         PMD_INIT_FUNC_TRACE();
1566
1567         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1568         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1569         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1570
1571         /* for secondary processes, we don't initialise any further as primary
1572          * has already done this work. Only check we don't need a different
1573          * RX function
1574          */
1575         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1576                 struct ixgbe_tx_queue *txq;
1577                 /* TX queue function in primary, set by last queue initialized
1578                  * Tx queue may not initialized by primary process
1579                  */
1580                 if (eth_dev->data->tx_queues) {
1581                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1582                         ixgbe_set_tx_function(eth_dev, txq);
1583                 } else {
1584                         /* Use default TX function if we get here */
1585                         PMD_INIT_LOG(NOTICE,
1586                                      "No TX queues configured yet. Using default TX function.");
1587                 }
1588
1589                 ixgbe_set_rx_function(eth_dev);
1590
1591                 return 0;
1592         }
1593
1594         rte_eth_copy_pci_info(eth_dev, pci_dev);
1595
1596         hw->device_id = pci_dev->id.device_id;
1597         hw->vendor_id = pci_dev->id.vendor_id;
1598         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1599
1600         /* initialize the vfta */
1601         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1602
1603         /* initialize the hw strip bitmap*/
1604         memset(hwstrip, 0, sizeof(*hwstrip));
1605
1606         /* Initialize the shared code (base driver) */
1607         diag = ixgbe_init_shared_code(hw);
1608         if (diag != IXGBE_SUCCESS) {
1609                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1610                 return -EIO;
1611         }
1612
1613         /* init_mailbox_params */
1614         hw->mbx.ops.init_params(hw);
1615
1616         /* Reset the hw statistics */
1617         ixgbevf_dev_stats_reset(eth_dev);
1618
1619         /* Disable the interrupts for VF */
1620         ixgbevf_intr_disable(eth_dev);
1621
1622         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1623         diag = hw->mac.ops.reset_hw(hw);
1624
1625         /*
1626          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1627          * the underlying PF driver has not assigned a MAC address to the VF.
1628          * In this case, assign a random MAC address.
1629          */
1630         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1631                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1632                 /*
1633                  * This error code will be propagated to the app by
1634                  * rte_eth_dev_reset, so use a public error code rather than
1635                  * the internal-only IXGBE_ERR_RESET_FAILED
1636                  */
1637                 return -EAGAIN;
1638         }
1639
1640         /* negotiate mailbox API version to use with the PF. */
1641         ixgbevf_negotiate_api(hw);
1642
1643         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1644         ixgbevf_get_queues(hw, &tcs, &tc);
1645
1646         /* Allocate memory for storing MAC addresses */
1647         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1648                                                hw->mac.num_rar_entries, 0);
1649         if (eth_dev->data->mac_addrs == NULL) {
1650                 PMD_INIT_LOG(ERR,
1651                              "Failed to allocate %u bytes needed to store "
1652                              "MAC addresses",
1653                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1654                 return -ENOMEM;
1655         }
1656
1657         /* Generate a random MAC address, if none was assigned by PF. */
1658         if (is_zero_ether_addr(perm_addr)) {
1659                 generate_random_mac_addr(perm_addr);
1660                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1661                 if (diag) {
1662                         rte_free(eth_dev->data->mac_addrs);
1663                         eth_dev->data->mac_addrs = NULL;
1664                         return diag;
1665                 }
1666                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1667                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1668                              "%02x:%02x:%02x:%02x:%02x:%02x",
1669                              perm_addr->addr_bytes[0],
1670                              perm_addr->addr_bytes[1],
1671                              perm_addr->addr_bytes[2],
1672                              perm_addr->addr_bytes[3],
1673                              perm_addr->addr_bytes[4],
1674                              perm_addr->addr_bytes[5]);
1675         }
1676
1677         /* Copy the permanent MAC address */
1678         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1679
1680         /* reset the hardware with the new settings */
1681         diag = hw->mac.ops.start_hw(hw);
1682         switch (diag) {
1683         case  0:
1684                 break;
1685
1686         default:
1687                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1688                 return -EIO;
1689         }
1690
1691         rte_intr_callback_register(intr_handle,
1692                                    ixgbevf_dev_interrupt_handler, eth_dev);
1693         rte_intr_enable(intr_handle);
1694         ixgbevf_intr_enable(eth_dev);
1695
1696         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1697                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1698                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1699
1700         return 0;
1701 }
1702
1703 /* Virtual Function device uninit */
1704
1705 static int
1706 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1707 {
1708         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1709         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1710         struct ixgbe_hw *hw;
1711
1712         PMD_INIT_FUNC_TRACE();
1713
1714         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1715                 return 0;
1716
1717         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1718
1719         if (hw->adapter_stopped == 0)
1720                 ixgbevf_dev_close(eth_dev);
1721
1722         eth_dev->dev_ops = NULL;
1723         eth_dev->rx_pkt_burst = NULL;
1724         eth_dev->tx_pkt_burst = NULL;
1725
1726         /* Disable the interrupts for VF */
1727         ixgbevf_intr_disable(eth_dev);
1728
1729         rte_intr_disable(intr_handle);
1730         rte_intr_callback_unregister(intr_handle,
1731                                      ixgbevf_dev_interrupt_handler, eth_dev);
1732
1733         return 0;
1734 }
1735
1736 static int
1737 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1738                 struct rte_pci_device *pci_dev)
1739 {
1740         char name[RTE_ETH_NAME_MAX_LEN];
1741         struct rte_eth_dev *pf_ethdev;
1742         struct rte_eth_devargs eth_da;
1743         int i, retval;
1744
1745         if (pci_dev->device.devargs) {
1746                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1747                                 &eth_da);
1748                 if (retval)
1749                         return retval;
1750         } else
1751                 memset(&eth_da, 0, sizeof(eth_da));
1752
1753         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1754                 sizeof(struct ixgbe_adapter),
1755                 eth_dev_pci_specific_init, pci_dev,
1756                 eth_ixgbe_dev_init, NULL);
1757
1758         if (retval || eth_da.nb_representor_ports < 1)
1759                 return retval;
1760
1761         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1762         if (pf_ethdev == NULL)
1763                 return -ENODEV;
1764
1765         /* probe VF representor ports */
1766         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1767                 struct ixgbe_vf_info *vfinfo;
1768                 struct ixgbe_vf_representor representor;
1769
1770                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1771                         pf_ethdev->data->dev_private);
1772                 if (vfinfo == NULL) {
1773                         PMD_DRV_LOG(ERR,
1774                                 "no virtual functions supported by PF");
1775                         break;
1776                 }
1777
1778                 representor.vf_id = eth_da.representor_ports[i];
1779                 representor.switch_domain_id = vfinfo->switch_domain_id;
1780                 representor.pf_ethdev = pf_ethdev;
1781
1782                 /* representor port net_bdf_port */
1783                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1784                         pci_dev->device.name,
1785                         eth_da.representor_ports[i]);
1786
1787                 retval = rte_eth_dev_create(&pci_dev->device, name,
1788                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1789                         ixgbe_vf_representor_init, &representor);
1790
1791                 if (retval)
1792                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1793                                 "representor %s.", name);
1794         }
1795
1796         return 0;
1797 }
1798
1799 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1800 {
1801         struct rte_eth_dev *ethdev;
1802
1803         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1804         if (!ethdev)
1805                 return -ENODEV;
1806
1807         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1808                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1809         else
1810                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1811 }
1812
1813 static struct rte_pci_driver rte_ixgbe_pmd = {
1814         .id_table = pci_id_ixgbe_map,
1815         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1816                      RTE_PCI_DRV_IOVA_AS_VA,
1817         .probe = eth_ixgbe_pci_probe,
1818         .remove = eth_ixgbe_pci_remove,
1819 };
1820
1821 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1822         struct rte_pci_device *pci_dev)
1823 {
1824         return rte_eth_dev_pci_generic_probe(pci_dev,
1825                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1826 }
1827
1828 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1829 {
1830         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1831 }
1832
1833 /*
1834  * virtual function driver struct
1835  */
1836 static struct rte_pci_driver rte_ixgbevf_pmd = {
1837         .id_table = pci_id_ixgbevf_map,
1838         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1839         .probe = eth_ixgbevf_pci_probe,
1840         .remove = eth_ixgbevf_pci_remove,
1841 };
1842
1843 static int
1844 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1845 {
1846         struct ixgbe_hw *hw =
1847                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848         struct ixgbe_vfta *shadow_vfta =
1849                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1850         uint32_t vfta;
1851         uint32_t vid_idx;
1852         uint32_t vid_bit;
1853
1854         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1855         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1856         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1857         if (on)
1858                 vfta |= vid_bit;
1859         else
1860                 vfta &= ~vid_bit;
1861         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1862
1863         /* update local VFTA copy */
1864         shadow_vfta->vfta[vid_idx] = vfta;
1865
1866         return 0;
1867 }
1868
1869 static void
1870 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1871 {
1872         if (on)
1873                 ixgbe_vlan_hw_strip_enable(dev, queue);
1874         else
1875                 ixgbe_vlan_hw_strip_disable(dev, queue);
1876 }
1877
1878 static int
1879 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1880                     enum rte_vlan_type vlan_type,
1881                     uint16_t tpid)
1882 {
1883         struct ixgbe_hw *hw =
1884                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1885         int ret = 0;
1886         uint32_t reg;
1887         uint32_t qinq;
1888
1889         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1890         qinq &= IXGBE_DMATXCTL_GDV;
1891
1892         switch (vlan_type) {
1893         case ETH_VLAN_TYPE_INNER:
1894                 if (qinq) {
1895                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1896                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1897                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1898                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1899                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1900                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1901                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1902                 } else {
1903                         ret = -ENOTSUP;
1904                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1905                                     " by single VLAN");
1906                 }
1907                 break;
1908         case ETH_VLAN_TYPE_OUTER:
1909                 if (qinq) {
1910                         /* Only the high 16-bits is valid */
1911                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1912                                         IXGBE_EXVET_VET_EXT_SHIFT);
1913                 } else {
1914                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1915                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1916                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1917                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1918                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1919                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1920                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1921                 }
1922
1923                 break;
1924         default:
1925                 ret = -EINVAL;
1926                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1927                 break;
1928         }
1929
1930         return ret;
1931 }
1932
1933 void
1934 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_hw *hw =
1937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         uint32_t vlnctrl;
1939
1940         PMD_INIT_FUNC_TRACE();
1941
1942         /* Filter Table Disable */
1943         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1944         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1945
1946         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1947 }
1948
1949 void
1950 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1951 {
1952         struct ixgbe_hw *hw =
1953                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1954         struct ixgbe_vfta *shadow_vfta =
1955                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1956         uint32_t vlnctrl;
1957         uint16_t i;
1958
1959         PMD_INIT_FUNC_TRACE();
1960
1961         /* Filter Table Enable */
1962         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1963         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1964         vlnctrl |= IXGBE_VLNCTRL_VFE;
1965
1966         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1967
1968         /* write whatever is in local vfta copy */
1969         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1970                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1971 }
1972
1973 static void
1974 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1975 {
1976         struct ixgbe_hwstrip *hwstrip =
1977                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1978         struct ixgbe_rx_queue *rxq;
1979
1980         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1981                 return;
1982
1983         if (on)
1984                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1985         else
1986                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1987
1988         if (queue >= dev->data->nb_rx_queues)
1989                 return;
1990
1991         rxq = dev->data->rx_queues[queue];
1992
1993         if (on) {
1994                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1995                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1996         } else {
1997                 rxq->vlan_flags = PKT_RX_VLAN;
1998                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1999         }
2000 }
2001
2002 static void
2003 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2004 {
2005         struct ixgbe_hw *hw =
2006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2007         uint32_t ctrl;
2008
2009         PMD_INIT_FUNC_TRACE();
2010
2011         if (hw->mac.type == ixgbe_mac_82598EB) {
2012                 /* No queue level support */
2013                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2014                 return;
2015         }
2016
2017         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2018         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2019         ctrl &= ~IXGBE_RXDCTL_VME;
2020         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2021
2022         /* record those setting for HW strip per queue */
2023         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2024 }
2025
2026 static void
2027 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2028 {
2029         struct ixgbe_hw *hw =
2030                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031         uint32_t ctrl;
2032
2033         PMD_INIT_FUNC_TRACE();
2034
2035         if (hw->mac.type == ixgbe_mac_82598EB) {
2036                 /* No queue level supported */
2037                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2038                 return;
2039         }
2040
2041         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2042         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2043         ctrl |= IXGBE_RXDCTL_VME;
2044         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2045
2046         /* record those setting for HW strip per queue */
2047         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2048 }
2049
2050 static void
2051 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2052 {
2053         struct ixgbe_hw *hw =
2054                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         uint32_t ctrl;
2056
2057         PMD_INIT_FUNC_TRACE();
2058
2059         /* DMATXCTRL: Geric Double VLAN Disable */
2060         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2061         ctrl &= ~IXGBE_DMATXCTL_GDV;
2062         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2063
2064         /* CTRL_EXT: Global Double VLAN Disable */
2065         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2066         ctrl &= ~IXGBE_EXTENDED_VLAN;
2067         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2068
2069 }
2070
2071 static void
2072 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2073 {
2074         struct ixgbe_hw *hw =
2075                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2076         uint32_t ctrl;
2077
2078         PMD_INIT_FUNC_TRACE();
2079
2080         /* DMATXCTRL: Geric Double VLAN Enable */
2081         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2082         ctrl |= IXGBE_DMATXCTL_GDV;
2083         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2084
2085         /* CTRL_EXT: Global Double VLAN Enable */
2086         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2087         ctrl |= IXGBE_EXTENDED_VLAN;
2088         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2089
2090         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2091         if (hw->mac.type == ixgbe_mac_X550 ||
2092             hw->mac.type == ixgbe_mac_X550EM_x ||
2093             hw->mac.type == ixgbe_mac_X550EM_a) {
2094                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2095                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2096                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2097         }
2098
2099         /*
2100          * VET EXT field in the EXVET register = 0x8100 by default
2101          * So no need to change. Same to VT field of DMATXCTL register
2102          */
2103 }
2104
2105 void
2106 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2107 {
2108         struct ixgbe_hw *hw =
2109                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2111         uint32_t ctrl;
2112         uint16_t i;
2113         struct ixgbe_rx_queue *rxq;
2114         bool on;
2115
2116         PMD_INIT_FUNC_TRACE();
2117
2118         if (hw->mac.type == ixgbe_mac_82598EB) {
2119                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2120                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2121                         ctrl |= IXGBE_VLNCTRL_VME;
2122                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2123                 } else {
2124                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2125                         ctrl &= ~IXGBE_VLNCTRL_VME;
2126                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2127                 }
2128         } else {
2129                 /*
2130                  * Other 10G NIC, the VLAN strip can be setup
2131                  * per queue in RXDCTL
2132                  */
2133                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2134                         rxq = dev->data->rx_queues[i];
2135                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2136                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2137                                 ctrl |= IXGBE_RXDCTL_VME;
2138                                 on = TRUE;
2139                         } else {
2140                                 ctrl &= ~IXGBE_RXDCTL_VME;
2141                                 on = FALSE;
2142                         }
2143                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2144
2145                         /* record those setting for HW strip per queue */
2146                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2147                 }
2148         }
2149 }
2150
2151 static void
2152 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2153 {
2154         uint16_t i;
2155         struct rte_eth_rxmode *rxmode;
2156         struct ixgbe_rx_queue *rxq;
2157
2158         if (mask & ETH_VLAN_STRIP_MASK) {
2159                 rxmode = &dev->data->dev_conf.rxmode;
2160                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2161                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2162                                 rxq = dev->data->rx_queues[i];
2163                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2164                         }
2165                 else
2166                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2167                                 rxq = dev->data->rx_queues[i];
2168                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2169                         }
2170         }
2171 }
2172
2173 static int
2174 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2175 {
2176         struct rte_eth_rxmode *rxmode;
2177         rxmode = &dev->data->dev_conf.rxmode;
2178
2179         if (mask & ETH_VLAN_STRIP_MASK) {
2180                 ixgbe_vlan_hw_strip_config(dev);
2181         }
2182
2183         if (mask & ETH_VLAN_FILTER_MASK) {
2184                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2185                         ixgbe_vlan_hw_filter_enable(dev);
2186                 else
2187                         ixgbe_vlan_hw_filter_disable(dev);
2188         }
2189
2190         if (mask & ETH_VLAN_EXTEND_MASK) {
2191                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2192                         ixgbe_vlan_hw_extend_enable(dev);
2193                 else
2194                         ixgbe_vlan_hw_extend_disable(dev);
2195         }
2196
2197         return 0;
2198 }
2199
2200 static int
2201 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2202 {
2203         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2204
2205         ixgbe_vlan_offload_config(dev, mask);
2206
2207         return 0;
2208 }
2209
2210 static void
2211 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2212 {
2213         struct ixgbe_hw *hw =
2214                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2215         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2216         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2217
2218         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2219         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2220 }
2221
2222 static int
2223 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2224 {
2225         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2226
2227         switch (nb_rx_q) {
2228         case 1:
2229         case 2:
2230                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2231                 break;
2232         case 4:
2233                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2234                 break;
2235         default:
2236                 return -EINVAL;
2237         }
2238
2239         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2240                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2241         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2242                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2243         return 0;
2244 }
2245
2246 static int
2247 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2248 {
2249         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2250         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2251         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2252         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2253
2254         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2255                 /* check multi-queue mode */
2256                 switch (dev_conf->rxmode.mq_mode) {
2257                 case ETH_MQ_RX_VMDQ_DCB:
2258                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2259                         break;
2260                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2261                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2262                         PMD_INIT_LOG(ERR, "SRIOV active,"
2263                                         " unsupported mq_mode rx %d.",
2264                                         dev_conf->rxmode.mq_mode);
2265                         return -EINVAL;
2266                 case ETH_MQ_RX_RSS:
2267                 case ETH_MQ_RX_VMDQ_RSS:
2268                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2269                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2270                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2271                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2272                                                 " invalid queue number"
2273                                                 " for VMDQ RSS, allowed"
2274                                                 " value are 1, 2 or 4.");
2275                                         return -EINVAL;
2276                                 }
2277                         break;
2278                 case ETH_MQ_RX_VMDQ_ONLY:
2279                 case ETH_MQ_RX_NONE:
2280                         /* if nothing mq mode configure, use default scheme */
2281                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2282                         break;
2283                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2284                         /* SRIOV only works in VMDq enable mode */
2285                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2286                                         " wrong mq_mode rx %d.",
2287                                         dev_conf->rxmode.mq_mode);
2288                         return -EINVAL;
2289                 }
2290
2291                 switch (dev_conf->txmode.mq_mode) {
2292                 case ETH_MQ_TX_VMDQ_DCB:
2293                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2294                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2295                         break;
2296                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2297                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2298                         break;
2299                 }
2300
2301                 /* check valid queue number */
2302                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2303                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2304                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2305                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2306                                         " must be less than or equal to %d.",
2307                                         nb_rx_q, nb_tx_q,
2308                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2309                         return -EINVAL;
2310                 }
2311         } else {
2312                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2313                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2314                                           " not supported.");
2315                         return -EINVAL;
2316                 }
2317                 /* check configuration for vmdb+dcb mode */
2318                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2319                         const struct rte_eth_vmdq_dcb_conf *conf;
2320
2321                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2322                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2323                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2324                                 return -EINVAL;
2325                         }
2326                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2327                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2328                                conf->nb_queue_pools == ETH_32_POOLS)) {
2329                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2330                                                 " nb_queue_pools must be %d or %d.",
2331                                                 ETH_16_POOLS, ETH_32_POOLS);
2332                                 return -EINVAL;
2333                         }
2334                 }
2335                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2336                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2337
2338                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2339                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2340                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2341                                 return -EINVAL;
2342                         }
2343                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2344                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2345                                conf->nb_queue_pools == ETH_32_POOLS)) {
2346                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2347                                                 " nb_queue_pools != %d and"
2348                                                 " nb_queue_pools != %d.",
2349                                                 ETH_16_POOLS, ETH_32_POOLS);
2350                                 return -EINVAL;
2351                         }
2352                 }
2353
2354                 /* For DCB mode check our configuration before we go further */
2355                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2356                         const struct rte_eth_dcb_rx_conf *conf;
2357
2358                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2359                         if (!(conf->nb_tcs == ETH_4_TCS ||
2360                                conf->nb_tcs == ETH_8_TCS)) {
2361                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2362                                                 " and nb_tcs != %d.",
2363                                                 ETH_4_TCS, ETH_8_TCS);
2364                                 return -EINVAL;
2365                         }
2366                 }
2367
2368                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2369                         const struct rte_eth_dcb_tx_conf *conf;
2370
2371                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2372                         if (!(conf->nb_tcs == ETH_4_TCS ||
2373                                conf->nb_tcs == ETH_8_TCS)) {
2374                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2375                                                 " and nb_tcs != %d.",
2376                                                 ETH_4_TCS, ETH_8_TCS);
2377                                 return -EINVAL;
2378                         }
2379                 }
2380
2381                 /*
2382                  * When DCB/VT is off, maximum number of queues changes,
2383                  * except for 82598EB, which remains constant.
2384                  */
2385                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2386                                 hw->mac.type != ixgbe_mac_82598EB) {
2387                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2388                                 PMD_INIT_LOG(ERR,
2389                                              "Neither VT nor DCB are enabled, "
2390                                              "nb_tx_q > %d.",
2391                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2392                                 return -EINVAL;
2393                         }
2394                 }
2395         }
2396         return 0;
2397 }
2398
2399 static int
2400 ixgbe_dev_configure(struct rte_eth_dev *dev)
2401 {
2402         struct ixgbe_interrupt *intr =
2403                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2404         struct ixgbe_adapter *adapter =
2405                 (struct ixgbe_adapter *)dev->data->dev_private;
2406         int ret;
2407
2408         PMD_INIT_FUNC_TRACE();
2409         /* multipe queue mode checking */
2410         ret  = ixgbe_check_mq_mode(dev);
2411         if (ret != 0) {
2412                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2413                             ret);
2414                 return ret;
2415         }
2416
2417         /* set flag to update link status after init */
2418         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2419
2420         /*
2421          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2422          * allocation or vector Rx preconditions we will reset it.
2423          */
2424         adapter->rx_bulk_alloc_allowed = true;
2425         adapter->rx_vec_allowed = true;
2426
2427         return 0;
2428 }
2429
2430 static void
2431 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2432 {
2433         struct ixgbe_hw *hw =
2434                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         struct ixgbe_interrupt *intr =
2436                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2437         uint32_t gpie;
2438
2439         /* only set up it on X550EM_X */
2440         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2441                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2442                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2443                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2444                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2445                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2446         }
2447 }
2448
2449 int
2450 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2451                         uint16_t tx_rate, uint64_t q_msk)
2452 {
2453         struct ixgbe_hw *hw;
2454         struct ixgbe_vf_info *vfinfo;
2455         struct rte_eth_link link;
2456         uint8_t  nb_q_per_pool;
2457         uint32_t queue_stride;
2458         uint32_t queue_idx, idx = 0, vf_idx;
2459         uint32_t queue_end;
2460         uint16_t total_rate = 0;
2461         struct rte_pci_device *pci_dev;
2462
2463         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2464         rte_eth_link_get_nowait(dev->data->port_id, &link);
2465
2466         if (vf >= pci_dev->max_vfs)
2467                 return -EINVAL;
2468
2469         if (tx_rate > link.link_speed)
2470                 return -EINVAL;
2471
2472         if (q_msk == 0)
2473                 return 0;
2474
2475         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2477         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2478         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2479         queue_idx = vf * queue_stride;
2480         queue_end = queue_idx + nb_q_per_pool - 1;
2481         if (queue_end >= hw->mac.max_tx_queues)
2482                 return -EINVAL;
2483
2484         if (vfinfo) {
2485                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2486                         if (vf_idx == vf)
2487                                 continue;
2488                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2489                                 idx++)
2490                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2491                 }
2492         } else {
2493                 return -EINVAL;
2494         }
2495
2496         /* Store tx_rate for this vf. */
2497         for (idx = 0; idx < nb_q_per_pool; idx++) {
2498                 if (((uint64_t)0x1 << idx) & q_msk) {
2499                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2500                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2501                         total_rate += tx_rate;
2502                 }
2503         }
2504
2505         if (total_rate > dev->data->dev_link.link_speed) {
2506                 /* Reset stored TX rate of the VF if it causes exceed
2507                  * link speed.
2508                  */
2509                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2510                 return -EINVAL;
2511         }
2512
2513         /* Set RTTBCNRC of each queue/pool for vf X  */
2514         for (; queue_idx <= queue_end; queue_idx++) {
2515                 if (0x1 & q_msk)
2516                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2517                 q_msk = q_msk >> 1;
2518         }
2519
2520         return 0;
2521 }
2522
2523 /*
2524  * Configure device link speed and setup link.
2525  * It returns 0 on success.
2526  */
2527 static int
2528 ixgbe_dev_start(struct rte_eth_dev *dev)
2529 {
2530         struct ixgbe_hw *hw =
2531                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2532         struct ixgbe_vf_info *vfinfo =
2533                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2534         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2535         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2536         uint32_t intr_vector = 0;
2537         int err, link_up = 0, negotiate = 0;
2538         uint32_t speed = 0;
2539         uint32_t allowed_speeds = 0;
2540         int mask = 0;
2541         int status;
2542         uint16_t vf, idx;
2543         uint32_t *link_speeds;
2544         struct ixgbe_tm_conf *tm_conf =
2545                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2546
2547         PMD_INIT_FUNC_TRACE();
2548
2549         /* IXGBE devices don't support:
2550         *    - half duplex (checked afterwards for valid speeds)
2551         *    - fixed speed: TODO implement
2552         */
2553         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2554                 PMD_INIT_LOG(ERR,
2555                 "Invalid link_speeds for port %u, fix speed not supported",
2556                                 dev->data->port_id);
2557                 return -EINVAL;
2558         }
2559
2560         /* Stop the link setup handler before resetting the HW. */
2561         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2562
2563         /* disable uio/vfio intr/eventfd mapping */
2564         rte_intr_disable(intr_handle);
2565
2566         /* stop adapter */
2567         hw->adapter_stopped = 0;
2568         ixgbe_stop_adapter(hw);
2569
2570         /* reinitialize adapter
2571          * this calls reset and start
2572          */
2573         status = ixgbe_pf_reset_hw(hw);
2574         if (status != 0)
2575                 return -1;
2576         hw->mac.ops.start_hw(hw);
2577         hw->mac.get_link_status = true;
2578
2579         /* configure PF module if SRIOV enabled */
2580         ixgbe_pf_host_configure(dev);
2581
2582         ixgbe_dev_phy_intr_setup(dev);
2583
2584         /* check and configure queue intr-vector mapping */
2585         if ((rte_intr_cap_multiple(intr_handle) ||
2586              !RTE_ETH_DEV_SRIOV(dev).active) &&
2587             dev->data->dev_conf.intr_conf.rxq != 0) {
2588                 intr_vector = dev->data->nb_rx_queues;
2589                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2590                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2591                                         IXGBE_MAX_INTR_QUEUE_NUM);
2592                         return -ENOTSUP;
2593                 }
2594                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2595                         return -1;
2596         }
2597
2598         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2599                 intr_handle->intr_vec =
2600                         rte_zmalloc("intr_vec",
2601                                     dev->data->nb_rx_queues * sizeof(int), 0);
2602                 if (intr_handle->intr_vec == NULL) {
2603                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2604                                      " intr_vec", dev->data->nb_rx_queues);
2605                         return -ENOMEM;
2606                 }
2607         }
2608
2609         /* confiugre msix for sleep until rx interrupt */
2610         ixgbe_configure_msix(dev);
2611
2612         /* initialize transmission unit */
2613         ixgbe_dev_tx_init(dev);
2614
2615         /* This can fail when allocating mbufs for descriptor rings */
2616         err = ixgbe_dev_rx_init(dev);
2617         if (err) {
2618                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2619                 goto error;
2620         }
2621
2622         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2623                 ETH_VLAN_EXTEND_MASK;
2624         err = ixgbe_vlan_offload_config(dev, mask);
2625         if (err) {
2626                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2627                 goto error;
2628         }
2629
2630         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2631                 /* Enable vlan filtering for VMDq */
2632                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2633         }
2634
2635         /* Configure DCB hw */
2636         ixgbe_configure_dcb(dev);
2637
2638         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2639                 err = ixgbe_fdir_configure(dev);
2640                 if (err)
2641                         goto error;
2642         }
2643
2644         /* Restore vf rate limit */
2645         if (vfinfo != NULL) {
2646                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2647                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2648                                 if (vfinfo[vf].tx_rate[idx] != 0)
2649                                         ixgbe_set_vf_rate_limit(
2650                                                 dev, vf,
2651                                                 vfinfo[vf].tx_rate[idx],
2652                                                 1 << idx);
2653         }
2654
2655         ixgbe_restore_statistics_mapping(dev);
2656
2657         err = ixgbe_dev_rxtx_start(dev);
2658         if (err < 0) {
2659                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2660                 goto error;
2661         }
2662
2663         /* Skip link setup if loopback mode is enabled. */
2664         if (dev->data->dev_conf.lpbk_mode != 0) {
2665                 err = ixgbe_check_supported_loopback_mode(dev);
2666                 if (err < 0) {
2667                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2668                         goto error;
2669                 } else {
2670                         goto skip_link_setup;
2671                 }
2672         }
2673
2674         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2675                 err = hw->mac.ops.setup_sfp(hw);
2676                 if (err)
2677                         goto error;
2678         }
2679
2680         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2681                 /* Turn on the copper */
2682                 ixgbe_set_phy_power(hw, true);
2683         } else {
2684                 /* Turn on the laser */
2685                 ixgbe_enable_tx_laser(hw);
2686         }
2687
2688         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2689         if (err)
2690                 goto error;
2691         dev->data->dev_link.link_status = link_up;
2692
2693         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2694         if (err)
2695                 goto error;
2696
2697         switch (hw->mac.type) {
2698         case ixgbe_mac_X550:
2699         case ixgbe_mac_X550EM_x:
2700         case ixgbe_mac_X550EM_a:
2701                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2702                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2703                         ETH_LINK_SPEED_10G;
2704                 break;
2705         default:
2706                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2707                         ETH_LINK_SPEED_10G;
2708         }
2709
2710         link_speeds = &dev->data->dev_conf.link_speeds;
2711         if (*link_speeds & ~allowed_speeds) {
2712                 PMD_INIT_LOG(ERR, "Invalid link setting");
2713                 goto error;
2714         }
2715
2716         speed = 0x0;
2717         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2718                 switch (hw->mac.type) {
2719                 case ixgbe_mac_82598EB:
2720                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2721                         break;
2722                 case ixgbe_mac_82599EB:
2723                 case ixgbe_mac_X540:
2724                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2725                         break;
2726                 case ixgbe_mac_X550:
2727                 case ixgbe_mac_X550EM_x:
2728                 case ixgbe_mac_X550EM_a:
2729                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2730                         break;
2731                 default:
2732                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2733                 }
2734         } else {
2735                 if (*link_speeds & ETH_LINK_SPEED_10G)
2736                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2737                 if (*link_speeds & ETH_LINK_SPEED_5G)
2738                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2739                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2740                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2741                 if (*link_speeds & ETH_LINK_SPEED_1G)
2742                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2743                 if (*link_speeds & ETH_LINK_SPEED_100M)
2744                         speed |= IXGBE_LINK_SPEED_100_FULL;
2745         }
2746
2747         err = ixgbe_setup_link(hw, speed, link_up);
2748         if (err)
2749                 goto error;
2750
2751 skip_link_setup:
2752
2753         if (rte_intr_allow_others(intr_handle)) {
2754                 /* check if lsc interrupt is enabled */
2755                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2756                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2757                 else
2758                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2759                 ixgbe_dev_macsec_interrupt_setup(dev);
2760         } else {
2761                 rte_intr_callback_unregister(intr_handle,
2762                                              ixgbe_dev_interrupt_handler, dev);
2763                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2764                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2765                                      " no intr multiplex");
2766         }
2767
2768         /* check if rxq interrupt is enabled */
2769         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2770             rte_intr_dp_is_en(intr_handle))
2771                 ixgbe_dev_rxq_interrupt_setup(dev);
2772
2773         /* enable uio/vfio intr/eventfd mapping */
2774         rte_intr_enable(intr_handle);
2775
2776         /* resume enabled intr since hw reset */
2777         ixgbe_enable_intr(dev);
2778         ixgbe_l2_tunnel_conf(dev);
2779         ixgbe_filter_restore(dev);
2780
2781         if (tm_conf->root && !tm_conf->committed)
2782                 PMD_DRV_LOG(WARNING,
2783                             "please call hierarchy_commit() "
2784                             "before starting the port");
2785
2786         /*
2787          * Update link status right before return, because it may
2788          * start link configuration process in a separate thread.
2789          */
2790         ixgbe_dev_link_update(dev, 0);
2791
2792         return 0;
2793
2794 error:
2795         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2796         ixgbe_dev_clear_queues(dev);
2797         return -EIO;
2798 }
2799
2800 /*
2801  * Stop device: disable rx and tx functions to allow for reconfiguring.
2802  */
2803 static void
2804 ixgbe_dev_stop(struct rte_eth_dev *dev)
2805 {
2806         struct rte_eth_link link;
2807         struct ixgbe_adapter *adapter =
2808                 (struct ixgbe_adapter *)dev->data->dev_private;
2809         struct ixgbe_hw *hw =
2810                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811         struct ixgbe_vf_info *vfinfo =
2812                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2813         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2814         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2815         int vf;
2816         struct ixgbe_tm_conf *tm_conf =
2817                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2818
2819         PMD_INIT_FUNC_TRACE();
2820
2821         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2822
2823         /* disable interrupts */
2824         ixgbe_disable_intr(hw);
2825
2826         /* reset the NIC */
2827         ixgbe_pf_reset_hw(hw);
2828         hw->adapter_stopped = 0;
2829
2830         /* stop adapter */
2831         ixgbe_stop_adapter(hw);
2832
2833         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2834                 vfinfo[vf].clear_to_send = false;
2835
2836         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2837                 /* Turn off the copper */
2838                 ixgbe_set_phy_power(hw, false);
2839         } else {
2840                 /* Turn off the laser */
2841                 ixgbe_disable_tx_laser(hw);
2842         }
2843
2844         ixgbe_dev_clear_queues(dev);
2845
2846         /* Clear stored conf */
2847         dev->data->scattered_rx = 0;
2848         dev->data->lro = 0;
2849
2850         /* Clear recorded link status */
2851         memset(&link, 0, sizeof(link));
2852         rte_eth_linkstatus_set(dev, &link);
2853
2854         if (!rte_intr_allow_others(intr_handle))
2855                 /* resume to the default handler */
2856                 rte_intr_callback_register(intr_handle,
2857                                            ixgbe_dev_interrupt_handler,
2858                                            (void *)dev);
2859
2860         /* Clean datapath event and queue/vec mapping */
2861         rte_intr_efd_disable(intr_handle);
2862         if (intr_handle->intr_vec != NULL) {
2863                 rte_free(intr_handle->intr_vec);
2864                 intr_handle->intr_vec = NULL;
2865         }
2866
2867         /* reset hierarchy commit */
2868         tm_conf->committed = false;
2869
2870         adapter->rss_reta_updated = 0;
2871 }
2872
2873 /*
2874  * Set device link up: enable tx.
2875  */
2876 static int
2877 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2878 {
2879         struct ixgbe_hw *hw =
2880                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2881         if (hw->mac.type == ixgbe_mac_82599EB) {
2882 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2883                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2884                         /* Not suported in bypass mode */
2885                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2886                                      "by device id 0x%x", hw->device_id);
2887                         return -ENOTSUP;
2888                 }
2889 #endif
2890         }
2891
2892         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2893                 /* Turn on the copper */
2894                 ixgbe_set_phy_power(hw, true);
2895         } else {
2896                 /* Turn on the laser */
2897                 ixgbe_enable_tx_laser(hw);
2898         }
2899
2900         return 0;
2901 }
2902
2903 /*
2904  * Set device link down: disable tx.
2905  */
2906 static int
2907 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2908 {
2909         struct ixgbe_hw *hw =
2910                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2911         if (hw->mac.type == ixgbe_mac_82599EB) {
2912 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2913                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2914                         /* Not suported in bypass mode */
2915                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2916                                      "by device id 0x%x", hw->device_id);
2917                         return -ENOTSUP;
2918                 }
2919 #endif
2920         }
2921
2922         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2923                 /* Turn off the copper */
2924                 ixgbe_set_phy_power(hw, false);
2925         } else {
2926                 /* Turn off the laser */
2927                 ixgbe_disable_tx_laser(hw);
2928         }
2929
2930         return 0;
2931 }
2932
2933 /*
2934  * Reset and stop device.
2935  */
2936 static void
2937 ixgbe_dev_close(struct rte_eth_dev *dev)
2938 {
2939         struct ixgbe_hw *hw =
2940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941
2942         PMD_INIT_FUNC_TRACE();
2943
2944         ixgbe_pf_reset_hw(hw);
2945
2946         ixgbe_dev_stop(dev);
2947         hw->adapter_stopped = 1;
2948
2949         ixgbe_dev_free_queues(dev);
2950
2951         ixgbe_disable_pcie_master(hw);
2952
2953         /* reprogram the RAR[0] in case user changed it. */
2954         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2955 }
2956
2957 /*
2958  * Reset PF device.
2959  */
2960 static int
2961 ixgbe_dev_reset(struct rte_eth_dev *dev)
2962 {
2963         int ret;
2964
2965         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2966          * its VF to make them align with it. The detailed notification
2967          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2968          * To avoid unexpected behavior in VF, currently reset of PF with
2969          * SR-IOV activation is not supported. It might be supported later.
2970          */
2971         if (dev->data->sriov.active)
2972                 return -ENOTSUP;
2973
2974         ret = eth_ixgbe_dev_uninit(dev);
2975         if (ret)
2976                 return ret;
2977
2978         ret = eth_ixgbe_dev_init(dev, NULL);
2979
2980         return ret;
2981 }
2982
2983 static void
2984 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2985                            struct ixgbe_hw_stats *hw_stats,
2986                            struct ixgbe_macsec_stats *macsec_stats,
2987                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2988                            uint64_t *total_qprc, uint64_t *total_qprdc)
2989 {
2990         uint32_t bprc, lxon, lxoff, total;
2991         uint32_t delta_gprc = 0;
2992         unsigned i;
2993         /* Workaround for RX byte count not including CRC bytes when CRC
2994          * strip is enabled. CRC bytes are removed from counters when crc_strip
2995          * is disabled.
2996          */
2997         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2998                         IXGBE_HLREG0_RXCRCSTRP);
2999
3000         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3001         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3002         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3003         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3004
3005         for (i = 0; i < 8; i++) {
3006                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3007
3008                 /* global total per queue */
3009                 hw_stats->mpc[i] += mp;
3010                 /* Running comprehensive total for stats display */
3011                 *total_missed_rx += hw_stats->mpc[i];
3012                 if (hw->mac.type == ixgbe_mac_82598EB) {
3013                         hw_stats->rnbc[i] +=
3014                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3015                         hw_stats->pxonrxc[i] +=
3016                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3017                         hw_stats->pxoffrxc[i] +=
3018                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3019                 } else {
3020                         hw_stats->pxonrxc[i] +=
3021                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3022                         hw_stats->pxoffrxc[i] +=
3023                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3024                         hw_stats->pxon2offc[i] +=
3025                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3026                 }
3027                 hw_stats->pxontxc[i] +=
3028                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3029                 hw_stats->pxofftxc[i] +=
3030                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3031         }
3032         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3033                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3034                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3035                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3036
3037                 delta_gprc += delta_qprc;
3038
3039                 hw_stats->qprc[i] += delta_qprc;
3040                 hw_stats->qptc[i] += delta_qptc;
3041
3042                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3043                 hw_stats->qbrc[i] +=
3044                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3045                 if (crc_strip == 0)
3046                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3047
3048                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3049                 hw_stats->qbtc[i] +=
3050                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3051
3052                 hw_stats->qprdc[i] += delta_qprdc;
3053                 *total_qprdc += hw_stats->qprdc[i];
3054
3055                 *total_qprc += hw_stats->qprc[i];
3056                 *total_qbrc += hw_stats->qbrc[i];
3057         }
3058         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3059         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3060         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3061
3062         /*
3063          * An errata states that gprc actually counts good + missed packets:
3064          * Workaround to set gprc to summated queue packet receives
3065          */
3066         hw_stats->gprc = *total_qprc;
3067
3068         if (hw->mac.type != ixgbe_mac_82598EB) {
3069                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3070                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3071                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3072                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3073                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3074                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3075                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3076                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3077         } else {
3078                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3079                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3080                 /* 82598 only has a counter in the high register */
3081                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3082                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3083                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3084         }
3085         uint64_t old_tpr = hw_stats->tpr;
3086
3087         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3088         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3089
3090         if (crc_strip == 0)
3091                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3092
3093         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3094         hw_stats->gptc += delta_gptc;
3095         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3096         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3097
3098         /*
3099          * Workaround: mprc hardware is incorrectly counting
3100          * broadcasts, so for now we subtract those.
3101          */
3102         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3103         hw_stats->bprc += bprc;
3104         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3105         if (hw->mac.type == ixgbe_mac_82598EB)
3106                 hw_stats->mprc -= bprc;
3107
3108         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3109         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3110         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3111         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3112         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3113         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3114
3115         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3116         hw_stats->lxontxc += lxon;
3117         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3118         hw_stats->lxofftxc += lxoff;
3119         total = lxon + lxoff;
3120
3121         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3122         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3123         hw_stats->gptc -= total;
3124         hw_stats->mptc -= total;
3125         hw_stats->ptc64 -= total;
3126         hw_stats->gotc -= total * ETHER_MIN_LEN;
3127
3128         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3129         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3130         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3131         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3132         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3133         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3134         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3135         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3136         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3137         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3138         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3139         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3140         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3141         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3142         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3143         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3144         /* Only read FCOE on 82599 */
3145         if (hw->mac.type != ixgbe_mac_82598EB) {
3146                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3147                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3148                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3149                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3150                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3151         }
3152
3153         /* Flow Director Stats registers */
3154         if (hw->mac.type != ixgbe_mac_82598EB) {
3155                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3156                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3157                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3158                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3159                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3160                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3161                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3162                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3163                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3164                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3165         }
3166         /* MACsec Stats registers */
3167         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3168         macsec_stats->out_pkts_encrypted +=
3169                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3170         macsec_stats->out_pkts_protected +=
3171                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3172         macsec_stats->out_octets_encrypted +=
3173                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3174         macsec_stats->out_octets_protected +=
3175                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3176         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3177         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3178         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3179         macsec_stats->in_pkts_unknownsci +=
3180                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3181         macsec_stats->in_octets_decrypted +=
3182                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3183         macsec_stats->in_octets_validated +=
3184                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3185         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3186         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3187         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3188         for (i = 0; i < 2; i++) {
3189                 macsec_stats->in_pkts_ok +=
3190                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3191                 macsec_stats->in_pkts_invalid +=
3192                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3193                 macsec_stats->in_pkts_notvalid +=
3194                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3195         }
3196         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3197         macsec_stats->in_pkts_notusingsa +=
3198                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3199 }
3200
3201 /*
3202  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3203  */
3204 static int
3205 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3206 {
3207         struct ixgbe_hw *hw =
3208                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3209         struct ixgbe_hw_stats *hw_stats =
3210                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3211         struct ixgbe_macsec_stats *macsec_stats =
3212                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3213                                 dev->data->dev_private);
3214         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3215         unsigned i;
3216
3217         total_missed_rx = 0;
3218         total_qbrc = 0;
3219         total_qprc = 0;
3220         total_qprdc = 0;
3221
3222         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3223                         &total_qbrc, &total_qprc, &total_qprdc);
3224
3225         if (stats == NULL)
3226                 return -EINVAL;
3227
3228         /* Fill out the rte_eth_stats statistics structure */
3229         stats->ipackets = total_qprc;
3230         stats->ibytes = total_qbrc;
3231         stats->opackets = hw_stats->gptc;
3232         stats->obytes = hw_stats->gotc;
3233
3234         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3235                 stats->q_ipackets[i] = hw_stats->qprc[i];
3236                 stats->q_opackets[i] = hw_stats->qptc[i];
3237                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3238                 stats->q_obytes[i] = hw_stats->qbtc[i];
3239                 stats->q_errors[i] = hw_stats->qprdc[i];
3240         }
3241
3242         /* Rx Errors */
3243         stats->imissed  = total_missed_rx;
3244         stats->ierrors  = hw_stats->crcerrs +
3245                           hw_stats->mspdc +
3246                           hw_stats->rlec +
3247                           hw_stats->ruc +
3248                           hw_stats->roc +
3249                           hw_stats->illerrc +
3250                           hw_stats->errbc +
3251                           hw_stats->rfc +
3252                           hw_stats->fccrc +
3253                           hw_stats->fclast;
3254
3255         /* Tx Errors */
3256         stats->oerrors  = 0;
3257         return 0;
3258 }
3259
3260 static void
3261 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3262 {
3263         struct ixgbe_hw_stats *stats =
3264                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3265
3266         /* HW registers are cleared on read */
3267         ixgbe_dev_stats_get(dev, NULL);
3268
3269         /* Reset software totals */
3270         memset(stats, 0, sizeof(*stats));
3271 }
3272
3273 /* This function calculates the number of xstats based on the current config */
3274 static unsigned
3275 ixgbe_xstats_calc_num(void) {
3276         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3277                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3278                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3279 }
3280
3281 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3282         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3283 {
3284         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3285         unsigned stat, i, count;
3286
3287         if (xstats_names != NULL) {
3288                 count = 0;
3289
3290                 /* Note: limit >= cnt_stats checked upstream
3291                  * in rte_eth_xstats_names()
3292                  */
3293
3294                 /* Extended stats from ixgbe_hw_stats */
3295                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3296                         snprintf(xstats_names[count].name,
3297                                 sizeof(xstats_names[count].name),
3298                                 "%s",
3299                                 rte_ixgbe_stats_strings[i].name);
3300                         count++;
3301                 }
3302
3303                 /* MACsec Stats */
3304                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3305                         snprintf(xstats_names[count].name,
3306                                 sizeof(xstats_names[count].name),
3307                                 "%s",
3308                                 rte_ixgbe_macsec_strings[i].name);
3309                         count++;
3310                 }
3311
3312                 /* RX Priority Stats */
3313                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3314                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3315                                 snprintf(xstats_names[count].name,
3316                                         sizeof(xstats_names[count].name),
3317                                         "rx_priority%u_%s", i,
3318                                         rte_ixgbe_rxq_strings[stat].name);
3319                                 count++;
3320                         }
3321                 }
3322
3323                 /* TX Priority Stats */
3324                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3325                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3326                                 snprintf(xstats_names[count].name,
3327                                         sizeof(xstats_names[count].name),
3328                                         "tx_priority%u_%s", i,
3329                                         rte_ixgbe_txq_strings[stat].name);
3330                                 count++;
3331                         }
3332                 }
3333         }
3334         return cnt_stats;
3335 }
3336
3337 static int ixgbe_dev_xstats_get_names_by_id(
3338         struct rte_eth_dev *dev,
3339         struct rte_eth_xstat_name *xstats_names,
3340         const uint64_t *ids,
3341         unsigned int limit)
3342 {
3343         if (!ids) {
3344                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3345                 unsigned int stat, i, count;
3346
3347                 if (xstats_names != NULL) {
3348                         count = 0;
3349
3350                         /* Note: limit >= cnt_stats checked upstream
3351                          * in rte_eth_xstats_names()
3352                          */
3353
3354                         /* Extended stats from ixgbe_hw_stats */
3355                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3356                                 snprintf(xstats_names[count].name,
3357                                         sizeof(xstats_names[count].name),
3358                                         "%s",
3359                                         rte_ixgbe_stats_strings[i].name);
3360                                 count++;
3361                         }
3362
3363                         /* MACsec Stats */
3364                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3365                                 snprintf(xstats_names[count].name,
3366                                         sizeof(xstats_names[count].name),
3367                                         "%s",
3368                                         rte_ixgbe_macsec_strings[i].name);
3369                                 count++;
3370                         }
3371
3372                         /* RX Priority Stats */
3373                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3374                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3375                                         snprintf(xstats_names[count].name,
3376                                             sizeof(xstats_names[count].name),
3377                                             "rx_priority%u_%s", i,
3378                                             rte_ixgbe_rxq_strings[stat].name);
3379                                         count++;
3380                                 }
3381                         }
3382
3383                         /* TX Priority Stats */
3384                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3385                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3386                                         snprintf(xstats_names[count].name,
3387                                             sizeof(xstats_names[count].name),
3388                                             "tx_priority%u_%s", i,
3389                                             rte_ixgbe_txq_strings[stat].name);
3390                                         count++;
3391                                 }
3392                         }
3393                 }
3394                 return cnt_stats;
3395         }
3396
3397         uint16_t i;
3398         uint16_t size = ixgbe_xstats_calc_num();
3399         struct rte_eth_xstat_name xstats_names_copy[size];
3400
3401         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3402                         size);
3403
3404         for (i = 0; i < limit; i++) {
3405                 if (ids[i] >= size) {
3406                         PMD_INIT_LOG(ERR, "id value isn't valid");
3407                         return -1;
3408                 }
3409                 strcpy(xstats_names[i].name,
3410                                 xstats_names_copy[ids[i]].name);
3411         }
3412         return limit;
3413 }
3414
3415 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3416         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3417 {
3418         unsigned i;
3419
3420         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3421                 return -ENOMEM;
3422
3423         if (xstats_names != NULL)
3424                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3425                         snprintf(xstats_names[i].name,
3426                                 sizeof(xstats_names[i].name),
3427                                 "%s", rte_ixgbevf_stats_strings[i].name);
3428         return IXGBEVF_NB_XSTATS;
3429 }
3430
3431 static int
3432 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3433                                          unsigned n)
3434 {
3435         struct ixgbe_hw *hw =
3436                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3437         struct ixgbe_hw_stats *hw_stats =
3438                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3439         struct ixgbe_macsec_stats *macsec_stats =
3440                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3441                                 dev->data->dev_private);
3442         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3443         unsigned i, stat, count = 0;
3444
3445         count = ixgbe_xstats_calc_num();
3446
3447         if (n < count)
3448                 return count;
3449
3450         total_missed_rx = 0;
3451         total_qbrc = 0;
3452         total_qprc = 0;
3453         total_qprdc = 0;
3454
3455         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3456                         &total_qbrc, &total_qprc, &total_qprdc);
3457
3458         /* If this is a reset xstats is NULL, and we have cleared the
3459          * registers by reading them.
3460          */
3461         if (!xstats)
3462                 return 0;
3463
3464         /* Extended stats from ixgbe_hw_stats */
3465         count = 0;
3466         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3467                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3468                                 rte_ixgbe_stats_strings[i].offset);
3469                 xstats[count].id = count;
3470                 count++;
3471         }
3472
3473         /* MACsec Stats */
3474         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3475                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3476                                 rte_ixgbe_macsec_strings[i].offset);
3477                 xstats[count].id = count;
3478                 count++;
3479         }
3480
3481         /* RX Priority Stats */
3482         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3483                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3484                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3485                                         rte_ixgbe_rxq_strings[stat].offset +
3486                                         (sizeof(uint64_t) * i));
3487                         xstats[count].id = count;
3488                         count++;
3489                 }
3490         }
3491
3492         /* TX Priority Stats */
3493         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3494                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3495                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3496                                         rte_ixgbe_txq_strings[stat].offset +
3497                                         (sizeof(uint64_t) * i));
3498                         xstats[count].id = count;
3499                         count++;
3500                 }
3501         }
3502         return count;
3503 }
3504
3505 static int
3506 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3507                 uint64_t *values, unsigned int n)
3508 {
3509         if (!ids) {
3510                 struct ixgbe_hw *hw =
3511                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512                 struct ixgbe_hw_stats *hw_stats =
3513                                 IXGBE_DEV_PRIVATE_TO_STATS(
3514                                                 dev->data->dev_private);
3515                 struct ixgbe_macsec_stats *macsec_stats =
3516                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3517                                         dev->data->dev_private);
3518                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3519                 unsigned int i, stat, count = 0;
3520
3521                 count = ixgbe_xstats_calc_num();
3522
3523                 if (!ids && n < count)
3524                         return count;
3525
3526                 total_missed_rx = 0;
3527                 total_qbrc = 0;
3528                 total_qprc = 0;
3529                 total_qprdc = 0;
3530
3531                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3532                                 &total_missed_rx, &total_qbrc, &total_qprc,
3533                                 &total_qprdc);
3534
3535                 /* If this is a reset xstats is NULL, and we have cleared the
3536                  * registers by reading them.
3537                  */
3538                 if (!ids && !values)
3539                         return 0;
3540
3541                 /* Extended stats from ixgbe_hw_stats */
3542                 count = 0;
3543                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3544                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3545                                         rte_ixgbe_stats_strings[i].offset);
3546                         count++;
3547                 }
3548
3549                 /* MACsec Stats */
3550                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3551                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3552                                         rte_ixgbe_macsec_strings[i].offset);
3553                         count++;
3554                 }
3555
3556                 /* RX Priority Stats */
3557                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3558                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3559                                 values[count] =
3560                                         *(uint64_t *)(((char *)hw_stats) +
3561                                         rte_ixgbe_rxq_strings[stat].offset +
3562                                         (sizeof(uint64_t) * i));
3563                                 count++;
3564                         }
3565                 }
3566
3567                 /* TX Priority Stats */
3568                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3569                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3570                                 values[count] =
3571                                         *(uint64_t *)(((char *)hw_stats) +
3572                                         rte_ixgbe_txq_strings[stat].offset +
3573                                         (sizeof(uint64_t) * i));
3574                                 count++;
3575                         }
3576                 }
3577                 return count;
3578         }
3579
3580         uint16_t i;
3581         uint16_t size = ixgbe_xstats_calc_num();
3582         uint64_t values_copy[size];
3583
3584         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3585
3586         for (i = 0; i < n; i++) {
3587                 if (ids[i] >= size) {
3588                         PMD_INIT_LOG(ERR, "id value isn't valid");
3589                         return -1;
3590                 }
3591                 values[i] = values_copy[ids[i]];
3592         }
3593         return n;
3594 }
3595
3596 static void
3597 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3598 {
3599         struct ixgbe_hw_stats *stats =
3600                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3601         struct ixgbe_macsec_stats *macsec_stats =
3602                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3603                                 dev->data->dev_private);
3604
3605         unsigned count = ixgbe_xstats_calc_num();
3606
3607         /* HW registers are cleared on read */
3608         ixgbe_dev_xstats_get(dev, NULL, count);
3609
3610         /* Reset software totals */
3611         memset(stats, 0, sizeof(*stats));
3612         memset(macsec_stats, 0, sizeof(*macsec_stats));
3613 }
3614
3615 static void
3616 ixgbevf_update_stats(struct rte_eth_dev *dev)
3617 {
3618         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3620                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3621
3622         /* Good Rx packet, include VF loopback */
3623         UPDATE_VF_STAT(IXGBE_VFGPRC,
3624             hw_stats->last_vfgprc, hw_stats->vfgprc);
3625
3626         /* Good Rx octets, include VF loopback */
3627         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3628             hw_stats->last_vfgorc, hw_stats->vfgorc);
3629
3630         /* Good Tx packet, include VF loopback */
3631         UPDATE_VF_STAT(IXGBE_VFGPTC,
3632             hw_stats->last_vfgptc, hw_stats->vfgptc);
3633
3634         /* Good Tx octets, include VF loopback */
3635         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3636             hw_stats->last_vfgotc, hw_stats->vfgotc);
3637
3638         /* Rx Multicst Packet */
3639         UPDATE_VF_STAT(IXGBE_VFMPRC,
3640             hw_stats->last_vfmprc, hw_stats->vfmprc);
3641 }
3642
3643 static int
3644 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3645                        unsigned n)
3646 {
3647         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3648                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3649         unsigned i;
3650
3651         if (n < IXGBEVF_NB_XSTATS)
3652                 return IXGBEVF_NB_XSTATS;
3653
3654         ixgbevf_update_stats(dev);
3655
3656         if (!xstats)
3657                 return 0;
3658
3659         /* Extended stats */
3660         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3661                 xstats[i].id = i;
3662                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3663                         rte_ixgbevf_stats_strings[i].offset);
3664         }
3665
3666         return IXGBEVF_NB_XSTATS;
3667 }
3668
3669 static int
3670 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3671 {
3672         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3673                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3674
3675         ixgbevf_update_stats(dev);
3676
3677         if (stats == NULL)
3678                 return -EINVAL;
3679
3680         stats->ipackets = hw_stats->vfgprc;
3681         stats->ibytes = hw_stats->vfgorc;
3682         stats->opackets = hw_stats->vfgptc;
3683         stats->obytes = hw_stats->vfgotc;
3684         return 0;
3685 }
3686
3687 static void
3688 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3689 {
3690         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3691                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3692
3693         /* Sync HW register to the last stats */
3694         ixgbevf_dev_stats_get(dev, NULL);
3695
3696         /* reset HW current stats*/
3697         hw_stats->vfgprc = 0;
3698         hw_stats->vfgorc = 0;
3699         hw_stats->vfgptc = 0;
3700         hw_stats->vfgotc = 0;
3701 }
3702
3703 static int
3704 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3705 {
3706         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3707         u16 eeprom_verh, eeprom_verl;
3708         u32 etrack_id;
3709         int ret;
3710
3711         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3712         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3713
3714         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3715         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3716
3717         ret += 1; /* add the size of '\0' */
3718         if (fw_size < (u32)ret)
3719                 return ret;
3720         else
3721                 return 0;
3722 }
3723
3724 static void
3725 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3726 {
3727         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3730
3731         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3732         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3733         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3734                 /*
3735                  * When DCB/VT is off, maximum number of queues changes,
3736                  * except for 82598EB, which remains constant.
3737                  */
3738                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3739                                 hw->mac.type != ixgbe_mac_82598EB)
3740                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3741         }
3742         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3743         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3744         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3745         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3746         dev_info->max_vfs = pci_dev->max_vfs;
3747         if (hw->mac.type == ixgbe_mac_82598EB)
3748                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3749         else
3750                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3751         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3752         dev_info->min_mtu = ETHER_MIN_MTU;
3753         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3754         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3755         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3756                                      dev_info->rx_queue_offload_capa);
3757         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3758         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3759
3760         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3761                 .rx_thresh = {
3762                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3763                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3764                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3765                 },
3766                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3767                 .rx_drop_en = 0,
3768                 .offloads = 0,
3769         };
3770
3771         dev_info->default_txconf = (struct rte_eth_txconf) {
3772                 .tx_thresh = {
3773                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3774                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3775                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3776                 },
3777                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3778                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3779                 .offloads = 0,
3780         };
3781
3782         dev_info->rx_desc_lim = rx_desc_lim;
3783         dev_info->tx_desc_lim = tx_desc_lim;
3784
3785         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3786         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3787         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3788
3789         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3790         if (hw->mac.type == ixgbe_mac_X540 ||
3791             hw->mac.type == ixgbe_mac_X540_vf ||
3792             hw->mac.type == ixgbe_mac_X550 ||
3793             hw->mac.type == ixgbe_mac_X550_vf) {
3794                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3795         }
3796         if (hw->mac.type == ixgbe_mac_X550) {
3797                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3798                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3799         }
3800
3801         /* Driver-preferred Rx/Tx parameters */
3802         dev_info->default_rxportconf.burst_size = 32;
3803         dev_info->default_txportconf.burst_size = 32;
3804         dev_info->default_rxportconf.nb_queues = 1;
3805         dev_info->default_txportconf.nb_queues = 1;
3806         dev_info->default_rxportconf.ring_size = 256;
3807         dev_info->default_txportconf.ring_size = 256;
3808 }
3809
3810 static const uint32_t *
3811 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3812 {
3813         static const uint32_t ptypes[] = {
3814                 /* For non-vec functions,
3815                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3816                  * for vec functions,
3817                  * refers to _recv_raw_pkts_vec().
3818                  */
3819                 RTE_PTYPE_L2_ETHER,
3820                 RTE_PTYPE_L3_IPV4,
3821                 RTE_PTYPE_L3_IPV4_EXT,
3822                 RTE_PTYPE_L3_IPV6,
3823                 RTE_PTYPE_L3_IPV6_EXT,
3824                 RTE_PTYPE_L4_SCTP,
3825                 RTE_PTYPE_L4_TCP,
3826                 RTE_PTYPE_L4_UDP,
3827                 RTE_PTYPE_TUNNEL_IP,
3828                 RTE_PTYPE_INNER_L3_IPV6,
3829                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3830                 RTE_PTYPE_INNER_L4_TCP,
3831                 RTE_PTYPE_INNER_L4_UDP,
3832                 RTE_PTYPE_UNKNOWN
3833         };
3834
3835         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3836             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3837             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3838             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3839                 return ptypes;
3840
3841 #if defined(RTE_ARCH_X86)
3842         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3843             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3844                 return ptypes;
3845 #endif
3846         return NULL;
3847 }
3848
3849 static void
3850 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3851                      struct rte_eth_dev_info *dev_info)
3852 {
3853         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3855
3856         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3857         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3858         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3859         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3860         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3861         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3862         dev_info->max_vfs = pci_dev->max_vfs;
3863         if (hw->mac.type == ixgbe_mac_82598EB)
3864                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3865         else
3866                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3867         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3868         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3869                                      dev_info->rx_queue_offload_capa);
3870         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3871         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3872
3873         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3874                 .rx_thresh = {
3875                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3876                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3877                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3878                 },
3879                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3880                 .rx_drop_en = 0,
3881                 .offloads = 0,
3882         };
3883
3884         dev_info->default_txconf = (struct rte_eth_txconf) {
3885                 .tx_thresh = {
3886                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3887                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3888                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3889                 },
3890                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3891                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3892                 .offloads = 0,
3893         };
3894
3895         dev_info->rx_desc_lim = rx_desc_lim;
3896         dev_info->tx_desc_lim = tx_desc_lim;
3897 }
3898
3899 static int
3900 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3901                    int *link_up, int wait_to_complete)
3902 {
3903         struct ixgbe_mbx_info *mbx = &hw->mbx;
3904         struct ixgbe_mac_info *mac = &hw->mac;
3905         uint32_t links_reg, in_msg;
3906         int ret_val = 0;
3907
3908         /* If we were hit with a reset drop the link */
3909         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3910                 mac->get_link_status = true;
3911
3912         if (!mac->get_link_status)
3913                 goto out;
3914
3915         /* if link status is down no point in checking to see if pf is up */
3916         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3917         if (!(links_reg & IXGBE_LINKS_UP))
3918                 goto out;
3919
3920         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3921          * before the link status is correct
3922          */
3923         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3924                 int i;
3925
3926                 for (i = 0; i < 5; i++) {
3927                         rte_delay_us(100);
3928                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3929
3930                         if (!(links_reg & IXGBE_LINKS_UP))
3931                                 goto out;
3932                 }
3933         }
3934
3935         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3936         case IXGBE_LINKS_SPEED_10G_82599:
3937                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3938                 if (hw->mac.type >= ixgbe_mac_X550) {
3939                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3940                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3941                 }
3942                 break;
3943         case IXGBE_LINKS_SPEED_1G_82599:
3944                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3945                 break;
3946         case IXGBE_LINKS_SPEED_100_82599:
3947                 *speed = IXGBE_LINK_SPEED_100_FULL;
3948                 if (hw->mac.type == ixgbe_mac_X550) {
3949                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3950                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3951                 }
3952                 break;
3953         case IXGBE_LINKS_SPEED_10_X550EM_A:
3954                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3955                 /* Since Reserved in older MAC's */
3956                 if (hw->mac.type >= ixgbe_mac_X550)
3957                         *speed = IXGBE_LINK_SPEED_10_FULL;
3958                 break;
3959         default:
3960                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3961         }
3962
3963         /* if the read failed it could just be a mailbox collision, best wait
3964          * until we are called again and don't report an error
3965          */
3966         if (mbx->ops.read(hw, &in_msg, 1, 0))
3967                 goto out;
3968
3969         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3970                 /* msg is not CTS and is NACK we must have lost CTS status */
3971                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3972                         mac->get_link_status = false;
3973                 goto out;
3974         }
3975
3976         /* the pf is talking, if we timed out in the past we reinit */
3977         if (!mbx->timeout) {
3978                 ret_val = -1;
3979                 goto out;
3980         }
3981
3982         /* if we passed all the tests above then the link is up and we no
3983          * longer need to check for link
3984          */
3985         mac->get_link_status = false;
3986
3987 out:
3988         *link_up = !mac->get_link_status;
3989         return ret_val;
3990 }
3991
3992 static void
3993 ixgbe_dev_setup_link_alarm_handler(void *param)
3994 {
3995         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3997         struct ixgbe_interrupt *intr =
3998                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3999         u32 speed;
4000         bool autoneg = false;
4001
4002         speed = hw->phy.autoneg_advertised;
4003         if (!speed)
4004                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4005
4006         ixgbe_setup_link(hw, speed, true);
4007
4008         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4009 }
4010
4011 /* return 0 means link status changed, -1 means not changed */
4012 int
4013 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4014                             int wait_to_complete, int vf)
4015 {
4016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4017         struct rte_eth_link link;
4018         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4019         struct ixgbe_interrupt *intr =
4020                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4021         int link_up;
4022         int diag;
4023         int wait = 1;
4024
4025         memset(&link, 0, sizeof(link));
4026         link.link_status = ETH_LINK_DOWN;
4027         link.link_speed = ETH_SPEED_NUM_NONE;
4028         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4029         link.link_autoneg = ETH_LINK_AUTONEG;
4030
4031         hw->mac.get_link_status = true;
4032
4033         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4034                 return rte_eth_linkstatus_set(dev, &link);
4035
4036         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4037         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4038                 wait = 0;
4039
4040         if (vf)
4041                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4042         else
4043                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4044
4045         if (diag != 0) {
4046                 link.link_speed = ETH_SPEED_NUM_100M;
4047                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4048                 return rte_eth_linkstatus_set(dev, &link);
4049         }
4050
4051         if (link_up == 0) {
4052                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4053                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4054                         rte_eal_alarm_set(10,
4055                                 ixgbe_dev_setup_link_alarm_handler, dev);
4056                 }
4057                 return rte_eth_linkstatus_set(dev, &link);
4058         }
4059
4060         link.link_status = ETH_LINK_UP;
4061         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4062
4063         switch (link_speed) {
4064         default:
4065         case IXGBE_LINK_SPEED_UNKNOWN:
4066                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4067                 link.link_speed = ETH_SPEED_NUM_100M;
4068                 break;
4069
4070         case IXGBE_LINK_SPEED_100_FULL:
4071                 link.link_speed = ETH_SPEED_NUM_100M;
4072                 break;
4073
4074         case IXGBE_LINK_SPEED_1GB_FULL:
4075                 link.link_speed = ETH_SPEED_NUM_1G;
4076                 break;
4077
4078         case IXGBE_LINK_SPEED_2_5GB_FULL:
4079                 link.link_speed = ETH_SPEED_NUM_2_5G;
4080                 break;
4081
4082         case IXGBE_LINK_SPEED_5GB_FULL:
4083                 link.link_speed = ETH_SPEED_NUM_5G;
4084                 break;
4085
4086         case IXGBE_LINK_SPEED_10GB_FULL:
4087                 link.link_speed = ETH_SPEED_NUM_10G;
4088                 break;
4089         }
4090
4091         return rte_eth_linkstatus_set(dev, &link);
4092 }
4093
4094 static int
4095 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4096 {
4097         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4098 }
4099
4100 static int
4101 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4102 {
4103         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4104 }
4105
4106 static void
4107 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4108 {
4109         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4110         uint32_t fctrl;
4111
4112         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4113         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4114         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4115 }
4116
4117 static void
4118 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4119 {
4120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4121         uint32_t fctrl;
4122
4123         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4124         fctrl &= (~IXGBE_FCTRL_UPE);
4125         if (dev->data->all_multicast == 1)
4126                 fctrl |= IXGBE_FCTRL_MPE;
4127         else
4128                 fctrl &= (~IXGBE_FCTRL_MPE);
4129         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4130 }
4131
4132 static void
4133 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4134 {
4135         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4136         uint32_t fctrl;
4137
4138         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4139         fctrl |= IXGBE_FCTRL_MPE;
4140         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4141 }
4142
4143 static void
4144 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4145 {
4146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4147         uint32_t fctrl;
4148
4149         if (dev->data->promiscuous == 1)
4150                 return; /* must remain in all_multicast mode */
4151
4152         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4153         fctrl &= (~IXGBE_FCTRL_MPE);
4154         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4155 }
4156
4157 /**
4158  * It clears the interrupt causes and enables the interrupt.
4159  * It will be called once only during nic initialized.
4160  *
4161  * @param dev
4162  *  Pointer to struct rte_eth_dev.
4163  * @param on
4164  *  Enable or Disable.
4165  *
4166  * @return
4167  *  - On success, zero.
4168  *  - On failure, a negative value.
4169  */
4170 static int
4171 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4172 {
4173         struct ixgbe_interrupt *intr =
4174                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4175
4176         ixgbe_dev_link_status_print(dev);
4177         if (on)
4178                 intr->mask |= IXGBE_EICR_LSC;
4179         else
4180                 intr->mask &= ~IXGBE_EICR_LSC;
4181
4182         return 0;
4183 }
4184
4185 /**
4186  * It clears the interrupt causes and enables the interrupt.
4187  * It will be called once only during nic initialized.
4188  *
4189  * @param dev
4190  *  Pointer to struct rte_eth_dev.
4191  *
4192  * @return
4193  *  - On success, zero.
4194  *  - On failure, a negative value.
4195  */
4196 static int
4197 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4198 {
4199         struct ixgbe_interrupt *intr =
4200                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4201
4202         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4203
4204         return 0;
4205 }
4206
4207 /**
4208  * It clears the interrupt causes and enables the interrupt.
4209  * It will be called once only during nic initialized.
4210  *
4211  * @param dev
4212  *  Pointer to struct rte_eth_dev.
4213  *
4214  * @return
4215  *  - On success, zero.
4216  *  - On failure, a negative value.
4217  */
4218 static int
4219 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4220 {
4221         struct ixgbe_interrupt *intr =
4222                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4223
4224         intr->mask |= IXGBE_EICR_LINKSEC;
4225
4226         return 0;
4227 }
4228
4229 /*
4230  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4231  *
4232  * @param dev
4233  *  Pointer to struct rte_eth_dev.
4234  *
4235  * @return
4236  *  - On success, zero.
4237  *  - On failure, a negative value.
4238  */
4239 static int
4240 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4241 {
4242         uint32_t eicr;
4243         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4244         struct ixgbe_interrupt *intr =
4245                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4246
4247         /* clear all cause mask */
4248         ixgbe_disable_intr(hw);
4249
4250         /* read-on-clear nic registers here */
4251         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4252         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4253
4254         intr->flags = 0;
4255
4256         /* set flag for async link update */
4257         if (eicr & IXGBE_EICR_LSC)
4258                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4259
4260         if (eicr & IXGBE_EICR_MAILBOX)
4261                 intr->flags |= IXGBE_FLAG_MAILBOX;
4262
4263         if (eicr & IXGBE_EICR_LINKSEC)
4264                 intr->flags |= IXGBE_FLAG_MACSEC;
4265
4266         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4267             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4268             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4269                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4270
4271         return 0;
4272 }
4273
4274 /**
4275  * It gets and then prints the link status.
4276  *
4277  * @param dev
4278  *  Pointer to struct rte_eth_dev.
4279  *
4280  * @return
4281  *  - On success, zero.
4282  *  - On failure, a negative value.
4283  */
4284 static void
4285 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4286 {
4287         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4288         struct rte_eth_link link;
4289
4290         rte_eth_linkstatus_get(dev, &link);
4291
4292         if (link.link_status) {
4293                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4294                                         (int)(dev->data->port_id),
4295                                         (unsigned)link.link_speed,
4296                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4297                                         "full-duplex" : "half-duplex");
4298         } else {
4299                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4300                                 (int)(dev->data->port_id));
4301         }
4302         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4303                                 pci_dev->addr.domain,
4304                                 pci_dev->addr.bus,
4305                                 pci_dev->addr.devid,
4306                                 pci_dev->addr.function);
4307 }
4308
4309 /*
4310  * It executes link_update after knowing an interrupt occurred.
4311  *
4312  * @param dev
4313  *  Pointer to struct rte_eth_dev.
4314  *
4315  * @return
4316  *  - On success, zero.
4317  *  - On failure, a negative value.
4318  */
4319 static int
4320 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4321 {
4322         struct ixgbe_interrupt *intr =
4323                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4324         int64_t timeout;
4325         struct ixgbe_hw *hw =
4326                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4327
4328         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4329
4330         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4331                 ixgbe_pf_mbx_process(dev);
4332                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4333         }
4334
4335         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4336                 ixgbe_handle_lasi(hw);
4337                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4338         }
4339
4340         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4341                 struct rte_eth_link link;
4342
4343                 /* get the link status before link update, for predicting later */
4344                 rte_eth_linkstatus_get(dev, &link);
4345
4346                 ixgbe_dev_link_update(dev, 0);
4347
4348                 /* likely to up */
4349                 if (!link.link_status)
4350                         /* handle it 1 sec later, wait it being stable */
4351                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4352                 /* likely to down */
4353                 else
4354                         /* handle it 4 sec later, wait it being stable */
4355                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4356
4357                 ixgbe_dev_link_status_print(dev);
4358                 if (rte_eal_alarm_set(timeout * 1000,
4359                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4360                         PMD_DRV_LOG(ERR, "Error setting alarm");
4361                 else {
4362                         /* remember original mask */
4363                         intr->mask_original = intr->mask;
4364                         /* only disable lsc interrupt */
4365                         intr->mask &= ~IXGBE_EIMS_LSC;
4366                 }
4367         }
4368
4369         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4370         ixgbe_enable_intr(dev);
4371
4372         return 0;
4373 }
4374
4375 /**
4376  * Interrupt handler which shall be registered for alarm callback for delayed
4377  * handling specific interrupt to wait for the stable nic state. As the
4378  * NIC interrupt state is not stable for ixgbe after link is just down,
4379  * it needs to wait 4 seconds to get the stable status.
4380  *
4381  * @param handle
4382  *  Pointer to interrupt handle.
4383  * @param param
4384  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4385  *
4386  * @return
4387  *  void
4388  */
4389 static void
4390 ixgbe_dev_interrupt_delayed_handler(void *param)
4391 {
4392         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4393         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4394         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4395         struct ixgbe_interrupt *intr =
4396                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4397         struct ixgbe_hw *hw =
4398                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4399         uint32_t eicr;
4400
4401         ixgbe_disable_intr(hw);
4402
4403         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4404         if (eicr & IXGBE_EICR_MAILBOX)
4405                 ixgbe_pf_mbx_process(dev);
4406
4407         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4408                 ixgbe_handle_lasi(hw);
4409                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4410         }
4411
4412         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4413                 ixgbe_dev_link_update(dev, 0);
4414                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4415                 ixgbe_dev_link_status_print(dev);
4416                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4417                                               NULL);
4418         }
4419
4420         if (intr->flags & IXGBE_FLAG_MACSEC) {
4421                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4422                                               NULL);
4423                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4424         }
4425
4426         /* restore original mask */
4427         intr->mask = intr->mask_original;
4428         intr->mask_original = 0;
4429
4430         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4431         ixgbe_enable_intr(dev);
4432         rte_intr_enable(intr_handle);
4433 }
4434
4435 /**
4436  * Interrupt handler triggered by NIC  for handling
4437  * specific interrupt.
4438  *
4439  * @param handle
4440  *  Pointer to interrupt handle.
4441  * @param param
4442  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4443  *
4444  * @return
4445  *  void
4446  */
4447 static void
4448 ixgbe_dev_interrupt_handler(void *param)
4449 {
4450         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4451
4452         ixgbe_dev_interrupt_get_status(dev);
4453         ixgbe_dev_interrupt_action(dev);
4454 }
4455
4456 static int
4457 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4458 {
4459         struct ixgbe_hw *hw;
4460
4461         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4462         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4463 }
4464
4465 static int
4466 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4467 {
4468         struct ixgbe_hw *hw;
4469
4470         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4471         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4472 }
4473
4474 static int
4475 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4476 {
4477         struct ixgbe_hw *hw;
4478         uint32_t mflcn_reg;
4479         uint32_t fccfg_reg;
4480         int rx_pause;
4481         int tx_pause;
4482
4483         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484
4485         fc_conf->pause_time = hw->fc.pause_time;
4486         fc_conf->high_water = hw->fc.high_water[0];
4487         fc_conf->low_water = hw->fc.low_water[0];
4488         fc_conf->send_xon = hw->fc.send_xon;
4489         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4490
4491         /*
4492          * Return rx_pause status according to actual setting of
4493          * MFLCN register.
4494          */
4495         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4496         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4497                 rx_pause = 1;
4498         else
4499                 rx_pause = 0;
4500
4501         /*
4502          * Return tx_pause status according to actual setting of
4503          * FCCFG register.
4504          */
4505         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4506         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4507                 tx_pause = 1;
4508         else
4509                 tx_pause = 0;
4510
4511         if (rx_pause && tx_pause)
4512                 fc_conf->mode = RTE_FC_FULL;
4513         else if (rx_pause)
4514                 fc_conf->mode = RTE_FC_RX_PAUSE;
4515         else if (tx_pause)
4516                 fc_conf->mode = RTE_FC_TX_PAUSE;
4517         else
4518                 fc_conf->mode = RTE_FC_NONE;
4519
4520         return 0;
4521 }
4522
4523 static int
4524 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4525 {
4526         struct ixgbe_hw *hw;
4527         int err;
4528         uint32_t rx_buf_size;
4529         uint32_t max_high_water;
4530         uint32_t mflcn;
4531         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4532                 ixgbe_fc_none,
4533                 ixgbe_fc_rx_pause,
4534                 ixgbe_fc_tx_pause,
4535                 ixgbe_fc_full
4536         };
4537
4538         PMD_INIT_FUNC_TRACE();
4539
4540         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4541         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4542         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4543
4544         /*
4545          * At least reserve one Ethernet frame for watermark
4546          * high_water/low_water in kilo bytes for ixgbe
4547          */
4548         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4549         if ((fc_conf->high_water > max_high_water) ||
4550                 (fc_conf->high_water < fc_conf->low_water)) {
4551                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4552                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4553                 return -EINVAL;
4554         }
4555
4556         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4557         hw->fc.pause_time     = fc_conf->pause_time;
4558         hw->fc.high_water[0]  = fc_conf->high_water;
4559         hw->fc.low_water[0]   = fc_conf->low_water;
4560         hw->fc.send_xon       = fc_conf->send_xon;
4561         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4562
4563         err = ixgbe_fc_enable(hw);
4564
4565         /* Not negotiated is not an error case */
4566         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4567
4568                 /* check if we want to forward MAC frames - driver doesn't have native
4569                  * capability to do that, so we'll write the registers ourselves */
4570
4571                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4572
4573                 /* set or clear MFLCN.PMCF bit depending on configuration */
4574                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4575                         mflcn |= IXGBE_MFLCN_PMCF;
4576                 else
4577                         mflcn &= ~IXGBE_MFLCN_PMCF;
4578
4579                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4580                 IXGBE_WRITE_FLUSH(hw);
4581
4582                 return 0;
4583         }
4584
4585         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4586         return -EIO;
4587 }
4588
4589 /**
4590  *  ixgbe_pfc_enable_generic - Enable flow control
4591  *  @hw: pointer to hardware structure
4592  *  @tc_num: traffic class number
4593  *  Enable flow control according to the current settings.
4594  */
4595 static int
4596 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4597 {
4598         int ret_val = 0;
4599         uint32_t mflcn_reg, fccfg_reg;
4600         uint32_t reg;
4601         uint32_t fcrtl, fcrth;
4602         uint8_t i;
4603         uint8_t nb_rx_en;
4604
4605         /* Validate the water mark configuration */
4606         if (!hw->fc.pause_time) {
4607                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4608                 goto out;
4609         }
4610
4611         /* Low water mark of zero causes XOFF floods */
4612         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4613                  /* High/Low water can not be 0 */
4614                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4615                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4616                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4617                         goto out;
4618                 }
4619
4620                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4621                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4622                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4623                         goto out;
4624                 }
4625         }
4626         /* Negotiate the fc mode to use */
4627         ixgbe_fc_autoneg(hw);
4628
4629         /* Disable any previous flow control settings */
4630         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4631         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4632
4633         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4634         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4635
4636         switch (hw->fc.current_mode) {
4637         case ixgbe_fc_none:
4638                 /*
4639                  * If the count of enabled RX Priority Flow control >1,
4640                  * and the TX pause can not be disabled
4641                  */
4642                 nb_rx_en = 0;
4643                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4644                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4645                         if (reg & IXGBE_FCRTH_FCEN)
4646                                 nb_rx_en++;
4647                 }
4648                 if (nb_rx_en > 1)
4649                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4650                 break;
4651         case ixgbe_fc_rx_pause:
4652                 /*
4653                  * Rx Flow control is enabled and Tx Flow control is
4654                  * disabled by software override. Since there really
4655                  * isn't a way to advertise that we are capable of RX
4656                  * Pause ONLY, we will advertise that we support both
4657                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4658                  * disable the adapter's ability to send PAUSE frames.
4659                  */
4660                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4661                 /*
4662                  * If the count of enabled RX Priority Flow control >1,
4663                  * and the TX pause can not be disabled
4664                  */
4665                 nb_rx_en = 0;
4666                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4667                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4668                         if (reg & IXGBE_FCRTH_FCEN)
4669                                 nb_rx_en++;
4670                 }
4671                 if (nb_rx_en > 1)
4672                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4673                 break;
4674         case ixgbe_fc_tx_pause:
4675                 /*
4676                  * Tx Flow control is enabled, and Rx Flow control is
4677                  * disabled by software override.
4678                  */
4679                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4680                 break;
4681         case ixgbe_fc_full:
4682                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4683                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4684                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4685                 break;
4686         default:
4687                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4688                 ret_val = IXGBE_ERR_CONFIG;
4689                 goto out;
4690         }
4691
4692         /* Set 802.3x based flow control settings. */
4693         mflcn_reg |= IXGBE_MFLCN_DPF;
4694         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4695         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4696
4697         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4698         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4699                 hw->fc.high_water[tc_num]) {
4700                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4701                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4702                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4703         } else {
4704                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4705                 /*
4706                  * In order to prevent Tx hangs when the internal Tx
4707                  * switch is enabled we must set the high water mark
4708                  * to the maximum FCRTH value.  This allows the Tx
4709                  * switch to function even under heavy Rx workloads.
4710                  */
4711                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4712         }
4713         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4714
4715         /* Configure pause time (2 TCs per register) */
4716         reg = hw->fc.pause_time * 0x00010001;
4717         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4718                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4719
4720         /* Configure flow control refresh threshold value */
4721         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4722
4723 out:
4724         return ret_val;
4725 }
4726
4727 static int
4728 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4729 {
4730         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4731         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4732
4733         if (hw->mac.type != ixgbe_mac_82598EB) {
4734                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4735         }
4736         return ret_val;
4737 }
4738
4739 static int
4740 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4741 {
4742         int err;
4743         uint32_t rx_buf_size;
4744         uint32_t max_high_water;
4745         uint8_t tc_num;
4746         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4747         struct ixgbe_hw *hw =
4748                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4749         struct ixgbe_dcb_config *dcb_config =
4750                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4751
4752         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4753                 ixgbe_fc_none,
4754                 ixgbe_fc_rx_pause,
4755                 ixgbe_fc_tx_pause,
4756                 ixgbe_fc_full
4757         };
4758
4759         PMD_INIT_FUNC_TRACE();
4760
4761         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4762         tc_num = map[pfc_conf->priority];
4763         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4764         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4765         /*
4766          * At least reserve one Ethernet frame for watermark
4767          * high_water/low_water in kilo bytes for ixgbe
4768          */
4769         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4770         if ((pfc_conf->fc.high_water > max_high_water) ||
4771             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4772                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4773                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4774                 return -EINVAL;
4775         }
4776
4777         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4778         hw->fc.pause_time = pfc_conf->fc.pause_time;
4779         hw->fc.send_xon = pfc_conf->fc.send_xon;
4780         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4781         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4782
4783         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4784
4785         /* Not negotiated is not an error case */
4786         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4787                 return 0;
4788
4789         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4790         return -EIO;
4791 }
4792
4793 static int
4794 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4795                           struct rte_eth_rss_reta_entry64 *reta_conf,
4796                           uint16_t reta_size)
4797 {
4798         uint16_t i, sp_reta_size;
4799         uint8_t j, mask;
4800         uint32_t reta, r;
4801         uint16_t idx, shift;
4802         struct ixgbe_adapter *adapter =
4803                 (struct ixgbe_adapter *)dev->data->dev_private;
4804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4805         uint32_t reta_reg;
4806
4807         PMD_INIT_FUNC_TRACE();
4808
4809         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4810                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4811                         "NIC.");
4812                 return -ENOTSUP;
4813         }
4814
4815         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4816         if (reta_size != sp_reta_size) {
4817                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4818                         "(%d) doesn't match the number hardware can supported "
4819                         "(%d)", reta_size, sp_reta_size);
4820                 return -EINVAL;
4821         }
4822
4823         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4824                 idx = i / RTE_RETA_GROUP_SIZE;
4825                 shift = i % RTE_RETA_GROUP_SIZE;
4826                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4827                                                 IXGBE_4_BIT_MASK);
4828                 if (!mask)
4829                         continue;
4830                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4831                 if (mask == IXGBE_4_BIT_MASK)
4832                         r = 0;
4833                 else
4834                         r = IXGBE_READ_REG(hw, reta_reg);
4835                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4836                         if (mask & (0x1 << j))
4837                                 reta |= reta_conf[idx].reta[shift + j] <<
4838                                                         (CHAR_BIT * j);
4839                         else
4840                                 reta |= r & (IXGBE_8_BIT_MASK <<
4841                                                 (CHAR_BIT * j));
4842                 }
4843                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4844         }
4845         adapter->rss_reta_updated = 1;
4846
4847         return 0;
4848 }
4849
4850 static int
4851 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4852                          struct rte_eth_rss_reta_entry64 *reta_conf,
4853                          uint16_t reta_size)
4854 {
4855         uint16_t i, sp_reta_size;
4856         uint8_t j, mask;
4857         uint32_t reta;
4858         uint16_t idx, shift;
4859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4860         uint32_t reta_reg;
4861
4862         PMD_INIT_FUNC_TRACE();
4863         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4864         if (reta_size != sp_reta_size) {
4865                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4866                         "(%d) doesn't match the number hardware can supported "
4867                         "(%d)", reta_size, sp_reta_size);
4868                 return -EINVAL;
4869         }
4870
4871         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4872                 idx = i / RTE_RETA_GROUP_SIZE;
4873                 shift = i % RTE_RETA_GROUP_SIZE;
4874                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4875                                                 IXGBE_4_BIT_MASK);
4876                 if (!mask)
4877                         continue;
4878
4879                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4880                 reta = IXGBE_READ_REG(hw, reta_reg);
4881                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4882                         if (mask & (0x1 << j))
4883                                 reta_conf[idx].reta[shift + j] =
4884                                         ((reta >> (CHAR_BIT * j)) &
4885                                                 IXGBE_8_BIT_MASK);
4886                 }
4887         }
4888
4889         return 0;
4890 }
4891
4892 static int
4893 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4894                                 uint32_t index, uint32_t pool)
4895 {
4896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4897         uint32_t enable_addr = 1;
4898
4899         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4900                              pool, enable_addr);
4901 }
4902
4903 static void
4904 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4905 {
4906         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4907
4908         ixgbe_clear_rar(hw, index);
4909 }
4910
4911 static int
4912 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4913 {
4914         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4915
4916         ixgbe_remove_rar(dev, 0);
4917         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4918
4919         return 0;
4920 }
4921
4922 static bool
4923 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4924 {
4925         if (strcmp(dev->device->driver->name, drv->driver.name))
4926                 return false;
4927
4928         return true;
4929 }
4930
4931 bool
4932 is_ixgbe_supported(struct rte_eth_dev *dev)
4933 {
4934         return is_device_supported(dev, &rte_ixgbe_pmd);
4935 }
4936
4937 static int
4938 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4939 {
4940         uint32_t hlreg0;
4941         uint32_t maxfrs;
4942         struct ixgbe_hw *hw;
4943         struct rte_eth_dev_info dev_info;
4944         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
4945         struct rte_eth_dev_data *dev_data = dev->data;
4946
4947         ixgbe_dev_info_get(dev, &dev_info);
4948
4949         /* check that mtu is within the allowed range */
4950         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4951                 return -EINVAL;
4952
4953         /* If device is started, refuse mtu that requires the support of
4954          * scattered packets when this feature has not been enabled before.
4955          */
4956         if (dev_data->dev_started && !dev_data->scattered_rx &&
4957             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4958              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4959                 PMD_INIT_LOG(ERR, "Stop port first.");
4960                 return -EINVAL;
4961         }
4962
4963         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4964         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4965
4966         /* switch to jumbo mode if needed */
4967         if (frame_size > ETHER_MAX_LEN) {
4968                 dev->data->dev_conf.rxmode.offloads |=
4969                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4970                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4971         } else {
4972                 dev->data->dev_conf.rxmode.offloads &=
4973                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4974                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4975         }
4976         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4977
4978         /* update max frame size */
4979         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4980
4981         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4982         maxfrs &= 0x0000FFFF;
4983         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4984         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4985
4986         return 0;
4987 }
4988
4989 /*
4990  * Virtual Function operations
4991  */
4992 static void
4993 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4994 {
4995         struct ixgbe_interrupt *intr =
4996                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4997         struct ixgbe_hw *hw =
4998                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4999
5000         PMD_INIT_FUNC_TRACE();
5001
5002         /* Clear interrupt mask to stop from interrupts being generated */
5003         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5004
5005         IXGBE_WRITE_FLUSH(hw);
5006
5007         /* Clear mask value. */
5008         intr->mask = 0;
5009 }
5010
5011 static void
5012 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5013 {
5014         struct ixgbe_interrupt *intr =
5015                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5016         struct ixgbe_hw *hw =
5017                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5018
5019         PMD_INIT_FUNC_TRACE();
5020
5021         /* VF enable interrupt autoclean */
5022         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5023         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5024         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5025
5026         IXGBE_WRITE_FLUSH(hw);
5027
5028         /* Save IXGBE_VTEIMS value to mask. */
5029         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5030 }
5031
5032 static int
5033 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5034 {
5035         struct rte_eth_conf *conf = &dev->data->dev_conf;
5036         struct ixgbe_adapter *adapter =
5037                         (struct ixgbe_adapter *)dev->data->dev_private;
5038
5039         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5040                      dev->data->port_id);
5041
5042         /*
5043          * VF has no ability to enable/disable HW CRC
5044          * Keep the persistent behavior the same as Host PF
5045          */
5046 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5047         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5048                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5049                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5050         }
5051 #else
5052         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5053                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5054                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5055         }
5056 #endif
5057
5058         /*
5059          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5060          * allocation or vector Rx preconditions we will reset it.
5061          */
5062         adapter->rx_bulk_alloc_allowed = true;
5063         adapter->rx_vec_allowed = true;
5064
5065         return 0;
5066 }
5067
5068 static int
5069 ixgbevf_dev_start(struct rte_eth_dev *dev)
5070 {
5071         struct ixgbe_hw *hw =
5072                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073         uint32_t intr_vector = 0;
5074         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5075         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5076
5077         int err, mask = 0;
5078
5079         PMD_INIT_FUNC_TRACE();
5080
5081         /* Stop the link setup handler before resetting the HW. */
5082         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5083
5084         err = hw->mac.ops.reset_hw(hw);
5085         if (err) {
5086                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5087                 return err;
5088         }
5089         hw->mac.get_link_status = true;
5090
5091         /* negotiate mailbox API version to use with the PF. */
5092         ixgbevf_negotiate_api(hw);
5093
5094         ixgbevf_dev_tx_init(dev);
5095
5096         /* This can fail when allocating mbufs for descriptor rings */
5097         err = ixgbevf_dev_rx_init(dev);
5098         if (err) {
5099                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5100                 ixgbe_dev_clear_queues(dev);
5101                 return err;
5102         }
5103
5104         /* Set vfta */
5105         ixgbevf_set_vfta_all(dev, 1);
5106
5107         /* Set HW strip */
5108         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5109                 ETH_VLAN_EXTEND_MASK;
5110         err = ixgbevf_vlan_offload_config(dev, mask);
5111         if (err) {
5112                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5113                 ixgbe_dev_clear_queues(dev);
5114                 return err;
5115         }
5116
5117         ixgbevf_dev_rxtx_start(dev);
5118
5119         /* check and configure queue intr-vector mapping */
5120         if (rte_intr_cap_multiple(intr_handle) &&
5121             dev->data->dev_conf.intr_conf.rxq) {
5122                 /* According to datasheet, only vector 0/1/2 can be used,
5123                  * now only one vector is used for Rx queue
5124                  */
5125                 intr_vector = 1;
5126                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5127                         return -1;
5128         }
5129
5130         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5131                 intr_handle->intr_vec =
5132                         rte_zmalloc("intr_vec",
5133                                     dev->data->nb_rx_queues * sizeof(int), 0);
5134                 if (intr_handle->intr_vec == NULL) {
5135                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5136                                      " intr_vec", dev->data->nb_rx_queues);
5137                         return -ENOMEM;
5138                 }
5139         }
5140         ixgbevf_configure_msix(dev);
5141
5142         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5143          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5144          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5145          * is not cleared, it will fail when following rte_intr_enable( ) tries
5146          * to map Rx queue interrupt to other VFIO vectors.
5147          * So clear uio/vfio intr/evevnfd first to avoid failure.
5148          */
5149         rte_intr_disable(intr_handle);
5150
5151         rte_intr_enable(intr_handle);
5152
5153         /* Re-enable interrupt for VF */
5154         ixgbevf_intr_enable(dev);
5155
5156         /*
5157          * Update link status right before return, because it may
5158          * start link configuration process in a separate thread.
5159          */
5160         ixgbevf_dev_link_update(dev, 0);
5161
5162         return 0;
5163 }
5164
5165 static void
5166 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5167 {
5168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5169         struct ixgbe_adapter *adapter =
5170                 (struct ixgbe_adapter *)dev->data->dev_private;
5171         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5172         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5173
5174         PMD_INIT_FUNC_TRACE();
5175
5176         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5177
5178         ixgbevf_intr_disable(dev);
5179
5180         hw->adapter_stopped = 1;
5181         ixgbe_stop_adapter(hw);
5182
5183         /*
5184           * Clear what we set, but we still keep shadow_vfta to
5185           * restore after device starts
5186           */
5187         ixgbevf_set_vfta_all(dev, 0);
5188
5189         /* Clear stored conf */
5190         dev->data->scattered_rx = 0;
5191
5192         ixgbe_dev_clear_queues(dev);
5193
5194         /* Clean datapath event and queue/vec mapping */
5195         rte_intr_efd_disable(intr_handle);
5196         if (intr_handle->intr_vec != NULL) {
5197                 rte_free(intr_handle->intr_vec);
5198                 intr_handle->intr_vec = NULL;
5199         }
5200
5201         adapter->rss_reta_updated = 0;
5202 }
5203
5204 static void
5205 ixgbevf_dev_close(struct rte_eth_dev *dev)
5206 {
5207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5208
5209         PMD_INIT_FUNC_TRACE();
5210
5211         ixgbe_reset_hw(hw);
5212
5213         ixgbevf_dev_stop(dev);
5214
5215         ixgbe_dev_free_queues(dev);
5216
5217         /**
5218          * Remove the VF MAC address ro ensure
5219          * that the VF traffic goes to the PF
5220          * after stop, close and detach of the VF
5221          **/
5222         ixgbevf_remove_mac_addr(dev, 0);
5223 }
5224
5225 /*
5226  * Reset VF device
5227  */
5228 static int
5229 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5230 {
5231         int ret;
5232
5233         ret = eth_ixgbevf_dev_uninit(dev);
5234         if (ret)
5235                 return ret;
5236
5237         ret = eth_ixgbevf_dev_init(dev);
5238
5239         return ret;
5240 }
5241
5242 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5243 {
5244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5245         struct ixgbe_vfta *shadow_vfta =
5246                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5247         int i = 0, j = 0, vfta = 0, mask = 1;
5248
5249         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5250                 vfta = shadow_vfta->vfta[i];
5251                 if (vfta) {
5252                         mask = 1;
5253                         for (j = 0; j < 32; j++) {
5254                                 if (vfta & mask)
5255                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5256                                                        on, false);
5257                                 mask <<= 1;
5258                         }
5259                 }
5260         }
5261
5262 }
5263
5264 static int
5265 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5266 {
5267         struct ixgbe_hw *hw =
5268                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5269         struct ixgbe_vfta *shadow_vfta =
5270                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5271         uint32_t vid_idx = 0;
5272         uint32_t vid_bit = 0;
5273         int ret = 0;
5274
5275         PMD_INIT_FUNC_TRACE();
5276
5277         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5278         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5279         if (ret) {
5280                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5281                 return ret;
5282         }
5283         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5284         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5285
5286         /* Save what we set and retore it after device reset */
5287         if (on)
5288                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5289         else
5290                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5291
5292         return 0;
5293 }
5294
5295 static void
5296 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5297 {
5298         struct ixgbe_hw *hw =
5299                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5300         uint32_t ctrl;
5301
5302         PMD_INIT_FUNC_TRACE();
5303
5304         if (queue >= hw->mac.max_rx_queues)
5305                 return;
5306
5307         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5308         if (on)
5309                 ctrl |= IXGBE_RXDCTL_VME;
5310         else
5311                 ctrl &= ~IXGBE_RXDCTL_VME;
5312         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5313
5314         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5315 }
5316
5317 static int
5318 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5319 {
5320         struct ixgbe_rx_queue *rxq;
5321         uint16_t i;
5322         int on = 0;
5323
5324         /* VF function only support hw strip feature, others are not support */
5325         if (mask & ETH_VLAN_STRIP_MASK) {
5326                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5327                         rxq = dev->data->rx_queues[i];
5328                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5329                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5330                 }
5331         }
5332
5333         return 0;
5334 }
5335
5336 static int
5337 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5338 {
5339         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5340
5341         ixgbevf_vlan_offload_config(dev, mask);
5342
5343         return 0;
5344 }
5345
5346 int
5347 ixgbe_vt_check(struct ixgbe_hw *hw)
5348 {
5349         uint32_t reg_val;
5350
5351         /* if Virtualization Technology is enabled */
5352         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5353         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5354                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5355                 return -1;
5356         }
5357
5358         return 0;
5359 }
5360
5361 static uint32_t
5362 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5363 {
5364         uint32_t vector = 0;
5365
5366         switch (hw->mac.mc_filter_type) {
5367         case 0:   /* use bits [47:36] of the address */
5368                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5369                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5370                 break;
5371         case 1:   /* use bits [46:35] of the address */
5372                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5373                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5374                 break;
5375         case 2:   /* use bits [45:34] of the address */
5376                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5377                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5378                 break;
5379         case 3:   /* use bits [43:32] of the address */
5380                 vector = ((uc_addr->addr_bytes[4]) |
5381                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5382                 break;
5383         default:  /* Invalid mc_filter_type */
5384                 break;
5385         }
5386
5387         /* vector can only be 12-bits or boundary will be exceeded */
5388         vector &= 0xFFF;
5389         return vector;
5390 }
5391
5392 static int
5393 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5394                         uint8_t on)
5395 {
5396         uint32_t vector;
5397         uint32_t uta_idx;
5398         uint32_t reg_val;
5399         uint32_t uta_shift;
5400         uint32_t rc;
5401         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5402         const uint32_t ixgbe_uta_bit_shift = 5;
5403         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5404         const uint32_t bit1 = 0x1;
5405
5406         struct ixgbe_hw *hw =
5407                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5408         struct ixgbe_uta_info *uta_info =
5409                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5410
5411         /* The UTA table only exists on 82599 hardware and newer */
5412         if (hw->mac.type < ixgbe_mac_82599EB)
5413                 return -ENOTSUP;
5414
5415         vector = ixgbe_uta_vector(hw, mac_addr);
5416         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5417         uta_shift = vector & ixgbe_uta_bit_mask;
5418
5419         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5420         if (rc == on)
5421                 return 0;
5422
5423         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5424         if (on) {
5425                 uta_info->uta_in_use++;
5426                 reg_val |= (bit1 << uta_shift);
5427                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5428         } else {
5429                 uta_info->uta_in_use--;
5430                 reg_val &= ~(bit1 << uta_shift);
5431                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5432         }
5433
5434         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5435
5436         if (uta_info->uta_in_use > 0)
5437                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5438                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5439         else
5440                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5441
5442         return 0;
5443 }
5444
5445 static int
5446 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5447 {
5448         int i;
5449         struct ixgbe_hw *hw =
5450                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5451         struct ixgbe_uta_info *uta_info =
5452                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5453
5454         /* The UTA table only exists on 82599 hardware and newer */
5455         if (hw->mac.type < ixgbe_mac_82599EB)
5456                 return -ENOTSUP;
5457
5458         if (on) {
5459                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5460                         uta_info->uta_shadow[i] = ~0;
5461                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5462                 }
5463         } else {
5464                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5465                         uta_info->uta_shadow[i] = 0;
5466                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5467                 }
5468         }
5469         return 0;
5470
5471 }
5472
5473 uint32_t
5474 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5475 {
5476         uint32_t new_val = orig_val;
5477
5478         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5479                 new_val |= IXGBE_VMOLR_AUPE;
5480         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5481                 new_val |= IXGBE_VMOLR_ROMPE;
5482         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5483                 new_val |= IXGBE_VMOLR_ROPE;
5484         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5485                 new_val |= IXGBE_VMOLR_BAM;
5486         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5487                 new_val |= IXGBE_VMOLR_MPE;
5488
5489         return new_val;
5490 }
5491
5492 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5493 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5494 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5495 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5496 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5497         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5498         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5499
5500 static int
5501 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5502                       struct rte_eth_mirror_conf *mirror_conf,
5503                       uint8_t rule_id, uint8_t on)
5504 {
5505         uint32_t mr_ctl, vlvf;
5506         uint32_t mp_lsb = 0;
5507         uint32_t mv_msb = 0;
5508         uint32_t mv_lsb = 0;
5509         uint32_t mp_msb = 0;
5510         uint8_t i = 0;
5511         int reg_index = 0;
5512         uint64_t vlan_mask = 0;
5513
5514         const uint8_t pool_mask_offset = 32;
5515         const uint8_t vlan_mask_offset = 32;
5516         const uint8_t dst_pool_offset = 8;
5517         const uint8_t rule_mr_offset  = 4;
5518         const uint8_t mirror_rule_mask = 0x0F;
5519
5520         struct ixgbe_mirror_info *mr_info =
5521                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5522         struct ixgbe_hw *hw =
5523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5524         uint8_t mirror_type = 0;
5525
5526         if (ixgbe_vt_check(hw) < 0)
5527                 return -ENOTSUP;
5528
5529         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5530                 return -EINVAL;
5531
5532         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5533                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5534                             mirror_conf->rule_type);
5535                 return -EINVAL;
5536         }
5537
5538         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5539                 mirror_type |= IXGBE_MRCTL_VLME;
5540                 /* Check if vlan id is valid and find conresponding VLAN ID
5541                  * index in VLVF
5542                  */
5543                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5544                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5545                                 /* search vlan id related pool vlan filter
5546                                  * index
5547                                  */
5548                                 reg_index = ixgbe_find_vlvf_slot(
5549                                                 hw,
5550                                                 mirror_conf->vlan.vlan_id[i],
5551                                                 false);
5552                                 if (reg_index < 0)
5553                                         return -EINVAL;
5554                                 vlvf = IXGBE_READ_REG(hw,
5555                                                       IXGBE_VLVF(reg_index));
5556                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5557                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5558                                       mirror_conf->vlan.vlan_id[i]))
5559                                         vlan_mask |= (1ULL << reg_index);
5560                                 else
5561                                         return -EINVAL;
5562                         }
5563                 }
5564
5565                 if (on) {
5566                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5567                         mv_msb = vlan_mask >> vlan_mask_offset;
5568
5569                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5570                                                 mirror_conf->vlan.vlan_mask;
5571                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5572                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5573                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5574                                                 mirror_conf->vlan.vlan_id[i];
5575                         }
5576                 } else {
5577                         mv_lsb = 0;
5578                         mv_msb = 0;
5579                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5580                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5581                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5582                 }
5583         }
5584
5585         /**
5586          * if enable pool mirror, write related pool mask register,if disable
5587          * pool mirror, clear PFMRVM register
5588          */
5589         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5590                 mirror_type |= IXGBE_MRCTL_VPME;
5591                 if (on) {
5592                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5593                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5594                         mr_info->mr_conf[rule_id].pool_mask =
5595                                         mirror_conf->pool_mask;
5596
5597                 } else {
5598                         mp_lsb = 0;
5599                         mp_msb = 0;
5600                         mr_info->mr_conf[rule_id].pool_mask = 0;
5601                 }
5602         }
5603         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5604                 mirror_type |= IXGBE_MRCTL_UPME;
5605         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5606                 mirror_type |= IXGBE_MRCTL_DPME;
5607
5608         /* read  mirror control register and recalculate it */
5609         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5610
5611         if (on) {
5612                 mr_ctl |= mirror_type;
5613                 mr_ctl &= mirror_rule_mask;
5614                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5615         } else {
5616                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5617         }
5618
5619         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5620         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5621
5622         /* write mirrror control  register */
5623         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5624
5625         /* write pool mirrror control  register */
5626         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5627                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5628                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5629                                 mp_msb);
5630         }
5631         /* write VLAN mirrror control  register */
5632         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5633                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5634                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5635                                 mv_msb);
5636         }
5637
5638         return 0;
5639 }
5640
5641 static int
5642 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5643 {
5644         int mr_ctl = 0;
5645         uint32_t lsb_val = 0;
5646         uint32_t msb_val = 0;
5647         const uint8_t rule_mr_offset = 4;
5648
5649         struct ixgbe_hw *hw =
5650                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5651         struct ixgbe_mirror_info *mr_info =
5652                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5653
5654         if (ixgbe_vt_check(hw) < 0)
5655                 return -ENOTSUP;
5656
5657         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5658                 return -EINVAL;
5659
5660         memset(&mr_info->mr_conf[rule_id], 0,
5661                sizeof(struct rte_eth_mirror_conf));
5662
5663         /* clear PFVMCTL register */
5664         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5665
5666         /* clear pool mask register */
5667         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5668         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5669
5670         /* clear vlan mask register */
5671         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5672         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5673
5674         return 0;
5675 }
5676
5677 static int
5678 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5679 {
5680         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5681         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5682         struct ixgbe_interrupt *intr =
5683                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5684         struct ixgbe_hw *hw =
5685                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5686         uint32_t vec = IXGBE_MISC_VEC_ID;
5687
5688         if (rte_intr_allow_others(intr_handle))
5689                 vec = IXGBE_RX_VEC_START;
5690         intr->mask |= (1 << vec);
5691         RTE_SET_USED(queue_id);
5692         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5693
5694         rte_intr_enable(intr_handle);
5695
5696         return 0;
5697 }
5698
5699 static int
5700 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5701 {
5702         struct ixgbe_interrupt *intr =
5703                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5704         struct ixgbe_hw *hw =
5705                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5706         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5707         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5708         uint32_t vec = IXGBE_MISC_VEC_ID;
5709
5710         if (rte_intr_allow_others(intr_handle))
5711                 vec = IXGBE_RX_VEC_START;
5712         intr->mask &= ~(1 << vec);
5713         RTE_SET_USED(queue_id);
5714         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5715
5716         return 0;
5717 }
5718
5719 static int
5720 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5721 {
5722         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5723         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5724         uint32_t mask;
5725         struct ixgbe_hw *hw =
5726                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5727         struct ixgbe_interrupt *intr =
5728                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5729
5730         if (queue_id < 16) {
5731                 ixgbe_disable_intr(hw);
5732                 intr->mask |= (1 << queue_id);
5733                 ixgbe_enable_intr(dev);
5734         } else if (queue_id < 32) {
5735                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5736                 mask &= (1 << queue_id);
5737                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5738         } else if (queue_id < 64) {
5739                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5740                 mask &= (1 << (queue_id - 32));
5741                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5742         }
5743         rte_intr_enable(intr_handle);
5744
5745         return 0;
5746 }
5747
5748 static int
5749 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5750 {
5751         uint32_t mask;
5752         struct ixgbe_hw *hw =
5753                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5754         struct ixgbe_interrupt *intr =
5755                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5756
5757         if (queue_id < 16) {
5758                 ixgbe_disable_intr(hw);
5759                 intr->mask &= ~(1 << queue_id);
5760                 ixgbe_enable_intr(dev);
5761         } else if (queue_id < 32) {
5762                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5763                 mask &= ~(1 << queue_id);
5764                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5765         } else if (queue_id < 64) {
5766                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5767                 mask &= ~(1 << (queue_id - 32));
5768                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5769         }
5770
5771         return 0;
5772 }
5773
5774 static void
5775 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5776                      uint8_t queue, uint8_t msix_vector)
5777 {
5778         uint32_t tmp, idx;
5779
5780         if (direction == -1) {
5781                 /* other causes */
5782                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5783                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5784                 tmp &= ~0xFF;
5785                 tmp |= msix_vector;
5786                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5787         } else {
5788                 /* rx or tx cause */
5789                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5790                 idx = ((16 * (queue & 1)) + (8 * direction));
5791                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5792                 tmp &= ~(0xFF << idx);
5793                 tmp |= (msix_vector << idx);
5794                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5795         }
5796 }
5797
5798 /**
5799  * set the IVAR registers, mapping interrupt causes to vectors
5800  * @param hw
5801  *  pointer to ixgbe_hw struct
5802  * @direction
5803  *  0 for Rx, 1 for Tx, -1 for other causes
5804  * @queue
5805  *  queue to map the corresponding interrupt to
5806  * @msix_vector
5807  *  the vector to map to the corresponding queue
5808  */
5809 static void
5810 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5811                    uint8_t queue, uint8_t msix_vector)
5812 {
5813         uint32_t tmp, idx;
5814
5815         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5816         if (hw->mac.type == ixgbe_mac_82598EB) {
5817                 if (direction == -1)
5818                         direction = 0;
5819                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5820                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5821                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5822                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5823                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5824         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5825                         (hw->mac.type == ixgbe_mac_X540) ||
5826                         (hw->mac.type == ixgbe_mac_X550)) {
5827                 if (direction == -1) {
5828                         /* other causes */
5829                         idx = ((queue & 1) * 8);
5830                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5831                         tmp &= ~(0xFF << idx);
5832                         tmp |= (msix_vector << idx);
5833                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5834                 } else {
5835                         /* rx or tx causes */
5836                         idx = ((16 * (queue & 1)) + (8 * direction));
5837                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5838                         tmp &= ~(0xFF << idx);
5839                         tmp |= (msix_vector << idx);
5840                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5841                 }
5842         }
5843 }
5844
5845 static void
5846 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5847 {
5848         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5849         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5850         struct ixgbe_hw *hw =
5851                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5852         uint32_t q_idx;
5853         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5854         uint32_t base = IXGBE_MISC_VEC_ID;
5855
5856         /* Configure VF other cause ivar */
5857         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5858
5859         /* won't configure msix register if no mapping is done
5860          * between intr vector and event fd.
5861          */
5862         if (!rte_intr_dp_is_en(intr_handle))
5863                 return;
5864
5865         if (rte_intr_allow_others(intr_handle)) {
5866                 base = IXGBE_RX_VEC_START;
5867                 vector_idx = IXGBE_RX_VEC_START;
5868         }
5869
5870         /* Configure all RX queues of VF */
5871         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5872                 /* Force all queue use vector 0,
5873                  * as IXGBE_VF_MAXMSIVECOTR = 1
5874                  */
5875                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5876                 intr_handle->intr_vec[q_idx] = vector_idx;
5877                 if (vector_idx < base + intr_handle->nb_efd - 1)
5878                         vector_idx++;
5879         }
5880
5881         /* As RX queue setting above show, all queues use the vector 0.
5882          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5883          */
5884         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5885                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5886                         | IXGBE_EITR_CNT_WDIS);
5887 }
5888
5889 /**
5890  * Sets up the hardware to properly generate MSI-X interrupts
5891  * @hw
5892  *  board private structure
5893  */
5894 static void
5895 ixgbe_configure_msix(struct rte_eth_dev *dev)
5896 {
5897         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5898         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5899         struct ixgbe_hw *hw =
5900                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5901         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5902         uint32_t vec = IXGBE_MISC_VEC_ID;
5903         uint32_t mask;
5904         uint32_t gpie;
5905
5906         /* won't configure msix register if no mapping is done
5907          * between intr vector and event fd
5908          * but if misx has been enabled already, need to configure
5909          * auto clean, auto mask and throttling.
5910          */
5911         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5912         if (!rte_intr_dp_is_en(intr_handle) &&
5913             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5914                 return;
5915
5916         if (rte_intr_allow_others(intr_handle))
5917                 vec = base = IXGBE_RX_VEC_START;
5918
5919         /* setup GPIE for MSI-x mode */
5920         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5921         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5922                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5923         /* auto clearing and auto setting corresponding bits in EIMS
5924          * when MSI-X interrupt is triggered
5925          */
5926         if (hw->mac.type == ixgbe_mac_82598EB) {
5927                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5928         } else {
5929                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5930                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5931         }
5932         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5933
5934         /* Populate the IVAR table and set the ITR values to the
5935          * corresponding register.
5936          */
5937         if (rte_intr_dp_is_en(intr_handle)) {
5938                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5939                         queue_id++) {
5940                         /* by default, 1:1 mapping */
5941                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5942                         intr_handle->intr_vec[queue_id] = vec;
5943                         if (vec < base + intr_handle->nb_efd - 1)
5944                                 vec++;
5945                 }
5946
5947                 switch (hw->mac.type) {
5948                 case ixgbe_mac_82598EB:
5949                         ixgbe_set_ivar_map(hw, -1,
5950                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5951                                            IXGBE_MISC_VEC_ID);
5952                         break;
5953                 case ixgbe_mac_82599EB:
5954                 case ixgbe_mac_X540:
5955                 case ixgbe_mac_X550:
5956                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5957                         break;
5958                 default:
5959                         break;
5960                 }
5961         }
5962         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5963                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5964                         | IXGBE_EITR_CNT_WDIS);
5965
5966         /* set up to autoclear timer, and the vectors */
5967         mask = IXGBE_EIMS_ENABLE_MASK;
5968         mask &= ~(IXGBE_EIMS_OTHER |
5969                   IXGBE_EIMS_MAILBOX |
5970                   IXGBE_EIMS_LSC);
5971
5972         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5973 }
5974
5975 int
5976 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5977                            uint16_t queue_idx, uint16_t tx_rate)
5978 {
5979         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5980         struct rte_eth_rxmode *rxmode;
5981         uint32_t rf_dec, rf_int;
5982         uint32_t bcnrc_val;
5983         uint16_t link_speed = dev->data->dev_link.link_speed;
5984
5985         if (queue_idx >= hw->mac.max_tx_queues)
5986                 return -EINVAL;
5987
5988         if (tx_rate != 0) {
5989                 /* Calculate the rate factor values to set */
5990                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5991                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5992                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5993
5994                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5995                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5996                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5997                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5998         } else {
5999                 bcnrc_val = 0;
6000         }
6001
6002         rxmode = &dev->data->dev_conf.rxmode;
6003         /*
6004          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6005          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6006          * set as 0x4.
6007          */
6008         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6009             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6010                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6011                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6012         else
6013                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6014                         IXGBE_MMW_SIZE_DEFAULT);
6015
6016         /* Set RTTBCNRC of queue X */
6017         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6018         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6019         IXGBE_WRITE_FLUSH(hw);
6020
6021         return 0;
6022 }
6023
6024 static int
6025 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
6026                      __attribute__((unused)) uint32_t index,
6027                      __attribute__((unused)) uint32_t pool)
6028 {
6029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6030         int diag;
6031
6032         /*
6033          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6034          * operation. Trap this case to avoid exhausting the [very limited]
6035          * set of PF resources used to store VF MAC addresses.
6036          */
6037         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6038                 return -1;
6039         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6040         if (diag != 0)
6041                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6042                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6043                             mac_addr->addr_bytes[0],
6044                             mac_addr->addr_bytes[1],
6045                             mac_addr->addr_bytes[2],
6046                             mac_addr->addr_bytes[3],
6047                             mac_addr->addr_bytes[4],
6048                             mac_addr->addr_bytes[5],
6049                             diag);
6050         return diag;
6051 }
6052
6053 static void
6054 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6055 {
6056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6057         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6058         struct ether_addr *mac_addr;
6059         uint32_t i;
6060         int diag;
6061
6062         /*
6063          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6064          * not support the deletion of a given MAC address.
6065          * Instead, it imposes to delete all MAC addresses, then to add again
6066          * all MAC addresses with the exception of the one to be deleted.
6067          */
6068         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6069
6070         /*
6071          * Add again all MAC addresses, with the exception of the deleted one
6072          * and of the permanent MAC address.
6073          */
6074         for (i = 0, mac_addr = dev->data->mac_addrs;
6075              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6076                 /* Skip the deleted MAC address */
6077                 if (i == index)
6078                         continue;
6079                 /* Skip NULL MAC addresses */
6080                 if (is_zero_ether_addr(mac_addr))
6081                         continue;
6082                 /* Skip the permanent MAC address */
6083                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6084                         continue;
6085                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6086                 if (diag != 0)
6087                         PMD_DRV_LOG(ERR,
6088                                     "Adding again MAC address "
6089                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6090                                     "diag=%d",
6091                                     mac_addr->addr_bytes[0],
6092                                     mac_addr->addr_bytes[1],
6093                                     mac_addr->addr_bytes[2],
6094                                     mac_addr->addr_bytes[3],
6095                                     mac_addr->addr_bytes[4],
6096                                     mac_addr->addr_bytes[5],
6097                                     diag);
6098         }
6099 }
6100
6101 static int
6102 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6103 {
6104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6105
6106         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6107
6108         return 0;
6109 }
6110
6111 int
6112 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6113                         struct rte_eth_syn_filter *filter,
6114                         bool add)
6115 {
6116         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6117         struct ixgbe_filter_info *filter_info =
6118                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6119         uint32_t syn_info;
6120         uint32_t synqf;
6121
6122         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6123                 return -EINVAL;
6124
6125         syn_info = filter_info->syn_info;
6126
6127         if (add) {
6128                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6129                         return -EINVAL;
6130                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6131                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6132
6133                 if (filter->hig_pri)
6134                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6135                 else
6136                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6137         } else {
6138                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6139                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6140                         return -ENOENT;
6141                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6142         }
6143
6144         filter_info->syn_info = synqf;
6145         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6146         IXGBE_WRITE_FLUSH(hw);
6147         return 0;
6148 }
6149
6150 static int
6151 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6152                         struct rte_eth_syn_filter *filter)
6153 {
6154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6156
6157         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6158                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6159                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6160                 return 0;
6161         }
6162         return -ENOENT;
6163 }
6164
6165 static int
6166 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6167                         enum rte_filter_op filter_op,
6168                         void *arg)
6169 {
6170         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6171         int ret;
6172
6173         MAC_TYPE_FILTER_SUP(hw->mac.type);
6174
6175         if (filter_op == RTE_ETH_FILTER_NOP)
6176                 return 0;
6177
6178         if (arg == NULL) {
6179                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6180                             filter_op);
6181                 return -EINVAL;
6182         }
6183
6184         switch (filter_op) {
6185         case RTE_ETH_FILTER_ADD:
6186                 ret = ixgbe_syn_filter_set(dev,
6187                                 (struct rte_eth_syn_filter *)arg,
6188                                 TRUE);
6189                 break;
6190         case RTE_ETH_FILTER_DELETE:
6191                 ret = ixgbe_syn_filter_set(dev,
6192                                 (struct rte_eth_syn_filter *)arg,
6193                                 FALSE);
6194                 break;
6195         case RTE_ETH_FILTER_GET:
6196                 ret = ixgbe_syn_filter_get(dev,
6197                                 (struct rte_eth_syn_filter *)arg);
6198                 break;
6199         default:
6200                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6201                 ret = -EINVAL;
6202                 break;
6203         }
6204
6205         return ret;
6206 }
6207
6208
6209 static inline enum ixgbe_5tuple_protocol
6210 convert_protocol_type(uint8_t protocol_value)
6211 {
6212         if (protocol_value == IPPROTO_TCP)
6213                 return IXGBE_FILTER_PROTOCOL_TCP;
6214         else if (protocol_value == IPPROTO_UDP)
6215                 return IXGBE_FILTER_PROTOCOL_UDP;
6216         else if (protocol_value == IPPROTO_SCTP)
6217                 return IXGBE_FILTER_PROTOCOL_SCTP;
6218         else
6219                 return IXGBE_FILTER_PROTOCOL_NONE;
6220 }
6221
6222 /* inject a 5-tuple filter to HW */
6223 static inline void
6224 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6225                            struct ixgbe_5tuple_filter *filter)
6226 {
6227         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6228         int i;
6229         uint32_t ftqf, sdpqf;
6230         uint32_t l34timir = 0;
6231         uint8_t mask = 0xff;
6232
6233         i = filter->index;
6234
6235         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6236                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6237         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6238
6239         ftqf = (uint32_t)(filter->filter_info.proto &
6240                 IXGBE_FTQF_PROTOCOL_MASK);
6241         ftqf |= (uint32_t)((filter->filter_info.priority &
6242                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6243         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6244                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6245         if (filter->filter_info.dst_ip_mask == 0)
6246                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6247         if (filter->filter_info.src_port_mask == 0)
6248                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6249         if (filter->filter_info.dst_port_mask == 0)
6250                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6251         if (filter->filter_info.proto_mask == 0)
6252                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6253         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6254         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6255         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6256
6257         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6258         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6259         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6260         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6261
6262         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6263         l34timir |= (uint32_t)(filter->queue <<
6264                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6265         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6266 }
6267
6268 /*
6269  * add a 5tuple filter
6270  *
6271  * @param
6272  * dev: Pointer to struct rte_eth_dev.
6273  * index: the index the filter allocates.
6274  * filter: ponter to the filter that will be added.
6275  * rx_queue: the queue id the filter assigned to.
6276  *
6277  * @return
6278  *    - On success, zero.
6279  *    - On failure, a negative value.
6280  */
6281 static int
6282 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6283                         struct ixgbe_5tuple_filter *filter)
6284 {
6285         struct ixgbe_filter_info *filter_info =
6286                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6287         int i, idx, shift;
6288
6289         /*
6290          * look for an unused 5tuple filter index,
6291          * and insert the filter to list.
6292          */
6293         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6294                 idx = i / (sizeof(uint32_t) * NBBY);
6295                 shift = i % (sizeof(uint32_t) * NBBY);
6296                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6297                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6298                         filter->index = i;
6299                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6300                                           filter,
6301                                           entries);
6302                         break;
6303                 }
6304         }
6305         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6306                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6307                 return -ENOSYS;
6308         }
6309
6310         ixgbe_inject_5tuple_filter(dev, filter);
6311
6312         return 0;
6313 }
6314
6315 /*
6316  * remove a 5tuple filter
6317  *
6318  * @param
6319  * dev: Pointer to struct rte_eth_dev.
6320  * filter: the pointer of the filter will be removed.
6321  */
6322 static void
6323 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6324                         struct ixgbe_5tuple_filter *filter)
6325 {
6326         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6327         struct ixgbe_filter_info *filter_info =
6328                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6329         uint16_t index = filter->index;
6330
6331         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6332                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6333         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6334         rte_free(filter);
6335
6336         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6337         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6338         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6339         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6340         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6341 }
6342
6343 static int
6344 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6345 {
6346         struct ixgbe_hw *hw;
6347         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6348         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6349
6350         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6351
6352         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6353                 return -EINVAL;
6354
6355         /* refuse mtu that requires the support of scattered packets when this
6356          * feature has not been enabled before.
6357          */
6358         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6359             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6360              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6361                 return -EINVAL;
6362
6363         /*
6364          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6365          * request of the version 2.0 of the mailbox API.
6366          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6367          * of the mailbox API.
6368          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6369          * prior to 3.11.33 which contains the following change:
6370          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6371          */
6372         ixgbevf_rlpml_set_vf(hw, max_frame);
6373
6374         /* update max frame size */
6375         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6376         return 0;
6377 }
6378
6379 static inline struct ixgbe_5tuple_filter *
6380 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6381                         struct ixgbe_5tuple_filter_info *key)
6382 {
6383         struct ixgbe_5tuple_filter *it;
6384
6385         TAILQ_FOREACH(it, filter_list, entries) {
6386                 if (memcmp(key, &it->filter_info,
6387                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6388                         return it;
6389                 }
6390         }
6391         return NULL;
6392 }
6393
6394 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6395 static inline int
6396 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6397                         struct ixgbe_5tuple_filter_info *filter_info)
6398 {
6399         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6400                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6401                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6402                 return -EINVAL;
6403
6404         switch (filter->dst_ip_mask) {
6405         case UINT32_MAX:
6406                 filter_info->dst_ip_mask = 0;
6407                 filter_info->dst_ip = filter->dst_ip;
6408                 break;
6409         case 0:
6410                 filter_info->dst_ip_mask = 1;
6411                 break;
6412         default:
6413                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6414                 return -EINVAL;
6415         }
6416
6417         switch (filter->src_ip_mask) {
6418         case UINT32_MAX:
6419                 filter_info->src_ip_mask = 0;
6420                 filter_info->src_ip = filter->src_ip;
6421                 break;
6422         case 0:
6423                 filter_info->src_ip_mask = 1;
6424                 break;
6425         default:
6426                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6427                 return -EINVAL;
6428         }
6429
6430         switch (filter->dst_port_mask) {
6431         case UINT16_MAX:
6432                 filter_info->dst_port_mask = 0;
6433                 filter_info->dst_port = filter->dst_port;
6434                 break;
6435         case 0:
6436                 filter_info->dst_port_mask = 1;
6437                 break;
6438         default:
6439                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6440                 return -EINVAL;
6441         }
6442
6443         switch (filter->src_port_mask) {
6444         case UINT16_MAX:
6445                 filter_info->src_port_mask = 0;
6446                 filter_info->src_port = filter->src_port;
6447                 break;
6448         case 0:
6449                 filter_info->src_port_mask = 1;
6450                 break;
6451         default:
6452                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6453                 return -EINVAL;
6454         }
6455
6456         switch (filter->proto_mask) {
6457         case UINT8_MAX:
6458                 filter_info->proto_mask = 0;
6459                 filter_info->proto =
6460                         convert_protocol_type(filter->proto);
6461                 break;
6462         case 0:
6463                 filter_info->proto_mask = 1;
6464                 break;
6465         default:
6466                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6467                 return -EINVAL;
6468         }
6469
6470         filter_info->priority = (uint8_t)filter->priority;
6471         return 0;
6472 }
6473
6474 /*
6475  * add or delete a ntuple filter
6476  *
6477  * @param
6478  * dev: Pointer to struct rte_eth_dev.
6479  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6480  * add: if true, add filter, if false, remove filter
6481  *
6482  * @return
6483  *    - On success, zero.
6484  *    - On failure, a negative value.
6485  */
6486 int
6487 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6488                         struct rte_eth_ntuple_filter *ntuple_filter,
6489                         bool add)
6490 {
6491         struct ixgbe_filter_info *filter_info =
6492                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6493         struct ixgbe_5tuple_filter_info filter_5tuple;
6494         struct ixgbe_5tuple_filter *filter;
6495         int ret;
6496
6497         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6498                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6499                 return -EINVAL;
6500         }
6501
6502         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6503         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6504         if (ret < 0)
6505                 return ret;
6506
6507         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6508                                          &filter_5tuple);
6509         if (filter != NULL && add) {
6510                 PMD_DRV_LOG(ERR, "filter exists.");
6511                 return -EEXIST;
6512         }
6513         if (filter == NULL && !add) {
6514                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6515                 return -ENOENT;
6516         }
6517
6518         if (add) {
6519                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6520                                 sizeof(struct ixgbe_5tuple_filter), 0);
6521                 if (filter == NULL)
6522                         return -ENOMEM;
6523                 rte_memcpy(&filter->filter_info,
6524                                  &filter_5tuple,
6525                                  sizeof(struct ixgbe_5tuple_filter_info));
6526                 filter->queue = ntuple_filter->queue;
6527                 ret = ixgbe_add_5tuple_filter(dev, filter);
6528                 if (ret < 0) {
6529                         rte_free(filter);
6530                         return ret;
6531                 }
6532         } else
6533                 ixgbe_remove_5tuple_filter(dev, filter);
6534
6535         return 0;
6536 }
6537
6538 /*
6539  * get a ntuple filter
6540  *
6541  * @param
6542  * dev: Pointer to struct rte_eth_dev.
6543  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6544  *
6545  * @return
6546  *    - On success, zero.
6547  *    - On failure, a negative value.
6548  */
6549 static int
6550 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6551                         struct rte_eth_ntuple_filter *ntuple_filter)
6552 {
6553         struct ixgbe_filter_info *filter_info =
6554                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6555         struct ixgbe_5tuple_filter_info filter_5tuple;
6556         struct ixgbe_5tuple_filter *filter;
6557         int ret;
6558
6559         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6560                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6561                 return -EINVAL;
6562         }
6563
6564         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6565         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6566         if (ret < 0)
6567                 return ret;
6568
6569         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6570                                          &filter_5tuple);
6571         if (filter == NULL) {
6572                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6573                 return -ENOENT;
6574         }
6575         ntuple_filter->queue = filter->queue;
6576         return 0;
6577 }
6578
6579 /*
6580  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6581  * @dev: pointer to rte_eth_dev structure
6582  * @filter_op:operation will be taken.
6583  * @arg: a pointer to specific structure corresponding to the filter_op
6584  *
6585  * @return
6586  *    - On success, zero.
6587  *    - On failure, a negative value.
6588  */
6589 static int
6590 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6591                                 enum rte_filter_op filter_op,
6592                                 void *arg)
6593 {
6594         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6595         int ret;
6596
6597         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6598
6599         if (filter_op == RTE_ETH_FILTER_NOP)
6600                 return 0;
6601
6602         if (arg == NULL) {
6603                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6604                             filter_op);
6605                 return -EINVAL;
6606         }
6607
6608         switch (filter_op) {
6609         case RTE_ETH_FILTER_ADD:
6610                 ret = ixgbe_add_del_ntuple_filter(dev,
6611                         (struct rte_eth_ntuple_filter *)arg,
6612                         TRUE);
6613                 break;
6614         case RTE_ETH_FILTER_DELETE:
6615                 ret = ixgbe_add_del_ntuple_filter(dev,
6616                         (struct rte_eth_ntuple_filter *)arg,
6617                         FALSE);
6618                 break;
6619         case RTE_ETH_FILTER_GET:
6620                 ret = ixgbe_get_ntuple_filter(dev,
6621                         (struct rte_eth_ntuple_filter *)arg);
6622                 break;
6623         default:
6624                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6625                 ret = -EINVAL;
6626                 break;
6627         }
6628         return ret;
6629 }
6630
6631 int
6632 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6633                         struct rte_eth_ethertype_filter *filter,
6634                         bool add)
6635 {
6636         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6637         struct ixgbe_filter_info *filter_info =
6638                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6639         uint32_t etqf = 0;
6640         uint32_t etqs = 0;
6641         int ret;
6642         struct ixgbe_ethertype_filter ethertype_filter;
6643
6644         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6645                 return -EINVAL;
6646
6647         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6648                 filter->ether_type == ETHER_TYPE_IPv6) {
6649                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6650                         " ethertype filter.", filter->ether_type);
6651                 return -EINVAL;
6652         }
6653
6654         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6655                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6656                 return -EINVAL;
6657         }
6658         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6659                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6660                 return -EINVAL;
6661         }
6662
6663         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6664         if (ret >= 0 && add) {
6665                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6666                             filter->ether_type);
6667                 return -EEXIST;
6668         }
6669         if (ret < 0 && !add) {
6670                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6671                             filter->ether_type);
6672                 return -ENOENT;
6673         }
6674
6675         if (add) {
6676                 etqf = IXGBE_ETQF_FILTER_EN;
6677                 etqf |= (uint32_t)filter->ether_type;
6678                 etqs |= (uint32_t)((filter->queue <<
6679                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6680                                     IXGBE_ETQS_RX_QUEUE);
6681                 etqs |= IXGBE_ETQS_QUEUE_EN;
6682
6683                 ethertype_filter.ethertype = filter->ether_type;
6684                 ethertype_filter.etqf = etqf;
6685                 ethertype_filter.etqs = etqs;
6686                 ethertype_filter.conf = FALSE;
6687                 ret = ixgbe_ethertype_filter_insert(filter_info,
6688                                                     &ethertype_filter);
6689                 if (ret < 0) {
6690                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6691                         return -ENOSPC;
6692                 }
6693         } else {
6694                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6695                 if (ret < 0)
6696                         return -ENOSYS;
6697         }
6698         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6699         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6700         IXGBE_WRITE_FLUSH(hw);
6701
6702         return 0;
6703 }
6704
6705 static int
6706 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6707                         struct rte_eth_ethertype_filter *filter)
6708 {
6709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6710         struct ixgbe_filter_info *filter_info =
6711                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6712         uint32_t etqf, etqs;
6713         int ret;
6714
6715         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6716         if (ret < 0) {
6717                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6718                             filter->ether_type);
6719                 return -ENOENT;
6720         }
6721
6722         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6723         if (etqf & IXGBE_ETQF_FILTER_EN) {
6724                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6725                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6726                 filter->flags = 0;
6727                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6728                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6729                 return 0;
6730         }
6731         return -ENOENT;
6732 }
6733
6734 /*
6735  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6736  * @dev: pointer to rte_eth_dev structure
6737  * @filter_op:operation will be taken.
6738  * @arg: a pointer to specific structure corresponding to the filter_op
6739  */
6740 static int
6741 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6742                                 enum rte_filter_op filter_op,
6743                                 void *arg)
6744 {
6745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6746         int ret;
6747
6748         MAC_TYPE_FILTER_SUP(hw->mac.type);
6749
6750         if (filter_op == RTE_ETH_FILTER_NOP)
6751                 return 0;
6752
6753         if (arg == NULL) {
6754                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6755                             filter_op);
6756                 return -EINVAL;
6757         }
6758
6759         switch (filter_op) {
6760         case RTE_ETH_FILTER_ADD:
6761                 ret = ixgbe_add_del_ethertype_filter(dev,
6762                         (struct rte_eth_ethertype_filter *)arg,
6763                         TRUE);
6764                 break;
6765         case RTE_ETH_FILTER_DELETE:
6766                 ret = ixgbe_add_del_ethertype_filter(dev,
6767                         (struct rte_eth_ethertype_filter *)arg,
6768                         FALSE);
6769                 break;
6770         case RTE_ETH_FILTER_GET:
6771                 ret = ixgbe_get_ethertype_filter(dev,
6772                         (struct rte_eth_ethertype_filter *)arg);
6773                 break;
6774         default:
6775                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6776                 ret = -EINVAL;
6777                 break;
6778         }
6779         return ret;
6780 }
6781
6782 static int
6783 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6784                      enum rte_filter_type filter_type,
6785                      enum rte_filter_op filter_op,
6786                      void *arg)
6787 {
6788         int ret = 0;
6789
6790         switch (filter_type) {
6791         case RTE_ETH_FILTER_NTUPLE:
6792                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6793                 break;
6794         case RTE_ETH_FILTER_ETHERTYPE:
6795                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6796                 break;
6797         case RTE_ETH_FILTER_SYN:
6798                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6799                 break;
6800         case RTE_ETH_FILTER_FDIR:
6801                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6802                 break;
6803         case RTE_ETH_FILTER_L2_TUNNEL:
6804                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6805                 break;
6806         case RTE_ETH_FILTER_GENERIC:
6807                 if (filter_op != RTE_ETH_FILTER_GET)
6808                         return -EINVAL;
6809                 *(const void **)arg = &ixgbe_flow_ops;
6810                 break;
6811         default:
6812                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6813                                                         filter_type);
6814                 ret = -EINVAL;
6815                 break;
6816         }
6817
6818         return ret;
6819 }
6820
6821 static u8 *
6822 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6823                         u8 **mc_addr_ptr, u32 *vmdq)
6824 {
6825         u8 *mc_addr;
6826
6827         *vmdq = 0;
6828         mc_addr = *mc_addr_ptr;
6829         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6830         return mc_addr;
6831 }
6832
6833 static int
6834 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6835                           struct ether_addr *mc_addr_set,
6836                           uint32_t nb_mc_addr)
6837 {
6838         struct ixgbe_hw *hw;
6839         u8 *mc_addr_list;
6840
6841         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6842         mc_addr_list = (u8 *)mc_addr_set;
6843         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6844                                          ixgbe_dev_addr_list_itr, TRUE);
6845 }
6846
6847 static uint64_t
6848 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6849 {
6850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6851         uint64_t systime_cycles;
6852
6853         switch (hw->mac.type) {
6854         case ixgbe_mac_X550:
6855         case ixgbe_mac_X550EM_x:
6856         case ixgbe_mac_X550EM_a:
6857                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6858                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6859                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6860                                 * NSEC_PER_SEC;
6861                 break;
6862         default:
6863                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6864                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6865                                 << 32;
6866         }
6867
6868         return systime_cycles;
6869 }
6870
6871 static uint64_t
6872 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6873 {
6874         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6875         uint64_t rx_tstamp_cycles;
6876
6877         switch (hw->mac.type) {
6878         case ixgbe_mac_X550:
6879         case ixgbe_mac_X550EM_x:
6880         case ixgbe_mac_X550EM_a:
6881                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6882                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6883                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6884                                 * NSEC_PER_SEC;
6885                 break;
6886         default:
6887                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6888                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6889                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6890                                 << 32;
6891         }
6892
6893         return rx_tstamp_cycles;
6894 }
6895
6896 static uint64_t
6897 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6898 {
6899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6900         uint64_t tx_tstamp_cycles;
6901
6902         switch (hw->mac.type) {
6903         case ixgbe_mac_X550:
6904         case ixgbe_mac_X550EM_x:
6905         case ixgbe_mac_X550EM_a:
6906                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6907                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6908                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6909                                 * NSEC_PER_SEC;
6910                 break;
6911         default:
6912                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6913                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6914                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6915                                 << 32;
6916         }
6917
6918         return tx_tstamp_cycles;
6919 }
6920
6921 static void
6922 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6923 {
6924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6925         struct ixgbe_adapter *adapter =
6926                 (struct ixgbe_adapter *)dev->data->dev_private;
6927         struct rte_eth_link link;
6928         uint32_t incval = 0;
6929         uint32_t shift = 0;
6930
6931         /* Get current link speed. */
6932         ixgbe_dev_link_update(dev, 1);
6933         rte_eth_linkstatus_get(dev, &link);
6934
6935         switch (link.link_speed) {
6936         case ETH_SPEED_NUM_100M:
6937                 incval = IXGBE_INCVAL_100;
6938                 shift = IXGBE_INCVAL_SHIFT_100;
6939                 break;
6940         case ETH_SPEED_NUM_1G:
6941                 incval = IXGBE_INCVAL_1GB;
6942                 shift = IXGBE_INCVAL_SHIFT_1GB;
6943                 break;
6944         case ETH_SPEED_NUM_10G:
6945         default:
6946                 incval = IXGBE_INCVAL_10GB;
6947                 shift = IXGBE_INCVAL_SHIFT_10GB;
6948                 break;
6949         }
6950
6951         switch (hw->mac.type) {
6952         case ixgbe_mac_X550:
6953         case ixgbe_mac_X550EM_x:
6954         case ixgbe_mac_X550EM_a:
6955                 /* Independent of link speed. */
6956                 incval = 1;
6957                 /* Cycles read will be interpreted as ns. */
6958                 shift = 0;
6959                 /* Fall-through */
6960         case ixgbe_mac_X540:
6961                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6962                 break;
6963         case ixgbe_mac_82599EB:
6964                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6965                 shift -= IXGBE_INCVAL_SHIFT_82599;
6966                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6967                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6968                 break;
6969         default:
6970                 /* Not supported. */
6971                 return;
6972         }
6973
6974         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6975         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6976         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6977
6978         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6979         adapter->systime_tc.cc_shift = shift;
6980         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6981
6982         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6983         adapter->rx_tstamp_tc.cc_shift = shift;
6984         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6985
6986         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6987         adapter->tx_tstamp_tc.cc_shift = shift;
6988         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6989 }
6990
6991 static int
6992 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6993 {
6994         struct ixgbe_adapter *adapter =
6995                         (struct ixgbe_adapter *)dev->data->dev_private;
6996
6997         adapter->systime_tc.nsec += delta;
6998         adapter->rx_tstamp_tc.nsec += delta;
6999         adapter->tx_tstamp_tc.nsec += delta;
7000
7001         return 0;
7002 }
7003
7004 static int
7005 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7006 {
7007         uint64_t ns;
7008         struct ixgbe_adapter *adapter =
7009                         (struct ixgbe_adapter *)dev->data->dev_private;
7010
7011         ns = rte_timespec_to_ns(ts);
7012         /* Set the timecounters to a new value. */
7013         adapter->systime_tc.nsec = ns;
7014         adapter->rx_tstamp_tc.nsec = ns;
7015         adapter->tx_tstamp_tc.nsec = ns;
7016
7017         return 0;
7018 }
7019
7020 static int
7021 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7022 {
7023         uint64_t ns, systime_cycles;
7024         struct ixgbe_adapter *adapter =
7025                         (struct ixgbe_adapter *)dev->data->dev_private;
7026
7027         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7028         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7029         *ts = rte_ns_to_timespec(ns);
7030
7031         return 0;
7032 }
7033
7034 static int
7035 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7036 {
7037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7038         uint32_t tsync_ctl;
7039         uint32_t tsauxc;
7040
7041         /* Stop the timesync system time. */
7042         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7043         /* Reset the timesync system time value. */
7044         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7045         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7046
7047         /* Enable system time for platforms where it isn't on by default. */
7048         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7049         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7050         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7051
7052         ixgbe_start_timecounters(dev);
7053
7054         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7055         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7056                         (ETHER_TYPE_1588 |
7057                          IXGBE_ETQF_FILTER_EN |
7058                          IXGBE_ETQF_1588));
7059
7060         /* Enable timestamping of received PTP packets. */
7061         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7062         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7063         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7064
7065         /* Enable timestamping of transmitted PTP packets. */
7066         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7067         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7068         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7069
7070         IXGBE_WRITE_FLUSH(hw);
7071
7072         return 0;
7073 }
7074
7075 static int
7076 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7077 {
7078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7079         uint32_t tsync_ctl;
7080
7081         /* Disable timestamping of transmitted PTP packets. */
7082         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7083         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7084         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7085
7086         /* Disable timestamping of received PTP packets. */
7087         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7088         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7089         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7090
7091         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7092         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7093
7094         /* Stop incrementating the System Time registers. */
7095         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7096
7097         return 0;
7098 }
7099
7100 static int
7101 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7102                                  struct timespec *timestamp,
7103                                  uint32_t flags __rte_unused)
7104 {
7105         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7106         struct ixgbe_adapter *adapter =
7107                 (struct ixgbe_adapter *)dev->data->dev_private;
7108         uint32_t tsync_rxctl;
7109         uint64_t rx_tstamp_cycles;
7110         uint64_t ns;
7111
7112         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7113         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7114                 return -EINVAL;
7115
7116         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7117         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7118         *timestamp = rte_ns_to_timespec(ns);
7119
7120         return  0;
7121 }
7122
7123 static int
7124 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7125                                  struct timespec *timestamp)
7126 {
7127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7128         struct ixgbe_adapter *adapter =
7129                 (struct ixgbe_adapter *)dev->data->dev_private;
7130         uint32_t tsync_txctl;
7131         uint64_t tx_tstamp_cycles;
7132         uint64_t ns;
7133
7134         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7135         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7136                 return -EINVAL;
7137
7138         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7139         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7140         *timestamp = rte_ns_to_timespec(ns);
7141
7142         return 0;
7143 }
7144
7145 static int
7146 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7147 {
7148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7149         int count = 0;
7150         int g_ind = 0;
7151         const struct reg_info *reg_group;
7152         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7153                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7154
7155         while ((reg_group = reg_set[g_ind++]))
7156                 count += ixgbe_regs_group_count(reg_group);
7157
7158         return count;
7159 }
7160
7161 static int
7162 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7163 {
7164         int count = 0;
7165         int g_ind = 0;
7166         const struct reg_info *reg_group;
7167
7168         while ((reg_group = ixgbevf_regs[g_ind++]))
7169                 count += ixgbe_regs_group_count(reg_group);
7170
7171         return count;
7172 }
7173
7174 static int
7175 ixgbe_get_regs(struct rte_eth_dev *dev,
7176               struct rte_dev_reg_info *regs)
7177 {
7178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7179         uint32_t *data = regs->data;
7180         int g_ind = 0;
7181         int count = 0;
7182         const struct reg_info *reg_group;
7183         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7184                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7185
7186         if (data == NULL) {
7187                 regs->length = ixgbe_get_reg_length(dev);
7188                 regs->width = sizeof(uint32_t);
7189                 return 0;
7190         }
7191
7192         /* Support only full register dump */
7193         if ((regs->length == 0) ||
7194             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7195                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7196                         hw->device_id;
7197                 while ((reg_group = reg_set[g_ind++]))
7198                         count += ixgbe_read_regs_group(dev, &data[count],
7199                                 reg_group);
7200                 return 0;
7201         }
7202
7203         return -ENOTSUP;
7204 }
7205
7206 static int
7207 ixgbevf_get_regs(struct rte_eth_dev *dev,
7208                 struct rte_dev_reg_info *regs)
7209 {
7210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7211         uint32_t *data = regs->data;
7212         int g_ind = 0;
7213         int count = 0;
7214         const struct reg_info *reg_group;
7215
7216         if (data == NULL) {
7217                 regs->length = ixgbevf_get_reg_length(dev);
7218                 regs->width = sizeof(uint32_t);
7219                 return 0;
7220         }
7221
7222         /* Support only full register dump */
7223         if ((regs->length == 0) ||
7224             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7225                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7226                         hw->device_id;
7227                 while ((reg_group = ixgbevf_regs[g_ind++]))
7228                         count += ixgbe_read_regs_group(dev, &data[count],
7229                                                       reg_group);
7230                 return 0;
7231         }
7232
7233         return -ENOTSUP;
7234 }
7235
7236 static int
7237 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7238 {
7239         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7240
7241         /* Return unit is byte count */
7242         return hw->eeprom.word_size * 2;
7243 }
7244
7245 static int
7246 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7247                 struct rte_dev_eeprom_info *in_eeprom)
7248 {
7249         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7250         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7251         uint16_t *data = in_eeprom->data;
7252         int first, length;
7253
7254         first = in_eeprom->offset >> 1;
7255         length = in_eeprom->length >> 1;
7256         if ((first > hw->eeprom.word_size) ||
7257             ((first + length) > hw->eeprom.word_size))
7258                 return -EINVAL;
7259
7260         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7261
7262         return eeprom->ops.read_buffer(hw, first, length, data);
7263 }
7264
7265 static int
7266 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7267                 struct rte_dev_eeprom_info *in_eeprom)
7268 {
7269         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7270         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7271         uint16_t *data = in_eeprom->data;
7272         int first, length;
7273
7274         first = in_eeprom->offset >> 1;
7275         length = in_eeprom->length >> 1;
7276         if ((first > hw->eeprom.word_size) ||
7277             ((first + length) > hw->eeprom.word_size))
7278                 return -EINVAL;
7279
7280         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7281
7282         return eeprom->ops.write_buffer(hw,  first, length, data);
7283 }
7284
7285 static int
7286 ixgbe_get_module_info(struct rte_eth_dev *dev,
7287                       struct rte_eth_dev_module_info *modinfo)
7288 {
7289         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7290         uint32_t status;
7291         uint8_t sff8472_rev, addr_mode;
7292         bool page_swap = false;
7293
7294         /* Check whether we support SFF-8472 or not */
7295         status = hw->phy.ops.read_i2c_eeprom(hw,
7296                                              IXGBE_SFF_SFF_8472_COMP,
7297                                              &sff8472_rev);
7298         if (status != 0)
7299                 return -EIO;
7300
7301         /* addressing mode is not supported */
7302         status = hw->phy.ops.read_i2c_eeprom(hw,
7303                                              IXGBE_SFF_SFF_8472_SWAP,
7304                                              &addr_mode);
7305         if (status != 0)
7306                 return -EIO;
7307
7308         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7309                 PMD_DRV_LOG(ERR,
7310                             "Address change required to access page 0xA2, "
7311                             "but not supported. Please report the module "
7312                             "type to the driver maintainers.");
7313                 page_swap = true;
7314         }
7315
7316         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7317                 /* We have a SFP, but it does not support SFF-8472 */
7318                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7319                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7320         } else {
7321                 /* We have a SFP which supports a revision of SFF-8472. */
7322                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7323                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7324         }
7325
7326         return 0;
7327 }
7328
7329 static int
7330 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7331                         struct rte_dev_eeprom_info *info)
7332 {
7333         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7334         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7335         uint8_t databyte = 0xFF;
7336         uint8_t *data = info->data;
7337         uint32_t i = 0;
7338
7339         if (info->length == 0)
7340                 return -EINVAL;
7341
7342         for (i = info->offset; i < info->offset + info->length; i++) {
7343                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7344                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7345                 else
7346                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7347
7348                 if (status != 0)
7349                         return -EIO;
7350
7351                 data[i - info->offset] = databyte;
7352         }
7353
7354         return 0;
7355 }
7356
7357 uint16_t
7358 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7359         switch (mac_type) {
7360         case ixgbe_mac_X550:
7361         case ixgbe_mac_X550EM_x:
7362         case ixgbe_mac_X550EM_a:
7363                 return ETH_RSS_RETA_SIZE_512;
7364         case ixgbe_mac_X550_vf:
7365         case ixgbe_mac_X550EM_x_vf:
7366         case ixgbe_mac_X550EM_a_vf:
7367                 return ETH_RSS_RETA_SIZE_64;
7368         default:
7369                 return ETH_RSS_RETA_SIZE_128;
7370         }
7371 }
7372
7373 uint32_t
7374 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7375         switch (mac_type) {
7376         case ixgbe_mac_X550:
7377         case ixgbe_mac_X550EM_x:
7378         case ixgbe_mac_X550EM_a:
7379                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7380                         return IXGBE_RETA(reta_idx >> 2);
7381                 else
7382                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7383         case ixgbe_mac_X550_vf:
7384         case ixgbe_mac_X550EM_x_vf:
7385         case ixgbe_mac_X550EM_a_vf:
7386                 return IXGBE_VFRETA(reta_idx >> 2);
7387         default:
7388                 return IXGBE_RETA(reta_idx >> 2);
7389         }
7390 }
7391
7392 uint32_t
7393 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7394         switch (mac_type) {
7395         case ixgbe_mac_X550_vf:
7396         case ixgbe_mac_X550EM_x_vf:
7397         case ixgbe_mac_X550EM_a_vf:
7398                 return IXGBE_VFMRQC;
7399         default:
7400                 return IXGBE_MRQC;
7401         }
7402 }
7403
7404 uint32_t
7405 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7406         switch (mac_type) {
7407         case ixgbe_mac_X550_vf:
7408         case ixgbe_mac_X550EM_x_vf:
7409         case ixgbe_mac_X550EM_a_vf:
7410                 return IXGBE_VFRSSRK(i);
7411         default:
7412                 return IXGBE_RSSRK(i);
7413         }
7414 }
7415
7416 bool
7417 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7418         switch (mac_type) {
7419         case ixgbe_mac_82599_vf:
7420         case ixgbe_mac_X540_vf:
7421                 return 0;
7422         default:
7423                 return 1;
7424         }
7425 }
7426
7427 static int
7428 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7429                         struct rte_eth_dcb_info *dcb_info)
7430 {
7431         struct ixgbe_dcb_config *dcb_config =
7432                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7433         struct ixgbe_dcb_tc_config *tc;
7434         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7435         uint8_t nb_tcs;
7436         uint8_t i, j;
7437
7438         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7439                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7440         else
7441                 dcb_info->nb_tcs = 1;
7442
7443         tc_queue = &dcb_info->tc_queue;
7444         nb_tcs = dcb_info->nb_tcs;
7445
7446         if (dcb_config->vt_mode) { /* vt is enabled*/
7447                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7448                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7449                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7450                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7451                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7452                         for (j = 0; j < nb_tcs; j++) {
7453                                 tc_queue->tc_rxq[0][j].base = j;
7454                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7455                                 tc_queue->tc_txq[0][j].base = j;
7456                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7457                         }
7458                 } else {
7459                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7460                                 for (j = 0; j < nb_tcs; j++) {
7461                                         tc_queue->tc_rxq[i][j].base =
7462                                                 i * nb_tcs + j;
7463                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7464                                         tc_queue->tc_txq[i][j].base =
7465                                                 i * nb_tcs + j;
7466                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7467                                 }
7468                         }
7469                 }
7470         } else { /* vt is disabled*/
7471                 struct rte_eth_dcb_rx_conf *rx_conf =
7472                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7473                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7474                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7475                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7476                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7477                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7478                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7479                         }
7480                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7481                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7482                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7483                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7484                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7485                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7486                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7487                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7488                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7489                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7490                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7491                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7492                         }
7493                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7494                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7495                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7496                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7497                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7498                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7499                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7500                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7501                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7502                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7503                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7504                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7505                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7506                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7507                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7508                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7509                 }
7510         }
7511         for (i = 0; i < dcb_info->nb_tcs; i++) {
7512                 tc = &dcb_config->tc_config[i];
7513                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7514         }
7515         return 0;
7516 }
7517
7518 /* Update e-tag ether type */
7519 static int
7520 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7521                             uint16_t ether_type)
7522 {
7523         uint32_t etag_etype;
7524
7525         if (hw->mac.type != ixgbe_mac_X550 &&
7526             hw->mac.type != ixgbe_mac_X550EM_x &&
7527             hw->mac.type != ixgbe_mac_X550EM_a) {
7528                 return -ENOTSUP;
7529         }
7530
7531         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7532         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7533         etag_etype |= ether_type;
7534         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7535         IXGBE_WRITE_FLUSH(hw);
7536
7537         return 0;
7538 }
7539
7540 /* Config l2 tunnel ether type */
7541 static int
7542 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7543                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7544 {
7545         int ret = 0;
7546         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7547         struct ixgbe_l2_tn_info *l2_tn_info =
7548                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7549
7550         if (l2_tunnel == NULL)
7551                 return -EINVAL;
7552
7553         switch (l2_tunnel->l2_tunnel_type) {
7554         case RTE_L2_TUNNEL_TYPE_E_TAG:
7555                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7556                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7557                 break;
7558         default:
7559                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7560                 ret = -EINVAL;
7561                 break;
7562         }
7563
7564         return ret;
7565 }
7566
7567 /* Enable e-tag tunnel */
7568 static int
7569 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7570 {
7571         uint32_t etag_etype;
7572
7573         if (hw->mac.type != ixgbe_mac_X550 &&
7574             hw->mac.type != ixgbe_mac_X550EM_x &&
7575             hw->mac.type != ixgbe_mac_X550EM_a) {
7576                 return -ENOTSUP;
7577         }
7578
7579         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7580         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7581         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7582         IXGBE_WRITE_FLUSH(hw);
7583
7584         return 0;
7585 }
7586
7587 /* Enable l2 tunnel */
7588 static int
7589 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7590                            enum rte_eth_tunnel_type l2_tunnel_type)
7591 {
7592         int ret = 0;
7593         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7594         struct ixgbe_l2_tn_info *l2_tn_info =
7595                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7596
7597         switch (l2_tunnel_type) {
7598         case RTE_L2_TUNNEL_TYPE_E_TAG:
7599                 l2_tn_info->e_tag_en = TRUE;
7600                 ret = ixgbe_e_tag_enable(hw);
7601                 break;
7602         default:
7603                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7604                 ret = -EINVAL;
7605                 break;
7606         }
7607
7608         return ret;
7609 }
7610
7611 /* Disable e-tag tunnel */
7612 static int
7613 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7614 {
7615         uint32_t etag_etype;
7616
7617         if (hw->mac.type != ixgbe_mac_X550 &&
7618             hw->mac.type != ixgbe_mac_X550EM_x &&
7619             hw->mac.type != ixgbe_mac_X550EM_a) {
7620                 return -ENOTSUP;
7621         }
7622
7623         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7624         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7625         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7626         IXGBE_WRITE_FLUSH(hw);
7627
7628         return 0;
7629 }
7630
7631 /* Disable l2 tunnel */
7632 static int
7633 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7634                             enum rte_eth_tunnel_type l2_tunnel_type)
7635 {
7636         int ret = 0;
7637         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7638         struct ixgbe_l2_tn_info *l2_tn_info =
7639                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7640
7641         switch (l2_tunnel_type) {
7642         case RTE_L2_TUNNEL_TYPE_E_TAG:
7643                 l2_tn_info->e_tag_en = FALSE;
7644                 ret = ixgbe_e_tag_disable(hw);
7645                 break;
7646         default:
7647                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7648                 ret = -EINVAL;
7649                 break;
7650         }
7651
7652         return ret;
7653 }
7654
7655 static int
7656 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7657                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7658 {
7659         int ret = 0;
7660         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7661         uint32_t i, rar_entries;
7662         uint32_t rar_low, rar_high;
7663
7664         if (hw->mac.type != ixgbe_mac_X550 &&
7665             hw->mac.type != ixgbe_mac_X550EM_x &&
7666             hw->mac.type != ixgbe_mac_X550EM_a) {
7667                 return -ENOTSUP;
7668         }
7669
7670         rar_entries = ixgbe_get_num_rx_addrs(hw);
7671
7672         for (i = 1; i < rar_entries; i++) {
7673                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7674                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7675                 if ((rar_high & IXGBE_RAH_AV) &&
7676                     (rar_high & IXGBE_RAH_ADTYPE) &&
7677                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7678                      l2_tunnel->tunnel_id)) {
7679                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7680                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7681
7682                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7683
7684                         return ret;
7685                 }
7686         }
7687
7688         return ret;
7689 }
7690
7691 static int
7692 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7693                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7694 {
7695         int ret = 0;
7696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7697         uint32_t i, rar_entries;
7698         uint32_t rar_low, rar_high;
7699
7700         if (hw->mac.type != ixgbe_mac_X550 &&
7701             hw->mac.type != ixgbe_mac_X550EM_x &&
7702             hw->mac.type != ixgbe_mac_X550EM_a) {
7703                 return -ENOTSUP;
7704         }
7705
7706         /* One entry for one tunnel. Try to remove potential existing entry. */
7707         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7708
7709         rar_entries = ixgbe_get_num_rx_addrs(hw);
7710
7711         for (i = 1; i < rar_entries; i++) {
7712                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7713                 if (rar_high & IXGBE_RAH_AV) {
7714                         continue;
7715                 } else {
7716                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7717                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7718                         rar_low = l2_tunnel->tunnel_id;
7719
7720                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7721                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7722
7723                         return ret;
7724                 }
7725         }
7726
7727         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7728                      " Please remove a rule before adding a new one.");
7729         return -EINVAL;
7730 }
7731
7732 static inline struct ixgbe_l2_tn_filter *
7733 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7734                           struct ixgbe_l2_tn_key *key)
7735 {
7736         int ret;
7737
7738         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7739         if (ret < 0)
7740                 return NULL;
7741
7742         return l2_tn_info->hash_map[ret];
7743 }
7744
7745 static inline int
7746 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7747                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7748 {
7749         int ret;
7750
7751         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7752                                &l2_tn_filter->key);
7753
7754         if (ret < 0) {
7755                 PMD_DRV_LOG(ERR,
7756                             "Failed to insert L2 tunnel filter"
7757                             " to hash table %d!",
7758                             ret);
7759                 return ret;
7760         }
7761
7762         l2_tn_info->hash_map[ret] = l2_tn_filter;
7763
7764         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7765
7766         return 0;
7767 }
7768
7769 static inline int
7770 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7771                           struct ixgbe_l2_tn_key *key)
7772 {
7773         int ret;
7774         struct ixgbe_l2_tn_filter *l2_tn_filter;
7775
7776         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7777
7778         if (ret < 0) {
7779                 PMD_DRV_LOG(ERR,
7780                             "No such L2 tunnel filter to delete %d!",
7781                             ret);
7782                 return ret;
7783         }
7784
7785         l2_tn_filter = l2_tn_info->hash_map[ret];
7786         l2_tn_info->hash_map[ret] = NULL;
7787
7788         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7789         rte_free(l2_tn_filter);
7790
7791         return 0;
7792 }
7793
7794 /* Add l2 tunnel filter */
7795 int
7796 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7797                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7798                                bool restore)
7799 {
7800         int ret;
7801         struct ixgbe_l2_tn_info *l2_tn_info =
7802                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7803         struct ixgbe_l2_tn_key key;
7804         struct ixgbe_l2_tn_filter *node;
7805
7806         if (!restore) {
7807                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7808                 key.tn_id = l2_tunnel->tunnel_id;
7809
7810                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7811
7812                 if (node) {
7813                         PMD_DRV_LOG(ERR,
7814                                     "The L2 tunnel filter already exists!");
7815                         return -EINVAL;
7816                 }
7817
7818                 node = rte_zmalloc("ixgbe_l2_tn",
7819                                    sizeof(struct ixgbe_l2_tn_filter),
7820                                    0);
7821                 if (!node)
7822                         return -ENOMEM;
7823
7824                 rte_memcpy(&node->key,
7825                                  &key,
7826                                  sizeof(struct ixgbe_l2_tn_key));
7827                 node->pool = l2_tunnel->pool;
7828                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7829                 if (ret < 0) {
7830                         rte_free(node);
7831                         return ret;
7832                 }
7833         }
7834
7835         switch (l2_tunnel->l2_tunnel_type) {
7836         case RTE_L2_TUNNEL_TYPE_E_TAG:
7837                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7838                 break;
7839         default:
7840                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7841                 ret = -EINVAL;
7842                 break;
7843         }
7844
7845         if ((!restore) && (ret < 0))
7846                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7847
7848         return ret;
7849 }
7850
7851 /* Delete l2 tunnel filter */
7852 int
7853 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7854                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7855 {
7856         int ret;
7857         struct ixgbe_l2_tn_info *l2_tn_info =
7858                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7859         struct ixgbe_l2_tn_key key;
7860
7861         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7862         key.tn_id = l2_tunnel->tunnel_id;
7863         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7864         if (ret < 0)
7865                 return ret;
7866
7867         switch (l2_tunnel->l2_tunnel_type) {
7868         case RTE_L2_TUNNEL_TYPE_E_TAG:
7869                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7870                 break;
7871         default:
7872                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7873                 ret = -EINVAL;
7874                 break;
7875         }
7876
7877         return ret;
7878 }
7879
7880 /**
7881  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7882  * @dev: pointer to rte_eth_dev structure
7883  * @filter_op:operation will be taken.
7884  * @arg: a pointer to specific structure corresponding to the filter_op
7885  */
7886 static int
7887 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7888                                   enum rte_filter_op filter_op,
7889                                   void *arg)
7890 {
7891         int ret;
7892
7893         if (filter_op == RTE_ETH_FILTER_NOP)
7894                 return 0;
7895
7896         if (arg == NULL) {
7897                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7898                             filter_op);
7899                 return -EINVAL;
7900         }
7901
7902         switch (filter_op) {
7903         case RTE_ETH_FILTER_ADD:
7904                 ret = ixgbe_dev_l2_tunnel_filter_add
7905                         (dev,
7906                          (struct rte_eth_l2_tunnel_conf *)arg,
7907                          FALSE);
7908                 break;
7909         case RTE_ETH_FILTER_DELETE:
7910                 ret = ixgbe_dev_l2_tunnel_filter_del
7911                         (dev,
7912                          (struct rte_eth_l2_tunnel_conf *)arg);
7913                 break;
7914         default:
7915                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7916                 ret = -EINVAL;
7917                 break;
7918         }
7919         return ret;
7920 }
7921
7922 static int
7923 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7924 {
7925         int ret = 0;
7926         uint32_t ctrl;
7927         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7928
7929         if (hw->mac.type != ixgbe_mac_X550 &&
7930             hw->mac.type != ixgbe_mac_X550EM_x &&
7931             hw->mac.type != ixgbe_mac_X550EM_a) {
7932                 return -ENOTSUP;
7933         }
7934
7935         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7936         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7937         if (en)
7938                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7939         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7940
7941         return ret;
7942 }
7943
7944 /* Enable l2 tunnel forwarding */
7945 static int
7946 ixgbe_dev_l2_tunnel_forwarding_enable
7947         (struct rte_eth_dev *dev,
7948          enum rte_eth_tunnel_type l2_tunnel_type)
7949 {
7950         struct ixgbe_l2_tn_info *l2_tn_info =
7951                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7952         int ret = 0;
7953
7954         switch (l2_tunnel_type) {
7955         case RTE_L2_TUNNEL_TYPE_E_TAG:
7956                 l2_tn_info->e_tag_fwd_en = TRUE;
7957                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7958                 break;
7959         default:
7960                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7961                 ret = -EINVAL;
7962                 break;
7963         }
7964
7965         return ret;
7966 }
7967
7968 /* Disable l2 tunnel forwarding */
7969 static int
7970 ixgbe_dev_l2_tunnel_forwarding_disable
7971         (struct rte_eth_dev *dev,
7972          enum rte_eth_tunnel_type l2_tunnel_type)
7973 {
7974         struct ixgbe_l2_tn_info *l2_tn_info =
7975                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7976         int ret = 0;
7977
7978         switch (l2_tunnel_type) {
7979         case RTE_L2_TUNNEL_TYPE_E_TAG:
7980                 l2_tn_info->e_tag_fwd_en = FALSE;
7981                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7982                 break;
7983         default:
7984                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7985                 ret = -EINVAL;
7986                 break;
7987         }
7988
7989         return ret;
7990 }
7991
7992 static int
7993 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7994                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7995                              bool en)
7996 {
7997         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7998         int ret = 0;
7999         uint32_t vmtir, vmvir;
8000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8001
8002         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8003                 PMD_DRV_LOG(ERR,
8004                             "VF id %u should be less than %u",
8005                             l2_tunnel->vf_id,
8006                             pci_dev->max_vfs);
8007                 return -EINVAL;
8008         }
8009
8010         if (hw->mac.type != ixgbe_mac_X550 &&
8011             hw->mac.type != ixgbe_mac_X550EM_x &&
8012             hw->mac.type != ixgbe_mac_X550EM_a) {
8013                 return -ENOTSUP;
8014         }
8015
8016         if (en)
8017                 vmtir = l2_tunnel->tunnel_id;
8018         else
8019                 vmtir = 0;
8020
8021         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8022
8023         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8024         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8025         if (en)
8026                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8027         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8028
8029         return ret;
8030 }
8031
8032 /* Enable l2 tunnel tag insertion */
8033 static int
8034 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8035                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8036 {
8037         int ret = 0;
8038
8039         switch (l2_tunnel->l2_tunnel_type) {
8040         case RTE_L2_TUNNEL_TYPE_E_TAG:
8041                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8042                 break;
8043         default:
8044                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8045                 ret = -EINVAL;
8046                 break;
8047         }
8048
8049         return ret;
8050 }
8051
8052 /* Disable l2 tunnel tag insertion */
8053 static int
8054 ixgbe_dev_l2_tunnel_insertion_disable
8055         (struct rte_eth_dev *dev,
8056          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8057 {
8058         int ret = 0;
8059
8060         switch (l2_tunnel->l2_tunnel_type) {
8061         case RTE_L2_TUNNEL_TYPE_E_TAG:
8062                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8063                 break;
8064         default:
8065                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8066                 ret = -EINVAL;
8067                 break;
8068         }
8069
8070         return ret;
8071 }
8072
8073 static int
8074 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8075                              bool en)
8076 {
8077         int ret = 0;
8078         uint32_t qde;
8079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8080
8081         if (hw->mac.type != ixgbe_mac_X550 &&
8082             hw->mac.type != ixgbe_mac_X550EM_x &&
8083             hw->mac.type != ixgbe_mac_X550EM_a) {
8084                 return -ENOTSUP;
8085         }
8086
8087         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8088         if (en)
8089                 qde |= IXGBE_QDE_STRIP_TAG;
8090         else
8091                 qde &= ~IXGBE_QDE_STRIP_TAG;
8092         qde &= ~IXGBE_QDE_READ;
8093         qde |= IXGBE_QDE_WRITE;
8094         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8095
8096         return ret;
8097 }
8098
8099 /* Enable l2 tunnel tag stripping */
8100 static int
8101 ixgbe_dev_l2_tunnel_stripping_enable
8102         (struct rte_eth_dev *dev,
8103          enum rte_eth_tunnel_type l2_tunnel_type)
8104 {
8105         int ret = 0;
8106
8107         switch (l2_tunnel_type) {
8108         case RTE_L2_TUNNEL_TYPE_E_TAG:
8109                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8110                 break;
8111         default:
8112                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8113                 ret = -EINVAL;
8114                 break;
8115         }
8116
8117         return ret;
8118 }
8119
8120 /* Disable l2 tunnel tag stripping */
8121 static int
8122 ixgbe_dev_l2_tunnel_stripping_disable
8123         (struct rte_eth_dev *dev,
8124          enum rte_eth_tunnel_type l2_tunnel_type)
8125 {
8126         int ret = 0;
8127
8128         switch (l2_tunnel_type) {
8129         case RTE_L2_TUNNEL_TYPE_E_TAG:
8130                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8131                 break;
8132         default:
8133                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8134                 ret = -EINVAL;
8135                 break;
8136         }
8137
8138         return ret;
8139 }
8140
8141 /* Enable/disable l2 tunnel offload functions */
8142 static int
8143 ixgbe_dev_l2_tunnel_offload_set
8144         (struct rte_eth_dev *dev,
8145          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8146          uint32_t mask,
8147          uint8_t en)
8148 {
8149         int ret = 0;
8150
8151         if (l2_tunnel == NULL)
8152                 return -EINVAL;
8153
8154         ret = -EINVAL;
8155         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8156                 if (en)
8157                         ret = ixgbe_dev_l2_tunnel_enable(
8158                                 dev,
8159                                 l2_tunnel->l2_tunnel_type);
8160                 else
8161                         ret = ixgbe_dev_l2_tunnel_disable(
8162                                 dev,
8163                                 l2_tunnel->l2_tunnel_type);
8164         }
8165
8166         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8167                 if (en)
8168                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8169                                 dev,
8170                                 l2_tunnel);
8171                 else
8172                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8173                                 dev,
8174                                 l2_tunnel);
8175         }
8176
8177         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8178                 if (en)
8179                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8180                                 dev,
8181                                 l2_tunnel->l2_tunnel_type);
8182                 else
8183                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8184                                 dev,
8185                                 l2_tunnel->l2_tunnel_type);
8186         }
8187
8188         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8189                 if (en)
8190                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8191                                 dev,
8192                                 l2_tunnel->l2_tunnel_type);
8193                 else
8194                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8195                                 dev,
8196                                 l2_tunnel->l2_tunnel_type);
8197         }
8198
8199         return ret;
8200 }
8201
8202 static int
8203 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8204                         uint16_t port)
8205 {
8206         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8207         IXGBE_WRITE_FLUSH(hw);
8208
8209         return 0;
8210 }
8211
8212 /* There's only one register for VxLAN UDP port.
8213  * So, we cannot add several ports. Will update it.
8214  */
8215 static int
8216 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8217                      uint16_t port)
8218 {
8219         if (port == 0) {
8220                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8221                 return -EINVAL;
8222         }
8223
8224         return ixgbe_update_vxlan_port(hw, port);
8225 }
8226
8227 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8228  * UDP port, it must have a value.
8229  * So, will reset it to the original value 0.
8230  */
8231 static int
8232 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8233                      uint16_t port)
8234 {
8235         uint16_t cur_port;
8236
8237         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8238
8239         if (cur_port != port) {
8240                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8241                 return -EINVAL;
8242         }
8243
8244         return ixgbe_update_vxlan_port(hw, 0);
8245 }
8246
8247 /* Add UDP tunneling port */
8248 static int
8249 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8250                               struct rte_eth_udp_tunnel *udp_tunnel)
8251 {
8252         int ret = 0;
8253         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8254
8255         if (hw->mac.type != ixgbe_mac_X550 &&
8256             hw->mac.type != ixgbe_mac_X550EM_x &&
8257             hw->mac.type != ixgbe_mac_X550EM_a) {
8258                 return -ENOTSUP;
8259         }
8260
8261         if (udp_tunnel == NULL)
8262                 return -EINVAL;
8263
8264         switch (udp_tunnel->prot_type) {
8265         case RTE_TUNNEL_TYPE_VXLAN:
8266                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8267                 break;
8268
8269         case RTE_TUNNEL_TYPE_GENEVE:
8270         case RTE_TUNNEL_TYPE_TEREDO:
8271                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8272                 ret = -EINVAL;
8273                 break;
8274
8275         default:
8276                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8277                 ret = -EINVAL;
8278                 break;
8279         }
8280
8281         return ret;
8282 }
8283
8284 /* Remove UDP tunneling port */
8285 static int
8286 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8287                               struct rte_eth_udp_tunnel *udp_tunnel)
8288 {
8289         int ret = 0;
8290         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8291
8292         if (hw->mac.type != ixgbe_mac_X550 &&
8293             hw->mac.type != ixgbe_mac_X550EM_x &&
8294             hw->mac.type != ixgbe_mac_X550EM_a) {
8295                 return -ENOTSUP;
8296         }
8297
8298         if (udp_tunnel == NULL)
8299                 return -EINVAL;
8300
8301         switch (udp_tunnel->prot_type) {
8302         case RTE_TUNNEL_TYPE_VXLAN:
8303                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8304                 break;
8305         case RTE_TUNNEL_TYPE_GENEVE:
8306         case RTE_TUNNEL_TYPE_TEREDO:
8307                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8308                 ret = -EINVAL;
8309                 break;
8310         default:
8311                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8312                 ret = -EINVAL;
8313                 break;
8314         }
8315
8316         return ret;
8317 }
8318
8319 static void
8320 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8321 {
8322         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8323
8324         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC);
8325 }
8326
8327 static void
8328 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8329 {
8330         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8331
8332         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8333 }
8334
8335 static void
8336 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8337 {
8338         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8339
8340         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8341 }
8342
8343 static void
8344 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8345 {
8346         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8347
8348         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8349 }
8350
8351 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8352 {
8353         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8354         u32 in_msg = 0;
8355
8356         /* peek the message first */
8357         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8358
8359         /* PF reset VF event */
8360         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8361                 /* dummy mbx read to ack pf */
8362                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8363                         return;
8364                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8365                                               NULL);
8366         }
8367 }
8368
8369 static int
8370 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8371 {
8372         uint32_t eicr;
8373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8374         struct ixgbe_interrupt *intr =
8375                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8376         ixgbevf_intr_disable(dev);
8377
8378         /* read-on-clear nic registers here */
8379         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8380         intr->flags = 0;
8381
8382         /* only one misc vector supported - mailbox */
8383         eicr &= IXGBE_VTEICR_MASK;
8384         if (eicr == IXGBE_MISC_VEC_ID)
8385                 intr->flags |= IXGBE_FLAG_MAILBOX;
8386
8387         return 0;
8388 }
8389
8390 static int
8391 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8392 {
8393         struct ixgbe_interrupt *intr =
8394                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8395
8396         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8397                 ixgbevf_mbx_process(dev);
8398                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8399         }
8400
8401         ixgbevf_intr_enable(dev);
8402
8403         return 0;
8404 }
8405
8406 static void
8407 ixgbevf_dev_interrupt_handler(void *param)
8408 {
8409         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8410
8411         ixgbevf_dev_interrupt_get_status(dev);
8412         ixgbevf_dev_interrupt_action(dev);
8413 }
8414
8415 /**
8416  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8417  *  @hw: pointer to hardware structure
8418  *
8419  *  Stops the transmit data path and waits for the HW to internally empty
8420  *  the Tx security block
8421  **/
8422 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8423 {
8424 #define IXGBE_MAX_SECTX_POLL 40
8425
8426         int i;
8427         int sectxreg;
8428
8429         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8430         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8431         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8432         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8433                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8434                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8435                         break;
8436                 /* Use interrupt-safe sleep just in case */
8437                 usec_delay(1000);
8438         }
8439
8440         /* For informational purposes only */
8441         if (i >= IXGBE_MAX_SECTX_POLL)
8442                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8443                          "path fully disabled.  Continuing with init.");
8444
8445         return IXGBE_SUCCESS;
8446 }
8447
8448 /**
8449  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8450  *  @hw: pointer to hardware structure
8451  *
8452  *  Enables the transmit data path.
8453  **/
8454 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8455 {
8456         uint32_t sectxreg;
8457
8458         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8459         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8460         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8461         IXGBE_WRITE_FLUSH(hw);
8462
8463         return IXGBE_SUCCESS;
8464 }
8465
8466 /* restore n-tuple filter */
8467 static inline void
8468 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8469 {
8470         struct ixgbe_filter_info *filter_info =
8471                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8472         struct ixgbe_5tuple_filter *node;
8473
8474         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8475                 ixgbe_inject_5tuple_filter(dev, node);
8476         }
8477 }
8478
8479 /* restore ethernet type filter */
8480 static inline void
8481 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8482 {
8483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8484         struct ixgbe_filter_info *filter_info =
8485                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8486         int i;
8487
8488         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8489                 if (filter_info->ethertype_mask & (1 << i)) {
8490                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8491                                         filter_info->ethertype_filters[i].etqf);
8492                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8493                                         filter_info->ethertype_filters[i].etqs);
8494                         IXGBE_WRITE_FLUSH(hw);
8495                 }
8496         }
8497 }
8498
8499 /* restore SYN filter */
8500 static inline void
8501 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8502 {
8503         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8504         struct ixgbe_filter_info *filter_info =
8505                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8506         uint32_t synqf;
8507
8508         synqf = filter_info->syn_info;
8509
8510         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8511                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8512                 IXGBE_WRITE_FLUSH(hw);
8513         }
8514 }
8515
8516 /* restore L2 tunnel filter */
8517 static inline void
8518 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8519 {
8520         struct ixgbe_l2_tn_info *l2_tn_info =
8521                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8522         struct ixgbe_l2_tn_filter *node;
8523         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8524
8525         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8526                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8527                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8528                 l2_tn_conf.pool           = node->pool;
8529                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8530         }
8531 }
8532
8533 /* restore rss filter */
8534 static inline void
8535 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8536 {
8537         struct ixgbe_filter_info *filter_info =
8538                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8539
8540         if (filter_info->rss_info.conf.queue_num)
8541                 ixgbe_config_rss_filter(dev,
8542                         &filter_info->rss_info, TRUE);
8543 }
8544
8545 static int
8546 ixgbe_filter_restore(struct rte_eth_dev *dev)
8547 {
8548         ixgbe_ntuple_filter_restore(dev);
8549         ixgbe_ethertype_filter_restore(dev);
8550         ixgbe_syn_filter_restore(dev);
8551         ixgbe_fdir_filter_restore(dev);
8552         ixgbe_l2_tn_filter_restore(dev);
8553         ixgbe_rss_filter_restore(dev);
8554
8555         return 0;
8556 }
8557
8558 static void
8559 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8560 {
8561         struct ixgbe_l2_tn_info *l2_tn_info =
8562                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8564
8565         if (l2_tn_info->e_tag_en)
8566                 (void)ixgbe_e_tag_enable(hw);
8567
8568         if (l2_tn_info->e_tag_fwd_en)
8569                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8570
8571         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8572 }
8573
8574 /* remove all the n-tuple filters */
8575 void
8576 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8577 {
8578         struct ixgbe_filter_info *filter_info =
8579                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8580         struct ixgbe_5tuple_filter *p_5tuple;
8581
8582         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8583                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8584 }
8585
8586 /* remove all the ether type filters */
8587 void
8588 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8589 {
8590         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8591         struct ixgbe_filter_info *filter_info =
8592                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8593         int i;
8594
8595         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8596                 if (filter_info->ethertype_mask & (1 << i) &&
8597                     !filter_info->ethertype_filters[i].conf) {
8598                         (void)ixgbe_ethertype_filter_remove(filter_info,
8599                                                             (uint8_t)i);
8600                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8601                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8602                         IXGBE_WRITE_FLUSH(hw);
8603                 }
8604         }
8605 }
8606
8607 /* remove the SYN filter */
8608 void
8609 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8610 {
8611         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8612         struct ixgbe_filter_info *filter_info =
8613                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8614
8615         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8616                 filter_info->syn_info = 0;
8617
8618                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8619                 IXGBE_WRITE_FLUSH(hw);
8620         }
8621 }
8622
8623 /* remove all the L2 tunnel filters */
8624 int
8625 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8626 {
8627         struct ixgbe_l2_tn_info *l2_tn_info =
8628                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8629         struct ixgbe_l2_tn_filter *l2_tn_filter;
8630         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8631         int ret = 0;
8632
8633         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8634                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8635                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8636                 l2_tn_conf.pool           = l2_tn_filter->pool;
8637                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8638                 if (ret < 0)
8639                         return ret;
8640         }
8641
8642         return 0;
8643 }
8644
8645 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8646 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8647 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8648 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8649 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8650 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8651
8652 RTE_INIT(ixgbe_init_log)
8653 {
8654         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8655         if (ixgbe_logtype_init >= 0)
8656                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8657         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8658         if (ixgbe_logtype_driver >= 0)
8659                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8660 }