drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffff
 140
 141 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 142 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 143 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 144 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 147 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 154                                 int wait_to_complete);
 155 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *stats);
 157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstats *xstats, unsigned n);
 159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 160                                   struct rte_eth_xstats *xstats, unsigned n);
 161 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 163 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 164                                              uint16_t queue_id,
 165                                              uint8_t stat_idx,
 166                                              uint8_t is_rx);
 167 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 168                                struct rte_eth_dev_info *dev_info);
 169 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 170                                  struct rte_eth_dev_info *dev_info);
 171 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 172
 173 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 174                 uint16_t vlan_id, int on);
 175 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 176 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 177                 uint16_t queue, bool on);
 178 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 179                 int on);
 180 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 181 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 182 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 183 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 184 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 185
 186 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 187 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 188 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 189                                struct rte_eth_fc_conf *fc_conf);
 190 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 191                                struct rte_eth_fc_conf *fc_conf);
 192 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 193                 struct rte_eth_pfc_conf *pfc_conf);
 194 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 195                         struct rte_eth_rss_reta_entry64 *reta_conf,
 196                         uint16_t reta_size);
 197 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 198                         struct rte_eth_rss_reta_entry64 *reta_conf,
 199                         uint16_t reta_size);
 200 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 201 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 203 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 204 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 205 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 206                 void *param);
 207 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 208 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 209                 uint32_t index, uint32_t pool);
 210 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 211 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 212                                            struct ether_addr *mac_addr);
 213 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 214
 215 /* For Virtual Function support */
 216 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 219 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 220 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 221 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 222 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 223 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 224 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 225                 struct rte_eth_stats *stats);
 226 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 227 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 228                 uint16_t vlan_id, int on);
 229 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 230                 uint16_t queue, int on);
 231 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 232 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 233 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 234                                             uint16_t queue_id);
 235 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 236                                              uint16_t queue_id);
 237 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 238                                  uint8_t queue, uint8_t msix_vector);
 239 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 240
 241 /* For Eth VMDQ APIs support */
 242 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 243                 ether_addr* mac_addr,uint8_t on);
 244 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 245 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 246                 uint16_t rx_mask, uint8_t on);
 247 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 248 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 249 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 250                 uint64_t pool_mask,uint8_t vlan_on);
 251 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 252                 struct rte_eth_mirror_conf *mirror_conf,
 253                 uint8_t rule_id, uint8_t on);
 254 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 255                 uint8_t rule_id);
 256 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 257                                           uint16_t queue_id);
 258 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 259                                            uint16_t queue_id);
 260 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 261                                uint8_t queue, uint8_t msix_vector);
 262 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 263
 264 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 265                 uint16_t queue_idx, uint16_t tx_rate);
 266 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 267                 uint16_t tx_rate, uint64_t q_msk);
 268
 269 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 270                                  struct ether_addr *mac_addr,
 271                                  uint32_t index, uint32_t pool);
 272 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 273 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                                              struct ether_addr *mac_addr);
 275 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 276                         struct rte_eth_syn_filter *filter,
 277                         bool add);
 278 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 279                         struct rte_eth_syn_filter *filter);
 280 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 281                         enum rte_filter_op filter_op,
 282                         void *arg);
 283 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 284                         struct ixgbe_5tuple_filter *filter);
 285 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 286                         struct ixgbe_5tuple_filter *filter);
 287 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 288                         struct rte_eth_ntuple_filter *filter,
 289                         bool add);
 290 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 291                                 enum rte_filter_op filter_op,
 292                                 void *arg);
 293 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 294                         struct rte_eth_ntuple_filter *filter);
 295 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 296                         struct rte_eth_ethertype_filter *filter,
 297                         bool add);
 298 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 299                                 enum rte_filter_op filter_op,
 300                                 void *arg);
 301 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 302                         struct rte_eth_ethertype_filter *filter);
 303 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 304                      enum rte_filter_type filter_type,
 305                      enum rte_filter_op filter_op,
 306                      void *arg);
 307 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 308
 309 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 310                                       struct ether_addr *mc_addr_set,
 311                                       uint32_t nb_mc_addr);
 312 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 313                                    struct rte_eth_dcb_info *dcb_info);
 314
 315 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 316 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 317                             struct rte_dev_reg_info *regs);
 318 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 319 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 320                                 struct rte_dev_eeprom_info *eeprom);
 321 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 322                                 struct rte_dev_eeprom_info *eeprom);
 323
 324 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 325 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 326                                 struct rte_dev_reg_info *regs);
 327
 328 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 329 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 330 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 331                                             struct timespec *timestamp,
 332                                             uint32_t flags);
 333 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 334                                             struct timespec *timestamp);
 335 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 336 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 337                                    struct timespec *timestamp);
 338 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 339                                    const struct timespec *timestamp);
 340
 341 /*
 342  * Define VF Stats MACRO for Non "cleared on read" register
 343  */
 344 #define UPDATE_VF_STAT(reg, last, cur)                          \
 345 {                                                               \
 346         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 347         cur += (latest - last) & UINT_MAX;                      \
 348         last = latest;                                          \
 349 }
 350
 351 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 352 {                                                                \
 353         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 354         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 355         u64 latest = ((new_msb << 32) | new_lsb);                \
 356         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 357         last = latest;                                           \
 358 }
 359
 360 #define IXGBE_SET_HWSTRIP(h, q) do{\
 361                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 362                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 363                 (h)->bitmap[idx] |= 1 << bit;\
 364         }while(0)
 365
 366 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 367                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 368                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 369                 (h)->bitmap[idx] &= ~(1 << bit);\
 370         }while(0)
 371
 372 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 373                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 374                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 375                 (r) = (h)->bitmap[idx] >> bit & 1;\
 376         }while(0)
 377
 378 /*
 379  * The set of PCI devices this driver supports
 380  */
 381 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 382
 383 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 384 #include "rte_pci_dev_ids.h"
 385
 386 { .vendor_id = 0, /* sentinel */ },
 387 };
 388
 389
 390 /*
 391  * The set of PCI devices this driver supports (for 82599 VF)
 392  */
 393 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 394
 395 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 396 #include "rte_pci_dev_ids.h"
 397 { .vendor_id = 0, /* sentinel */ },
 398
 399 };
 400
 401 static const struct rte_eth_desc_lim rx_desc_lim = {
 402         .nb_max = IXGBE_MAX_RING_DESC,
 403         .nb_min = IXGBE_MIN_RING_DESC,
 404         .nb_align = IXGBE_RXD_ALIGN,
 405 };
 406
 407 static const struct rte_eth_desc_lim tx_desc_lim = {
 408         .nb_max = IXGBE_MAX_RING_DESC,
 409         .nb_min = IXGBE_MIN_RING_DESC,
 410         .nb_align = IXGBE_TXD_ALIGN,
 411 };
 412
 413 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 414         .dev_configure        = ixgbe_dev_configure,
 415         .dev_start            = ixgbe_dev_start,
 416         .dev_stop             = ixgbe_dev_stop,
 417         .dev_set_link_up    = ixgbe_dev_set_link_up,
 418         .dev_set_link_down  = ixgbe_dev_set_link_down,
 419         .dev_close            = ixgbe_dev_close,
 420         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 421         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 422         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 423         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 424         .link_update          = ixgbe_dev_link_update,
 425         .stats_get            = ixgbe_dev_stats_get,
 426         .xstats_get           = ixgbe_dev_xstats_get,
 427         .stats_reset          = ixgbe_dev_stats_reset,
 428         .xstats_reset         = ixgbe_dev_xstats_reset,
 429         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 430         .dev_infos_get        = ixgbe_dev_info_get,
 431         .mtu_set              = ixgbe_dev_mtu_set,
 432         .vlan_filter_set      = ixgbe_vlan_filter_set,
 433         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 434         .vlan_offload_set     = ixgbe_vlan_offload_set,
 435         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 436         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 437         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 438         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 439         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 440         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 441         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 442         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 443         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 444         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 445         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 446         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 447         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 448         .dev_led_on           = ixgbe_dev_led_on,
 449         .dev_led_off          = ixgbe_dev_led_off,
 450         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 451         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 452         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 453         .mac_addr_add         = ixgbe_add_rar,
 454         .mac_addr_remove      = ixgbe_remove_rar,
 455         .mac_addr_set         = ixgbe_set_default_mac_addr,
 456         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 457         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 458         .mirror_rule_set      = ixgbe_mirror_rule_set,
 459         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 460         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 461         .set_vf_rx            = ixgbe_set_pool_rx,
 462         .set_vf_tx            = ixgbe_set_pool_tx,
 463         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 464         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 465         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 466         .reta_update          = ixgbe_dev_rss_reta_update,
 467         .reta_query           = ixgbe_dev_rss_reta_query,
 468 #ifdef RTE_NIC_BYPASS
 469         .bypass_init          = ixgbe_bypass_init,
 470         .bypass_state_set     = ixgbe_bypass_state_store,
 471         .bypass_state_show    = ixgbe_bypass_state_show,
 472         .bypass_event_set     = ixgbe_bypass_event_store,
 473         .bypass_event_show    = ixgbe_bypass_event_show,
 474         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 475         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 476         .bypass_ver_show      = ixgbe_bypass_ver_show,
 477         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 478 #endif /* RTE_NIC_BYPASS */
 479         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 480         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 481         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 482         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 483         .rxq_info_get         = ixgbe_rxq_info_get,
 484         .txq_info_get         = ixgbe_txq_info_get,
 485         .timesync_enable      = ixgbe_timesync_enable,
 486         .timesync_disable     = ixgbe_timesync_disable,
 487         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 488         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 489         .get_reg_length       = ixgbe_get_reg_length,
 490         .get_reg              = ixgbe_get_regs,
 491         .get_eeprom_length    = ixgbe_get_eeprom_length,
 492         .get_eeprom           = ixgbe_get_eeprom,
 493         .set_eeprom           = ixgbe_set_eeprom,
 494         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 495         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 496         .timesync_read_time   = ixgbe_timesync_read_time,
 497         .timesync_write_time  = ixgbe_timesync_write_time,
 498 };
 499
 500 /*
 501  * dev_ops for virtual function, bare necessities for basic vf
 502  * operation have been implemented
 503  */
 504 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 505         .dev_configure        = ixgbevf_dev_configure,
 506         .dev_start            = ixgbevf_dev_start,
 507         .dev_stop             = ixgbevf_dev_stop,
 508         .link_update          = ixgbe_dev_link_update,
 509         .stats_get            = ixgbevf_dev_stats_get,
 510         .xstats_get           = ixgbevf_dev_xstats_get,
 511         .stats_reset          = ixgbevf_dev_stats_reset,
 512         .xstats_reset         = ixgbevf_dev_stats_reset,
 513         .dev_close            = ixgbevf_dev_close,
 514         .dev_infos_get        = ixgbevf_dev_info_get,
 515         .mtu_set              = ixgbevf_dev_set_mtu,
 516         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 517         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 518         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 519         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 520         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 521         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 522         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 523         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 524         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 525         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 526         .mac_addr_add         = ixgbevf_add_mac_addr,
 527         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 528         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 529         .rxq_info_get         = ixgbe_rxq_info_get,
 530         .txq_info_get         = ixgbe_txq_info_get,
 531         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 532         .get_reg_length       = ixgbevf_get_reg_length,
 533         .get_reg              = ixgbevf_get_regs,
 534         .reta_update          = ixgbe_dev_rss_reta_update,
 535         .reta_query           = ixgbe_dev_rss_reta_query,
 536         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 537         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 538 };
 539
 540 /* store statistics names and its offset in stats structure */
 541 struct rte_ixgbe_xstats_name_off {
 542         char name[RTE_ETH_XSTATS_NAME_SIZE];
 543         unsigned offset;
 544 };
 545
 546 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 547         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 548         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 549         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 550         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 551         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 552         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 553         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 554         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 555         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 556         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 557         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 558         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 559         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 560         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 561         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 562                 prc1023)},
 563         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 564                 prc1522)},
 565         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 566         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 567         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 568         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 569         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 570         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 571         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 572         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 573         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 574         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 575         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 576         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 577         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 578         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 579         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 580         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 581         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 582                 ptc1023)},
 583         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 584                 ptc1522)},
 585         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 586         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 587         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 588         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 589
 590         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 591                 fdirustat_add)},
 592         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 593                 fdirustat_remove)},
 594         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 595                 fdirfstat_fadd)},
 596         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 597                 fdirfstat_fremove)},
 598         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 599                 fdirmatch)},
 600         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 601                 fdirmiss)},
 602
 603         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 604         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 605         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 606                 fclast)},
 607         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 608         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 609         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 610         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 611         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 612                 fcoe_noddp)},
 613         {"rx_fcoe_no_direct_data_placement_ext_buff",
 614                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 615
 616         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 617                 lxontxc)},
 618         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 619                 lxonrxc)},
 620         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 621                 lxofftxc)},
 622         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 623                 lxoffrxc)},
 624         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 625 };
 626
 627 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 628                            sizeof(rte_ixgbe_stats_strings[0]))
 629
 630 /* Per-queue statistics */
 631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 632         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 633         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 634         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 635         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 636 };
 637
 638 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 639                            sizeof(rte_ixgbe_rxq_strings[0]))
 640
 641 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 642         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 643         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 644         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 645                 pxon2offc)},
 646 };
 647
 648 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 649                            sizeof(rte_ixgbe_txq_strings[0]))
 650
 651 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 652         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 653 };
 654
 655 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 656                 sizeof(rte_ixgbevf_stats_strings[0]))
 657
 658 /**
 659  * Atomically reads the link status information from global
 660  * structure rte_eth_dev.
 661  *
 662  * @param dev
 663  *   - Pointer to the structure rte_eth_dev to read from.
 664  *   - Pointer to the buffer to be saved with the link status.
 665  *
 666  * @return
 667  *   - On success, zero.
 668  *   - On failure, negative value.
 669  */
 670 static inline int
 671 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 672                                 struct rte_eth_link *link)
 673 {
 674         struct rte_eth_link *dst = link;
 675         struct rte_eth_link *src = &(dev->data->dev_link);
 676
 677         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 678                                         *(uint64_t *)src) == 0)
 679                 return -1;
 680
 681         return 0;
 682 }
 683
 684 /**
 685  * Atomically writes the link status information into global
 686  * structure rte_eth_dev.
 687  *
 688  * @param dev
 689  *   - Pointer to the structure rte_eth_dev to read from.
 690  *   - Pointer to the buffer to be saved with the link status.
 691  *
 692  * @return
 693  *   - On success, zero.
 694  *   - On failure, negative value.
 695  */
 696 static inline int
 697 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 698                                 struct rte_eth_link *link)
 699 {
 700         struct rte_eth_link *dst = &(dev->data->dev_link);
 701         struct rte_eth_link *src = link;
 702
 703         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 704                                         *(uint64_t *)src) == 0)
 705                 return -1;
 706
 707         return 0;
 708 }
 709
 710 /*
 711  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 712  */
 713 static inline int
 714 ixgbe_is_sfp(struct ixgbe_hw *hw)
 715 {
 716         switch (hw->phy.type) {
 717         case ixgbe_phy_sfp_avago:
 718         case ixgbe_phy_sfp_ftl:
 719         case ixgbe_phy_sfp_intel:
 720         case ixgbe_phy_sfp_unknown:
 721         case ixgbe_phy_sfp_passive_tyco:
 722         case ixgbe_phy_sfp_passive_unknown:
 723                 return 1;
 724         default:
 725                 return 0;
 726         }
 727 }
 728
 729 static inline int32_t
 730 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 731 {
 732         uint32_t ctrl_ext;
 733         int32_t status;
 734
 735         status = ixgbe_reset_hw(hw);
 736
 737         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 738         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 739         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 740         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 741         IXGBE_WRITE_FLUSH(hw);
 742
 743         return status;
 744 }
 745
 746 static inline void
 747 ixgbe_enable_intr(struct rte_eth_dev *dev)
 748 {
 749         struct ixgbe_interrupt *intr =
 750                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 751         struct ixgbe_hw *hw =
 752                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753
 754         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 755         IXGBE_WRITE_FLUSH(hw);
 756 }
 757
 758 /*
 759  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 760  */
 761 static void
 762 ixgbe_disable_intr(struct ixgbe_hw *hw)
 763 {
 764         PMD_INIT_FUNC_TRACE();
 765
 766         if (hw->mac.type == ixgbe_mac_82598EB) {
 767                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 768         } else {
 769                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 770                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 771                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 772         }
 773         IXGBE_WRITE_FLUSH(hw);
 774 }
 775
 776 /*
 777  * This function resets queue statistics mapping registers.
 778  * From Niantic datasheet, Initialization of Statistics section:
 779  * "...if software requires the queue counters, the RQSMR and TQSM registers
 780  * must be re-programmed following a device reset.
 781  */
 782 static void
 783 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 784 {
 785         uint32_t i;
 786
 787         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 788                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 789                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 790         }
 791 }
 792
 793
 794 static int
 795 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 796                                   uint16_t queue_id,
 797                                   uint8_t stat_idx,
 798                                   uint8_t is_rx)
 799 {
 800 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 801 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 802 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 803
 804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 805         struct ixgbe_stat_mapping_registers *stat_mappings =
 806                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 807         uint32_t qsmr_mask = 0;
 808         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 809         uint32_t q_map;
 810         uint8_t n, offset;
 811
 812         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 813                 (hw->mac.type != ixgbe_mac_X540) &&
 814                 (hw->mac.type != ixgbe_mac_X550) &&
 815                 (hw->mac.type != ixgbe_mac_X550EM_x))
 816                 return -ENOSYS;
 817
 818         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 819                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 820                      queue_id, stat_idx);
 821
 822         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 823         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 824                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 825                 return -EIO;
 826         }
 827         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 828
 829         /* Now clear any previous stat_idx set */
 830         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 831         if (!is_rx)
 832                 stat_mappings->tqsm[n] &= ~clearing_mask;
 833         else
 834                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 835
 836         q_map = (uint32_t)stat_idx;
 837         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 838         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 839         if (!is_rx)
 840                 stat_mappings->tqsm[n] |= qsmr_mask;
 841         else
 842                 stat_mappings->rqsmr[n] |= qsmr_mask;
 843
 844         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 845                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 846                      queue_id, stat_idx);
 847         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 848                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 849
 850         /* Now write the mapping in the appropriate register */
 851         if (is_rx) {
 852                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 853                              stat_mappings->rqsmr[n], n);
 854                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 855         }
 856         else {
 857                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 858                              stat_mappings->tqsm[n], n);
 859                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 860         }
 861         return 0;
 862 }
 863
 864 static void
 865 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 866 {
 867         struct ixgbe_stat_mapping_registers *stat_mappings =
 868                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 869         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 870         int i;
 871
 872         /* write whatever was in stat mapping table to the NIC */
 873         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 /* rx */
 875                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 876
 877                 /* tx */
 878                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 879         }
 880 }
 881
 882 static void
 883 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 884 {
 885         uint8_t i;
 886         struct ixgbe_dcb_tc_config *tc;
 887         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 888
 889         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 890         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 891         for (i = 0; i < dcb_max_tc; i++) {
 892                 tc = &dcb_config->tc_config[i];
 893                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 894                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 895                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 896                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 897                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 898                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 899                 tc->pfc = ixgbe_dcb_pfc_disabled;
 900         }
 901
 902         /* Initialize default user to priority mapping, UPx->TC0 */
 903         tc = &dcb_config->tc_config[0];
 904         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 905         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 906         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 907                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 908                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 909         }
 910         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 911         dcb_config->pfc_mode_enable = false;
 912         dcb_config->vt_mode = true;
 913         dcb_config->round_robin_enable = false;
 914         /* support all DCB capabilities in 82599 */
 915         dcb_config->support.capabilities = 0xFF;
 916
 917         /*we only support 4 Tcs for X540, X550 */
 918         if (hw->mac.type == ixgbe_mac_X540 ||
 919                 hw->mac.type == ixgbe_mac_X550 ||
 920                 hw->mac.type == ixgbe_mac_X550EM_x) {
 921                 dcb_config->num_tcs.pg_tcs = 4;
 922                 dcb_config->num_tcs.pfc_tcs = 4;
 923         }
 924 }
 925
 926 /*
 927  * Ensure that all locks are released before first NVM or PHY access
 928  */
 929 static void
 930 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 931 {
 932         uint16_t mask;
 933
 934         /*
 935          * Phy lock should not fail in this early stage. If this is the case,
 936          * it is due to an improper exit of the application.
 937          * So force the release of the faulty lock. Release of common lock
 938          * is done automatically by swfw_sync function.
 939          */
 940         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 941         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 942                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 943         }
 944         ixgbe_release_swfw_semaphore(hw, mask);
 945
 946         /*
 947          * These ones are more tricky since they are common to all ports; but
 948          * swfw_sync retries last long enough (1s) to be almost sure that if
 949          * lock can not be taken it is due to an improper lock of the
 950          * semaphore.
 951          */
 952         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 953         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 954                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 955         }
 956         ixgbe_release_swfw_semaphore(hw, mask);
 957 }
 958
 959 /*
 960  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 961  * It returns 0 on success.
 962  */
 963 static int
 964 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 965 {
 966         struct rte_pci_device *pci_dev;
 967         struct ixgbe_hw *hw =
 968                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 969         struct ixgbe_vfta * shadow_vfta =
 970                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 971         struct ixgbe_hwstrip *hwstrip =
 972                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 973         struct ixgbe_dcb_config *dcb_config =
 974                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 975         struct ixgbe_filter_info *filter_info =
 976                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 977         uint32_t ctrl_ext;
 978         uint16_t csum;
 979         int diag, i;
 980
 981         PMD_INIT_FUNC_TRACE();
 982
 983         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 984         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 985         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 986
 987         /*
 988          * For secondary processes, we don't initialise any further as primary
 989          * has already done this work. Only check we don't need a different
 990          * RX and TX function.
 991          */
 992         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 993                 struct ixgbe_tx_queue *txq;
 994                 /* TX queue function in primary, set by last queue initialized
 995                  * Tx queue may not initialized by primary process */
 996                 if (eth_dev->data->tx_queues) {
 997                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 998                         ixgbe_set_tx_function(eth_dev, txq);
 999                 } else {
1000                         /* Use default TX function if we get here */
1001                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1002                                              "Using default TX function.");
1003                 }
1004
1005                 ixgbe_set_rx_function(eth_dev);
1006
1007                 return 0;
1008         }
1009         pci_dev = eth_dev->pci_dev;
1010
1011         rte_eth_copy_pci_info(eth_dev, pci_dev);
1012
1013         /* Vendor and Device ID need to be set before init of shared code */
1014         hw->device_id = pci_dev->id.device_id;
1015         hw->vendor_id = pci_dev->id.vendor_id;
1016         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1017         hw->allow_unsupported_sfp = 1;
1018
1019         /* Initialize the shared code (base driver) */
1020 #ifdef RTE_NIC_BYPASS
1021         diag = ixgbe_bypass_init_shared_code(hw);
1022 #else
1023         diag = ixgbe_init_shared_code(hw);
1024 #endif /* RTE_NIC_BYPASS */
1025
1026         if (diag != IXGBE_SUCCESS) {
1027                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1028                 return -EIO;
1029         }
1030
1031         /* pick up the PCI bus settings for reporting later */
1032         ixgbe_get_bus_info(hw);
1033
1034         /* Unlock any pending hardware semaphore */
1035         ixgbe_swfw_lock_reset(hw);
1036
1037         /* Initialize DCB configuration*/
1038         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1039         ixgbe_dcb_init(hw,dcb_config);
1040         /* Get Hardware Flow Control setting */
1041         hw->fc.requested_mode = ixgbe_fc_full;
1042         hw->fc.current_mode = ixgbe_fc_full;
1043         hw->fc.pause_time = IXGBE_FC_PAUSE;
1044         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1045                 hw->fc.low_water[i] = IXGBE_FC_LO;
1046                 hw->fc.high_water[i] = IXGBE_FC_HI;
1047         }
1048         hw->fc.send_xon = 1;
1049
1050         /* Make sure we have a good EEPROM before we read from it */
1051         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1052         if (diag != IXGBE_SUCCESS) {
1053                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1054                 return -EIO;
1055         }
1056
1057 #ifdef RTE_NIC_BYPASS
1058         diag = ixgbe_bypass_init_hw(hw);
1059 #else
1060         diag = ixgbe_init_hw(hw);
1061 #endif /* RTE_NIC_BYPASS */
1062
1063         /*
1064          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1065          * is called too soon after the kernel driver unbinding/binding occurs.
1066          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1067          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1068          * also called. See ixgbe_identify_phy_82599(). The reason for the
1069          * failure is not known, and only occuts when virtualisation features
1070          * are disabled in the bios. A delay of 100ms  was found to be enough by
1071          * trial-and-error, and is doubled to be safe.
1072          */
1073         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1074                 rte_delay_ms(200);
1075                 diag = ixgbe_init_hw(hw);
1076         }
1077
1078         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1079                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1080                     "LOM.  Please be aware there may be issues associated "
1081                     "with your hardware.");
1082                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1083                     "please contact your Intel or hardware representative "
1084                     "who provided you with this hardware.");
1085         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1086                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1087         if (diag) {
1088                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1089                 return -EIO;
1090         }
1091
1092         /* Reset the hw statistics */
1093         ixgbe_dev_stats_reset(eth_dev);
1094
1095         /* disable interrupt */
1096         ixgbe_disable_intr(hw);
1097
1098         /* reset mappings for queue statistics hw counters*/
1099         ixgbe_reset_qstat_mappings(hw);
1100
1101         /* Allocate memory for storing MAC addresses */
1102         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1103                         hw->mac.num_rar_entries, 0);
1104         if (eth_dev->data->mac_addrs == NULL) {
1105                 PMD_INIT_LOG(ERR,
1106                         "Failed to allocate %u bytes needed to store "
1107                         "MAC addresses",
1108                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1109                 return -ENOMEM;
1110         }
1111         /* Copy the permanent MAC address */
1112         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1113                         &eth_dev->data->mac_addrs[0]);
1114
1115         /* Allocate memory for storing hash filter MAC addresses */
1116         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1117                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1118         if (eth_dev->data->hash_mac_addrs == NULL) {
1119                 PMD_INIT_LOG(ERR,
1120                         "Failed to allocate %d bytes needed to store MAC addresses",
1121                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1122                 return -ENOMEM;
1123         }
1124
1125         /* initialize the vfta */
1126         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1127
1128         /* initialize the hw strip bitmap*/
1129         memset(hwstrip, 0, sizeof(*hwstrip));
1130
1131         /* initialize PF if max_vfs not zero */
1132         ixgbe_pf_host_init(eth_dev);
1133
1134         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1135         /* let hardware know driver is loaded */
1136         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1137         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1138         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1139         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1140         IXGBE_WRITE_FLUSH(hw);
1141
1142         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1143                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1144                              (int) hw->mac.type, (int) hw->phy.type,
1145                              (int) hw->phy.sfp_type);
1146         else
1147                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1148                              (int) hw->mac.type, (int) hw->phy.type);
1149
1150         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1151                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1152                         pci_dev->id.device_id);
1153
1154         rte_intr_callback_register(&pci_dev->intr_handle,
1155                                    ixgbe_dev_interrupt_handler,
1156                                    (void *)eth_dev);
1157
1158         /* enable uio/vfio intr/eventfd mapping */
1159         rte_intr_enable(&pci_dev->intr_handle);
1160
1161         /* enable support intr */
1162         ixgbe_enable_intr(eth_dev);
1163
1164         /* initialize 5tuple filter list */
1165         TAILQ_INIT(&filter_info->fivetuple_list);
1166         memset(filter_info->fivetuple_mask, 0,
1167                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1168
1169         return 0;
1170 }
1171
1172 static int
1173 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1174 {
1175         struct rte_pci_device *pci_dev;
1176         struct ixgbe_hw *hw;
1177
1178         PMD_INIT_FUNC_TRACE();
1179
1180         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1181                 return -EPERM;
1182
1183         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1184         pci_dev = eth_dev->pci_dev;
1185
1186         if (hw->adapter_stopped == 0)
1187                 ixgbe_dev_close(eth_dev);
1188
1189         eth_dev->dev_ops = NULL;
1190         eth_dev->rx_pkt_burst = NULL;
1191         eth_dev->tx_pkt_burst = NULL;
1192
1193         /* Unlock any pending hardware semaphore */
1194         ixgbe_swfw_lock_reset(hw);
1195
1196         /* disable uio intr before callback unregister */
1197         rte_intr_disable(&(pci_dev->intr_handle));
1198         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1199                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1200
1201         /* uninitialize PF if max_vfs not zero */
1202         ixgbe_pf_host_uninit(eth_dev);
1203
1204         rte_free(eth_dev->data->mac_addrs);
1205         eth_dev->data->mac_addrs = NULL;
1206
1207         rte_free(eth_dev->data->hash_mac_addrs);
1208         eth_dev->data->hash_mac_addrs = NULL;
1209
1210         return 0;
1211 }
1212
1213 /*
1214  * Negotiate mailbox API version with the PF.
1215  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1216  * Then we try to negotiate starting with the most recent one.
1217  * If all negotiation attempts fail, then we will proceed with
1218  * the default one (ixgbe_mbox_api_10).
1219  */
1220 static void
1221 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1222 {
1223         int32_t i;
1224
1225         /* start with highest supported, proceed down */
1226         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1227                 ixgbe_mbox_api_11,
1228                 ixgbe_mbox_api_10,
1229         };
1230
1231         for (i = 0;
1232                         i != RTE_DIM(sup_ver) &&
1233                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1234                         i++)
1235                 ;
1236 }
1237
1238 static void
1239 generate_random_mac_addr(struct ether_addr *mac_addr)
1240 {
1241         uint64_t random;
1242
1243         /* Set Organizationally Unique Identifier (OUI) prefix. */
1244         mac_addr->addr_bytes[0] = 0x00;
1245         mac_addr->addr_bytes[1] = 0x09;
1246         mac_addr->addr_bytes[2] = 0xC0;
1247         /* Force indication of locally assigned MAC address. */
1248         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1249         /* Generate the last 3 bytes of the MAC address with a random number. */
1250         random = rte_rand();
1251         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1252 }
1253
1254 /*
1255  * Virtual Function device init
1256  */
1257 static int
1258 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1259 {
1260         int diag;
1261         uint32_t tc, tcs;
1262         struct rte_pci_device *pci_dev;
1263         struct ixgbe_hw *hw =
1264                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1265         struct ixgbe_vfta * shadow_vfta =
1266                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1267         struct ixgbe_hwstrip *hwstrip =
1268                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1269         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1270
1271         PMD_INIT_FUNC_TRACE();
1272
1273         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1274         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1275         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1276
1277         /* for secondary processes, we don't initialise any further as primary
1278          * has already done this work. Only check we don't need a different
1279          * RX function */
1280         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1281                 if (eth_dev->data->scattered_rx)
1282                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1283                 return 0;
1284         }
1285
1286         pci_dev = eth_dev->pci_dev;
1287
1288         rte_eth_copy_pci_info(eth_dev, pci_dev);
1289
1290         hw->device_id = pci_dev->id.device_id;
1291         hw->vendor_id = pci_dev->id.vendor_id;
1292         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1293
1294         /* initialize the vfta */
1295         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1296
1297         /* initialize the hw strip bitmap*/
1298         memset(hwstrip, 0, sizeof(*hwstrip));
1299
1300         /* Initialize the shared code (base driver) */
1301         diag = ixgbe_init_shared_code(hw);
1302         if (diag != IXGBE_SUCCESS) {
1303                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1304                 return -EIO;
1305         }
1306
1307         /* init_mailbox_params */
1308         hw->mbx.ops.init_params(hw);
1309
1310         /* Reset the hw statistics */
1311         ixgbevf_dev_stats_reset(eth_dev);
1312
1313         /* Disable the interrupts for VF */
1314         ixgbevf_intr_disable(hw);
1315
1316         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1317         diag = hw->mac.ops.reset_hw(hw);
1318
1319         /*
1320          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1321          * the underlying PF driver has not assigned a MAC address to the VF.
1322          * In this case, assign a random MAC address.
1323          */
1324         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1325                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1326                 return (diag);
1327         }
1328
1329         /* negotiate mailbox API version to use with the PF. */
1330         ixgbevf_negotiate_api(hw);
1331
1332         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1333         ixgbevf_get_queues(hw, &tcs, &tc);
1334
1335         /* Allocate memory for storing MAC addresses */
1336         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1337                         hw->mac.num_rar_entries, 0);
1338         if (eth_dev->data->mac_addrs == NULL) {
1339                 PMD_INIT_LOG(ERR,
1340                         "Failed to allocate %u bytes needed to store "
1341                         "MAC addresses",
1342                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1343                 return -ENOMEM;
1344         }
1345
1346         /* Generate a random MAC address, if none was assigned by PF. */
1347         if (is_zero_ether_addr(perm_addr)) {
1348                 generate_random_mac_addr(perm_addr);
1349                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1350                 if (diag) {
1351                         rte_free(eth_dev->data->mac_addrs);
1352                         eth_dev->data->mac_addrs = NULL;
1353                         return diag;
1354                 }
1355                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1356                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1357                              "%02x:%02x:%02x:%02x:%02x:%02x",
1358                              perm_addr->addr_bytes[0],
1359                              perm_addr->addr_bytes[1],
1360                              perm_addr->addr_bytes[2],
1361                              perm_addr->addr_bytes[3],
1362                              perm_addr->addr_bytes[4],
1363                              perm_addr->addr_bytes[5]);
1364         }
1365
1366         /* Copy the permanent MAC address */
1367         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1368
1369         /* reset the hardware with the new settings */
1370         diag = hw->mac.ops.start_hw(hw);
1371         switch (diag) {
1372                 case  0:
1373                         break;
1374
1375                 default:
1376                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1377                         return (-EIO);
1378         }
1379
1380         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1381                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1382                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1383
1384         return 0;
1385 }
1386
1387 /* Virtual Function device uninit */
1388
1389 static int
1390 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1391 {
1392         struct ixgbe_hw *hw;
1393         unsigned i;
1394
1395         PMD_INIT_FUNC_TRACE();
1396
1397         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1398                 return -EPERM;
1399
1400         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1401
1402         if (hw->adapter_stopped == 0)
1403                 ixgbevf_dev_close(eth_dev);
1404
1405         eth_dev->dev_ops = NULL;
1406         eth_dev->rx_pkt_burst = NULL;
1407         eth_dev->tx_pkt_burst = NULL;
1408
1409         /* Disable the interrupts for VF */
1410         ixgbevf_intr_disable(hw);
1411
1412         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1413                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1414                 eth_dev->data->rx_queues[i] = NULL;
1415         }
1416         eth_dev->data->nb_rx_queues = 0;
1417
1418         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1419                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1420                 eth_dev->data->tx_queues[i] = NULL;
1421         }
1422         eth_dev->data->nb_tx_queues = 0;
1423
1424         rte_free(eth_dev->data->mac_addrs);
1425         eth_dev->data->mac_addrs = NULL;
1426
1427         return 0;
1428 }
1429
1430 static struct eth_driver rte_ixgbe_pmd = {
1431         .pci_drv = {
1432                 .name = "rte_ixgbe_pmd",
1433                 .id_table = pci_id_ixgbe_map,
1434                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1435                         RTE_PCI_DRV_DETACHABLE,
1436         },
1437         .eth_dev_init = eth_ixgbe_dev_init,
1438         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1439         .dev_private_size = sizeof(struct ixgbe_adapter),
1440 };
1441
1442 /*
1443  * virtual function driver struct
1444  */
1445 static struct eth_driver rte_ixgbevf_pmd = {
1446         .pci_drv = {
1447                 .name = "rte_ixgbevf_pmd",
1448                 .id_table = pci_id_ixgbevf_map,
1449                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1450         },
1451         .eth_dev_init = eth_ixgbevf_dev_init,
1452         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1453         .dev_private_size = sizeof(struct ixgbe_adapter),
1454 };
1455
1456 /*
1457  * Driver initialization routine.
1458  * Invoked once at EAL init time.
1459  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1460  */
1461 static int
1462 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1463 {
1464         PMD_INIT_FUNC_TRACE();
1465
1466         rte_eth_driver_register(&rte_ixgbe_pmd);
1467         return 0;
1468 }
1469
1470 /*
1471  * VF Driver initialization routine.
1472  * Invoked one at EAL init time.
1473  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1474  */
1475 static int
1476 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1477 {
1478         PMD_INIT_FUNC_TRACE();
1479
1480         rte_eth_driver_register(&rte_ixgbevf_pmd);
1481         return (0);
1482 }
1483
1484 static int
1485 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1486 {
1487         struct ixgbe_hw *hw =
1488                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489         struct ixgbe_vfta * shadow_vfta =
1490                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1491         uint32_t vfta;
1492         uint32_t vid_idx;
1493         uint32_t vid_bit;
1494
1495         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1496         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1497         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1498         if (on)
1499                 vfta |= vid_bit;
1500         else
1501                 vfta &= ~vid_bit;
1502         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1503
1504         /* update local VFTA copy */
1505         shadow_vfta->vfta[vid_idx] = vfta;
1506
1507         return 0;
1508 }
1509
1510 static void
1511 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1512 {
1513         if (on)
1514                 ixgbe_vlan_hw_strip_enable(dev, queue);
1515         else
1516                 ixgbe_vlan_hw_strip_disable(dev, queue);
1517 }
1518
1519 static void
1520 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1521 {
1522         struct ixgbe_hw *hw =
1523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524
1525         /* Only the high 16-bits is valid */
1526         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1527 }
1528
1529 void
1530 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1531 {
1532         struct ixgbe_hw *hw =
1533                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1534         uint32_t vlnctrl;
1535
1536         PMD_INIT_FUNC_TRACE();
1537
1538         /* Filter Table Disable */
1539         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1540         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1541
1542         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1543 }
1544
1545 void
1546 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1547 {
1548         struct ixgbe_hw *hw =
1549                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550         struct ixgbe_vfta * shadow_vfta =
1551                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1552         uint32_t vlnctrl;
1553         uint16_t i;
1554
1555         PMD_INIT_FUNC_TRACE();
1556
1557         /* Filter Table Enable */
1558         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1559         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1560         vlnctrl |= IXGBE_VLNCTRL_VFE;
1561
1562         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1563
1564         /* write whatever is in local vfta copy */
1565         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1566                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1567 }
1568
1569 static void
1570 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1571 {
1572         struct ixgbe_hwstrip *hwstrip =
1573                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1574
1575         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1576                 return;
1577
1578         if (on)
1579                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1580         else
1581                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1582 }
1583
1584 static void
1585 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1586 {
1587         struct ixgbe_hw *hw =
1588                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1589         uint32_t ctrl;
1590
1591         PMD_INIT_FUNC_TRACE();
1592
1593         if (hw->mac.type == ixgbe_mac_82598EB) {
1594                 /* No queue level support */
1595                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1596                 return;
1597         }
1598         else {
1599                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1600                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1601                 ctrl &= ~IXGBE_RXDCTL_VME;
1602                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1603         }
1604         /* record those setting for HW strip per queue */
1605         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1606 }
1607
1608 static void
1609 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1610 {
1611         struct ixgbe_hw *hw =
1612                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613         uint32_t ctrl;
1614
1615         PMD_INIT_FUNC_TRACE();
1616
1617         if (hw->mac.type == ixgbe_mac_82598EB) {
1618                 /* No queue level supported */
1619                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1620                 return;
1621         }
1622         else {
1623                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1624                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1625                 ctrl |= IXGBE_RXDCTL_VME;
1626                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1627         }
1628         /* record those setting for HW strip per queue */
1629         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1630 }
1631
1632 void
1633 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1634 {
1635         struct ixgbe_hw *hw =
1636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         uint32_t ctrl;
1638         uint16_t i;
1639
1640         PMD_INIT_FUNC_TRACE();
1641
1642         if (hw->mac.type == ixgbe_mac_82598EB) {
1643                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1644                 ctrl &= ~IXGBE_VLNCTRL_VME;
1645                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1646         }
1647         else {
1648                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1649                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1650                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1651                         ctrl &= ~IXGBE_RXDCTL_VME;
1652                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1653
1654                         /* record those setting for HW strip per queue */
1655                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1656                 }
1657         }
1658 }
1659
1660 void
1661 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1662 {
1663         struct ixgbe_hw *hw =
1664                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665         uint32_t ctrl;
1666         uint16_t i;
1667
1668         PMD_INIT_FUNC_TRACE();
1669
1670         if (hw->mac.type == ixgbe_mac_82598EB) {
1671                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1672                 ctrl |= IXGBE_VLNCTRL_VME;
1673                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1674         }
1675         else {
1676                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1677                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1678                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1679                         ctrl |= IXGBE_RXDCTL_VME;
1680                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1681
1682                         /* record those setting for HW strip per queue */
1683                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1684                 }
1685         }
1686 }
1687
1688 static void
1689 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1690 {
1691         struct ixgbe_hw *hw =
1692                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1693         uint32_t ctrl;
1694
1695         PMD_INIT_FUNC_TRACE();
1696
1697         /* DMATXCTRL: Geric Double VLAN Disable */
1698         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1699         ctrl &= ~IXGBE_DMATXCTL_GDV;
1700         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1701
1702         /* CTRL_EXT: Global Double VLAN Disable */
1703         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1704         ctrl &= ~IXGBE_EXTENDED_VLAN;
1705         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1706
1707 }
1708
1709 static void
1710 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1711 {
1712         struct ixgbe_hw *hw =
1713                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1714         uint32_t ctrl;
1715
1716         PMD_INIT_FUNC_TRACE();
1717
1718         /* DMATXCTRL: Geric Double VLAN Enable */
1719         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1720         ctrl |= IXGBE_DMATXCTL_GDV;
1721         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1722
1723         /* CTRL_EXT: Global Double VLAN Enable */
1724         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1725         ctrl |= IXGBE_EXTENDED_VLAN;
1726         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1727
1728         /*
1729          * VET EXT field in the EXVET register = 0x8100 by default
1730          * So no need to change. Same to VT field of DMATXCTL register
1731          */
1732 }
1733
1734 static void
1735 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1736 {
1737         if(mask & ETH_VLAN_STRIP_MASK){
1738                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1739                         ixgbe_vlan_hw_strip_enable_all(dev);
1740                 else
1741                         ixgbe_vlan_hw_strip_disable_all(dev);
1742         }
1743
1744         if(mask & ETH_VLAN_FILTER_MASK){
1745                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1746                         ixgbe_vlan_hw_filter_enable(dev);
1747                 else
1748                         ixgbe_vlan_hw_filter_disable(dev);
1749         }
1750
1751         if(mask & ETH_VLAN_EXTEND_MASK){
1752                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1753                         ixgbe_vlan_hw_extend_enable(dev);
1754                 else
1755                         ixgbe_vlan_hw_extend_disable(dev);
1756         }
1757 }
1758
1759 static void
1760 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1761 {
1762         struct ixgbe_hw *hw =
1763                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1765         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1766         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1767         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1768 }
1769
1770 static int
1771 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1772 {
1773         switch (nb_rx_q) {
1774         case 1:
1775         case 2:
1776                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1777                 break;
1778         case 4:
1779                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1780                 break;
1781         default:
1782                 return -EINVAL;
1783         }
1784
1785         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1786         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1787
1788         return 0;
1789 }
1790
1791 static int
1792 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1793 {
1794         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1795         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1796         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1797
1798         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1799                 /* check multi-queue mode */
1800                 switch (dev_conf->rxmode.mq_mode) {
1801                 case ETH_MQ_RX_VMDQ_DCB:
1802                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1803                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1804                         PMD_INIT_LOG(ERR, "SRIOV active,"
1805                                         " unsupported mq_mode rx %d.",
1806                                         dev_conf->rxmode.mq_mode);
1807                         return -EINVAL;
1808                 case ETH_MQ_RX_RSS:
1809                 case ETH_MQ_RX_VMDQ_RSS:
1810                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1811                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1812                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1813                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1814                                                 " invalid queue number"
1815                                                 " for VMDQ RSS, allowed"
1816                                                 " value are 1, 2 or 4.");
1817                                         return -EINVAL;
1818                                 }
1819                         break;
1820                 case ETH_MQ_RX_VMDQ_ONLY:
1821                 case ETH_MQ_RX_NONE:
1822                         /* if nothing mq mode configure, use default scheme */
1823                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1824                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1825                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1826                         break;
1827                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1828                         /* SRIOV only works in VMDq enable mode */
1829                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1830                                         " wrong mq_mode rx %d.",
1831                                         dev_conf->rxmode.mq_mode);
1832                         return -EINVAL;
1833                 }
1834
1835                 switch (dev_conf->txmode.mq_mode) {
1836                 case ETH_MQ_TX_VMDQ_DCB:
1837                         /* DCB VMDQ in SRIOV mode, not implement yet */
1838                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1839                                         " unsupported VMDQ mq_mode tx %d.",
1840                                         dev_conf->txmode.mq_mode);
1841                         return -EINVAL;
1842                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1843                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1844                         break;
1845                 }
1846
1847                 /* check valid queue number */
1848                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1849                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1850                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1851                                         " queue number must less equal to %d.",
1852                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1853                         return -EINVAL;
1854                 }
1855         } else {
1856                 /* check configuration for vmdb+dcb mode */
1857                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1858                         const struct rte_eth_vmdq_dcb_conf *conf;
1859
1860                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1861                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1862                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1863                                 return -EINVAL;
1864                         }
1865                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1866                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1867                                conf->nb_queue_pools == ETH_32_POOLS)) {
1868                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1869                                                 " nb_queue_pools must be %d or %d.",
1870                                                 ETH_16_POOLS, ETH_32_POOLS);
1871                                 return -EINVAL;
1872                         }
1873                 }
1874                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1875                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1876
1877                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1878                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1879                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1880                                 return -EINVAL;
1881                         }
1882                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1883                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1884                                conf->nb_queue_pools == ETH_32_POOLS)) {
1885                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1886                                                 " nb_queue_pools != %d and"
1887                                                 " nb_queue_pools != %d.",
1888                                                 ETH_16_POOLS, ETH_32_POOLS);
1889                                 return -EINVAL;
1890                         }
1891                 }
1892
1893                 /* For DCB mode check our configuration before we go further */
1894                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1895                         const struct rte_eth_dcb_rx_conf *conf;
1896
1897                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1898                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1899                                                  IXGBE_DCB_NB_QUEUES);
1900                                 return -EINVAL;
1901                         }
1902                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1903                         if (!(conf->nb_tcs == ETH_4_TCS ||
1904                                conf->nb_tcs == ETH_8_TCS)) {
1905                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1906                                                 " and nb_tcs != %d.",
1907                                                 ETH_4_TCS, ETH_8_TCS);
1908                                 return -EINVAL;
1909                         }
1910                 }
1911
1912                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1913                         const struct rte_eth_dcb_tx_conf *conf;
1914
1915                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1916                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1917                                                  IXGBE_DCB_NB_QUEUES);
1918                                 return -EINVAL;
1919                         }
1920                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1921                         if (!(conf->nb_tcs == ETH_4_TCS ||
1922                                conf->nb_tcs == ETH_8_TCS)) {
1923                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1924                                                 " and nb_tcs != %d.",
1925                                                 ETH_4_TCS, ETH_8_TCS);
1926                                 return -EINVAL;
1927                         }
1928                 }
1929         }
1930         return 0;
1931 }
1932
1933 static int
1934 ixgbe_dev_configure(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_interrupt *intr =
1937                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1938         struct ixgbe_adapter *adapter =
1939                 (struct ixgbe_adapter *)dev->data->dev_private;
1940         int ret;
1941
1942         PMD_INIT_FUNC_TRACE();
1943         /* multipe queue mode checking */
1944         ret  = ixgbe_check_mq_mode(dev);
1945         if (ret != 0) {
1946                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1947                             ret);
1948                 return ret;
1949         }
1950
1951         /* set flag to update link status after init */
1952         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1953
1954         /*
1955          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1956          * allocation or vector Rx preconditions we will reset it.
1957          */
1958         adapter->rx_bulk_alloc_allowed = true;
1959         adapter->rx_vec_allowed = true;
1960
1961         return 0;
1962 }
1963
1964 /*
1965  * Configure device link speed and setup link.
1966  * It returns 0 on success.
1967  */
1968 static int
1969 ixgbe_dev_start(struct rte_eth_dev *dev)
1970 {
1971         struct ixgbe_hw *hw =
1972                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973         struct ixgbe_vf_info *vfinfo =
1974                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1975         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1976         uint32_t intr_vector = 0;
1977         int err, link_up = 0, negotiate = 0;
1978         uint32_t speed = 0;
1979         int mask = 0;
1980         int status;
1981         uint16_t vf, idx;
1982
1983         PMD_INIT_FUNC_TRACE();
1984
1985         /* IXGBE devices don't support half duplex */
1986         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1987                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1988                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1989                              dev->data->dev_conf.link_duplex,
1990                              dev->data->port_id);
1991                 return -EINVAL;
1992         }
1993
1994         /* stop adapter */
1995         hw->adapter_stopped = 0;
1996         ixgbe_stop_adapter(hw);
1997
1998         /* reinitialize adapter
1999          * this calls reset and start */
2000         status = ixgbe_pf_reset_hw(hw);
2001         if (status != 0)
2002                 return -1;
2003         hw->mac.ops.start_hw(hw);
2004         hw->mac.get_link_status = true;
2005
2006         /* configure PF module if SRIOV enabled */
2007         ixgbe_pf_host_configure(dev);
2008
2009         /* check and configure queue intr-vector mapping */
2010         if ((rte_intr_cap_multiple(intr_handle) ||
2011              !RTE_ETH_DEV_SRIOV(dev).active) &&
2012             dev->data->dev_conf.intr_conf.rxq != 0) {
2013                 intr_vector = dev->data->nb_rx_queues;
2014                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2015                         return -1;
2016         }
2017
2018         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2019                 intr_handle->intr_vec =
2020                         rte_zmalloc("intr_vec",
2021                                     dev->data->nb_rx_queues * sizeof(int), 0);
2022                 if (intr_handle->intr_vec == NULL) {
2023                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2024                                      " intr_vec\n", dev->data->nb_rx_queues);
2025                         return -ENOMEM;
2026                 }
2027         }
2028
2029         /* confiugre msix for sleep until rx interrupt */
2030         ixgbe_configure_msix(dev);
2031
2032         /* initialize transmission unit */
2033         ixgbe_dev_tx_init(dev);
2034
2035         /* This can fail when allocating mbufs for descriptor rings */
2036         err = ixgbe_dev_rx_init(dev);
2037         if (err) {
2038                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2039                 goto error;
2040         }
2041
2042         err = ixgbe_dev_rxtx_start(dev);
2043         if (err < 0) {
2044                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2045                 goto error;
2046         }
2047
2048         /* Skip link setup if loopback mode is enabled for 82599. */
2049         if (hw->mac.type == ixgbe_mac_82599EB &&
2050                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2051                 goto skip_link_setup;
2052
2053         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2054                 err = hw->mac.ops.setup_sfp(hw);
2055                 if (err)
2056                         goto error;
2057         }
2058
2059         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2060                 /* Turn on the copper */
2061                 ixgbe_set_phy_power(hw, true);
2062         } else {
2063                 /* Turn on the laser */
2064                 ixgbe_enable_tx_laser(hw);
2065         }
2066
2067         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2068         if (err)
2069                 goto error;
2070         dev->data->dev_link.link_status = link_up;
2071
2072         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2073         if (err)
2074                 goto error;
2075
2076         switch(dev->data->dev_conf.link_speed) {
2077         case ETH_LINK_SPEED_AUTONEG:
2078                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2079                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2080                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2081                 break;
2082         case ETH_LINK_SPEED_100:
2083                 /*
2084                  * Invalid for 82598 but error will be detected by
2085                  * ixgbe_setup_link()
2086                  */
2087                 speed = IXGBE_LINK_SPEED_100_FULL;
2088                 break;
2089         case ETH_LINK_SPEED_1000:
2090                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2091                 break;
2092         case ETH_LINK_SPEED_10000:
2093                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2094                 break;
2095         default:
2096                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2097                              dev->data->dev_conf.link_speed,
2098                              dev->data->port_id);
2099                 goto error;
2100         }
2101
2102         err = ixgbe_setup_link(hw, speed, link_up);
2103         if (err)
2104                 goto error;
2105
2106 skip_link_setup:
2107
2108         if (rte_intr_allow_others(intr_handle)) {
2109                 /* check if lsc interrupt is enabled */
2110                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2111                         ixgbe_dev_lsc_interrupt_setup(dev);
2112         } else {
2113                 rte_intr_callback_unregister(intr_handle,
2114                                              ixgbe_dev_interrupt_handler,
2115                                              (void *)dev);
2116                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2117                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2118                                      " no intr multiplex\n");
2119         }
2120
2121         /* check if rxq interrupt is enabled */
2122         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2123             rte_intr_dp_is_en(intr_handle))
2124                 ixgbe_dev_rxq_interrupt_setup(dev);
2125
2126         /* enable uio/vfio intr/eventfd mapping */
2127         rte_intr_enable(intr_handle);
2128
2129         /* resume enabled intr since hw reset */
2130         ixgbe_enable_intr(dev);
2131
2132         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2133                 ETH_VLAN_EXTEND_MASK;
2134         ixgbe_vlan_offload_set(dev, mask);
2135
2136         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2137                 /* Enable vlan filtering for VMDq */
2138                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2139         }
2140
2141         /* Configure DCB hw */
2142         ixgbe_configure_dcb(dev);
2143
2144         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2145                 err = ixgbe_fdir_configure(dev);
2146                 if (err)
2147                         goto error;
2148         }
2149
2150         /* Restore vf rate limit */
2151         if (vfinfo != NULL) {
2152                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2153                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2154                                 if (vfinfo[vf].tx_rate[idx] != 0)
2155                                         ixgbe_set_vf_rate_limit(dev, vf,
2156                                                 vfinfo[vf].tx_rate[idx],
2157                                                 1 << idx);
2158         }
2159
2160         ixgbe_restore_statistics_mapping(dev);
2161
2162         return (0);
2163
2164 error:
2165         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2166         ixgbe_dev_clear_queues(dev);
2167         return -EIO;
2168 }
2169
2170 /*
2171  * Stop device: disable rx and tx functions to allow for reconfiguring.
2172  */
2173 static void
2174 ixgbe_dev_stop(struct rte_eth_dev *dev)
2175 {
2176         struct rte_eth_link link;
2177         struct ixgbe_hw *hw =
2178                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2179         struct ixgbe_vf_info *vfinfo =
2180                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2181         struct ixgbe_filter_info *filter_info =
2182                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2183         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2184         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2185         int vf;
2186
2187         PMD_INIT_FUNC_TRACE();
2188
2189         /* disable interrupts */
2190         ixgbe_disable_intr(hw);
2191
2192         /* disable intr eventfd mapping */
2193         rte_intr_disable(intr_handle);
2194
2195         /* reset the NIC */
2196         ixgbe_pf_reset_hw(hw);
2197         hw->adapter_stopped = 0;
2198
2199         /* stop adapter */
2200         ixgbe_stop_adapter(hw);
2201
2202         for (vf = 0; vfinfo != NULL &&
2203                      vf < dev->pci_dev->max_vfs; vf++)
2204                 vfinfo[vf].clear_to_send = false;
2205
2206         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2207                 /* Turn off the copper */
2208                 ixgbe_set_phy_power(hw, false);
2209         } else {
2210                 /* Turn off the laser */
2211                 ixgbe_disable_tx_laser(hw);
2212         }
2213
2214         ixgbe_dev_clear_queues(dev);
2215
2216         /* Clear stored conf */
2217         dev->data->scattered_rx = 0;
2218         dev->data->lro = 0;
2219
2220         /* Clear recorded link status */
2221         memset(&link, 0, sizeof(link));
2222         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2223
2224         /* Remove all ntuple filters of the device */
2225         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2226              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2227                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2228                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2229                              p_5tuple, entries);
2230                 rte_free(p_5tuple);
2231         }
2232         memset(filter_info->fivetuple_mask, 0,
2233                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2234
2235         if (!rte_intr_allow_others(intr_handle))
2236                 /* resume to the default handler */
2237                 rte_intr_callback_register(intr_handle,
2238                                            ixgbe_dev_interrupt_handler,
2239                                            (void *)dev);
2240
2241         /* Clean datapath event and queue/vec mapping */
2242         rte_intr_efd_disable(intr_handle);
2243         if (intr_handle->intr_vec != NULL) {
2244                 rte_free(intr_handle->intr_vec);
2245                 intr_handle->intr_vec = NULL;
2246         }
2247 }
2248
2249 /*
2250  * Set device link up: enable tx.
2251  */
2252 static int
2253 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2254 {
2255         struct ixgbe_hw *hw =
2256                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2257         if (hw->mac.type == ixgbe_mac_82599EB) {
2258 #ifdef RTE_NIC_BYPASS
2259                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2260                         /* Not suported in bypass mode */
2261                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2262                                      "by device id 0x%x", hw->device_id);
2263                         return -ENOTSUP;
2264                 }
2265 #endif
2266         }
2267
2268         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2269                 /* Turn on the copper */
2270                 ixgbe_set_phy_power(hw, true);
2271         } else {
2272                 /* Turn on the laser */
2273                 ixgbe_enable_tx_laser(hw);
2274         }
2275
2276         return 0;
2277 }
2278
2279 /*
2280  * Set device link down: disable tx.
2281  */
2282 static int
2283 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2284 {
2285         struct ixgbe_hw *hw =
2286                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         if (hw->mac.type == ixgbe_mac_82599EB) {
2288 #ifdef RTE_NIC_BYPASS
2289                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2290                         /* Not suported in bypass mode */
2291                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2292                                      "by device id 0x%x", hw->device_id);
2293                         return -ENOTSUP;
2294                 }
2295 #endif
2296         }
2297
2298         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2299                 /* Turn off the copper */
2300                 ixgbe_set_phy_power(hw, false);
2301         } else {
2302                 /* Turn off the laser */
2303                 ixgbe_disable_tx_laser(hw);
2304         }
2305
2306         return 0;
2307 }
2308
2309 /*
2310  * Reest and stop device.
2311  */
2312 static void
2313 ixgbe_dev_close(struct rte_eth_dev *dev)
2314 {
2315         struct ixgbe_hw *hw =
2316                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317
2318         PMD_INIT_FUNC_TRACE();
2319
2320         ixgbe_pf_reset_hw(hw);
2321
2322         ixgbe_dev_stop(dev);
2323         hw->adapter_stopped = 1;
2324
2325         ixgbe_dev_free_queues(dev);
2326
2327         ixgbe_disable_pcie_master(hw);
2328
2329         /* reprogram the RAR[0] in case user changed it. */
2330         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2331 }
2332
2333 static void
2334 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2335                                                    *hw_stats, uint64_t *total_missed_rx,
2336                                                    uint64_t *total_qbrc, uint64_t *total_qprc,
2337                                                    uint64_t *total_qprdc)
2338 {
2339         uint32_t bprc, lxon, lxoff, total;
2340         unsigned i;
2341
2342         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2343         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2344         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2345         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2346
2347         for (i = 0; i < 8; i++) {
2348                 uint32_t mp;
2349                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2350                 /* global total per queue */
2351                 hw_stats->mpc[i] += mp;
2352                 /* Running comprehensive total for stats display */
2353                 *total_missed_rx += hw_stats->mpc[i];
2354                 if (hw->mac.type == ixgbe_mac_82598EB) {
2355                         hw_stats->rnbc[i] +=
2356                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2357                         hw_stats->pxonrxc[i] +=
2358                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2359                         hw_stats->pxoffrxc[i] +=
2360                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2361                 } else {
2362                         hw_stats->pxonrxc[i] +=
2363                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2364                         hw_stats->pxoffrxc[i] +=
2365                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2366                         hw_stats->pxon2offc[i] +=
2367                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2368                 }
2369                 hw_stats->pxontxc[i] +=
2370                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2371                 hw_stats->pxofftxc[i] +=
2372                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2373         }
2374         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2375                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2376                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2377                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2378                 hw_stats->qbrc[i] +=
2379                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2380                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2381                 hw_stats->qbtc[i] +=
2382                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2383                 *total_qprdc += hw_stats->qprdc[i] +=
2384                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2385
2386                 *total_qprc += hw_stats->qprc[i];
2387                 *total_qbrc += hw_stats->qbrc[i];
2388         }
2389         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2390         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2391         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2392
2393         /* Note that gprc counts missed packets */
2394         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2395
2396         if (hw->mac.type != ixgbe_mac_82598EB) {
2397                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2398                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2399                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2400                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2401                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2402                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2403                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2404                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2405         } else {
2406                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2407                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2408                 /* 82598 only has a counter in the high register */
2409                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2410                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2411                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2412         }
2413
2414         /*
2415          * Workaround: mprc hardware is incorrectly counting
2416          * broadcasts, so for now we subtract those.
2417          */
2418         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2419         hw_stats->bprc += bprc;
2420         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2421         if (hw->mac.type == ixgbe_mac_82598EB)
2422                 hw_stats->mprc -= bprc;
2423
2424         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2425         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2426         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2427         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2428         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2429         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2430
2431         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2432         hw_stats->lxontxc += lxon;
2433         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2434         hw_stats->lxofftxc += lxoff;
2435         total = lxon + lxoff;
2436
2437         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2438         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2439         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2440         hw_stats->gptc -= total;
2441         hw_stats->mptc -= total;
2442         hw_stats->ptc64 -= total;
2443         hw_stats->gotc -= total * ETHER_MIN_LEN;
2444
2445         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2446         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2447         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2448         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2449         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2450         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2451         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2452         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2453         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2454         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2455         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2456         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2457         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2458         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2459         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2460         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2461         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2462         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2463         /* Only read FCOE on 82599 */
2464         if (hw->mac.type != ixgbe_mac_82598EB) {
2465                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2466                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2467                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2468                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2469                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2470         }
2471
2472         /* Flow Director Stats registers */
2473         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2474         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2475 }
2476
2477 /*
2478  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2479  */
2480 static void
2481 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2482 {
2483         struct ixgbe_hw *hw =
2484                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2485         struct ixgbe_hw_stats *hw_stats =
2486                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2487         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2488         unsigned i;
2489
2490         total_missed_rx = 0;
2491         total_qbrc = 0;
2492         total_qprc = 0;
2493         total_qprdc = 0;
2494
2495         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2496                         &total_qprc, &total_qprdc);
2497
2498         if (stats == NULL)
2499                 return;
2500
2501         /* Fill out the rte_eth_stats statistics structure */
2502         stats->ipackets = total_qprc;
2503         stats->ibytes = total_qbrc;
2504         stats->opackets = hw_stats->gptc;
2505         stats->obytes = hw_stats->gotc;
2506
2507         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2508                 stats->q_ipackets[i] = hw_stats->qprc[i];
2509                 stats->q_opackets[i] = hw_stats->qptc[i];
2510                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2511                 stats->q_obytes[i] = hw_stats->qbtc[i];
2512                 stats->q_errors[i] = hw_stats->qprdc[i];
2513         }
2514
2515         /* Rx Errors */
2516         stats->ierrors  = hw_stats->crcerrs +
2517                           hw_stats->mspdc +
2518                           hw_stats->rlec +
2519                           hw_stats->ruc +
2520                           hw_stats->roc +
2521                           total_missed_rx +
2522                           hw_stats->illerrc +
2523                           hw_stats->errbc +
2524                           hw_stats->rfc +
2525                           hw_stats->fccrc +
2526                           hw_stats->fclast;
2527
2528         /* Tx Errors */
2529         stats->oerrors  = 0;
2530 }
2531
2532 static void
2533 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2534 {
2535         struct ixgbe_hw_stats *stats =
2536                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2537
2538         /* HW registers are cleared on read */
2539         ixgbe_dev_stats_get(dev, NULL);
2540
2541         /* Reset software totals */
2542         memset(stats, 0, sizeof(*stats));
2543 }
2544
2545 /* This function calculates the number of xstats based on the current config */
2546 static unsigned
2547 ixgbe_xstats_calc_num(void) {
2548         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2549                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2550 }
2551
2552 static int
2553 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2554                                          unsigned n)
2555 {
2556         struct ixgbe_hw *hw =
2557                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2558         struct ixgbe_hw_stats *hw_stats =
2559                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2560         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2561         unsigned i, stat, count = 0;
2562
2563         count = ixgbe_xstats_calc_num();
2564
2565         if (n < count)
2566                 return count;
2567
2568         total_missed_rx = 0;
2569         total_qbrc = 0;
2570         total_qprc = 0;
2571         total_qprdc = 0;
2572
2573         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2574                                    &total_qprc, &total_qprdc);
2575
2576         /* If this is a reset xstats is NULL, and we have cleared the
2577          * registers by reading them.
2578          */
2579         if (!xstats)
2580                 return 0;
2581
2582         /* Extended stats from ixgbe_hw_stats */
2583         count = 0;
2584         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2585                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2586                          rte_ixgbe_stats_strings[i].name);
2587                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2588                                 rte_ixgbe_stats_strings[i].offset);
2589                 count++;
2590         }
2591
2592         /* RX Priority Stats */
2593         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2594                 for (i = 0; i < 8; i++) {
2595                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2596                                  "rx_priority%u_%s", i,
2597                                  rte_ixgbe_rxq_strings[stat].name);
2598                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2599                                         rte_ixgbe_rxq_strings[stat].offset +
2600                                         (sizeof(uint64_t) * i));
2601                         count++;
2602                 }
2603         }
2604
2605         /* TX Priority Stats */
2606         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2607                 for (i = 0; i < 8; i++) {
2608                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2609                                  "tx_priority%u_%s", i,
2610                                  rte_ixgbe_txq_strings[stat].name);
2611                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2612                                         rte_ixgbe_txq_strings[stat].offset +
2613                                         (sizeof(uint64_t) * i));
2614                         count++;
2615                 }
2616         }
2617
2618         return count;
2619 }
2620
2621 static void
2622 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2623 {
2624         struct ixgbe_hw_stats *stats =
2625                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2626
2627         unsigned count = ixgbe_xstats_calc_num();
2628
2629         /* HW registers are cleared on read */
2630         ixgbe_dev_xstats_get(dev, NULL, count);
2631
2632         /* Reset software totals */
2633         memset(stats, 0, sizeof(*stats));
2634 }
2635
2636 static void
2637 ixgbevf_update_stats(struct rte_eth_dev *dev)
2638 {
2639         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2641                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2642
2643         /* Good Rx packet, include VF loopback */
2644         UPDATE_VF_STAT(IXGBE_VFGPRC,
2645             hw_stats->last_vfgprc, hw_stats->vfgprc);
2646
2647         /* Good Rx octets, include VF loopback */
2648         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2649             hw_stats->last_vfgorc, hw_stats->vfgorc);
2650
2651         /* Good Tx packet, include VF loopback */
2652         UPDATE_VF_STAT(IXGBE_VFGPTC,
2653             hw_stats->last_vfgptc, hw_stats->vfgptc);
2654
2655         /* Good Tx octets, include VF loopback */
2656         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2657             hw_stats->last_vfgotc, hw_stats->vfgotc);
2658
2659         /* Rx Multicst Packet */
2660         UPDATE_VF_STAT(IXGBE_VFMPRC,
2661             hw_stats->last_vfmprc, hw_stats->vfmprc);
2662 }
2663
2664 static int
2665 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2666                        unsigned n)
2667 {
2668         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2669                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2670         unsigned i;
2671
2672         if (n < IXGBEVF_NB_XSTATS)
2673                 return IXGBEVF_NB_XSTATS;
2674
2675         ixgbevf_update_stats(dev);
2676
2677         if (!xstats)
2678                 return 0;
2679
2680         /* Extended stats */
2681         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2682                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2683                          "%s", rte_ixgbevf_stats_strings[i].name);
2684                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2685                         rte_ixgbevf_stats_strings[i].offset);
2686         }
2687
2688         return IXGBEVF_NB_XSTATS;
2689 }
2690
2691 static void
2692 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2693 {
2694         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2695                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2696
2697         ixgbevf_update_stats(dev);
2698
2699         if (stats == NULL)
2700                 return;
2701
2702         stats->ipackets = hw_stats->vfgprc;
2703         stats->ibytes = hw_stats->vfgorc;
2704         stats->opackets = hw_stats->vfgptc;
2705         stats->obytes = hw_stats->vfgotc;
2706         stats->imcasts = hw_stats->vfmprc;
2707         /* stats->imcasts should be removed as imcasts is deprecated */
2708 }
2709
2710 static void
2711 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2712 {
2713         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2714                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2715
2716         /* Sync HW register to the last stats */
2717         ixgbevf_dev_stats_get(dev, NULL);
2718
2719         /* reset HW current stats*/
2720         hw_stats->vfgprc = 0;
2721         hw_stats->vfgorc = 0;
2722         hw_stats->vfgptc = 0;
2723         hw_stats->vfgotc = 0;
2724         hw_stats->vfmprc = 0;
2725
2726 }
2727
2728 static void
2729 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2730 {
2731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2732
2733         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2734         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2735         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2736         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2737         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2738         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2739         dev_info->max_vfs = dev->pci_dev->max_vfs;
2740         if (hw->mac.type == ixgbe_mac_82598EB)
2741                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2742         else
2743                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2744         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2745         dev_info->rx_offload_capa =
2746                 DEV_RX_OFFLOAD_VLAN_STRIP |
2747                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2748                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2749                 DEV_RX_OFFLOAD_TCP_CKSUM;
2750
2751         /*
2752          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2753          * mode.
2754          */
2755         if ((hw->mac.type == ixgbe_mac_82599EB ||
2756              hw->mac.type == ixgbe_mac_X540) &&
2757             !RTE_ETH_DEV_SRIOV(dev).active)
2758                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2759
2760         dev_info->tx_offload_capa =
2761                 DEV_TX_OFFLOAD_VLAN_INSERT |
2762                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2763                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2764                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2765                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2766                 DEV_TX_OFFLOAD_TCP_TSO;
2767
2768         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2769                 .rx_thresh = {
2770                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2771                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2772                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2773                 },
2774                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2775                 .rx_drop_en = 0,
2776         };
2777
2778         dev_info->default_txconf = (struct rte_eth_txconf) {
2779                 .tx_thresh = {
2780                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2781                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2782                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2783                 },
2784                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2785                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2786                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2787                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2788         };
2789
2790         dev_info->rx_desc_lim = rx_desc_lim;
2791         dev_info->tx_desc_lim = tx_desc_lim;
2792
2793         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2794         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2795         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2796 }
2797
2798 static void
2799 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2800                      struct rte_eth_dev_info *dev_info)
2801 {
2802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803
2804         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2805         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2806         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2807         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2808         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2809         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2810         dev_info->max_vfs = dev->pci_dev->max_vfs;
2811         if (hw->mac.type == ixgbe_mac_82598EB)
2812                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2813         else
2814                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2815         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2816                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2817                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2818                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2819         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2820                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2821                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2822                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2823                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2824                                 DEV_TX_OFFLOAD_TCP_TSO;
2825
2826         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2827                 .rx_thresh = {
2828                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2829                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2830                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2831                 },
2832                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2833                 .rx_drop_en = 0,
2834         };
2835
2836         dev_info->default_txconf = (struct rte_eth_txconf) {
2837                 .tx_thresh = {
2838                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2839                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2840                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2841                 },
2842                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2843                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2844                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2845                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2846         };
2847
2848         dev_info->rx_desc_lim = rx_desc_lim;
2849         dev_info->tx_desc_lim = tx_desc_lim;
2850 }
2851
2852 /* return 0 means link status changed, -1 means not changed */
2853 static int
2854 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2855 {
2856         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2857         struct rte_eth_link link, old;
2858         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2859         int link_up;
2860         int diag;
2861
2862         link.link_status = 0;
2863         link.link_speed = 0;
2864         link.link_duplex = 0;
2865         memset(&old, 0, sizeof(old));
2866         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2867
2868         hw->mac.get_link_status = true;
2869
2870         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2871         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2872                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2873         else
2874                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2875
2876         if (diag != 0) {
2877                 link.link_speed = ETH_LINK_SPEED_100;
2878                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2879                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2880                 if (link.link_status == old.link_status)
2881                         return -1;
2882                 return 0;
2883         }
2884
2885         if (link_up == 0) {
2886                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2887                 if (link.link_status == old.link_status)
2888                         return -1;
2889                 return 0;
2890         }
2891         link.link_status = 1;
2892         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2893
2894         switch (link_speed) {
2895         default:
2896         case IXGBE_LINK_SPEED_UNKNOWN:
2897                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2898                 link.link_speed = ETH_LINK_SPEED_100;
2899                 break;
2900
2901         case IXGBE_LINK_SPEED_100_FULL:
2902                 link.link_speed = ETH_LINK_SPEED_100;
2903                 break;
2904
2905         case IXGBE_LINK_SPEED_1GB_FULL:
2906                 link.link_speed = ETH_LINK_SPEED_1000;
2907                 break;
2908
2909         case IXGBE_LINK_SPEED_10GB_FULL:
2910                 link.link_speed = ETH_LINK_SPEED_10000;
2911                 break;
2912         }
2913         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2914
2915         if (link.link_status == old.link_status)
2916                 return -1;
2917
2918         return 0;
2919 }
2920
2921 static void
2922 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2923 {
2924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2925         uint32_t fctrl;
2926
2927         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2928         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2929         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2930 }
2931
2932 static void
2933 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2934 {
2935         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936         uint32_t fctrl;
2937
2938         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2939         fctrl &= (~IXGBE_FCTRL_UPE);
2940         if (dev->data->all_multicast == 1)
2941                 fctrl |= IXGBE_FCTRL_MPE;
2942         else
2943                 fctrl &= (~IXGBE_FCTRL_MPE);
2944         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2945 }
2946
2947 static void
2948 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2949 {
2950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951         uint32_t fctrl;
2952
2953         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2954         fctrl |= IXGBE_FCTRL_MPE;
2955         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2956 }
2957
2958 static void
2959 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2960 {
2961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962         uint32_t fctrl;
2963
2964         if (dev->data->promiscuous == 1)
2965                 return; /* must remain in all_multicast mode */
2966
2967         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2968         fctrl &= (~IXGBE_FCTRL_MPE);
2969         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2970 }
2971
2972 /**
2973  * It clears the interrupt causes and enables the interrupt.
2974  * It will be called once only during nic initialized.
2975  *
2976  * @param dev
2977  *  Pointer to struct rte_eth_dev.
2978  *
2979  * @return
2980  *  - On success, zero.
2981  *  - On failure, a negative value.
2982  */
2983 static int
2984 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2985 {
2986         struct ixgbe_interrupt *intr =
2987                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2988
2989         ixgbe_dev_link_status_print(dev);
2990         intr->mask |= IXGBE_EICR_LSC;
2991
2992         return 0;
2993 }
2994
2995 /**
2996  * It clears the interrupt causes and enables the interrupt.
2997  * It will be called once only during nic initialized.
2998  *
2999  * @param dev
3000  *  Pointer to struct rte_eth_dev.
3001  *
3002  * @return
3003  *  - On success, zero.
3004  *  - On failure, a negative value.
3005  */
3006 static int
3007 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3008 {
3009         struct ixgbe_interrupt *intr =
3010                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3011
3012         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3013
3014         return 0;
3015 }
3016
3017 /*
3018  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3019  *
3020  * @param dev
3021  *  Pointer to struct rte_eth_dev.
3022  *
3023  * @return
3024  *  - On success, zero.
3025  *  - On failure, a negative value.
3026  */
3027 static int
3028 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3029 {
3030         uint32_t eicr;
3031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3032         struct ixgbe_interrupt *intr =
3033                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3034
3035         /* clear all cause mask */
3036         ixgbe_disable_intr(hw);
3037
3038         /* read-on-clear nic registers here */
3039         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3040         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3041
3042         intr->flags = 0;
3043
3044         /* set flag for async link update */
3045         if (eicr & IXGBE_EICR_LSC)
3046                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3047
3048         if (eicr & IXGBE_EICR_MAILBOX)
3049                 intr->flags |= IXGBE_FLAG_MAILBOX;
3050
3051         return 0;
3052 }
3053
3054 /**
3055  * It gets and then prints the link status.
3056  *
3057  * @param dev
3058  *  Pointer to struct rte_eth_dev.
3059  *
3060  * @return
3061  *  - On success, zero.
3062  *  - On failure, a negative value.
3063  */
3064 static void
3065 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3066 {
3067         struct rte_eth_link link;
3068
3069         memset(&link, 0, sizeof(link));
3070         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3071         if (link.link_status) {
3072                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3073                                         (int)(dev->data->port_id),
3074                                         (unsigned)link.link_speed,
3075                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3076                                         "full-duplex" : "half-duplex");
3077         } else {
3078                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3079                                 (int)(dev->data->port_id));
3080         }
3081         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3082                                 dev->pci_dev->addr.domain,
3083                                 dev->pci_dev->addr.bus,
3084                                 dev->pci_dev->addr.devid,
3085                                 dev->pci_dev->addr.function);
3086 }
3087
3088 /*
3089  * It executes link_update after knowing an interrupt occurred.
3090  *
3091  * @param dev
3092  *  Pointer to struct rte_eth_dev.
3093  *
3094  * @return
3095  *  - On success, zero.
3096  *  - On failure, a negative value.
3097  */
3098 static int
3099 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3100 {
3101         struct ixgbe_interrupt *intr =
3102                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3103         int64_t timeout;
3104         struct rte_eth_link link;
3105         int intr_enable_delay = false;
3106
3107         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3108
3109         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3110                 ixgbe_pf_mbx_process(dev);
3111                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3112         }
3113
3114         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3115                 /* get the link status before link update, for predicting later */
3116                 memset(&link, 0, sizeof(link));
3117                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3118
3119                 ixgbe_dev_link_update(dev, 0);
3120
3121                 /* likely to up */
3122                 if (!link.link_status)
3123                         /* handle it 1 sec later, wait it being stable */
3124                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3125                 /* likely to down */
3126                 else
3127                         /* handle it 4 sec later, wait it being stable */
3128                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3129
3130                 ixgbe_dev_link_status_print(dev);
3131
3132                 intr_enable_delay = true;
3133         }
3134
3135         if (intr_enable_delay) {
3136                 if (rte_eal_alarm_set(timeout * 1000,
3137                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3138                         PMD_DRV_LOG(ERR, "Error setting alarm");
3139         } else {
3140                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3141                 ixgbe_enable_intr(dev);
3142                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3143         }
3144
3145
3146         return 0;
3147 }
3148
3149 /**
3150  * Interrupt handler which shall be registered for alarm callback for delayed
3151  * handling specific interrupt to wait for the stable nic state. As the
3152  * NIC interrupt state is not stable for ixgbe after link is just down,
3153  * it needs to wait 4 seconds to get the stable status.
3154  *
3155  * @param handle
3156  *  Pointer to interrupt handle.
3157  * @param param
3158  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3159  *
3160  * @return
3161  *  void
3162  */
3163 static void
3164 ixgbe_dev_interrupt_delayed_handler(void *param)
3165 {
3166         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3167         struct ixgbe_interrupt *intr =
3168                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3169         struct ixgbe_hw *hw =
3170                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3171         uint32_t eicr;
3172
3173         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3174         if (eicr & IXGBE_EICR_MAILBOX)
3175                 ixgbe_pf_mbx_process(dev);
3176
3177         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3178                 ixgbe_dev_link_update(dev, 0);
3179                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3180                 ixgbe_dev_link_status_print(dev);
3181                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3182         }
3183
3184         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3185         ixgbe_enable_intr(dev);
3186         rte_intr_enable(&(dev->pci_dev->intr_handle));
3187 }
3188
3189 /**
3190  * Interrupt handler triggered by NIC  for handling
3191  * specific interrupt.
3192  *
3193  * @param handle
3194  *  Pointer to interrupt handle.
3195  * @param param
3196  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3197  *
3198  * @return
3199  *  void
3200  */
3201 static void
3202 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3203                             void *param)
3204 {
3205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3206
3207         ixgbe_dev_interrupt_get_status(dev);
3208         ixgbe_dev_interrupt_action(dev);
3209 }
3210
3211 static int
3212 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3213 {
3214         struct ixgbe_hw *hw;
3215
3216         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3217         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3218 }
3219
3220 static int
3221 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3222 {
3223         struct ixgbe_hw *hw;
3224
3225         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3226         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3227 }
3228
3229 static int
3230 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3231 {
3232         struct ixgbe_hw *hw;
3233         uint32_t mflcn_reg;
3234         uint32_t fccfg_reg;
3235         int rx_pause;
3236         int tx_pause;
3237
3238         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3239
3240         fc_conf->pause_time = hw->fc.pause_time;
3241         fc_conf->high_water = hw->fc.high_water[0];
3242         fc_conf->low_water = hw->fc.low_water[0];
3243         fc_conf->send_xon = hw->fc.send_xon;
3244         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3245
3246         /*
3247          * Return rx_pause status according to actual setting of
3248          * MFLCN register.
3249          */
3250         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3251         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3252                 rx_pause = 1;
3253         else
3254                 rx_pause = 0;
3255
3256         /*
3257          * Return tx_pause status according to actual setting of
3258          * FCCFG register.
3259          */
3260         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3261         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3262                 tx_pause = 1;
3263         else
3264                 tx_pause = 0;
3265
3266         if (rx_pause && tx_pause)
3267                 fc_conf->mode = RTE_FC_FULL;
3268         else if (rx_pause)
3269                 fc_conf->mode = RTE_FC_RX_PAUSE;
3270         else if (tx_pause)
3271                 fc_conf->mode = RTE_FC_TX_PAUSE;
3272         else
3273                 fc_conf->mode = RTE_FC_NONE;
3274
3275         return 0;
3276 }
3277
3278 static int
3279 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3280 {
3281         struct ixgbe_hw *hw;
3282         int err;
3283         uint32_t rx_buf_size;
3284         uint32_t max_high_water;
3285         uint32_t mflcn;
3286         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3287                 ixgbe_fc_none,
3288                 ixgbe_fc_rx_pause,
3289                 ixgbe_fc_tx_pause,
3290                 ixgbe_fc_full
3291         };
3292
3293         PMD_INIT_FUNC_TRACE();
3294
3295         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3297         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3298
3299         /*
3300          * At least reserve one Ethernet frame for watermark
3301          * high_water/low_water in kilo bytes for ixgbe
3302          */
3303         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3304         if ((fc_conf->high_water > max_high_water) ||
3305                 (fc_conf->high_water < fc_conf->low_water)) {
3306                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3307                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3308                 return (-EINVAL);
3309         }
3310
3311         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3312         hw->fc.pause_time     = fc_conf->pause_time;
3313         hw->fc.high_water[0]  = fc_conf->high_water;
3314         hw->fc.low_water[0]   = fc_conf->low_water;
3315         hw->fc.send_xon       = fc_conf->send_xon;
3316         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3317
3318         err = ixgbe_fc_enable(hw);
3319
3320         /* Not negotiated is not an error case */
3321         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3322
3323                 /* check if we want to forward MAC frames - driver doesn't have native
3324                  * capability to do that, so we'll write the registers ourselves */
3325
3326                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3327
3328                 /* set or clear MFLCN.PMCF bit depending on configuration */
3329                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3330                         mflcn |= IXGBE_MFLCN_PMCF;
3331                 else
3332                         mflcn &= ~IXGBE_MFLCN_PMCF;
3333
3334                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3335                 IXGBE_WRITE_FLUSH(hw);
3336
3337                 return 0;
3338         }
3339
3340         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3341         return -EIO;
3342 }
3343
3344 /**
3345  *  ixgbe_pfc_enable_generic - Enable flow control
3346  *  @hw: pointer to hardware structure
3347  *  @tc_num: traffic class number
3348  *  Enable flow control according to the current settings.
3349  */
3350 static int
3351 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3352 {
3353         int ret_val = 0;
3354         uint32_t mflcn_reg, fccfg_reg;
3355         uint32_t reg;
3356         uint32_t fcrtl, fcrth;
3357         uint8_t i;
3358         uint8_t nb_rx_en;
3359
3360         /* Validate the water mark configuration */
3361         if (!hw->fc.pause_time) {
3362                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3363                 goto out;
3364         }
3365
3366         /* Low water mark of zero causes XOFF floods */
3367         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3368                  /* High/Low water can not be 0 */
3369                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3370                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3371                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3372                         goto out;
3373                 }
3374
3375                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3376                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3377                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3378                         goto out;
3379                 }
3380         }
3381         /* Negotiate the fc mode to use */
3382         ixgbe_fc_autoneg(hw);
3383
3384         /* Disable any previous flow control settings */
3385         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3386         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3387
3388         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3389         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3390
3391         switch (hw->fc.current_mode) {
3392         case ixgbe_fc_none:
3393                 /*
3394                  * If the count of enabled RX Priority Flow control >1,
3395                  * and the TX pause can not be disabled
3396                  */
3397                 nb_rx_en = 0;
3398                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3399                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3400                         if (reg & IXGBE_FCRTH_FCEN)
3401                                 nb_rx_en++;
3402                 }
3403                 if (nb_rx_en > 1)
3404                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3405                 break;
3406         case ixgbe_fc_rx_pause:
3407                 /*
3408                  * Rx Flow control is enabled and Tx Flow control is
3409                  * disabled by software override. Since there really
3410                  * isn't a way to advertise that we are capable of RX
3411                  * Pause ONLY, we will advertise that we support both
3412                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3413                  * disable the adapter's ability to send PAUSE frames.
3414                  */
3415                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3416                 /*
3417                  * If the count of enabled RX Priority Flow control >1,
3418                  * and the TX pause can not be disabled
3419                  */
3420                 nb_rx_en = 0;
3421                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3422                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3423                         if (reg & IXGBE_FCRTH_FCEN)
3424                                 nb_rx_en++;
3425                 }
3426                 if (nb_rx_en > 1)
3427                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3428                 break;
3429         case ixgbe_fc_tx_pause:
3430                 /*
3431                  * Tx Flow control is enabled, and Rx Flow control is
3432                  * disabled by software override.
3433                  */
3434                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3435                 break;
3436         case ixgbe_fc_full:
3437                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3438                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3439                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3440                 break;
3441         default:
3442                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3443                 ret_val = IXGBE_ERR_CONFIG;
3444                 goto out;
3445                 break;
3446         }
3447
3448         /* Set 802.3x based flow control settings. */
3449         mflcn_reg |= IXGBE_MFLCN_DPF;
3450         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3451         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3452
3453         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3454         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3455                 hw->fc.high_water[tc_num]) {
3456                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3457                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3458                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3459         } else {
3460                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3461                 /*
3462                  * In order to prevent Tx hangs when the internal Tx
3463                  * switch is enabled we must set the high water mark
3464                  * to the maximum FCRTH value.  This allows the Tx
3465                  * switch to function even under heavy Rx workloads.
3466                  */
3467                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3468         }
3469         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3470
3471         /* Configure pause time (2 TCs per register) */
3472         reg = hw->fc.pause_time * 0x00010001;
3473         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3474                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3475
3476         /* Configure flow control refresh threshold value */
3477         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3478
3479 out:
3480         return ret_val;
3481 }
3482
3483 static int
3484 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3485 {
3486         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3487         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3488
3489         if(hw->mac.type != ixgbe_mac_82598EB) {
3490                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3491         }
3492         return ret_val;
3493 }
3494
3495 static int
3496 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3497 {
3498         int err;
3499         uint32_t rx_buf_size;
3500         uint32_t max_high_water;
3501         uint8_t tc_num;
3502         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3503         struct ixgbe_hw *hw =
3504                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3505         struct ixgbe_dcb_config *dcb_config =
3506                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3507
3508         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3509                 ixgbe_fc_none,
3510                 ixgbe_fc_rx_pause,
3511                 ixgbe_fc_tx_pause,
3512                 ixgbe_fc_full
3513         };
3514
3515         PMD_INIT_FUNC_TRACE();
3516
3517         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3518         tc_num = map[pfc_conf->priority];
3519         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3520         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3521         /*
3522          * At least reserve one Ethernet frame for watermark
3523          * high_water/low_water in kilo bytes for ixgbe
3524          */
3525         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3526         if ((pfc_conf->fc.high_water > max_high_water) ||
3527             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3528                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3529                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3530                 return (-EINVAL);
3531         }
3532
3533         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3534         hw->fc.pause_time = pfc_conf->fc.pause_time;
3535         hw->fc.send_xon = pfc_conf->fc.send_xon;
3536         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3537         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3538
3539         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3540
3541         /* Not negotiated is not an error case */
3542         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3543                 return 0;
3544
3545         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3546         return -EIO;
3547 }
3548
3549 static int
3550 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3551                           struct rte_eth_rss_reta_entry64 *reta_conf,
3552                           uint16_t reta_size)
3553 {
3554         uint8_t i, j, mask;
3555         uint32_t reta, r;
3556         uint16_t idx, shift;
3557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3558         uint16_t sp_reta_size;
3559         uint32_t reta_reg;
3560
3561         PMD_INIT_FUNC_TRACE();
3562
3563         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3564                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3565                         "NIC.");
3566                 return -ENOTSUP;
3567         }
3568
3569         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3570         if (reta_size != sp_reta_size) {
3571                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3572                         "(%d) doesn't match the number hardware can supported "
3573                         "(%d)\n", reta_size, sp_reta_size);
3574                 return -EINVAL;
3575         }
3576
3577         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3578                 idx = i / RTE_RETA_GROUP_SIZE;
3579                 shift = i % RTE_RETA_GROUP_SIZE;
3580                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3581                                                 IXGBE_4_BIT_MASK);
3582                 if (!mask)
3583                         continue;
3584                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3585                 if (mask == IXGBE_4_BIT_MASK)
3586                         r = 0;
3587                 else
3588                         r = IXGBE_READ_REG(hw, reta_reg);
3589                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3590                         if (mask & (0x1 << j))
3591                                 reta |= reta_conf[idx].reta[shift + j] <<
3592                                                         (CHAR_BIT * j);
3593                         else
3594                                 reta |= r & (IXGBE_8_BIT_MASK <<
3595                                                 (CHAR_BIT * j));
3596                 }
3597                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3598         }
3599
3600         return 0;
3601 }
3602
3603 static int
3604 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3605                          struct rte_eth_rss_reta_entry64 *reta_conf,
3606                          uint16_t reta_size)
3607 {
3608         uint8_t i, j, mask;
3609         uint32_t reta;
3610         uint16_t idx, shift;
3611         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612         uint16_t sp_reta_size;
3613         uint32_t reta_reg;
3614
3615         PMD_INIT_FUNC_TRACE();
3616         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3617         if (reta_size != sp_reta_size) {
3618                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3619                         "(%d) doesn't match the number hardware can supported "
3620                         "(%d)\n", reta_size, sp_reta_size);
3621                 return -EINVAL;
3622         }
3623
3624         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3625                 idx = i / RTE_RETA_GROUP_SIZE;
3626                 shift = i % RTE_RETA_GROUP_SIZE;
3627                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3628                                                 IXGBE_4_BIT_MASK);
3629                 if (!mask)
3630                         continue;
3631
3632                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3633                 reta = IXGBE_READ_REG(hw, reta_reg);
3634                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3635                         if (mask & (0x1 << j))
3636                                 reta_conf[idx].reta[shift + j] =
3637                                         ((reta >> (CHAR_BIT * j)) &
3638                                                 IXGBE_8_BIT_MASK);
3639                 }
3640         }
3641
3642         return 0;
3643 }
3644
3645 static void
3646 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3647                                 uint32_t index, uint32_t pool)
3648 {
3649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3650         uint32_t enable_addr = 1;
3651
3652         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3653 }
3654
3655 static void
3656 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3657 {
3658         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3659
3660         ixgbe_clear_rar(hw, index);
3661 }
3662
3663 static void
3664 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3665 {
3666         ixgbe_remove_rar(dev, 0);
3667
3668         ixgbe_add_rar(dev, addr, 0, 0);
3669 }
3670
3671 static int
3672 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3673 {
3674         uint32_t hlreg0;
3675         uint32_t maxfrs;
3676         struct ixgbe_hw *hw;
3677         struct rte_eth_dev_info dev_info;
3678         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3679
3680         ixgbe_dev_info_get(dev, &dev_info);
3681
3682         /* check that mtu is within the allowed range */
3683         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3684                 return -EINVAL;
3685
3686         /* refuse mtu that requires the support of scattered packets when this
3687          * feature has not been enabled before. */
3688         if (!dev->data->scattered_rx &&
3689             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3690              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3691                 return -EINVAL;
3692
3693         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3694         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3695
3696         /* switch to jumbo mode if needed */
3697         if (frame_size > ETHER_MAX_LEN) {
3698                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3699                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3700         } else {
3701                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3702                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3703         }
3704         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3705
3706         /* update max frame size */
3707         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3708
3709         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3710         maxfrs &= 0x0000FFFF;
3711         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3712         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3713
3714         return 0;
3715 }
3716
3717 /*
3718  * Virtual Function operations
3719  */
3720 static void
3721 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3722 {
3723         PMD_INIT_FUNC_TRACE();
3724
3725         /* Clear interrupt mask to stop from interrupts being generated */
3726         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3727
3728         IXGBE_WRITE_FLUSH(hw);
3729 }
3730
3731 static void
3732 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3733 {
3734         PMD_INIT_FUNC_TRACE();
3735
3736         /* VF enable interrupt autoclean */
3737         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3738         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3739         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3740
3741         IXGBE_WRITE_FLUSH(hw);
3742 }
3743
3744 static int
3745 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3746 {
3747         struct rte_eth_conf* conf = &dev->data->dev_conf;
3748         struct ixgbe_adapter *adapter =
3749                         (struct ixgbe_adapter *)dev->data->dev_private;
3750
3751         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3752                      dev->data->port_id);
3753
3754         /*
3755          * VF has no ability to enable/disable HW CRC
3756          * Keep the persistent behavior the same as Host PF
3757          */
3758 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3759         if (!conf->rxmode.hw_strip_crc) {
3760                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3761                 conf->rxmode.hw_strip_crc = 1;
3762         }
3763 #else
3764         if (conf->rxmode.hw_strip_crc) {
3765                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3766                 conf->rxmode.hw_strip_crc = 0;
3767         }
3768 #endif
3769
3770         /*
3771          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3772          * allocation or vector Rx preconditions we will reset it.
3773          */
3774         adapter->rx_bulk_alloc_allowed = true;
3775         adapter->rx_vec_allowed = true;
3776
3777         return 0;
3778 }
3779
3780 static int
3781 ixgbevf_dev_start(struct rte_eth_dev *dev)
3782 {
3783         struct ixgbe_hw *hw =
3784                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785         uint32_t intr_vector = 0;
3786         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3787
3788         int err, mask = 0;
3789
3790         PMD_INIT_FUNC_TRACE();
3791
3792         hw->mac.ops.reset_hw(hw);
3793         hw->mac.get_link_status = true;
3794
3795         /* negotiate mailbox API version to use with the PF. */
3796         ixgbevf_negotiate_api(hw);
3797
3798         ixgbevf_dev_tx_init(dev);
3799
3800         /* This can fail when allocating mbufs for descriptor rings */
3801         err = ixgbevf_dev_rx_init(dev);
3802         if (err) {
3803                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3804                 ixgbe_dev_clear_queues(dev);
3805                 return err;
3806         }
3807
3808         /* Set vfta */
3809         ixgbevf_set_vfta_all(dev,1);
3810
3811         /* Set HW strip */
3812         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3813                 ETH_VLAN_EXTEND_MASK;
3814         ixgbevf_vlan_offload_set(dev, mask);
3815
3816         ixgbevf_dev_rxtx_start(dev);
3817
3818         /* check and configure queue intr-vector mapping */
3819         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3820                 intr_vector = dev->data->nb_rx_queues;
3821                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3822                         return -1;
3823         }
3824
3825         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3826                 intr_handle->intr_vec =
3827                         rte_zmalloc("intr_vec",
3828                                     dev->data->nb_rx_queues * sizeof(int), 0);
3829                 if (intr_handle->intr_vec == NULL) {
3830                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3831                                      " intr_vec\n", dev->data->nb_rx_queues);
3832                         return -ENOMEM;
3833                 }
3834         }
3835         ixgbevf_configure_msix(dev);
3836
3837         rte_intr_enable(intr_handle);
3838
3839         /* Re-enable interrupt for VF */
3840         ixgbevf_intr_enable(hw);
3841
3842         return 0;
3843 }
3844
3845 static void
3846 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3847 {
3848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3850
3851         PMD_INIT_FUNC_TRACE();
3852
3853         hw->adapter_stopped = 1;
3854         ixgbe_stop_adapter(hw);
3855
3856         /*
3857           * Clear what we set, but we still keep shadow_vfta to
3858           * restore after device starts
3859           */
3860         ixgbevf_set_vfta_all(dev,0);
3861
3862         /* Clear stored conf */
3863         dev->data->scattered_rx = 0;
3864
3865         ixgbe_dev_clear_queues(dev);
3866
3867         /* disable intr eventfd mapping */
3868         rte_intr_disable(intr_handle);
3869
3870         /* Clean datapath event and queue/vec mapping */
3871         rte_intr_efd_disable(intr_handle);
3872         if (intr_handle->intr_vec != NULL) {
3873                 rte_free(intr_handle->intr_vec);
3874                 intr_handle->intr_vec = NULL;
3875         }
3876 }
3877
3878 static void
3879 ixgbevf_dev_close(struct rte_eth_dev *dev)
3880 {
3881         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3882
3883         PMD_INIT_FUNC_TRACE();
3884
3885         ixgbe_reset_hw(hw);
3886
3887         ixgbevf_dev_stop(dev);
3888
3889         ixgbe_dev_free_queues(dev);
3890
3891         /* reprogram the RAR[0] in case user changed it. */
3892         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3893 }
3894
3895 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3896 {
3897         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3898         struct ixgbe_vfta * shadow_vfta =
3899                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3900         int i = 0, j = 0, vfta = 0, mask = 1;
3901
3902         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3903                 vfta = shadow_vfta->vfta[i];
3904                 if(vfta){
3905                         mask = 1;
3906                         for (j = 0; j < 32; j++){
3907                                 if(vfta & mask)
3908                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3909                                 mask<<=1;
3910                         }
3911                 }
3912         }
3913
3914 }
3915
3916 static int
3917 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3918 {
3919         struct ixgbe_hw *hw =
3920                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921         struct ixgbe_vfta * shadow_vfta =
3922                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3923         uint32_t vid_idx = 0;
3924         uint32_t vid_bit = 0;
3925         int ret = 0;
3926
3927         PMD_INIT_FUNC_TRACE();
3928
3929         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3930         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3931         if(ret){
3932                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3933                 return ret;
3934         }
3935         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3936         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3937
3938         /* Save what we set and retore it after device reset */
3939         if (on)
3940                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3941         else
3942                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3943
3944         return 0;
3945 }
3946
3947 static void
3948 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3949 {
3950         struct ixgbe_hw *hw =
3951                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3952         uint32_t ctrl;
3953
3954         PMD_INIT_FUNC_TRACE();
3955
3956         if(queue >= hw->mac.max_rx_queues)
3957                 return;
3958
3959         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3960         if(on)
3961                 ctrl |= IXGBE_RXDCTL_VME;
3962         else
3963                 ctrl &= ~IXGBE_RXDCTL_VME;
3964         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3965
3966         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3967 }
3968
3969 static void
3970 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3971 {
3972         struct ixgbe_hw *hw =
3973                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3974         uint16_t i;
3975         int on = 0;
3976
3977         /* VF function only support hw strip feature, others are not support */
3978         if(mask & ETH_VLAN_STRIP_MASK){
3979                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3980
3981                 for(i=0; i < hw->mac.max_rx_queues; i++)
3982                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3983         }
3984 }
3985
3986 static int
3987 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3988 {
3989         uint32_t reg_val;
3990
3991         /* we only need to do this if VMDq is enabled */
3992         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3993         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3994                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3995                 return (-1);
3996         }
3997
3998         return 0;
3999 }
4000
4001 static uint32_t
4002 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4003 {
4004         uint32_t vector = 0;
4005         switch (hw->mac.mc_filter_type) {
4006         case 0:   /* use bits [47:36] of the address */
4007                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4008                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4009                 break;
4010         case 1:   /* use bits [46:35] of the address */
4011                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4012                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4013                 break;
4014         case 2:   /* use bits [45:34] of the address */
4015                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4016                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4017                 break;
4018         case 3:   /* use bits [43:32] of the address */
4019                 vector = ((uc_addr->addr_bytes[4]) |
4020                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4021                 break;
4022         default:  /* Invalid mc_filter_type */
4023                 break;
4024         }
4025
4026         /* vector can only be 12-bits or boundary will be exceeded */
4027         vector &= 0xFFF;
4028         return vector;
4029 }
4030
4031 static int
4032 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4033                                uint8_t on)
4034 {
4035         uint32_t vector;
4036         uint32_t uta_idx;
4037         uint32_t reg_val;
4038         uint32_t uta_shift;
4039         uint32_t rc;
4040         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4041         const uint32_t ixgbe_uta_bit_shift = 5;
4042         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4043         const uint32_t bit1 = 0x1;
4044
4045         struct ixgbe_hw *hw =
4046                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4047         struct ixgbe_uta_info *uta_info =
4048                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4049
4050         /* The UTA table only exists on 82599 hardware and newer */
4051         if (hw->mac.type < ixgbe_mac_82599EB)
4052                 return (-ENOTSUP);
4053
4054         vector = ixgbe_uta_vector(hw,mac_addr);
4055         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4056         uta_shift = vector & ixgbe_uta_bit_mask;
4057
4058         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4059         if(rc == on)
4060                 return 0;
4061
4062         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4063         if (on) {
4064                 uta_info->uta_in_use++;
4065                 reg_val |= (bit1 << uta_shift);
4066                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4067         } else {
4068                 uta_info->uta_in_use--;
4069                 reg_val &= ~(bit1 << uta_shift);
4070                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4071         }
4072
4073         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4074
4075         if (uta_info->uta_in_use > 0)
4076                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4077                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4078         else
4079                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4080
4081         return 0;
4082 }
4083
4084 static int
4085 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4086 {
4087         int i;
4088         struct ixgbe_hw *hw =
4089                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4090         struct ixgbe_uta_info *uta_info =
4091                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4092
4093         /* The UTA table only exists on 82599 hardware and newer */
4094         if (hw->mac.type < ixgbe_mac_82599EB)
4095                 return (-ENOTSUP);
4096
4097         if(on) {
4098                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4099                         uta_info->uta_shadow[i] = ~0;
4100                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4101                 }
4102         } else {
4103                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4104                         uta_info->uta_shadow[i] = 0;
4105                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4106                 }
4107         }
4108         return 0;
4109
4110 }
4111
4112 uint32_t
4113 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4114 {
4115         uint32_t new_val = orig_val;
4116
4117         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4118                 new_val |= IXGBE_VMOLR_AUPE;
4119         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4120                 new_val |= IXGBE_VMOLR_ROMPE;
4121         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4122                 new_val |= IXGBE_VMOLR_ROPE;
4123         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4124                 new_val |= IXGBE_VMOLR_BAM;
4125         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4126                 new_val |= IXGBE_VMOLR_MPE;
4127
4128         return new_val;
4129 }
4130
4131 static int
4132 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4133                                uint16_t rx_mask, uint8_t on)
4134 {
4135         int val = 0;
4136
4137         struct ixgbe_hw *hw =
4138                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4139         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4140
4141         if (hw->mac.type == ixgbe_mac_82598EB) {
4142                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4143                              " on 82599 hardware and newer");
4144                 return (-ENOTSUP);
4145         }
4146         if (ixgbe_vmdq_mode_check(hw) < 0)
4147                 return (-ENOTSUP);
4148
4149         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4150
4151         if (on)
4152                 vmolr |= val;
4153         else
4154                 vmolr &= ~val;
4155
4156         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4157
4158         return 0;
4159 }
4160
4161 static int
4162 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4163 {
4164         uint32_t reg,addr;
4165         uint32_t val;
4166         const uint8_t bit1 = 0x1;
4167
4168         struct ixgbe_hw *hw =
4169                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4170
4171         if (ixgbe_vmdq_mode_check(hw) < 0)
4172                 return (-ENOTSUP);
4173
4174         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4175         reg = IXGBE_READ_REG(hw, addr);
4176         val = bit1 << pool;
4177
4178         if (on)
4179                 reg |= val;
4180         else
4181                 reg &= ~val;
4182
4183         IXGBE_WRITE_REG(hw, addr,reg);
4184
4185         return 0;
4186 }
4187
4188 static int
4189 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4190 {
4191         uint32_t reg,addr;
4192         uint32_t val;
4193         const uint8_t bit1 = 0x1;
4194
4195         struct ixgbe_hw *hw =
4196                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4197
4198         if (ixgbe_vmdq_mode_check(hw) < 0)
4199                 return (-ENOTSUP);
4200
4201         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4202         reg = IXGBE_READ_REG(hw, addr);
4203         val = bit1 << pool;
4204
4205         if (on)
4206                 reg |= val;
4207         else
4208                 reg &= ~val;
4209
4210         IXGBE_WRITE_REG(hw, addr,reg);
4211
4212         return 0;
4213 }
4214
4215 static int
4216 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4217                         uint64_t pool_mask, uint8_t vlan_on)
4218 {
4219         int ret = 0;
4220         uint16_t pool_idx;
4221         struct ixgbe_hw *hw =
4222                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4223
4224         if (ixgbe_vmdq_mode_check(hw) < 0)
4225                 return (-ENOTSUP);
4226         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4227                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4228                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4229                         if (ret < 0)
4230                                 return ret;
4231         }
4232
4233         return ret;
4234 }
4235
4236 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4237 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4238 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4239 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4240 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4241         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4242         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4243
4244 static int
4245 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4246                         struct rte_eth_mirror_conf *mirror_conf,
4247                         uint8_t rule_id, uint8_t on)
4248 {
4249         uint32_t mr_ctl,vlvf;
4250         uint32_t mp_lsb = 0;
4251         uint32_t mv_msb = 0;
4252         uint32_t mv_lsb = 0;
4253         uint32_t mp_msb = 0;
4254         uint8_t i = 0;
4255         int reg_index = 0;
4256         uint64_t vlan_mask = 0;
4257
4258         const uint8_t pool_mask_offset = 32;
4259         const uint8_t vlan_mask_offset = 32;
4260         const uint8_t dst_pool_offset = 8;
4261         const uint8_t rule_mr_offset  = 4;
4262         const uint8_t mirror_rule_mask= 0x0F;
4263
4264         struct ixgbe_mirror_info *mr_info =
4265                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4266         struct ixgbe_hw *hw =
4267                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4268         uint8_t mirror_type = 0;
4269
4270         if (ixgbe_vmdq_mode_check(hw) < 0)
4271                 return -ENOTSUP;
4272
4273         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4274                 return -EINVAL;
4275
4276         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4277                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4278                         mirror_conf->rule_type);
4279                 return -EINVAL;
4280         }
4281
4282         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4283                 mirror_type |= IXGBE_MRCTL_VLME;
4284                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4285                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4286                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4287                                 /* search vlan id related pool vlan filter index */
4288                                 reg_index = ixgbe_find_vlvf_slot(hw,
4289                                                 mirror_conf->vlan.vlan_id[i]);
4290                                 if(reg_index < 0)
4291                                         return -EINVAL;
4292                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4293                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4294                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4295                                       mirror_conf->vlan.vlan_id[i]))
4296                                         vlan_mask |= (1ULL << reg_index);
4297                                 else
4298                                         return -EINVAL;
4299                         }
4300                 }
4301
4302                 if (on) {
4303                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4304                         mv_msb = vlan_mask >> vlan_mask_offset;
4305
4306                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4307                                                 mirror_conf->vlan.vlan_mask;
4308                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4309                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4310                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4311                                                 mirror_conf->vlan.vlan_id[i];
4312                         }
4313                 } else {
4314                         mv_lsb = 0;
4315                         mv_msb = 0;
4316                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4317                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4318                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4319                 }
4320         }
4321
4322         /*
4323          * if enable pool mirror, write related pool mask register,if disable
4324          * pool mirror, clear PFMRVM register
4325          */
4326         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4327                 mirror_type |= IXGBE_MRCTL_VPME;
4328                 if (on) {
4329                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4330                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4331                         mr_info->mr_conf[rule_id].pool_mask =
4332                                         mirror_conf->pool_mask;
4333
4334                 } else {
4335                         mp_lsb = 0;
4336                         mp_msb = 0;
4337                         mr_info->mr_conf[rule_id].pool_mask = 0;
4338                 }
4339         }
4340         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4341                 mirror_type |= IXGBE_MRCTL_UPME;
4342         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4343                 mirror_type |= IXGBE_MRCTL_DPME;
4344
4345         /* read  mirror control register and recalculate it */
4346         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4347
4348         if (on) {
4349                 mr_ctl |= mirror_type;
4350                 mr_ctl &= mirror_rule_mask;
4351                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4352         } else
4353                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4354
4355         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4356         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4357
4358         /* write mirrror control  register */
4359         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4360
4361         /* write pool mirrror control  register */
4362         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4363                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4364                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4365                                 mp_msb);
4366         }
4367         /* write VLAN mirrror control  register */
4368         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4369                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4370                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4371                                 mv_msb);
4372         }
4373
4374         return 0;
4375 }
4376
4377 static int
4378 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4379 {
4380         int mr_ctl = 0;
4381         uint32_t lsb_val = 0;
4382         uint32_t msb_val = 0;
4383         const uint8_t rule_mr_offset = 4;
4384
4385         struct ixgbe_hw *hw =
4386                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4387         struct ixgbe_mirror_info *mr_info =
4388                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4389
4390         if (ixgbe_vmdq_mode_check(hw) < 0)
4391                 return (-ENOTSUP);
4392
4393         memset(&mr_info->mr_conf[rule_id], 0,
4394                 sizeof(struct rte_eth_mirror_conf));
4395
4396         /* clear PFVMCTL register */
4397         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4398
4399         /* clear pool mask register */
4400         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4401         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4402
4403         /* clear vlan mask register */
4404         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4405         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4406
4407         return 0;
4408 }
4409
4410 static int
4411 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4412 {
4413         uint32_t mask;
4414         struct ixgbe_hw *hw =
4415                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4416
4417         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4418         mask |= (1 << IXGBE_MISC_VEC_ID);
4419         RTE_SET_USED(queue_id);
4420         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4421
4422         rte_intr_enable(&dev->pci_dev->intr_handle);
4423
4424         return 0;
4425 }
4426
4427 static int
4428 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4429 {
4430         uint32_t mask;
4431         struct ixgbe_hw *hw =
4432                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4433
4434         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4435         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4436         RTE_SET_USED(queue_id);
4437         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4438
4439         return 0;
4440 }
4441
4442 static int
4443 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4444 {
4445         uint32_t mask;
4446         struct ixgbe_hw *hw =
4447                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4448         struct ixgbe_interrupt *intr =
4449                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4450
4451         if (queue_id < 16) {
4452                 ixgbe_disable_intr(hw);
4453                 intr->mask |= (1 << queue_id);
4454                 ixgbe_enable_intr(dev);
4455         } else if (queue_id < 32) {
4456                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4457                 mask &= (1 << queue_id);
4458                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4459         } else if (queue_id < 64) {
4460                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4461                 mask &= (1 << (queue_id - 32));
4462                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4463         }
4464         rte_intr_enable(&dev->pci_dev->intr_handle);
4465
4466         return 0;
4467 }
4468
4469 static int
4470 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4471 {
4472         uint32_t mask;
4473         struct ixgbe_hw *hw =
4474                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475         struct ixgbe_interrupt *intr =
4476                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4477
4478         if (queue_id < 16) {
4479                 ixgbe_disable_intr(hw);
4480                 intr->mask &= ~(1 << queue_id);
4481                 ixgbe_enable_intr(dev);
4482         } else if (queue_id < 32) {
4483                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4484                 mask &= ~(1 << queue_id);
4485                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4486         } else if (queue_id < 64) {
4487                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4488                 mask &= ~(1 << (queue_id - 32));
4489                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4490         }
4491
4492         return 0;
4493 }
4494
4495 static void
4496 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4497                      uint8_t queue, uint8_t msix_vector)
4498 {
4499         uint32_t tmp, idx;
4500
4501         if (direction == -1) {
4502                 /* other causes */
4503                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4504                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4505                 tmp &= ~0xFF;
4506                 tmp |= msix_vector;
4507                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4508         } else {
4509                 /* rx or tx cause */
4510                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4511                 idx = ((16 * (queue & 1)) + (8 * direction));
4512                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4513                 tmp &= ~(0xFF << idx);
4514                 tmp |= (msix_vector << idx);
4515                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4516         }
4517 }
4518
4519 /**
4520  * set the IVAR registers, mapping interrupt causes to vectors
4521  * @param hw
4522  *  pointer to ixgbe_hw struct
4523  * @direction
4524  *  0 for Rx, 1 for Tx, -1 for other causes
4525  * @queue
4526  *  queue to map the corresponding interrupt to
4527  * @msix_vector
4528  *  the vector to map to the corresponding queue
4529  */
4530 static void
4531 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4532                    uint8_t queue, uint8_t msix_vector)
4533 {
4534         uint32_t tmp, idx;
4535
4536         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4537         if (hw->mac.type == ixgbe_mac_82598EB) {
4538                 if (direction == -1)
4539                         direction = 0;
4540                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4541                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4542                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4543                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4544                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4545         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4546                         (hw->mac.type == ixgbe_mac_X540)) {
4547                 if (direction == -1) {
4548                         /* other causes */
4549                         idx = ((queue & 1) * 8);
4550                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4551                         tmp &= ~(0xFF << idx);
4552                         tmp |= (msix_vector << idx);
4553                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4554                 } else {
4555                         /* rx or tx causes */
4556                         idx = ((16 * (queue & 1)) + (8 * direction));
4557                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4558                         tmp &= ~(0xFF << idx);
4559                         tmp |= (msix_vector << idx);
4560                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4561                 }
4562         }
4563 }
4564
4565 static void
4566 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4567 {
4568         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4569         struct ixgbe_hw *hw =
4570                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4571         uint32_t q_idx;
4572         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4573
4574         /* won't configure msix register if no mapping is done
4575          * between intr vector and event fd.
4576          */
4577         if (!rte_intr_dp_is_en(intr_handle))
4578                 return;
4579
4580         /* Configure all RX queues of VF */
4581         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4582                 /* Force all queue use vector 0,
4583                  * as IXGBE_VF_MAXMSIVECOTR = 1
4584                  */
4585                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4586                 intr_handle->intr_vec[q_idx] = vector_idx;
4587         }
4588
4589         /* Configure VF other cause ivar */
4590         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4591 }
4592
4593 /**
4594  * Sets up the hardware to properly generate MSI-X interrupts
4595  * @hw
4596  *  board private structure
4597  */
4598 static void
4599 ixgbe_configure_msix(struct rte_eth_dev *dev)
4600 {
4601         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4602         struct ixgbe_hw *hw =
4603                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4604         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4605         uint32_t vec = IXGBE_MISC_VEC_ID;
4606         uint32_t mask;
4607         uint32_t gpie;
4608
4609         /* won't configure msix register if no mapping is done
4610          * between intr vector and event fd
4611          */
4612         if (!rte_intr_dp_is_en(intr_handle))
4613                 return;
4614
4615         if (rte_intr_allow_others(intr_handle))
4616                 vec = base = IXGBE_RX_VEC_START;
4617
4618         /* setup GPIE for MSI-x mode */
4619         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4620         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4621                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4622         /* auto clearing and auto setting corresponding bits in EIMS
4623          * when MSI-X interrupt is triggered
4624          */
4625         if (hw->mac.type == ixgbe_mac_82598EB) {
4626                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4627         } else {
4628                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4629                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4630         }
4631         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4632
4633         /* Populate the IVAR table and set the ITR values to the
4634          * corresponding register.
4635          */
4636         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4637              queue_id++) {
4638                 /* by default, 1:1 mapping */
4639                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4640                 intr_handle->intr_vec[queue_id] = vec;
4641                 if (vec < base + intr_handle->nb_efd - 1)
4642                         vec++;
4643         }
4644
4645         switch (hw->mac.type) {
4646         case ixgbe_mac_82598EB:
4647                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4648                                    IXGBE_MISC_VEC_ID);
4649                 break;
4650         case ixgbe_mac_82599EB:
4651         case ixgbe_mac_X540:
4652                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4653                 break;
4654         default:
4655                 break;
4656         }
4657         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4658                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4659
4660         /* set up to autoclear timer, and the vectors */
4661         mask = IXGBE_EIMS_ENABLE_MASK;
4662         mask &= ~(IXGBE_EIMS_OTHER |
4663                   IXGBE_EIMS_MAILBOX |
4664                   IXGBE_EIMS_LSC);
4665
4666         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4667 }
4668
4669 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4670         uint16_t queue_idx, uint16_t tx_rate)
4671 {
4672         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4673         uint32_t rf_dec, rf_int;
4674         uint32_t bcnrc_val;
4675         uint16_t link_speed = dev->data->dev_link.link_speed;
4676
4677         if (queue_idx >= hw->mac.max_tx_queues)
4678                 return -EINVAL;
4679
4680         if (tx_rate != 0) {
4681                 /* Calculate the rate factor values to set */
4682                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4683                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4684                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4685
4686                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4687                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4688                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4689                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4690         } else {
4691                 bcnrc_val = 0;
4692         }
4693
4694         /*
4695          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4696          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4697          * set as 0x4.
4698          */
4699         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4700                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4701                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4702                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4703                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4704         else
4705                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4706                         IXGBE_MMW_SIZE_DEFAULT);
4707
4708         /* Set RTTBCNRC of queue X */
4709         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4710         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4711         IXGBE_WRITE_FLUSH(hw);
4712
4713         return 0;
4714 }
4715
4716 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4717         uint16_t tx_rate, uint64_t q_msk)
4718 {
4719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4720         struct ixgbe_vf_info *vfinfo =
4721                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4722         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4723         uint32_t queue_stride =
4724                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4725         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4726         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4727         uint16_t total_rate = 0;
4728
4729         if (queue_end >= hw->mac.max_tx_queues)
4730                 return -EINVAL;
4731
4732         if (vfinfo != NULL) {
4733                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4734                         if (vf_idx == vf)
4735                                 continue;
4736                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4737                                 idx++)
4738                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4739                 }
4740         } else
4741                 return -EINVAL;
4742
4743         /* Store tx_rate for this vf. */
4744         for (idx = 0; idx < nb_q_per_pool; idx++) {
4745                 if (((uint64_t)0x1 << idx) & q_msk) {
4746                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4747                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4748                         total_rate += tx_rate;
4749                 }
4750         }
4751
4752         if (total_rate > dev->data->dev_link.link_speed) {
4753                 /*
4754                  * Reset stored TX rate of the VF if it causes exceed
4755                  * link speed.
4756                  */
4757                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4758                 return -EINVAL;
4759         }
4760
4761         /* Set RTTBCNRC of each queue/pool for vf X  */
4762         for (; queue_idx <= queue_end; queue_idx++) {
4763                 if (0x1 & q_msk)
4764                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4765                 q_msk = q_msk >> 1;
4766         }
4767
4768         return 0;
4769 }
4770
4771 static void
4772 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4773                      __attribute__((unused)) uint32_t index,
4774                      __attribute__((unused)) uint32_t pool)
4775 {
4776         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4777         int diag;
4778
4779         /*
4780          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4781          * operation. Trap this case to avoid exhausting the [very limited]
4782          * set of PF resources used to store VF MAC addresses.
4783          */
4784         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4785                 return;
4786         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4787         if (diag == 0)
4788                 return;
4789         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4790 }
4791
4792 static void
4793 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4794 {
4795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4796         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4797         struct ether_addr *mac_addr;
4798         uint32_t i;
4799         int diag;
4800
4801         /*
4802          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4803          * not support the deletion of a given MAC address.
4804          * Instead, it imposes to delete all MAC addresses, then to add again
4805          * all MAC addresses with the exception of the one to be deleted.
4806          */
4807         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4808
4809         /*
4810          * Add again all MAC addresses, with the exception of the deleted one
4811          * and of the permanent MAC address.
4812          */
4813         for (i = 0, mac_addr = dev->data->mac_addrs;
4814              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4815                 /* Skip the deleted MAC address */
4816                 if (i == index)
4817                         continue;
4818                 /* Skip NULL MAC addresses */
4819                 if (is_zero_ether_addr(mac_addr))
4820                         continue;
4821                 /* Skip the permanent MAC address */
4822                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4823                         continue;
4824                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4825                 if (diag != 0)
4826                         PMD_DRV_LOG(ERR,
4827                                     "Adding again MAC address "
4828                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4829                                     "diag=%d",
4830                                     mac_addr->addr_bytes[0],
4831                                     mac_addr->addr_bytes[1],
4832                                     mac_addr->addr_bytes[2],
4833                                     mac_addr->addr_bytes[3],
4834                                     mac_addr->addr_bytes[4],
4835                                     mac_addr->addr_bytes[5],
4836                                     diag);
4837         }
4838 }
4839
4840 static void
4841 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4842 {
4843         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4844
4845         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4846 }
4847
4848 #define MAC_TYPE_FILTER_SUP(type)    do {\
4849         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4850                 (type) != ixgbe_mac_X550)\
4851                 return -ENOTSUP;\
4852 } while (0)
4853
4854 static int
4855 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4856                         struct rte_eth_syn_filter *filter,
4857                         bool add)
4858 {
4859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4860         uint32_t synqf;
4861
4862         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4863                 return -EINVAL;
4864
4865         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4866
4867         if (add) {
4868                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4869                         return -EINVAL;
4870                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4871                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4872
4873                 if (filter->hig_pri)
4874                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4875                 else
4876                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4877         } else {
4878                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4879                         return -ENOENT;
4880                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4881         }
4882         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4883         IXGBE_WRITE_FLUSH(hw);
4884         return 0;
4885 }
4886
4887 static int
4888 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4889                         struct rte_eth_syn_filter *filter)
4890 {
4891         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4892         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4893
4894         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4895                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4896                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4897                 return 0;
4898         }
4899         return -ENOENT;
4900 }
4901
4902 static int
4903 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4904                         enum rte_filter_op filter_op,
4905                         void *arg)
4906 {
4907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4908         int ret;
4909
4910         MAC_TYPE_FILTER_SUP(hw->mac.type);
4911
4912         if (filter_op == RTE_ETH_FILTER_NOP)
4913                 return 0;
4914
4915         if (arg == NULL) {
4916                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4917                             filter_op);
4918                 return -EINVAL;
4919         }
4920
4921         switch (filter_op) {
4922         case RTE_ETH_FILTER_ADD:
4923                 ret = ixgbe_syn_filter_set(dev,
4924                                 (struct rte_eth_syn_filter *)arg,
4925                                 TRUE);
4926                 break;
4927         case RTE_ETH_FILTER_DELETE:
4928                 ret = ixgbe_syn_filter_set(dev,
4929                                 (struct rte_eth_syn_filter *)arg,
4930                                 FALSE);
4931                 break;
4932         case RTE_ETH_FILTER_GET:
4933                 ret = ixgbe_syn_filter_get(dev,
4934                                 (struct rte_eth_syn_filter *)arg);
4935                 break;
4936         default:
4937                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4938                 ret = -EINVAL;
4939                 break;
4940         }
4941
4942         return ret;
4943 }
4944
4945
4946 static inline enum ixgbe_5tuple_protocol
4947 convert_protocol_type(uint8_t protocol_value)
4948 {
4949         if (protocol_value == IPPROTO_TCP)
4950                 return IXGBE_FILTER_PROTOCOL_TCP;
4951         else if (protocol_value == IPPROTO_UDP)
4952                 return IXGBE_FILTER_PROTOCOL_UDP;
4953         else if (protocol_value == IPPROTO_SCTP)
4954                 return IXGBE_FILTER_PROTOCOL_SCTP;
4955         else
4956                 return IXGBE_FILTER_PROTOCOL_NONE;
4957 }
4958
4959 /*
4960  * add a 5tuple filter
4961  *
4962  * @param
4963  * dev: Pointer to struct rte_eth_dev.
4964  * index: the index the filter allocates.
4965  * filter: ponter to the filter that will be added.
4966  * rx_queue: the queue id the filter assigned to.
4967  *
4968  * @return
4969  *    - On success, zero.
4970  *    - On failure, a negative value.
4971  */
4972 static int
4973 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4974                         struct ixgbe_5tuple_filter *filter)
4975 {
4976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4977         struct ixgbe_filter_info *filter_info =
4978                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4979         int i, idx, shift;
4980         uint32_t ftqf, sdpqf;
4981         uint32_t l34timir = 0;
4982         uint8_t mask = 0xff;
4983
4984         /*
4985          * look for an unused 5tuple filter index,
4986          * and insert the filter to list.
4987          */
4988         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4989                 idx = i / (sizeof(uint32_t) * NBBY);
4990                 shift = i % (sizeof(uint32_t) * NBBY);
4991                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
4992                         filter_info->fivetuple_mask[idx] |= 1 << shift;
4993                         filter->index = i;
4994                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4995                                           filter,
4996                                           entries);
4997                         break;
4998                 }
4999         }
5000         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5001                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5002                 return -ENOSYS;
5003         }
5004
5005         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5006                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5007         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5008
5009         ftqf = (uint32_t)(filter->filter_info.proto &
5010                 IXGBE_FTQF_PROTOCOL_MASK);
5011         ftqf |= (uint32_t)((filter->filter_info.priority &
5012                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5013         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5014                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5015         if (filter->filter_info.dst_ip_mask == 0)
5016                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5017         if (filter->filter_info.src_port_mask == 0)
5018                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5019         if (filter->filter_info.dst_port_mask == 0)
5020                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5021         if (filter->filter_info.proto_mask == 0)
5022                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5023         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5024         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5025         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5026
5027         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5028         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5029         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5030         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5031
5032         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5033         l34timir |= (uint32_t)(filter->queue <<
5034                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5035         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5036         return 0;
5037 }
5038
5039 /*
5040  * remove a 5tuple filter
5041  *
5042  * @param
5043  * dev: Pointer to struct rte_eth_dev.
5044  * filter: the pointer of the filter will be removed.
5045  */
5046 static void
5047 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5048                         struct ixgbe_5tuple_filter *filter)
5049 {
5050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051         struct ixgbe_filter_info *filter_info =
5052                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5053         uint16_t index = filter->index;
5054
5055         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5056                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5057         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5058         rte_free(filter);
5059
5060         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5061         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5062         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5063         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5064         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5065 }
5066
5067 static int
5068 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5069 {
5070         struct ixgbe_hw *hw;
5071         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5072
5073         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5074
5075         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5076                 return -EINVAL;
5077
5078         /* refuse mtu that requires the support of scattered packets when this
5079          * feature has not been enabled before. */
5080         if (!dev->data->scattered_rx &&
5081             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5082              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5083                 return -EINVAL;
5084
5085         /*
5086          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5087          * request of the version 2.0 of the mailbox API.
5088          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5089          * of the mailbox API.
5090          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5091          * prior to 3.11.33 which contains the following change:
5092          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5093          */
5094         ixgbevf_rlpml_set_vf(hw, max_frame);
5095
5096         /* update max frame size */
5097         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5098         return 0;
5099 }
5100
5101 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5102         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5103                 return -ENOTSUP;\
5104 } while (0)
5105
5106 static inline struct ixgbe_5tuple_filter *
5107 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5108                         struct ixgbe_5tuple_filter_info *key)
5109 {
5110         struct ixgbe_5tuple_filter *it;
5111
5112         TAILQ_FOREACH(it, filter_list, entries) {
5113                 if (memcmp(key, &it->filter_info,
5114                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5115                         return it;
5116                 }
5117         }
5118         return NULL;
5119 }
5120
5121 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5122 static inline int
5123 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5124                         struct ixgbe_5tuple_filter_info *filter_info)
5125 {
5126         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5127                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5128                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5129                 return -EINVAL;
5130
5131         switch (filter->dst_ip_mask) {
5132         case UINT32_MAX:
5133                 filter_info->dst_ip_mask = 0;
5134                 filter_info->dst_ip = filter->dst_ip;
5135                 break;
5136         case 0:
5137                 filter_info->dst_ip_mask = 1;
5138                 break;
5139         default:
5140                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5141                 return -EINVAL;
5142         }
5143
5144         switch (filter->src_ip_mask) {
5145         case UINT32_MAX:
5146                 filter_info->src_ip_mask = 0;
5147                 filter_info->src_ip = filter->src_ip;
5148                 break;
5149         case 0:
5150                 filter_info->src_ip_mask = 1;
5151                 break;
5152         default:
5153                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5154                 return -EINVAL;
5155         }
5156
5157         switch (filter->dst_port_mask) {
5158         case UINT16_MAX:
5159                 filter_info->dst_port_mask = 0;
5160                 filter_info->dst_port = filter->dst_port;
5161                 break;
5162         case 0:
5163                 filter_info->dst_port_mask = 1;
5164                 break;
5165         default:
5166                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5167                 return -EINVAL;
5168         }
5169
5170         switch (filter->src_port_mask) {
5171         case UINT16_MAX:
5172                 filter_info->src_port_mask = 0;
5173                 filter_info->src_port = filter->src_port;
5174                 break;
5175         case 0:
5176                 filter_info->src_port_mask = 1;
5177                 break;
5178         default:
5179                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5180                 return -EINVAL;
5181         }
5182
5183         switch (filter->proto_mask) {
5184         case UINT8_MAX:
5185                 filter_info->proto_mask = 0;
5186                 filter_info->proto =
5187                         convert_protocol_type(filter->proto);
5188                 break;
5189         case 0:
5190                 filter_info->proto_mask = 1;
5191                 break;
5192         default:
5193                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5194                 return -EINVAL;
5195         }
5196
5197         filter_info->priority = (uint8_t)filter->priority;
5198         return 0;
5199 }
5200
5201 /*
5202  * add or delete a ntuple filter
5203  *
5204  * @param
5205  * dev: Pointer to struct rte_eth_dev.
5206  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5207  * add: if true, add filter, if false, remove filter
5208  *
5209  * @return
5210  *    - On success, zero.
5211  *    - On failure, a negative value.
5212  */
5213 static int
5214 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5215                         struct rte_eth_ntuple_filter *ntuple_filter,
5216                         bool add)
5217 {
5218         struct ixgbe_filter_info *filter_info =
5219                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5220         struct ixgbe_5tuple_filter_info filter_5tuple;
5221         struct ixgbe_5tuple_filter *filter;
5222         int ret;
5223
5224         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5225                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5226                 return -EINVAL;
5227         }
5228
5229         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5230         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5231         if (ret < 0)
5232                 return ret;
5233
5234         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5235                                          &filter_5tuple);
5236         if (filter != NULL && add) {
5237                 PMD_DRV_LOG(ERR, "filter exists.");
5238                 return -EEXIST;
5239         }
5240         if (filter == NULL && !add) {
5241                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5242                 return -ENOENT;
5243         }
5244
5245         if (add) {
5246                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5247                                 sizeof(struct ixgbe_5tuple_filter), 0);
5248                 if (filter == NULL)
5249                         return -ENOMEM;
5250                 (void)rte_memcpy(&filter->filter_info,
5251                                  &filter_5tuple,
5252                                  sizeof(struct ixgbe_5tuple_filter_info));
5253                 filter->queue = ntuple_filter->queue;
5254                 ret = ixgbe_add_5tuple_filter(dev, filter);
5255                 if (ret < 0) {
5256                         rte_free(filter);
5257                         return ret;
5258                 }
5259         } else
5260                 ixgbe_remove_5tuple_filter(dev, filter);
5261
5262         return 0;
5263 }
5264
5265 /*
5266  * get a ntuple filter
5267  *
5268  * @param
5269  * dev: Pointer to struct rte_eth_dev.
5270  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5271  *
5272  * @return
5273  *    - On success, zero.
5274  *    - On failure, a negative value.
5275  */
5276 static int
5277 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5278                         struct rte_eth_ntuple_filter *ntuple_filter)
5279 {
5280         struct ixgbe_filter_info *filter_info =
5281                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5282         struct ixgbe_5tuple_filter_info filter_5tuple;
5283         struct ixgbe_5tuple_filter *filter;
5284         int ret;
5285
5286         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5287                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5288                 return -EINVAL;
5289         }
5290
5291         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5292         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5293         if (ret < 0)
5294                 return ret;
5295
5296         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5297                                          &filter_5tuple);
5298         if (filter == NULL) {
5299                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5300                 return -ENOENT;
5301         }
5302         ntuple_filter->queue = filter->queue;
5303         return 0;
5304 }
5305
5306 /*
5307  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5308  * @dev: pointer to rte_eth_dev structure
5309  * @filter_op:operation will be taken.
5310  * @arg: a pointer to specific structure corresponding to the filter_op
5311  *
5312  * @return
5313  *    - On success, zero.
5314  *    - On failure, a negative value.
5315  */
5316 static int
5317 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5318                                 enum rte_filter_op filter_op,
5319                                 void *arg)
5320 {
5321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5322         int ret;
5323
5324         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5325
5326         if (filter_op == RTE_ETH_FILTER_NOP)
5327                 return 0;
5328
5329         if (arg == NULL) {
5330                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5331                             filter_op);
5332                 return -EINVAL;
5333         }
5334
5335         switch (filter_op) {
5336         case RTE_ETH_FILTER_ADD:
5337                 ret = ixgbe_add_del_ntuple_filter(dev,
5338                         (struct rte_eth_ntuple_filter *)arg,
5339                         TRUE);
5340                 break;
5341         case RTE_ETH_FILTER_DELETE:
5342                 ret = ixgbe_add_del_ntuple_filter(dev,
5343                         (struct rte_eth_ntuple_filter *)arg,
5344                         FALSE);
5345                 break;
5346         case RTE_ETH_FILTER_GET:
5347                 ret = ixgbe_get_ntuple_filter(dev,
5348                         (struct rte_eth_ntuple_filter *)arg);
5349                 break;
5350         default:
5351                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5352                 ret = -EINVAL;
5353                 break;
5354         }
5355         return ret;
5356 }
5357
5358 static inline int
5359 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5360                         uint16_t ethertype)
5361 {
5362         int i;
5363
5364         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5365                 if (filter_info->ethertype_filters[i] == ethertype &&
5366                     (filter_info->ethertype_mask & (1 << i)))
5367                         return i;
5368         }
5369         return -1;
5370 }
5371
5372 static inline int
5373 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5374                         uint16_t ethertype)
5375 {
5376         int i;
5377
5378         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5379                 if (!(filter_info->ethertype_mask & (1 << i))) {
5380                         filter_info->ethertype_mask |= 1 << i;
5381                         filter_info->ethertype_filters[i] = ethertype;
5382                         return i;
5383                 }
5384         }
5385         return -1;
5386 }
5387
5388 static inline int
5389 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5390                         uint8_t idx)
5391 {
5392         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5393                 return -1;
5394         filter_info->ethertype_mask &= ~(1 << idx);
5395         filter_info->ethertype_filters[idx] = 0;
5396         return idx;
5397 }
5398
5399 static int
5400 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5401                         struct rte_eth_ethertype_filter *filter,
5402                         bool add)
5403 {
5404         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5405         struct ixgbe_filter_info *filter_info =
5406                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5407         uint32_t etqf = 0;
5408         uint32_t etqs = 0;
5409         int ret;
5410
5411         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5412                 return -EINVAL;
5413
5414         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5415                 filter->ether_type == ETHER_TYPE_IPv6) {
5416                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5417                         " ethertype filter.", filter->ether_type);
5418                 return -EINVAL;
5419         }
5420
5421         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5422                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5423                 return -EINVAL;
5424         }
5425         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5426                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5427                 return -EINVAL;
5428         }
5429
5430         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5431         if (ret >= 0 && add) {
5432                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5433                             filter->ether_type);
5434                 return -EEXIST;
5435         }
5436         if (ret < 0 && !add) {
5437                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5438                             filter->ether_type);
5439                 return -ENOENT;
5440         }
5441
5442         if (add) {
5443                 ret = ixgbe_ethertype_filter_insert(filter_info,
5444                         filter->ether_type);
5445                 if (ret < 0) {
5446                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5447                         return -ENOSYS;
5448                 }
5449                 etqf = IXGBE_ETQF_FILTER_EN;
5450                 etqf |= (uint32_t)filter->ether_type;
5451                 etqs |= (uint32_t)((filter->queue <<
5452                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5453                                     IXGBE_ETQS_RX_QUEUE);
5454                 etqs |= IXGBE_ETQS_QUEUE_EN;
5455         } else {
5456                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5457                 if (ret < 0)
5458                         return -ENOSYS;
5459         }
5460         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5461         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5462         IXGBE_WRITE_FLUSH(hw);
5463
5464         return 0;
5465 }
5466
5467 static int
5468 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5469                         struct rte_eth_ethertype_filter *filter)
5470 {
5471         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5472         struct ixgbe_filter_info *filter_info =
5473                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5474         uint32_t etqf, etqs;
5475         int ret;
5476
5477         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5478         if (ret < 0) {
5479                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5480                             filter->ether_type);
5481                 return -ENOENT;
5482         }
5483
5484         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5485         if (etqf & IXGBE_ETQF_FILTER_EN) {
5486                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5487                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5488                 filter->flags = 0;
5489                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5490                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5491                 return 0;
5492         }
5493         return -ENOENT;
5494 }
5495
5496 /*
5497  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5498  * @dev: pointer to rte_eth_dev structure
5499  * @filter_op:operation will be taken.
5500  * @arg: a pointer to specific structure corresponding to the filter_op
5501  */
5502 static int
5503 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5504                                 enum rte_filter_op filter_op,
5505                                 void *arg)
5506 {
5507         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5508         int ret;
5509
5510         MAC_TYPE_FILTER_SUP(hw->mac.type);
5511
5512         if (filter_op == RTE_ETH_FILTER_NOP)
5513                 return 0;
5514
5515         if (arg == NULL) {
5516                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5517                             filter_op);
5518                 return -EINVAL;
5519         }
5520
5521         switch (filter_op) {
5522         case RTE_ETH_FILTER_ADD:
5523                 ret = ixgbe_add_del_ethertype_filter(dev,
5524                         (struct rte_eth_ethertype_filter *)arg,
5525                         TRUE);
5526                 break;
5527         case RTE_ETH_FILTER_DELETE:
5528                 ret = ixgbe_add_del_ethertype_filter(dev,
5529                         (struct rte_eth_ethertype_filter *)arg,
5530                         FALSE);
5531                 break;
5532         case RTE_ETH_FILTER_GET:
5533                 ret = ixgbe_get_ethertype_filter(dev,
5534                         (struct rte_eth_ethertype_filter *)arg);
5535                 break;
5536         default:
5537                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5538                 ret = -EINVAL;
5539                 break;
5540         }
5541         return ret;
5542 }
5543
5544 static int
5545 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5546                      enum rte_filter_type filter_type,
5547                      enum rte_filter_op filter_op,
5548                      void *arg)
5549 {
5550         int ret = -EINVAL;
5551
5552         switch (filter_type) {
5553         case RTE_ETH_FILTER_NTUPLE:
5554                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5555                 break;
5556         case RTE_ETH_FILTER_ETHERTYPE:
5557                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5558                 break;
5559         case RTE_ETH_FILTER_SYN:
5560                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5561                 break;
5562         case RTE_ETH_FILTER_FDIR:
5563                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5564                 break;
5565         default:
5566                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5567                                                         filter_type);
5568                 break;
5569         }
5570
5571         return ret;
5572 }
5573
5574 static u8 *
5575 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5576                         u8 **mc_addr_ptr, u32 *vmdq)
5577 {
5578         u8 *mc_addr;
5579
5580         *vmdq = 0;
5581         mc_addr = *mc_addr_ptr;
5582         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5583         return mc_addr;
5584 }
5585
5586 static int
5587 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5588                           struct ether_addr *mc_addr_set,
5589                           uint32_t nb_mc_addr)
5590 {
5591         struct ixgbe_hw *hw;
5592         u8 *mc_addr_list;
5593
5594         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5595         mc_addr_list = (u8 *)mc_addr_set;
5596         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5597                                          ixgbe_dev_addr_list_itr, TRUE);
5598 }
5599
5600 static uint64_t
5601 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5602 {
5603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5604         uint64_t systime_cycles;
5605
5606         switch (hw->mac.type) {
5607         case ixgbe_mac_X550:
5608                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5609                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5610                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5611                                 * NSEC_PER_SEC;
5612                 break;
5613         default:
5614                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5615                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5616                                 << 32;
5617         }
5618
5619         return systime_cycles;
5620 }
5621
5622 static uint64_t
5623 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5624 {
5625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5626         uint64_t rx_tstamp_cycles;
5627
5628         switch (hw->mac.type) {
5629         case ixgbe_mac_X550:
5630                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5631                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5632                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5633                                 * NSEC_PER_SEC;
5634                 break;
5635         default:
5636                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5637                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5638                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5639                                 << 32;
5640         }
5641
5642         return rx_tstamp_cycles;
5643 }
5644
5645 static uint64_t
5646 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5647 {
5648         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649         uint64_t tx_tstamp_cycles;
5650
5651         switch (hw->mac.type) {
5652         case ixgbe_mac_X550:
5653                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5654                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5655                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5656                                 * NSEC_PER_SEC;
5657                 break;
5658         default:
5659                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5660                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5661                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5662                                 << 32;
5663         }
5664
5665         return tx_tstamp_cycles;
5666 }
5667
5668 static void
5669 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5670 {
5671         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5672         struct ixgbe_adapter *adapter =
5673                 (struct ixgbe_adapter *)dev->data->dev_private;
5674         struct rte_eth_link link;
5675         uint32_t incval = 0;
5676         uint32_t shift = 0;
5677
5678         /* Get current link speed. */
5679         memset(&link, 0, sizeof(link));
5680         ixgbe_dev_link_update(dev, 1);
5681         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5682
5683         switch (link.link_speed) {
5684         case ETH_LINK_SPEED_100:
5685                 incval = IXGBE_INCVAL_100;
5686                 shift = IXGBE_INCVAL_SHIFT_100;
5687                 break;
5688         case ETH_LINK_SPEED_1000:
5689                 incval = IXGBE_INCVAL_1GB;
5690                 shift = IXGBE_INCVAL_SHIFT_1GB;
5691                 break;
5692         case ETH_LINK_SPEED_10000:
5693         default:
5694                 incval = IXGBE_INCVAL_10GB;
5695                 shift = IXGBE_INCVAL_SHIFT_10GB;
5696                 break;
5697         }
5698
5699         switch (hw->mac.type) {
5700         case ixgbe_mac_X550:
5701                 /* Independent of link speed. */
5702                 incval = 1;
5703                 /* Cycles read will be interpreted as ns. */
5704                 shift = 0;
5705                 /* Fall-through */
5706         case ixgbe_mac_X540:
5707                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5708                 break;
5709         case ixgbe_mac_82599EB:
5710                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5711                 shift -= IXGBE_INCVAL_SHIFT_82599;
5712                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5713                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5714                 break;
5715         default:
5716                 /* Not supported. */
5717                 return;
5718         }
5719
5720         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5721         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5722         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5723
5724         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5725         adapter->systime_tc.cc_shift = shift;
5726         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5727
5728         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5729         adapter->rx_tstamp_tc.cc_shift = shift;
5730         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5731
5732         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5733         adapter->tx_tstamp_tc.cc_shift = shift;
5734         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5735 }
5736
5737 static int
5738 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5739 {
5740         struct ixgbe_adapter *adapter =
5741                         (struct ixgbe_adapter *)dev->data->dev_private;
5742
5743         adapter->systime_tc.nsec += delta;
5744         adapter->rx_tstamp_tc.nsec += delta;
5745         adapter->tx_tstamp_tc.nsec += delta;
5746
5747         return 0;
5748 }
5749
5750 static int
5751 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5752 {
5753         uint64_t ns;
5754         struct ixgbe_adapter *adapter =
5755                         (struct ixgbe_adapter *)dev->data->dev_private;
5756
5757         ns = rte_timespec_to_ns(ts);
5758         /* Set the timecounters to a new value. */
5759         adapter->systime_tc.nsec = ns;
5760         adapter->rx_tstamp_tc.nsec = ns;
5761         adapter->tx_tstamp_tc.nsec = ns;
5762
5763         return 0;
5764 }
5765
5766 static int
5767 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5768 {
5769         uint64_t ns, systime_cycles;
5770         struct ixgbe_adapter *adapter =
5771                         (struct ixgbe_adapter *)dev->data->dev_private;
5772
5773         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5774         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5775         *ts = rte_ns_to_timespec(ns);
5776
5777         return 0;
5778 }
5779
5780 static int
5781 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5782 {
5783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5784         uint32_t tsync_ctl;
5785         uint32_t tsauxc;
5786
5787         /* Stop the timesync system time. */
5788         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5789         /* Reset the timesync system time value. */
5790         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5791         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5792
5793         /* Enable system time for platforms where it isn't on by default. */
5794         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5795         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5796         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5797
5798         ixgbe_start_timecounters(dev);
5799
5800         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5801         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5802                         (ETHER_TYPE_1588 |
5803                          IXGBE_ETQF_FILTER_EN |
5804                          IXGBE_ETQF_1588));
5805
5806         /* Enable timestamping of received PTP packets. */
5807         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5808         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5809         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5810
5811         /* Enable timestamping of transmitted PTP packets. */
5812         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5813         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5814         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5815
5816         IXGBE_WRITE_FLUSH(hw);
5817
5818         return 0;
5819 }
5820
5821 static int
5822 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5823 {
5824         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5825         uint32_t tsync_ctl;
5826
5827         /* Disable timestamping of transmitted PTP packets. */
5828         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5829         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5830         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5831
5832         /* Disable timestamping of received PTP packets. */
5833         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5834         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5835         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5836
5837         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5838         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5839
5840         /* Stop incrementating the System Time registers. */
5841         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5842
5843         return 0;
5844 }
5845
5846 static int
5847 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5848                                  struct timespec *timestamp,
5849                                  uint32_t flags __rte_unused)
5850 {
5851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5852         struct ixgbe_adapter *adapter =
5853                 (struct ixgbe_adapter *)dev->data->dev_private;
5854         uint32_t tsync_rxctl;
5855         uint64_t rx_tstamp_cycles;
5856         uint64_t ns;
5857
5858         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5859         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5860                 return -EINVAL;
5861
5862         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
5863         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5864         *timestamp = rte_ns_to_timespec(ns);
5865
5866         return  0;
5867 }
5868
5869 static int
5870 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5871                                  struct timespec *timestamp)
5872 {
5873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5874         struct ixgbe_adapter *adapter =
5875                 (struct ixgbe_adapter *)dev->data->dev_private;
5876         uint32_t tsync_txctl;
5877         uint64_t tx_tstamp_cycles;
5878         uint64_t ns;
5879
5880         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5881         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5882                 return -EINVAL;
5883
5884         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
5885         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5886         *timestamp = rte_ns_to_timespec(ns);
5887
5888         return 0;
5889 }
5890
5891 static int
5892 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5893 {
5894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5895         int count = 0;
5896         int g_ind = 0;
5897         const struct reg_info *reg_group;
5898         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5899                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5900
5901         while ((reg_group = reg_set[g_ind++]))
5902                 count += ixgbe_regs_group_count(reg_group);
5903
5904         return count;
5905 }
5906
5907 static int
5908 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5909 {
5910         int count = 0;
5911         int g_ind = 0;
5912         const struct reg_info *reg_group;
5913
5914         while ((reg_group = ixgbevf_regs[g_ind++]))
5915                 count += ixgbe_regs_group_count(reg_group);
5916
5917         return count;
5918 }
5919
5920 static int
5921 ixgbe_get_regs(struct rte_eth_dev *dev,
5922               struct rte_dev_reg_info *regs)
5923 {
5924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5925         uint32_t *data = regs->data;
5926         int g_ind = 0;
5927         int count = 0;
5928         const struct reg_info *reg_group;
5929         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5930                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5931
5932         /* Support only full register dump */
5933         if ((regs->length == 0) ||
5934             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5935                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5936                         hw->device_id;
5937                 while ((reg_group = reg_set[g_ind++]))
5938                         count += ixgbe_read_regs_group(dev, &data[count],
5939                                 reg_group);
5940                 return 0;
5941         }
5942
5943         return -ENOTSUP;
5944 }
5945
5946 static int
5947 ixgbevf_get_regs(struct rte_eth_dev *dev,
5948                 struct rte_dev_reg_info *regs)
5949 {
5950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5951         uint32_t *data = regs->data;
5952         int g_ind = 0;
5953         int count = 0;
5954         const struct reg_info *reg_group;
5955
5956         /* Support only full register dump */
5957         if ((regs->length == 0) ||
5958             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5959                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5960                         hw->device_id;
5961                 while ((reg_group = ixgbevf_regs[g_ind++]))
5962                         count += ixgbe_read_regs_group(dev, &data[count],
5963                                                       reg_group);
5964                 return 0;
5965         }
5966
5967         return -ENOTSUP;
5968 }
5969
5970 static int
5971 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5972 {
5973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5974
5975         /* Return unit is byte count */
5976         return hw->eeprom.word_size * 2;
5977 }
5978
5979 static int
5980 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5981                 struct rte_dev_eeprom_info *in_eeprom)
5982 {
5983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5984         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5985         uint16_t *data = in_eeprom->data;
5986         int first, length;
5987
5988         first = in_eeprom->offset >> 1;
5989         length = in_eeprom->length >> 1;
5990         if ((first > hw->eeprom.word_size) ||
5991             ((first + length) > hw->eeprom.word_size))
5992                 return -EINVAL;
5993
5994         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5995
5996         return eeprom->ops.read_buffer(hw, first, length, data);
5997 }
5998
5999 static int
6000 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6001                 struct rte_dev_eeprom_info *in_eeprom)
6002 {
6003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6004         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6005         uint16_t *data = in_eeprom->data;
6006         int first, length;
6007
6008         first = in_eeprom->offset >> 1;
6009         length = in_eeprom->length >> 1;
6010         if ((first > hw->eeprom.word_size) ||
6011             ((first + length) > hw->eeprom.word_size))
6012                 return -EINVAL;
6013
6014         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6015
6016         return eeprom->ops.write_buffer(hw,  first, length, data);
6017 }
6018
6019 uint16_t
6020 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6021         switch (mac_type) {
6022         case ixgbe_mac_X550:
6023         case ixgbe_mac_X550EM_x:
6024                 return ETH_RSS_RETA_SIZE_512;
6025         case ixgbe_mac_X550_vf:
6026         case ixgbe_mac_X550EM_x_vf:
6027                 return ETH_RSS_RETA_SIZE_64;
6028         default:
6029                 return ETH_RSS_RETA_SIZE_128;
6030         }
6031 }
6032
6033 uint32_t
6034 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6035         switch (mac_type) {
6036         case ixgbe_mac_X550:
6037         case ixgbe_mac_X550EM_x:
6038                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6039                         return IXGBE_RETA(reta_idx >> 2);
6040                 else
6041                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6042         case ixgbe_mac_X550_vf:
6043         case ixgbe_mac_X550EM_x_vf:
6044                 return IXGBE_VFRETA(reta_idx >> 2);
6045         default:
6046                 return IXGBE_RETA(reta_idx >> 2);
6047         }
6048 }
6049
6050 uint32_t
6051 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6052         switch (mac_type) {
6053         case ixgbe_mac_X550_vf:
6054         case ixgbe_mac_X550EM_x_vf:
6055                 return IXGBE_VFMRQC;
6056         default:
6057                 return IXGBE_MRQC;
6058         }
6059 }
6060
6061 uint32_t
6062 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6063         switch (mac_type) {
6064         case ixgbe_mac_X550_vf:
6065         case ixgbe_mac_X550EM_x_vf:
6066                 return IXGBE_VFRSSRK(i);
6067         default:
6068                 return IXGBE_RSSRK(i);
6069         }
6070 }
6071
6072 bool
6073 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6074         switch (mac_type) {
6075         case ixgbe_mac_82599_vf:
6076         case ixgbe_mac_X540_vf:
6077                 return 0;
6078         default:
6079                 return 1;
6080         }
6081 }
6082
6083 static int
6084 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6085                         struct rte_eth_dcb_info *dcb_info)
6086 {
6087         struct ixgbe_dcb_config *dcb_config =
6088                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6089         struct ixgbe_dcb_tc_config *tc;
6090         uint8_t i, j;
6091
6092         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6093                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6094         else
6095                 dcb_info->nb_tcs = 1;
6096
6097         if (dcb_config->vt_mode) { /* vt is enabled*/
6098                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6099                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6100                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6101                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6102                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6103                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6104                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6105                                                 i * dcb_info->nb_tcs + j;
6106                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6107                                 dcb_info->tc_queue.tc_txq[i][j].base =
6108                                                 i * dcb_info->nb_tcs + j;
6109                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6110                         }
6111                 }
6112         } else { /* vt is disabled*/
6113                 struct rte_eth_dcb_rx_conf *rx_conf =
6114                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6115                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6116                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6117                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6118                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6119                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6120                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6121                         }
6122                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6123                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6124                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6125                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6126                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6127                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6128                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6129                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6130                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6131                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6132                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6133                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6134                         }
6135                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6136                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6137                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6138                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6139                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6140                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6141                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6142                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6143                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6144                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6145                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6146                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6147                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6148                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6149                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6150                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6151                 }
6152         }
6153         for (i = 0; i < dcb_info->nb_tcs; i++) {
6154                 tc = &dcb_config->tc_config[i];
6155                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6156         }
6157         return 0;
6158 }
6159
6160 static struct rte_driver rte_ixgbe_driver = {
6161         .type = PMD_PDEV,
6162         .init = rte_ixgbe_pmd_init,
6163 };
6164
6165 static struct rte_driver rte_ixgbevf_driver = {
6166         .type = PMD_PDEV,
6167         .init = rte_ixgbevf_pmd_init,
6168 };
6169
6170 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6171 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);