drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 #define IXGBE_HKEY_MAX_INDEX 10
 104
 105 /* Additional timesync values. */
 106 #define NSEC_PER_SEC             1000000000L
 107 #define IXGBE_INCVAL_10GB        0x66666666
 108 #define IXGBE_INCVAL_1GB         0x40000000
 109 #define IXGBE_INCVAL_100         0x50000000
 110 #define IXGBE_INCVAL_SHIFT_10GB  28
 111 #define IXGBE_INCVAL_SHIFT_1GB   24
 112 #define IXGBE_INCVAL_SHIFT_100   21
 113 #define IXGBE_INCVAL_SHIFT_82599 7
 114 #define IXGBE_INCPER_SHIFT_82599 24
 115
 116 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 117
 118 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 119 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 120 #define DEFAULT_ETAG_ETYPE                     0x893f
 121 #define IXGBE_ETAG_ETYPE                       0x00005084
 122 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 123 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 124 #define IXGBE_RAH_ADTYPE                       0x40000000
 125 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 126 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 127 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 128 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 129 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 130 #define IXGBE_VTEICR_MASK                      0x07
 131
 132 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 133 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 134
 135 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 136 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 154                                 int wait_to_complete);
 155 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *stats);
 157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstat *xstats, unsigned n);
 159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 160                                   struct rte_eth_xstat *xstats, unsigned n);
 161 static int
 162 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 163                 uint64_t *values, unsigned int n);
 164 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         unsigned int size);
 169 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 171 static int ixgbe_dev_xstats_get_names_by_id(
 172         struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names,
 174         const uint64_t *ids,
 175         unsigned int limit);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 181                                  size_t fw_size);
 182 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 183                                struct rte_eth_dev_info *dev_info);
 184 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 185 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 186                                  struct rte_eth_dev_info *dev_info);
 187 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 188
 189 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 190                 uint16_t vlan_id, int on);
 191 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 192                                enum rte_vlan_type vlan_type,
 193                                uint16_t tpid_id);
 194 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 195                 uint16_t queue, bool on);
 196 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 197                 int on);
 198 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 200 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 201 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 202 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 203
 204 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 205 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 206 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 209                                struct rte_eth_fc_conf *fc_conf);
 210 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 211                 struct rte_eth_pfc_conf *pfc_conf);
 212 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 220 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 224                                       struct rte_intr_handle *handle);
 225 static void ixgbe_dev_interrupt_handler(void *param);
 226 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 227 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 228                          uint32_t index, uint32_t pool);
 229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 230 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 231                                            struct ether_addr *mac_addr);
 232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 233 static bool is_device_supported(struct rte_eth_dev *dev,
 234                                 struct rte_pci_driver *drv);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 242                                    int wait_to_complete);
 243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 247 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 249                 struct rte_eth_stats *stats);
 250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 252                 uint16_t vlan_id, int on);
 253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                 uint16_t queue, int on);
 255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 258                                             uint16_t queue_id);
 259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 260                                              uint16_t queue_id);
 261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 262                                  uint8_t queue, uint8_t msix_vector);
 263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 266
 267 /* For Eth VMDQ APIs support */
 268 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 269                 ether_addr * mac_addr, uint8_t on);
 270 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 271 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 272                 struct rte_eth_mirror_conf *mirror_conf,
 273                 uint8_t rule_id, uint8_t on);
 274 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 275                 uint8_t rule_id);
 276 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                           uint16_t queue_id);
 278 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                            uint16_t queue_id);
 280 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                uint8_t queue, uint8_t msix_vector);
 282 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 283
 284 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                 struct ether_addr *mac_addr,
 286                                 uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter);
 292 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 293                         enum rte_filter_op filter_op,
 294                         void *arg);
 295 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 298                         struct ixgbe_5tuple_filter *filter);
 299 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 300                                 enum rte_filter_op filter_op,
 301                                 void *arg);
 302 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter);
 304 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 305                                 enum rte_filter_op filter_op,
 306                                 void *arg);
 307 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 308                         struct rte_eth_ethertype_filter *filter);
 309 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 310                      enum rte_filter_type filter_type,
 311                      enum rte_filter_op filter_op,
 312                      void *arg);
 313 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 314
 315 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 316                                       struct ether_addr *mc_addr_set,
 317                                       uint32_t nb_mc_addr);
 318 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 319                                    struct rte_eth_dcb_info *dcb_info);
 320
 321 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 323                             struct rte_dev_reg_info *regs);
 324 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 325 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 328                                 struct rte_dev_eeprom_info *eeprom);
 329
 330 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 331 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 332                                 struct rte_dev_reg_info *regs);
 333
 334 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 335 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 337                                             struct timespec *timestamp,
 338                                             uint32_t flags);
 339 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp);
 341 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 342 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 343                                    struct timespec *timestamp);
 344 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 345                                    const struct timespec *timestamp);
 346 static void ixgbevf_dev_interrupt_handler(void *param);
 347
 348 static int ixgbe_dev_l2_tunnel_eth_type_conf
 349         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 350 static int ixgbe_dev_l2_tunnel_offload_set
 351         (struct rte_eth_dev *dev,
 352          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 353          uint32_t mask,
 354          uint8_t en);
 355 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 356                                              enum rte_filter_op filter_op,
 357                                              void *arg);
 358
 359 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 360                                          struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 364 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 365
 366 /*
 367  * Define VF Stats MACRO for Non "cleared on read" register
 368  */
 369 #define UPDATE_VF_STAT(reg, last, cur)                          \
 370 {                                                               \
 371         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 372         cur += (latest - last) & UINT_MAX;                      \
 373         last = latest;                                          \
 374 }
 375
 376 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 377 {                                                                \
 378         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 379         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 380         u64 latest = ((new_msb << 32) | new_lsb);                \
 381         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 382         last = latest;                                           \
 383 }
 384
 385 #define IXGBE_SET_HWSTRIP(h, q) do {\
 386                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 387                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 388                 (h)->bitmap[idx] |= 1 << bit;\
 389         } while (0)
 390
 391 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 392                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] &= ~(1 << bit);\
 395         } while (0)
 396
 397 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 398                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 400                 (r) = (h)->bitmap[idx] >> bit & 1;\
 401         } while (0)
 402
 403 int ixgbe_logtype_init;
 404 int ixgbe_logtype_driver;
 405
 406 /*
 407  * The set of PCI devices this driver supports
 408  */
 409 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 458 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 460 #endif
 461         { .vendor_id = 0, /* sentinel */ },
 462 };
 463
 464 /*
 465  * The set of PCI devices this driver supports (for 82599 VF)
 466  */
 467 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct rte_eth_desc_lim rx_desc_lim = {
 482         .nb_max = IXGBE_MAX_RING_DESC,
 483         .nb_min = IXGBE_MIN_RING_DESC,
 484         .nb_align = IXGBE_RXD_ALIGN,
 485 };
 486
 487 static const struct rte_eth_desc_lim tx_desc_lim = {
 488         .nb_max = IXGBE_MAX_RING_DESC,
 489         .nb_min = IXGBE_MIN_RING_DESC,
 490         .nb_align = IXGBE_TXD_ALIGN,
 491         .nb_seg_max = IXGBE_TX_MAX_SEG,
 492         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 493 };
 494
 495 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 496         .dev_configure        = ixgbe_dev_configure,
 497         .dev_start            = ixgbe_dev_start,
 498         .dev_stop             = ixgbe_dev_stop,
 499         .dev_set_link_up    = ixgbe_dev_set_link_up,
 500         .dev_set_link_down  = ixgbe_dev_set_link_down,
 501         .dev_close            = ixgbe_dev_close,
 502         .dev_reset            = ixgbe_dev_reset,
 503         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 504         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 505         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 506         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 507         .link_update          = ixgbe_dev_link_update,
 508         .stats_get            = ixgbe_dev_stats_get,
 509         .xstats_get           = ixgbe_dev_xstats_get,
 510         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 511         .stats_reset          = ixgbe_dev_stats_reset,
 512         .xstats_reset         = ixgbe_dev_xstats_reset,
 513         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 514         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 515         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 516         .fw_version_get       = ixgbe_fw_version_get,
 517         .dev_infos_get        = ixgbe_dev_info_get,
 518         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 519         .mtu_set              = ixgbe_dev_mtu_set,
 520         .vlan_filter_set      = ixgbe_vlan_filter_set,
 521         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 522         .vlan_offload_set     = ixgbe_vlan_offload_set,
 523         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 524         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 525         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 526         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 527         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 528         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 529         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 530         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 531         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 532         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 533         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 534         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 535         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 536         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 537         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 538         .dev_led_on           = ixgbe_dev_led_on,
 539         .dev_led_off          = ixgbe_dev_led_off,
 540         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 541         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 542         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 543         .mac_addr_add         = ixgbe_add_rar,
 544         .mac_addr_remove      = ixgbe_remove_rar,
 545         .mac_addr_set         = ixgbe_set_default_mac_addr,
 546         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 547         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 548         .mirror_rule_set      = ixgbe_mirror_rule_set,
 549         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 550         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 551         .reta_update          = ixgbe_dev_rss_reta_update,
 552         .reta_query           = ixgbe_dev_rss_reta_query,
 553         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 554         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 555         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 556         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 557         .rxq_info_get         = ixgbe_rxq_info_get,
 558         .txq_info_get         = ixgbe_txq_info_get,
 559         .timesync_enable      = ixgbe_timesync_enable,
 560         .timesync_disable     = ixgbe_timesync_disable,
 561         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 562         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 563         .get_reg              = ixgbe_get_regs,
 564         .get_eeprom_length    = ixgbe_get_eeprom_length,
 565         .get_eeprom           = ixgbe_get_eeprom,
 566         .set_eeprom           = ixgbe_set_eeprom,
 567         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 568         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 569         .timesync_read_time   = ixgbe_timesync_read_time,
 570         .timesync_write_time  = ixgbe_timesync_write_time,
 571         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 572         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 573         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 574         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 575         .tm_ops_get           = ixgbe_tm_ops_get,
 576 };
 577
 578 /*
 579  * dev_ops for virtual function, bare necessities for basic vf
 580  * operation have been implemented
 581  */
 582 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 583         .dev_configure        = ixgbevf_dev_configure,
 584         .dev_start            = ixgbevf_dev_start,
 585         .dev_stop             = ixgbevf_dev_stop,
 586         .link_update          = ixgbevf_dev_link_update,
 587         .stats_get            = ixgbevf_dev_stats_get,
 588         .xstats_get           = ixgbevf_dev_xstats_get,
 589         .stats_reset          = ixgbevf_dev_stats_reset,
 590         .xstats_reset         = ixgbevf_dev_stats_reset,
 591         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 592         .dev_close            = ixgbevf_dev_close,
 593         .dev_reset            = ixgbevf_dev_reset,
 594         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 595         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 596         .dev_infos_get        = ixgbevf_dev_info_get,
 597         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 598         .mtu_set              = ixgbevf_dev_set_mtu,
 599         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 600         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 601         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 602         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 603         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 604         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 605         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 606         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 607         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 608         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 609         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 610         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 611         .mac_addr_add         = ixgbevf_add_mac_addr,
 612         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 613         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 614         .rxq_info_get         = ixgbe_rxq_info_get,
 615         .txq_info_get         = ixgbe_txq_info_get,
 616         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 617         .get_reg              = ixgbevf_get_regs,
 618         .reta_update          = ixgbe_dev_rss_reta_update,
 619         .reta_query           = ixgbe_dev_rss_reta_query,
 620         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 621         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 622 };
 623
 624 /* store statistics names and its offset in stats structure */
 625 struct rte_ixgbe_xstats_name_off {
 626         char name[RTE_ETH_XSTATS_NAME_SIZE];
 627         unsigned offset;
 628 };
 629
 630 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 631         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 632         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 633         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 634         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 635         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 636         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 637         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 638         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 639         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 640         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 641         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 642         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 643         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 644         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 645         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 646                 prc1023)},
 647         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 648                 prc1522)},
 649         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 650         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 651         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 652         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 653         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 654         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 655         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 656         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 657         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 658         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 659         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 660         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 661         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 662         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 663         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 664         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 665         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 666                 ptc1023)},
 667         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 668                 ptc1522)},
 669         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 670         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 671         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 672         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 673
 674         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 675                 fdirustat_add)},
 676         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 677                 fdirustat_remove)},
 678         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 679                 fdirfstat_fadd)},
 680         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 681                 fdirfstat_fremove)},
 682         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 683                 fdirmatch)},
 684         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 685                 fdirmiss)},
 686
 687         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 688         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 689         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 690                 fclast)},
 691         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 692         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 693         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 694         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 695         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 696                 fcoe_noddp)},
 697         {"rx_fcoe_no_direct_data_placement_ext_buff",
 698                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 699
 700         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 701                 lxontxc)},
 702         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 703                 lxonrxc)},
 704         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxofftxc)},
 706         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxoffrxc)},
 708         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 709 };
 710
 711 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 712                            sizeof(rte_ixgbe_stats_strings[0]))
 713
 714 /* MACsec statistics */
 715 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 716         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 717                 out_pkts_untagged)},
 718         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 719                 out_pkts_encrypted)},
 720         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_protected)},
 722         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_octets_encrypted)},
 724         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_octets_protected)},
 726         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_untagged)},
 728         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_badtag)},
 730         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_nosci)},
 732         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_unknownsci)},
 734         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 735                 in_octets_decrypted)},
 736         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 737                 in_octets_validated)},
 738         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_unchecked)},
 740         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_delayed)},
 742         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_late)},
 744         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_ok)},
 746         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_invalid)},
 748         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_notvalid)},
 750         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_unusedsa)},
 752         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notusingsa)},
 754 };
 755
 756 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 757                            sizeof(rte_ixgbe_macsec_strings[0]))
 758
 759 /* Per-queue statistics */
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 761         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 762         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 763         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 764         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 765 };
 766
 767 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 768                            sizeof(rte_ixgbe_rxq_strings[0]))
 769 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 772         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 773         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 774         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 775                 pxon2offc)},
 776 };
 777
 778 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 779                            sizeof(rte_ixgbe_txq_strings[0]))
 780 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 781
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 783         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 784 };
 785
 786 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 787                 sizeof(rte_ixgbevf_stats_strings[0]))
 788
 789 /*
 790  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 791  */
 792 static inline int
 793 ixgbe_is_sfp(struct ixgbe_hw *hw)
 794 {
 795         switch (hw->phy.type) {
 796         case ixgbe_phy_sfp_avago:
 797         case ixgbe_phy_sfp_ftl:
 798         case ixgbe_phy_sfp_intel:
 799         case ixgbe_phy_sfp_unknown:
 800         case ixgbe_phy_sfp_passive_tyco:
 801         case ixgbe_phy_sfp_passive_unknown:
 802                 return 1;
 803         default:
 804                 return 0;
 805         }
 806 }
 807
 808 static inline int32_t
 809 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 810 {
 811         uint32_t ctrl_ext;
 812         int32_t status;
 813
 814         status = ixgbe_reset_hw(hw);
 815
 816         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 817         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 818         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 819         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 820         IXGBE_WRITE_FLUSH(hw);
 821
 822         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 823                 status = IXGBE_SUCCESS;
 824         return status;
 825 }
 826
 827 static inline void
 828 ixgbe_enable_intr(struct rte_eth_dev *dev)
 829 {
 830         struct ixgbe_interrupt *intr =
 831                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 832         struct ixgbe_hw *hw =
 833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 834
 835         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 836         IXGBE_WRITE_FLUSH(hw);
 837 }
 838
 839 /*
 840  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 841  */
 842 static void
 843 ixgbe_disable_intr(struct ixgbe_hw *hw)
 844 {
 845         PMD_INIT_FUNC_TRACE();
 846
 847         if (hw->mac.type == ixgbe_mac_82598EB) {
 848                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 849         } else {
 850                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 853         }
 854         IXGBE_WRITE_FLUSH(hw);
 855 }
 856
 857 /*
 858  * This function resets queue statistics mapping registers.
 859  * From Niantic datasheet, Initialization of Statistics section:
 860  * "...if software requires the queue counters, the RQSMR and TQSM registers
 861  * must be re-programmed following a device reset.
 862  */
 863 static void
 864 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 865 {
 866         uint32_t i;
 867
 868         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 869                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 870                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 871         }
 872 }
 873
 874
 875 static int
 876 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 877                                   uint16_t queue_id,
 878                                   uint8_t stat_idx,
 879                                   uint8_t is_rx)
 880 {
 881 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 882 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 883 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 884
 885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 886         struct ixgbe_stat_mapping_registers *stat_mappings =
 887                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 888         uint32_t qsmr_mask = 0;
 889         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 890         uint32_t q_map;
 891         uint8_t n, offset;
 892
 893         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 894                 (hw->mac.type != ixgbe_mac_X540) &&
 895                 (hw->mac.type != ixgbe_mac_X550) &&
 896                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 897                 (hw->mac.type != ixgbe_mac_X550EM_a))
 898                 return -ENOSYS;
 899
 900         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 901                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 902                      queue_id, stat_idx);
 903
 904         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 905         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 906                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 907                 return -EIO;
 908         }
 909         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 910
 911         /* Now clear any previous stat_idx set */
 912         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 913         if (!is_rx)
 914                 stat_mappings->tqsm[n] &= ~clearing_mask;
 915         else
 916                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 917
 918         q_map = (uint32_t)stat_idx;
 919         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 920         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 921         if (!is_rx)
 922                 stat_mappings->tqsm[n] |= qsmr_mask;
 923         else
 924                 stat_mappings->rqsmr[n] |= qsmr_mask;
 925
 926         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 927                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 928                      queue_id, stat_idx);
 929         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 930                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 931
 932         /* Now write the mapping in the appropriate register */
 933         if (is_rx) {
 934                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 935                              stat_mappings->rqsmr[n], n);
 936                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 937         } else {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 939                              stat_mappings->tqsm[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 941         }
 942         return 0;
 943 }
 944
 945 static void
 946 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 947 {
 948         struct ixgbe_stat_mapping_registers *stat_mappings =
 949                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951         int i;
 952
 953         /* write whatever was in stat mapping table to the NIC */
 954         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 /* rx */
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 957
 958                 /* tx */
 959                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 960         }
 961 }
 962
 963 static void
 964 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 965 {
 966         uint8_t i;
 967         struct ixgbe_dcb_tc_config *tc;
 968         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 969
 970         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 971         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 972         for (i = 0; i < dcb_max_tc; i++) {
 973                 tc = &dcb_config->tc_config[i];
 974                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 975                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 976                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 977                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 978                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 979                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 980                 tc->pfc = ixgbe_dcb_pfc_disabled;
 981         }
 982
 983         /* Initialize default user to priority mapping, UPx->TC0 */
 984         tc = &dcb_config->tc_config[0];
 985         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 986         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 987         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 988                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 989                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 990         }
 991         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 992         dcb_config->pfc_mode_enable = false;
 993         dcb_config->vt_mode = true;
 994         dcb_config->round_robin_enable = false;
 995         /* support all DCB capabilities in 82599 */
 996         dcb_config->support.capabilities = 0xFF;
 997
 998         /*we only support 4 Tcs for X540, X550 */
 999         if (hw->mac.type == ixgbe_mac_X540 ||
1000                 hw->mac.type == ixgbe_mac_X550 ||
1001                 hw->mac.type == ixgbe_mac_X550EM_x ||
1002                 hw->mac.type == ixgbe_mac_X550EM_a) {
1003                 dcb_config->num_tcs.pg_tcs = 4;
1004                 dcb_config->num_tcs.pfc_tcs = 4;
1005         }
1006 }
1007
1008 /*
1009  * Ensure that all locks are released before first NVM or PHY access
1010  */
1011 static void
1012 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1013 {
1014         uint16_t mask;
1015
1016         /*
1017          * Phy lock should not fail in this early stage. If this is the case,
1018          * it is due to an improper exit of the application.
1019          * So force the release of the faulty lock. Release of common lock
1020          * is done automatically by swfw_sync function.
1021          */
1022         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1023         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1024                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1025         }
1026         ixgbe_release_swfw_semaphore(hw, mask);
1027
1028         /*
1029          * These ones are more tricky since they are common to all ports; but
1030          * swfw_sync retries last long enough (1s) to be almost sure that if
1031          * lock can not be taken it is due to an improper lock of the
1032          * semaphore.
1033          */
1034         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1035         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1037         }
1038         ixgbe_release_swfw_semaphore(hw, mask);
1039 }
1040
1041 /*
1042  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1043  * It returns 0 on success.
1044  */
1045 static int
1046 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1047 {
1048         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1049         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1050         struct ixgbe_hw *hw =
1051                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1052         struct ixgbe_vfta *shadow_vfta =
1053                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1054         struct ixgbe_hwstrip *hwstrip =
1055                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1056         struct ixgbe_dcb_config *dcb_config =
1057                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1058         struct ixgbe_filter_info *filter_info =
1059                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1060         struct ixgbe_bw_conf *bw_conf =
1061                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1062         uint32_t ctrl_ext;
1063         uint16_t csum;
1064         int diag, i;
1065
1066         PMD_INIT_FUNC_TRACE();
1067
1068         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1069         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1070         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1071         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1072
1073         /*
1074          * For secondary processes, we don't initialise any further as primary
1075          * has already done this work. Only check we don't need a different
1076          * RX and TX function.
1077          */
1078         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1079                 struct ixgbe_tx_queue *txq;
1080                 /* TX queue function in primary, set by last queue initialized
1081                  * Tx queue may not initialized by primary process
1082                  */
1083                 if (eth_dev->data->tx_queues) {
1084                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1085                         ixgbe_set_tx_function(eth_dev, txq);
1086                 } else {
1087                         /* Use default TX function if we get here */
1088                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1089                                      "Using default TX function.");
1090                 }
1091
1092                 ixgbe_set_rx_function(eth_dev);
1093
1094                 return 0;
1095         }
1096
1097         rte_eth_copy_pci_info(eth_dev, pci_dev);
1098
1099         /* Vendor and Device ID need to be set before init of shared code */
1100         hw->device_id = pci_dev->id.device_id;
1101         hw->vendor_id = pci_dev->id.vendor_id;
1102         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1103         hw->allow_unsupported_sfp = 1;
1104
1105         /* Initialize the shared code (base driver) */
1106 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1107         diag = ixgbe_bypass_init_shared_code(hw);
1108 #else
1109         diag = ixgbe_init_shared_code(hw);
1110 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1111
1112         if (diag != IXGBE_SUCCESS) {
1113                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1114                 return -EIO;
1115         }
1116
1117         /* pick up the PCI bus settings for reporting later */
1118         ixgbe_get_bus_info(hw);
1119
1120         /* Unlock any pending hardware semaphore */
1121         ixgbe_swfw_lock_reset(hw);
1122
1123 #ifdef RTE_LIBRTE_SECURITY
1124         /* Initialize security_ctx only for primary process*/
1125         if (ixgbe_ipsec_ctx_create(eth_dev))
1126                 return -ENOMEM;
1127 #endif
1128
1129         /* Initialize DCB configuration*/
1130         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1131         ixgbe_dcb_init(hw, dcb_config);
1132         /* Get Hardware Flow Control setting */
1133         hw->fc.requested_mode = ixgbe_fc_full;
1134         hw->fc.current_mode = ixgbe_fc_full;
1135         hw->fc.pause_time = IXGBE_FC_PAUSE;
1136         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1137                 hw->fc.low_water[i] = IXGBE_FC_LO;
1138                 hw->fc.high_water[i] = IXGBE_FC_HI;
1139         }
1140         hw->fc.send_xon = 1;
1141
1142         /* Make sure we have a good EEPROM before we read from it */
1143         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1144         if (diag != IXGBE_SUCCESS) {
1145                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1146                 return -EIO;
1147         }
1148
1149 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1150         diag = ixgbe_bypass_init_hw(hw);
1151 #else
1152         diag = ixgbe_init_hw(hw);
1153 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1154
1155         /*
1156          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1157          * is called too soon after the kernel driver unbinding/binding occurs.
1158          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1159          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1160          * also called. See ixgbe_identify_phy_82599(). The reason for the
1161          * failure is not known, and only occuts when virtualisation features
1162          * are disabled in the bios. A delay of 100ms  was found to be enough by
1163          * trial-and-error, and is doubled to be safe.
1164          */
1165         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1166                 rte_delay_ms(200);
1167                 diag = ixgbe_init_hw(hw);
1168         }
1169
1170         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1171                 diag = IXGBE_SUCCESS;
1172
1173         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1174                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1175                              "LOM.  Please be aware there may be issues associated "
1176                              "with your hardware.");
1177                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1178                              "please contact your Intel or hardware representative "
1179                              "who provided you with this hardware.");
1180         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1181                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1182         if (diag) {
1183                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1184                 return -EIO;
1185         }
1186
1187         /* Reset the hw statistics */
1188         ixgbe_dev_stats_reset(eth_dev);
1189
1190         /* disable interrupt */
1191         ixgbe_disable_intr(hw);
1192
1193         /* reset mappings for queue statistics hw counters*/
1194         ixgbe_reset_qstat_mappings(hw);
1195
1196         /* Allocate memory for storing MAC addresses */
1197         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1198                                                hw->mac.num_rar_entries, 0);
1199         if (eth_dev->data->mac_addrs == NULL) {
1200                 PMD_INIT_LOG(ERR,
1201                              "Failed to allocate %u bytes needed to store "
1202                              "MAC addresses",
1203                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1204                 return -ENOMEM;
1205         }
1206         /* Copy the permanent MAC address */
1207         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1208                         &eth_dev->data->mac_addrs[0]);
1209
1210         /* Allocate memory for storing hash filter MAC addresses */
1211         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1212                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1213         if (eth_dev->data->hash_mac_addrs == NULL) {
1214                 PMD_INIT_LOG(ERR,
1215                              "Failed to allocate %d bytes needed to store MAC addresses",
1216                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1217                 return -ENOMEM;
1218         }
1219
1220         /* initialize the vfta */
1221         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1222
1223         /* initialize the hw strip bitmap*/
1224         memset(hwstrip, 0, sizeof(*hwstrip));
1225
1226         /* initialize PF if max_vfs not zero */
1227         ixgbe_pf_host_init(eth_dev);
1228
1229         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1230         /* let hardware know driver is loaded */
1231         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1232         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1233         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1234         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1235         IXGBE_WRITE_FLUSH(hw);
1236
1237         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1238                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1239                              (int) hw->mac.type, (int) hw->phy.type,
1240                              (int) hw->phy.sfp_type);
1241         else
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type);
1244
1245         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1246                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1247                      pci_dev->id.device_id);
1248
1249         rte_intr_callback_register(intr_handle,
1250                                    ixgbe_dev_interrupt_handler, eth_dev);
1251
1252         /* enable uio/vfio intr/eventfd mapping */
1253         rte_intr_enable(intr_handle);
1254
1255         /* enable support intr */
1256         ixgbe_enable_intr(eth_dev);
1257
1258         /* initialize filter info */
1259         memset(filter_info, 0,
1260                sizeof(struct ixgbe_filter_info));
1261
1262         /* initialize 5tuple filter list */
1263         TAILQ_INIT(&filter_info->fivetuple_list);
1264
1265         /* initialize flow director filter list & hash */
1266         ixgbe_fdir_filter_init(eth_dev);
1267
1268         /* initialize l2 tunnel filter list & hash */
1269         ixgbe_l2_tn_filter_init(eth_dev);
1270
1271         /* initialize flow filter lists */
1272         ixgbe_filterlist_init();
1273
1274         /* initialize bandwidth configuration info */
1275         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1276
1277         /* initialize Traffic Manager configuration */
1278         ixgbe_tm_conf_init(eth_dev);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1285 {
1286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1287         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288         struct ixgbe_hw *hw;
1289         int retries = 0;
1290         int ret;
1291
1292         PMD_INIT_FUNC_TRACE();
1293
1294         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1295                 return -EPERM;
1296
1297         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1298
1299         if (hw->adapter_stopped == 0)
1300                 ixgbe_dev_close(eth_dev);
1301
1302         eth_dev->dev_ops = NULL;
1303         eth_dev->rx_pkt_burst = NULL;
1304         eth_dev->tx_pkt_burst = NULL;
1305
1306         /* Unlock any pending hardware semaphore */
1307         ixgbe_swfw_lock_reset(hw);
1308
1309         /* disable uio intr before callback unregister */
1310         rte_intr_disable(intr_handle);
1311
1312         do {
1313                 ret = rte_intr_callback_unregister(intr_handle,
1314                                 ixgbe_dev_interrupt_handler, eth_dev);
1315                 if (ret >= 0) {
1316                         break;
1317                 } else if (ret != -EAGAIN) {
1318                         PMD_INIT_LOG(ERR,
1319                                 "intr callback unregister failed: %d",
1320                                 ret);
1321                         return ret;
1322                 }
1323                 rte_delay_ms(100);
1324         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1325
1326         /* uninitialize PF if max_vfs not zero */
1327         ixgbe_pf_host_uninit(eth_dev);
1328
1329         rte_free(eth_dev->data->mac_addrs);
1330         eth_dev->data->mac_addrs = NULL;
1331
1332         rte_free(eth_dev->data->hash_mac_addrs);
1333         eth_dev->data->hash_mac_addrs = NULL;
1334
1335         /* remove all the fdir filters & hash */
1336         ixgbe_fdir_filter_uninit(eth_dev);
1337
1338         /* remove all the L2 tunnel filters & hash */
1339         ixgbe_l2_tn_filter_uninit(eth_dev);
1340
1341         /* Remove all ntuple filters of the device */
1342         ixgbe_ntuple_filter_uninit(eth_dev);
1343
1344         /* clear all the filters list */
1345         ixgbe_filterlist_flush();
1346
1347         /* Remove all Traffic Manager configuration */
1348         ixgbe_tm_conf_uninit(eth_dev);
1349
1350 #ifdef RTE_LIBRTE_SECURITY
1351         rte_free(eth_dev->security_ctx);
1352 #endif
1353
1354         return 0;
1355 }
1356
1357 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct ixgbe_filter_info *filter_info =
1360                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1361         struct ixgbe_5tuple_filter *p_5tuple;
1362
1363         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1364                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1365                              p_5tuple,
1366                              entries);
1367                 rte_free(p_5tuple);
1368         }
1369         memset(filter_info->fivetuple_mask, 0,
1370                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1371
1372         return 0;
1373 }
1374
1375 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1376 {
1377         struct ixgbe_hw_fdir_info *fdir_info =
1378                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1379         struct ixgbe_fdir_filter *fdir_filter;
1380
1381                 if (fdir_info->hash_map)
1382                 rte_free(fdir_info->hash_map);
1383         if (fdir_info->hash_handle)
1384                 rte_hash_free(fdir_info->hash_handle);
1385
1386         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1387                 TAILQ_REMOVE(&fdir_info->fdir_list,
1388                              fdir_filter,
1389                              entries);
1390                 rte_free(fdir_filter);
1391         }
1392
1393         return 0;
1394 }
1395
1396 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1397 {
1398         struct ixgbe_l2_tn_info *l2_tn_info =
1399                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1400         struct ixgbe_l2_tn_filter *l2_tn_filter;
1401
1402         if (l2_tn_info->hash_map)
1403                 rte_free(l2_tn_info->hash_map);
1404         if (l2_tn_info->hash_handle)
1405                 rte_hash_free(l2_tn_info->hash_handle);
1406
1407         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1408                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1409                              l2_tn_filter,
1410                              entries);
1411                 rte_free(l2_tn_filter);
1412         }
1413
1414         return 0;
1415 }
1416
1417 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1418 {
1419         struct ixgbe_hw_fdir_info *fdir_info =
1420                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1421         char fdir_hash_name[RTE_HASH_NAMESIZE];
1422         struct rte_hash_parameters fdir_hash_params = {
1423                 .name = fdir_hash_name,
1424                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1425                 .key_len = sizeof(union ixgbe_atr_input),
1426                 .hash_func = rte_hash_crc,
1427                 .hash_func_init_val = 0,
1428                 .socket_id = rte_socket_id(),
1429         };
1430
1431         TAILQ_INIT(&fdir_info->fdir_list);
1432         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1433                  "fdir_%s", eth_dev->device->name);
1434         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1435         if (!fdir_info->hash_handle) {
1436                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1437                 return -EINVAL;
1438         }
1439         fdir_info->hash_map = rte_zmalloc("ixgbe",
1440                                           sizeof(struct ixgbe_fdir_filter *) *
1441                                           IXGBE_MAX_FDIR_FILTER_NUM,
1442                                           0);
1443         if (!fdir_info->hash_map) {
1444                 PMD_INIT_LOG(ERR,
1445                              "Failed to allocate memory for fdir hash map!");
1446                 return -ENOMEM;
1447         }
1448         fdir_info->mask_added = FALSE;
1449
1450         return 0;
1451 }
1452
1453 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1454 {
1455         struct ixgbe_l2_tn_info *l2_tn_info =
1456                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1457         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1458         struct rte_hash_parameters l2_tn_hash_params = {
1459                 .name = l2_tn_hash_name,
1460                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1461                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1462                 .hash_func = rte_hash_crc,
1463                 .hash_func_init_val = 0,
1464                 .socket_id = rte_socket_id(),
1465         };
1466
1467         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1468         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1469                  "l2_tn_%s", eth_dev->device->name);
1470         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1471         if (!l2_tn_info->hash_handle) {
1472                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1473                 return -EINVAL;
1474         }
1475         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1476                                    sizeof(struct ixgbe_l2_tn_filter *) *
1477                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1478                                    0);
1479         if (!l2_tn_info->hash_map) {
1480                 PMD_INIT_LOG(ERR,
1481                         "Failed to allocate memory for L2 TN hash map!");
1482                 return -ENOMEM;
1483         }
1484         l2_tn_info->e_tag_en = FALSE;
1485         l2_tn_info->e_tag_fwd_en = FALSE;
1486         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1487
1488         return 0;
1489 }
1490 /*
1491  * Negotiate mailbox API version with the PF.
1492  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1493  * Then we try to negotiate starting with the most recent one.
1494  * If all negotiation attempts fail, then we will proceed with
1495  * the default one (ixgbe_mbox_api_10).
1496  */
1497 static void
1498 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1499 {
1500         int32_t i;
1501
1502         /* start with highest supported, proceed down */
1503         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1504                 ixgbe_mbox_api_12,
1505                 ixgbe_mbox_api_11,
1506                 ixgbe_mbox_api_10,
1507         };
1508
1509         for (i = 0;
1510                         i != RTE_DIM(sup_ver) &&
1511                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1512                         i++)
1513                 ;
1514 }
1515
1516 static void
1517 generate_random_mac_addr(struct ether_addr *mac_addr)
1518 {
1519         uint64_t random;
1520
1521         /* Set Organizationally Unique Identifier (OUI) prefix. */
1522         mac_addr->addr_bytes[0] = 0x00;
1523         mac_addr->addr_bytes[1] = 0x09;
1524         mac_addr->addr_bytes[2] = 0xC0;
1525         /* Force indication of locally assigned MAC address. */
1526         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1527         /* Generate the last 3 bytes of the MAC address with a random number. */
1528         random = rte_rand();
1529         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1530 }
1531
1532 /*
1533  * Virtual Function device init
1534  */
1535 static int
1536 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1537 {
1538         int diag;
1539         uint32_t tc, tcs;
1540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542         struct ixgbe_hw *hw =
1543                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1544         struct ixgbe_vfta *shadow_vfta =
1545                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1546         struct ixgbe_hwstrip *hwstrip =
1547                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1548         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1549
1550         PMD_INIT_FUNC_TRACE();
1551
1552         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1553         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1554         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1555
1556         /* for secondary processes, we don't initialise any further as primary
1557          * has already done this work. Only check we don't need a different
1558          * RX function
1559          */
1560         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1561                 struct ixgbe_tx_queue *txq;
1562                 /* TX queue function in primary, set by last queue initialized
1563                  * Tx queue may not initialized by primary process
1564                  */
1565                 if (eth_dev->data->tx_queues) {
1566                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1567                         ixgbe_set_tx_function(eth_dev, txq);
1568                 } else {
1569                         /* Use default TX function if we get here */
1570                         PMD_INIT_LOG(NOTICE,
1571                                      "No TX queues configured yet. Using default TX function.");
1572                 }
1573
1574                 ixgbe_set_rx_function(eth_dev);
1575
1576                 return 0;
1577         }
1578
1579         rte_eth_copy_pci_info(eth_dev, pci_dev);
1580
1581         hw->device_id = pci_dev->id.device_id;
1582         hw->vendor_id = pci_dev->id.vendor_id;
1583         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1584
1585         /* initialize the vfta */
1586         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1587
1588         /* initialize the hw strip bitmap*/
1589         memset(hwstrip, 0, sizeof(*hwstrip));
1590
1591         /* Initialize the shared code (base driver) */
1592         diag = ixgbe_init_shared_code(hw);
1593         if (diag != IXGBE_SUCCESS) {
1594                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1595                 return -EIO;
1596         }
1597
1598         /* init_mailbox_params */
1599         hw->mbx.ops.init_params(hw);
1600
1601         /* Reset the hw statistics */
1602         ixgbevf_dev_stats_reset(eth_dev);
1603
1604         /* Disable the interrupts for VF */
1605         ixgbevf_intr_disable(hw);
1606
1607         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1608         diag = hw->mac.ops.reset_hw(hw);
1609
1610         /*
1611          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1612          * the underlying PF driver has not assigned a MAC address to the VF.
1613          * In this case, assign a random MAC address.
1614          */
1615         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1616                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1617                 return diag;
1618         }
1619
1620         /* negotiate mailbox API version to use with the PF. */
1621         ixgbevf_negotiate_api(hw);
1622
1623         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1624         ixgbevf_get_queues(hw, &tcs, &tc);
1625
1626         /* Allocate memory for storing MAC addresses */
1627         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1628                                                hw->mac.num_rar_entries, 0);
1629         if (eth_dev->data->mac_addrs == NULL) {
1630                 PMD_INIT_LOG(ERR,
1631                              "Failed to allocate %u bytes needed to store "
1632                              "MAC addresses",
1633                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1634                 return -ENOMEM;
1635         }
1636
1637         /* Generate a random MAC address, if none was assigned by PF. */
1638         if (is_zero_ether_addr(perm_addr)) {
1639                 generate_random_mac_addr(perm_addr);
1640                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1641                 if (diag) {
1642                         rte_free(eth_dev->data->mac_addrs);
1643                         eth_dev->data->mac_addrs = NULL;
1644                         return diag;
1645                 }
1646                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1647                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1648                              "%02x:%02x:%02x:%02x:%02x:%02x",
1649                              perm_addr->addr_bytes[0],
1650                              perm_addr->addr_bytes[1],
1651                              perm_addr->addr_bytes[2],
1652                              perm_addr->addr_bytes[3],
1653                              perm_addr->addr_bytes[4],
1654                              perm_addr->addr_bytes[5]);
1655         }
1656
1657         /* Copy the permanent MAC address */
1658         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1659
1660         /* reset the hardware with the new settings */
1661         diag = hw->mac.ops.start_hw(hw);
1662         switch (diag) {
1663         case  0:
1664                 break;
1665
1666         default:
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return -EIO;
1669         }
1670
1671         rte_intr_callback_register(intr_handle,
1672                                    ixgbevf_dev_interrupt_handler, eth_dev);
1673         rte_intr_enable(intr_handle);
1674         ixgbevf_intr_enable(hw);
1675
1676         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1677                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1678                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1679
1680         return 0;
1681 }
1682
1683 /* Virtual Function device uninit */
1684
1685 static int
1686 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1687 {
1688         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1689         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690         struct ixgbe_hw *hw;
1691
1692         PMD_INIT_FUNC_TRACE();
1693
1694         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1695                 return -EPERM;
1696
1697         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1698
1699         if (hw->adapter_stopped == 0)
1700                 ixgbevf_dev_close(eth_dev);
1701
1702         eth_dev->dev_ops = NULL;
1703         eth_dev->rx_pkt_burst = NULL;
1704         eth_dev->tx_pkt_burst = NULL;
1705
1706         /* Disable the interrupts for VF */
1707         ixgbevf_intr_disable(hw);
1708
1709         rte_free(eth_dev->data->mac_addrs);
1710         eth_dev->data->mac_addrs = NULL;
1711
1712         rte_intr_disable(intr_handle);
1713         rte_intr_callback_unregister(intr_handle,
1714                                      ixgbevf_dev_interrupt_handler, eth_dev);
1715
1716         return 0;
1717 }
1718
1719 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1720         struct rte_pci_device *pci_dev)
1721 {
1722         return rte_eth_dev_pci_generic_probe(pci_dev,
1723                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1724 }
1725
1726 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1727 {
1728         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1729 }
1730
1731 static struct rte_pci_driver rte_ixgbe_pmd = {
1732         .id_table = pci_id_ixgbe_map,
1733         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1734                      RTE_PCI_DRV_IOVA_AS_VA,
1735         .probe = eth_ixgbe_pci_probe,
1736         .remove = eth_ixgbe_pci_remove,
1737 };
1738
1739 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1740         struct rte_pci_device *pci_dev)
1741 {
1742         return rte_eth_dev_pci_generic_probe(pci_dev,
1743                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1744 }
1745
1746 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1747 {
1748         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1749 }
1750
1751 /*
1752  * virtual function driver struct
1753  */
1754 static struct rte_pci_driver rte_ixgbevf_pmd = {
1755         .id_table = pci_id_ixgbevf_map,
1756         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1757         .probe = eth_ixgbevf_pci_probe,
1758         .remove = eth_ixgbevf_pci_remove,
1759 };
1760
1761 static int
1762 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1763 {
1764         struct ixgbe_hw *hw =
1765                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1766         struct ixgbe_vfta *shadow_vfta =
1767                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1768         uint32_t vfta;
1769         uint32_t vid_idx;
1770         uint32_t vid_bit;
1771
1772         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1773         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1774         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1775         if (on)
1776                 vfta |= vid_bit;
1777         else
1778                 vfta &= ~vid_bit;
1779         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1780
1781         /* update local VFTA copy */
1782         shadow_vfta->vfta[vid_idx] = vfta;
1783
1784         return 0;
1785 }
1786
1787 static void
1788 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1789 {
1790         if (on)
1791                 ixgbe_vlan_hw_strip_enable(dev, queue);
1792         else
1793                 ixgbe_vlan_hw_strip_disable(dev, queue);
1794 }
1795
1796 static int
1797 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1798                     enum rte_vlan_type vlan_type,
1799                     uint16_t tpid)
1800 {
1801         struct ixgbe_hw *hw =
1802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803         int ret = 0;
1804         uint32_t reg;
1805         uint32_t qinq;
1806
1807         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1808         qinq &= IXGBE_DMATXCTL_GDV;
1809
1810         switch (vlan_type) {
1811         case ETH_VLAN_TYPE_INNER:
1812                 if (qinq) {
1813                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1814                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1815                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1816                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1817                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1818                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1819                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1820                 } else {
1821                         ret = -ENOTSUP;
1822                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1823                                     " by single VLAN");
1824                 }
1825                 break;
1826         case ETH_VLAN_TYPE_OUTER:
1827                 if (qinq) {
1828                         /* Only the high 16-bits is valid */
1829                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1830                                         IXGBE_EXVET_VET_EXT_SHIFT);
1831                 } else {
1832                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1833                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1834                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1835                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1836                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1837                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1838                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1839                 }
1840
1841                 break;
1842         default:
1843                 ret = -EINVAL;
1844                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1845                 break;
1846         }
1847
1848         return ret;
1849 }
1850
1851 void
1852 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1853 {
1854         struct ixgbe_hw *hw =
1855                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856         uint32_t vlnctrl;
1857
1858         PMD_INIT_FUNC_TRACE();
1859
1860         /* Filter Table Disable */
1861         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1862         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1863
1864         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1865 }
1866
1867 void
1868 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         struct ixgbe_vfta *shadow_vfta =
1873                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1874         uint32_t vlnctrl;
1875         uint16_t i;
1876
1877         PMD_INIT_FUNC_TRACE();
1878
1879         /* Filter Table Enable */
1880         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1881         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1882         vlnctrl |= IXGBE_VLNCTRL_VFE;
1883
1884         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1885
1886         /* write whatever is in local vfta copy */
1887         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1888                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1889 }
1890
1891 static void
1892 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1893 {
1894         struct ixgbe_hwstrip *hwstrip =
1895                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1896         struct ixgbe_rx_queue *rxq;
1897
1898         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1899                 return;
1900
1901         if (on)
1902                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1903         else
1904                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1905
1906         if (queue >= dev->data->nb_rx_queues)
1907                 return;
1908
1909         rxq = dev->data->rx_queues[queue];
1910
1911         if (on)
1912                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1913         else
1914                 rxq->vlan_flags = PKT_RX_VLAN;
1915 }
1916
1917 static void
1918 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint32_t ctrl;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         if (hw->mac.type == ixgbe_mac_82598EB) {
1927                 /* No queue level support */
1928                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1929                 return;
1930         }
1931
1932         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1933         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1934         ctrl &= ~IXGBE_RXDCTL_VME;
1935         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1936
1937         /* record those setting for HW strip per queue */
1938         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1939 }
1940
1941 static void
1942 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1943 {
1944         struct ixgbe_hw *hw =
1945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946         uint32_t ctrl;
1947
1948         PMD_INIT_FUNC_TRACE();
1949
1950         if (hw->mac.type == ixgbe_mac_82598EB) {
1951                 /* No queue level supported */
1952                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1953                 return;
1954         }
1955
1956         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1957         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1958         ctrl |= IXGBE_RXDCTL_VME;
1959         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1960
1961         /* record those setting for HW strip per queue */
1962         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1963 }
1964
1965 static void
1966 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1967 {
1968         struct ixgbe_hw *hw =
1969                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970         uint32_t ctrl;
1971
1972         PMD_INIT_FUNC_TRACE();
1973
1974         /* DMATXCTRL: Geric Double VLAN Disable */
1975         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1976         ctrl &= ~IXGBE_DMATXCTL_GDV;
1977         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1978
1979         /* CTRL_EXT: Global Double VLAN Disable */
1980         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1981         ctrl &= ~IXGBE_EXTENDED_VLAN;
1982         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1983
1984 }
1985
1986 static void
1987 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1988 {
1989         struct ixgbe_hw *hw =
1990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         uint32_t ctrl;
1992
1993         PMD_INIT_FUNC_TRACE();
1994
1995         /* DMATXCTRL: Geric Double VLAN Enable */
1996         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1997         ctrl |= IXGBE_DMATXCTL_GDV;
1998         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1999
2000         /* CTRL_EXT: Global Double VLAN Enable */
2001         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2002         ctrl |= IXGBE_EXTENDED_VLAN;
2003         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2004
2005         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2006         if (hw->mac.type == ixgbe_mac_X550 ||
2007             hw->mac.type == ixgbe_mac_X550EM_x ||
2008             hw->mac.type == ixgbe_mac_X550EM_a) {
2009                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2010                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2011                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2012         }
2013
2014         /*
2015          * VET EXT field in the EXVET register = 0x8100 by default
2016          * So no need to change. Same to VT field of DMATXCTL register
2017          */
2018 }
2019
2020 void
2021 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2022 {
2023         struct ixgbe_hw *hw =
2024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2026         uint32_t ctrl;
2027         uint16_t i;
2028         struct ixgbe_rx_queue *rxq;
2029         bool on;
2030
2031         PMD_INIT_FUNC_TRACE();
2032
2033         if (hw->mac.type == ixgbe_mac_82598EB) {
2034                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2035                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2036                         ctrl |= IXGBE_VLNCTRL_VME;
2037                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2038                 } else {
2039                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2040                         ctrl &= ~IXGBE_VLNCTRL_VME;
2041                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2042                 }
2043         } else {
2044                 /*
2045                  * Other 10G NIC, the VLAN strip can be setup
2046                  * per queue in RXDCTL
2047                  */
2048                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2049                         rxq = dev->data->rx_queues[i];
2050                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2051                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2052                                 ctrl |= IXGBE_RXDCTL_VME;
2053                                 on = TRUE;
2054                         } else {
2055                                 ctrl &= ~IXGBE_RXDCTL_VME;
2056                                 on = FALSE;
2057                         }
2058                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2059
2060                         /* record those setting for HW strip per queue */
2061                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2062                 }
2063         }
2064 }
2065
2066 static int
2067 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2068 {
2069         if (mask & ETH_VLAN_STRIP_MASK) {
2070                 ixgbe_vlan_hw_strip_config(dev);
2071         }
2072
2073         if (mask & ETH_VLAN_FILTER_MASK) {
2074                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2075                         ixgbe_vlan_hw_filter_enable(dev);
2076                 else
2077                         ixgbe_vlan_hw_filter_disable(dev);
2078         }
2079
2080         if (mask & ETH_VLAN_EXTEND_MASK) {
2081                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2082                         ixgbe_vlan_hw_extend_enable(dev);
2083                 else
2084                         ixgbe_vlan_hw_extend_disable(dev);
2085         }
2086
2087         return 0;
2088 }
2089
2090 static void
2091 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2092 {
2093         struct ixgbe_hw *hw =
2094                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2096         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2097
2098         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2099         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2100 }
2101
2102 static int
2103 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2104 {
2105         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2106
2107         switch (nb_rx_q) {
2108         case 1:
2109         case 2:
2110                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2111                 break;
2112         case 4:
2113                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2114                 break;
2115         default:
2116                 return -EINVAL;
2117         }
2118
2119         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2120                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2121         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2122                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2123         return 0;
2124 }
2125
2126 static int
2127 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2128 {
2129         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2131         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2132         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2133
2134         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2135                 /* check multi-queue mode */
2136                 switch (dev_conf->rxmode.mq_mode) {
2137                 case ETH_MQ_RX_VMDQ_DCB:
2138                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2139                         break;
2140                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2141                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2142                         PMD_INIT_LOG(ERR, "SRIOV active,"
2143                                         " unsupported mq_mode rx %d.",
2144                                         dev_conf->rxmode.mq_mode);
2145                         return -EINVAL;
2146                 case ETH_MQ_RX_RSS:
2147                 case ETH_MQ_RX_VMDQ_RSS:
2148                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2149                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2150                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2151                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2152                                                 " invalid queue number"
2153                                                 " for VMDQ RSS, allowed"
2154                                                 " value are 1, 2 or 4.");
2155                                         return -EINVAL;
2156                                 }
2157                         break;
2158                 case ETH_MQ_RX_VMDQ_ONLY:
2159                 case ETH_MQ_RX_NONE:
2160                         /* if nothing mq mode configure, use default scheme */
2161                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2162                         break;
2163                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2164                         /* SRIOV only works in VMDq enable mode */
2165                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2166                                         " wrong mq_mode rx %d.",
2167                                         dev_conf->rxmode.mq_mode);
2168                         return -EINVAL;
2169                 }
2170
2171                 switch (dev_conf->txmode.mq_mode) {
2172                 case ETH_MQ_TX_VMDQ_DCB:
2173                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2174                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2175                         break;
2176                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2177                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2178                         break;
2179                 }
2180
2181                 /* check valid queue number */
2182                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2183                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2184                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2185                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2186                                         " must be less than or equal to %d.",
2187                                         nb_rx_q, nb_tx_q,
2188                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2189                         return -EINVAL;
2190                 }
2191         } else {
2192                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2193                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2194                                           " not supported.");
2195                         return -EINVAL;
2196                 }
2197                 /* check configuration for vmdb+dcb mode */
2198                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2199                         const struct rte_eth_vmdq_dcb_conf *conf;
2200
2201                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2202                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2203                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2204                                 return -EINVAL;
2205                         }
2206                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2207                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2208                                conf->nb_queue_pools == ETH_32_POOLS)) {
2209                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2210                                                 " nb_queue_pools must be %d or %d.",
2211                                                 ETH_16_POOLS, ETH_32_POOLS);
2212                                 return -EINVAL;
2213                         }
2214                 }
2215                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2216                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2217
2218                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2219                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2220                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2221                                 return -EINVAL;
2222                         }
2223                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2224                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2225                                conf->nb_queue_pools == ETH_32_POOLS)) {
2226                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2227                                                 " nb_queue_pools != %d and"
2228                                                 " nb_queue_pools != %d.",
2229                                                 ETH_16_POOLS, ETH_32_POOLS);
2230                                 return -EINVAL;
2231                         }
2232                 }
2233
2234                 /* For DCB mode check our configuration before we go further */
2235                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2236                         const struct rte_eth_dcb_rx_conf *conf;
2237
2238                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2239                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2240                                                  IXGBE_DCB_NB_QUEUES);
2241                                 return -EINVAL;
2242                         }
2243                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2244                         if (!(conf->nb_tcs == ETH_4_TCS ||
2245                                conf->nb_tcs == ETH_8_TCS)) {
2246                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2247                                                 " and nb_tcs != %d.",
2248                                                 ETH_4_TCS, ETH_8_TCS);
2249                                 return -EINVAL;
2250                         }
2251                 }
2252
2253                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2254                         const struct rte_eth_dcb_tx_conf *conf;
2255
2256                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2257                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2258                                                  IXGBE_DCB_NB_QUEUES);
2259                                 return -EINVAL;
2260                         }
2261                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2262                         if (!(conf->nb_tcs == ETH_4_TCS ||
2263                                conf->nb_tcs == ETH_8_TCS)) {
2264                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2265                                                 " and nb_tcs != %d.",
2266                                                 ETH_4_TCS, ETH_8_TCS);
2267                                 return -EINVAL;
2268                         }
2269                 }
2270
2271                 /*
2272                  * When DCB/VT is off, maximum number of queues changes,
2273                  * except for 82598EB, which remains constant.
2274                  */
2275                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2276                                 hw->mac.type != ixgbe_mac_82598EB) {
2277                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2278                                 PMD_INIT_LOG(ERR,
2279                                              "Neither VT nor DCB are enabled, "
2280                                              "nb_tx_q > %d.",
2281                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2282                                 return -EINVAL;
2283                         }
2284                 }
2285         }
2286         return 0;
2287 }
2288
2289 static int
2290 ixgbe_dev_configure(struct rte_eth_dev *dev)
2291 {
2292         struct ixgbe_interrupt *intr =
2293                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2294         struct ixgbe_adapter *adapter =
2295                 (struct ixgbe_adapter *)dev->data->dev_private;
2296         int ret;
2297
2298         PMD_INIT_FUNC_TRACE();
2299         /* multipe queue mode checking */
2300         ret  = ixgbe_check_mq_mode(dev);
2301         if (ret != 0) {
2302                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2303                             ret);
2304                 return ret;
2305         }
2306
2307         /* set flag to update link status after init */
2308         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2309
2310         /*
2311          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2312          * allocation or vector Rx preconditions we will reset it.
2313          */
2314         adapter->rx_bulk_alloc_allowed = true;
2315         adapter->rx_vec_allowed = true;
2316
2317         return 0;
2318 }
2319
2320 static void
2321 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2322 {
2323         struct ixgbe_hw *hw =
2324                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2325         struct ixgbe_interrupt *intr =
2326                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2327         uint32_t gpie;
2328
2329         /* only set up it on X550EM_X */
2330         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2331                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2332                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2333                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2334                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2335                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2336         }
2337 }
2338
2339 int
2340 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2341                         uint16_t tx_rate, uint64_t q_msk)
2342 {
2343         struct ixgbe_hw *hw;
2344         struct ixgbe_vf_info *vfinfo;
2345         struct rte_eth_link link;
2346         uint8_t  nb_q_per_pool;
2347         uint32_t queue_stride;
2348         uint32_t queue_idx, idx = 0, vf_idx;
2349         uint32_t queue_end;
2350         uint16_t total_rate = 0;
2351         struct rte_pci_device *pci_dev;
2352
2353         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2354         rte_eth_link_get_nowait(dev->data->port_id, &link);
2355
2356         if (vf >= pci_dev->max_vfs)
2357                 return -EINVAL;
2358
2359         if (tx_rate > link.link_speed)
2360                 return -EINVAL;
2361
2362         if (q_msk == 0)
2363                 return 0;
2364
2365         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2367         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2368         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2369         queue_idx = vf * queue_stride;
2370         queue_end = queue_idx + nb_q_per_pool - 1;
2371         if (queue_end >= hw->mac.max_tx_queues)
2372                 return -EINVAL;
2373
2374         if (vfinfo) {
2375                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2376                         if (vf_idx == vf)
2377                                 continue;
2378                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2379                                 idx++)
2380                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2381                 }
2382         } else {
2383                 return -EINVAL;
2384         }
2385
2386         /* Store tx_rate for this vf. */
2387         for (idx = 0; idx < nb_q_per_pool; idx++) {
2388                 if (((uint64_t)0x1 << idx) & q_msk) {
2389                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2390                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2391                         total_rate += tx_rate;
2392                 }
2393         }
2394
2395         if (total_rate > dev->data->dev_link.link_speed) {
2396                 /* Reset stored TX rate of the VF if it causes exceed
2397                  * link speed.
2398                  */
2399                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2400                 return -EINVAL;
2401         }
2402
2403         /* Set RTTBCNRC of each queue/pool for vf X  */
2404         for (; queue_idx <= queue_end; queue_idx++) {
2405                 if (0x1 & q_msk)
2406                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2407                 q_msk = q_msk >> 1;
2408         }
2409
2410         return 0;
2411 }
2412
2413 /*
2414  * Configure device link speed and setup link.
2415  * It returns 0 on success.
2416  */
2417 static int
2418 ixgbe_dev_start(struct rte_eth_dev *dev)
2419 {
2420         struct ixgbe_hw *hw =
2421                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2422         struct ixgbe_vf_info *vfinfo =
2423                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2424         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2425         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2426         uint32_t intr_vector = 0;
2427         int err, link_up = 0, negotiate = 0;
2428         uint32_t speed = 0;
2429         int mask = 0;
2430         int status;
2431         uint16_t vf, idx;
2432         uint32_t *link_speeds;
2433         struct ixgbe_tm_conf *tm_conf =
2434                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2435
2436         PMD_INIT_FUNC_TRACE();
2437
2438         /* IXGBE devices don't support:
2439         *    - half duplex (checked afterwards for valid speeds)
2440         *    - fixed speed: TODO implement
2441         */
2442         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2443                 PMD_INIT_LOG(ERR,
2444                 "Invalid link_speeds for port %u, fix speed not supported",
2445                                 dev->data->port_id);
2446                 return -EINVAL;
2447         }
2448
2449         /* disable uio/vfio intr/eventfd mapping */
2450         rte_intr_disable(intr_handle);
2451
2452         /* stop adapter */
2453         hw->adapter_stopped = 0;
2454         ixgbe_stop_adapter(hw);
2455
2456         /* reinitialize adapter
2457          * this calls reset and start
2458          */
2459         status = ixgbe_pf_reset_hw(hw);
2460         if (status != 0)
2461                 return -1;
2462         hw->mac.ops.start_hw(hw);
2463         hw->mac.get_link_status = true;
2464
2465         /* configure PF module if SRIOV enabled */
2466         ixgbe_pf_host_configure(dev);
2467
2468         ixgbe_dev_phy_intr_setup(dev);
2469
2470         /* check and configure queue intr-vector mapping */
2471         if ((rte_intr_cap_multiple(intr_handle) ||
2472              !RTE_ETH_DEV_SRIOV(dev).active) &&
2473             dev->data->dev_conf.intr_conf.rxq != 0) {
2474                 intr_vector = dev->data->nb_rx_queues;
2475                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2476                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2477                                         IXGBE_MAX_INTR_QUEUE_NUM);
2478                         return -ENOTSUP;
2479                 }
2480                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2481                         return -1;
2482         }
2483
2484         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2485                 intr_handle->intr_vec =
2486                         rte_zmalloc("intr_vec",
2487                                     dev->data->nb_rx_queues * sizeof(int), 0);
2488                 if (intr_handle->intr_vec == NULL) {
2489                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2490                                      " intr_vec", dev->data->nb_rx_queues);
2491                         return -ENOMEM;
2492                 }
2493         }
2494
2495         /* confiugre msix for sleep until rx interrupt */
2496         ixgbe_configure_msix(dev);
2497
2498         /* initialize transmission unit */
2499         ixgbe_dev_tx_init(dev);
2500
2501         /* This can fail when allocating mbufs for descriptor rings */
2502         err = ixgbe_dev_rx_init(dev);
2503         if (err) {
2504                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2505                 goto error;
2506         }
2507
2508         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2509                 ETH_VLAN_EXTEND_MASK;
2510         err = ixgbe_vlan_offload_set(dev, mask);
2511         if (err) {
2512                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2513                 goto error;
2514         }
2515
2516         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2517                 /* Enable vlan filtering for VMDq */
2518                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2519         }
2520
2521         /* Configure DCB hw */
2522         ixgbe_configure_dcb(dev);
2523
2524         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2525                 err = ixgbe_fdir_configure(dev);
2526                 if (err)
2527                         goto error;
2528         }
2529
2530         /* Restore vf rate limit */
2531         if (vfinfo != NULL) {
2532                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2533                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2534                                 if (vfinfo[vf].tx_rate[idx] != 0)
2535                                         ixgbe_set_vf_rate_limit(
2536                                                 dev, vf,
2537                                                 vfinfo[vf].tx_rate[idx],
2538                                                 1 << idx);
2539         }
2540
2541         ixgbe_restore_statistics_mapping(dev);
2542
2543         err = ixgbe_dev_rxtx_start(dev);
2544         if (err < 0) {
2545                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2546                 goto error;
2547         }
2548
2549         /* Skip link setup if loopback mode is enabled for 82599. */
2550         if (hw->mac.type == ixgbe_mac_82599EB &&
2551                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2552                 goto skip_link_setup;
2553
2554         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2555                 err = hw->mac.ops.setup_sfp(hw);
2556                 if (err)
2557                         goto error;
2558         }
2559
2560         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2561                 /* Turn on the copper */
2562                 ixgbe_set_phy_power(hw, true);
2563         } else {
2564                 /* Turn on the laser */
2565                 ixgbe_enable_tx_laser(hw);
2566         }
2567
2568         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2569         if (err)
2570                 goto error;
2571         dev->data->dev_link.link_status = link_up;
2572
2573         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2574         if (err)
2575                 goto error;
2576
2577         link_speeds = &dev->data->dev_conf.link_speeds;
2578         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2579                         ETH_LINK_SPEED_10G)) {
2580                 PMD_INIT_LOG(ERR, "Invalid link setting");
2581                 goto error;
2582         }
2583
2584         speed = 0x0;
2585         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2586                 switch (hw->mac.type) {
2587                 case ixgbe_mac_82598EB:
2588                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2589                         break;
2590                 case ixgbe_mac_82599EB:
2591                 case ixgbe_mac_X540:
2592                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2593                         break;
2594                 case ixgbe_mac_X550:
2595                 case ixgbe_mac_X550EM_x:
2596                 case ixgbe_mac_X550EM_a:
2597                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2598                         break;
2599                 default:
2600                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2601                 }
2602         } else {
2603                 if (*link_speeds & ETH_LINK_SPEED_10G)
2604                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2605                 if (*link_speeds & ETH_LINK_SPEED_1G)
2606                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2607                 if (*link_speeds & ETH_LINK_SPEED_100M)
2608                         speed |= IXGBE_LINK_SPEED_100_FULL;
2609         }
2610
2611         err = ixgbe_setup_link(hw, speed, link_up);
2612         if (err)
2613                 goto error;
2614
2615 skip_link_setup:
2616
2617         if (rte_intr_allow_others(intr_handle)) {
2618                 /* check if lsc interrupt is enabled */
2619                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2620                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2621                 else
2622                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2623                 ixgbe_dev_macsec_interrupt_setup(dev);
2624         } else {
2625                 rte_intr_callback_unregister(intr_handle,
2626                                              ixgbe_dev_interrupt_handler, dev);
2627                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2628                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2629                                      " no intr multiplex");
2630         }
2631
2632         /* check if rxq interrupt is enabled */
2633         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2634             rte_intr_dp_is_en(intr_handle))
2635                 ixgbe_dev_rxq_interrupt_setup(dev);
2636
2637         /* enable uio/vfio intr/eventfd mapping */
2638         rte_intr_enable(intr_handle);
2639
2640         /* resume enabled intr since hw reset */
2641         ixgbe_enable_intr(dev);
2642         ixgbe_l2_tunnel_conf(dev);
2643         ixgbe_filter_restore(dev);
2644
2645         if (tm_conf->root && !tm_conf->committed)
2646                 PMD_DRV_LOG(WARNING,
2647                             "please call hierarchy_commit() "
2648                             "before starting the port");
2649
2650         return 0;
2651
2652 error:
2653         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2654         ixgbe_dev_clear_queues(dev);
2655         return -EIO;
2656 }
2657
2658 /*
2659  * Stop device: disable rx and tx functions to allow for reconfiguring.
2660  */
2661 static void
2662 ixgbe_dev_stop(struct rte_eth_dev *dev)
2663 {
2664         struct rte_eth_link link;
2665         struct ixgbe_hw *hw =
2666                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2667         struct ixgbe_vf_info *vfinfo =
2668                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2669         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2670         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2671         int vf;
2672         struct ixgbe_tm_conf *tm_conf =
2673                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2674
2675         PMD_INIT_FUNC_TRACE();
2676
2677         /* disable interrupts */
2678         ixgbe_disable_intr(hw);
2679
2680         /* reset the NIC */
2681         ixgbe_pf_reset_hw(hw);
2682         hw->adapter_stopped = 0;
2683
2684         /* stop adapter */
2685         ixgbe_stop_adapter(hw);
2686
2687         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2688                 vfinfo[vf].clear_to_send = false;
2689
2690         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2691                 /* Turn off the copper */
2692                 ixgbe_set_phy_power(hw, false);
2693         } else {
2694                 /* Turn off the laser */
2695                 ixgbe_disable_tx_laser(hw);
2696         }
2697
2698         ixgbe_dev_clear_queues(dev);
2699
2700         /* Clear stored conf */
2701         dev->data->scattered_rx = 0;
2702         dev->data->lro = 0;
2703
2704         /* Clear recorded link status */
2705         memset(&link, 0, sizeof(link));
2706         rte_eth_linkstatus_set(dev, &link);
2707
2708         if (!rte_intr_allow_others(intr_handle))
2709                 /* resume to the default handler */
2710                 rte_intr_callback_register(intr_handle,
2711                                            ixgbe_dev_interrupt_handler,
2712                                            (void *)dev);
2713
2714         /* Clean datapath event and queue/vec mapping */
2715         rte_intr_efd_disable(intr_handle);
2716         if (intr_handle->intr_vec != NULL) {
2717                 rte_free(intr_handle->intr_vec);
2718                 intr_handle->intr_vec = NULL;
2719         }
2720
2721         /* reset hierarchy commit */
2722         tm_conf->committed = false;
2723 }
2724
2725 /*
2726  * Set device link up: enable tx.
2727  */
2728 static int
2729 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2730 {
2731         struct ixgbe_hw *hw =
2732                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2733         if (hw->mac.type == ixgbe_mac_82599EB) {
2734 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2735                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2736                         /* Not suported in bypass mode */
2737                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2738                                      "by device id 0x%x", hw->device_id);
2739                         return -ENOTSUP;
2740                 }
2741 #endif
2742         }
2743
2744         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2745                 /* Turn on the copper */
2746                 ixgbe_set_phy_power(hw, true);
2747         } else {
2748                 /* Turn on the laser */
2749                 ixgbe_enable_tx_laser(hw);
2750         }
2751
2752         return 0;
2753 }
2754
2755 /*
2756  * Set device link down: disable tx.
2757  */
2758 static int
2759 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2760 {
2761         struct ixgbe_hw *hw =
2762                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2763         if (hw->mac.type == ixgbe_mac_82599EB) {
2764 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2765                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2766                         /* Not suported in bypass mode */
2767                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2768                                      "by device id 0x%x", hw->device_id);
2769                         return -ENOTSUP;
2770                 }
2771 #endif
2772         }
2773
2774         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2775                 /* Turn off the copper */
2776                 ixgbe_set_phy_power(hw, false);
2777         } else {
2778                 /* Turn off the laser */
2779                 ixgbe_disable_tx_laser(hw);
2780         }
2781
2782         return 0;
2783 }
2784
2785 /*
2786  * Reset and stop device.
2787  */
2788 static void
2789 ixgbe_dev_close(struct rte_eth_dev *dev)
2790 {
2791         struct ixgbe_hw *hw =
2792                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2793
2794         PMD_INIT_FUNC_TRACE();
2795
2796         ixgbe_pf_reset_hw(hw);
2797
2798         ixgbe_dev_stop(dev);
2799         hw->adapter_stopped = 1;
2800
2801         ixgbe_dev_free_queues(dev);
2802
2803         ixgbe_disable_pcie_master(hw);
2804
2805         /* reprogram the RAR[0] in case user changed it. */
2806         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2807 }
2808
2809 /*
2810  * Reset PF device.
2811  */
2812 static int
2813 ixgbe_dev_reset(struct rte_eth_dev *dev)
2814 {
2815         int ret;
2816
2817         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2818          * its VF to make them align with it. The detailed notification
2819          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2820          * To avoid unexpected behavior in VF, currently reset of PF with
2821          * SR-IOV activation is not supported. It might be supported later.
2822          */
2823         if (dev->data->sriov.active)
2824                 return -ENOTSUP;
2825
2826         ret = eth_ixgbe_dev_uninit(dev);
2827         if (ret)
2828                 return ret;
2829
2830         ret = eth_ixgbe_dev_init(dev);
2831
2832         return ret;
2833 }
2834
2835 static void
2836 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2837                            struct ixgbe_hw_stats *hw_stats,
2838                            struct ixgbe_macsec_stats *macsec_stats,
2839                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2840                            uint64_t *total_qprc, uint64_t *total_qprdc)
2841 {
2842         uint32_t bprc, lxon, lxoff, total;
2843         uint32_t delta_gprc = 0;
2844         unsigned i;
2845         /* Workaround for RX byte count not including CRC bytes when CRC
2846          * strip is enabled. CRC bytes are removed from counters when crc_strip
2847          * is disabled.
2848          */
2849         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2850                         IXGBE_HLREG0_RXCRCSTRP);
2851
2852         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2853         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2854         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2855         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2856
2857         for (i = 0; i < 8; i++) {
2858                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2859
2860                 /* global total per queue */
2861                 hw_stats->mpc[i] += mp;
2862                 /* Running comprehensive total for stats display */
2863                 *total_missed_rx += hw_stats->mpc[i];
2864                 if (hw->mac.type == ixgbe_mac_82598EB) {
2865                         hw_stats->rnbc[i] +=
2866                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2867                         hw_stats->pxonrxc[i] +=
2868                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2869                         hw_stats->pxoffrxc[i] +=
2870                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2871                 } else {
2872                         hw_stats->pxonrxc[i] +=
2873                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2874                         hw_stats->pxoffrxc[i] +=
2875                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2876                         hw_stats->pxon2offc[i] +=
2877                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2878                 }
2879                 hw_stats->pxontxc[i] +=
2880                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2881                 hw_stats->pxofftxc[i] +=
2882                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2883         }
2884         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2885                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2886                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2887                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2888
2889                 delta_gprc += delta_qprc;
2890
2891                 hw_stats->qprc[i] += delta_qprc;
2892                 hw_stats->qptc[i] += delta_qptc;
2893
2894                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2895                 hw_stats->qbrc[i] +=
2896                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2897                 if (crc_strip == 0)
2898                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2899
2900                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2901                 hw_stats->qbtc[i] +=
2902                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2903
2904                 hw_stats->qprdc[i] += delta_qprdc;
2905                 *total_qprdc += hw_stats->qprdc[i];
2906
2907                 *total_qprc += hw_stats->qprc[i];
2908                 *total_qbrc += hw_stats->qbrc[i];
2909         }
2910         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2911         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2912         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2913
2914         /*
2915          * An errata states that gprc actually counts good + missed packets:
2916          * Workaround to set gprc to summated queue packet receives
2917          */
2918         hw_stats->gprc = *total_qprc;
2919
2920         if (hw->mac.type != ixgbe_mac_82598EB) {
2921                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2922                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2923                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2924                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2925                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2926                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2927                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2928                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2929         } else {
2930                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2931                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2932                 /* 82598 only has a counter in the high register */
2933                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2934                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2935                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2936         }
2937         uint64_t old_tpr = hw_stats->tpr;
2938
2939         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2940         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2941
2942         if (crc_strip == 0)
2943                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2944
2945         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2946         hw_stats->gptc += delta_gptc;
2947         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2948         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2949
2950         /*
2951          * Workaround: mprc hardware is incorrectly counting
2952          * broadcasts, so for now we subtract those.
2953          */
2954         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2955         hw_stats->bprc += bprc;
2956         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2957         if (hw->mac.type == ixgbe_mac_82598EB)
2958                 hw_stats->mprc -= bprc;
2959
2960         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2961         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2962         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2963         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2964         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2965         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2966
2967         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2968         hw_stats->lxontxc += lxon;
2969         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2970         hw_stats->lxofftxc += lxoff;
2971         total = lxon + lxoff;
2972
2973         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2974         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2975         hw_stats->gptc -= total;
2976         hw_stats->mptc -= total;
2977         hw_stats->ptc64 -= total;
2978         hw_stats->gotc -= total * ETHER_MIN_LEN;
2979
2980         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2981         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2982         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2983         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2984         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2985         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2986         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2987         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2988         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2989         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2990         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2991         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2992         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2993         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2994         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2995         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2996         /* Only read FCOE on 82599 */
2997         if (hw->mac.type != ixgbe_mac_82598EB) {
2998                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2999                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3000                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3001                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3002                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3003         }
3004
3005         /* Flow Director Stats registers */
3006         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3007         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3008
3009         /* MACsec Stats registers */
3010         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3011         macsec_stats->out_pkts_encrypted +=
3012                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3013         macsec_stats->out_pkts_protected +=
3014                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3015         macsec_stats->out_octets_encrypted +=
3016                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3017         macsec_stats->out_octets_protected +=
3018                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3019         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3020         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3021         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3022         macsec_stats->in_pkts_unknownsci +=
3023                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3024         macsec_stats->in_octets_decrypted +=
3025                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3026         macsec_stats->in_octets_validated +=
3027                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3028         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3029         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3030         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3031         for (i = 0; i < 2; i++) {
3032                 macsec_stats->in_pkts_ok +=
3033                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3034                 macsec_stats->in_pkts_invalid +=
3035                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3036                 macsec_stats->in_pkts_notvalid +=
3037                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3038         }
3039         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3040         macsec_stats->in_pkts_notusingsa +=
3041                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3042 }
3043
3044 /*
3045  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3046  */
3047 static int
3048 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3049 {
3050         struct ixgbe_hw *hw =
3051                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3052         struct ixgbe_hw_stats *hw_stats =
3053                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3054         struct ixgbe_macsec_stats *macsec_stats =
3055                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3056                                 dev->data->dev_private);
3057         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3058         unsigned i;
3059
3060         total_missed_rx = 0;
3061         total_qbrc = 0;
3062         total_qprc = 0;
3063         total_qprdc = 0;
3064
3065         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3066                         &total_qbrc, &total_qprc, &total_qprdc);
3067
3068         if (stats == NULL)
3069                 return -EINVAL;
3070
3071         /* Fill out the rte_eth_stats statistics structure */
3072         stats->ipackets = total_qprc;
3073         stats->ibytes = total_qbrc;
3074         stats->opackets = hw_stats->gptc;
3075         stats->obytes = hw_stats->gotc;
3076
3077         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3078                 stats->q_ipackets[i] = hw_stats->qprc[i];
3079                 stats->q_opackets[i] = hw_stats->qptc[i];
3080                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3081                 stats->q_obytes[i] = hw_stats->qbtc[i];
3082                 stats->q_errors[i] = hw_stats->qprdc[i];
3083         }
3084
3085         /* Rx Errors */
3086         stats->imissed  = total_missed_rx;
3087         stats->ierrors  = hw_stats->crcerrs +
3088                           hw_stats->mspdc +
3089                           hw_stats->rlec +
3090                           hw_stats->ruc +
3091                           hw_stats->roc +
3092                           hw_stats->illerrc +
3093                           hw_stats->errbc +
3094                           hw_stats->rfc +
3095                           hw_stats->fccrc +
3096                           hw_stats->fclast;
3097
3098         /* Tx Errors */
3099         stats->oerrors  = 0;
3100         return 0;
3101 }
3102
3103 static void
3104 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3105 {
3106         struct ixgbe_hw_stats *stats =
3107                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3108
3109         /* HW registers are cleared on read */
3110         ixgbe_dev_stats_get(dev, NULL);
3111
3112         /* Reset software totals */
3113         memset(stats, 0, sizeof(*stats));
3114 }
3115
3116 /* This function calculates the number of xstats based on the current config */
3117 static unsigned
3118 ixgbe_xstats_calc_num(void) {
3119         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3120                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3121                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3122 }
3123
3124 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3125         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3126 {
3127         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3128         unsigned stat, i, count;
3129
3130         if (xstats_names != NULL) {
3131                 count = 0;
3132
3133                 /* Note: limit >= cnt_stats checked upstream
3134                  * in rte_eth_xstats_names()
3135                  */
3136
3137                 /* Extended stats from ixgbe_hw_stats */
3138                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3139                         snprintf(xstats_names[count].name,
3140                                 sizeof(xstats_names[count].name),
3141                                 "%s",
3142                                 rte_ixgbe_stats_strings[i].name);
3143                         count++;
3144                 }
3145
3146                 /* MACsec Stats */
3147                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3148                         snprintf(xstats_names[count].name,
3149                                 sizeof(xstats_names[count].name),
3150                                 "%s",
3151                                 rte_ixgbe_macsec_strings[i].name);
3152                         count++;
3153                 }
3154
3155                 /* RX Priority Stats */
3156                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3157                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3158                                 snprintf(xstats_names[count].name,
3159                                         sizeof(xstats_names[count].name),
3160                                         "rx_priority%u_%s", i,
3161                                         rte_ixgbe_rxq_strings[stat].name);
3162                                 count++;
3163                         }
3164                 }
3165
3166                 /* TX Priority Stats */
3167                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3168                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3169                                 snprintf(xstats_names[count].name,
3170                                         sizeof(xstats_names[count].name),
3171                                         "tx_priority%u_%s", i,
3172                                         rte_ixgbe_txq_strings[stat].name);
3173                                 count++;
3174                         }
3175                 }
3176         }
3177         return cnt_stats;
3178 }
3179
3180 static int ixgbe_dev_xstats_get_names_by_id(
3181         struct rte_eth_dev *dev,
3182         struct rte_eth_xstat_name *xstats_names,
3183         const uint64_t *ids,
3184         unsigned int limit)
3185 {
3186         if (!ids) {
3187                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3188                 unsigned int stat, i, count;
3189
3190                 if (xstats_names != NULL) {
3191                         count = 0;
3192
3193                         /* Note: limit >= cnt_stats checked upstream
3194                          * in rte_eth_xstats_names()
3195                          */
3196
3197                         /* Extended stats from ixgbe_hw_stats */
3198                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3199                                 snprintf(xstats_names[count].name,
3200                                         sizeof(xstats_names[count].name),
3201                                         "%s",
3202                                         rte_ixgbe_stats_strings[i].name);
3203                                 count++;
3204                         }
3205
3206                         /* MACsec Stats */
3207                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3208                                 snprintf(xstats_names[count].name,
3209                                         sizeof(xstats_names[count].name),
3210                                         "%s",
3211                                         rte_ixgbe_macsec_strings[i].name);
3212                                 count++;
3213                         }
3214
3215                         /* RX Priority Stats */
3216                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3217                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3218                                         snprintf(xstats_names[count].name,
3219                                             sizeof(xstats_names[count].name),
3220                                             "rx_priority%u_%s", i,
3221                                             rte_ixgbe_rxq_strings[stat].name);
3222                                         count++;
3223                                 }
3224                         }
3225
3226                         /* TX Priority Stats */
3227                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3228                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3229                                         snprintf(xstats_names[count].name,
3230                                             sizeof(xstats_names[count].name),
3231                                             "tx_priority%u_%s", i,
3232                                             rte_ixgbe_txq_strings[stat].name);
3233                                         count++;
3234                                 }
3235                         }
3236                 }
3237                 return cnt_stats;
3238         }
3239
3240         uint16_t i;
3241         uint16_t size = ixgbe_xstats_calc_num();
3242         struct rte_eth_xstat_name xstats_names_copy[size];
3243
3244         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3245                         size);
3246
3247         for (i = 0; i < limit; i++) {
3248                 if (ids[i] >= size) {
3249                         PMD_INIT_LOG(ERR, "id value isn't valid");
3250                         return -1;
3251                 }
3252                 strcpy(xstats_names[i].name,
3253                                 xstats_names_copy[ids[i]].name);
3254         }
3255         return limit;
3256 }
3257
3258 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3259         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3260 {
3261         unsigned i;
3262
3263         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3264                 return -ENOMEM;
3265
3266         if (xstats_names != NULL)
3267                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3268                         snprintf(xstats_names[i].name,
3269                                 sizeof(xstats_names[i].name),
3270                                 "%s", rte_ixgbevf_stats_strings[i].name);
3271         return IXGBEVF_NB_XSTATS;
3272 }
3273
3274 static int
3275 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3276                                          unsigned n)
3277 {
3278         struct ixgbe_hw *hw =
3279                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3280         struct ixgbe_hw_stats *hw_stats =
3281                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3282         struct ixgbe_macsec_stats *macsec_stats =
3283                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3284                                 dev->data->dev_private);
3285         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3286         unsigned i, stat, count = 0;
3287
3288         count = ixgbe_xstats_calc_num();
3289
3290         if (n < count)
3291                 return count;
3292
3293         total_missed_rx = 0;
3294         total_qbrc = 0;
3295         total_qprc = 0;
3296         total_qprdc = 0;
3297
3298         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3299                         &total_qbrc, &total_qprc, &total_qprdc);
3300
3301         /* If this is a reset xstats is NULL, and we have cleared the
3302          * registers by reading them.
3303          */
3304         if (!xstats)
3305                 return 0;
3306
3307         /* Extended stats from ixgbe_hw_stats */
3308         count = 0;
3309         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3310                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3311                                 rte_ixgbe_stats_strings[i].offset);
3312                 xstats[count].id = count;
3313                 count++;
3314         }
3315
3316         /* MACsec Stats */
3317         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3318                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3319                                 rte_ixgbe_macsec_strings[i].offset);
3320                 xstats[count].id = count;
3321                 count++;
3322         }
3323
3324         /* RX Priority Stats */
3325         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3326                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3327                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3328                                         rte_ixgbe_rxq_strings[stat].offset +
3329                                         (sizeof(uint64_t) * i));
3330                         xstats[count].id = count;
3331                         count++;
3332                 }
3333         }
3334
3335         /* TX Priority Stats */
3336         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3337                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3338                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3339                                         rte_ixgbe_txq_strings[stat].offset +
3340                                         (sizeof(uint64_t) * i));
3341                         xstats[count].id = count;
3342                         count++;
3343                 }
3344         }
3345         return count;
3346 }
3347
3348 static int
3349 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3350                 uint64_t *values, unsigned int n)
3351 {
3352         if (!ids) {
3353                 struct ixgbe_hw *hw =
3354                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3355                 struct ixgbe_hw_stats *hw_stats =
3356                                 IXGBE_DEV_PRIVATE_TO_STATS(
3357                                                 dev->data->dev_private);
3358                 struct ixgbe_macsec_stats *macsec_stats =
3359                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3360                                         dev->data->dev_private);
3361                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3362                 unsigned int i, stat, count = 0;
3363
3364                 count = ixgbe_xstats_calc_num();
3365
3366                 if (!ids && n < count)
3367                         return count;
3368
3369                 total_missed_rx = 0;
3370                 total_qbrc = 0;
3371                 total_qprc = 0;
3372                 total_qprdc = 0;
3373
3374                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3375                                 &total_missed_rx, &total_qbrc, &total_qprc,
3376                                 &total_qprdc);
3377
3378                 /* If this is a reset xstats is NULL, and we have cleared the
3379                  * registers by reading them.
3380                  */
3381                 if (!ids && !values)
3382                         return 0;
3383
3384                 /* Extended stats from ixgbe_hw_stats */
3385                 count = 0;
3386                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3387                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3388                                         rte_ixgbe_stats_strings[i].offset);
3389                         count++;
3390                 }
3391
3392                 /* MACsec Stats */
3393                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3394                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3395                                         rte_ixgbe_macsec_strings[i].offset);
3396                         count++;
3397                 }
3398
3399                 /* RX Priority Stats */
3400                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3401                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3402                                 values[count] =
3403                                         *(uint64_t *)(((char *)hw_stats) +
3404                                         rte_ixgbe_rxq_strings[stat].offset +
3405                                         (sizeof(uint64_t) * i));
3406                                 count++;
3407                         }
3408                 }
3409
3410                 /* TX Priority Stats */
3411                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3412                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3413                                 values[count] =
3414                                         *(uint64_t *)(((char *)hw_stats) +
3415                                         rte_ixgbe_txq_strings[stat].offset +
3416                                         (sizeof(uint64_t) * i));
3417                                 count++;
3418                         }
3419                 }
3420                 return count;
3421         }
3422
3423         uint16_t i;
3424         uint16_t size = ixgbe_xstats_calc_num();
3425         uint64_t values_copy[size];
3426
3427         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3428
3429         for (i = 0; i < n; i++) {
3430                 if (ids[i] >= size) {
3431                         PMD_INIT_LOG(ERR, "id value isn't valid");
3432                         return -1;
3433                 }
3434                 values[i] = values_copy[ids[i]];
3435         }
3436         return n;
3437 }
3438
3439 static void
3440 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3441 {
3442         struct ixgbe_hw_stats *stats =
3443                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3444         struct ixgbe_macsec_stats *macsec_stats =
3445                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3446                                 dev->data->dev_private);
3447
3448         unsigned count = ixgbe_xstats_calc_num();
3449
3450         /* HW registers are cleared on read */
3451         ixgbe_dev_xstats_get(dev, NULL, count);
3452
3453         /* Reset software totals */
3454         memset(stats, 0, sizeof(*stats));
3455         memset(macsec_stats, 0, sizeof(*macsec_stats));
3456 }
3457
3458 static void
3459 ixgbevf_update_stats(struct rte_eth_dev *dev)
3460 {
3461         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3463                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3464
3465         /* Good Rx packet, include VF loopback */
3466         UPDATE_VF_STAT(IXGBE_VFGPRC,
3467             hw_stats->last_vfgprc, hw_stats->vfgprc);
3468
3469         /* Good Rx octets, include VF loopback */
3470         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3471             hw_stats->last_vfgorc, hw_stats->vfgorc);
3472
3473         /* Good Tx packet, include VF loopback */
3474         UPDATE_VF_STAT(IXGBE_VFGPTC,
3475             hw_stats->last_vfgptc, hw_stats->vfgptc);
3476
3477         /* Good Tx octets, include VF loopback */
3478         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3479             hw_stats->last_vfgotc, hw_stats->vfgotc);
3480
3481         /* Rx Multicst Packet */
3482         UPDATE_VF_STAT(IXGBE_VFMPRC,
3483             hw_stats->last_vfmprc, hw_stats->vfmprc);
3484 }
3485
3486 static int
3487 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3488                        unsigned n)
3489 {
3490         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3491                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3492         unsigned i;
3493
3494         if (n < IXGBEVF_NB_XSTATS)
3495                 return IXGBEVF_NB_XSTATS;
3496
3497         ixgbevf_update_stats(dev);
3498
3499         if (!xstats)
3500                 return 0;
3501
3502         /* Extended stats */
3503         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3504                 xstats[i].id = i;
3505                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3506                         rte_ixgbevf_stats_strings[i].offset);
3507         }
3508
3509         return IXGBEVF_NB_XSTATS;
3510 }
3511
3512 static int
3513 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3514 {
3515         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3516                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3517
3518         ixgbevf_update_stats(dev);
3519
3520         if (stats == NULL)
3521                 return -EINVAL;
3522
3523         stats->ipackets = hw_stats->vfgprc;
3524         stats->ibytes = hw_stats->vfgorc;
3525         stats->opackets = hw_stats->vfgptc;
3526         stats->obytes = hw_stats->vfgotc;
3527         return 0;
3528 }
3529
3530 static void
3531 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3532 {
3533         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3534                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3535
3536         /* Sync HW register to the last stats */
3537         ixgbevf_dev_stats_get(dev, NULL);
3538
3539         /* reset HW current stats*/
3540         hw_stats->vfgprc = 0;
3541         hw_stats->vfgorc = 0;
3542         hw_stats->vfgptc = 0;
3543         hw_stats->vfgotc = 0;
3544 }
3545
3546 static int
3547 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3548 {
3549         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3550         u16 eeprom_verh, eeprom_verl;
3551         u32 etrack_id;
3552         int ret;
3553
3554         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3555         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3556
3557         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3558         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3559
3560         ret += 1; /* add the size of '\0' */
3561         if (fw_size < (u32)ret)
3562                 return ret;
3563         else
3564                 return 0;
3565 }
3566
3567 static void
3568 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3569 {
3570         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3571         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3573
3574         dev_info->pci_dev = pci_dev;
3575         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3576         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3577         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3578                 /*
3579                  * When DCB/VT is off, maximum number of queues changes,
3580                  * except for 82598EB, which remains constant.
3581                  */
3582                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3583                                 hw->mac.type != ixgbe_mac_82598EB)
3584                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3585         }
3586         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3587         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3588         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3589         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3590         dev_info->max_vfs = pci_dev->max_vfs;
3591         if (hw->mac.type == ixgbe_mac_82598EB)
3592                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3593         else
3594                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3595         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3596         dev_info->rx_offload_capa =
3597                 DEV_RX_OFFLOAD_VLAN_STRIP |
3598                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3599                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3600                 DEV_RX_OFFLOAD_TCP_CKSUM  |
3601                 DEV_RX_OFFLOAD_CRC_STRIP;
3602
3603         /*
3604          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3605          * mode.
3606          */
3607         if ((hw->mac.type == ixgbe_mac_82599EB ||
3608              hw->mac.type == ixgbe_mac_X540) &&
3609             !RTE_ETH_DEV_SRIOV(dev).active)
3610                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3611
3612         if (hw->mac.type == ixgbe_mac_82599EB ||
3613             hw->mac.type == ixgbe_mac_X540)
3614                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3615
3616         if (hw->mac.type == ixgbe_mac_X550 ||
3617             hw->mac.type == ixgbe_mac_X550EM_x ||
3618             hw->mac.type == ixgbe_mac_X550EM_a)
3619                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3620
3621         dev_info->tx_offload_capa =
3622                 DEV_TX_OFFLOAD_VLAN_INSERT |
3623                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3624                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3625                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3626                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3627                 DEV_TX_OFFLOAD_TCP_TSO;
3628
3629         if (hw->mac.type == ixgbe_mac_82599EB ||
3630             hw->mac.type == ixgbe_mac_X540)
3631                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3632
3633         if (hw->mac.type == ixgbe_mac_X550 ||
3634             hw->mac.type == ixgbe_mac_X550EM_x ||
3635             hw->mac.type == ixgbe_mac_X550EM_a)
3636                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3637
3638 #ifdef RTE_LIBRTE_SECURITY
3639         if (dev->security_ctx) {
3640                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3641                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3642         }
3643 #endif
3644
3645         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3646                 .rx_thresh = {
3647                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3648                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3649                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3650                 },
3651                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3652                 .rx_drop_en = 0,
3653         };
3654
3655         dev_info->default_txconf = (struct rte_eth_txconf) {
3656                 .tx_thresh = {
3657                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3658                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3659                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3660                 },
3661                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3662                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3663                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3664                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3665         };
3666
3667         dev_info->rx_desc_lim = rx_desc_lim;
3668         dev_info->tx_desc_lim = tx_desc_lim;
3669
3670         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3671         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3672         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3673
3674         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3675         if (hw->mac.type == ixgbe_mac_X540 ||
3676             hw->mac.type == ixgbe_mac_X540_vf ||
3677             hw->mac.type == ixgbe_mac_X550 ||
3678             hw->mac.type == ixgbe_mac_X550_vf) {
3679                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3680         }
3681         if (hw->mac.type == ixgbe_mac_X550) {
3682                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3683                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3684         }
3685 }
3686
3687 static const uint32_t *
3688 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3689 {
3690         static const uint32_t ptypes[] = {
3691                 /* For non-vec functions,
3692                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3693                  * for vec functions,
3694                  * refers to _recv_raw_pkts_vec().
3695                  */
3696                 RTE_PTYPE_L2_ETHER,
3697                 RTE_PTYPE_L3_IPV4,
3698                 RTE_PTYPE_L3_IPV4_EXT,
3699                 RTE_PTYPE_L3_IPV6,
3700                 RTE_PTYPE_L3_IPV6_EXT,
3701                 RTE_PTYPE_L4_SCTP,
3702                 RTE_PTYPE_L4_TCP,
3703                 RTE_PTYPE_L4_UDP,
3704                 RTE_PTYPE_TUNNEL_IP,
3705                 RTE_PTYPE_INNER_L3_IPV6,
3706                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3707                 RTE_PTYPE_INNER_L4_TCP,
3708                 RTE_PTYPE_INNER_L4_UDP,
3709                 RTE_PTYPE_UNKNOWN
3710         };
3711
3712         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3713             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3714             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3715             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3716                 return ptypes;
3717
3718 #if defined(RTE_ARCH_X86)
3719         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3720             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3721                 return ptypes;
3722 #endif
3723         return NULL;
3724 }
3725
3726 static void
3727 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3728                      struct rte_eth_dev_info *dev_info)
3729 {
3730         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3732
3733         dev_info->pci_dev = pci_dev;
3734         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3735         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3736         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3737         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3738         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3739         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3740         dev_info->max_vfs = pci_dev->max_vfs;
3741         if (hw->mac.type == ixgbe_mac_82598EB)
3742                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3743         else
3744                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3745         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3746                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3747                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3748                                 DEV_RX_OFFLOAD_TCP_CKSUM  |
3749                                 DEV_RX_OFFLOAD_CRC_STRIP;
3750         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3751                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3752                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3753                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3754                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3755                                 DEV_TX_OFFLOAD_TCP_TSO;
3756
3757         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3758                 .rx_thresh = {
3759                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3760                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3761                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3762                 },
3763                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3764                 .rx_drop_en = 0,
3765         };
3766
3767         dev_info->default_txconf = (struct rte_eth_txconf) {
3768                 .tx_thresh = {
3769                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3770                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3771                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3772                 },
3773                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3774                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3775                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3776                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3777         };
3778
3779         dev_info->rx_desc_lim = rx_desc_lim;
3780         dev_info->tx_desc_lim = tx_desc_lim;
3781 }
3782
3783 static int
3784 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3785                    int *link_up, int wait_to_complete)
3786 {
3787         /**
3788          * for a quick link status checking, wait_to_compelet == 0,
3789          * skip PF link status checking
3790          */
3791         bool no_pflink_check = wait_to_complete == 0;
3792         struct ixgbe_mbx_info *mbx = &hw->mbx;
3793         struct ixgbe_mac_info *mac = &hw->mac;
3794         uint32_t links_reg, in_msg;
3795         int ret_val = 0;
3796
3797         /* If we were hit with a reset drop the link */
3798         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3799                 mac->get_link_status = true;
3800
3801         if (!mac->get_link_status)
3802                 goto out;
3803
3804         /* if link status is down no point in checking to see if pf is up */
3805         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3806         if (!(links_reg & IXGBE_LINKS_UP))
3807                 goto out;
3808
3809         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3810          * before the link status is correct
3811          */
3812         if (mac->type == ixgbe_mac_82599_vf) {
3813                 int i;
3814
3815                 for (i = 0; i < 5; i++) {
3816                         rte_delay_us(100);
3817                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3818
3819                         if (!(links_reg & IXGBE_LINKS_UP))
3820                                 goto out;
3821                 }
3822         }
3823
3824         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3825         case IXGBE_LINKS_SPEED_10G_82599:
3826                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3827                 if (hw->mac.type >= ixgbe_mac_X550) {
3828                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3829                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3830                 }
3831                 break;
3832         case IXGBE_LINKS_SPEED_1G_82599:
3833                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3834                 break;
3835         case IXGBE_LINKS_SPEED_100_82599:
3836                 *speed = IXGBE_LINK_SPEED_100_FULL;
3837                 if (hw->mac.type == ixgbe_mac_X550) {
3838                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3839                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3840                 }
3841                 break;
3842         case IXGBE_LINKS_SPEED_10_X550EM_A:
3843                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3844                 /* Since Reserved in older MAC's */
3845                 if (hw->mac.type >= ixgbe_mac_X550)
3846                         *speed = IXGBE_LINK_SPEED_10_FULL;
3847                 break;
3848         default:
3849                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3850         }
3851
3852         if (no_pflink_check) {
3853                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3854                         mac->get_link_status = true;
3855                 else
3856                         mac->get_link_status = false;
3857
3858                 goto out;
3859         }
3860         /* if the read failed it could just be a mailbox collision, best wait
3861          * until we are called again and don't report an error
3862          */
3863         if (mbx->ops.read(hw, &in_msg, 1, 0))
3864                 goto out;
3865
3866         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3867                 /* msg is not CTS and is NACK we must have lost CTS status */
3868                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3869                         ret_val = -1;
3870                 goto out;
3871         }
3872
3873         /* the pf is talking, if we timed out in the past we reinit */
3874         if (!mbx->timeout) {
3875                 ret_val = -1;
3876                 goto out;
3877         }
3878
3879         /* if we passed all the tests above then the link is up and we no
3880          * longer need to check for link
3881          */
3882         mac->get_link_status = false;
3883
3884 out:
3885         *link_up = !mac->get_link_status;
3886         return ret_val;
3887 }
3888
3889 /* return 0 means link status changed, -1 means not changed */
3890 static int
3891 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3892                             int wait_to_complete, int vf)
3893 {
3894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3895         struct rte_eth_link link;
3896         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3897         struct ixgbe_interrupt *intr =
3898                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3899         int link_up;
3900         int diag;
3901         u32 speed = 0;
3902         int wait = 1;
3903         bool autoneg = false;
3904
3905         memset(&link, 0, sizeof(link));
3906         link.link_status = ETH_LINK_DOWN;
3907         link.link_speed = 0;
3908         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3909         link.link_autoneg = ETH_LINK_AUTONEG;
3910
3911         hw->mac.get_link_status = true;
3912
3913         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3914                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3915                 speed = hw->phy.autoneg_advertised;
3916                 if (!speed)
3917                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3918                 ixgbe_setup_link(hw, speed, true);
3919         }
3920
3921         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3922         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3923                 wait = 0;
3924
3925         if (vf)
3926                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3927         else
3928                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3929
3930         if (diag != 0) {
3931                 link.link_speed = ETH_SPEED_NUM_100M;
3932                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3933                 return rte_eth_linkstatus_set(dev, &link);
3934         }
3935
3936         if (link_up == 0) {
3937                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3938                 return rte_eth_linkstatus_set(dev, &link);
3939         }
3940
3941         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3942         link.link_status = ETH_LINK_UP;
3943         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3944
3945         switch (link_speed) {
3946         default:
3947         case IXGBE_LINK_SPEED_UNKNOWN:
3948                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3949                 link.link_speed = ETH_SPEED_NUM_100M;
3950                 break;
3951
3952         case IXGBE_LINK_SPEED_100_FULL:
3953                 link.link_speed = ETH_SPEED_NUM_100M;
3954                 break;
3955
3956         case IXGBE_LINK_SPEED_1GB_FULL:
3957                 link.link_speed = ETH_SPEED_NUM_1G;
3958                 break;
3959
3960         case IXGBE_LINK_SPEED_2_5GB_FULL:
3961                 link.link_speed = ETH_SPEED_NUM_2_5G;
3962                 break;
3963
3964         case IXGBE_LINK_SPEED_5GB_FULL:
3965                 link.link_speed = ETH_SPEED_NUM_5G;
3966                 break;
3967
3968         case IXGBE_LINK_SPEED_10GB_FULL:
3969                 link.link_speed = ETH_SPEED_NUM_10G;
3970                 break;
3971         }
3972
3973         return rte_eth_linkstatus_set(dev, &link);
3974 }
3975
3976 static int
3977 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3978 {
3979         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3980 }
3981
3982 static int
3983 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3984 {
3985         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3986 }
3987
3988 static void
3989 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3990 {
3991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3992         uint32_t fctrl;
3993
3994         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3995         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3996         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3997 }
3998
3999 static void
4000 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4001 {
4002         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4003         uint32_t fctrl;
4004
4005         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4006         fctrl &= (~IXGBE_FCTRL_UPE);
4007         if (dev->data->all_multicast == 1)
4008                 fctrl |= IXGBE_FCTRL_MPE;
4009         else
4010                 fctrl &= (~IXGBE_FCTRL_MPE);
4011         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4012 }
4013
4014 static void
4015 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4016 {
4017         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4018         uint32_t fctrl;
4019
4020         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4021         fctrl |= IXGBE_FCTRL_MPE;
4022         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4023 }
4024
4025 static void
4026 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4027 {
4028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4029         uint32_t fctrl;
4030
4031         if (dev->data->promiscuous == 1)
4032                 return; /* must remain in all_multicast mode */
4033
4034         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4035         fctrl &= (~IXGBE_FCTRL_MPE);
4036         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4037 }
4038
4039 /**
4040  * It clears the interrupt causes and enables the interrupt.
4041  * It will be called once only during nic initialized.
4042  *
4043  * @param dev
4044  *  Pointer to struct rte_eth_dev.
4045  * @param on
4046  *  Enable or Disable.
4047  *
4048  * @return
4049  *  - On success, zero.
4050  *  - On failure, a negative value.
4051  */
4052 static int
4053 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4054 {
4055         struct ixgbe_interrupt *intr =
4056                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4057
4058         ixgbe_dev_link_status_print(dev);
4059         if (on)
4060                 intr->mask |= IXGBE_EICR_LSC;
4061         else
4062                 intr->mask &= ~IXGBE_EICR_LSC;
4063
4064         return 0;
4065 }
4066
4067 /**
4068  * It clears the interrupt causes and enables the interrupt.
4069  * It will be called once only during nic initialized.
4070  *
4071  * @param dev
4072  *  Pointer to struct rte_eth_dev.
4073  *
4074  * @return
4075  *  - On success, zero.
4076  *  - On failure, a negative value.
4077  */
4078 static int
4079 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4080 {
4081         struct ixgbe_interrupt *intr =
4082                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4083
4084         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4085
4086         return 0;
4087 }
4088
4089 /**
4090  * It clears the interrupt causes and enables the interrupt.
4091  * It will be called once only during nic initialized.
4092  *
4093  * @param dev
4094  *  Pointer to struct rte_eth_dev.
4095  *
4096  * @return
4097  *  - On success, zero.
4098  *  - On failure, a negative value.
4099  */
4100 static int
4101 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4102 {
4103         struct ixgbe_interrupt *intr =
4104                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4105
4106         intr->mask |= IXGBE_EICR_LINKSEC;
4107
4108         return 0;
4109 }
4110
4111 /*
4112  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4113  *
4114  * @param dev
4115  *  Pointer to struct rte_eth_dev.
4116  *
4117  * @return
4118  *  - On success, zero.
4119  *  - On failure, a negative value.
4120  */
4121 static int
4122 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4123 {
4124         uint32_t eicr;
4125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4126         struct ixgbe_interrupt *intr =
4127                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4128
4129         /* clear all cause mask */
4130         ixgbe_disable_intr(hw);
4131
4132         /* read-on-clear nic registers here */
4133         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4134         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4135
4136         intr->flags = 0;
4137
4138         /* set flag for async link update */
4139         if (eicr & IXGBE_EICR_LSC)
4140                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4141
4142         if (eicr & IXGBE_EICR_MAILBOX)
4143                 intr->flags |= IXGBE_FLAG_MAILBOX;
4144
4145         if (eicr & IXGBE_EICR_LINKSEC)
4146                 intr->flags |= IXGBE_FLAG_MACSEC;
4147
4148         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4149             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4150             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4151                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4152
4153         return 0;
4154 }
4155
4156 /**
4157  * It gets and then prints the link status.
4158  *
4159  * @param dev
4160  *  Pointer to struct rte_eth_dev.
4161  *
4162  * @return
4163  *  - On success, zero.
4164  *  - On failure, a negative value.
4165  */
4166 static void
4167 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4168 {
4169         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4170         struct rte_eth_link link;
4171
4172         rte_eth_linkstatus_get(dev, &link);
4173
4174         if (link.link_status) {
4175                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4176                                         (int)(dev->data->port_id),
4177                                         (unsigned)link.link_speed,
4178                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4179                                         "full-duplex" : "half-duplex");
4180         } else {
4181                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4182                                 (int)(dev->data->port_id));
4183         }
4184         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4185                                 pci_dev->addr.domain,
4186                                 pci_dev->addr.bus,
4187                                 pci_dev->addr.devid,
4188                                 pci_dev->addr.function);
4189 }
4190
4191 /*
4192  * It executes link_update after knowing an interrupt occurred.
4193  *
4194  * @param dev
4195  *  Pointer to struct rte_eth_dev.
4196  *
4197  * @return
4198  *  - On success, zero.
4199  *  - On failure, a negative value.
4200  */
4201 static int
4202 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4203                            struct rte_intr_handle *intr_handle)
4204 {
4205         struct ixgbe_interrupt *intr =
4206                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4207         int64_t timeout;
4208         struct ixgbe_hw *hw =
4209                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4210
4211         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4212
4213         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4214                 ixgbe_pf_mbx_process(dev);
4215                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4216         }
4217
4218         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4219                 ixgbe_handle_lasi(hw);
4220                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4221         }
4222
4223         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4224                 struct rte_eth_link link;
4225
4226                 /* get the link status before link update, for predicting later */
4227                 rte_eth_linkstatus_get(dev, &link);
4228
4229                 ixgbe_dev_link_update(dev, 0);
4230
4231                 /* likely to up */
4232                 if (!link.link_status)
4233                         /* handle it 1 sec later, wait it being stable */
4234                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4235                 /* likely to down */
4236                 else
4237                         /* handle it 4 sec later, wait it being stable */
4238                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4239
4240                 ixgbe_dev_link_status_print(dev);
4241                 if (rte_eal_alarm_set(timeout * 1000,
4242                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4243                         PMD_DRV_LOG(ERR, "Error setting alarm");
4244                 else {
4245                         /* remember original mask */
4246                         intr->mask_original = intr->mask;
4247                         /* only disable lsc interrupt */
4248                         intr->mask &= ~IXGBE_EIMS_LSC;
4249                 }
4250         }
4251
4252         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4253         ixgbe_enable_intr(dev);
4254         rte_intr_enable(intr_handle);
4255
4256         return 0;
4257 }
4258
4259 /**
4260  * Interrupt handler which shall be registered for alarm callback for delayed
4261  * handling specific interrupt to wait for the stable nic state. As the
4262  * NIC interrupt state is not stable for ixgbe after link is just down,
4263  * it needs to wait 4 seconds to get the stable status.
4264  *
4265  * @param handle
4266  *  Pointer to interrupt handle.
4267  * @param param
4268  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4269  *
4270  * @return
4271  *  void
4272  */
4273 static void
4274 ixgbe_dev_interrupt_delayed_handler(void *param)
4275 {
4276         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4277         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4278         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4279         struct ixgbe_interrupt *intr =
4280                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4281         struct ixgbe_hw *hw =
4282                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4283         uint32_t eicr;
4284
4285         ixgbe_disable_intr(hw);
4286
4287         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4288         if (eicr & IXGBE_EICR_MAILBOX)
4289                 ixgbe_pf_mbx_process(dev);
4290
4291         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4292                 ixgbe_handle_lasi(hw);
4293                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4294         }
4295
4296         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4297                 ixgbe_dev_link_update(dev, 0);
4298                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4299                 ixgbe_dev_link_status_print(dev);
4300                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4301                                               NULL);
4302         }
4303
4304         if (intr->flags & IXGBE_FLAG_MACSEC) {
4305                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4306                                               NULL);
4307                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4308         }
4309
4310         /* restore original mask */
4311         intr->mask = intr->mask_original;
4312         intr->mask_original = 0;
4313
4314         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4315         ixgbe_enable_intr(dev);
4316         rte_intr_enable(intr_handle);
4317 }
4318
4319 /**
4320  * Interrupt handler triggered by NIC  for handling
4321  * specific interrupt.
4322  *
4323  * @param handle
4324  *  Pointer to interrupt handle.
4325  * @param param
4326  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4327  *
4328  * @return
4329  *  void
4330  */
4331 static void
4332 ixgbe_dev_interrupt_handler(void *param)
4333 {
4334         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4335
4336         ixgbe_dev_interrupt_get_status(dev);
4337         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4338 }
4339
4340 static int
4341 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4342 {
4343         struct ixgbe_hw *hw;
4344
4345         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4347 }
4348
4349 static int
4350 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4351 {
4352         struct ixgbe_hw *hw;
4353
4354         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4356 }
4357
4358 static int
4359 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4360 {
4361         struct ixgbe_hw *hw;
4362         uint32_t mflcn_reg;
4363         uint32_t fccfg_reg;
4364         int rx_pause;
4365         int tx_pause;
4366
4367         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4368
4369         fc_conf->pause_time = hw->fc.pause_time;
4370         fc_conf->high_water = hw->fc.high_water[0];
4371         fc_conf->low_water = hw->fc.low_water[0];
4372         fc_conf->send_xon = hw->fc.send_xon;
4373         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4374
4375         /*
4376          * Return rx_pause status according to actual setting of
4377          * MFLCN register.
4378          */
4379         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4380         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4381                 rx_pause = 1;
4382         else
4383                 rx_pause = 0;
4384
4385         /*
4386          * Return tx_pause status according to actual setting of
4387          * FCCFG register.
4388          */
4389         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4390         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4391                 tx_pause = 1;
4392         else
4393                 tx_pause = 0;
4394
4395         if (rx_pause && tx_pause)
4396                 fc_conf->mode = RTE_FC_FULL;
4397         else if (rx_pause)
4398                 fc_conf->mode = RTE_FC_RX_PAUSE;
4399         else if (tx_pause)
4400                 fc_conf->mode = RTE_FC_TX_PAUSE;
4401         else
4402                 fc_conf->mode = RTE_FC_NONE;
4403
4404         return 0;
4405 }
4406
4407 static int
4408 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4409 {
4410         struct ixgbe_hw *hw;
4411         int err;
4412         uint32_t rx_buf_size;
4413         uint32_t max_high_water;
4414         uint32_t mflcn;
4415         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4416                 ixgbe_fc_none,
4417                 ixgbe_fc_rx_pause,
4418                 ixgbe_fc_tx_pause,
4419                 ixgbe_fc_full
4420         };
4421
4422         PMD_INIT_FUNC_TRACE();
4423
4424         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4425         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4426         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4427
4428         /*
4429          * At least reserve one Ethernet frame for watermark
4430          * high_water/low_water in kilo bytes for ixgbe
4431          */
4432         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4433         if ((fc_conf->high_water > max_high_water) ||
4434                 (fc_conf->high_water < fc_conf->low_water)) {
4435                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4436                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4437                 return -EINVAL;
4438         }
4439
4440         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4441         hw->fc.pause_time     = fc_conf->pause_time;
4442         hw->fc.high_water[0]  = fc_conf->high_water;
4443         hw->fc.low_water[0]   = fc_conf->low_water;
4444         hw->fc.send_xon       = fc_conf->send_xon;
4445         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4446
4447         err = ixgbe_fc_enable(hw);
4448
4449         /* Not negotiated is not an error case */
4450         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4451
4452                 /* check if we want to forward MAC frames - driver doesn't have native
4453                  * capability to do that, so we'll write the registers ourselves */
4454
4455                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4456
4457                 /* set or clear MFLCN.PMCF bit depending on configuration */
4458                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4459                         mflcn |= IXGBE_MFLCN_PMCF;
4460                 else
4461                         mflcn &= ~IXGBE_MFLCN_PMCF;
4462
4463                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4464                 IXGBE_WRITE_FLUSH(hw);
4465
4466                 return 0;
4467         }
4468
4469         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4470         return -EIO;
4471 }
4472
4473 /**
4474  *  ixgbe_pfc_enable_generic - Enable flow control
4475  *  @hw: pointer to hardware structure
4476  *  @tc_num: traffic class number
4477  *  Enable flow control according to the current settings.
4478  */
4479 static int
4480 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4481 {
4482         int ret_val = 0;
4483         uint32_t mflcn_reg, fccfg_reg;
4484         uint32_t reg;
4485         uint32_t fcrtl, fcrth;
4486         uint8_t i;
4487         uint8_t nb_rx_en;
4488
4489         /* Validate the water mark configuration */
4490         if (!hw->fc.pause_time) {
4491                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4492                 goto out;
4493         }
4494
4495         /* Low water mark of zero causes XOFF floods */
4496         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4497                  /* High/Low water can not be 0 */
4498                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4499                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4500                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4501                         goto out;
4502                 }
4503
4504                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4505                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4506                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4507                         goto out;
4508                 }
4509         }
4510         /* Negotiate the fc mode to use */
4511         ixgbe_fc_autoneg(hw);
4512
4513         /* Disable any previous flow control settings */
4514         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4515         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4516
4517         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4518         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4519
4520         switch (hw->fc.current_mode) {
4521         case ixgbe_fc_none:
4522                 /*
4523                  * If the count of enabled RX Priority Flow control >1,
4524                  * and the TX pause can not be disabled
4525                  */
4526                 nb_rx_en = 0;
4527                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4528                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4529                         if (reg & IXGBE_FCRTH_FCEN)
4530                                 nb_rx_en++;
4531                 }
4532                 if (nb_rx_en > 1)
4533                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4534                 break;
4535         case ixgbe_fc_rx_pause:
4536                 /*
4537                  * Rx Flow control is enabled and Tx Flow control is
4538                  * disabled by software override. Since there really
4539                  * isn't a way to advertise that we are capable of RX
4540                  * Pause ONLY, we will advertise that we support both
4541                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4542                  * disable the adapter's ability to send PAUSE frames.
4543                  */
4544                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4545                 /*
4546                  * If the count of enabled RX Priority Flow control >1,
4547                  * and the TX pause can not be disabled
4548                  */
4549                 nb_rx_en = 0;
4550                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4551                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4552                         if (reg & IXGBE_FCRTH_FCEN)
4553                                 nb_rx_en++;
4554                 }
4555                 if (nb_rx_en > 1)
4556                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4557                 break;
4558         case ixgbe_fc_tx_pause:
4559                 /*
4560                  * Tx Flow control is enabled, and Rx Flow control is
4561                  * disabled by software override.
4562                  */
4563                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4564                 break;
4565         case ixgbe_fc_full:
4566                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4567                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4568                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4569                 break;
4570         default:
4571                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4572                 ret_val = IXGBE_ERR_CONFIG;
4573                 goto out;
4574         }
4575
4576         /* Set 802.3x based flow control settings. */
4577         mflcn_reg |= IXGBE_MFLCN_DPF;
4578         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4579         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4580
4581         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4582         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4583                 hw->fc.high_water[tc_num]) {
4584                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4585                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4586                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4587         } else {
4588                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4589                 /*
4590                  * In order to prevent Tx hangs when the internal Tx
4591                  * switch is enabled we must set the high water mark
4592                  * to the maximum FCRTH value.  This allows the Tx
4593                  * switch to function even under heavy Rx workloads.
4594                  */
4595                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4596         }
4597         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4598
4599         /* Configure pause time (2 TCs per register) */
4600         reg = hw->fc.pause_time * 0x00010001;
4601         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4602                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4603
4604         /* Configure flow control refresh threshold value */
4605         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4606
4607 out:
4608         return ret_val;
4609 }
4610
4611 static int
4612 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4613 {
4614         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4615         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4616
4617         if (hw->mac.type != ixgbe_mac_82598EB) {
4618                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4619         }
4620         return ret_val;
4621 }
4622
4623 static int
4624 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4625 {
4626         int err;
4627         uint32_t rx_buf_size;
4628         uint32_t max_high_water;
4629         uint8_t tc_num;
4630         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4631         struct ixgbe_hw *hw =
4632                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4633         struct ixgbe_dcb_config *dcb_config =
4634                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4635
4636         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4637                 ixgbe_fc_none,
4638                 ixgbe_fc_rx_pause,
4639                 ixgbe_fc_tx_pause,
4640                 ixgbe_fc_full
4641         };
4642
4643         PMD_INIT_FUNC_TRACE();
4644
4645         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4646         tc_num = map[pfc_conf->priority];
4647         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4648         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4649         /*
4650          * At least reserve one Ethernet frame for watermark
4651          * high_water/low_water in kilo bytes for ixgbe
4652          */
4653         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4654         if ((pfc_conf->fc.high_water > max_high_water) ||
4655             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4656                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4657                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4658                 return -EINVAL;
4659         }
4660
4661         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4662         hw->fc.pause_time = pfc_conf->fc.pause_time;
4663         hw->fc.send_xon = pfc_conf->fc.send_xon;
4664         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4665         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4666
4667         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4668
4669         /* Not negotiated is not an error case */
4670         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4671                 return 0;
4672
4673         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4674         return -EIO;
4675 }
4676
4677 static int
4678 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4679                           struct rte_eth_rss_reta_entry64 *reta_conf,
4680                           uint16_t reta_size)
4681 {
4682         uint16_t i, sp_reta_size;
4683         uint8_t j, mask;
4684         uint32_t reta, r;
4685         uint16_t idx, shift;
4686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4687         uint32_t reta_reg;
4688
4689         PMD_INIT_FUNC_TRACE();
4690
4691         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4692                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4693                         "NIC.");
4694                 return -ENOTSUP;
4695         }
4696
4697         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4698         if (reta_size != sp_reta_size) {
4699                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4700                         "(%d) doesn't match the number hardware can supported "
4701                         "(%d)", reta_size, sp_reta_size);
4702                 return -EINVAL;
4703         }
4704
4705         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4706                 idx = i / RTE_RETA_GROUP_SIZE;
4707                 shift = i % RTE_RETA_GROUP_SIZE;
4708                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4709                                                 IXGBE_4_BIT_MASK);
4710                 if (!mask)
4711                         continue;
4712                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4713                 if (mask == IXGBE_4_BIT_MASK)
4714                         r = 0;
4715                 else
4716                         r = IXGBE_READ_REG(hw, reta_reg);
4717                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4718                         if (mask & (0x1 << j))
4719                                 reta |= reta_conf[idx].reta[shift + j] <<
4720                                                         (CHAR_BIT * j);
4721                         else
4722                                 reta |= r & (IXGBE_8_BIT_MASK <<
4723                                                 (CHAR_BIT * j));
4724                 }
4725                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4726         }
4727
4728         return 0;
4729 }
4730
4731 static int
4732 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4733                          struct rte_eth_rss_reta_entry64 *reta_conf,
4734                          uint16_t reta_size)
4735 {
4736         uint16_t i, sp_reta_size;
4737         uint8_t j, mask;
4738         uint32_t reta;
4739         uint16_t idx, shift;
4740         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741         uint32_t reta_reg;
4742
4743         PMD_INIT_FUNC_TRACE();
4744         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4745         if (reta_size != sp_reta_size) {
4746                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4747                         "(%d) doesn't match the number hardware can supported "
4748                         "(%d)", reta_size, sp_reta_size);
4749                 return -EINVAL;
4750         }
4751
4752         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4753                 idx = i / RTE_RETA_GROUP_SIZE;
4754                 shift = i % RTE_RETA_GROUP_SIZE;
4755                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4756                                                 IXGBE_4_BIT_MASK);
4757                 if (!mask)
4758                         continue;
4759
4760                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4761                 reta = IXGBE_READ_REG(hw, reta_reg);
4762                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4763                         if (mask & (0x1 << j))
4764                                 reta_conf[idx].reta[shift + j] =
4765                                         ((reta >> (CHAR_BIT * j)) &
4766                                                 IXGBE_8_BIT_MASK);
4767                 }
4768         }
4769
4770         return 0;
4771 }
4772
4773 static int
4774 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4775                                 uint32_t index, uint32_t pool)
4776 {
4777         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4778         uint32_t enable_addr = 1;
4779
4780         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4781                              pool, enable_addr);
4782 }
4783
4784 static void
4785 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4786 {
4787         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4788
4789         ixgbe_clear_rar(hw, index);
4790 }
4791
4792 static void
4793 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4794 {
4795         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4796
4797         ixgbe_remove_rar(dev, 0);
4798
4799         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4800 }
4801
4802 static bool
4803 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4804 {
4805         if (strcmp(dev->device->driver->name, drv->driver.name))
4806                 return false;
4807
4808         return true;
4809 }
4810
4811 bool
4812 is_ixgbe_supported(struct rte_eth_dev *dev)
4813 {
4814         return is_device_supported(dev, &rte_ixgbe_pmd);
4815 }
4816
4817 static int
4818 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4819 {
4820         uint32_t hlreg0;
4821         uint32_t maxfrs;
4822         struct ixgbe_hw *hw;
4823         struct rte_eth_dev_info dev_info;
4824         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4825         struct rte_eth_dev_data *dev_data = dev->data;
4826
4827         ixgbe_dev_info_get(dev, &dev_info);
4828
4829         /* check that mtu is within the allowed range */
4830         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4831                 return -EINVAL;
4832
4833         /* If device is started, refuse mtu that requires the support of
4834          * scattered packets when this feature has not been enabled before.
4835          */
4836         if (dev_data->dev_started && !dev_data->scattered_rx &&
4837             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4838              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4839                 PMD_INIT_LOG(ERR, "Stop port first.");
4840                 return -EINVAL;
4841         }
4842
4843         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4844         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4845
4846         /* switch to jumbo mode if needed */
4847         if (frame_size > ETHER_MAX_LEN) {
4848                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4849                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4850         } else {
4851                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4852                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4853         }
4854         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4855
4856         /* update max frame size */
4857         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4858
4859         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4860         maxfrs &= 0x0000FFFF;
4861         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4862         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4863
4864         return 0;
4865 }
4866
4867 /*
4868  * Virtual Function operations
4869  */
4870 static void
4871 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4872 {
4873         PMD_INIT_FUNC_TRACE();
4874
4875         /* Clear interrupt mask to stop from interrupts being generated */
4876         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4877
4878         IXGBE_WRITE_FLUSH(hw);
4879 }
4880
4881 static void
4882 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4883 {
4884         PMD_INIT_FUNC_TRACE();
4885
4886         /* VF enable interrupt autoclean */
4887         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4888         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4889         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4890
4891         IXGBE_WRITE_FLUSH(hw);
4892 }
4893
4894 static int
4895 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4896 {
4897         struct rte_eth_conf *conf = &dev->data->dev_conf;
4898         struct ixgbe_adapter *adapter =
4899                         (struct ixgbe_adapter *)dev->data->dev_private;
4900
4901         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4902                      dev->data->port_id);
4903
4904         /*
4905          * VF has no ability to enable/disable HW CRC
4906          * Keep the persistent behavior the same as Host PF
4907          */
4908 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4909         if (!conf->rxmode.hw_strip_crc) {
4910                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4911                 conf->rxmode.hw_strip_crc = 1;
4912         }
4913 #else
4914         if (conf->rxmode.hw_strip_crc) {
4915                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4916                 conf->rxmode.hw_strip_crc = 0;
4917         }
4918 #endif
4919
4920         /*
4921          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4922          * allocation or vector Rx preconditions we will reset it.
4923          */
4924         adapter->rx_bulk_alloc_allowed = true;
4925         adapter->rx_vec_allowed = true;
4926
4927         return 0;
4928 }
4929
4930 static int
4931 ixgbevf_dev_start(struct rte_eth_dev *dev)
4932 {
4933         struct ixgbe_hw *hw =
4934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4935         uint32_t intr_vector = 0;
4936         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4937         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4938
4939         int err, mask = 0;
4940
4941         PMD_INIT_FUNC_TRACE();
4942
4943         err = hw->mac.ops.reset_hw(hw);
4944         if (err) {
4945                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4946                 return err;
4947         }
4948         hw->mac.get_link_status = true;
4949
4950         /* negotiate mailbox API version to use with the PF. */
4951         ixgbevf_negotiate_api(hw);
4952
4953         ixgbevf_dev_tx_init(dev);
4954
4955         /* This can fail when allocating mbufs for descriptor rings */
4956         err = ixgbevf_dev_rx_init(dev);
4957         if (err) {
4958                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4959                 ixgbe_dev_clear_queues(dev);
4960                 return err;
4961         }
4962
4963         /* Set vfta */
4964         ixgbevf_set_vfta_all(dev, 1);
4965
4966         /* Set HW strip */
4967         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4968                 ETH_VLAN_EXTEND_MASK;
4969         err = ixgbevf_vlan_offload_set(dev, mask);
4970         if (err) {
4971                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4972                 ixgbe_dev_clear_queues(dev);
4973                 return err;
4974         }
4975
4976         ixgbevf_dev_rxtx_start(dev);
4977
4978         /* check and configure queue intr-vector mapping */
4979         if (rte_intr_cap_multiple(intr_handle) &&
4980             dev->data->dev_conf.intr_conf.rxq) {
4981                 /* According to datasheet, only vector 0/1/2 can be used,
4982                  * now only one vector is used for Rx queue
4983                  */
4984                 intr_vector = 1;
4985                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4986                         return -1;
4987         }
4988
4989         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4990                 intr_handle->intr_vec =
4991                         rte_zmalloc("intr_vec",
4992                                     dev->data->nb_rx_queues * sizeof(int), 0);
4993                 if (intr_handle->intr_vec == NULL) {
4994                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4995                                      " intr_vec", dev->data->nb_rx_queues);
4996                         return -ENOMEM;
4997                 }
4998         }
4999         ixgbevf_configure_msix(dev);
5000
5001         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5002          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5003          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5004          * is not cleared, it will fail when following rte_intr_enable( ) tries
5005          * to map Rx queue interrupt to other VFIO vectors.
5006          * So clear uio/vfio intr/evevnfd first to avoid failure.
5007          */
5008         rte_intr_disable(intr_handle);
5009
5010         rte_intr_enable(intr_handle);
5011
5012         /* Re-enable interrupt for VF */
5013         ixgbevf_intr_enable(hw);
5014
5015         return 0;
5016 }
5017
5018 static void
5019 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5020 {
5021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5022         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5023         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5024
5025         PMD_INIT_FUNC_TRACE();
5026
5027         ixgbevf_intr_disable(hw);
5028
5029         hw->adapter_stopped = 1;
5030         ixgbe_stop_adapter(hw);
5031
5032         /*
5033           * Clear what we set, but we still keep shadow_vfta to
5034           * restore after device starts
5035           */
5036         ixgbevf_set_vfta_all(dev, 0);
5037
5038         /* Clear stored conf */
5039         dev->data->scattered_rx = 0;
5040
5041         ixgbe_dev_clear_queues(dev);
5042
5043         /* Clean datapath event and queue/vec mapping */
5044         rte_intr_efd_disable(intr_handle);
5045         if (intr_handle->intr_vec != NULL) {
5046                 rte_free(intr_handle->intr_vec);
5047                 intr_handle->intr_vec = NULL;
5048         }
5049 }
5050
5051 static void
5052 ixgbevf_dev_close(struct rte_eth_dev *dev)
5053 {
5054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5055
5056         PMD_INIT_FUNC_TRACE();
5057
5058         ixgbe_reset_hw(hw);
5059
5060         ixgbevf_dev_stop(dev);
5061
5062         ixgbe_dev_free_queues(dev);
5063
5064         /**
5065          * Remove the VF MAC address ro ensure
5066          * that the VF traffic goes to the PF
5067          * after stop, close and detach of the VF
5068          **/
5069         ixgbevf_remove_mac_addr(dev, 0);
5070 }
5071
5072 /*
5073  * Reset VF device
5074  */
5075 static int
5076 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5077 {
5078         int ret;
5079
5080         ret = eth_ixgbevf_dev_uninit(dev);
5081         if (ret)
5082                 return ret;
5083
5084         ret = eth_ixgbevf_dev_init(dev);
5085
5086         return ret;
5087 }
5088
5089 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5090 {
5091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5092         struct ixgbe_vfta *shadow_vfta =
5093                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5094         int i = 0, j = 0, vfta = 0, mask = 1;
5095
5096         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5097                 vfta = shadow_vfta->vfta[i];
5098                 if (vfta) {
5099                         mask = 1;
5100                         for (j = 0; j < 32; j++) {
5101                                 if (vfta & mask)
5102                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5103                                                        on, false);
5104                                 mask <<= 1;
5105                         }
5106                 }
5107         }
5108
5109 }
5110
5111 static int
5112 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5113 {
5114         struct ixgbe_hw *hw =
5115                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116         struct ixgbe_vfta *shadow_vfta =
5117                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5118         uint32_t vid_idx = 0;
5119         uint32_t vid_bit = 0;
5120         int ret = 0;
5121
5122         PMD_INIT_FUNC_TRACE();
5123
5124         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5125         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5126         if (ret) {
5127                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5128                 return ret;
5129         }
5130         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5131         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5132
5133         /* Save what we set and retore it after device reset */
5134         if (on)
5135                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5136         else
5137                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5138
5139         return 0;
5140 }
5141
5142 static void
5143 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5144 {
5145         struct ixgbe_hw *hw =
5146                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147         uint32_t ctrl;
5148
5149         PMD_INIT_FUNC_TRACE();
5150
5151         if (queue >= hw->mac.max_rx_queues)
5152                 return;
5153
5154         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5155         if (on)
5156                 ctrl |= IXGBE_RXDCTL_VME;
5157         else
5158                 ctrl &= ~IXGBE_RXDCTL_VME;
5159         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5160
5161         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5162 }
5163
5164 static int
5165 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5166 {
5167         struct ixgbe_hw *hw =
5168                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5169         uint16_t i;
5170         int on = 0;
5171
5172         /* VF function only support hw strip feature, others are not support */
5173         if (mask & ETH_VLAN_STRIP_MASK) {
5174                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5175
5176                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5177                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5178         }
5179
5180         return 0;
5181 }
5182
5183 int
5184 ixgbe_vt_check(struct ixgbe_hw *hw)
5185 {
5186         uint32_t reg_val;
5187
5188         /* if Virtualization Technology is enabled */
5189         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5190         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5191                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5192                 return -1;
5193         }
5194
5195         return 0;
5196 }
5197
5198 static uint32_t
5199 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5200 {
5201         uint32_t vector = 0;
5202
5203         switch (hw->mac.mc_filter_type) {
5204         case 0:   /* use bits [47:36] of the address */
5205                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5206                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5207                 break;
5208         case 1:   /* use bits [46:35] of the address */
5209                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5210                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5211                 break;
5212         case 2:   /* use bits [45:34] of the address */
5213                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5214                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5215                 break;
5216         case 3:   /* use bits [43:32] of the address */
5217                 vector = ((uc_addr->addr_bytes[4]) |
5218                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5219                 break;
5220         default:  /* Invalid mc_filter_type */
5221                 break;
5222         }
5223
5224         /* vector can only be 12-bits or boundary will be exceeded */
5225         vector &= 0xFFF;
5226         return vector;
5227 }
5228
5229 static int
5230 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5231                         uint8_t on)
5232 {
5233         uint32_t vector;
5234         uint32_t uta_idx;
5235         uint32_t reg_val;
5236         uint32_t uta_shift;
5237         uint32_t rc;
5238         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5239         const uint32_t ixgbe_uta_bit_shift = 5;
5240         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5241         const uint32_t bit1 = 0x1;
5242
5243         struct ixgbe_hw *hw =
5244                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5245         struct ixgbe_uta_info *uta_info =
5246                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5247
5248         /* The UTA table only exists on 82599 hardware and newer */
5249         if (hw->mac.type < ixgbe_mac_82599EB)
5250                 return -ENOTSUP;
5251
5252         vector = ixgbe_uta_vector(hw, mac_addr);
5253         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5254         uta_shift = vector & ixgbe_uta_bit_mask;
5255
5256         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5257         if (rc == on)
5258                 return 0;
5259
5260         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5261         if (on) {
5262                 uta_info->uta_in_use++;
5263                 reg_val |= (bit1 << uta_shift);
5264                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5265         } else {
5266                 uta_info->uta_in_use--;
5267                 reg_val &= ~(bit1 << uta_shift);
5268                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5269         }
5270
5271         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5272
5273         if (uta_info->uta_in_use > 0)
5274                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5275                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5276         else
5277                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5278
5279         return 0;
5280 }
5281
5282 static int
5283 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5284 {
5285         int i;
5286         struct ixgbe_hw *hw =
5287                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5288         struct ixgbe_uta_info *uta_info =
5289                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5290
5291         /* The UTA table only exists on 82599 hardware and newer */
5292         if (hw->mac.type < ixgbe_mac_82599EB)
5293                 return -ENOTSUP;
5294
5295         if (on) {
5296                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5297                         uta_info->uta_shadow[i] = ~0;
5298                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5299                 }
5300         } else {
5301                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5302                         uta_info->uta_shadow[i] = 0;
5303                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5304                 }
5305         }
5306         return 0;
5307
5308 }
5309
5310 uint32_t
5311 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5312 {
5313         uint32_t new_val = orig_val;
5314
5315         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5316                 new_val |= IXGBE_VMOLR_AUPE;
5317         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5318                 new_val |= IXGBE_VMOLR_ROMPE;
5319         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5320                 new_val |= IXGBE_VMOLR_ROPE;
5321         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5322                 new_val |= IXGBE_VMOLR_BAM;
5323         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5324                 new_val |= IXGBE_VMOLR_MPE;
5325
5326         return new_val;
5327 }
5328
5329 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5330 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5331 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5332 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5333 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5334         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5335         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5336
5337 static int
5338 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5339                       struct rte_eth_mirror_conf *mirror_conf,
5340                       uint8_t rule_id, uint8_t on)
5341 {
5342         uint32_t mr_ctl, vlvf;
5343         uint32_t mp_lsb = 0;
5344         uint32_t mv_msb = 0;
5345         uint32_t mv_lsb = 0;
5346         uint32_t mp_msb = 0;
5347         uint8_t i = 0;
5348         int reg_index = 0;
5349         uint64_t vlan_mask = 0;
5350
5351         const uint8_t pool_mask_offset = 32;
5352         const uint8_t vlan_mask_offset = 32;
5353         const uint8_t dst_pool_offset = 8;
5354         const uint8_t rule_mr_offset  = 4;
5355         const uint8_t mirror_rule_mask = 0x0F;
5356
5357         struct ixgbe_mirror_info *mr_info =
5358                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5359         struct ixgbe_hw *hw =
5360                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5361         uint8_t mirror_type = 0;
5362
5363         if (ixgbe_vt_check(hw) < 0)
5364                 return -ENOTSUP;
5365
5366         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5367                 return -EINVAL;
5368
5369         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5370                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5371                             mirror_conf->rule_type);
5372                 return -EINVAL;
5373         }
5374
5375         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5376                 mirror_type |= IXGBE_MRCTL_VLME;
5377                 /* Check if vlan id is valid and find conresponding VLAN ID
5378                  * index in VLVF
5379                  */
5380                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5381                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5382                                 /* search vlan id related pool vlan filter
5383                                  * index
5384                                  */
5385                                 reg_index = ixgbe_find_vlvf_slot(
5386                                                 hw,
5387                                                 mirror_conf->vlan.vlan_id[i],
5388                                                 false);
5389                                 if (reg_index < 0)
5390                                         return -EINVAL;
5391                                 vlvf = IXGBE_READ_REG(hw,
5392                                                       IXGBE_VLVF(reg_index));
5393                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5394                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5395                                       mirror_conf->vlan.vlan_id[i]))
5396                                         vlan_mask |= (1ULL << reg_index);
5397                                 else
5398                                         return -EINVAL;
5399                         }
5400                 }
5401
5402                 if (on) {
5403                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5404                         mv_msb = vlan_mask >> vlan_mask_offset;
5405
5406                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5407                                                 mirror_conf->vlan.vlan_mask;
5408                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5409                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5410                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5411                                                 mirror_conf->vlan.vlan_id[i];
5412                         }
5413                 } else {
5414                         mv_lsb = 0;
5415                         mv_msb = 0;
5416                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5417                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5418                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5419                 }
5420         }
5421
5422         /**
5423          * if enable pool mirror, write related pool mask register,if disable
5424          * pool mirror, clear PFMRVM register
5425          */
5426         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5427                 mirror_type |= IXGBE_MRCTL_VPME;
5428                 if (on) {
5429                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5430                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5431                         mr_info->mr_conf[rule_id].pool_mask =
5432                                         mirror_conf->pool_mask;
5433
5434                 } else {
5435                         mp_lsb = 0;
5436                         mp_msb = 0;
5437                         mr_info->mr_conf[rule_id].pool_mask = 0;
5438                 }
5439         }
5440         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5441                 mirror_type |= IXGBE_MRCTL_UPME;
5442         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5443                 mirror_type |= IXGBE_MRCTL_DPME;
5444
5445         /* read  mirror control register and recalculate it */
5446         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5447
5448         if (on) {
5449                 mr_ctl |= mirror_type;
5450                 mr_ctl &= mirror_rule_mask;
5451                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5452         } else {
5453                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5454         }
5455
5456         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5457         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5458
5459         /* write mirrror control  register */
5460         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5461
5462         /* write pool mirrror control  register */
5463         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5464                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5465                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5466                                 mp_msb);
5467         }
5468         /* write VLAN mirrror control  register */
5469         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5470                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5471                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5472                                 mv_msb);
5473         }
5474
5475         return 0;
5476 }
5477
5478 static int
5479 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5480 {
5481         int mr_ctl = 0;
5482         uint32_t lsb_val = 0;
5483         uint32_t msb_val = 0;
5484         const uint8_t rule_mr_offset = 4;
5485
5486         struct ixgbe_hw *hw =
5487                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5488         struct ixgbe_mirror_info *mr_info =
5489                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5490
5491         if (ixgbe_vt_check(hw) < 0)
5492                 return -ENOTSUP;
5493
5494         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5495                 return -EINVAL;
5496
5497         memset(&mr_info->mr_conf[rule_id], 0,
5498                sizeof(struct rte_eth_mirror_conf));
5499
5500         /* clear PFVMCTL register */
5501         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5502
5503         /* clear pool mask register */
5504         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5505         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5506
5507         /* clear vlan mask register */
5508         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5509         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5510
5511         return 0;
5512 }
5513
5514 static int
5515 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5516 {
5517         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5518         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5519         uint32_t mask;
5520         struct ixgbe_hw *hw =
5521                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5522         uint32_t vec = IXGBE_MISC_VEC_ID;
5523
5524         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5525         if (rte_intr_allow_others(intr_handle))
5526                 vec = IXGBE_RX_VEC_START;
5527         mask |= (1 << vec);
5528         RTE_SET_USED(queue_id);
5529         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5530
5531         rte_intr_enable(intr_handle);
5532
5533         return 0;
5534 }
5535
5536 static int
5537 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5538 {
5539         uint32_t mask;
5540         struct ixgbe_hw *hw =
5541                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5542         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5543         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5544         uint32_t vec = IXGBE_MISC_VEC_ID;
5545
5546         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5547         if (rte_intr_allow_others(intr_handle))
5548                 vec = IXGBE_RX_VEC_START;
5549         mask &= ~(1 << vec);
5550         RTE_SET_USED(queue_id);
5551         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5552
5553         return 0;
5554 }
5555
5556 static int
5557 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5558 {
5559         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5560         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5561         uint32_t mask;
5562         struct ixgbe_hw *hw =
5563                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5564         struct ixgbe_interrupt *intr =
5565                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5566
5567         if (queue_id < 16) {
5568                 ixgbe_disable_intr(hw);
5569                 intr->mask |= (1 << queue_id);
5570                 ixgbe_enable_intr(dev);
5571         } else if (queue_id < 32) {
5572                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5573                 mask &= (1 << queue_id);
5574                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5575         } else if (queue_id < 64) {
5576                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5577                 mask &= (1 << (queue_id - 32));
5578                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5579         }
5580         rte_intr_enable(intr_handle);
5581
5582         return 0;
5583 }
5584
5585 static int
5586 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5587 {
5588         uint32_t mask;
5589         struct ixgbe_hw *hw =
5590                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5591         struct ixgbe_interrupt *intr =
5592                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5593
5594         if (queue_id < 16) {
5595                 ixgbe_disable_intr(hw);
5596                 intr->mask &= ~(1 << queue_id);
5597                 ixgbe_enable_intr(dev);
5598         } else if (queue_id < 32) {
5599                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5600                 mask &= ~(1 << queue_id);
5601                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5602         } else if (queue_id < 64) {
5603                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5604                 mask &= ~(1 << (queue_id - 32));
5605                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5606         }
5607
5608         return 0;
5609 }
5610
5611 static void
5612 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5613                      uint8_t queue, uint8_t msix_vector)
5614 {
5615         uint32_t tmp, idx;
5616
5617         if (direction == -1) {
5618                 /* other causes */
5619                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5620                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5621                 tmp &= ~0xFF;
5622                 tmp |= msix_vector;
5623                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5624         } else {
5625                 /* rx or tx cause */
5626                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5627                 idx = ((16 * (queue & 1)) + (8 * direction));
5628                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5629                 tmp &= ~(0xFF << idx);
5630                 tmp |= (msix_vector << idx);
5631                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5632         }
5633 }
5634
5635 /**
5636  * set the IVAR registers, mapping interrupt causes to vectors
5637  * @param hw
5638  *  pointer to ixgbe_hw struct
5639  * @direction
5640  *  0 for Rx, 1 for Tx, -1 for other causes
5641  * @queue
5642  *  queue to map the corresponding interrupt to
5643  * @msix_vector
5644  *  the vector to map to the corresponding queue
5645  */
5646 static void
5647 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5648                    uint8_t queue, uint8_t msix_vector)
5649 {
5650         uint32_t tmp, idx;
5651
5652         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5653         if (hw->mac.type == ixgbe_mac_82598EB) {
5654                 if (direction == -1)
5655                         direction = 0;
5656                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5657                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5658                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5659                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5660                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5661         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5662                         (hw->mac.type == ixgbe_mac_X540) ||
5663                         (hw->mac.type == ixgbe_mac_X550)) {
5664                 if (direction == -1) {
5665                         /* other causes */
5666                         idx = ((queue & 1) * 8);
5667                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5668                         tmp &= ~(0xFF << idx);
5669                         tmp |= (msix_vector << idx);
5670                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5671                 } else {
5672                         /* rx or tx causes */
5673                         idx = ((16 * (queue & 1)) + (8 * direction));
5674                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5675                         tmp &= ~(0xFF << idx);
5676                         tmp |= (msix_vector << idx);
5677                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5678                 }
5679         }
5680 }
5681
5682 static void
5683 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5684 {
5685         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5686         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5687         struct ixgbe_hw *hw =
5688                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5689         uint32_t q_idx;
5690         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5691         uint32_t base = IXGBE_MISC_VEC_ID;
5692
5693         /* Configure VF other cause ivar */
5694         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5695
5696         /* won't configure msix register if no mapping is done
5697          * between intr vector and event fd.
5698          */
5699         if (!rte_intr_dp_is_en(intr_handle))
5700                 return;
5701
5702         if (rte_intr_allow_others(intr_handle)) {
5703                 base = IXGBE_RX_VEC_START;
5704                 vector_idx = IXGBE_RX_VEC_START;
5705         }
5706
5707         /* Configure all RX queues of VF */
5708         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5709                 /* Force all queue use vector 0,
5710                  * as IXGBE_VF_MAXMSIVECOTR = 1
5711                  */
5712                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5713                 intr_handle->intr_vec[q_idx] = vector_idx;
5714                 if (vector_idx < base + intr_handle->nb_efd - 1)
5715                         vector_idx++;
5716         }
5717 }
5718
5719 /**
5720  * Sets up the hardware to properly generate MSI-X interrupts
5721  * @hw
5722  *  board private structure
5723  */
5724 static void
5725 ixgbe_configure_msix(struct rte_eth_dev *dev)
5726 {
5727         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5728         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5729         struct ixgbe_hw *hw =
5730                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5731         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5732         uint32_t vec = IXGBE_MISC_VEC_ID;
5733         uint32_t mask;
5734         uint32_t gpie;
5735
5736         /* won't configure msix register if no mapping is done
5737          * between intr vector and event fd
5738          */
5739         if (!rte_intr_dp_is_en(intr_handle))
5740                 return;
5741
5742         if (rte_intr_allow_others(intr_handle))
5743                 vec = base = IXGBE_RX_VEC_START;
5744
5745         /* setup GPIE for MSI-x mode */
5746         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5747         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5748                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5749         /* auto clearing and auto setting corresponding bits in EIMS
5750          * when MSI-X interrupt is triggered
5751          */
5752         if (hw->mac.type == ixgbe_mac_82598EB) {
5753                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5754         } else {
5755                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5756                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5757         }
5758         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5759
5760         /* Populate the IVAR table and set the ITR values to the
5761          * corresponding register.
5762          */
5763         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5764              queue_id++) {
5765                 /* by default, 1:1 mapping */
5766                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5767                 intr_handle->intr_vec[queue_id] = vec;
5768                 if (vec < base + intr_handle->nb_efd - 1)
5769                         vec++;
5770         }
5771
5772         switch (hw->mac.type) {
5773         case ixgbe_mac_82598EB:
5774                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5775                                    IXGBE_MISC_VEC_ID);
5776                 break;
5777         case ixgbe_mac_82599EB:
5778         case ixgbe_mac_X540:
5779         case ixgbe_mac_X550:
5780                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5781                 break;
5782         default:
5783                 break;
5784         }
5785         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5786                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5787
5788         /* set up to autoclear timer, and the vectors */
5789         mask = IXGBE_EIMS_ENABLE_MASK;
5790         mask &= ~(IXGBE_EIMS_OTHER |
5791                   IXGBE_EIMS_MAILBOX |
5792                   IXGBE_EIMS_LSC);
5793
5794         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5795 }
5796
5797 int
5798 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5799                            uint16_t queue_idx, uint16_t tx_rate)
5800 {
5801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5802         uint32_t rf_dec, rf_int;
5803         uint32_t bcnrc_val;
5804         uint16_t link_speed = dev->data->dev_link.link_speed;
5805
5806         if (queue_idx >= hw->mac.max_tx_queues)
5807                 return -EINVAL;
5808
5809         if (tx_rate != 0) {
5810                 /* Calculate the rate factor values to set */
5811                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5812                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5813                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5814
5815                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5816                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5817                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5818                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5819         } else {
5820                 bcnrc_val = 0;
5821         }
5822
5823         /*
5824          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5825          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5826          * set as 0x4.
5827          */
5828         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5829                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5830                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5831                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5832                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5833         else
5834                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5835                         IXGBE_MMW_SIZE_DEFAULT);
5836
5837         /* Set RTTBCNRC of queue X */
5838         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5839         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5840         IXGBE_WRITE_FLUSH(hw);
5841
5842         return 0;
5843 }
5844
5845 static int
5846 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5847                      __attribute__((unused)) uint32_t index,
5848                      __attribute__((unused)) uint32_t pool)
5849 {
5850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5851         int diag;
5852
5853         /*
5854          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5855          * operation. Trap this case to avoid exhausting the [very limited]
5856          * set of PF resources used to store VF MAC addresses.
5857          */
5858         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5859                 return -1;
5860         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5861         if (diag != 0)
5862                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5863                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5864                             mac_addr->addr_bytes[0],
5865                             mac_addr->addr_bytes[1],
5866                             mac_addr->addr_bytes[2],
5867                             mac_addr->addr_bytes[3],
5868                             mac_addr->addr_bytes[4],
5869                             mac_addr->addr_bytes[5],
5870                             diag);
5871         return diag;
5872 }
5873
5874 static void
5875 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5876 {
5877         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5878         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5879         struct ether_addr *mac_addr;
5880         uint32_t i;
5881         int diag;
5882
5883         /*
5884          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5885          * not support the deletion of a given MAC address.
5886          * Instead, it imposes to delete all MAC addresses, then to add again
5887          * all MAC addresses with the exception of the one to be deleted.
5888          */
5889         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5890
5891         /*
5892          * Add again all MAC addresses, with the exception of the deleted one
5893          * and of the permanent MAC address.
5894          */
5895         for (i = 0, mac_addr = dev->data->mac_addrs;
5896              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5897                 /* Skip the deleted MAC address */
5898                 if (i == index)
5899                         continue;
5900                 /* Skip NULL MAC addresses */
5901                 if (is_zero_ether_addr(mac_addr))
5902                         continue;
5903                 /* Skip the permanent MAC address */
5904                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5905                         continue;
5906                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5907                 if (diag != 0)
5908                         PMD_DRV_LOG(ERR,
5909                                     "Adding again MAC address "
5910                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5911                                     "diag=%d",
5912                                     mac_addr->addr_bytes[0],
5913                                     mac_addr->addr_bytes[1],
5914                                     mac_addr->addr_bytes[2],
5915                                     mac_addr->addr_bytes[3],
5916                                     mac_addr->addr_bytes[4],
5917                                     mac_addr->addr_bytes[5],
5918                                     diag);
5919         }
5920 }
5921
5922 static void
5923 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5924 {
5925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5926
5927         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5928 }
5929
5930 int
5931 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5932                         struct rte_eth_syn_filter *filter,
5933                         bool add)
5934 {
5935         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5936         struct ixgbe_filter_info *filter_info =
5937                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5938         uint32_t syn_info;
5939         uint32_t synqf;
5940
5941         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5942                 return -EINVAL;
5943
5944         syn_info = filter_info->syn_info;
5945
5946         if (add) {
5947                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5948                         return -EINVAL;
5949                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5950                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5951
5952                 if (filter->hig_pri)
5953                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5954                 else
5955                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5956         } else {
5957                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5958                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5959                         return -ENOENT;
5960                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5961         }
5962
5963         filter_info->syn_info = synqf;
5964         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5965         IXGBE_WRITE_FLUSH(hw);
5966         return 0;
5967 }
5968
5969 static int
5970 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5971                         struct rte_eth_syn_filter *filter)
5972 {
5973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5974         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5975
5976         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5977                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5978                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5979                 return 0;
5980         }
5981         return -ENOENT;
5982 }
5983
5984 static int
5985 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5986                         enum rte_filter_op filter_op,
5987                         void *arg)
5988 {
5989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5990         int ret;
5991
5992         MAC_TYPE_FILTER_SUP(hw->mac.type);
5993
5994         if (filter_op == RTE_ETH_FILTER_NOP)
5995                 return 0;
5996
5997         if (arg == NULL) {
5998                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5999                             filter_op);
6000                 return -EINVAL;
6001         }
6002
6003         switch (filter_op) {
6004         case RTE_ETH_FILTER_ADD:
6005                 ret = ixgbe_syn_filter_set(dev,
6006                                 (struct rte_eth_syn_filter *)arg,
6007                                 TRUE);
6008                 break;
6009         case RTE_ETH_FILTER_DELETE:
6010                 ret = ixgbe_syn_filter_set(dev,
6011                                 (struct rte_eth_syn_filter *)arg,
6012                                 FALSE);
6013                 break;
6014         case RTE_ETH_FILTER_GET:
6015                 ret = ixgbe_syn_filter_get(dev,
6016                                 (struct rte_eth_syn_filter *)arg);
6017                 break;
6018         default:
6019                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6020                 ret = -EINVAL;
6021                 break;
6022         }
6023
6024         return ret;
6025 }
6026
6027
6028 static inline enum ixgbe_5tuple_protocol
6029 convert_protocol_type(uint8_t protocol_value)
6030 {
6031         if (protocol_value == IPPROTO_TCP)
6032                 return IXGBE_FILTER_PROTOCOL_TCP;
6033         else if (protocol_value == IPPROTO_UDP)
6034                 return IXGBE_FILTER_PROTOCOL_UDP;
6035         else if (protocol_value == IPPROTO_SCTP)
6036                 return IXGBE_FILTER_PROTOCOL_SCTP;
6037         else
6038                 return IXGBE_FILTER_PROTOCOL_NONE;
6039 }
6040
6041 /* inject a 5-tuple filter to HW */
6042 static inline void
6043 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6044                            struct ixgbe_5tuple_filter *filter)
6045 {
6046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6047         int i;
6048         uint32_t ftqf, sdpqf;
6049         uint32_t l34timir = 0;
6050         uint8_t mask = 0xff;
6051
6052         i = filter->index;
6053
6054         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6055                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6056         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6057
6058         ftqf = (uint32_t)(filter->filter_info.proto &
6059                 IXGBE_FTQF_PROTOCOL_MASK);
6060         ftqf |= (uint32_t)((filter->filter_info.priority &
6061                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6062         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6063                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6064         if (filter->filter_info.dst_ip_mask == 0)
6065                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6066         if (filter->filter_info.src_port_mask == 0)
6067                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6068         if (filter->filter_info.dst_port_mask == 0)
6069                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6070         if (filter->filter_info.proto_mask == 0)
6071                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6072         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6073         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6074         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6075
6076         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6077         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6078         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6079         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6080
6081         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6082         l34timir |= (uint32_t)(filter->queue <<
6083                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6084         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6085 }
6086
6087 /*
6088  * add a 5tuple filter
6089  *
6090  * @param
6091  * dev: Pointer to struct rte_eth_dev.
6092  * index: the index the filter allocates.
6093  * filter: ponter to the filter that will be added.
6094  * rx_queue: the queue id the filter assigned to.
6095  *
6096  * @return
6097  *    - On success, zero.
6098  *    - On failure, a negative value.
6099  */
6100 static int
6101 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6102                         struct ixgbe_5tuple_filter *filter)
6103 {
6104         struct ixgbe_filter_info *filter_info =
6105                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6106         int i, idx, shift;
6107
6108         /*
6109          * look for an unused 5tuple filter index,
6110          * and insert the filter to list.
6111          */
6112         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6113                 idx = i / (sizeof(uint32_t) * NBBY);
6114                 shift = i % (sizeof(uint32_t) * NBBY);
6115                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6116                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6117                         filter->index = i;
6118                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6119                                           filter,
6120                                           entries);
6121                         break;
6122                 }
6123         }
6124         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6125                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6126                 return -ENOSYS;
6127         }
6128
6129         ixgbe_inject_5tuple_filter(dev, filter);
6130
6131         return 0;
6132 }
6133
6134 /*
6135  * remove a 5tuple filter
6136  *
6137  * @param
6138  * dev: Pointer to struct rte_eth_dev.
6139  * filter: the pointer of the filter will be removed.
6140  */
6141 static void
6142 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6143                         struct ixgbe_5tuple_filter *filter)
6144 {
6145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6146         struct ixgbe_filter_info *filter_info =
6147                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6148         uint16_t index = filter->index;
6149
6150         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6151                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6152         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6153         rte_free(filter);
6154
6155         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6156         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6157         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6158         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6159         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6160 }
6161
6162 static int
6163 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6164 {
6165         struct ixgbe_hw *hw;
6166         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6167         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6168
6169         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6170
6171         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6172                 return -EINVAL;
6173
6174         /* refuse mtu that requires the support of scattered packets when this
6175          * feature has not been enabled before.
6176          */
6177         if (!rx_conf->enable_scatter &&
6178             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6179              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6180                 return -EINVAL;
6181
6182         /*
6183          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6184          * request of the version 2.0 of the mailbox API.
6185          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6186          * of the mailbox API.
6187          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6188          * prior to 3.11.33 which contains the following change:
6189          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6190          */
6191         ixgbevf_rlpml_set_vf(hw, max_frame);
6192
6193         /* update max frame size */
6194         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6195         return 0;
6196 }
6197
6198 static inline struct ixgbe_5tuple_filter *
6199 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6200                         struct ixgbe_5tuple_filter_info *key)
6201 {
6202         struct ixgbe_5tuple_filter *it;
6203
6204         TAILQ_FOREACH(it, filter_list, entries) {
6205                 if (memcmp(key, &it->filter_info,
6206                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6207                         return it;
6208                 }
6209         }
6210         return NULL;
6211 }
6212
6213 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6214 static inline int
6215 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6216                         struct ixgbe_5tuple_filter_info *filter_info)
6217 {
6218         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6219                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6220                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6221                 return -EINVAL;
6222
6223         switch (filter->dst_ip_mask) {
6224         case UINT32_MAX:
6225                 filter_info->dst_ip_mask = 0;
6226                 filter_info->dst_ip = filter->dst_ip;
6227                 break;
6228         case 0:
6229                 filter_info->dst_ip_mask = 1;
6230                 break;
6231         default:
6232                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6233                 return -EINVAL;
6234         }
6235
6236         switch (filter->src_ip_mask) {
6237         case UINT32_MAX:
6238                 filter_info->src_ip_mask = 0;
6239                 filter_info->src_ip = filter->src_ip;
6240                 break;
6241         case 0:
6242                 filter_info->src_ip_mask = 1;
6243                 break;
6244         default:
6245                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6246                 return -EINVAL;
6247         }
6248
6249         switch (filter->dst_port_mask) {
6250         case UINT16_MAX:
6251                 filter_info->dst_port_mask = 0;
6252                 filter_info->dst_port = filter->dst_port;
6253                 break;
6254         case 0:
6255                 filter_info->dst_port_mask = 1;
6256                 break;
6257         default:
6258                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6259                 return -EINVAL;
6260         }
6261
6262         switch (filter->src_port_mask) {
6263         case UINT16_MAX:
6264                 filter_info->src_port_mask = 0;
6265                 filter_info->src_port = filter->src_port;
6266                 break;
6267         case 0:
6268                 filter_info->src_port_mask = 1;
6269                 break;
6270         default:
6271                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6272                 return -EINVAL;
6273         }
6274
6275         switch (filter->proto_mask) {
6276         case UINT8_MAX:
6277                 filter_info->proto_mask = 0;
6278                 filter_info->proto =
6279                         convert_protocol_type(filter->proto);
6280                 break;
6281         case 0:
6282                 filter_info->proto_mask = 1;
6283                 break;
6284         default:
6285                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6286                 return -EINVAL;
6287         }
6288
6289         filter_info->priority = (uint8_t)filter->priority;
6290         return 0;
6291 }
6292
6293 /*
6294  * add or delete a ntuple filter
6295  *
6296  * @param
6297  * dev: Pointer to struct rte_eth_dev.
6298  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6299  * add: if true, add filter, if false, remove filter
6300  *
6301  * @return
6302  *    - On success, zero.
6303  *    - On failure, a negative value.
6304  */
6305 int
6306 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6307                         struct rte_eth_ntuple_filter *ntuple_filter,
6308                         bool add)
6309 {
6310         struct ixgbe_filter_info *filter_info =
6311                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6312         struct ixgbe_5tuple_filter_info filter_5tuple;
6313         struct ixgbe_5tuple_filter *filter;
6314         int ret;
6315
6316         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6317                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6318                 return -EINVAL;
6319         }
6320
6321         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6322         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6323         if (ret < 0)
6324                 return ret;
6325
6326         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6327                                          &filter_5tuple);
6328         if (filter != NULL && add) {
6329                 PMD_DRV_LOG(ERR, "filter exists.");
6330                 return -EEXIST;
6331         }
6332         if (filter == NULL && !add) {
6333                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6334                 return -ENOENT;
6335         }
6336
6337         if (add) {
6338                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6339                                 sizeof(struct ixgbe_5tuple_filter), 0);
6340                 if (filter == NULL)
6341                         return -ENOMEM;
6342                 rte_memcpy(&filter->filter_info,
6343                                  &filter_5tuple,
6344                                  sizeof(struct ixgbe_5tuple_filter_info));
6345                 filter->queue = ntuple_filter->queue;
6346                 ret = ixgbe_add_5tuple_filter(dev, filter);
6347                 if (ret < 0) {
6348                         rte_free(filter);
6349                         return ret;
6350                 }
6351         } else
6352                 ixgbe_remove_5tuple_filter(dev, filter);
6353
6354         return 0;
6355 }
6356
6357 /*
6358  * get a ntuple filter
6359  *
6360  * @param
6361  * dev: Pointer to struct rte_eth_dev.
6362  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6363  *
6364  * @return
6365  *    - On success, zero.
6366  *    - On failure, a negative value.
6367  */
6368 static int
6369 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6370                         struct rte_eth_ntuple_filter *ntuple_filter)
6371 {
6372         struct ixgbe_filter_info *filter_info =
6373                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6374         struct ixgbe_5tuple_filter_info filter_5tuple;
6375         struct ixgbe_5tuple_filter *filter;
6376         int ret;
6377
6378         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6379                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6380                 return -EINVAL;
6381         }
6382
6383         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6384         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6385         if (ret < 0)
6386                 return ret;
6387
6388         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6389                                          &filter_5tuple);
6390         if (filter == NULL) {
6391                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6392                 return -ENOENT;
6393         }
6394         ntuple_filter->queue = filter->queue;
6395         return 0;
6396 }
6397
6398 /*
6399  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6400  * @dev: pointer to rte_eth_dev structure
6401  * @filter_op:operation will be taken.
6402  * @arg: a pointer to specific structure corresponding to the filter_op
6403  *
6404  * @return
6405  *    - On success, zero.
6406  *    - On failure, a negative value.
6407  */
6408 static int
6409 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6410                                 enum rte_filter_op filter_op,
6411                                 void *arg)
6412 {
6413         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6414         int ret;
6415
6416         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6417
6418         if (filter_op == RTE_ETH_FILTER_NOP)
6419                 return 0;
6420
6421         if (arg == NULL) {
6422                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6423                             filter_op);
6424                 return -EINVAL;
6425         }
6426
6427         switch (filter_op) {
6428         case RTE_ETH_FILTER_ADD:
6429                 ret = ixgbe_add_del_ntuple_filter(dev,
6430                         (struct rte_eth_ntuple_filter *)arg,
6431                         TRUE);
6432                 break;
6433         case RTE_ETH_FILTER_DELETE:
6434                 ret = ixgbe_add_del_ntuple_filter(dev,
6435                         (struct rte_eth_ntuple_filter *)arg,
6436                         FALSE);
6437                 break;
6438         case RTE_ETH_FILTER_GET:
6439                 ret = ixgbe_get_ntuple_filter(dev,
6440                         (struct rte_eth_ntuple_filter *)arg);
6441                 break;
6442         default:
6443                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6444                 ret = -EINVAL;
6445                 break;
6446         }
6447         return ret;
6448 }
6449
6450 int
6451 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6452                         struct rte_eth_ethertype_filter *filter,
6453                         bool add)
6454 {
6455         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6456         struct ixgbe_filter_info *filter_info =
6457                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6458         uint32_t etqf = 0;
6459         uint32_t etqs = 0;
6460         int ret;
6461         struct ixgbe_ethertype_filter ethertype_filter;
6462
6463         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6464                 return -EINVAL;
6465
6466         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6467                 filter->ether_type == ETHER_TYPE_IPv6) {
6468                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6469                         " ethertype filter.", filter->ether_type);
6470                 return -EINVAL;
6471         }
6472
6473         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6474                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6475                 return -EINVAL;
6476         }
6477         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6478                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6479                 return -EINVAL;
6480         }
6481
6482         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6483         if (ret >= 0 && add) {
6484                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6485                             filter->ether_type);
6486                 return -EEXIST;
6487         }
6488         if (ret < 0 && !add) {
6489                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6490                             filter->ether_type);
6491                 return -ENOENT;
6492         }
6493
6494         if (add) {
6495                 etqf = IXGBE_ETQF_FILTER_EN;
6496                 etqf |= (uint32_t)filter->ether_type;
6497                 etqs |= (uint32_t)((filter->queue <<
6498                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6499                                     IXGBE_ETQS_RX_QUEUE);
6500                 etqs |= IXGBE_ETQS_QUEUE_EN;
6501
6502                 ethertype_filter.ethertype = filter->ether_type;
6503                 ethertype_filter.etqf = etqf;
6504                 ethertype_filter.etqs = etqs;
6505                 ethertype_filter.conf = FALSE;
6506                 ret = ixgbe_ethertype_filter_insert(filter_info,
6507                                                     &ethertype_filter);
6508                 if (ret < 0) {
6509                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6510                         return -ENOSPC;
6511                 }
6512         } else {
6513                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6514                 if (ret < 0)
6515                         return -ENOSYS;
6516         }
6517         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6518         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6519         IXGBE_WRITE_FLUSH(hw);
6520
6521         return 0;
6522 }
6523
6524 static int
6525 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6526                         struct rte_eth_ethertype_filter *filter)
6527 {
6528         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6529         struct ixgbe_filter_info *filter_info =
6530                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6531         uint32_t etqf, etqs;
6532         int ret;
6533
6534         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6535         if (ret < 0) {
6536                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6537                             filter->ether_type);
6538                 return -ENOENT;
6539         }
6540
6541         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6542         if (etqf & IXGBE_ETQF_FILTER_EN) {
6543                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6544                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6545                 filter->flags = 0;
6546                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6547                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6548                 return 0;
6549         }
6550         return -ENOENT;
6551 }
6552
6553 /*
6554  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6555  * @dev: pointer to rte_eth_dev structure
6556  * @filter_op:operation will be taken.
6557  * @arg: a pointer to specific structure corresponding to the filter_op
6558  */
6559 static int
6560 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6561                                 enum rte_filter_op filter_op,
6562                                 void *arg)
6563 {
6564         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6565         int ret;
6566
6567         MAC_TYPE_FILTER_SUP(hw->mac.type);
6568
6569         if (filter_op == RTE_ETH_FILTER_NOP)
6570                 return 0;
6571
6572         if (arg == NULL) {
6573                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6574                             filter_op);
6575                 return -EINVAL;
6576         }
6577
6578         switch (filter_op) {
6579         case RTE_ETH_FILTER_ADD:
6580                 ret = ixgbe_add_del_ethertype_filter(dev,
6581                         (struct rte_eth_ethertype_filter *)arg,
6582                         TRUE);
6583                 break;
6584         case RTE_ETH_FILTER_DELETE:
6585                 ret = ixgbe_add_del_ethertype_filter(dev,
6586                         (struct rte_eth_ethertype_filter *)arg,
6587                         FALSE);
6588                 break;
6589         case RTE_ETH_FILTER_GET:
6590                 ret = ixgbe_get_ethertype_filter(dev,
6591                         (struct rte_eth_ethertype_filter *)arg);
6592                 break;
6593         default:
6594                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6595                 ret = -EINVAL;
6596                 break;
6597         }
6598         return ret;
6599 }
6600
6601 static int
6602 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6603                      enum rte_filter_type filter_type,
6604                      enum rte_filter_op filter_op,
6605                      void *arg)
6606 {
6607         int ret = 0;
6608
6609         switch (filter_type) {
6610         case RTE_ETH_FILTER_NTUPLE:
6611                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6612                 break;
6613         case RTE_ETH_FILTER_ETHERTYPE:
6614                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6615                 break;
6616         case RTE_ETH_FILTER_SYN:
6617                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6618                 break;
6619         case RTE_ETH_FILTER_FDIR:
6620                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6621                 break;
6622         case RTE_ETH_FILTER_L2_TUNNEL:
6623                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6624                 break;
6625         case RTE_ETH_FILTER_GENERIC:
6626                 if (filter_op != RTE_ETH_FILTER_GET)
6627                         return -EINVAL;
6628                 *(const void **)arg = &ixgbe_flow_ops;
6629                 break;
6630         default:
6631                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6632                                                         filter_type);
6633                 ret = -EINVAL;
6634                 break;
6635         }
6636
6637         return ret;
6638 }
6639
6640 static u8 *
6641 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6642                         u8 **mc_addr_ptr, u32 *vmdq)
6643 {
6644         u8 *mc_addr;
6645
6646         *vmdq = 0;
6647         mc_addr = *mc_addr_ptr;
6648         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6649         return mc_addr;
6650 }
6651
6652 static int
6653 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6654                           struct ether_addr *mc_addr_set,
6655                           uint32_t nb_mc_addr)
6656 {
6657         struct ixgbe_hw *hw;
6658         u8 *mc_addr_list;
6659
6660         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6661         mc_addr_list = (u8 *)mc_addr_set;
6662         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6663                                          ixgbe_dev_addr_list_itr, TRUE);
6664 }
6665
6666 static uint64_t
6667 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6668 {
6669         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6670         uint64_t systime_cycles;
6671
6672         switch (hw->mac.type) {
6673         case ixgbe_mac_X550:
6674         case ixgbe_mac_X550EM_x:
6675         case ixgbe_mac_X550EM_a:
6676                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6677                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6678                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6679                                 * NSEC_PER_SEC;
6680                 break;
6681         default:
6682                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6683                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6684                                 << 32;
6685         }
6686
6687         return systime_cycles;
6688 }
6689
6690 static uint64_t
6691 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6692 {
6693         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6694         uint64_t rx_tstamp_cycles;
6695
6696         switch (hw->mac.type) {
6697         case ixgbe_mac_X550:
6698         case ixgbe_mac_X550EM_x:
6699         case ixgbe_mac_X550EM_a:
6700                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6701                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6702                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6703                                 * NSEC_PER_SEC;
6704                 break;
6705         default:
6706                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6707                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6708                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6709                                 << 32;
6710         }
6711
6712         return rx_tstamp_cycles;
6713 }
6714
6715 static uint64_t
6716 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6717 {
6718         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6719         uint64_t tx_tstamp_cycles;
6720
6721         switch (hw->mac.type) {
6722         case ixgbe_mac_X550:
6723         case ixgbe_mac_X550EM_x:
6724         case ixgbe_mac_X550EM_a:
6725                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6726                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6727                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6728                                 * NSEC_PER_SEC;
6729                 break;
6730         default:
6731                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6732                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6733                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6734                                 << 32;
6735         }
6736
6737         return tx_tstamp_cycles;
6738 }
6739
6740 static void
6741 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6742 {
6743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6744         struct ixgbe_adapter *adapter =
6745                 (struct ixgbe_adapter *)dev->data->dev_private;
6746         struct rte_eth_link link;
6747         uint32_t incval = 0;
6748         uint32_t shift = 0;
6749
6750         /* Get current link speed. */
6751         ixgbe_dev_link_update(dev, 1);
6752         rte_eth_linkstatus_get(dev, &link);
6753
6754         switch (link.link_speed) {
6755         case ETH_SPEED_NUM_100M:
6756                 incval = IXGBE_INCVAL_100;
6757                 shift = IXGBE_INCVAL_SHIFT_100;
6758                 break;
6759         case ETH_SPEED_NUM_1G:
6760                 incval = IXGBE_INCVAL_1GB;
6761                 shift = IXGBE_INCVAL_SHIFT_1GB;
6762                 break;
6763         case ETH_SPEED_NUM_10G:
6764         default:
6765                 incval = IXGBE_INCVAL_10GB;
6766                 shift = IXGBE_INCVAL_SHIFT_10GB;
6767                 break;
6768         }
6769
6770         switch (hw->mac.type) {
6771         case ixgbe_mac_X550:
6772         case ixgbe_mac_X550EM_x:
6773         case ixgbe_mac_X550EM_a:
6774                 /* Independent of link speed. */
6775                 incval = 1;
6776                 /* Cycles read will be interpreted as ns. */
6777                 shift = 0;
6778                 /* Fall-through */
6779         case ixgbe_mac_X540:
6780                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6781                 break;
6782         case ixgbe_mac_82599EB:
6783                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6784                 shift -= IXGBE_INCVAL_SHIFT_82599;
6785                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6786                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6787                 break;
6788         default:
6789                 /* Not supported. */
6790                 return;
6791         }
6792
6793         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6794         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6795         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6796
6797         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6798         adapter->systime_tc.cc_shift = shift;
6799         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6800
6801         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6802         adapter->rx_tstamp_tc.cc_shift = shift;
6803         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6804
6805         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6806         adapter->tx_tstamp_tc.cc_shift = shift;
6807         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6808 }
6809
6810 static int
6811 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6812 {
6813         struct ixgbe_adapter *adapter =
6814                         (struct ixgbe_adapter *)dev->data->dev_private;
6815
6816         adapter->systime_tc.nsec += delta;
6817         adapter->rx_tstamp_tc.nsec += delta;
6818         adapter->tx_tstamp_tc.nsec += delta;
6819
6820         return 0;
6821 }
6822
6823 static int
6824 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6825 {
6826         uint64_t ns;
6827         struct ixgbe_adapter *adapter =
6828                         (struct ixgbe_adapter *)dev->data->dev_private;
6829
6830         ns = rte_timespec_to_ns(ts);
6831         /* Set the timecounters to a new value. */
6832         adapter->systime_tc.nsec = ns;
6833         adapter->rx_tstamp_tc.nsec = ns;
6834         adapter->tx_tstamp_tc.nsec = ns;
6835
6836         return 0;
6837 }
6838
6839 static int
6840 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6841 {
6842         uint64_t ns, systime_cycles;
6843         struct ixgbe_adapter *adapter =
6844                         (struct ixgbe_adapter *)dev->data->dev_private;
6845
6846         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6847         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6848         *ts = rte_ns_to_timespec(ns);
6849
6850         return 0;
6851 }
6852
6853 static int
6854 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6855 {
6856         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6857         uint32_t tsync_ctl;
6858         uint32_t tsauxc;
6859
6860         /* Stop the timesync system time. */
6861         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6862         /* Reset the timesync system time value. */
6863         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6864         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6865
6866         /* Enable system time for platforms where it isn't on by default. */
6867         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6868         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6869         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6870
6871         ixgbe_start_timecounters(dev);
6872
6873         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6874         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6875                         (ETHER_TYPE_1588 |
6876                          IXGBE_ETQF_FILTER_EN |
6877                          IXGBE_ETQF_1588));
6878
6879         /* Enable timestamping of received PTP packets. */
6880         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6881         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6882         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6883
6884         /* Enable timestamping of transmitted PTP packets. */
6885         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6886         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6887         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6888
6889         IXGBE_WRITE_FLUSH(hw);
6890
6891         return 0;
6892 }
6893
6894 static int
6895 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6896 {
6897         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6898         uint32_t tsync_ctl;
6899
6900         /* Disable timestamping of transmitted PTP packets. */
6901         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6902         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6903         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6904
6905         /* Disable timestamping of received PTP packets. */
6906         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6907         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6908         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6909
6910         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6911         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6912
6913         /* Stop incrementating the System Time registers. */
6914         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6915
6916         return 0;
6917 }
6918
6919 static int
6920 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6921                                  struct timespec *timestamp,
6922                                  uint32_t flags __rte_unused)
6923 {
6924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6925         struct ixgbe_adapter *adapter =
6926                 (struct ixgbe_adapter *)dev->data->dev_private;
6927         uint32_t tsync_rxctl;
6928         uint64_t rx_tstamp_cycles;
6929         uint64_t ns;
6930
6931         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6932         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6933                 return -EINVAL;
6934
6935         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6936         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6937         *timestamp = rte_ns_to_timespec(ns);
6938
6939         return  0;
6940 }
6941
6942 static int
6943 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6944                                  struct timespec *timestamp)
6945 {
6946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6947         struct ixgbe_adapter *adapter =
6948                 (struct ixgbe_adapter *)dev->data->dev_private;
6949         uint32_t tsync_txctl;
6950         uint64_t tx_tstamp_cycles;
6951         uint64_t ns;
6952
6953         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6954         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6955                 return -EINVAL;
6956
6957         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6958         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6959         *timestamp = rte_ns_to_timespec(ns);
6960
6961         return 0;
6962 }
6963
6964 static int
6965 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6966 {
6967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6968         int count = 0;
6969         int g_ind = 0;
6970         const struct reg_info *reg_group;
6971         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6972                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6973
6974         while ((reg_group = reg_set[g_ind++]))
6975                 count += ixgbe_regs_group_count(reg_group);
6976
6977         return count;
6978 }
6979
6980 static int
6981 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6982 {
6983         int count = 0;
6984         int g_ind = 0;
6985         const struct reg_info *reg_group;
6986
6987         while ((reg_group = ixgbevf_regs[g_ind++]))
6988                 count += ixgbe_regs_group_count(reg_group);
6989
6990         return count;
6991 }
6992
6993 static int
6994 ixgbe_get_regs(struct rte_eth_dev *dev,
6995               struct rte_dev_reg_info *regs)
6996 {
6997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6998         uint32_t *data = regs->data;
6999         int g_ind = 0;
7000         int count = 0;
7001         const struct reg_info *reg_group;
7002         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7003                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7004
7005         if (data == NULL) {
7006                 regs->length = ixgbe_get_reg_length(dev);
7007                 regs->width = sizeof(uint32_t);
7008                 return 0;
7009         }
7010
7011         /* Support only full register dump */
7012         if ((regs->length == 0) ||
7013             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7014                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7015                         hw->device_id;
7016                 while ((reg_group = reg_set[g_ind++]))
7017                         count += ixgbe_read_regs_group(dev, &data[count],
7018                                 reg_group);
7019                 return 0;
7020         }
7021
7022         return -ENOTSUP;
7023 }
7024
7025 static int
7026 ixgbevf_get_regs(struct rte_eth_dev *dev,
7027                 struct rte_dev_reg_info *regs)
7028 {
7029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7030         uint32_t *data = regs->data;
7031         int g_ind = 0;
7032         int count = 0;
7033         const struct reg_info *reg_group;
7034
7035         if (data == NULL) {
7036                 regs->length = ixgbevf_get_reg_length(dev);
7037                 regs->width = sizeof(uint32_t);
7038                 return 0;
7039         }
7040
7041         /* Support only full register dump */
7042         if ((regs->length == 0) ||
7043             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7044                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7045                         hw->device_id;
7046                 while ((reg_group = ixgbevf_regs[g_ind++]))
7047                         count += ixgbe_read_regs_group(dev, &data[count],
7048                                                       reg_group);
7049                 return 0;
7050         }
7051
7052         return -ENOTSUP;
7053 }
7054
7055 static int
7056 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7057 {
7058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7059
7060         /* Return unit is byte count */
7061         return hw->eeprom.word_size * 2;
7062 }
7063
7064 static int
7065 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7066                 struct rte_dev_eeprom_info *in_eeprom)
7067 {
7068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7069         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7070         uint16_t *data = in_eeprom->data;
7071         int first, length;
7072
7073         first = in_eeprom->offset >> 1;
7074         length = in_eeprom->length >> 1;
7075         if ((first > hw->eeprom.word_size) ||
7076             ((first + length) > hw->eeprom.word_size))
7077                 return -EINVAL;
7078
7079         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7080
7081         return eeprom->ops.read_buffer(hw, first, length, data);
7082 }
7083
7084 static int
7085 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7086                 struct rte_dev_eeprom_info *in_eeprom)
7087 {
7088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7089         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7090         uint16_t *data = in_eeprom->data;
7091         int first, length;
7092
7093         first = in_eeprom->offset >> 1;
7094         length = in_eeprom->length >> 1;
7095         if ((first > hw->eeprom.word_size) ||
7096             ((first + length) > hw->eeprom.word_size))
7097                 return -EINVAL;
7098
7099         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7100
7101         return eeprom->ops.write_buffer(hw,  first, length, data);
7102 }
7103
7104 uint16_t
7105 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7106         switch (mac_type) {
7107         case ixgbe_mac_X550:
7108         case ixgbe_mac_X550EM_x:
7109         case ixgbe_mac_X550EM_a:
7110                 return ETH_RSS_RETA_SIZE_512;
7111         case ixgbe_mac_X550_vf:
7112         case ixgbe_mac_X550EM_x_vf:
7113         case ixgbe_mac_X550EM_a_vf:
7114                 return ETH_RSS_RETA_SIZE_64;
7115         default:
7116                 return ETH_RSS_RETA_SIZE_128;
7117         }
7118 }
7119
7120 uint32_t
7121 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7122         switch (mac_type) {
7123         case ixgbe_mac_X550:
7124         case ixgbe_mac_X550EM_x:
7125         case ixgbe_mac_X550EM_a:
7126                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7127                         return IXGBE_RETA(reta_idx >> 2);
7128                 else
7129                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7130         case ixgbe_mac_X550_vf:
7131         case ixgbe_mac_X550EM_x_vf:
7132         case ixgbe_mac_X550EM_a_vf:
7133                 return IXGBE_VFRETA(reta_idx >> 2);
7134         default:
7135                 return IXGBE_RETA(reta_idx >> 2);
7136         }
7137 }
7138
7139 uint32_t
7140 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7141         switch (mac_type) {
7142         case ixgbe_mac_X550_vf:
7143         case ixgbe_mac_X550EM_x_vf:
7144         case ixgbe_mac_X550EM_a_vf:
7145                 return IXGBE_VFMRQC;
7146         default:
7147                 return IXGBE_MRQC;
7148         }
7149 }
7150
7151 uint32_t
7152 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7153         switch (mac_type) {
7154         case ixgbe_mac_X550_vf:
7155         case ixgbe_mac_X550EM_x_vf:
7156         case ixgbe_mac_X550EM_a_vf:
7157                 return IXGBE_VFRSSRK(i);
7158         default:
7159                 return IXGBE_RSSRK(i);
7160         }
7161 }
7162
7163 bool
7164 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7165         switch (mac_type) {
7166         case ixgbe_mac_82599_vf:
7167         case ixgbe_mac_X540_vf:
7168                 return 0;
7169         default:
7170                 return 1;
7171         }
7172 }
7173
7174 static int
7175 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7176                         struct rte_eth_dcb_info *dcb_info)
7177 {
7178         struct ixgbe_dcb_config *dcb_config =
7179                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7180         struct ixgbe_dcb_tc_config *tc;
7181         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7182         uint8_t nb_tcs;
7183         uint8_t i, j;
7184
7185         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7186                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7187         else
7188                 dcb_info->nb_tcs = 1;
7189
7190         tc_queue = &dcb_info->tc_queue;
7191         nb_tcs = dcb_info->nb_tcs;
7192
7193         if (dcb_config->vt_mode) { /* vt is enabled*/
7194                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7195                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7196                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7197                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7198                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7199                         for (j = 0; j < nb_tcs; j++) {
7200                                 tc_queue->tc_rxq[0][j].base = j;
7201                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7202                                 tc_queue->tc_txq[0][j].base = j;
7203                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7204                         }
7205                 } else {
7206                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7207                                 for (j = 0; j < nb_tcs; j++) {
7208                                         tc_queue->tc_rxq[i][j].base =
7209                                                 i * nb_tcs + j;
7210                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7211                                         tc_queue->tc_txq[i][j].base =
7212                                                 i * nb_tcs + j;
7213                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7214                                 }
7215                         }
7216                 }
7217         } else { /* vt is disabled*/
7218                 struct rte_eth_dcb_rx_conf *rx_conf =
7219                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7220                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7221                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7222                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7223                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7224                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7225                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7226                         }
7227                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7228                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7229                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7230                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7231                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7232                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7233                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7234                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7235                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7236                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7237                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7238                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7239                         }
7240                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7241                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7242                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7243                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7244                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7245                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7246                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7247                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7248                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7249                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7250                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7251                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7252                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7253                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7254                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7255                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7256                 }
7257         }
7258         for (i = 0; i < dcb_info->nb_tcs; i++) {
7259                 tc = &dcb_config->tc_config[i];
7260                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7261         }
7262         return 0;
7263 }
7264
7265 /* Update e-tag ether type */
7266 static int
7267 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7268                             uint16_t ether_type)
7269 {
7270         uint32_t etag_etype;
7271
7272         if (hw->mac.type != ixgbe_mac_X550 &&
7273             hw->mac.type != ixgbe_mac_X550EM_x &&
7274             hw->mac.type != ixgbe_mac_X550EM_a) {
7275                 return -ENOTSUP;
7276         }
7277
7278         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7279         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7280         etag_etype |= ether_type;
7281         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7282         IXGBE_WRITE_FLUSH(hw);
7283
7284         return 0;
7285 }
7286
7287 /* Config l2 tunnel ether type */
7288 static int
7289 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7290                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7291 {
7292         int ret = 0;
7293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7294         struct ixgbe_l2_tn_info *l2_tn_info =
7295                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7296
7297         if (l2_tunnel == NULL)
7298                 return -EINVAL;
7299
7300         switch (l2_tunnel->l2_tunnel_type) {
7301         case RTE_L2_TUNNEL_TYPE_E_TAG:
7302                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7303                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7304                 break;
7305         default:
7306                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7307                 ret = -EINVAL;
7308                 break;
7309         }
7310
7311         return ret;
7312 }
7313
7314 /* Enable e-tag tunnel */
7315 static int
7316 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7317 {
7318         uint32_t etag_etype;
7319
7320         if (hw->mac.type != ixgbe_mac_X550 &&
7321             hw->mac.type != ixgbe_mac_X550EM_x &&
7322             hw->mac.type != ixgbe_mac_X550EM_a) {
7323                 return -ENOTSUP;
7324         }
7325
7326         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7327         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7328         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7329         IXGBE_WRITE_FLUSH(hw);
7330
7331         return 0;
7332 }
7333
7334 /* Enable l2 tunnel */
7335 static int
7336 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7337                            enum rte_eth_tunnel_type l2_tunnel_type)
7338 {
7339         int ret = 0;
7340         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7341         struct ixgbe_l2_tn_info *l2_tn_info =
7342                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7343
7344         switch (l2_tunnel_type) {
7345         case RTE_L2_TUNNEL_TYPE_E_TAG:
7346                 l2_tn_info->e_tag_en = TRUE;
7347                 ret = ixgbe_e_tag_enable(hw);
7348                 break;
7349         default:
7350                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7351                 ret = -EINVAL;
7352                 break;
7353         }
7354
7355         return ret;
7356 }
7357
7358 /* Disable e-tag tunnel */
7359 static int
7360 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7361 {
7362         uint32_t etag_etype;
7363
7364         if (hw->mac.type != ixgbe_mac_X550 &&
7365             hw->mac.type != ixgbe_mac_X550EM_x &&
7366             hw->mac.type != ixgbe_mac_X550EM_a) {
7367                 return -ENOTSUP;
7368         }
7369
7370         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7371         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7372         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7373         IXGBE_WRITE_FLUSH(hw);
7374
7375         return 0;
7376 }
7377
7378 /* Disable l2 tunnel */
7379 static int
7380 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7381                             enum rte_eth_tunnel_type l2_tunnel_type)
7382 {
7383         int ret = 0;
7384         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7385         struct ixgbe_l2_tn_info *l2_tn_info =
7386                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7387
7388         switch (l2_tunnel_type) {
7389         case RTE_L2_TUNNEL_TYPE_E_TAG:
7390                 l2_tn_info->e_tag_en = FALSE;
7391                 ret = ixgbe_e_tag_disable(hw);
7392                 break;
7393         default:
7394                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7395                 ret = -EINVAL;
7396                 break;
7397         }
7398
7399         return ret;
7400 }
7401
7402 static int
7403 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7404                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7405 {
7406         int ret = 0;
7407         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7408         uint32_t i, rar_entries;
7409         uint32_t rar_low, rar_high;
7410
7411         if (hw->mac.type != ixgbe_mac_X550 &&
7412             hw->mac.type != ixgbe_mac_X550EM_x &&
7413             hw->mac.type != ixgbe_mac_X550EM_a) {
7414                 return -ENOTSUP;
7415         }
7416
7417         rar_entries = ixgbe_get_num_rx_addrs(hw);
7418
7419         for (i = 1; i < rar_entries; i++) {
7420                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7421                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7422                 if ((rar_high & IXGBE_RAH_AV) &&
7423                     (rar_high & IXGBE_RAH_ADTYPE) &&
7424                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7425                      l2_tunnel->tunnel_id)) {
7426                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7427                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7428
7429                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7430
7431                         return ret;
7432                 }
7433         }
7434
7435         return ret;
7436 }
7437
7438 static int
7439 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7440                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7441 {
7442         int ret = 0;
7443         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7444         uint32_t i, rar_entries;
7445         uint32_t rar_low, rar_high;
7446
7447         if (hw->mac.type != ixgbe_mac_X550 &&
7448             hw->mac.type != ixgbe_mac_X550EM_x &&
7449             hw->mac.type != ixgbe_mac_X550EM_a) {
7450                 return -ENOTSUP;
7451         }
7452
7453         /* One entry for one tunnel. Try to remove potential existing entry. */
7454         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7455
7456         rar_entries = ixgbe_get_num_rx_addrs(hw);
7457
7458         for (i = 1; i < rar_entries; i++) {
7459                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7460                 if (rar_high & IXGBE_RAH_AV) {
7461                         continue;
7462                 } else {
7463                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7464                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7465                         rar_low = l2_tunnel->tunnel_id;
7466
7467                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7468                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7469
7470                         return ret;
7471                 }
7472         }
7473
7474         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7475                      " Please remove a rule before adding a new one.");
7476         return -EINVAL;
7477 }
7478
7479 static inline struct ixgbe_l2_tn_filter *
7480 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7481                           struct ixgbe_l2_tn_key *key)
7482 {
7483         int ret;
7484
7485         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7486         if (ret < 0)
7487                 return NULL;
7488
7489         return l2_tn_info->hash_map[ret];
7490 }
7491
7492 static inline int
7493 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7494                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7495 {
7496         int ret;
7497
7498         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7499                                &l2_tn_filter->key);
7500
7501         if (ret < 0) {
7502                 PMD_DRV_LOG(ERR,
7503                             "Failed to insert L2 tunnel filter"
7504                             " to hash table %d!",
7505                             ret);
7506                 return ret;
7507         }
7508
7509         l2_tn_info->hash_map[ret] = l2_tn_filter;
7510
7511         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7512
7513         return 0;
7514 }
7515
7516 static inline int
7517 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7518                           struct ixgbe_l2_tn_key *key)
7519 {
7520         int ret;
7521         struct ixgbe_l2_tn_filter *l2_tn_filter;
7522
7523         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7524
7525         if (ret < 0) {
7526                 PMD_DRV_LOG(ERR,
7527                             "No such L2 tunnel filter to delete %d!",
7528                             ret);
7529                 return ret;
7530         }
7531
7532         l2_tn_filter = l2_tn_info->hash_map[ret];
7533         l2_tn_info->hash_map[ret] = NULL;
7534
7535         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7536         rte_free(l2_tn_filter);
7537
7538         return 0;
7539 }
7540
7541 /* Add l2 tunnel filter */
7542 int
7543 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7544                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7545                                bool restore)
7546 {
7547         int ret;
7548         struct ixgbe_l2_tn_info *l2_tn_info =
7549                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7550         struct ixgbe_l2_tn_key key;
7551         struct ixgbe_l2_tn_filter *node;
7552
7553         if (!restore) {
7554                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7555                 key.tn_id = l2_tunnel->tunnel_id;
7556
7557                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7558
7559                 if (node) {
7560                         PMD_DRV_LOG(ERR,
7561                                     "The L2 tunnel filter already exists!");
7562                         return -EINVAL;
7563                 }
7564
7565                 node = rte_zmalloc("ixgbe_l2_tn",
7566                                    sizeof(struct ixgbe_l2_tn_filter),
7567                                    0);
7568                 if (!node)
7569                         return -ENOMEM;
7570
7571                 rte_memcpy(&node->key,
7572                                  &key,
7573                                  sizeof(struct ixgbe_l2_tn_key));
7574                 node->pool = l2_tunnel->pool;
7575                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7576                 if (ret < 0) {
7577                         rte_free(node);
7578                         return ret;
7579                 }
7580         }
7581
7582         switch (l2_tunnel->l2_tunnel_type) {
7583         case RTE_L2_TUNNEL_TYPE_E_TAG:
7584                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7585                 break;
7586         default:
7587                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7588                 ret = -EINVAL;
7589                 break;
7590         }
7591
7592         if ((!restore) && (ret < 0))
7593                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7594
7595         return ret;
7596 }
7597
7598 /* Delete l2 tunnel filter */
7599 int
7600 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7601                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7602 {
7603         int ret;
7604         struct ixgbe_l2_tn_info *l2_tn_info =
7605                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7606         struct ixgbe_l2_tn_key key;
7607
7608         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7609         key.tn_id = l2_tunnel->tunnel_id;
7610         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7611         if (ret < 0)
7612                 return ret;
7613
7614         switch (l2_tunnel->l2_tunnel_type) {
7615         case RTE_L2_TUNNEL_TYPE_E_TAG:
7616                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7617                 break;
7618         default:
7619                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7620                 ret = -EINVAL;
7621                 break;
7622         }
7623
7624         return ret;
7625 }
7626
7627 /**
7628  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7629  * @dev: pointer to rte_eth_dev structure
7630  * @filter_op:operation will be taken.
7631  * @arg: a pointer to specific structure corresponding to the filter_op
7632  */
7633 static int
7634 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7635                                   enum rte_filter_op filter_op,
7636                                   void *arg)
7637 {
7638         int ret;
7639
7640         if (filter_op == RTE_ETH_FILTER_NOP)
7641                 return 0;
7642
7643         if (arg == NULL) {
7644                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7645                             filter_op);
7646                 return -EINVAL;
7647         }
7648
7649         switch (filter_op) {
7650         case RTE_ETH_FILTER_ADD:
7651                 ret = ixgbe_dev_l2_tunnel_filter_add
7652                         (dev,
7653                          (struct rte_eth_l2_tunnel_conf *)arg,
7654                          FALSE);
7655                 break;
7656         case RTE_ETH_FILTER_DELETE:
7657                 ret = ixgbe_dev_l2_tunnel_filter_del
7658                         (dev,
7659                          (struct rte_eth_l2_tunnel_conf *)arg);
7660                 break;
7661         default:
7662                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7663                 ret = -EINVAL;
7664                 break;
7665         }
7666         return ret;
7667 }
7668
7669 static int
7670 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7671 {
7672         int ret = 0;
7673         uint32_t ctrl;
7674         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7675
7676         if (hw->mac.type != ixgbe_mac_X550 &&
7677             hw->mac.type != ixgbe_mac_X550EM_x &&
7678             hw->mac.type != ixgbe_mac_X550EM_a) {
7679                 return -ENOTSUP;
7680         }
7681
7682         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7683         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7684         if (en)
7685                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7686         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7687
7688         return ret;
7689 }
7690
7691 /* Enable l2 tunnel forwarding */
7692 static int
7693 ixgbe_dev_l2_tunnel_forwarding_enable
7694         (struct rte_eth_dev *dev,
7695          enum rte_eth_tunnel_type l2_tunnel_type)
7696 {
7697         struct ixgbe_l2_tn_info *l2_tn_info =
7698                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7699         int ret = 0;
7700
7701         switch (l2_tunnel_type) {
7702         case RTE_L2_TUNNEL_TYPE_E_TAG:
7703                 l2_tn_info->e_tag_fwd_en = TRUE;
7704                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7705                 break;
7706         default:
7707                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7708                 ret = -EINVAL;
7709                 break;
7710         }
7711
7712         return ret;
7713 }
7714
7715 /* Disable l2 tunnel forwarding */
7716 static int
7717 ixgbe_dev_l2_tunnel_forwarding_disable
7718         (struct rte_eth_dev *dev,
7719          enum rte_eth_tunnel_type l2_tunnel_type)
7720 {
7721         struct ixgbe_l2_tn_info *l2_tn_info =
7722                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7723         int ret = 0;
7724
7725         switch (l2_tunnel_type) {
7726         case RTE_L2_TUNNEL_TYPE_E_TAG:
7727                 l2_tn_info->e_tag_fwd_en = FALSE;
7728                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7729                 break;
7730         default:
7731                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7732                 ret = -EINVAL;
7733                 break;
7734         }
7735
7736         return ret;
7737 }
7738
7739 static int
7740 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7741                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7742                              bool en)
7743 {
7744         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7745         int ret = 0;
7746         uint32_t vmtir, vmvir;
7747         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7748
7749         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7750                 PMD_DRV_LOG(ERR,
7751                             "VF id %u should be less than %u",
7752                             l2_tunnel->vf_id,
7753                             pci_dev->max_vfs);
7754                 return -EINVAL;
7755         }
7756
7757         if (hw->mac.type != ixgbe_mac_X550 &&
7758             hw->mac.type != ixgbe_mac_X550EM_x &&
7759             hw->mac.type != ixgbe_mac_X550EM_a) {
7760                 return -ENOTSUP;
7761         }
7762
7763         if (en)
7764                 vmtir = l2_tunnel->tunnel_id;
7765         else
7766                 vmtir = 0;
7767
7768         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7769
7770         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7771         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7772         if (en)
7773                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7774         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7775
7776         return ret;
7777 }
7778
7779 /* Enable l2 tunnel tag insertion */
7780 static int
7781 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7782                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7783 {
7784         int ret = 0;
7785
7786         switch (l2_tunnel->l2_tunnel_type) {
7787         case RTE_L2_TUNNEL_TYPE_E_TAG:
7788                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7789                 break;
7790         default:
7791                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7792                 ret = -EINVAL;
7793                 break;
7794         }
7795
7796         return ret;
7797 }
7798
7799 /* Disable l2 tunnel tag insertion */
7800 static int
7801 ixgbe_dev_l2_tunnel_insertion_disable
7802         (struct rte_eth_dev *dev,
7803          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7804 {
7805         int ret = 0;
7806
7807         switch (l2_tunnel->l2_tunnel_type) {
7808         case RTE_L2_TUNNEL_TYPE_E_TAG:
7809                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7810                 break;
7811         default:
7812                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7813                 ret = -EINVAL;
7814                 break;
7815         }
7816
7817         return ret;
7818 }
7819
7820 static int
7821 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7822                              bool en)
7823 {
7824         int ret = 0;
7825         uint32_t qde;
7826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7827
7828         if (hw->mac.type != ixgbe_mac_X550 &&
7829             hw->mac.type != ixgbe_mac_X550EM_x &&
7830             hw->mac.type != ixgbe_mac_X550EM_a) {
7831                 return -ENOTSUP;
7832         }
7833
7834         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7835         if (en)
7836                 qde |= IXGBE_QDE_STRIP_TAG;
7837         else
7838                 qde &= ~IXGBE_QDE_STRIP_TAG;
7839         qde &= ~IXGBE_QDE_READ;
7840         qde |= IXGBE_QDE_WRITE;
7841         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7842
7843         return ret;
7844 }
7845
7846 /* Enable l2 tunnel tag stripping */
7847 static int
7848 ixgbe_dev_l2_tunnel_stripping_enable
7849         (struct rte_eth_dev *dev,
7850          enum rte_eth_tunnel_type l2_tunnel_type)
7851 {
7852         int ret = 0;
7853
7854         switch (l2_tunnel_type) {
7855         case RTE_L2_TUNNEL_TYPE_E_TAG:
7856                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7857                 break;
7858         default:
7859                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7860                 ret = -EINVAL;
7861                 break;
7862         }
7863
7864         return ret;
7865 }
7866
7867 /* Disable l2 tunnel tag stripping */
7868 static int
7869 ixgbe_dev_l2_tunnel_stripping_disable
7870         (struct rte_eth_dev *dev,
7871          enum rte_eth_tunnel_type l2_tunnel_type)
7872 {
7873         int ret = 0;
7874
7875         switch (l2_tunnel_type) {
7876         case RTE_L2_TUNNEL_TYPE_E_TAG:
7877                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7878                 break;
7879         default:
7880                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7881                 ret = -EINVAL;
7882                 break;
7883         }
7884
7885         return ret;
7886 }
7887
7888 /* Enable/disable l2 tunnel offload functions */
7889 static int
7890 ixgbe_dev_l2_tunnel_offload_set
7891         (struct rte_eth_dev *dev,
7892          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7893          uint32_t mask,
7894          uint8_t en)
7895 {
7896         int ret = 0;
7897
7898         if (l2_tunnel == NULL)
7899                 return -EINVAL;
7900
7901         ret = -EINVAL;
7902         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7903                 if (en)
7904                         ret = ixgbe_dev_l2_tunnel_enable(
7905                                 dev,
7906                                 l2_tunnel->l2_tunnel_type);
7907                 else
7908                         ret = ixgbe_dev_l2_tunnel_disable(
7909                                 dev,
7910                                 l2_tunnel->l2_tunnel_type);
7911         }
7912
7913         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7914                 if (en)
7915                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7916                                 dev,
7917                                 l2_tunnel);
7918                 else
7919                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7920                                 dev,
7921                                 l2_tunnel);
7922         }
7923
7924         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7925                 if (en)
7926                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7927                                 dev,
7928                                 l2_tunnel->l2_tunnel_type);
7929                 else
7930                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7931                                 dev,
7932                                 l2_tunnel->l2_tunnel_type);
7933         }
7934
7935         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7936                 if (en)
7937                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7938                                 dev,
7939                                 l2_tunnel->l2_tunnel_type);
7940                 else
7941                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7942                                 dev,
7943                                 l2_tunnel->l2_tunnel_type);
7944         }
7945
7946         return ret;
7947 }
7948
7949 static int
7950 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7951                         uint16_t port)
7952 {
7953         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7954         IXGBE_WRITE_FLUSH(hw);
7955
7956         return 0;
7957 }
7958
7959 /* There's only one register for VxLAN UDP port.
7960  * So, we cannot add several ports. Will update it.
7961  */
7962 static int
7963 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7964                      uint16_t port)
7965 {
7966         if (port == 0) {
7967                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7968                 return -EINVAL;
7969         }
7970
7971         return ixgbe_update_vxlan_port(hw, port);
7972 }
7973
7974 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7975  * UDP port, it must have a value.
7976  * So, will reset it to the original value 0.
7977  */
7978 static int
7979 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7980                      uint16_t port)
7981 {
7982         uint16_t cur_port;
7983
7984         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7985
7986         if (cur_port != port) {
7987                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7988                 return -EINVAL;
7989         }
7990
7991         return ixgbe_update_vxlan_port(hw, 0);
7992 }
7993
7994 /* Add UDP tunneling port */
7995 static int
7996 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7997                               struct rte_eth_udp_tunnel *udp_tunnel)
7998 {
7999         int ret = 0;
8000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8001
8002         if (hw->mac.type != ixgbe_mac_X550 &&
8003             hw->mac.type != ixgbe_mac_X550EM_x &&
8004             hw->mac.type != ixgbe_mac_X550EM_a) {
8005                 return -ENOTSUP;
8006         }
8007
8008         if (udp_tunnel == NULL)
8009                 return -EINVAL;
8010
8011         switch (udp_tunnel->prot_type) {
8012         case RTE_TUNNEL_TYPE_VXLAN:
8013                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8014                 break;
8015
8016         case RTE_TUNNEL_TYPE_GENEVE:
8017         case RTE_TUNNEL_TYPE_TEREDO:
8018                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8019                 ret = -EINVAL;
8020                 break;
8021
8022         default:
8023                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8024                 ret = -EINVAL;
8025                 break;
8026         }
8027
8028         return ret;
8029 }
8030
8031 /* Remove UDP tunneling port */
8032 static int
8033 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8034                               struct rte_eth_udp_tunnel *udp_tunnel)
8035 {
8036         int ret = 0;
8037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8038
8039         if (hw->mac.type != ixgbe_mac_X550 &&
8040             hw->mac.type != ixgbe_mac_X550EM_x &&
8041             hw->mac.type != ixgbe_mac_X550EM_a) {
8042                 return -ENOTSUP;
8043         }
8044
8045         if (udp_tunnel == NULL)
8046                 return -EINVAL;
8047
8048         switch (udp_tunnel->prot_type) {
8049         case RTE_TUNNEL_TYPE_VXLAN:
8050                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8051                 break;
8052         case RTE_TUNNEL_TYPE_GENEVE:
8053         case RTE_TUNNEL_TYPE_TEREDO:
8054                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8055                 ret = -EINVAL;
8056                 break;
8057         default:
8058                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8059                 ret = -EINVAL;
8060                 break;
8061         }
8062
8063         return ret;
8064 }
8065
8066 static void
8067 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8068 {
8069         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8070
8071         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8072 }
8073
8074 static void
8075 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8076 {
8077         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8078
8079         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8080 }
8081
8082 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8083 {
8084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8085         u32 in_msg = 0;
8086
8087         /* peek the message first */
8088         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8089
8090         /* PF reset VF event */
8091         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8092                 /* dummy mbx read to ack pf */
8093                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8094                         return;
8095                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8096                                               NULL);
8097         }
8098 }
8099
8100 static int
8101 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8102 {
8103         uint32_t eicr;
8104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8105         struct ixgbe_interrupt *intr =
8106                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8107         ixgbevf_intr_disable(hw);
8108
8109         /* read-on-clear nic registers here */
8110         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8111         intr->flags = 0;
8112
8113         /* only one misc vector supported - mailbox */
8114         eicr &= IXGBE_VTEICR_MASK;
8115         if (eicr == IXGBE_MISC_VEC_ID)
8116                 intr->flags |= IXGBE_FLAG_MAILBOX;
8117
8118         return 0;
8119 }
8120
8121 static int
8122 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8123 {
8124         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8125         struct ixgbe_interrupt *intr =
8126                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8127
8128         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8129                 ixgbevf_mbx_process(dev);
8130                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8131         }
8132
8133         ixgbevf_intr_enable(hw);
8134
8135         return 0;
8136 }
8137
8138 static void
8139 ixgbevf_dev_interrupt_handler(void *param)
8140 {
8141         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8142
8143         ixgbevf_dev_interrupt_get_status(dev);
8144         ixgbevf_dev_interrupt_action(dev);
8145 }
8146
8147 /**
8148  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8149  *  @hw: pointer to hardware structure
8150  *
8151  *  Stops the transmit data path and waits for the HW to internally empty
8152  *  the Tx security block
8153  **/
8154 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8155 {
8156 #define IXGBE_MAX_SECTX_POLL 40
8157
8158         int i;
8159         int sectxreg;
8160
8161         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8162         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8163         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8164         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8165                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8166                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8167                         break;
8168                 /* Use interrupt-safe sleep just in case */
8169                 usec_delay(1000);
8170         }
8171
8172         /* For informational purposes only */
8173         if (i >= IXGBE_MAX_SECTX_POLL)
8174                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8175                          "path fully disabled.  Continuing with init.");
8176
8177         return IXGBE_SUCCESS;
8178 }
8179
8180 /**
8181  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8182  *  @hw: pointer to hardware structure
8183  *
8184  *  Enables the transmit data path.
8185  **/
8186 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8187 {
8188         uint32_t sectxreg;
8189
8190         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8191         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8192         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8193         IXGBE_WRITE_FLUSH(hw);
8194
8195         return IXGBE_SUCCESS;
8196 }
8197
8198 /* restore n-tuple filter */
8199 static inline void
8200 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8201 {
8202         struct ixgbe_filter_info *filter_info =
8203                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8204         struct ixgbe_5tuple_filter *node;
8205
8206         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8207                 ixgbe_inject_5tuple_filter(dev, node);
8208         }
8209 }
8210
8211 /* restore ethernet type filter */
8212 static inline void
8213 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8214 {
8215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8216         struct ixgbe_filter_info *filter_info =
8217                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8218         int i;
8219
8220         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8221                 if (filter_info->ethertype_mask & (1 << i)) {
8222                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8223                                         filter_info->ethertype_filters[i].etqf);
8224                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8225                                         filter_info->ethertype_filters[i].etqs);
8226                         IXGBE_WRITE_FLUSH(hw);
8227                 }
8228         }
8229 }
8230
8231 /* restore SYN filter */
8232 static inline void
8233 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8234 {
8235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8236         struct ixgbe_filter_info *filter_info =
8237                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8238         uint32_t synqf;
8239
8240         synqf = filter_info->syn_info;
8241
8242         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8243                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8244                 IXGBE_WRITE_FLUSH(hw);
8245         }
8246 }
8247
8248 /* restore L2 tunnel filter */
8249 static inline void
8250 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8251 {
8252         struct ixgbe_l2_tn_info *l2_tn_info =
8253                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8254         struct ixgbe_l2_tn_filter *node;
8255         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8256
8257         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8258                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8259                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8260                 l2_tn_conf.pool           = node->pool;
8261                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8262         }
8263 }
8264
8265 /* restore rss filter */
8266 static inline void
8267 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8268 {
8269         struct ixgbe_filter_info *filter_info =
8270                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8271
8272         if (filter_info->rss_info.num)
8273                 ixgbe_config_rss_filter(dev,
8274                         &filter_info->rss_info, TRUE);
8275 }
8276
8277 static int
8278 ixgbe_filter_restore(struct rte_eth_dev *dev)
8279 {
8280         ixgbe_ntuple_filter_restore(dev);
8281         ixgbe_ethertype_filter_restore(dev);
8282         ixgbe_syn_filter_restore(dev);
8283         ixgbe_fdir_filter_restore(dev);
8284         ixgbe_l2_tn_filter_restore(dev);
8285         ixgbe_rss_filter_restore(dev);
8286
8287         return 0;
8288 }
8289
8290 static void
8291 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8292 {
8293         struct ixgbe_l2_tn_info *l2_tn_info =
8294                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8295         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8296
8297         if (l2_tn_info->e_tag_en)
8298                 (void)ixgbe_e_tag_enable(hw);
8299
8300         if (l2_tn_info->e_tag_fwd_en)
8301                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8302
8303         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8304 }
8305
8306 /* remove all the n-tuple filters */
8307 void
8308 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8309 {
8310         struct ixgbe_filter_info *filter_info =
8311                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8312         struct ixgbe_5tuple_filter *p_5tuple;
8313
8314         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8315                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8316 }
8317
8318 /* remove all the ether type filters */
8319 void
8320 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8321 {
8322         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8323         struct ixgbe_filter_info *filter_info =
8324                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8325         int i;
8326
8327         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8328                 if (filter_info->ethertype_mask & (1 << i) &&
8329                     !filter_info->ethertype_filters[i].conf) {
8330                         (void)ixgbe_ethertype_filter_remove(filter_info,
8331                                                             (uint8_t)i);
8332                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8333                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8334                         IXGBE_WRITE_FLUSH(hw);
8335                 }
8336         }
8337 }
8338
8339 /* remove the SYN filter */
8340 void
8341 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8342 {
8343         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8344         struct ixgbe_filter_info *filter_info =
8345                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8346
8347         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8348                 filter_info->syn_info = 0;
8349
8350                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8351                 IXGBE_WRITE_FLUSH(hw);
8352         }
8353 }
8354
8355 /* remove all the L2 tunnel filters */
8356 int
8357 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8358 {
8359         struct ixgbe_l2_tn_info *l2_tn_info =
8360                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8361         struct ixgbe_l2_tn_filter *l2_tn_filter;
8362         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8363         int ret = 0;
8364
8365         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8366                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8367                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8368                 l2_tn_conf.pool           = l2_tn_filter->pool;
8369                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8370                 if (ret < 0)
8371                         return ret;
8372         }
8373
8374         return 0;
8375 }
8376
8377 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8378 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8379 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8380 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8381 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8382 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8383
8384 RTE_INIT(ixgbe_init_log);
8385 static void
8386 ixgbe_init_log(void)
8387 {
8388         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8389         if (ixgbe_logtype_init >= 0)
8390                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8391         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8392         if (ixgbe_logtype_driver >= 0)
8393                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8394 }