drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 #define IXGBE_HKEY_MAX_INDEX 10
 104
 105 /* Additional timesync values. */
 106 #define NSEC_PER_SEC             1000000000L
 107 #define IXGBE_INCVAL_10GB        0x66666666
 108 #define IXGBE_INCVAL_1GB         0x40000000
 109 #define IXGBE_INCVAL_100         0x50000000
 110 #define IXGBE_INCVAL_SHIFT_10GB  28
 111 #define IXGBE_INCVAL_SHIFT_1GB   24
 112 #define IXGBE_INCVAL_SHIFT_100   21
 113 #define IXGBE_INCVAL_SHIFT_82599 7
 114 #define IXGBE_INCPER_SHIFT_82599 24
 115
 116 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 117
 118 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 119 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 120 #define DEFAULT_ETAG_ETYPE                     0x893f
 121 #define IXGBE_ETAG_ETYPE                       0x00005084
 122 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 123 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 124 #define IXGBE_RAH_ADTYPE                       0x40000000
 125 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 126 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 127 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 128 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 129 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 130 #define IXGBE_VTEICR_MASK                      0x07
 131
 132 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 133 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 134
 135 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 136 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 154                                 int wait_to_complete);
 155 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *stats);
 157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstat *xstats, unsigned n);
 159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 160                                   struct rte_eth_xstat *xstats, unsigned n);
 161 static int
 162 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 163                 uint64_t *values, unsigned int n);
 164 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         unsigned int size);
 169 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 171 static int ixgbe_dev_xstats_get_names_by_id(
 172         struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names,
 174         const uint64_t *ids,
 175         unsigned int limit);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 181                                  size_t fw_size);
 182 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 183                                struct rte_eth_dev_info *dev_info);
 184 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 185 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 186                                  struct rte_eth_dev_info *dev_info);
 187 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 188
 189 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 190                 uint16_t vlan_id, int on);
 191 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 192                                enum rte_vlan_type vlan_type,
 193                                uint16_t tpid_id);
 194 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 195                 uint16_t queue, bool on);
 196 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 197                 int on);
 198 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 200 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 201 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 202 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 203
 204 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 205 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 206 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 209                                struct rte_eth_fc_conf *fc_conf);
 210 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 211                 struct rte_eth_pfc_conf *pfc_conf);
 212 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 220 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 224                                       struct rte_intr_handle *handle);
 225 static void ixgbe_dev_interrupt_handler(void *param);
 226 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 227 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 228                          uint32_t index, uint32_t pool);
 229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 230 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 231                                            struct ether_addr *mac_addr);
 232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 233 static bool is_device_supported(struct rte_eth_dev *dev,
 234                                 struct rte_pci_driver *drv);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 242                                    int wait_to_complete);
 243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 247 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 249                 struct rte_eth_stats *stats);
 250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 252                 uint16_t vlan_id, int on);
 253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                 uint16_t queue, int on);
 255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 258                                             uint16_t queue_id);
 259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 260                                              uint16_t queue_id);
 261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 262                                  uint8_t queue, uint8_t msix_vector);
 263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 266
 267 /* For Eth VMDQ APIs support */
 268 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 269                 ether_addr * mac_addr, uint8_t on);
 270 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 271 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 272                 struct rte_eth_mirror_conf *mirror_conf,
 273                 uint8_t rule_id, uint8_t on);
 274 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 275                 uint8_t rule_id);
 276 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                           uint16_t queue_id);
 278 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                            uint16_t queue_id);
 280 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                uint8_t queue, uint8_t msix_vector);
 282 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 283
 284 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                 struct ether_addr *mac_addr,
 286                                 uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter);
 292 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 293                         enum rte_filter_op filter_op,
 294                         void *arg);
 295 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 298                         struct ixgbe_5tuple_filter *filter);
 299 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 300                                 enum rte_filter_op filter_op,
 301                                 void *arg);
 302 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter);
 304 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 305                                 enum rte_filter_op filter_op,
 306                                 void *arg);
 307 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 308                         struct rte_eth_ethertype_filter *filter);
 309 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 310                      enum rte_filter_type filter_type,
 311                      enum rte_filter_op filter_op,
 312                      void *arg);
 313 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 314
 315 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 316                                       struct ether_addr *mc_addr_set,
 317                                       uint32_t nb_mc_addr);
 318 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 319                                    struct rte_eth_dcb_info *dcb_info);
 320
 321 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 323                             struct rte_dev_reg_info *regs);
 324 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 325 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 328                                 struct rte_dev_eeprom_info *eeprom);
 329
 330 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 331 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 332                                 struct rte_dev_reg_info *regs);
 333
 334 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 335 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 337                                             struct timespec *timestamp,
 338                                             uint32_t flags);
 339 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp);
 341 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 342 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 343                                    struct timespec *timestamp);
 344 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 345                                    const struct timespec *timestamp);
 346 static void ixgbevf_dev_interrupt_handler(void *param);
 347
 348 static int ixgbe_dev_l2_tunnel_eth_type_conf
 349         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 350 static int ixgbe_dev_l2_tunnel_offload_set
 351         (struct rte_eth_dev *dev,
 352          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 353          uint32_t mask,
 354          uint8_t en);
 355 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 356                                              enum rte_filter_op filter_op,
 357                                              void *arg);
 358
 359 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 360                                          struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 364 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 365
 366 /*
 367  * Define VF Stats MACRO for Non "cleared on read" register
 368  */
 369 #define UPDATE_VF_STAT(reg, last, cur)                          \
 370 {                                                               \
 371         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 372         cur += (latest - last) & UINT_MAX;                      \
 373         last = latest;                                          \
 374 }
 375
 376 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 377 {                                                                \
 378         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 379         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 380         u64 latest = ((new_msb << 32) | new_lsb);                \
 381         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 382         last = latest;                                           \
 383 }
 384
 385 #define IXGBE_SET_HWSTRIP(h, q) do {\
 386                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 387                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 388                 (h)->bitmap[idx] |= 1 << bit;\
 389         } while (0)
 390
 391 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 392                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] &= ~(1 << bit);\
 395         } while (0)
 396
 397 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 398                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 400                 (r) = (h)->bitmap[idx] >> bit & 1;\
 401         } while (0)
 402
 403 int ixgbe_logtype_init;
 404 int ixgbe_logtype_driver;
 405
 406 /*
 407  * The set of PCI devices this driver supports
 408  */
 409 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 458 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 460 #endif
 461         { .vendor_id = 0, /* sentinel */ },
 462 };
 463
 464 /*
 465  * The set of PCI devices this driver supports (for 82599 VF)
 466  */
 467 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct rte_eth_desc_lim rx_desc_lim = {
 482         .nb_max = IXGBE_MAX_RING_DESC,
 483         .nb_min = IXGBE_MIN_RING_DESC,
 484         .nb_align = IXGBE_RXD_ALIGN,
 485 };
 486
 487 static const struct rte_eth_desc_lim tx_desc_lim = {
 488         .nb_max = IXGBE_MAX_RING_DESC,
 489         .nb_min = IXGBE_MIN_RING_DESC,
 490         .nb_align = IXGBE_TXD_ALIGN,
 491         .nb_seg_max = IXGBE_TX_MAX_SEG,
 492         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 493 };
 494
 495 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 496         .dev_configure        = ixgbe_dev_configure,
 497         .dev_start            = ixgbe_dev_start,
 498         .dev_stop             = ixgbe_dev_stop,
 499         .dev_set_link_up    = ixgbe_dev_set_link_up,
 500         .dev_set_link_down  = ixgbe_dev_set_link_down,
 501         .dev_close            = ixgbe_dev_close,
 502         .dev_reset            = ixgbe_dev_reset,
 503         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 504         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 505         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 506         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 507         .link_update          = ixgbe_dev_link_update,
 508         .stats_get            = ixgbe_dev_stats_get,
 509         .xstats_get           = ixgbe_dev_xstats_get,
 510         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 511         .stats_reset          = ixgbe_dev_stats_reset,
 512         .xstats_reset         = ixgbe_dev_xstats_reset,
 513         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 514         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 515         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 516         .fw_version_get       = ixgbe_fw_version_get,
 517         .dev_infos_get        = ixgbe_dev_info_get,
 518         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 519         .mtu_set              = ixgbe_dev_mtu_set,
 520         .vlan_filter_set      = ixgbe_vlan_filter_set,
 521         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 522         .vlan_offload_set     = ixgbe_vlan_offload_set,
 523         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 524         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 525         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 526         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 527         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 528         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 529         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 530         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 531         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 532         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 533         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 534         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 535         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 536         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 537         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 538         .dev_led_on           = ixgbe_dev_led_on,
 539         .dev_led_off          = ixgbe_dev_led_off,
 540         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 541         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 542         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 543         .mac_addr_add         = ixgbe_add_rar,
 544         .mac_addr_remove      = ixgbe_remove_rar,
 545         .mac_addr_set         = ixgbe_set_default_mac_addr,
 546         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 547         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 548         .mirror_rule_set      = ixgbe_mirror_rule_set,
 549         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 550         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 551         .reta_update          = ixgbe_dev_rss_reta_update,
 552         .reta_query           = ixgbe_dev_rss_reta_query,
 553         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 554         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 555         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 556         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 557         .rxq_info_get         = ixgbe_rxq_info_get,
 558         .txq_info_get         = ixgbe_txq_info_get,
 559         .timesync_enable      = ixgbe_timesync_enable,
 560         .timesync_disable     = ixgbe_timesync_disable,
 561         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 562         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 563         .get_reg              = ixgbe_get_regs,
 564         .get_eeprom_length    = ixgbe_get_eeprom_length,
 565         .get_eeprom           = ixgbe_get_eeprom,
 566         .set_eeprom           = ixgbe_set_eeprom,
 567         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 568         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 569         .timesync_read_time   = ixgbe_timesync_read_time,
 570         .timesync_write_time  = ixgbe_timesync_write_time,
 571         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 572         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 573         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 574         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 575         .tm_ops_get           = ixgbe_tm_ops_get,
 576 };
 577
 578 /*
 579  * dev_ops for virtual function, bare necessities for basic vf
 580  * operation have been implemented
 581  */
 582 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 583         .dev_configure        = ixgbevf_dev_configure,
 584         .dev_start            = ixgbevf_dev_start,
 585         .dev_stop             = ixgbevf_dev_stop,
 586         .link_update          = ixgbevf_dev_link_update,
 587         .stats_get            = ixgbevf_dev_stats_get,
 588         .xstats_get           = ixgbevf_dev_xstats_get,
 589         .stats_reset          = ixgbevf_dev_stats_reset,
 590         .xstats_reset         = ixgbevf_dev_stats_reset,
 591         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 592         .dev_close            = ixgbevf_dev_close,
 593         .dev_reset            = ixgbevf_dev_reset,
 594         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 595         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 596         .dev_infos_get        = ixgbevf_dev_info_get,
 597         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 598         .mtu_set              = ixgbevf_dev_set_mtu,
 599         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 600         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 601         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 602         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 603         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 604         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 605         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 606         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 607         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 608         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 609         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 610         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 611         .mac_addr_add         = ixgbevf_add_mac_addr,
 612         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 613         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 614         .rxq_info_get         = ixgbe_rxq_info_get,
 615         .txq_info_get         = ixgbe_txq_info_get,
 616         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 617         .get_reg              = ixgbevf_get_regs,
 618         .reta_update          = ixgbe_dev_rss_reta_update,
 619         .reta_query           = ixgbe_dev_rss_reta_query,
 620         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 621         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 622 };
 623
 624 /* store statistics names and its offset in stats structure */
 625 struct rte_ixgbe_xstats_name_off {
 626         char name[RTE_ETH_XSTATS_NAME_SIZE];
 627         unsigned offset;
 628 };
 629
 630 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 631         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 632         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 633         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 634         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 635         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 636         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 637         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 638         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 639         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 640         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 641         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 642         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 643         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 644         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 645         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 646                 prc1023)},
 647         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 648                 prc1522)},
 649         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 650         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 651         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 652         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 653         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 654         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 655         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 656         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 657         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 658         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 659         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 660         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 661         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 662         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 663         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 664         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 665         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 666                 ptc1023)},
 667         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 668                 ptc1522)},
 669         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 670         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 671         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 672         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 673
 674         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 675                 fdirustat_add)},
 676         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 677                 fdirustat_remove)},
 678         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 679                 fdirfstat_fadd)},
 680         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 681                 fdirfstat_fremove)},
 682         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 683                 fdirmatch)},
 684         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 685                 fdirmiss)},
 686
 687         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 688         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 689         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 690                 fclast)},
 691         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 692         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 693         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 694         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 695         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 696                 fcoe_noddp)},
 697         {"rx_fcoe_no_direct_data_placement_ext_buff",
 698                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 699
 700         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 701                 lxontxc)},
 702         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 703                 lxonrxc)},
 704         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxofftxc)},
 706         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxoffrxc)},
 708         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 709 };
 710
 711 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 712                            sizeof(rte_ixgbe_stats_strings[0]))
 713
 714 /* MACsec statistics */
 715 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 716         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 717                 out_pkts_untagged)},
 718         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 719                 out_pkts_encrypted)},
 720         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_protected)},
 722         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_octets_encrypted)},
 724         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_octets_protected)},
 726         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_untagged)},
 728         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_badtag)},
 730         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_nosci)},
 732         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_unknownsci)},
 734         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 735                 in_octets_decrypted)},
 736         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 737                 in_octets_validated)},
 738         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_unchecked)},
 740         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_delayed)},
 742         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_late)},
 744         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_ok)},
 746         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_invalid)},
 748         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_notvalid)},
 750         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_unusedsa)},
 752         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notusingsa)},
 754 };
 755
 756 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 757                            sizeof(rte_ixgbe_macsec_strings[0]))
 758
 759 /* Per-queue statistics */
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 761         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 762         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 763         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 764         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 765 };
 766
 767 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 768                            sizeof(rte_ixgbe_rxq_strings[0]))
 769 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 772         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 773         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 774         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 775                 pxon2offc)},
 776 };
 777
 778 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 779                            sizeof(rte_ixgbe_txq_strings[0]))
 780 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 781
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 783         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 784 };
 785
 786 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 787                 sizeof(rte_ixgbevf_stats_strings[0]))
 788
 789 /*
 790  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 791  */
 792 static inline int
 793 ixgbe_is_sfp(struct ixgbe_hw *hw)
 794 {
 795         switch (hw->phy.type) {
 796         case ixgbe_phy_sfp_avago:
 797         case ixgbe_phy_sfp_ftl:
 798         case ixgbe_phy_sfp_intel:
 799         case ixgbe_phy_sfp_unknown:
 800         case ixgbe_phy_sfp_passive_tyco:
 801         case ixgbe_phy_sfp_passive_unknown:
 802                 return 1;
 803         default:
 804                 return 0;
 805         }
 806 }
 807
 808 static inline int32_t
 809 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 810 {
 811         uint32_t ctrl_ext;
 812         int32_t status;
 813
 814         status = ixgbe_reset_hw(hw);
 815
 816         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 817         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 818         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 819         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 820         IXGBE_WRITE_FLUSH(hw);
 821
 822         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 823                 status = IXGBE_SUCCESS;
 824         return status;
 825 }
 826
 827 static inline void
 828 ixgbe_enable_intr(struct rte_eth_dev *dev)
 829 {
 830         struct ixgbe_interrupt *intr =
 831                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 832         struct ixgbe_hw *hw =
 833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 834
 835         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 836         IXGBE_WRITE_FLUSH(hw);
 837 }
 838
 839 /*
 840  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 841  */
 842 static void
 843 ixgbe_disable_intr(struct ixgbe_hw *hw)
 844 {
 845         PMD_INIT_FUNC_TRACE();
 846
 847         if (hw->mac.type == ixgbe_mac_82598EB) {
 848                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 849         } else {
 850                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 853         }
 854         IXGBE_WRITE_FLUSH(hw);
 855 }
 856
 857 /*
 858  * This function resets queue statistics mapping registers.
 859  * From Niantic datasheet, Initialization of Statistics section:
 860  * "...if software requires the queue counters, the RQSMR and TQSM registers
 861  * must be re-programmed following a device reset.
 862  */
 863 static void
 864 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 865 {
 866         uint32_t i;
 867
 868         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 869                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 870                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 871         }
 872 }
 873
 874
 875 static int
 876 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 877                                   uint16_t queue_id,
 878                                   uint8_t stat_idx,
 879                                   uint8_t is_rx)
 880 {
 881 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 882 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 883 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 884
 885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 886         struct ixgbe_stat_mapping_registers *stat_mappings =
 887                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 888         uint32_t qsmr_mask = 0;
 889         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 890         uint32_t q_map;
 891         uint8_t n, offset;
 892
 893         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 894                 (hw->mac.type != ixgbe_mac_X540) &&
 895                 (hw->mac.type != ixgbe_mac_X550) &&
 896                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 897                 (hw->mac.type != ixgbe_mac_X550EM_a))
 898                 return -ENOSYS;
 899
 900         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 901                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 902                      queue_id, stat_idx);
 903
 904         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 905         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 906                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 907                 return -EIO;
 908         }
 909         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 910
 911         /* Now clear any previous stat_idx set */
 912         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 913         if (!is_rx)
 914                 stat_mappings->tqsm[n] &= ~clearing_mask;
 915         else
 916                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 917
 918         q_map = (uint32_t)stat_idx;
 919         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 920         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 921         if (!is_rx)
 922                 stat_mappings->tqsm[n] |= qsmr_mask;
 923         else
 924                 stat_mappings->rqsmr[n] |= qsmr_mask;
 925
 926         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 927                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 928                      queue_id, stat_idx);
 929         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 930                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 931
 932         /* Now write the mapping in the appropriate register */
 933         if (is_rx) {
 934                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 935                              stat_mappings->rqsmr[n], n);
 936                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 937         } else {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 939                              stat_mappings->tqsm[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 941         }
 942         return 0;
 943 }
 944
 945 static void
 946 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 947 {
 948         struct ixgbe_stat_mapping_registers *stat_mappings =
 949                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951         int i;
 952
 953         /* write whatever was in stat mapping table to the NIC */
 954         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 /* rx */
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 957
 958                 /* tx */
 959                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 960         }
 961 }
 962
 963 static void
 964 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 965 {
 966         uint8_t i;
 967         struct ixgbe_dcb_tc_config *tc;
 968         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 969
 970         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 971         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 972         for (i = 0; i < dcb_max_tc; i++) {
 973                 tc = &dcb_config->tc_config[i];
 974                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 975                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 976                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 977                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 978                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 979                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 980                 tc->pfc = ixgbe_dcb_pfc_disabled;
 981         }
 982
 983         /* Initialize default user to priority mapping, UPx->TC0 */
 984         tc = &dcb_config->tc_config[0];
 985         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 986         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 987         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 988                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 989                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 990         }
 991         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 992         dcb_config->pfc_mode_enable = false;
 993         dcb_config->vt_mode = true;
 994         dcb_config->round_robin_enable = false;
 995         /* support all DCB capabilities in 82599 */
 996         dcb_config->support.capabilities = 0xFF;
 997
 998         /*we only support 4 Tcs for X540, X550 */
 999         if (hw->mac.type == ixgbe_mac_X540 ||
1000                 hw->mac.type == ixgbe_mac_X550 ||
1001                 hw->mac.type == ixgbe_mac_X550EM_x ||
1002                 hw->mac.type == ixgbe_mac_X550EM_a) {
1003                 dcb_config->num_tcs.pg_tcs = 4;
1004                 dcb_config->num_tcs.pfc_tcs = 4;
1005         }
1006 }
1007
1008 /*
1009  * Ensure that all locks are released before first NVM or PHY access
1010  */
1011 static void
1012 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1013 {
1014         uint16_t mask;
1015
1016         /*
1017          * Phy lock should not fail in this early stage. If this is the case,
1018          * it is due to an improper exit of the application.
1019          * So force the release of the faulty lock. Release of common lock
1020          * is done automatically by swfw_sync function.
1021          */
1022         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1023         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1024                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1025         }
1026         ixgbe_release_swfw_semaphore(hw, mask);
1027
1028         /*
1029          * These ones are more tricky since they are common to all ports; but
1030          * swfw_sync retries last long enough (1s) to be almost sure that if
1031          * lock can not be taken it is due to an improper lock of the
1032          * semaphore.
1033          */
1034         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1035         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1037         }
1038         ixgbe_release_swfw_semaphore(hw, mask);
1039 }
1040
1041 /*
1042  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1043  * It returns 0 on success.
1044  */
1045 static int
1046 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1047 {
1048         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1049         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1050         struct ixgbe_hw *hw =
1051                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1052         struct ixgbe_vfta *shadow_vfta =
1053                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1054         struct ixgbe_hwstrip *hwstrip =
1055                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1056         struct ixgbe_dcb_config *dcb_config =
1057                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1058         struct ixgbe_filter_info *filter_info =
1059                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1060         struct ixgbe_bw_conf *bw_conf =
1061                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1062         uint32_t ctrl_ext;
1063         uint16_t csum;
1064         int diag, i;
1065
1066         PMD_INIT_FUNC_TRACE();
1067
1068         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1069         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1070         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1071         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1072
1073         /*
1074          * For secondary processes, we don't initialise any further as primary
1075          * has already done this work. Only check we don't need a different
1076          * RX and TX function.
1077          */
1078         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1079                 struct ixgbe_tx_queue *txq;
1080                 /* TX queue function in primary, set by last queue initialized
1081                  * Tx queue may not initialized by primary process
1082                  */
1083                 if (eth_dev->data->tx_queues) {
1084                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1085                         ixgbe_set_tx_function(eth_dev, txq);
1086                 } else {
1087                         /* Use default TX function if we get here */
1088                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1089                                      "Using default TX function.");
1090                 }
1091
1092                 ixgbe_set_rx_function(eth_dev);
1093
1094                 return 0;
1095         }
1096
1097         rte_eth_copy_pci_info(eth_dev, pci_dev);
1098
1099         /* Vendor and Device ID need to be set before init of shared code */
1100         hw->device_id = pci_dev->id.device_id;
1101         hw->vendor_id = pci_dev->id.vendor_id;
1102         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1103         hw->allow_unsupported_sfp = 1;
1104
1105         /* Initialize the shared code (base driver) */
1106 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1107         diag = ixgbe_bypass_init_shared_code(hw);
1108 #else
1109         diag = ixgbe_init_shared_code(hw);
1110 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1111
1112         if (diag != IXGBE_SUCCESS) {
1113                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1114                 return -EIO;
1115         }
1116
1117         /* pick up the PCI bus settings for reporting later */
1118         ixgbe_get_bus_info(hw);
1119
1120         /* Unlock any pending hardware semaphore */
1121         ixgbe_swfw_lock_reset(hw);
1122
1123 #ifdef RTE_LIBRTE_SECURITY
1124         /* Initialize security_ctx only for primary process*/
1125         if (ixgbe_ipsec_ctx_create(eth_dev))
1126                 return -ENOMEM;
1127 #endif
1128
1129         /* Initialize DCB configuration*/
1130         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1131         ixgbe_dcb_init(hw, dcb_config);
1132         /* Get Hardware Flow Control setting */
1133         hw->fc.requested_mode = ixgbe_fc_full;
1134         hw->fc.current_mode = ixgbe_fc_full;
1135         hw->fc.pause_time = IXGBE_FC_PAUSE;
1136         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1137                 hw->fc.low_water[i] = IXGBE_FC_LO;
1138                 hw->fc.high_water[i] = IXGBE_FC_HI;
1139         }
1140         hw->fc.send_xon = 1;
1141
1142         /* Make sure we have a good EEPROM before we read from it */
1143         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1144         if (diag != IXGBE_SUCCESS) {
1145                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1146                 return -EIO;
1147         }
1148
1149 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1150         diag = ixgbe_bypass_init_hw(hw);
1151 #else
1152         diag = ixgbe_init_hw(hw);
1153 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1154
1155         /*
1156          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1157          * is called too soon after the kernel driver unbinding/binding occurs.
1158          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1159          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1160          * also called. See ixgbe_identify_phy_82599(). The reason for the
1161          * failure is not known, and only occuts when virtualisation features
1162          * are disabled in the bios. A delay of 100ms  was found to be enough by
1163          * trial-and-error, and is doubled to be safe.
1164          */
1165         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1166                 rte_delay_ms(200);
1167                 diag = ixgbe_init_hw(hw);
1168         }
1169
1170         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1171                 diag = IXGBE_SUCCESS;
1172
1173         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1174                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1175                              "LOM.  Please be aware there may be issues associated "
1176                              "with your hardware.");
1177                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1178                              "please contact your Intel or hardware representative "
1179                              "who provided you with this hardware.");
1180         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1181                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1182         if (diag) {
1183                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1184                 return -EIO;
1185         }
1186
1187         /* Reset the hw statistics */
1188         ixgbe_dev_stats_reset(eth_dev);
1189
1190         /* disable interrupt */
1191         ixgbe_disable_intr(hw);
1192
1193         /* reset mappings for queue statistics hw counters*/
1194         ixgbe_reset_qstat_mappings(hw);
1195
1196         /* Allocate memory for storing MAC addresses */
1197         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1198                                                hw->mac.num_rar_entries, 0);
1199         if (eth_dev->data->mac_addrs == NULL) {
1200                 PMD_INIT_LOG(ERR,
1201                              "Failed to allocate %u bytes needed to store "
1202                              "MAC addresses",
1203                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1204                 return -ENOMEM;
1205         }
1206         /* Copy the permanent MAC address */
1207         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1208                         &eth_dev->data->mac_addrs[0]);
1209
1210         /* Allocate memory for storing hash filter MAC addresses */
1211         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1212                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1213         if (eth_dev->data->hash_mac_addrs == NULL) {
1214                 PMD_INIT_LOG(ERR,
1215                              "Failed to allocate %d bytes needed to store MAC addresses",
1216                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1217                 return -ENOMEM;
1218         }
1219
1220         /* initialize the vfta */
1221         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1222
1223         /* initialize the hw strip bitmap*/
1224         memset(hwstrip, 0, sizeof(*hwstrip));
1225
1226         /* initialize PF if max_vfs not zero */
1227         ixgbe_pf_host_init(eth_dev);
1228
1229         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1230         /* let hardware know driver is loaded */
1231         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1232         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1233         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1234         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1235         IXGBE_WRITE_FLUSH(hw);
1236
1237         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1238                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1239                              (int) hw->mac.type, (int) hw->phy.type,
1240                              (int) hw->phy.sfp_type);
1241         else
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type);
1244
1245         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1246                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1247                      pci_dev->id.device_id);
1248
1249         rte_intr_callback_register(intr_handle,
1250                                    ixgbe_dev_interrupt_handler, eth_dev);
1251
1252         /* enable uio/vfio intr/eventfd mapping */
1253         rte_intr_enable(intr_handle);
1254
1255         /* enable support intr */
1256         ixgbe_enable_intr(eth_dev);
1257
1258         /* initialize filter info */
1259         memset(filter_info, 0,
1260                sizeof(struct ixgbe_filter_info));
1261
1262         /* initialize 5tuple filter list */
1263         TAILQ_INIT(&filter_info->fivetuple_list);
1264
1265         /* initialize flow director filter list & hash */
1266         ixgbe_fdir_filter_init(eth_dev);
1267
1268         /* initialize l2 tunnel filter list & hash */
1269         ixgbe_l2_tn_filter_init(eth_dev);
1270
1271         /* initialize flow filter lists */
1272         ixgbe_filterlist_init();
1273
1274         /* initialize bandwidth configuration info */
1275         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1276
1277         /* initialize Traffic Manager configuration */
1278         ixgbe_tm_conf_init(eth_dev);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1285 {
1286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1287         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288         struct ixgbe_hw *hw;
1289         int retries = 0;
1290         int ret;
1291
1292         PMD_INIT_FUNC_TRACE();
1293
1294         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1295                 return -EPERM;
1296
1297         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1298
1299         if (hw->adapter_stopped == 0)
1300                 ixgbe_dev_close(eth_dev);
1301
1302         eth_dev->dev_ops = NULL;
1303         eth_dev->rx_pkt_burst = NULL;
1304         eth_dev->tx_pkt_burst = NULL;
1305
1306         /* Unlock any pending hardware semaphore */
1307         ixgbe_swfw_lock_reset(hw);
1308
1309         /* disable uio intr before callback unregister */
1310         rte_intr_disable(intr_handle);
1311
1312         do {
1313                 ret = rte_intr_callback_unregister(intr_handle,
1314                                 ixgbe_dev_interrupt_handler, eth_dev);
1315                 if (ret >= 0) {
1316                         break;
1317                 } else if (ret != -EAGAIN) {
1318                         PMD_INIT_LOG(ERR,
1319                                 "intr callback unregister failed: %d",
1320                                 ret);
1321                         return ret;
1322                 }
1323                 rte_delay_ms(100);
1324         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1325
1326         /* uninitialize PF if max_vfs not zero */
1327         ixgbe_pf_host_uninit(eth_dev);
1328
1329         rte_free(eth_dev->data->mac_addrs);
1330         eth_dev->data->mac_addrs = NULL;
1331
1332         rte_free(eth_dev->data->hash_mac_addrs);
1333         eth_dev->data->hash_mac_addrs = NULL;
1334
1335         /* remove all the fdir filters & hash */
1336         ixgbe_fdir_filter_uninit(eth_dev);
1337
1338         /* remove all the L2 tunnel filters & hash */
1339         ixgbe_l2_tn_filter_uninit(eth_dev);
1340
1341         /* Remove all ntuple filters of the device */
1342         ixgbe_ntuple_filter_uninit(eth_dev);
1343
1344         /* clear all the filters list */
1345         ixgbe_filterlist_flush();
1346
1347         /* Remove all Traffic Manager configuration */
1348         ixgbe_tm_conf_uninit(eth_dev);
1349
1350 #ifdef RTE_LIBRTE_SECURITY
1351         rte_free(eth_dev->security_ctx);
1352 #endif
1353
1354         return 0;
1355 }
1356
1357 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct ixgbe_filter_info *filter_info =
1360                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1361         struct ixgbe_5tuple_filter *p_5tuple;
1362
1363         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1364                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1365                              p_5tuple,
1366                              entries);
1367                 rte_free(p_5tuple);
1368         }
1369         memset(filter_info->fivetuple_mask, 0,
1370                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1371
1372         return 0;
1373 }
1374
1375 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1376 {
1377         struct ixgbe_hw_fdir_info *fdir_info =
1378                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1379         struct ixgbe_fdir_filter *fdir_filter;
1380
1381                 if (fdir_info->hash_map)
1382                 rte_free(fdir_info->hash_map);
1383         if (fdir_info->hash_handle)
1384                 rte_hash_free(fdir_info->hash_handle);
1385
1386         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1387                 TAILQ_REMOVE(&fdir_info->fdir_list,
1388                              fdir_filter,
1389                              entries);
1390                 rte_free(fdir_filter);
1391         }
1392
1393         return 0;
1394 }
1395
1396 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1397 {
1398         struct ixgbe_l2_tn_info *l2_tn_info =
1399                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1400         struct ixgbe_l2_tn_filter *l2_tn_filter;
1401
1402         if (l2_tn_info->hash_map)
1403                 rte_free(l2_tn_info->hash_map);
1404         if (l2_tn_info->hash_handle)
1405                 rte_hash_free(l2_tn_info->hash_handle);
1406
1407         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1408                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1409                              l2_tn_filter,
1410                              entries);
1411                 rte_free(l2_tn_filter);
1412         }
1413
1414         return 0;
1415 }
1416
1417 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1418 {
1419         struct ixgbe_hw_fdir_info *fdir_info =
1420                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1421         char fdir_hash_name[RTE_HASH_NAMESIZE];
1422         struct rte_hash_parameters fdir_hash_params = {
1423                 .name = fdir_hash_name,
1424                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1425                 .key_len = sizeof(union ixgbe_atr_input),
1426                 .hash_func = rte_hash_crc,
1427                 .hash_func_init_val = 0,
1428                 .socket_id = rte_socket_id(),
1429         };
1430
1431         TAILQ_INIT(&fdir_info->fdir_list);
1432         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1433                  "fdir_%s", eth_dev->device->name);
1434         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1435         if (!fdir_info->hash_handle) {
1436                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1437                 return -EINVAL;
1438         }
1439         fdir_info->hash_map = rte_zmalloc("ixgbe",
1440                                           sizeof(struct ixgbe_fdir_filter *) *
1441                                           IXGBE_MAX_FDIR_FILTER_NUM,
1442                                           0);
1443         if (!fdir_info->hash_map) {
1444                 PMD_INIT_LOG(ERR,
1445                              "Failed to allocate memory for fdir hash map!");
1446                 return -ENOMEM;
1447         }
1448         fdir_info->mask_added = FALSE;
1449
1450         return 0;
1451 }
1452
1453 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1454 {
1455         struct ixgbe_l2_tn_info *l2_tn_info =
1456                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1457         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1458         struct rte_hash_parameters l2_tn_hash_params = {
1459                 .name = l2_tn_hash_name,
1460                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1461                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1462                 .hash_func = rte_hash_crc,
1463                 .hash_func_init_val = 0,
1464                 .socket_id = rte_socket_id(),
1465         };
1466
1467         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1468         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1469                  "l2_tn_%s", eth_dev->device->name);
1470         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1471         if (!l2_tn_info->hash_handle) {
1472                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1473                 return -EINVAL;
1474         }
1475         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1476                                    sizeof(struct ixgbe_l2_tn_filter *) *
1477                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1478                                    0);
1479         if (!l2_tn_info->hash_map) {
1480                 PMD_INIT_LOG(ERR,
1481                         "Failed to allocate memory for L2 TN hash map!");
1482                 return -ENOMEM;
1483         }
1484         l2_tn_info->e_tag_en = FALSE;
1485         l2_tn_info->e_tag_fwd_en = FALSE;
1486         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1487
1488         return 0;
1489 }
1490 /*
1491  * Negotiate mailbox API version with the PF.
1492  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1493  * Then we try to negotiate starting with the most recent one.
1494  * If all negotiation attempts fail, then we will proceed with
1495  * the default one (ixgbe_mbox_api_10).
1496  */
1497 static void
1498 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1499 {
1500         int32_t i;
1501
1502         /* start with highest supported, proceed down */
1503         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1504                 ixgbe_mbox_api_12,
1505                 ixgbe_mbox_api_11,
1506                 ixgbe_mbox_api_10,
1507         };
1508
1509         for (i = 0;
1510                         i != RTE_DIM(sup_ver) &&
1511                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1512                         i++)
1513                 ;
1514 }
1515
1516 static void
1517 generate_random_mac_addr(struct ether_addr *mac_addr)
1518 {
1519         uint64_t random;
1520
1521         /* Set Organizationally Unique Identifier (OUI) prefix. */
1522         mac_addr->addr_bytes[0] = 0x00;
1523         mac_addr->addr_bytes[1] = 0x09;
1524         mac_addr->addr_bytes[2] = 0xC0;
1525         /* Force indication of locally assigned MAC address. */
1526         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1527         /* Generate the last 3 bytes of the MAC address with a random number. */
1528         random = rte_rand();
1529         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1530 }
1531
1532 /*
1533  * Virtual Function device init
1534  */
1535 static int
1536 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1537 {
1538         int diag;
1539         uint32_t tc, tcs;
1540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542         struct ixgbe_hw *hw =
1543                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1544         struct ixgbe_vfta *shadow_vfta =
1545                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1546         struct ixgbe_hwstrip *hwstrip =
1547                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1548         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1549
1550         PMD_INIT_FUNC_TRACE();
1551
1552         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1553         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1554         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1555
1556         /* for secondary processes, we don't initialise any further as primary
1557          * has already done this work. Only check we don't need a different
1558          * RX function
1559          */
1560         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1561                 struct ixgbe_tx_queue *txq;
1562                 /* TX queue function in primary, set by last queue initialized
1563                  * Tx queue may not initialized by primary process
1564                  */
1565                 if (eth_dev->data->tx_queues) {
1566                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1567                         ixgbe_set_tx_function(eth_dev, txq);
1568                 } else {
1569                         /* Use default TX function if we get here */
1570                         PMD_INIT_LOG(NOTICE,
1571                                      "No TX queues configured yet. Using default TX function.");
1572                 }
1573
1574                 ixgbe_set_rx_function(eth_dev);
1575
1576                 return 0;
1577         }
1578
1579         rte_eth_copy_pci_info(eth_dev, pci_dev);
1580
1581         hw->device_id = pci_dev->id.device_id;
1582         hw->vendor_id = pci_dev->id.vendor_id;
1583         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1584
1585         /* initialize the vfta */
1586         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1587
1588         /* initialize the hw strip bitmap*/
1589         memset(hwstrip, 0, sizeof(*hwstrip));
1590
1591         /* Initialize the shared code (base driver) */
1592         diag = ixgbe_init_shared_code(hw);
1593         if (diag != IXGBE_SUCCESS) {
1594                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1595                 return -EIO;
1596         }
1597
1598         /* init_mailbox_params */
1599         hw->mbx.ops.init_params(hw);
1600
1601         /* Reset the hw statistics */
1602         ixgbevf_dev_stats_reset(eth_dev);
1603
1604         /* Disable the interrupts for VF */
1605         ixgbevf_intr_disable(hw);
1606
1607         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1608         diag = hw->mac.ops.reset_hw(hw);
1609
1610         /*
1611          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1612          * the underlying PF driver has not assigned a MAC address to the VF.
1613          * In this case, assign a random MAC address.
1614          */
1615         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1616                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1617                 return diag;
1618         }
1619
1620         /* negotiate mailbox API version to use with the PF. */
1621         ixgbevf_negotiate_api(hw);
1622
1623         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1624         ixgbevf_get_queues(hw, &tcs, &tc);
1625
1626         /* Allocate memory for storing MAC addresses */
1627         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1628                                                hw->mac.num_rar_entries, 0);
1629         if (eth_dev->data->mac_addrs == NULL) {
1630                 PMD_INIT_LOG(ERR,
1631                              "Failed to allocate %u bytes needed to store "
1632                              "MAC addresses",
1633                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1634                 return -ENOMEM;
1635         }
1636
1637         /* Generate a random MAC address, if none was assigned by PF. */
1638         if (is_zero_ether_addr(perm_addr)) {
1639                 generate_random_mac_addr(perm_addr);
1640                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1641                 if (diag) {
1642                         rte_free(eth_dev->data->mac_addrs);
1643                         eth_dev->data->mac_addrs = NULL;
1644                         return diag;
1645                 }
1646                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1647                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1648                              "%02x:%02x:%02x:%02x:%02x:%02x",
1649                              perm_addr->addr_bytes[0],
1650                              perm_addr->addr_bytes[1],
1651                              perm_addr->addr_bytes[2],
1652                              perm_addr->addr_bytes[3],
1653                              perm_addr->addr_bytes[4],
1654                              perm_addr->addr_bytes[5]);
1655         }
1656
1657         /* Copy the permanent MAC address */
1658         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1659
1660         /* reset the hardware with the new settings */
1661         diag = hw->mac.ops.start_hw(hw);
1662         switch (diag) {
1663         case  0:
1664                 break;
1665
1666         default:
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return -EIO;
1669         }
1670
1671         rte_intr_callback_register(intr_handle,
1672                                    ixgbevf_dev_interrupt_handler, eth_dev);
1673         rte_intr_enable(intr_handle);
1674         ixgbevf_intr_enable(hw);
1675
1676         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1677                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1678                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1679
1680         return 0;
1681 }
1682
1683 /* Virtual Function device uninit */
1684
1685 static int
1686 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1687 {
1688         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1689         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690         struct ixgbe_hw *hw;
1691
1692         PMD_INIT_FUNC_TRACE();
1693
1694         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1695                 return -EPERM;
1696
1697         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1698
1699         if (hw->adapter_stopped == 0)
1700                 ixgbevf_dev_close(eth_dev);
1701
1702         eth_dev->dev_ops = NULL;
1703         eth_dev->rx_pkt_burst = NULL;
1704         eth_dev->tx_pkt_burst = NULL;
1705
1706         /* Disable the interrupts for VF */
1707         ixgbevf_intr_disable(hw);
1708
1709         rte_free(eth_dev->data->mac_addrs);
1710         eth_dev->data->mac_addrs = NULL;
1711
1712         rte_intr_disable(intr_handle);
1713         rte_intr_callback_unregister(intr_handle,
1714                                      ixgbevf_dev_interrupt_handler, eth_dev);
1715
1716         return 0;
1717 }
1718
1719 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1720         struct rte_pci_device *pci_dev)
1721 {
1722         return rte_eth_dev_pci_generic_probe(pci_dev,
1723                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1724 }
1725
1726 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1727 {
1728         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1729 }
1730
1731 static struct rte_pci_driver rte_ixgbe_pmd = {
1732         .id_table = pci_id_ixgbe_map,
1733         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1734                      RTE_PCI_DRV_IOVA_AS_VA,
1735         .probe = eth_ixgbe_pci_probe,
1736         .remove = eth_ixgbe_pci_remove,
1737 };
1738
1739 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1740         struct rte_pci_device *pci_dev)
1741 {
1742         return rte_eth_dev_pci_generic_probe(pci_dev,
1743                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1744 }
1745
1746 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1747 {
1748         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1749 }
1750
1751 /*
1752  * virtual function driver struct
1753  */
1754 static struct rte_pci_driver rte_ixgbevf_pmd = {
1755         .id_table = pci_id_ixgbevf_map,
1756         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1757         .probe = eth_ixgbevf_pci_probe,
1758         .remove = eth_ixgbevf_pci_remove,
1759 };
1760
1761 static int
1762 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1763 {
1764         struct ixgbe_hw *hw =
1765                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1766         struct ixgbe_vfta *shadow_vfta =
1767                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1768         uint32_t vfta;
1769         uint32_t vid_idx;
1770         uint32_t vid_bit;
1771
1772         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1773         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1774         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1775         if (on)
1776                 vfta |= vid_bit;
1777         else
1778                 vfta &= ~vid_bit;
1779         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1780
1781         /* update local VFTA copy */
1782         shadow_vfta->vfta[vid_idx] = vfta;
1783
1784         return 0;
1785 }
1786
1787 static void
1788 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1789 {
1790         if (on)
1791                 ixgbe_vlan_hw_strip_enable(dev, queue);
1792         else
1793                 ixgbe_vlan_hw_strip_disable(dev, queue);
1794 }
1795
1796 static int
1797 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1798                     enum rte_vlan_type vlan_type,
1799                     uint16_t tpid)
1800 {
1801         struct ixgbe_hw *hw =
1802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803         int ret = 0;
1804         uint32_t reg;
1805         uint32_t qinq;
1806
1807         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1808         qinq &= IXGBE_DMATXCTL_GDV;
1809
1810         switch (vlan_type) {
1811         case ETH_VLAN_TYPE_INNER:
1812                 if (qinq) {
1813                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1814                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1815                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1816                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1817                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1818                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1819                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1820                 } else {
1821                         ret = -ENOTSUP;
1822                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1823                                     " by single VLAN");
1824                 }
1825                 break;
1826         case ETH_VLAN_TYPE_OUTER:
1827                 if (qinq) {
1828                         /* Only the high 16-bits is valid */
1829                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1830                                         IXGBE_EXVET_VET_EXT_SHIFT);
1831                 } else {
1832                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1833                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1834                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1835                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1836                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1837                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1838                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1839                 }
1840
1841                 break;
1842         default:
1843                 ret = -EINVAL;
1844                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1845                 break;
1846         }
1847
1848         return ret;
1849 }
1850
1851 void
1852 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1853 {
1854         struct ixgbe_hw *hw =
1855                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856         uint32_t vlnctrl;
1857
1858         PMD_INIT_FUNC_TRACE();
1859
1860         /* Filter Table Disable */
1861         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1862         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1863
1864         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1865 }
1866
1867 void
1868 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         struct ixgbe_vfta *shadow_vfta =
1873                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1874         uint32_t vlnctrl;
1875         uint16_t i;
1876
1877         PMD_INIT_FUNC_TRACE();
1878
1879         /* Filter Table Enable */
1880         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1881         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1882         vlnctrl |= IXGBE_VLNCTRL_VFE;
1883
1884         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1885
1886         /* write whatever is in local vfta copy */
1887         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1888                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1889 }
1890
1891 static void
1892 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1893 {
1894         struct ixgbe_hwstrip *hwstrip =
1895                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1896         struct ixgbe_rx_queue *rxq;
1897
1898         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1899                 return;
1900
1901         if (on)
1902                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1903         else
1904                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1905
1906         if (queue >= dev->data->nb_rx_queues)
1907                 return;
1908
1909         rxq = dev->data->rx_queues[queue];
1910
1911         if (on)
1912                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1913         else
1914                 rxq->vlan_flags = PKT_RX_VLAN;
1915 }
1916
1917 static void
1918 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint32_t ctrl;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         if (hw->mac.type == ixgbe_mac_82598EB) {
1927                 /* No queue level support */
1928                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1929                 return;
1930         }
1931
1932         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1933         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1934         ctrl &= ~IXGBE_RXDCTL_VME;
1935         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1936
1937         /* record those setting for HW strip per queue */
1938         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1939 }
1940
1941 static void
1942 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1943 {
1944         struct ixgbe_hw *hw =
1945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946         uint32_t ctrl;
1947
1948         PMD_INIT_FUNC_TRACE();
1949
1950         if (hw->mac.type == ixgbe_mac_82598EB) {
1951                 /* No queue level supported */
1952                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1953                 return;
1954         }
1955
1956         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1957         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1958         ctrl |= IXGBE_RXDCTL_VME;
1959         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1960
1961         /* record those setting for HW strip per queue */
1962         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1963 }
1964
1965 static void
1966 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1967 {
1968         struct ixgbe_hw *hw =
1969                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970         uint32_t ctrl;
1971
1972         PMD_INIT_FUNC_TRACE();
1973
1974         /* DMATXCTRL: Geric Double VLAN Disable */
1975         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1976         ctrl &= ~IXGBE_DMATXCTL_GDV;
1977         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1978
1979         /* CTRL_EXT: Global Double VLAN Disable */
1980         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1981         ctrl &= ~IXGBE_EXTENDED_VLAN;
1982         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1983
1984 }
1985
1986 static void
1987 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1988 {
1989         struct ixgbe_hw *hw =
1990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         uint32_t ctrl;
1992
1993         PMD_INIT_FUNC_TRACE();
1994
1995         /* DMATXCTRL: Geric Double VLAN Enable */
1996         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1997         ctrl |= IXGBE_DMATXCTL_GDV;
1998         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1999
2000         /* CTRL_EXT: Global Double VLAN Enable */
2001         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2002         ctrl |= IXGBE_EXTENDED_VLAN;
2003         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2004
2005         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2006         if (hw->mac.type == ixgbe_mac_X550 ||
2007             hw->mac.type == ixgbe_mac_X550EM_x ||
2008             hw->mac.type == ixgbe_mac_X550EM_a) {
2009                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2010                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2011                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2012         }
2013
2014         /*
2015          * VET EXT field in the EXVET register = 0x8100 by default
2016          * So no need to change. Same to VT field of DMATXCTL register
2017          */
2018 }
2019
2020 void
2021 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2022 {
2023         struct ixgbe_hw *hw =
2024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2026         uint32_t ctrl;
2027         uint16_t i;
2028         struct ixgbe_rx_queue *rxq;
2029         bool on;
2030
2031         PMD_INIT_FUNC_TRACE();
2032
2033         if (hw->mac.type == ixgbe_mac_82598EB) {
2034                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2035                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2036                         ctrl |= IXGBE_VLNCTRL_VME;
2037                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2038                 } else {
2039                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2040                         ctrl &= ~IXGBE_VLNCTRL_VME;
2041                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2042                 }
2043         } else {
2044                 /*
2045                  * Other 10G NIC, the VLAN strip can be setup
2046                  * per queue in RXDCTL
2047                  */
2048                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2049                         rxq = dev->data->rx_queues[i];
2050                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2051                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2052                                 ctrl |= IXGBE_RXDCTL_VME;
2053                                 on = TRUE;
2054                         } else {
2055                                 ctrl &= ~IXGBE_RXDCTL_VME;
2056                                 on = FALSE;
2057                         }
2058                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2059
2060                         /* record those setting for HW strip per queue */
2061                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2062                 }
2063         }
2064 }
2065
2066 static int
2067 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2068 {
2069         struct rte_eth_rxmode *rxmode;
2070         rxmode = &dev->data->dev_conf.rxmode;
2071
2072         if (mask & ETH_VLAN_STRIP_MASK) {
2073                 ixgbe_vlan_hw_strip_config(dev);
2074         }
2075
2076         if (mask & ETH_VLAN_FILTER_MASK) {
2077                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2078                         ixgbe_vlan_hw_filter_enable(dev);
2079                 else
2080                         ixgbe_vlan_hw_filter_disable(dev);
2081         }
2082
2083         if (mask & ETH_VLAN_EXTEND_MASK) {
2084                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2085                         ixgbe_vlan_hw_extend_enable(dev);
2086                 else
2087                         ixgbe_vlan_hw_extend_disable(dev);
2088         }
2089
2090         return 0;
2091 }
2092
2093 static void
2094 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2095 {
2096         struct ixgbe_hw *hw =
2097                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2099         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2100
2101         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2102         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2103 }
2104
2105 static int
2106 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2107 {
2108         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2109
2110         switch (nb_rx_q) {
2111         case 1:
2112         case 2:
2113                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2114                 break;
2115         case 4:
2116                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2117                 break;
2118         default:
2119                 return -EINVAL;
2120         }
2121
2122         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2123                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2124         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2125                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2126         return 0;
2127 }
2128
2129 static int
2130 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2131 {
2132         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2135         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2136
2137         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2138                 /* check multi-queue mode */
2139                 switch (dev_conf->rxmode.mq_mode) {
2140                 case ETH_MQ_RX_VMDQ_DCB:
2141                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2142                         break;
2143                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2144                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2145                         PMD_INIT_LOG(ERR, "SRIOV active,"
2146                                         " unsupported mq_mode rx %d.",
2147                                         dev_conf->rxmode.mq_mode);
2148                         return -EINVAL;
2149                 case ETH_MQ_RX_RSS:
2150                 case ETH_MQ_RX_VMDQ_RSS:
2151                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2152                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2153                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2154                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2155                                                 " invalid queue number"
2156                                                 " for VMDQ RSS, allowed"
2157                                                 " value are 1, 2 or 4.");
2158                                         return -EINVAL;
2159                                 }
2160                         break;
2161                 case ETH_MQ_RX_VMDQ_ONLY:
2162                 case ETH_MQ_RX_NONE:
2163                         /* if nothing mq mode configure, use default scheme */
2164                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2165                         break;
2166                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2167                         /* SRIOV only works in VMDq enable mode */
2168                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2169                                         " wrong mq_mode rx %d.",
2170                                         dev_conf->rxmode.mq_mode);
2171                         return -EINVAL;
2172                 }
2173
2174                 switch (dev_conf->txmode.mq_mode) {
2175                 case ETH_MQ_TX_VMDQ_DCB:
2176                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2177                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2178                         break;
2179                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2180                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2181                         break;
2182                 }
2183
2184                 /* check valid queue number */
2185                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2186                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2187                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2188                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2189                                         " must be less than or equal to %d.",
2190                                         nb_rx_q, nb_tx_q,
2191                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2192                         return -EINVAL;
2193                 }
2194         } else {
2195                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2196                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2197                                           " not supported.");
2198                         return -EINVAL;
2199                 }
2200                 /* check configuration for vmdb+dcb mode */
2201                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2202                         const struct rte_eth_vmdq_dcb_conf *conf;
2203
2204                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2205                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2206                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2207                                 return -EINVAL;
2208                         }
2209                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2210                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2211                                conf->nb_queue_pools == ETH_32_POOLS)) {
2212                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2213                                                 " nb_queue_pools must be %d or %d.",
2214                                                 ETH_16_POOLS, ETH_32_POOLS);
2215                                 return -EINVAL;
2216                         }
2217                 }
2218                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2219                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2220
2221                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2222                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2223                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2224                                 return -EINVAL;
2225                         }
2226                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2227                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2228                                conf->nb_queue_pools == ETH_32_POOLS)) {
2229                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2230                                                 " nb_queue_pools != %d and"
2231                                                 " nb_queue_pools != %d.",
2232                                                 ETH_16_POOLS, ETH_32_POOLS);
2233                                 return -EINVAL;
2234                         }
2235                 }
2236
2237                 /* For DCB mode check our configuration before we go further */
2238                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2239                         const struct rte_eth_dcb_rx_conf *conf;
2240
2241                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2242                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2243                                                  IXGBE_DCB_NB_QUEUES);
2244                                 return -EINVAL;
2245                         }
2246                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2247                         if (!(conf->nb_tcs == ETH_4_TCS ||
2248                                conf->nb_tcs == ETH_8_TCS)) {
2249                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2250                                                 " and nb_tcs != %d.",
2251                                                 ETH_4_TCS, ETH_8_TCS);
2252                                 return -EINVAL;
2253                         }
2254                 }
2255
2256                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2257                         const struct rte_eth_dcb_tx_conf *conf;
2258
2259                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2260                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2261                                                  IXGBE_DCB_NB_QUEUES);
2262                                 return -EINVAL;
2263                         }
2264                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2265                         if (!(conf->nb_tcs == ETH_4_TCS ||
2266                                conf->nb_tcs == ETH_8_TCS)) {
2267                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2268                                                 " and nb_tcs != %d.",
2269                                                 ETH_4_TCS, ETH_8_TCS);
2270                                 return -EINVAL;
2271                         }
2272                 }
2273
2274                 /*
2275                  * When DCB/VT is off, maximum number of queues changes,
2276                  * except for 82598EB, which remains constant.
2277                  */
2278                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2279                                 hw->mac.type != ixgbe_mac_82598EB) {
2280                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2281                                 PMD_INIT_LOG(ERR,
2282                                              "Neither VT nor DCB are enabled, "
2283                                              "nb_tx_q > %d.",
2284                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2285                                 return -EINVAL;
2286                         }
2287                 }
2288         }
2289         return 0;
2290 }
2291
2292 static int
2293 ixgbe_dev_configure(struct rte_eth_dev *dev)
2294 {
2295         struct ixgbe_interrupt *intr =
2296                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2297         struct ixgbe_adapter *adapter =
2298                 (struct ixgbe_adapter *)dev->data->dev_private;
2299         struct rte_eth_dev_info dev_info;
2300         uint64_t rx_offloads;
2301         uint64_t tx_offloads;
2302         int ret;
2303
2304         PMD_INIT_FUNC_TRACE();
2305         /* multipe queue mode checking */
2306         ret  = ixgbe_check_mq_mode(dev);
2307         if (ret != 0) {
2308                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2309                             ret);
2310                 return ret;
2311         }
2312
2313         ixgbe_dev_info_get(dev, &dev_info);
2314         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2315         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2316                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2317                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2318                             rx_offloads, dev_info.rx_offload_capa);
2319                 return -ENOTSUP;
2320         }
2321         tx_offloads = dev->data->dev_conf.txmode.offloads;
2322         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2323                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2324                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2325                             tx_offloads, dev_info.tx_offload_capa);
2326                 return -ENOTSUP;
2327         }
2328
2329         /* set flag to update link status after init */
2330         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2331
2332         /*
2333          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2334          * allocation or vector Rx preconditions we will reset it.
2335          */
2336         adapter->rx_bulk_alloc_allowed = true;
2337         adapter->rx_vec_allowed = true;
2338
2339         return 0;
2340 }
2341
2342 static void
2343 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2344 {
2345         struct ixgbe_hw *hw =
2346                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         struct ixgbe_interrupt *intr =
2348                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2349         uint32_t gpie;
2350
2351         /* only set up it on X550EM_X */
2352         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2353                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2354                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2355                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2356                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2357                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2358         }
2359 }
2360
2361 int
2362 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2363                         uint16_t tx_rate, uint64_t q_msk)
2364 {
2365         struct ixgbe_hw *hw;
2366         struct ixgbe_vf_info *vfinfo;
2367         struct rte_eth_link link;
2368         uint8_t  nb_q_per_pool;
2369         uint32_t queue_stride;
2370         uint32_t queue_idx, idx = 0, vf_idx;
2371         uint32_t queue_end;
2372         uint16_t total_rate = 0;
2373         struct rte_pci_device *pci_dev;
2374
2375         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2376         rte_eth_link_get_nowait(dev->data->port_id, &link);
2377
2378         if (vf >= pci_dev->max_vfs)
2379                 return -EINVAL;
2380
2381         if (tx_rate > link.link_speed)
2382                 return -EINVAL;
2383
2384         if (q_msk == 0)
2385                 return 0;
2386
2387         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2389         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2390         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2391         queue_idx = vf * queue_stride;
2392         queue_end = queue_idx + nb_q_per_pool - 1;
2393         if (queue_end >= hw->mac.max_tx_queues)
2394                 return -EINVAL;
2395
2396         if (vfinfo) {
2397                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2398                         if (vf_idx == vf)
2399                                 continue;
2400                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2401                                 idx++)
2402                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2403                 }
2404         } else {
2405                 return -EINVAL;
2406         }
2407
2408         /* Store tx_rate for this vf. */
2409         for (idx = 0; idx < nb_q_per_pool; idx++) {
2410                 if (((uint64_t)0x1 << idx) & q_msk) {
2411                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2412                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2413                         total_rate += tx_rate;
2414                 }
2415         }
2416
2417         if (total_rate > dev->data->dev_link.link_speed) {
2418                 /* Reset stored TX rate of the VF if it causes exceed
2419                  * link speed.
2420                  */
2421                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2422                 return -EINVAL;
2423         }
2424
2425         /* Set RTTBCNRC of each queue/pool for vf X  */
2426         for (; queue_idx <= queue_end; queue_idx++) {
2427                 if (0x1 & q_msk)
2428                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2429                 q_msk = q_msk >> 1;
2430         }
2431
2432         return 0;
2433 }
2434
2435 /*
2436  * Configure device link speed and setup link.
2437  * It returns 0 on success.
2438  */
2439 static int
2440 ixgbe_dev_start(struct rte_eth_dev *dev)
2441 {
2442         struct ixgbe_hw *hw =
2443                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444         struct ixgbe_vf_info *vfinfo =
2445                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2446         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2447         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2448         uint32_t intr_vector = 0;
2449         int err, link_up = 0, negotiate = 0;
2450         uint32_t speed = 0;
2451         int mask = 0;
2452         int status;
2453         uint16_t vf, idx;
2454         uint32_t *link_speeds;
2455         struct ixgbe_tm_conf *tm_conf =
2456                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2457
2458         PMD_INIT_FUNC_TRACE();
2459
2460         /* IXGBE devices don't support:
2461         *    - half duplex (checked afterwards for valid speeds)
2462         *    - fixed speed: TODO implement
2463         */
2464         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2465                 PMD_INIT_LOG(ERR,
2466                 "Invalid link_speeds for port %u, fix speed not supported",
2467                                 dev->data->port_id);
2468                 return -EINVAL;
2469         }
2470
2471         /* disable uio/vfio intr/eventfd mapping */
2472         rte_intr_disable(intr_handle);
2473
2474         /* stop adapter */
2475         hw->adapter_stopped = 0;
2476         ixgbe_stop_adapter(hw);
2477
2478         /* reinitialize adapter
2479          * this calls reset and start
2480          */
2481         status = ixgbe_pf_reset_hw(hw);
2482         if (status != 0)
2483                 return -1;
2484         hw->mac.ops.start_hw(hw);
2485         hw->mac.get_link_status = true;
2486
2487         /* configure PF module if SRIOV enabled */
2488         ixgbe_pf_host_configure(dev);
2489
2490         ixgbe_dev_phy_intr_setup(dev);
2491
2492         /* check and configure queue intr-vector mapping */
2493         if ((rte_intr_cap_multiple(intr_handle) ||
2494              !RTE_ETH_DEV_SRIOV(dev).active) &&
2495             dev->data->dev_conf.intr_conf.rxq != 0) {
2496                 intr_vector = dev->data->nb_rx_queues;
2497                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2498                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2499                                         IXGBE_MAX_INTR_QUEUE_NUM);
2500                         return -ENOTSUP;
2501                 }
2502                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2503                         return -1;
2504         }
2505
2506         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2507                 intr_handle->intr_vec =
2508                         rte_zmalloc("intr_vec",
2509                                     dev->data->nb_rx_queues * sizeof(int), 0);
2510                 if (intr_handle->intr_vec == NULL) {
2511                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2512                                      " intr_vec", dev->data->nb_rx_queues);
2513                         return -ENOMEM;
2514                 }
2515         }
2516
2517         /* confiugre msix for sleep until rx interrupt */
2518         ixgbe_configure_msix(dev);
2519
2520         /* initialize transmission unit */
2521         ixgbe_dev_tx_init(dev);
2522
2523         /* This can fail when allocating mbufs for descriptor rings */
2524         err = ixgbe_dev_rx_init(dev);
2525         if (err) {
2526                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2527                 goto error;
2528         }
2529
2530         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2531                 ETH_VLAN_EXTEND_MASK;
2532         err = ixgbe_vlan_offload_set(dev, mask);
2533         if (err) {
2534                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2535                 goto error;
2536         }
2537
2538         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2539                 /* Enable vlan filtering for VMDq */
2540                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2541         }
2542
2543         /* Configure DCB hw */
2544         ixgbe_configure_dcb(dev);
2545
2546         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2547                 err = ixgbe_fdir_configure(dev);
2548                 if (err)
2549                         goto error;
2550         }
2551
2552         /* Restore vf rate limit */
2553         if (vfinfo != NULL) {
2554                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2555                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2556                                 if (vfinfo[vf].tx_rate[idx] != 0)
2557                                         ixgbe_set_vf_rate_limit(
2558                                                 dev, vf,
2559                                                 vfinfo[vf].tx_rate[idx],
2560                                                 1 << idx);
2561         }
2562
2563         ixgbe_restore_statistics_mapping(dev);
2564
2565         err = ixgbe_dev_rxtx_start(dev);
2566         if (err < 0) {
2567                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2568                 goto error;
2569         }
2570
2571         /* Skip link setup if loopback mode is enabled for 82599. */
2572         if (hw->mac.type == ixgbe_mac_82599EB &&
2573                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2574                 goto skip_link_setup;
2575
2576         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2577                 err = hw->mac.ops.setup_sfp(hw);
2578                 if (err)
2579                         goto error;
2580         }
2581
2582         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2583                 /* Turn on the copper */
2584                 ixgbe_set_phy_power(hw, true);
2585         } else {
2586                 /* Turn on the laser */
2587                 ixgbe_enable_tx_laser(hw);
2588         }
2589
2590         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2591         if (err)
2592                 goto error;
2593         dev->data->dev_link.link_status = link_up;
2594
2595         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2596         if (err)
2597                 goto error;
2598
2599         link_speeds = &dev->data->dev_conf.link_speeds;
2600         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2601                         ETH_LINK_SPEED_10G)) {
2602                 PMD_INIT_LOG(ERR, "Invalid link setting");
2603                 goto error;
2604         }
2605
2606         speed = 0x0;
2607         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2608                 switch (hw->mac.type) {
2609                 case ixgbe_mac_82598EB:
2610                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2611                         break;
2612                 case ixgbe_mac_82599EB:
2613                 case ixgbe_mac_X540:
2614                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2615                         break;
2616                 case ixgbe_mac_X550:
2617                 case ixgbe_mac_X550EM_x:
2618                 case ixgbe_mac_X550EM_a:
2619                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2620                         break;
2621                 default:
2622                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2623                 }
2624         } else {
2625                 if (*link_speeds & ETH_LINK_SPEED_10G)
2626                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2627                 if (*link_speeds & ETH_LINK_SPEED_1G)
2628                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2629                 if (*link_speeds & ETH_LINK_SPEED_100M)
2630                         speed |= IXGBE_LINK_SPEED_100_FULL;
2631         }
2632
2633         err = ixgbe_setup_link(hw, speed, link_up);
2634         if (err)
2635                 goto error;
2636
2637 skip_link_setup:
2638
2639         if (rte_intr_allow_others(intr_handle)) {
2640                 /* check if lsc interrupt is enabled */
2641                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2642                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2643                 else
2644                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2645                 ixgbe_dev_macsec_interrupt_setup(dev);
2646         } else {
2647                 rte_intr_callback_unregister(intr_handle,
2648                                              ixgbe_dev_interrupt_handler, dev);
2649                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2650                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2651                                      " no intr multiplex");
2652         }
2653
2654         /* check if rxq interrupt is enabled */
2655         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2656             rte_intr_dp_is_en(intr_handle))
2657                 ixgbe_dev_rxq_interrupt_setup(dev);
2658
2659         /* enable uio/vfio intr/eventfd mapping */
2660         rte_intr_enable(intr_handle);
2661
2662         /* resume enabled intr since hw reset */
2663         ixgbe_enable_intr(dev);
2664         ixgbe_l2_tunnel_conf(dev);
2665         ixgbe_filter_restore(dev);
2666
2667         if (tm_conf->root && !tm_conf->committed)
2668                 PMD_DRV_LOG(WARNING,
2669                             "please call hierarchy_commit() "
2670                             "before starting the port");
2671
2672         return 0;
2673
2674 error:
2675         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2676         ixgbe_dev_clear_queues(dev);
2677         return -EIO;
2678 }
2679
2680 /*
2681  * Stop device: disable rx and tx functions to allow for reconfiguring.
2682  */
2683 static void
2684 ixgbe_dev_stop(struct rte_eth_dev *dev)
2685 {
2686         struct rte_eth_link link;
2687         struct ixgbe_hw *hw =
2688                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689         struct ixgbe_vf_info *vfinfo =
2690                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2691         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2692         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2693         int vf;
2694         struct ixgbe_tm_conf *tm_conf =
2695                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2696
2697         PMD_INIT_FUNC_TRACE();
2698
2699         /* disable interrupts */
2700         ixgbe_disable_intr(hw);
2701
2702         /* reset the NIC */
2703         ixgbe_pf_reset_hw(hw);
2704         hw->adapter_stopped = 0;
2705
2706         /* stop adapter */
2707         ixgbe_stop_adapter(hw);
2708
2709         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2710                 vfinfo[vf].clear_to_send = false;
2711
2712         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2713                 /* Turn off the copper */
2714                 ixgbe_set_phy_power(hw, false);
2715         } else {
2716                 /* Turn off the laser */
2717                 ixgbe_disable_tx_laser(hw);
2718         }
2719
2720         ixgbe_dev_clear_queues(dev);
2721
2722         /* Clear stored conf */
2723         dev->data->scattered_rx = 0;
2724         dev->data->lro = 0;
2725
2726         /* Clear recorded link status */
2727         memset(&link, 0, sizeof(link));
2728         rte_eth_linkstatus_set(dev, &link);
2729
2730         if (!rte_intr_allow_others(intr_handle))
2731                 /* resume to the default handler */
2732                 rte_intr_callback_register(intr_handle,
2733                                            ixgbe_dev_interrupt_handler,
2734                                            (void *)dev);
2735
2736         /* Clean datapath event and queue/vec mapping */
2737         rte_intr_efd_disable(intr_handle);
2738         if (intr_handle->intr_vec != NULL) {
2739                 rte_free(intr_handle->intr_vec);
2740                 intr_handle->intr_vec = NULL;
2741         }
2742
2743         /* reset hierarchy commit */
2744         tm_conf->committed = false;
2745 }
2746
2747 /*
2748  * Set device link up: enable tx.
2749  */
2750 static int
2751 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2752 {
2753         struct ixgbe_hw *hw =
2754                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2755         if (hw->mac.type == ixgbe_mac_82599EB) {
2756 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2757                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2758                         /* Not suported in bypass mode */
2759                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2760                                      "by device id 0x%x", hw->device_id);
2761                         return -ENOTSUP;
2762                 }
2763 #endif
2764         }
2765
2766         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2767                 /* Turn on the copper */
2768                 ixgbe_set_phy_power(hw, true);
2769         } else {
2770                 /* Turn on the laser */
2771                 ixgbe_enable_tx_laser(hw);
2772         }
2773
2774         return 0;
2775 }
2776
2777 /*
2778  * Set device link down: disable tx.
2779  */
2780 static int
2781 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2782 {
2783         struct ixgbe_hw *hw =
2784                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785         if (hw->mac.type == ixgbe_mac_82599EB) {
2786 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2787                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2788                         /* Not suported in bypass mode */
2789                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2790                                      "by device id 0x%x", hw->device_id);
2791                         return -ENOTSUP;
2792                 }
2793 #endif
2794         }
2795
2796         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2797                 /* Turn off the copper */
2798                 ixgbe_set_phy_power(hw, false);
2799         } else {
2800                 /* Turn off the laser */
2801                 ixgbe_disable_tx_laser(hw);
2802         }
2803
2804         return 0;
2805 }
2806
2807 /*
2808  * Reset and stop device.
2809  */
2810 static void
2811 ixgbe_dev_close(struct rte_eth_dev *dev)
2812 {
2813         struct ixgbe_hw *hw =
2814                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815
2816         PMD_INIT_FUNC_TRACE();
2817
2818         ixgbe_pf_reset_hw(hw);
2819
2820         ixgbe_dev_stop(dev);
2821         hw->adapter_stopped = 1;
2822
2823         ixgbe_dev_free_queues(dev);
2824
2825         ixgbe_disable_pcie_master(hw);
2826
2827         /* reprogram the RAR[0] in case user changed it. */
2828         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2829 }
2830
2831 /*
2832  * Reset PF device.
2833  */
2834 static int
2835 ixgbe_dev_reset(struct rte_eth_dev *dev)
2836 {
2837         int ret;
2838
2839         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2840          * its VF to make them align with it. The detailed notification
2841          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2842          * To avoid unexpected behavior in VF, currently reset of PF with
2843          * SR-IOV activation is not supported. It might be supported later.
2844          */
2845         if (dev->data->sriov.active)
2846                 return -ENOTSUP;
2847
2848         ret = eth_ixgbe_dev_uninit(dev);
2849         if (ret)
2850                 return ret;
2851
2852         ret = eth_ixgbe_dev_init(dev);
2853
2854         return ret;
2855 }
2856
2857 static void
2858 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2859                            struct ixgbe_hw_stats *hw_stats,
2860                            struct ixgbe_macsec_stats *macsec_stats,
2861                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2862                            uint64_t *total_qprc, uint64_t *total_qprdc)
2863 {
2864         uint32_t bprc, lxon, lxoff, total;
2865         uint32_t delta_gprc = 0;
2866         unsigned i;
2867         /* Workaround for RX byte count not including CRC bytes when CRC
2868          * strip is enabled. CRC bytes are removed from counters when crc_strip
2869          * is disabled.
2870          */
2871         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2872                         IXGBE_HLREG0_RXCRCSTRP);
2873
2874         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2875         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2876         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2877         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2878
2879         for (i = 0; i < 8; i++) {
2880                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2881
2882                 /* global total per queue */
2883                 hw_stats->mpc[i] += mp;
2884                 /* Running comprehensive total for stats display */
2885                 *total_missed_rx += hw_stats->mpc[i];
2886                 if (hw->mac.type == ixgbe_mac_82598EB) {
2887                         hw_stats->rnbc[i] +=
2888                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2889                         hw_stats->pxonrxc[i] +=
2890                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2891                         hw_stats->pxoffrxc[i] +=
2892                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2893                 } else {
2894                         hw_stats->pxonrxc[i] +=
2895                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2896                         hw_stats->pxoffrxc[i] +=
2897                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2898                         hw_stats->pxon2offc[i] +=
2899                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2900                 }
2901                 hw_stats->pxontxc[i] +=
2902                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2903                 hw_stats->pxofftxc[i] +=
2904                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2905         }
2906         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2907                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2908                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2909                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2910
2911                 delta_gprc += delta_qprc;
2912
2913                 hw_stats->qprc[i] += delta_qprc;
2914                 hw_stats->qptc[i] += delta_qptc;
2915
2916                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2917                 hw_stats->qbrc[i] +=
2918                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2919                 if (crc_strip == 0)
2920                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2921
2922                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2923                 hw_stats->qbtc[i] +=
2924                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2925
2926                 hw_stats->qprdc[i] += delta_qprdc;
2927                 *total_qprdc += hw_stats->qprdc[i];
2928
2929                 *total_qprc += hw_stats->qprc[i];
2930                 *total_qbrc += hw_stats->qbrc[i];
2931         }
2932         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2933         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2934         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2935
2936         /*
2937          * An errata states that gprc actually counts good + missed packets:
2938          * Workaround to set gprc to summated queue packet receives
2939          */
2940         hw_stats->gprc = *total_qprc;
2941
2942         if (hw->mac.type != ixgbe_mac_82598EB) {
2943                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2944                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2945                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2946                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2947                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2948                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2949                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2950                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2951         } else {
2952                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2953                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2954                 /* 82598 only has a counter in the high register */
2955                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2956                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2957                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2958         }
2959         uint64_t old_tpr = hw_stats->tpr;
2960
2961         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2962         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2963
2964         if (crc_strip == 0)
2965                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2966
2967         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2968         hw_stats->gptc += delta_gptc;
2969         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2970         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2971
2972         /*
2973          * Workaround: mprc hardware is incorrectly counting
2974          * broadcasts, so for now we subtract those.
2975          */
2976         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2977         hw_stats->bprc += bprc;
2978         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2979         if (hw->mac.type == ixgbe_mac_82598EB)
2980                 hw_stats->mprc -= bprc;
2981
2982         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2983         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2984         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2985         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2986         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2987         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2988
2989         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2990         hw_stats->lxontxc += lxon;
2991         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2992         hw_stats->lxofftxc += lxoff;
2993         total = lxon + lxoff;
2994
2995         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2996         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2997         hw_stats->gptc -= total;
2998         hw_stats->mptc -= total;
2999         hw_stats->ptc64 -= total;
3000         hw_stats->gotc -= total * ETHER_MIN_LEN;
3001
3002         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3003         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3004         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3005         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3006         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3007         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3008         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3009         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3010         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3011         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3012         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3013         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3014         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3015         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3016         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3017         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3018         /* Only read FCOE on 82599 */
3019         if (hw->mac.type != ixgbe_mac_82598EB) {
3020                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3021                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3022                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3023                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3024                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3025         }
3026
3027         /* Flow Director Stats registers */
3028         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3029         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3030
3031         /* MACsec Stats registers */
3032         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3033         macsec_stats->out_pkts_encrypted +=
3034                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3035         macsec_stats->out_pkts_protected +=
3036                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3037         macsec_stats->out_octets_encrypted +=
3038                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3039         macsec_stats->out_octets_protected +=
3040                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3041         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3042         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3043         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3044         macsec_stats->in_pkts_unknownsci +=
3045                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3046         macsec_stats->in_octets_decrypted +=
3047                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3048         macsec_stats->in_octets_validated +=
3049                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3050         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3051         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3052         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3053         for (i = 0; i < 2; i++) {
3054                 macsec_stats->in_pkts_ok +=
3055                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3056                 macsec_stats->in_pkts_invalid +=
3057                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3058                 macsec_stats->in_pkts_notvalid +=
3059                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3060         }
3061         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3062         macsec_stats->in_pkts_notusingsa +=
3063                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3064 }
3065
3066 /*
3067  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3068  */
3069 static int
3070 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3071 {
3072         struct ixgbe_hw *hw =
3073                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074         struct ixgbe_hw_stats *hw_stats =
3075                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3076         struct ixgbe_macsec_stats *macsec_stats =
3077                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3078                                 dev->data->dev_private);
3079         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3080         unsigned i;
3081
3082         total_missed_rx = 0;
3083         total_qbrc = 0;
3084         total_qprc = 0;
3085         total_qprdc = 0;
3086
3087         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3088                         &total_qbrc, &total_qprc, &total_qprdc);
3089
3090         if (stats == NULL)
3091                 return -EINVAL;
3092
3093         /* Fill out the rte_eth_stats statistics structure */
3094         stats->ipackets = total_qprc;
3095         stats->ibytes = total_qbrc;
3096         stats->opackets = hw_stats->gptc;
3097         stats->obytes = hw_stats->gotc;
3098
3099         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3100                 stats->q_ipackets[i] = hw_stats->qprc[i];
3101                 stats->q_opackets[i] = hw_stats->qptc[i];
3102                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3103                 stats->q_obytes[i] = hw_stats->qbtc[i];
3104                 stats->q_errors[i] = hw_stats->qprdc[i];
3105         }
3106
3107         /* Rx Errors */
3108         stats->imissed  = total_missed_rx;
3109         stats->ierrors  = hw_stats->crcerrs +
3110                           hw_stats->mspdc +
3111                           hw_stats->rlec +
3112                           hw_stats->ruc +
3113                           hw_stats->roc +
3114                           hw_stats->illerrc +
3115                           hw_stats->errbc +
3116                           hw_stats->rfc +
3117                           hw_stats->fccrc +
3118                           hw_stats->fclast;
3119
3120         /* Tx Errors */
3121         stats->oerrors  = 0;
3122         return 0;
3123 }
3124
3125 static void
3126 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3127 {
3128         struct ixgbe_hw_stats *stats =
3129                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3130
3131         /* HW registers are cleared on read */
3132         ixgbe_dev_stats_get(dev, NULL);
3133
3134         /* Reset software totals */
3135         memset(stats, 0, sizeof(*stats));
3136 }
3137
3138 /* This function calculates the number of xstats based on the current config */
3139 static unsigned
3140 ixgbe_xstats_calc_num(void) {
3141         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3142                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3143                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3144 }
3145
3146 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3147         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3148 {
3149         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3150         unsigned stat, i, count;
3151
3152         if (xstats_names != NULL) {
3153                 count = 0;
3154
3155                 /* Note: limit >= cnt_stats checked upstream
3156                  * in rte_eth_xstats_names()
3157                  */
3158
3159                 /* Extended stats from ixgbe_hw_stats */
3160                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3161                         snprintf(xstats_names[count].name,
3162                                 sizeof(xstats_names[count].name),
3163                                 "%s",
3164                                 rte_ixgbe_stats_strings[i].name);
3165                         count++;
3166                 }
3167
3168                 /* MACsec Stats */
3169                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3170                         snprintf(xstats_names[count].name,
3171                                 sizeof(xstats_names[count].name),
3172                                 "%s",
3173                                 rte_ixgbe_macsec_strings[i].name);
3174                         count++;
3175                 }
3176
3177                 /* RX Priority Stats */
3178                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3179                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3180                                 snprintf(xstats_names[count].name,
3181                                         sizeof(xstats_names[count].name),
3182                                         "rx_priority%u_%s", i,
3183                                         rte_ixgbe_rxq_strings[stat].name);
3184                                 count++;
3185                         }
3186                 }
3187
3188                 /* TX Priority Stats */
3189                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3190                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3191                                 snprintf(xstats_names[count].name,
3192                                         sizeof(xstats_names[count].name),
3193                                         "tx_priority%u_%s", i,
3194                                         rte_ixgbe_txq_strings[stat].name);
3195                                 count++;
3196                         }
3197                 }
3198         }
3199         return cnt_stats;
3200 }
3201
3202 static int ixgbe_dev_xstats_get_names_by_id(
3203         struct rte_eth_dev *dev,
3204         struct rte_eth_xstat_name *xstats_names,
3205         const uint64_t *ids,
3206         unsigned int limit)
3207 {
3208         if (!ids) {
3209                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3210                 unsigned int stat, i, count;
3211
3212                 if (xstats_names != NULL) {
3213                         count = 0;
3214
3215                         /* Note: limit >= cnt_stats checked upstream
3216                          * in rte_eth_xstats_names()
3217                          */
3218
3219                         /* Extended stats from ixgbe_hw_stats */
3220                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3221                                 snprintf(xstats_names[count].name,
3222                                         sizeof(xstats_names[count].name),
3223                                         "%s",
3224                                         rte_ixgbe_stats_strings[i].name);
3225                                 count++;
3226                         }
3227
3228                         /* MACsec Stats */
3229                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3230                                 snprintf(xstats_names[count].name,
3231                                         sizeof(xstats_names[count].name),
3232                                         "%s",
3233                                         rte_ixgbe_macsec_strings[i].name);
3234                                 count++;
3235                         }
3236
3237                         /* RX Priority Stats */
3238                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3239                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3240                                         snprintf(xstats_names[count].name,
3241                                             sizeof(xstats_names[count].name),
3242                                             "rx_priority%u_%s", i,
3243                                             rte_ixgbe_rxq_strings[stat].name);
3244                                         count++;
3245                                 }
3246                         }
3247
3248                         /* TX Priority Stats */
3249                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3250                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3251                                         snprintf(xstats_names[count].name,
3252                                             sizeof(xstats_names[count].name),
3253                                             "tx_priority%u_%s", i,
3254                                             rte_ixgbe_txq_strings[stat].name);
3255                                         count++;
3256                                 }
3257                         }
3258                 }
3259                 return cnt_stats;
3260         }
3261
3262         uint16_t i;
3263         uint16_t size = ixgbe_xstats_calc_num();
3264         struct rte_eth_xstat_name xstats_names_copy[size];
3265
3266         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3267                         size);
3268
3269         for (i = 0; i < limit; i++) {
3270                 if (ids[i] >= size) {
3271                         PMD_INIT_LOG(ERR, "id value isn't valid");
3272                         return -1;
3273                 }
3274                 strcpy(xstats_names[i].name,
3275                                 xstats_names_copy[ids[i]].name);
3276         }
3277         return limit;
3278 }
3279
3280 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3281         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3282 {
3283         unsigned i;
3284
3285         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3286                 return -ENOMEM;
3287
3288         if (xstats_names != NULL)
3289                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3290                         snprintf(xstats_names[i].name,
3291                                 sizeof(xstats_names[i].name),
3292                                 "%s", rte_ixgbevf_stats_strings[i].name);
3293         return IXGBEVF_NB_XSTATS;
3294 }
3295
3296 static int
3297 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3298                                          unsigned n)
3299 {
3300         struct ixgbe_hw *hw =
3301                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302         struct ixgbe_hw_stats *hw_stats =
3303                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3304         struct ixgbe_macsec_stats *macsec_stats =
3305                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3306                                 dev->data->dev_private);
3307         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3308         unsigned i, stat, count = 0;
3309
3310         count = ixgbe_xstats_calc_num();
3311
3312         if (n < count)
3313                 return count;
3314
3315         total_missed_rx = 0;
3316         total_qbrc = 0;
3317         total_qprc = 0;
3318         total_qprdc = 0;
3319
3320         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3321                         &total_qbrc, &total_qprc, &total_qprdc);
3322
3323         /* If this is a reset xstats is NULL, and we have cleared the
3324          * registers by reading them.
3325          */
3326         if (!xstats)
3327                 return 0;
3328
3329         /* Extended stats from ixgbe_hw_stats */
3330         count = 0;
3331         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3332                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3333                                 rte_ixgbe_stats_strings[i].offset);
3334                 xstats[count].id = count;
3335                 count++;
3336         }
3337
3338         /* MACsec Stats */
3339         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3340                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3341                                 rte_ixgbe_macsec_strings[i].offset);
3342                 xstats[count].id = count;
3343                 count++;
3344         }
3345
3346         /* RX Priority Stats */
3347         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3348                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3349                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3350                                         rte_ixgbe_rxq_strings[stat].offset +
3351                                         (sizeof(uint64_t) * i));
3352                         xstats[count].id = count;
3353                         count++;
3354                 }
3355         }
3356
3357         /* TX Priority Stats */
3358         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3359                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3360                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3361                                         rte_ixgbe_txq_strings[stat].offset +
3362                                         (sizeof(uint64_t) * i));
3363                         xstats[count].id = count;
3364                         count++;
3365                 }
3366         }
3367         return count;
3368 }
3369
3370 static int
3371 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3372                 uint64_t *values, unsigned int n)
3373 {
3374         if (!ids) {
3375                 struct ixgbe_hw *hw =
3376                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3377                 struct ixgbe_hw_stats *hw_stats =
3378                                 IXGBE_DEV_PRIVATE_TO_STATS(
3379                                                 dev->data->dev_private);
3380                 struct ixgbe_macsec_stats *macsec_stats =
3381                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3382                                         dev->data->dev_private);
3383                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3384                 unsigned int i, stat, count = 0;
3385
3386                 count = ixgbe_xstats_calc_num();
3387
3388                 if (!ids && n < count)
3389                         return count;
3390
3391                 total_missed_rx = 0;
3392                 total_qbrc = 0;
3393                 total_qprc = 0;
3394                 total_qprdc = 0;
3395
3396                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3397                                 &total_missed_rx, &total_qbrc, &total_qprc,
3398                                 &total_qprdc);
3399
3400                 /* If this is a reset xstats is NULL, and we have cleared the
3401                  * registers by reading them.
3402                  */
3403                 if (!ids && !values)
3404                         return 0;
3405
3406                 /* Extended stats from ixgbe_hw_stats */
3407                 count = 0;
3408                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3409                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3410                                         rte_ixgbe_stats_strings[i].offset);
3411                         count++;
3412                 }
3413
3414                 /* MACsec Stats */
3415                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3416                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3417                                         rte_ixgbe_macsec_strings[i].offset);
3418                         count++;
3419                 }
3420
3421                 /* RX Priority Stats */
3422                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3423                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3424                                 values[count] =
3425                                         *(uint64_t *)(((char *)hw_stats) +
3426                                         rte_ixgbe_rxq_strings[stat].offset +
3427                                         (sizeof(uint64_t) * i));
3428                                 count++;
3429                         }
3430                 }
3431
3432                 /* TX Priority Stats */
3433                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3434                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3435                                 values[count] =
3436                                         *(uint64_t *)(((char *)hw_stats) +
3437                                         rte_ixgbe_txq_strings[stat].offset +
3438                                         (sizeof(uint64_t) * i));
3439                                 count++;
3440                         }
3441                 }
3442                 return count;
3443         }
3444
3445         uint16_t i;
3446         uint16_t size = ixgbe_xstats_calc_num();
3447         uint64_t values_copy[size];
3448
3449         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3450
3451         for (i = 0; i < n; i++) {
3452                 if (ids[i] >= size) {
3453                         PMD_INIT_LOG(ERR, "id value isn't valid");
3454                         return -1;
3455                 }
3456                 values[i] = values_copy[ids[i]];
3457         }
3458         return n;
3459 }
3460
3461 static void
3462 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3463 {
3464         struct ixgbe_hw_stats *stats =
3465                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3466         struct ixgbe_macsec_stats *macsec_stats =
3467                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3468                                 dev->data->dev_private);
3469
3470         unsigned count = ixgbe_xstats_calc_num();
3471
3472         /* HW registers are cleared on read */
3473         ixgbe_dev_xstats_get(dev, NULL, count);
3474
3475         /* Reset software totals */
3476         memset(stats, 0, sizeof(*stats));
3477         memset(macsec_stats, 0, sizeof(*macsec_stats));
3478 }
3479
3480 static void
3481 ixgbevf_update_stats(struct rte_eth_dev *dev)
3482 {
3483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3485                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3486
3487         /* Good Rx packet, include VF loopback */
3488         UPDATE_VF_STAT(IXGBE_VFGPRC,
3489             hw_stats->last_vfgprc, hw_stats->vfgprc);
3490
3491         /* Good Rx octets, include VF loopback */
3492         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3493             hw_stats->last_vfgorc, hw_stats->vfgorc);
3494
3495         /* Good Tx packet, include VF loopback */
3496         UPDATE_VF_STAT(IXGBE_VFGPTC,
3497             hw_stats->last_vfgptc, hw_stats->vfgptc);
3498
3499         /* Good Tx octets, include VF loopback */
3500         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3501             hw_stats->last_vfgotc, hw_stats->vfgotc);
3502
3503         /* Rx Multicst Packet */
3504         UPDATE_VF_STAT(IXGBE_VFMPRC,
3505             hw_stats->last_vfmprc, hw_stats->vfmprc);
3506 }
3507
3508 static int
3509 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3510                        unsigned n)
3511 {
3512         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3513                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3514         unsigned i;
3515
3516         if (n < IXGBEVF_NB_XSTATS)
3517                 return IXGBEVF_NB_XSTATS;
3518
3519         ixgbevf_update_stats(dev);
3520
3521         if (!xstats)
3522                 return 0;
3523
3524         /* Extended stats */
3525         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3526                 xstats[i].id = i;
3527                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3528                         rte_ixgbevf_stats_strings[i].offset);
3529         }
3530
3531         return IXGBEVF_NB_XSTATS;
3532 }
3533
3534 static int
3535 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3536 {
3537         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3538                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3539
3540         ixgbevf_update_stats(dev);
3541
3542         if (stats == NULL)
3543                 return -EINVAL;
3544
3545         stats->ipackets = hw_stats->vfgprc;
3546         stats->ibytes = hw_stats->vfgorc;
3547         stats->opackets = hw_stats->vfgptc;
3548         stats->obytes = hw_stats->vfgotc;
3549         return 0;
3550 }
3551
3552 static void
3553 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3554 {
3555         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3556                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3557
3558         /* Sync HW register to the last stats */
3559         ixgbevf_dev_stats_get(dev, NULL);
3560
3561         /* reset HW current stats*/
3562         hw_stats->vfgprc = 0;
3563         hw_stats->vfgorc = 0;
3564         hw_stats->vfgptc = 0;
3565         hw_stats->vfgotc = 0;
3566 }
3567
3568 static int
3569 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3570 {
3571         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572         u16 eeprom_verh, eeprom_verl;
3573         u32 etrack_id;
3574         int ret;
3575
3576         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3577         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3578
3579         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3580         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3581
3582         ret += 1; /* add the size of '\0' */
3583         if (fw_size < (u32)ret)
3584                 return ret;
3585         else
3586                 return 0;
3587 }
3588
3589 static void
3590 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3591 {
3592         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3593         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3594         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3595
3596         dev_info->pci_dev = pci_dev;
3597         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3598         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3599         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3600                 /*
3601                  * When DCB/VT is off, maximum number of queues changes,
3602                  * except for 82598EB, which remains constant.
3603                  */
3604                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3605                                 hw->mac.type != ixgbe_mac_82598EB)
3606                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3607         }
3608         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3609         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3610         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3611         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3612         dev_info->max_vfs = pci_dev->max_vfs;
3613         if (hw->mac.type == ixgbe_mac_82598EB)
3614                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3615         else
3616                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3617         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3618         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3619         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3620                                      dev_info->rx_queue_offload_capa);
3621         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3622         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3623
3624         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3625                 .rx_thresh = {
3626                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3627                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3628                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3629                 },
3630                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3631                 .rx_drop_en = 0,
3632                 .offloads = 0,
3633         };
3634
3635         dev_info->default_txconf = (struct rte_eth_txconf) {
3636                 .tx_thresh = {
3637                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3638                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3639                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3640                 },
3641                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3642                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3643                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3644                              ETH_TXQ_FLAGS_NOOFFLOADS |
3645                              ETH_TXQ_FLAGS_IGNORE,
3646                 .offloads = 0,
3647         };
3648
3649         dev_info->rx_desc_lim = rx_desc_lim;
3650         dev_info->tx_desc_lim = tx_desc_lim;
3651
3652         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3653         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3654         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3655
3656         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3657         if (hw->mac.type == ixgbe_mac_X540 ||
3658             hw->mac.type == ixgbe_mac_X540_vf ||
3659             hw->mac.type == ixgbe_mac_X550 ||
3660             hw->mac.type == ixgbe_mac_X550_vf) {
3661                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3662         }
3663         if (hw->mac.type == ixgbe_mac_X550) {
3664                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3665                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3666         }
3667 }
3668
3669 static const uint32_t *
3670 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3671 {
3672         static const uint32_t ptypes[] = {
3673                 /* For non-vec functions,
3674                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3675                  * for vec functions,
3676                  * refers to _recv_raw_pkts_vec().
3677                  */
3678                 RTE_PTYPE_L2_ETHER,
3679                 RTE_PTYPE_L3_IPV4,
3680                 RTE_PTYPE_L3_IPV4_EXT,
3681                 RTE_PTYPE_L3_IPV6,
3682                 RTE_PTYPE_L3_IPV6_EXT,
3683                 RTE_PTYPE_L4_SCTP,
3684                 RTE_PTYPE_L4_TCP,
3685                 RTE_PTYPE_L4_UDP,
3686                 RTE_PTYPE_TUNNEL_IP,
3687                 RTE_PTYPE_INNER_L3_IPV6,
3688                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3689                 RTE_PTYPE_INNER_L4_TCP,
3690                 RTE_PTYPE_INNER_L4_UDP,
3691                 RTE_PTYPE_UNKNOWN
3692         };
3693
3694         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3695             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3696             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3697             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3698                 return ptypes;
3699
3700 #if defined(RTE_ARCH_X86)
3701         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3702             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3703                 return ptypes;
3704 #endif
3705         return NULL;
3706 }
3707
3708 static void
3709 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3710                      struct rte_eth_dev_info *dev_info)
3711 {
3712         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714
3715         dev_info->pci_dev = pci_dev;
3716         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3717         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3718         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3719         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3720         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3721         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3722         dev_info->max_vfs = pci_dev->max_vfs;
3723         if (hw->mac.type == ixgbe_mac_82598EB)
3724                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3725         else
3726                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3727         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3728         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3729                                      dev_info->rx_queue_offload_capa);
3730         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3731         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3732
3733         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3734                 .rx_thresh = {
3735                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3736                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3737                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3738                 },
3739                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3740                 .rx_drop_en = 0,
3741                 .offloads = 0,
3742         };
3743
3744         dev_info->default_txconf = (struct rte_eth_txconf) {
3745                 .tx_thresh = {
3746                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3747                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3748                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3749                 },
3750                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3751                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3752                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3753                              ETH_TXQ_FLAGS_NOOFFLOADS |
3754                              ETH_TXQ_FLAGS_IGNORE,
3755                 .offloads = 0,
3756         };
3757
3758         dev_info->rx_desc_lim = rx_desc_lim;
3759         dev_info->tx_desc_lim = tx_desc_lim;
3760 }
3761
3762 static int
3763 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3764                    int *link_up, int wait_to_complete)
3765 {
3766         /**
3767          * for a quick link status checking, wait_to_compelet == 0,
3768          * skip PF link status checking
3769          */
3770         bool no_pflink_check = wait_to_complete == 0;
3771         struct ixgbe_mbx_info *mbx = &hw->mbx;
3772         struct ixgbe_mac_info *mac = &hw->mac;
3773         uint32_t links_reg, in_msg;
3774         int ret_val = 0;
3775
3776         /* If we were hit with a reset drop the link */
3777         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3778                 mac->get_link_status = true;
3779
3780         if (!mac->get_link_status)
3781                 goto out;
3782
3783         /* if link status is down no point in checking to see if pf is up */
3784         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3785         if (!(links_reg & IXGBE_LINKS_UP))
3786                 goto out;
3787
3788         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3789          * before the link status is correct
3790          */
3791         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3792                 int i;
3793
3794                 for (i = 0; i < 5; i++) {
3795                         rte_delay_us(100);
3796                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3797
3798                         if (!(links_reg & IXGBE_LINKS_UP))
3799                                 goto out;
3800                 }
3801         }
3802
3803         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3804         case IXGBE_LINKS_SPEED_10G_82599:
3805                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3806                 if (hw->mac.type >= ixgbe_mac_X550) {
3807                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3808                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3809                 }
3810                 break;
3811         case IXGBE_LINKS_SPEED_1G_82599:
3812                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3813                 break;
3814         case IXGBE_LINKS_SPEED_100_82599:
3815                 *speed = IXGBE_LINK_SPEED_100_FULL;
3816                 if (hw->mac.type == ixgbe_mac_X550) {
3817                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3818                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3819                 }
3820                 break;
3821         case IXGBE_LINKS_SPEED_10_X550EM_A:
3822                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3823                 /* Since Reserved in older MAC's */
3824                 if (hw->mac.type >= ixgbe_mac_X550)
3825                         *speed = IXGBE_LINK_SPEED_10_FULL;
3826                 break;
3827         default:
3828                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3829         }
3830
3831         if (no_pflink_check) {
3832                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3833                         mac->get_link_status = true;
3834                 else
3835                         mac->get_link_status = false;
3836
3837                 goto out;
3838         }
3839         /* if the read failed it could just be a mailbox collision, best wait
3840          * until we are called again and don't report an error
3841          */
3842         if (mbx->ops.read(hw, &in_msg, 1, 0))
3843                 goto out;
3844
3845         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3846                 /* msg is not CTS and is NACK we must have lost CTS status */
3847                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3848                         ret_val = -1;
3849                 goto out;
3850         }
3851
3852         /* the pf is talking, if we timed out in the past we reinit */
3853         if (!mbx->timeout) {
3854                 ret_val = -1;
3855                 goto out;
3856         }
3857
3858         /* if we passed all the tests above then the link is up and we no
3859          * longer need to check for link
3860          */
3861         mac->get_link_status = false;
3862
3863 out:
3864         *link_up = !mac->get_link_status;
3865         return ret_val;
3866 }
3867
3868 /* return 0 means link status changed, -1 means not changed */
3869 static int
3870 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3871                             int wait_to_complete, int vf)
3872 {
3873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3874         struct rte_eth_link link;
3875         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3876         struct ixgbe_interrupt *intr =
3877                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3878         int link_up;
3879         int diag;
3880         u32 speed = 0;
3881         int wait = 1;
3882         bool autoneg = false;
3883
3884         memset(&link, 0, sizeof(link));
3885         link.link_status = ETH_LINK_DOWN;
3886         link.link_speed = 0;
3887         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3888         link.link_autoneg = ETH_LINK_AUTONEG;
3889
3890         hw->mac.get_link_status = true;
3891
3892         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3893                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3894                 speed = hw->phy.autoneg_advertised;
3895                 if (!speed)
3896                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3897                 ixgbe_setup_link(hw, speed, true);
3898         }
3899
3900         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3901         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3902                 wait = 0;
3903
3904         if (vf)
3905                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3906         else
3907                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3908
3909         if (diag != 0) {
3910                 link.link_speed = ETH_SPEED_NUM_100M;
3911                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3912                 return rte_eth_linkstatus_set(dev, &link);
3913         }
3914
3915         if (link_up == 0) {
3916                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3917                 return rte_eth_linkstatus_set(dev, &link);
3918         }
3919
3920         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3921         link.link_status = ETH_LINK_UP;
3922         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3923
3924         switch (link_speed) {
3925         default:
3926         case IXGBE_LINK_SPEED_UNKNOWN:
3927                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3928                 link.link_speed = ETH_SPEED_NUM_100M;
3929                 break;
3930
3931         case IXGBE_LINK_SPEED_100_FULL:
3932                 link.link_speed = ETH_SPEED_NUM_100M;
3933                 break;
3934
3935         case IXGBE_LINK_SPEED_1GB_FULL:
3936                 link.link_speed = ETH_SPEED_NUM_1G;
3937                 break;
3938
3939         case IXGBE_LINK_SPEED_2_5GB_FULL:
3940                 link.link_speed = ETH_SPEED_NUM_2_5G;
3941                 break;
3942
3943         case IXGBE_LINK_SPEED_5GB_FULL:
3944                 link.link_speed = ETH_SPEED_NUM_5G;
3945                 break;
3946
3947         case IXGBE_LINK_SPEED_10GB_FULL:
3948                 link.link_speed = ETH_SPEED_NUM_10G;
3949                 break;
3950         }
3951
3952         return rte_eth_linkstatus_set(dev, &link);
3953 }
3954
3955 static int
3956 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3957 {
3958         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3959 }
3960
3961 static int
3962 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3963 {
3964         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3965 }
3966
3967 static void
3968 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3969 {
3970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3971         uint32_t fctrl;
3972
3973         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3974         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3975         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3976 }
3977
3978 static void
3979 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3980 {
3981         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3982         uint32_t fctrl;
3983
3984         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3985         fctrl &= (~IXGBE_FCTRL_UPE);
3986         if (dev->data->all_multicast == 1)
3987                 fctrl |= IXGBE_FCTRL_MPE;
3988         else
3989                 fctrl &= (~IXGBE_FCTRL_MPE);
3990         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3991 }
3992
3993 static void
3994 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3995 {
3996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3997         uint32_t fctrl;
3998
3999         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4000         fctrl |= IXGBE_FCTRL_MPE;
4001         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4002 }
4003
4004 static void
4005 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4006 {
4007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4008         uint32_t fctrl;
4009
4010         if (dev->data->promiscuous == 1)
4011                 return; /* must remain in all_multicast mode */
4012
4013         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4014         fctrl &= (~IXGBE_FCTRL_MPE);
4015         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4016 }
4017
4018 /**
4019  * It clears the interrupt causes and enables the interrupt.
4020  * It will be called once only during nic initialized.
4021  *
4022  * @param dev
4023  *  Pointer to struct rte_eth_dev.
4024  * @param on
4025  *  Enable or Disable.
4026  *
4027  * @return
4028  *  - On success, zero.
4029  *  - On failure, a negative value.
4030  */
4031 static int
4032 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4033 {
4034         struct ixgbe_interrupt *intr =
4035                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4036
4037         ixgbe_dev_link_status_print(dev);
4038         if (on)
4039                 intr->mask |= IXGBE_EICR_LSC;
4040         else
4041                 intr->mask &= ~IXGBE_EICR_LSC;
4042
4043         return 0;
4044 }
4045
4046 /**
4047  * It clears the interrupt causes and enables the interrupt.
4048  * It will be called once only during nic initialized.
4049  *
4050  * @param dev
4051  *  Pointer to struct rte_eth_dev.
4052  *
4053  * @return
4054  *  - On success, zero.
4055  *  - On failure, a negative value.
4056  */
4057 static int
4058 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4059 {
4060         struct ixgbe_interrupt *intr =
4061                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4062
4063         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4064
4065         return 0;
4066 }
4067
4068 /**
4069  * It clears the interrupt causes and enables the interrupt.
4070  * It will be called once only during nic initialized.
4071  *
4072  * @param dev
4073  *  Pointer to struct rte_eth_dev.
4074  *
4075  * @return
4076  *  - On success, zero.
4077  *  - On failure, a negative value.
4078  */
4079 static int
4080 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4081 {
4082         struct ixgbe_interrupt *intr =
4083                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4084
4085         intr->mask |= IXGBE_EICR_LINKSEC;
4086
4087         return 0;
4088 }
4089
4090 /*
4091  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4092  *
4093  * @param dev
4094  *  Pointer to struct rte_eth_dev.
4095  *
4096  * @return
4097  *  - On success, zero.
4098  *  - On failure, a negative value.
4099  */
4100 static int
4101 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4102 {
4103         uint32_t eicr;
4104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4105         struct ixgbe_interrupt *intr =
4106                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4107
4108         /* clear all cause mask */
4109         ixgbe_disable_intr(hw);
4110
4111         /* read-on-clear nic registers here */
4112         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4113         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4114
4115         intr->flags = 0;
4116
4117         /* set flag for async link update */
4118         if (eicr & IXGBE_EICR_LSC)
4119                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4120
4121         if (eicr & IXGBE_EICR_MAILBOX)
4122                 intr->flags |= IXGBE_FLAG_MAILBOX;
4123
4124         if (eicr & IXGBE_EICR_LINKSEC)
4125                 intr->flags |= IXGBE_FLAG_MACSEC;
4126
4127         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4128             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4129             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4130                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4131
4132         return 0;
4133 }
4134
4135 /**
4136  * It gets and then prints the link status.
4137  *
4138  * @param dev
4139  *  Pointer to struct rte_eth_dev.
4140  *
4141  * @return
4142  *  - On success, zero.
4143  *  - On failure, a negative value.
4144  */
4145 static void
4146 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4147 {
4148         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4149         struct rte_eth_link link;
4150
4151         rte_eth_linkstatus_get(dev, &link);
4152
4153         if (link.link_status) {
4154                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4155                                         (int)(dev->data->port_id),
4156                                         (unsigned)link.link_speed,
4157                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4158                                         "full-duplex" : "half-duplex");
4159         } else {
4160                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4161                                 (int)(dev->data->port_id));
4162         }
4163         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4164                                 pci_dev->addr.domain,
4165                                 pci_dev->addr.bus,
4166                                 pci_dev->addr.devid,
4167                                 pci_dev->addr.function);
4168 }
4169
4170 /*
4171  * It executes link_update after knowing an interrupt occurred.
4172  *
4173  * @param dev
4174  *  Pointer to struct rte_eth_dev.
4175  *
4176  * @return
4177  *  - On success, zero.
4178  *  - On failure, a negative value.
4179  */
4180 static int
4181 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4182                            struct rte_intr_handle *intr_handle)
4183 {
4184         struct ixgbe_interrupt *intr =
4185                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4186         int64_t timeout;
4187         struct ixgbe_hw *hw =
4188                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4189
4190         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4191
4192         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4193                 ixgbe_pf_mbx_process(dev);
4194                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4195         }
4196
4197         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4198                 ixgbe_handle_lasi(hw);
4199                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4200         }
4201
4202         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4203                 struct rte_eth_link link;
4204
4205                 /* get the link status before link update, for predicting later */
4206                 rte_eth_linkstatus_get(dev, &link);
4207
4208                 ixgbe_dev_link_update(dev, 0);
4209
4210                 /* likely to up */
4211                 if (!link.link_status)
4212                         /* handle it 1 sec later, wait it being stable */
4213                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4214                 /* likely to down */
4215                 else
4216                         /* handle it 4 sec later, wait it being stable */
4217                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4218
4219                 ixgbe_dev_link_status_print(dev);
4220                 if (rte_eal_alarm_set(timeout * 1000,
4221                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4222                         PMD_DRV_LOG(ERR, "Error setting alarm");
4223                 else {
4224                         /* remember original mask */
4225                         intr->mask_original = intr->mask;
4226                         /* only disable lsc interrupt */
4227                         intr->mask &= ~IXGBE_EIMS_LSC;
4228                 }
4229         }
4230
4231         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4232         ixgbe_enable_intr(dev);
4233         rte_intr_enable(intr_handle);
4234
4235         return 0;
4236 }
4237
4238 /**
4239  * Interrupt handler which shall be registered for alarm callback for delayed
4240  * handling specific interrupt to wait for the stable nic state. As the
4241  * NIC interrupt state is not stable for ixgbe after link is just down,
4242  * it needs to wait 4 seconds to get the stable status.
4243  *
4244  * @param handle
4245  *  Pointer to interrupt handle.
4246  * @param param
4247  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4248  *
4249  * @return
4250  *  void
4251  */
4252 static void
4253 ixgbe_dev_interrupt_delayed_handler(void *param)
4254 {
4255         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4256         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4257         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4258         struct ixgbe_interrupt *intr =
4259                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4260         struct ixgbe_hw *hw =
4261                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262         uint32_t eicr;
4263
4264         ixgbe_disable_intr(hw);
4265
4266         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4267         if (eicr & IXGBE_EICR_MAILBOX)
4268                 ixgbe_pf_mbx_process(dev);
4269
4270         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4271                 ixgbe_handle_lasi(hw);
4272                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4273         }
4274
4275         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4276                 ixgbe_dev_link_update(dev, 0);
4277                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4278                 ixgbe_dev_link_status_print(dev);
4279                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4280                                               NULL);
4281         }
4282
4283         if (intr->flags & IXGBE_FLAG_MACSEC) {
4284                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4285                                               NULL);
4286                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4287         }
4288
4289         /* restore original mask */
4290         intr->mask = intr->mask_original;
4291         intr->mask_original = 0;
4292
4293         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4294         ixgbe_enable_intr(dev);
4295         rte_intr_enable(intr_handle);
4296 }
4297
4298 /**
4299  * Interrupt handler triggered by NIC  for handling
4300  * specific interrupt.
4301  *
4302  * @param handle
4303  *  Pointer to interrupt handle.
4304  * @param param
4305  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4306  *
4307  * @return
4308  *  void
4309  */
4310 static void
4311 ixgbe_dev_interrupt_handler(void *param)
4312 {
4313         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4314
4315         ixgbe_dev_interrupt_get_status(dev);
4316         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4317 }
4318
4319 static int
4320 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4321 {
4322         struct ixgbe_hw *hw;
4323
4324         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4325         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4326 }
4327
4328 static int
4329 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4330 {
4331         struct ixgbe_hw *hw;
4332
4333         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4334         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4335 }
4336
4337 static int
4338 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4339 {
4340         struct ixgbe_hw *hw;
4341         uint32_t mflcn_reg;
4342         uint32_t fccfg_reg;
4343         int rx_pause;
4344         int tx_pause;
4345
4346         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4347
4348         fc_conf->pause_time = hw->fc.pause_time;
4349         fc_conf->high_water = hw->fc.high_water[0];
4350         fc_conf->low_water = hw->fc.low_water[0];
4351         fc_conf->send_xon = hw->fc.send_xon;
4352         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4353
4354         /*
4355          * Return rx_pause status according to actual setting of
4356          * MFLCN register.
4357          */
4358         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4359         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4360                 rx_pause = 1;
4361         else
4362                 rx_pause = 0;
4363
4364         /*
4365          * Return tx_pause status according to actual setting of
4366          * FCCFG register.
4367          */
4368         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4369         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4370                 tx_pause = 1;
4371         else
4372                 tx_pause = 0;
4373
4374         if (rx_pause && tx_pause)
4375                 fc_conf->mode = RTE_FC_FULL;
4376         else if (rx_pause)
4377                 fc_conf->mode = RTE_FC_RX_PAUSE;
4378         else if (tx_pause)
4379                 fc_conf->mode = RTE_FC_TX_PAUSE;
4380         else
4381                 fc_conf->mode = RTE_FC_NONE;
4382
4383         return 0;
4384 }
4385
4386 static int
4387 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4388 {
4389         struct ixgbe_hw *hw;
4390         int err;
4391         uint32_t rx_buf_size;
4392         uint32_t max_high_water;
4393         uint32_t mflcn;
4394         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4395                 ixgbe_fc_none,
4396                 ixgbe_fc_rx_pause,
4397                 ixgbe_fc_tx_pause,
4398                 ixgbe_fc_full
4399         };
4400
4401         PMD_INIT_FUNC_TRACE();
4402
4403         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4404         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4405         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4406
4407         /*
4408          * At least reserve one Ethernet frame for watermark
4409          * high_water/low_water in kilo bytes for ixgbe
4410          */
4411         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4412         if ((fc_conf->high_water > max_high_water) ||
4413                 (fc_conf->high_water < fc_conf->low_water)) {
4414                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4415                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4416                 return -EINVAL;
4417         }
4418
4419         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4420         hw->fc.pause_time     = fc_conf->pause_time;
4421         hw->fc.high_water[0]  = fc_conf->high_water;
4422         hw->fc.low_water[0]   = fc_conf->low_water;
4423         hw->fc.send_xon       = fc_conf->send_xon;
4424         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4425
4426         err = ixgbe_fc_enable(hw);
4427
4428         /* Not negotiated is not an error case */
4429         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4430
4431                 /* check if we want to forward MAC frames - driver doesn't have native
4432                  * capability to do that, so we'll write the registers ourselves */
4433
4434                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4435
4436                 /* set or clear MFLCN.PMCF bit depending on configuration */
4437                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4438                         mflcn |= IXGBE_MFLCN_PMCF;
4439                 else
4440                         mflcn &= ~IXGBE_MFLCN_PMCF;
4441
4442                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4443                 IXGBE_WRITE_FLUSH(hw);
4444
4445                 return 0;
4446         }
4447
4448         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4449         return -EIO;
4450 }
4451
4452 /**
4453  *  ixgbe_pfc_enable_generic - Enable flow control
4454  *  @hw: pointer to hardware structure
4455  *  @tc_num: traffic class number
4456  *  Enable flow control according to the current settings.
4457  */
4458 static int
4459 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4460 {
4461         int ret_val = 0;
4462         uint32_t mflcn_reg, fccfg_reg;
4463         uint32_t reg;
4464         uint32_t fcrtl, fcrth;
4465         uint8_t i;
4466         uint8_t nb_rx_en;
4467
4468         /* Validate the water mark configuration */
4469         if (!hw->fc.pause_time) {
4470                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4471                 goto out;
4472         }
4473
4474         /* Low water mark of zero causes XOFF floods */
4475         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4476                  /* High/Low water can not be 0 */
4477                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4478                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4479                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4480                         goto out;
4481                 }
4482
4483                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4484                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4485                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4486                         goto out;
4487                 }
4488         }
4489         /* Negotiate the fc mode to use */
4490         ixgbe_fc_autoneg(hw);
4491
4492         /* Disable any previous flow control settings */
4493         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4494         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4495
4496         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4497         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4498
4499         switch (hw->fc.current_mode) {
4500         case ixgbe_fc_none:
4501                 /*
4502                  * If the count of enabled RX Priority Flow control >1,
4503                  * and the TX pause can not be disabled
4504                  */
4505                 nb_rx_en = 0;
4506                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4507                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4508                         if (reg & IXGBE_FCRTH_FCEN)
4509                                 nb_rx_en++;
4510                 }
4511                 if (nb_rx_en > 1)
4512                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4513                 break;
4514         case ixgbe_fc_rx_pause:
4515                 /*
4516                  * Rx Flow control is enabled and Tx Flow control is
4517                  * disabled by software override. Since there really
4518                  * isn't a way to advertise that we are capable of RX
4519                  * Pause ONLY, we will advertise that we support both
4520                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4521                  * disable the adapter's ability to send PAUSE frames.
4522                  */
4523                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4524                 /*
4525                  * If the count of enabled RX Priority Flow control >1,
4526                  * and the TX pause can not be disabled
4527                  */
4528                 nb_rx_en = 0;
4529                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4530                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4531                         if (reg & IXGBE_FCRTH_FCEN)
4532                                 nb_rx_en++;
4533                 }
4534                 if (nb_rx_en > 1)
4535                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4536                 break;
4537         case ixgbe_fc_tx_pause:
4538                 /*
4539                  * Tx Flow control is enabled, and Rx Flow control is
4540                  * disabled by software override.
4541                  */
4542                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4543                 break;
4544         case ixgbe_fc_full:
4545                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4546                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4547                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4548                 break;
4549         default:
4550                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4551                 ret_val = IXGBE_ERR_CONFIG;
4552                 goto out;
4553         }
4554
4555         /* Set 802.3x based flow control settings. */
4556         mflcn_reg |= IXGBE_MFLCN_DPF;
4557         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4558         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4559
4560         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4561         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4562                 hw->fc.high_water[tc_num]) {
4563                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4564                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4565                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4566         } else {
4567                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4568                 /*
4569                  * In order to prevent Tx hangs when the internal Tx
4570                  * switch is enabled we must set the high water mark
4571                  * to the maximum FCRTH value.  This allows the Tx
4572                  * switch to function even under heavy Rx workloads.
4573                  */
4574                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4575         }
4576         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4577
4578         /* Configure pause time (2 TCs per register) */
4579         reg = hw->fc.pause_time * 0x00010001;
4580         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4581                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4582
4583         /* Configure flow control refresh threshold value */
4584         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4585
4586 out:
4587         return ret_val;
4588 }
4589
4590 static int
4591 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4592 {
4593         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4594         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4595
4596         if (hw->mac.type != ixgbe_mac_82598EB) {
4597                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4598         }
4599         return ret_val;
4600 }
4601
4602 static int
4603 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4604 {
4605         int err;
4606         uint32_t rx_buf_size;
4607         uint32_t max_high_water;
4608         uint8_t tc_num;
4609         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4610         struct ixgbe_hw *hw =
4611                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4612         struct ixgbe_dcb_config *dcb_config =
4613                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4614
4615         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4616                 ixgbe_fc_none,
4617                 ixgbe_fc_rx_pause,
4618                 ixgbe_fc_tx_pause,
4619                 ixgbe_fc_full
4620         };
4621
4622         PMD_INIT_FUNC_TRACE();
4623
4624         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4625         tc_num = map[pfc_conf->priority];
4626         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4627         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4628         /*
4629          * At least reserve one Ethernet frame for watermark
4630          * high_water/low_water in kilo bytes for ixgbe
4631          */
4632         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4633         if ((pfc_conf->fc.high_water > max_high_water) ||
4634             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4635                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4636                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4637                 return -EINVAL;
4638         }
4639
4640         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4641         hw->fc.pause_time = pfc_conf->fc.pause_time;
4642         hw->fc.send_xon = pfc_conf->fc.send_xon;
4643         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4644         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4645
4646         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4647
4648         /* Not negotiated is not an error case */
4649         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4650                 return 0;
4651
4652         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4653         return -EIO;
4654 }
4655
4656 static int
4657 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4658                           struct rte_eth_rss_reta_entry64 *reta_conf,
4659                           uint16_t reta_size)
4660 {
4661         uint16_t i, sp_reta_size;
4662         uint8_t j, mask;
4663         uint32_t reta, r;
4664         uint16_t idx, shift;
4665         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4666         uint32_t reta_reg;
4667
4668         PMD_INIT_FUNC_TRACE();
4669
4670         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4671                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4672                         "NIC.");
4673                 return -ENOTSUP;
4674         }
4675
4676         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4677         if (reta_size != sp_reta_size) {
4678                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4679                         "(%d) doesn't match the number hardware can supported "
4680                         "(%d)", reta_size, sp_reta_size);
4681                 return -EINVAL;
4682         }
4683
4684         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4685                 idx = i / RTE_RETA_GROUP_SIZE;
4686                 shift = i % RTE_RETA_GROUP_SIZE;
4687                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4688                                                 IXGBE_4_BIT_MASK);
4689                 if (!mask)
4690                         continue;
4691                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4692                 if (mask == IXGBE_4_BIT_MASK)
4693                         r = 0;
4694                 else
4695                         r = IXGBE_READ_REG(hw, reta_reg);
4696                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4697                         if (mask & (0x1 << j))
4698                                 reta |= reta_conf[idx].reta[shift + j] <<
4699                                                         (CHAR_BIT * j);
4700                         else
4701                                 reta |= r & (IXGBE_8_BIT_MASK <<
4702                                                 (CHAR_BIT * j));
4703                 }
4704                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4705         }
4706
4707         return 0;
4708 }
4709
4710 static int
4711 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4712                          struct rte_eth_rss_reta_entry64 *reta_conf,
4713                          uint16_t reta_size)
4714 {
4715         uint16_t i, sp_reta_size;
4716         uint8_t j, mask;
4717         uint32_t reta;
4718         uint16_t idx, shift;
4719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4720         uint32_t reta_reg;
4721
4722         PMD_INIT_FUNC_TRACE();
4723         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4724         if (reta_size != sp_reta_size) {
4725                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4726                         "(%d) doesn't match the number hardware can supported "
4727                         "(%d)", reta_size, sp_reta_size);
4728                 return -EINVAL;
4729         }
4730
4731         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4732                 idx = i / RTE_RETA_GROUP_SIZE;
4733                 shift = i % RTE_RETA_GROUP_SIZE;
4734                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4735                                                 IXGBE_4_BIT_MASK);
4736                 if (!mask)
4737                         continue;
4738
4739                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4740                 reta = IXGBE_READ_REG(hw, reta_reg);
4741                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4742                         if (mask & (0x1 << j))
4743                                 reta_conf[idx].reta[shift + j] =
4744                                         ((reta >> (CHAR_BIT * j)) &
4745                                                 IXGBE_8_BIT_MASK);
4746                 }
4747         }
4748
4749         return 0;
4750 }
4751
4752 static int
4753 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4754                                 uint32_t index, uint32_t pool)
4755 {
4756         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4757         uint32_t enable_addr = 1;
4758
4759         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4760                              pool, enable_addr);
4761 }
4762
4763 static void
4764 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4765 {
4766         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4767
4768         ixgbe_clear_rar(hw, index);
4769 }
4770
4771 static void
4772 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4773 {
4774         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4775
4776         ixgbe_remove_rar(dev, 0);
4777
4778         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4779 }
4780
4781 static bool
4782 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4783 {
4784         if (strcmp(dev->device->driver->name, drv->driver.name))
4785                 return false;
4786
4787         return true;
4788 }
4789
4790 bool
4791 is_ixgbe_supported(struct rte_eth_dev *dev)
4792 {
4793         return is_device_supported(dev, &rte_ixgbe_pmd);
4794 }
4795
4796 static int
4797 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4798 {
4799         uint32_t hlreg0;
4800         uint32_t maxfrs;
4801         struct ixgbe_hw *hw;
4802         struct rte_eth_dev_info dev_info;
4803         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4804         struct rte_eth_dev_data *dev_data = dev->data;
4805
4806         ixgbe_dev_info_get(dev, &dev_info);
4807
4808         /* check that mtu is within the allowed range */
4809         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4810                 return -EINVAL;
4811
4812         /* If device is started, refuse mtu that requires the support of
4813          * scattered packets when this feature has not been enabled before.
4814          */
4815         if (dev_data->dev_started && !dev_data->scattered_rx &&
4816             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4817              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4818                 PMD_INIT_LOG(ERR, "Stop port first.");
4819                 return -EINVAL;
4820         }
4821
4822         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4823         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4824
4825         /* switch to jumbo mode if needed */
4826         if (frame_size > ETHER_MAX_LEN) {
4827                 dev->data->dev_conf.rxmode.offloads |=
4828                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4829                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4830         } else {
4831                 dev->data->dev_conf.rxmode.offloads &=
4832                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4833                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4834         }
4835         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4836
4837         /* update max frame size */
4838         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4839
4840         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4841         maxfrs &= 0x0000FFFF;
4842         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4843         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4844
4845         return 0;
4846 }
4847
4848 /*
4849  * Virtual Function operations
4850  */
4851 static void
4852 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4853 {
4854         PMD_INIT_FUNC_TRACE();
4855
4856         /* Clear interrupt mask to stop from interrupts being generated */
4857         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4858
4859         IXGBE_WRITE_FLUSH(hw);
4860 }
4861
4862 static void
4863 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4864 {
4865         PMD_INIT_FUNC_TRACE();
4866
4867         /* VF enable interrupt autoclean */
4868         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4869         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4870         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4871
4872         IXGBE_WRITE_FLUSH(hw);
4873 }
4874
4875 static int
4876 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4877 {
4878         struct rte_eth_conf *conf = &dev->data->dev_conf;
4879         struct ixgbe_adapter *adapter =
4880                         (struct ixgbe_adapter *)dev->data->dev_private;
4881         struct rte_eth_dev_info dev_info;
4882         uint64_t rx_offloads;
4883         uint64_t tx_offloads;
4884
4885         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4886                      dev->data->port_id);
4887
4888         ixgbevf_dev_info_get(dev, &dev_info);
4889         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4890         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4891                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4892                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4893                             rx_offloads, dev_info.rx_offload_capa);
4894                 return -ENOTSUP;
4895         }
4896         tx_offloads = dev->data->dev_conf.txmode.offloads;
4897         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4898                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4899                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4900                             tx_offloads, dev_info.tx_offload_capa);
4901                 return -ENOTSUP;
4902         }
4903
4904         /*
4905          * VF has no ability to enable/disable HW CRC
4906          * Keep the persistent behavior the same as Host PF
4907          */
4908 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4909         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4910                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4911                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4912         }
4913 #else
4914         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4915                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4916                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4917         }
4918 #endif
4919
4920         /*
4921          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4922          * allocation or vector Rx preconditions we will reset it.
4923          */
4924         adapter->rx_bulk_alloc_allowed = true;
4925         adapter->rx_vec_allowed = true;
4926
4927         return 0;
4928 }
4929
4930 static int
4931 ixgbevf_dev_start(struct rte_eth_dev *dev)
4932 {
4933         struct ixgbe_hw *hw =
4934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4935         uint32_t intr_vector = 0;
4936         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4937         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4938
4939         int err, mask = 0;
4940
4941         PMD_INIT_FUNC_TRACE();
4942
4943         err = hw->mac.ops.reset_hw(hw);
4944         if (err) {
4945                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4946                 return err;
4947         }
4948         hw->mac.get_link_status = true;
4949
4950         /* negotiate mailbox API version to use with the PF. */
4951         ixgbevf_negotiate_api(hw);
4952
4953         ixgbevf_dev_tx_init(dev);
4954
4955         /* This can fail when allocating mbufs for descriptor rings */
4956         err = ixgbevf_dev_rx_init(dev);
4957         if (err) {
4958                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4959                 ixgbe_dev_clear_queues(dev);
4960                 return err;
4961         }
4962
4963         /* Set vfta */
4964         ixgbevf_set_vfta_all(dev, 1);
4965
4966         /* Set HW strip */
4967         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4968                 ETH_VLAN_EXTEND_MASK;
4969         err = ixgbevf_vlan_offload_set(dev, mask);
4970         if (err) {
4971                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4972                 ixgbe_dev_clear_queues(dev);
4973                 return err;
4974         }
4975
4976         ixgbevf_dev_rxtx_start(dev);
4977
4978         /* check and configure queue intr-vector mapping */
4979         if (rte_intr_cap_multiple(intr_handle) &&
4980             dev->data->dev_conf.intr_conf.rxq) {
4981                 /* According to datasheet, only vector 0/1/2 can be used,
4982                  * now only one vector is used for Rx queue
4983                  */
4984                 intr_vector = 1;
4985                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4986                         return -1;
4987         }
4988
4989         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4990                 intr_handle->intr_vec =
4991                         rte_zmalloc("intr_vec",
4992                                     dev->data->nb_rx_queues * sizeof(int), 0);
4993                 if (intr_handle->intr_vec == NULL) {
4994                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4995                                      " intr_vec", dev->data->nb_rx_queues);
4996                         return -ENOMEM;
4997                 }
4998         }
4999         ixgbevf_configure_msix(dev);
5000
5001         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5002          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5003          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5004          * is not cleared, it will fail when following rte_intr_enable( ) tries
5005          * to map Rx queue interrupt to other VFIO vectors.
5006          * So clear uio/vfio intr/evevnfd first to avoid failure.
5007          */
5008         rte_intr_disable(intr_handle);
5009
5010         rte_intr_enable(intr_handle);
5011
5012         /* Re-enable interrupt for VF */
5013         ixgbevf_intr_enable(hw);
5014
5015         return 0;
5016 }
5017
5018 static void
5019 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5020 {
5021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5022         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5023         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5024
5025         PMD_INIT_FUNC_TRACE();
5026
5027         ixgbevf_intr_disable(hw);
5028
5029         hw->adapter_stopped = 1;
5030         ixgbe_stop_adapter(hw);
5031
5032         /*
5033           * Clear what we set, but we still keep shadow_vfta to
5034           * restore after device starts
5035           */
5036         ixgbevf_set_vfta_all(dev, 0);
5037
5038         /* Clear stored conf */
5039         dev->data->scattered_rx = 0;
5040
5041         ixgbe_dev_clear_queues(dev);
5042
5043         /* Clean datapath event and queue/vec mapping */
5044         rte_intr_efd_disable(intr_handle);
5045         if (intr_handle->intr_vec != NULL) {
5046                 rte_free(intr_handle->intr_vec);
5047                 intr_handle->intr_vec = NULL;
5048         }
5049 }
5050
5051 static void
5052 ixgbevf_dev_close(struct rte_eth_dev *dev)
5053 {
5054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5055
5056         PMD_INIT_FUNC_TRACE();
5057
5058         ixgbe_reset_hw(hw);
5059
5060         ixgbevf_dev_stop(dev);
5061
5062         ixgbe_dev_free_queues(dev);
5063
5064         /**
5065          * Remove the VF MAC address ro ensure
5066          * that the VF traffic goes to the PF
5067          * after stop, close and detach of the VF
5068          **/
5069         ixgbevf_remove_mac_addr(dev, 0);
5070 }
5071
5072 /*
5073  * Reset VF device
5074  */
5075 static int
5076 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5077 {
5078         int ret;
5079
5080         ret = eth_ixgbevf_dev_uninit(dev);
5081         if (ret)
5082                 return ret;
5083
5084         ret = eth_ixgbevf_dev_init(dev);
5085
5086         return ret;
5087 }
5088
5089 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5090 {
5091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5092         struct ixgbe_vfta *shadow_vfta =
5093                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5094         int i = 0, j = 0, vfta = 0, mask = 1;
5095
5096         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5097                 vfta = shadow_vfta->vfta[i];
5098                 if (vfta) {
5099                         mask = 1;
5100                         for (j = 0; j < 32; j++) {
5101                                 if (vfta & mask)
5102                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5103                                                        on, false);
5104                                 mask <<= 1;
5105                         }
5106                 }
5107         }
5108
5109 }
5110
5111 static int
5112 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5113 {
5114         struct ixgbe_hw *hw =
5115                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116         struct ixgbe_vfta *shadow_vfta =
5117                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5118         uint32_t vid_idx = 0;
5119         uint32_t vid_bit = 0;
5120         int ret = 0;
5121
5122         PMD_INIT_FUNC_TRACE();
5123
5124         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5125         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5126         if (ret) {
5127                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5128                 return ret;
5129         }
5130         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5131         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5132
5133         /* Save what we set and retore it after device reset */
5134         if (on)
5135                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5136         else
5137                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5138
5139         return 0;
5140 }
5141
5142 static void
5143 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5144 {
5145         struct ixgbe_hw *hw =
5146                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147         uint32_t ctrl;
5148
5149         PMD_INIT_FUNC_TRACE();
5150
5151         if (queue >= hw->mac.max_rx_queues)
5152                 return;
5153
5154         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5155         if (on)
5156                 ctrl |= IXGBE_RXDCTL_VME;
5157         else
5158                 ctrl &= ~IXGBE_RXDCTL_VME;
5159         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5160
5161         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5162 }
5163
5164 static int
5165 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5166 {
5167         struct ixgbe_hw *hw =
5168                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5169         struct ixgbe_rx_queue *rxq;
5170         uint16_t i;
5171         int on = 0;
5172
5173         /* VF function only support hw strip feature, others are not support */
5174         if (mask & ETH_VLAN_STRIP_MASK) {
5175                 for (i = 0; i < hw->mac.max_rx_queues; i++) {
5176                         rxq = dev->data->rx_queues[i];
5177                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5178                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5179                 }
5180         }
5181
5182         return 0;
5183 }
5184
5185 int
5186 ixgbe_vt_check(struct ixgbe_hw *hw)
5187 {
5188         uint32_t reg_val;
5189
5190         /* if Virtualization Technology is enabled */
5191         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5192         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5193                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5194                 return -1;
5195         }
5196
5197         return 0;
5198 }
5199
5200 static uint32_t
5201 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5202 {
5203         uint32_t vector = 0;
5204
5205         switch (hw->mac.mc_filter_type) {
5206         case 0:   /* use bits [47:36] of the address */
5207                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5208                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5209                 break;
5210         case 1:   /* use bits [46:35] of the address */
5211                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5212                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5213                 break;
5214         case 2:   /* use bits [45:34] of the address */
5215                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5216                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5217                 break;
5218         case 3:   /* use bits [43:32] of the address */
5219                 vector = ((uc_addr->addr_bytes[4]) |
5220                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5221                 break;
5222         default:  /* Invalid mc_filter_type */
5223                 break;
5224         }
5225
5226         /* vector can only be 12-bits or boundary will be exceeded */
5227         vector &= 0xFFF;
5228         return vector;
5229 }
5230
5231 static int
5232 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5233                         uint8_t on)
5234 {
5235         uint32_t vector;
5236         uint32_t uta_idx;
5237         uint32_t reg_val;
5238         uint32_t uta_shift;
5239         uint32_t rc;
5240         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5241         const uint32_t ixgbe_uta_bit_shift = 5;
5242         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5243         const uint32_t bit1 = 0x1;
5244
5245         struct ixgbe_hw *hw =
5246                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5247         struct ixgbe_uta_info *uta_info =
5248                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5249
5250         /* The UTA table only exists on 82599 hardware and newer */
5251         if (hw->mac.type < ixgbe_mac_82599EB)
5252                 return -ENOTSUP;
5253
5254         vector = ixgbe_uta_vector(hw, mac_addr);
5255         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5256         uta_shift = vector & ixgbe_uta_bit_mask;
5257
5258         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5259         if (rc == on)
5260                 return 0;
5261
5262         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5263         if (on) {
5264                 uta_info->uta_in_use++;
5265                 reg_val |= (bit1 << uta_shift);
5266                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5267         } else {
5268                 uta_info->uta_in_use--;
5269                 reg_val &= ~(bit1 << uta_shift);
5270                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5271         }
5272
5273         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5274
5275         if (uta_info->uta_in_use > 0)
5276                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5277                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5278         else
5279                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5280
5281         return 0;
5282 }
5283
5284 static int
5285 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5286 {
5287         int i;
5288         struct ixgbe_hw *hw =
5289                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5290         struct ixgbe_uta_info *uta_info =
5291                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5292
5293         /* The UTA table only exists on 82599 hardware and newer */
5294         if (hw->mac.type < ixgbe_mac_82599EB)
5295                 return -ENOTSUP;
5296
5297         if (on) {
5298                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5299                         uta_info->uta_shadow[i] = ~0;
5300                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5301                 }
5302         } else {
5303                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5304                         uta_info->uta_shadow[i] = 0;
5305                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5306                 }
5307         }
5308         return 0;
5309
5310 }
5311
5312 uint32_t
5313 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5314 {
5315         uint32_t new_val = orig_val;
5316
5317         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5318                 new_val |= IXGBE_VMOLR_AUPE;
5319         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5320                 new_val |= IXGBE_VMOLR_ROMPE;
5321         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5322                 new_val |= IXGBE_VMOLR_ROPE;
5323         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5324                 new_val |= IXGBE_VMOLR_BAM;
5325         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5326                 new_val |= IXGBE_VMOLR_MPE;
5327
5328         return new_val;
5329 }
5330
5331 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5332 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5333 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5334 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5335 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5336         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5337         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5338
5339 static int
5340 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5341                       struct rte_eth_mirror_conf *mirror_conf,
5342                       uint8_t rule_id, uint8_t on)
5343 {
5344         uint32_t mr_ctl, vlvf;
5345         uint32_t mp_lsb = 0;
5346         uint32_t mv_msb = 0;
5347         uint32_t mv_lsb = 0;
5348         uint32_t mp_msb = 0;
5349         uint8_t i = 0;
5350         int reg_index = 0;
5351         uint64_t vlan_mask = 0;
5352
5353         const uint8_t pool_mask_offset = 32;
5354         const uint8_t vlan_mask_offset = 32;
5355         const uint8_t dst_pool_offset = 8;
5356         const uint8_t rule_mr_offset  = 4;
5357         const uint8_t mirror_rule_mask = 0x0F;
5358
5359         struct ixgbe_mirror_info *mr_info =
5360                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5361         struct ixgbe_hw *hw =
5362                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5363         uint8_t mirror_type = 0;
5364
5365         if (ixgbe_vt_check(hw) < 0)
5366                 return -ENOTSUP;
5367
5368         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5369                 return -EINVAL;
5370
5371         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5372                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5373                             mirror_conf->rule_type);
5374                 return -EINVAL;
5375         }
5376
5377         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5378                 mirror_type |= IXGBE_MRCTL_VLME;
5379                 /* Check if vlan id is valid and find conresponding VLAN ID
5380                  * index in VLVF
5381                  */
5382                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5383                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5384                                 /* search vlan id related pool vlan filter
5385                                  * index
5386                                  */
5387                                 reg_index = ixgbe_find_vlvf_slot(
5388                                                 hw,
5389                                                 mirror_conf->vlan.vlan_id[i],
5390                                                 false);
5391                                 if (reg_index < 0)
5392                                         return -EINVAL;
5393                                 vlvf = IXGBE_READ_REG(hw,
5394                                                       IXGBE_VLVF(reg_index));
5395                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5396                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5397                                       mirror_conf->vlan.vlan_id[i]))
5398                                         vlan_mask |= (1ULL << reg_index);
5399                                 else
5400                                         return -EINVAL;
5401                         }
5402                 }
5403
5404                 if (on) {
5405                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5406                         mv_msb = vlan_mask >> vlan_mask_offset;
5407
5408                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5409                                                 mirror_conf->vlan.vlan_mask;
5410                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5411                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5412                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5413                                                 mirror_conf->vlan.vlan_id[i];
5414                         }
5415                 } else {
5416                         mv_lsb = 0;
5417                         mv_msb = 0;
5418                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5419                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5420                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5421                 }
5422         }
5423
5424         /**
5425          * if enable pool mirror, write related pool mask register,if disable
5426          * pool mirror, clear PFMRVM register
5427          */
5428         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5429                 mirror_type |= IXGBE_MRCTL_VPME;
5430                 if (on) {
5431                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5432                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5433                         mr_info->mr_conf[rule_id].pool_mask =
5434                                         mirror_conf->pool_mask;
5435
5436                 } else {
5437                         mp_lsb = 0;
5438                         mp_msb = 0;
5439                         mr_info->mr_conf[rule_id].pool_mask = 0;
5440                 }
5441         }
5442         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5443                 mirror_type |= IXGBE_MRCTL_UPME;
5444         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5445                 mirror_type |= IXGBE_MRCTL_DPME;
5446
5447         /* read  mirror control register and recalculate it */
5448         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5449
5450         if (on) {
5451                 mr_ctl |= mirror_type;
5452                 mr_ctl &= mirror_rule_mask;
5453                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5454         } else {
5455                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5456         }
5457
5458         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5459         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5460
5461         /* write mirrror control  register */
5462         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5463
5464         /* write pool mirrror control  register */
5465         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5466                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5467                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5468                                 mp_msb);
5469         }
5470         /* write VLAN mirrror control  register */
5471         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5472                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5473                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5474                                 mv_msb);
5475         }
5476
5477         return 0;
5478 }
5479
5480 static int
5481 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5482 {
5483         int mr_ctl = 0;
5484         uint32_t lsb_val = 0;
5485         uint32_t msb_val = 0;
5486         const uint8_t rule_mr_offset = 4;
5487
5488         struct ixgbe_hw *hw =
5489                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5490         struct ixgbe_mirror_info *mr_info =
5491                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5492
5493         if (ixgbe_vt_check(hw) < 0)
5494                 return -ENOTSUP;
5495
5496         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5497                 return -EINVAL;
5498
5499         memset(&mr_info->mr_conf[rule_id], 0,
5500                sizeof(struct rte_eth_mirror_conf));
5501
5502         /* clear PFVMCTL register */
5503         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5504
5505         /* clear pool mask register */
5506         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5507         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5508
5509         /* clear vlan mask register */
5510         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5511         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5512
5513         return 0;
5514 }
5515
5516 static int
5517 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5518 {
5519         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5520         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5521         uint32_t mask;
5522         struct ixgbe_hw *hw =
5523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5524         uint32_t vec = IXGBE_MISC_VEC_ID;
5525
5526         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5527         if (rte_intr_allow_others(intr_handle))
5528                 vec = IXGBE_RX_VEC_START;
5529         mask |= (1 << vec);
5530         RTE_SET_USED(queue_id);
5531         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5532
5533         rte_intr_enable(intr_handle);
5534
5535         return 0;
5536 }
5537
5538 static int
5539 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5540 {
5541         uint32_t mask;
5542         struct ixgbe_hw *hw =
5543                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5546         uint32_t vec = IXGBE_MISC_VEC_ID;
5547
5548         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5549         if (rte_intr_allow_others(intr_handle))
5550                 vec = IXGBE_RX_VEC_START;
5551         mask &= ~(1 << vec);
5552         RTE_SET_USED(queue_id);
5553         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5554
5555         return 0;
5556 }
5557
5558 static int
5559 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5560 {
5561         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5562         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5563         uint32_t mask;
5564         struct ixgbe_hw *hw =
5565                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5566         struct ixgbe_interrupt *intr =
5567                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5568
5569         if (queue_id < 16) {
5570                 ixgbe_disable_intr(hw);
5571                 intr->mask |= (1 << queue_id);
5572                 ixgbe_enable_intr(dev);
5573         } else if (queue_id < 32) {
5574                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5575                 mask &= (1 << queue_id);
5576                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5577         } else if (queue_id < 64) {
5578                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5579                 mask &= (1 << (queue_id - 32));
5580                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5581         }
5582         rte_intr_enable(intr_handle);
5583
5584         return 0;
5585 }
5586
5587 static int
5588 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5589 {
5590         uint32_t mask;
5591         struct ixgbe_hw *hw =
5592                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5593         struct ixgbe_interrupt *intr =
5594                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5595
5596         if (queue_id < 16) {
5597                 ixgbe_disable_intr(hw);
5598                 intr->mask &= ~(1 << queue_id);
5599                 ixgbe_enable_intr(dev);
5600         } else if (queue_id < 32) {
5601                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5602                 mask &= ~(1 << queue_id);
5603                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5604         } else if (queue_id < 64) {
5605                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5606                 mask &= ~(1 << (queue_id - 32));
5607                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5608         }
5609
5610         return 0;
5611 }
5612
5613 static void
5614 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5615                      uint8_t queue, uint8_t msix_vector)
5616 {
5617         uint32_t tmp, idx;
5618
5619         if (direction == -1) {
5620                 /* other causes */
5621                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5622                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5623                 tmp &= ~0xFF;
5624                 tmp |= msix_vector;
5625                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5626         } else {
5627                 /* rx or tx cause */
5628                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5629                 idx = ((16 * (queue & 1)) + (8 * direction));
5630                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5631                 tmp &= ~(0xFF << idx);
5632                 tmp |= (msix_vector << idx);
5633                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5634         }
5635 }
5636
5637 /**
5638  * set the IVAR registers, mapping interrupt causes to vectors
5639  * @param hw
5640  *  pointer to ixgbe_hw struct
5641  * @direction
5642  *  0 for Rx, 1 for Tx, -1 for other causes
5643  * @queue
5644  *  queue to map the corresponding interrupt to
5645  * @msix_vector
5646  *  the vector to map to the corresponding queue
5647  */
5648 static void
5649 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5650                    uint8_t queue, uint8_t msix_vector)
5651 {
5652         uint32_t tmp, idx;
5653
5654         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5655         if (hw->mac.type == ixgbe_mac_82598EB) {
5656                 if (direction == -1)
5657                         direction = 0;
5658                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5659                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5660                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5661                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5662                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5663         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5664                         (hw->mac.type == ixgbe_mac_X540) ||
5665                         (hw->mac.type == ixgbe_mac_X550)) {
5666                 if (direction == -1) {
5667                         /* other causes */
5668                         idx = ((queue & 1) * 8);
5669                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5670                         tmp &= ~(0xFF << idx);
5671                         tmp |= (msix_vector << idx);
5672                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5673                 } else {
5674                         /* rx or tx causes */
5675                         idx = ((16 * (queue & 1)) + (8 * direction));
5676                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5677                         tmp &= ~(0xFF << idx);
5678                         tmp |= (msix_vector << idx);
5679                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5680                 }
5681         }
5682 }
5683
5684 static void
5685 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5686 {
5687         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5688         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5689         struct ixgbe_hw *hw =
5690                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5691         uint32_t q_idx;
5692         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5693         uint32_t base = IXGBE_MISC_VEC_ID;
5694
5695         /* Configure VF other cause ivar */
5696         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5697
5698         /* won't configure msix register if no mapping is done
5699          * between intr vector and event fd.
5700          */
5701         if (!rte_intr_dp_is_en(intr_handle))
5702                 return;
5703
5704         if (rte_intr_allow_others(intr_handle)) {
5705                 base = IXGBE_RX_VEC_START;
5706                 vector_idx = IXGBE_RX_VEC_START;
5707         }
5708
5709         /* Configure all RX queues of VF */
5710         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5711                 /* Force all queue use vector 0,
5712                  * as IXGBE_VF_MAXMSIVECOTR = 1
5713                  */
5714                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5715                 intr_handle->intr_vec[q_idx] = vector_idx;
5716                 if (vector_idx < base + intr_handle->nb_efd - 1)
5717                         vector_idx++;
5718         }
5719 }
5720
5721 /**
5722  * Sets up the hardware to properly generate MSI-X interrupts
5723  * @hw
5724  *  board private structure
5725  */
5726 static void
5727 ixgbe_configure_msix(struct rte_eth_dev *dev)
5728 {
5729         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5730         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5731         struct ixgbe_hw *hw =
5732                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5733         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5734         uint32_t vec = IXGBE_MISC_VEC_ID;
5735         uint32_t mask;
5736         uint32_t gpie;
5737
5738         /* won't configure msix register if no mapping is done
5739          * between intr vector and event fd
5740          */
5741         if (!rte_intr_dp_is_en(intr_handle))
5742                 return;
5743
5744         if (rte_intr_allow_others(intr_handle))
5745                 vec = base = IXGBE_RX_VEC_START;
5746
5747         /* setup GPIE for MSI-x mode */
5748         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5749         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5750                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5751         /* auto clearing and auto setting corresponding bits in EIMS
5752          * when MSI-X interrupt is triggered
5753          */
5754         if (hw->mac.type == ixgbe_mac_82598EB) {
5755                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5756         } else {
5757                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5758                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5759         }
5760         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5761
5762         /* Populate the IVAR table and set the ITR values to the
5763          * corresponding register.
5764          */
5765         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5766              queue_id++) {
5767                 /* by default, 1:1 mapping */
5768                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5769                 intr_handle->intr_vec[queue_id] = vec;
5770                 if (vec < base + intr_handle->nb_efd - 1)
5771                         vec++;
5772         }
5773
5774         switch (hw->mac.type) {
5775         case ixgbe_mac_82598EB:
5776                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5777                                    IXGBE_MISC_VEC_ID);
5778                 break;
5779         case ixgbe_mac_82599EB:
5780         case ixgbe_mac_X540:
5781         case ixgbe_mac_X550:
5782                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5783                 break;
5784         default:
5785                 break;
5786         }
5787         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5788                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5789
5790         /* set up to autoclear timer, and the vectors */
5791         mask = IXGBE_EIMS_ENABLE_MASK;
5792         mask &= ~(IXGBE_EIMS_OTHER |
5793                   IXGBE_EIMS_MAILBOX |
5794                   IXGBE_EIMS_LSC);
5795
5796         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5797 }
5798
5799 int
5800 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5801                            uint16_t queue_idx, uint16_t tx_rate)
5802 {
5803         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5804         struct rte_eth_rxmode *rxmode;
5805         uint32_t rf_dec, rf_int;
5806         uint32_t bcnrc_val;
5807         uint16_t link_speed = dev->data->dev_link.link_speed;
5808
5809         if (queue_idx >= hw->mac.max_tx_queues)
5810                 return -EINVAL;
5811
5812         if (tx_rate != 0) {
5813                 /* Calculate the rate factor values to set */
5814                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5815                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5816                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5817
5818                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5819                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5820                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5821                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5822         } else {
5823                 bcnrc_val = 0;
5824         }
5825
5826         rxmode = &dev->data->dev_conf.rxmode;
5827         /*
5828          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5829          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5830          * set as 0x4.
5831          */
5832         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5833             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5834                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5835                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5836         else
5837                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5838                         IXGBE_MMW_SIZE_DEFAULT);
5839
5840         /* Set RTTBCNRC of queue X */
5841         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5842         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5843         IXGBE_WRITE_FLUSH(hw);
5844
5845         return 0;
5846 }
5847
5848 static int
5849 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5850                      __attribute__((unused)) uint32_t index,
5851                      __attribute__((unused)) uint32_t pool)
5852 {
5853         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5854         int diag;
5855
5856         /*
5857          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5858          * operation. Trap this case to avoid exhausting the [very limited]
5859          * set of PF resources used to store VF MAC addresses.
5860          */
5861         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5862                 return -1;
5863         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5864         if (diag != 0)
5865                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5866                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5867                             mac_addr->addr_bytes[0],
5868                             mac_addr->addr_bytes[1],
5869                             mac_addr->addr_bytes[2],
5870                             mac_addr->addr_bytes[3],
5871                             mac_addr->addr_bytes[4],
5872                             mac_addr->addr_bytes[5],
5873                             diag);
5874         return diag;
5875 }
5876
5877 static void
5878 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5879 {
5880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5881         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5882         struct ether_addr *mac_addr;
5883         uint32_t i;
5884         int diag;
5885
5886         /*
5887          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5888          * not support the deletion of a given MAC address.
5889          * Instead, it imposes to delete all MAC addresses, then to add again
5890          * all MAC addresses with the exception of the one to be deleted.
5891          */
5892         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5893
5894         /*
5895          * Add again all MAC addresses, with the exception of the deleted one
5896          * and of the permanent MAC address.
5897          */
5898         for (i = 0, mac_addr = dev->data->mac_addrs;
5899              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5900                 /* Skip the deleted MAC address */
5901                 if (i == index)
5902                         continue;
5903                 /* Skip NULL MAC addresses */
5904                 if (is_zero_ether_addr(mac_addr))
5905                         continue;
5906                 /* Skip the permanent MAC address */
5907                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5908                         continue;
5909                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5910                 if (diag != 0)
5911                         PMD_DRV_LOG(ERR,
5912                                     "Adding again MAC address "
5913                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5914                                     "diag=%d",
5915                                     mac_addr->addr_bytes[0],
5916                                     mac_addr->addr_bytes[1],
5917                                     mac_addr->addr_bytes[2],
5918                                     mac_addr->addr_bytes[3],
5919                                     mac_addr->addr_bytes[4],
5920                                     mac_addr->addr_bytes[5],
5921                                     diag);
5922         }
5923 }
5924
5925 static void
5926 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5927 {
5928         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5929
5930         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5931 }
5932
5933 int
5934 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5935                         struct rte_eth_syn_filter *filter,
5936                         bool add)
5937 {
5938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5939         struct ixgbe_filter_info *filter_info =
5940                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5941         uint32_t syn_info;
5942         uint32_t synqf;
5943
5944         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5945                 return -EINVAL;
5946
5947         syn_info = filter_info->syn_info;
5948
5949         if (add) {
5950                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5951                         return -EINVAL;
5952                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5953                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5954
5955                 if (filter->hig_pri)
5956                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5957                 else
5958                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5959         } else {
5960                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5961                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5962                         return -ENOENT;
5963                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5964         }
5965
5966         filter_info->syn_info = synqf;
5967         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5968         IXGBE_WRITE_FLUSH(hw);
5969         return 0;
5970 }
5971
5972 static int
5973 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5974                         struct rte_eth_syn_filter *filter)
5975 {
5976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5977         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5978
5979         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5980                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5981                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5982                 return 0;
5983         }
5984         return -ENOENT;
5985 }
5986
5987 static int
5988 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5989                         enum rte_filter_op filter_op,
5990                         void *arg)
5991 {
5992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5993         int ret;
5994
5995         MAC_TYPE_FILTER_SUP(hw->mac.type);
5996
5997         if (filter_op == RTE_ETH_FILTER_NOP)
5998                 return 0;
5999
6000         if (arg == NULL) {
6001                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6002                             filter_op);
6003                 return -EINVAL;
6004         }
6005
6006         switch (filter_op) {
6007         case RTE_ETH_FILTER_ADD:
6008                 ret = ixgbe_syn_filter_set(dev,
6009                                 (struct rte_eth_syn_filter *)arg,
6010                                 TRUE);
6011                 break;
6012         case RTE_ETH_FILTER_DELETE:
6013                 ret = ixgbe_syn_filter_set(dev,
6014                                 (struct rte_eth_syn_filter *)arg,
6015                                 FALSE);
6016                 break;
6017         case RTE_ETH_FILTER_GET:
6018                 ret = ixgbe_syn_filter_get(dev,
6019                                 (struct rte_eth_syn_filter *)arg);
6020                 break;
6021         default:
6022                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6023                 ret = -EINVAL;
6024                 break;
6025         }
6026
6027         return ret;
6028 }
6029
6030
6031 static inline enum ixgbe_5tuple_protocol
6032 convert_protocol_type(uint8_t protocol_value)
6033 {
6034         if (protocol_value == IPPROTO_TCP)
6035                 return IXGBE_FILTER_PROTOCOL_TCP;
6036         else if (protocol_value == IPPROTO_UDP)
6037                 return IXGBE_FILTER_PROTOCOL_UDP;
6038         else if (protocol_value == IPPROTO_SCTP)
6039                 return IXGBE_FILTER_PROTOCOL_SCTP;
6040         else
6041                 return IXGBE_FILTER_PROTOCOL_NONE;
6042 }
6043
6044 /* inject a 5-tuple filter to HW */
6045 static inline void
6046 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6047                            struct ixgbe_5tuple_filter *filter)
6048 {
6049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6050         int i;
6051         uint32_t ftqf, sdpqf;
6052         uint32_t l34timir = 0;
6053         uint8_t mask = 0xff;
6054
6055         i = filter->index;
6056
6057         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6058                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6059         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6060
6061         ftqf = (uint32_t)(filter->filter_info.proto &
6062                 IXGBE_FTQF_PROTOCOL_MASK);
6063         ftqf |= (uint32_t)((filter->filter_info.priority &
6064                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6065         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6066                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6067         if (filter->filter_info.dst_ip_mask == 0)
6068                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6069         if (filter->filter_info.src_port_mask == 0)
6070                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6071         if (filter->filter_info.dst_port_mask == 0)
6072                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6073         if (filter->filter_info.proto_mask == 0)
6074                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6075         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6076         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6077         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6078
6079         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6080         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6081         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6082         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6083
6084         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6085         l34timir |= (uint32_t)(filter->queue <<
6086                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6087         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6088 }
6089
6090 /*
6091  * add a 5tuple filter
6092  *
6093  * @param
6094  * dev: Pointer to struct rte_eth_dev.
6095  * index: the index the filter allocates.
6096  * filter: ponter to the filter that will be added.
6097  * rx_queue: the queue id the filter assigned to.
6098  *
6099  * @return
6100  *    - On success, zero.
6101  *    - On failure, a negative value.
6102  */
6103 static int
6104 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6105                         struct ixgbe_5tuple_filter *filter)
6106 {
6107         struct ixgbe_filter_info *filter_info =
6108                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6109         int i, idx, shift;
6110
6111         /*
6112          * look for an unused 5tuple filter index,
6113          * and insert the filter to list.
6114          */
6115         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6116                 idx = i / (sizeof(uint32_t) * NBBY);
6117                 shift = i % (sizeof(uint32_t) * NBBY);
6118                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6119                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6120                         filter->index = i;
6121                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6122                                           filter,
6123                                           entries);
6124                         break;
6125                 }
6126         }
6127         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6128                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6129                 return -ENOSYS;
6130         }
6131
6132         ixgbe_inject_5tuple_filter(dev, filter);
6133
6134         return 0;
6135 }
6136
6137 /*
6138  * remove a 5tuple filter
6139  *
6140  * @param
6141  * dev: Pointer to struct rte_eth_dev.
6142  * filter: the pointer of the filter will be removed.
6143  */
6144 static void
6145 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6146                         struct ixgbe_5tuple_filter *filter)
6147 {
6148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6149         struct ixgbe_filter_info *filter_info =
6150                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6151         uint16_t index = filter->index;
6152
6153         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6154                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6155         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6156         rte_free(filter);
6157
6158         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6159         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6160         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6161         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6162         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6163 }
6164
6165 static int
6166 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6167 {
6168         struct ixgbe_hw *hw;
6169         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6170         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6171
6172         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6173
6174         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6175                 return -EINVAL;
6176
6177         /* refuse mtu that requires the support of scattered packets when this
6178          * feature has not been enabled before.
6179          */
6180         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6181             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6182              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6183                 return -EINVAL;
6184
6185         /*
6186          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6187          * request of the version 2.0 of the mailbox API.
6188          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6189          * of the mailbox API.
6190          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6191          * prior to 3.11.33 which contains the following change:
6192          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6193          */
6194         ixgbevf_rlpml_set_vf(hw, max_frame);
6195
6196         /* update max frame size */
6197         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6198         return 0;
6199 }
6200
6201 static inline struct ixgbe_5tuple_filter *
6202 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6203                         struct ixgbe_5tuple_filter_info *key)
6204 {
6205         struct ixgbe_5tuple_filter *it;
6206
6207         TAILQ_FOREACH(it, filter_list, entries) {
6208                 if (memcmp(key, &it->filter_info,
6209                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6210                         return it;
6211                 }
6212         }
6213         return NULL;
6214 }
6215
6216 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6217 static inline int
6218 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6219                         struct ixgbe_5tuple_filter_info *filter_info)
6220 {
6221         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6222                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6223                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6224                 return -EINVAL;
6225
6226         switch (filter->dst_ip_mask) {
6227         case UINT32_MAX:
6228                 filter_info->dst_ip_mask = 0;
6229                 filter_info->dst_ip = filter->dst_ip;
6230                 break;
6231         case 0:
6232                 filter_info->dst_ip_mask = 1;
6233                 break;
6234         default:
6235                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6236                 return -EINVAL;
6237         }
6238
6239         switch (filter->src_ip_mask) {
6240         case UINT32_MAX:
6241                 filter_info->src_ip_mask = 0;
6242                 filter_info->src_ip = filter->src_ip;
6243                 break;
6244         case 0:
6245                 filter_info->src_ip_mask = 1;
6246                 break;
6247         default:
6248                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6249                 return -EINVAL;
6250         }
6251
6252         switch (filter->dst_port_mask) {
6253         case UINT16_MAX:
6254                 filter_info->dst_port_mask = 0;
6255                 filter_info->dst_port = filter->dst_port;
6256                 break;
6257         case 0:
6258                 filter_info->dst_port_mask = 1;
6259                 break;
6260         default:
6261                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6262                 return -EINVAL;
6263         }
6264
6265         switch (filter->src_port_mask) {
6266         case UINT16_MAX:
6267                 filter_info->src_port_mask = 0;
6268                 filter_info->src_port = filter->src_port;
6269                 break;
6270         case 0:
6271                 filter_info->src_port_mask = 1;
6272                 break;
6273         default:
6274                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6275                 return -EINVAL;
6276         }
6277
6278         switch (filter->proto_mask) {
6279         case UINT8_MAX:
6280                 filter_info->proto_mask = 0;
6281                 filter_info->proto =
6282                         convert_protocol_type(filter->proto);
6283                 break;
6284         case 0:
6285                 filter_info->proto_mask = 1;
6286                 break;
6287         default:
6288                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6289                 return -EINVAL;
6290         }
6291
6292         filter_info->priority = (uint8_t)filter->priority;
6293         return 0;
6294 }
6295
6296 /*
6297  * add or delete a ntuple filter
6298  *
6299  * @param
6300  * dev: Pointer to struct rte_eth_dev.
6301  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6302  * add: if true, add filter, if false, remove filter
6303  *
6304  * @return
6305  *    - On success, zero.
6306  *    - On failure, a negative value.
6307  */
6308 int
6309 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6310                         struct rte_eth_ntuple_filter *ntuple_filter,
6311                         bool add)
6312 {
6313         struct ixgbe_filter_info *filter_info =
6314                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6315         struct ixgbe_5tuple_filter_info filter_5tuple;
6316         struct ixgbe_5tuple_filter *filter;
6317         int ret;
6318
6319         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6320                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6321                 return -EINVAL;
6322         }
6323
6324         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6325         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6326         if (ret < 0)
6327                 return ret;
6328
6329         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6330                                          &filter_5tuple);
6331         if (filter != NULL && add) {
6332                 PMD_DRV_LOG(ERR, "filter exists.");
6333                 return -EEXIST;
6334         }
6335         if (filter == NULL && !add) {
6336                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6337                 return -ENOENT;
6338         }
6339
6340         if (add) {
6341                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6342                                 sizeof(struct ixgbe_5tuple_filter), 0);
6343                 if (filter == NULL)
6344                         return -ENOMEM;
6345                 rte_memcpy(&filter->filter_info,
6346                                  &filter_5tuple,
6347                                  sizeof(struct ixgbe_5tuple_filter_info));
6348                 filter->queue = ntuple_filter->queue;
6349                 ret = ixgbe_add_5tuple_filter(dev, filter);
6350                 if (ret < 0) {
6351                         rte_free(filter);
6352                         return ret;
6353                 }
6354         } else
6355                 ixgbe_remove_5tuple_filter(dev, filter);
6356
6357         return 0;
6358 }
6359
6360 /*
6361  * get a ntuple filter
6362  *
6363  * @param
6364  * dev: Pointer to struct rte_eth_dev.
6365  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6366  *
6367  * @return
6368  *    - On success, zero.
6369  *    - On failure, a negative value.
6370  */
6371 static int
6372 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6373                         struct rte_eth_ntuple_filter *ntuple_filter)
6374 {
6375         struct ixgbe_filter_info *filter_info =
6376                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6377         struct ixgbe_5tuple_filter_info filter_5tuple;
6378         struct ixgbe_5tuple_filter *filter;
6379         int ret;
6380
6381         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6382                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6383                 return -EINVAL;
6384         }
6385
6386         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6387         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6388         if (ret < 0)
6389                 return ret;
6390
6391         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6392                                          &filter_5tuple);
6393         if (filter == NULL) {
6394                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6395                 return -ENOENT;
6396         }
6397         ntuple_filter->queue = filter->queue;
6398         return 0;
6399 }
6400
6401 /*
6402  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6403  * @dev: pointer to rte_eth_dev structure
6404  * @filter_op:operation will be taken.
6405  * @arg: a pointer to specific structure corresponding to the filter_op
6406  *
6407  * @return
6408  *    - On success, zero.
6409  *    - On failure, a negative value.
6410  */
6411 static int
6412 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6413                                 enum rte_filter_op filter_op,
6414                                 void *arg)
6415 {
6416         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6417         int ret;
6418
6419         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6420
6421         if (filter_op == RTE_ETH_FILTER_NOP)
6422                 return 0;
6423
6424         if (arg == NULL) {
6425                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6426                             filter_op);
6427                 return -EINVAL;
6428         }
6429
6430         switch (filter_op) {
6431         case RTE_ETH_FILTER_ADD:
6432                 ret = ixgbe_add_del_ntuple_filter(dev,
6433                         (struct rte_eth_ntuple_filter *)arg,
6434                         TRUE);
6435                 break;
6436         case RTE_ETH_FILTER_DELETE:
6437                 ret = ixgbe_add_del_ntuple_filter(dev,
6438                         (struct rte_eth_ntuple_filter *)arg,
6439                         FALSE);
6440                 break;
6441         case RTE_ETH_FILTER_GET:
6442                 ret = ixgbe_get_ntuple_filter(dev,
6443                         (struct rte_eth_ntuple_filter *)arg);
6444                 break;
6445         default:
6446                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6447                 ret = -EINVAL;
6448                 break;
6449         }
6450         return ret;
6451 }
6452
6453 int
6454 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6455                         struct rte_eth_ethertype_filter *filter,
6456                         bool add)
6457 {
6458         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6459         struct ixgbe_filter_info *filter_info =
6460                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6461         uint32_t etqf = 0;
6462         uint32_t etqs = 0;
6463         int ret;
6464         struct ixgbe_ethertype_filter ethertype_filter;
6465
6466         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6467                 return -EINVAL;
6468
6469         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6470                 filter->ether_type == ETHER_TYPE_IPv6) {
6471                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6472                         " ethertype filter.", filter->ether_type);
6473                 return -EINVAL;
6474         }
6475
6476         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6477                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6478                 return -EINVAL;
6479         }
6480         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6481                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6482                 return -EINVAL;
6483         }
6484
6485         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6486         if (ret >= 0 && add) {
6487                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6488                             filter->ether_type);
6489                 return -EEXIST;
6490         }
6491         if (ret < 0 && !add) {
6492                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6493                             filter->ether_type);
6494                 return -ENOENT;
6495         }
6496
6497         if (add) {
6498                 etqf = IXGBE_ETQF_FILTER_EN;
6499                 etqf |= (uint32_t)filter->ether_type;
6500                 etqs |= (uint32_t)((filter->queue <<
6501                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6502                                     IXGBE_ETQS_RX_QUEUE);
6503                 etqs |= IXGBE_ETQS_QUEUE_EN;
6504
6505                 ethertype_filter.ethertype = filter->ether_type;
6506                 ethertype_filter.etqf = etqf;
6507                 ethertype_filter.etqs = etqs;
6508                 ethertype_filter.conf = FALSE;
6509                 ret = ixgbe_ethertype_filter_insert(filter_info,
6510                                                     &ethertype_filter);
6511                 if (ret < 0) {
6512                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6513                         return -ENOSPC;
6514                 }
6515         } else {
6516                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6517                 if (ret < 0)
6518                         return -ENOSYS;
6519         }
6520         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6521         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6522         IXGBE_WRITE_FLUSH(hw);
6523
6524         return 0;
6525 }
6526
6527 static int
6528 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6529                         struct rte_eth_ethertype_filter *filter)
6530 {
6531         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6532         struct ixgbe_filter_info *filter_info =
6533                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6534         uint32_t etqf, etqs;
6535         int ret;
6536
6537         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6538         if (ret < 0) {
6539                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6540                             filter->ether_type);
6541                 return -ENOENT;
6542         }
6543
6544         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6545         if (etqf & IXGBE_ETQF_FILTER_EN) {
6546                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6547                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6548                 filter->flags = 0;
6549                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6550                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6551                 return 0;
6552         }
6553         return -ENOENT;
6554 }
6555
6556 /*
6557  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6558  * @dev: pointer to rte_eth_dev structure
6559  * @filter_op:operation will be taken.
6560  * @arg: a pointer to specific structure corresponding to the filter_op
6561  */
6562 static int
6563 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6564                                 enum rte_filter_op filter_op,
6565                                 void *arg)
6566 {
6567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6568         int ret;
6569
6570         MAC_TYPE_FILTER_SUP(hw->mac.type);
6571
6572         if (filter_op == RTE_ETH_FILTER_NOP)
6573                 return 0;
6574
6575         if (arg == NULL) {
6576                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6577                             filter_op);
6578                 return -EINVAL;
6579         }
6580
6581         switch (filter_op) {
6582         case RTE_ETH_FILTER_ADD:
6583                 ret = ixgbe_add_del_ethertype_filter(dev,
6584                         (struct rte_eth_ethertype_filter *)arg,
6585                         TRUE);
6586                 break;
6587         case RTE_ETH_FILTER_DELETE:
6588                 ret = ixgbe_add_del_ethertype_filter(dev,
6589                         (struct rte_eth_ethertype_filter *)arg,
6590                         FALSE);
6591                 break;
6592         case RTE_ETH_FILTER_GET:
6593                 ret = ixgbe_get_ethertype_filter(dev,
6594                         (struct rte_eth_ethertype_filter *)arg);
6595                 break;
6596         default:
6597                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6598                 ret = -EINVAL;
6599                 break;
6600         }
6601         return ret;
6602 }
6603
6604 static int
6605 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6606                      enum rte_filter_type filter_type,
6607                      enum rte_filter_op filter_op,
6608                      void *arg)
6609 {
6610         int ret = 0;
6611
6612         switch (filter_type) {
6613         case RTE_ETH_FILTER_NTUPLE:
6614                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6615                 break;
6616         case RTE_ETH_FILTER_ETHERTYPE:
6617                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6618                 break;
6619         case RTE_ETH_FILTER_SYN:
6620                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6621                 break;
6622         case RTE_ETH_FILTER_FDIR:
6623                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6624                 break;
6625         case RTE_ETH_FILTER_L2_TUNNEL:
6626                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6627                 break;
6628         case RTE_ETH_FILTER_GENERIC:
6629                 if (filter_op != RTE_ETH_FILTER_GET)
6630                         return -EINVAL;
6631                 *(const void **)arg = &ixgbe_flow_ops;
6632                 break;
6633         default:
6634                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6635                                                         filter_type);
6636                 ret = -EINVAL;
6637                 break;
6638         }
6639
6640         return ret;
6641 }
6642
6643 static u8 *
6644 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6645                         u8 **mc_addr_ptr, u32 *vmdq)
6646 {
6647         u8 *mc_addr;
6648
6649         *vmdq = 0;
6650         mc_addr = *mc_addr_ptr;
6651         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6652         return mc_addr;
6653 }
6654
6655 static int
6656 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6657                           struct ether_addr *mc_addr_set,
6658                           uint32_t nb_mc_addr)
6659 {
6660         struct ixgbe_hw *hw;
6661         u8 *mc_addr_list;
6662
6663         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6664         mc_addr_list = (u8 *)mc_addr_set;
6665         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6666                                          ixgbe_dev_addr_list_itr, TRUE);
6667 }
6668
6669 static uint64_t
6670 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6671 {
6672         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6673         uint64_t systime_cycles;
6674
6675         switch (hw->mac.type) {
6676         case ixgbe_mac_X550:
6677         case ixgbe_mac_X550EM_x:
6678         case ixgbe_mac_X550EM_a:
6679                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6680                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6681                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6682                                 * NSEC_PER_SEC;
6683                 break;
6684         default:
6685                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6686                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6687                                 << 32;
6688         }
6689
6690         return systime_cycles;
6691 }
6692
6693 static uint64_t
6694 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6695 {
6696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6697         uint64_t rx_tstamp_cycles;
6698
6699         switch (hw->mac.type) {
6700         case ixgbe_mac_X550:
6701         case ixgbe_mac_X550EM_x:
6702         case ixgbe_mac_X550EM_a:
6703                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6704                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6705                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6706                                 * NSEC_PER_SEC;
6707                 break;
6708         default:
6709                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6710                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6711                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6712                                 << 32;
6713         }
6714
6715         return rx_tstamp_cycles;
6716 }
6717
6718 static uint64_t
6719 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6720 {
6721         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6722         uint64_t tx_tstamp_cycles;
6723
6724         switch (hw->mac.type) {
6725         case ixgbe_mac_X550:
6726         case ixgbe_mac_X550EM_x:
6727         case ixgbe_mac_X550EM_a:
6728                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6729                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6730                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6731                                 * NSEC_PER_SEC;
6732                 break;
6733         default:
6734                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6735                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6736                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6737                                 << 32;
6738         }
6739
6740         return tx_tstamp_cycles;
6741 }
6742
6743 static void
6744 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6745 {
6746         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6747         struct ixgbe_adapter *adapter =
6748                 (struct ixgbe_adapter *)dev->data->dev_private;
6749         struct rte_eth_link link;
6750         uint32_t incval = 0;
6751         uint32_t shift = 0;
6752
6753         /* Get current link speed. */
6754         ixgbe_dev_link_update(dev, 1);
6755         rte_eth_linkstatus_get(dev, &link);
6756
6757         switch (link.link_speed) {
6758         case ETH_SPEED_NUM_100M:
6759                 incval = IXGBE_INCVAL_100;
6760                 shift = IXGBE_INCVAL_SHIFT_100;
6761                 break;
6762         case ETH_SPEED_NUM_1G:
6763                 incval = IXGBE_INCVAL_1GB;
6764                 shift = IXGBE_INCVAL_SHIFT_1GB;
6765                 break;
6766         case ETH_SPEED_NUM_10G:
6767         default:
6768                 incval = IXGBE_INCVAL_10GB;
6769                 shift = IXGBE_INCVAL_SHIFT_10GB;
6770                 break;
6771         }
6772
6773         switch (hw->mac.type) {
6774         case ixgbe_mac_X550:
6775         case ixgbe_mac_X550EM_x:
6776         case ixgbe_mac_X550EM_a:
6777                 /* Independent of link speed. */
6778                 incval = 1;
6779                 /* Cycles read will be interpreted as ns. */
6780                 shift = 0;
6781                 /* Fall-through */
6782         case ixgbe_mac_X540:
6783                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6784                 break;
6785         case ixgbe_mac_82599EB:
6786                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6787                 shift -= IXGBE_INCVAL_SHIFT_82599;
6788                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6789                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6790                 break;
6791         default:
6792                 /* Not supported. */
6793                 return;
6794         }
6795
6796         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6797         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6798         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6799
6800         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6801         adapter->systime_tc.cc_shift = shift;
6802         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6803
6804         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6805         adapter->rx_tstamp_tc.cc_shift = shift;
6806         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6807
6808         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6809         adapter->tx_tstamp_tc.cc_shift = shift;
6810         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6811 }
6812
6813 static int
6814 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6815 {
6816         struct ixgbe_adapter *adapter =
6817                         (struct ixgbe_adapter *)dev->data->dev_private;
6818
6819         adapter->systime_tc.nsec += delta;
6820         adapter->rx_tstamp_tc.nsec += delta;
6821         adapter->tx_tstamp_tc.nsec += delta;
6822
6823         return 0;
6824 }
6825
6826 static int
6827 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6828 {
6829         uint64_t ns;
6830         struct ixgbe_adapter *adapter =
6831                         (struct ixgbe_adapter *)dev->data->dev_private;
6832
6833         ns = rte_timespec_to_ns(ts);
6834         /* Set the timecounters to a new value. */
6835         adapter->systime_tc.nsec = ns;
6836         adapter->rx_tstamp_tc.nsec = ns;
6837         adapter->tx_tstamp_tc.nsec = ns;
6838
6839         return 0;
6840 }
6841
6842 static int
6843 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6844 {
6845         uint64_t ns, systime_cycles;
6846         struct ixgbe_adapter *adapter =
6847                         (struct ixgbe_adapter *)dev->data->dev_private;
6848
6849         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6850         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6851         *ts = rte_ns_to_timespec(ns);
6852
6853         return 0;
6854 }
6855
6856 static int
6857 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6858 {
6859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6860         uint32_t tsync_ctl;
6861         uint32_t tsauxc;
6862
6863         /* Stop the timesync system time. */
6864         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6865         /* Reset the timesync system time value. */
6866         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6867         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6868
6869         /* Enable system time for platforms where it isn't on by default. */
6870         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6871         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6872         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6873
6874         ixgbe_start_timecounters(dev);
6875
6876         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6877         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6878                         (ETHER_TYPE_1588 |
6879                          IXGBE_ETQF_FILTER_EN |
6880                          IXGBE_ETQF_1588));
6881
6882         /* Enable timestamping of received PTP packets. */
6883         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6884         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6885         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6886
6887         /* Enable timestamping of transmitted PTP packets. */
6888         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6889         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6890         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6891
6892         IXGBE_WRITE_FLUSH(hw);
6893
6894         return 0;
6895 }
6896
6897 static int
6898 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6899 {
6900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6901         uint32_t tsync_ctl;
6902
6903         /* Disable timestamping of transmitted PTP packets. */
6904         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6905         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6906         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6907
6908         /* Disable timestamping of received PTP packets. */
6909         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6910         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6911         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6912
6913         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6914         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6915
6916         /* Stop incrementating the System Time registers. */
6917         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6918
6919         return 0;
6920 }
6921
6922 static int
6923 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6924                                  struct timespec *timestamp,
6925                                  uint32_t flags __rte_unused)
6926 {
6927         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6928         struct ixgbe_adapter *adapter =
6929                 (struct ixgbe_adapter *)dev->data->dev_private;
6930         uint32_t tsync_rxctl;
6931         uint64_t rx_tstamp_cycles;
6932         uint64_t ns;
6933
6934         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6935         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6936                 return -EINVAL;
6937
6938         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6939         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6940         *timestamp = rte_ns_to_timespec(ns);
6941
6942         return  0;
6943 }
6944
6945 static int
6946 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6947                                  struct timespec *timestamp)
6948 {
6949         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6950         struct ixgbe_adapter *adapter =
6951                 (struct ixgbe_adapter *)dev->data->dev_private;
6952         uint32_t tsync_txctl;
6953         uint64_t tx_tstamp_cycles;
6954         uint64_t ns;
6955
6956         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6957         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6958                 return -EINVAL;
6959
6960         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6961         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6962         *timestamp = rte_ns_to_timespec(ns);
6963
6964         return 0;
6965 }
6966
6967 static int
6968 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6969 {
6970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6971         int count = 0;
6972         int g_ind = 0;
6973         const struct reg_info *reg_group;
6974         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6975                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6976
6977         while ((reg_group = reg_set[g_ind++]))
6978                 count += ixgbe_regs_group_count(reg_group);
6979
6980         return count;
6981 }
6982
6983 static int
6984 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6985 {
6986         int count = 0;
6987         int g_ind = 0;
6988         const struct reg_info *reg_group;
6989
6990         while ((reg_group = ixgbevf_regs[g_ind++]))
6991                 count += ixgbe_regs_group_count(reg_group);
6992
6993         return count;
6994 }
6995
6996 static int
6997 ixgbe_get_regs(struct rte_eth_dev *dev,
6998               struct rte_dev_reg_info *regs)
6999 {
7000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7001         uint32_t *data = regs->data;
7002         int g_ind = 0;
7003         int count = 0;
7004         const struct reg_info *reg_group;
7005         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7006                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7007
7008         if (data == NULL) {
7009                 regs->length = ixgbe_get_reg_length(dev);
7010                 regs->width = sizeof(uint32_t);
7011                 return 0;
7012         }
7013
7014         /* Support only full register dump */
7015         if ((regs->length == 0) ||
7016             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7017                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7018                         hw->device_id;
7019                 while ((reg_group = reg_set[g_ind++]))
7020                         count += ixgbe_read_regs_group(dev, &data[count],
7021                                 reg_group);
7022                 return 0;
7023         }
7024
7025         return -ENOTSUP;
7026 }
7027
7028 static int
7029 ixgbevf_get_regs(struct rte_eth_dev *dev,
7030                 struct rte_dev_reg_info *regs)
7031 {
7032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7033         uint32_t *data = regs->data;
7034         int g_ind = 0;
7035         int count = 0;
7036         const struct reg_info *reg_group;
7037
7038         if (data == NULL) {
7039                 regs->length = ixgbevf_get_reg_length(dev);
7040                 regs->width = sizeof(uint32_t);
7041                 return 0;
7042         }
7043
7044         /* Support only full register dump */
7045         if ((regs->length == 0) ||
7046             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7047                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7048                         hw->device_id;
7049                 while ((reg_group = ixgbevf_regs[g_ind++]))
7050                         count += ixgbe_read_regs_group(dev, &data[count],
7051                                                       reg_group);
7052                 return 0;
7053         }
7054
7055         return -ENOTSUP;
7056 }
7057
7058 static int
7059 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7060 {
7061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7062
7063         /* Return unit is byte count */
7064         return hw->eeprom.word_size * 2;
7065 }
7066
7067 static int
7068 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7069                 struct rte_dev_eeprom_info *in_eeprom)
7070 {
7071         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7072         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7073         uint16_t *data = in_eeprom->data;
7074         int first, length;
7075
7076         first = in_eeprom->offset >> 1;
7077         length = in_eeprom->length >> 1;
7078         if ((first > hw->eeprom.word_size) ||
7079             ((first + length) > hw->eeprom.word_size))
7080                 return -EINVAL;
7081
7082         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7083
7084         return eeprom->ops.read_buffer(hw, first, length, data);
7085 }
7086
7087 static int
7088 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7089                 struct rte_dev_eeprom_info *in_eeprom)
7090 {
7091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7092         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7093         uint16_t *data = in_eeprom->data;
7094         int first, length;
7095
7096         first = in_eeprom->offset >> 1;
7097         length = in_eeprom->length >> 1;
7098         if ((first > hw->eeprom.word_size) ||
7099             ((first + length) > hw->eeprom.word_size))
7100                 return -EINVAL;
7101
7102         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7103
7104         return eeprom->ops.write_buffer(hw,  first, length, data);
7105 }
7106
7107 uint16_t
7108 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7109         switch (mac_type) {
7110         case ixgbe_mac_X550:
7111         case ixgbe_mac_X550EM_x:
7112         case ixgbe_mac_X550EM_a:
7113                 return ETH_RSS_RETA_SIZE_512;
7114         case ixgbe_mac_X550_vf:
7115         case ixgbe_mac_X550EM_x_vf:
7116         case ixgbe_mac_X550EM_a_vf:
7117                 return ETH_RSS_RETA_SIZE_64;
7118         default:
7119                 return ETH_RSS_RETA_SIZE_128;
7120         }
7121 }
7122
7123 uint32_t
7124 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7125         switch (mac_type) {
7126         case ixgbe_mac_X550:
7127         case ixgbe_mac_X550EM_x:
7128         case ixgbe_mac_X550EM_a:
7129                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7130                         return IXGBE_RETA(reta_idx >> 2);
7131                 else
7132                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7133         case ixgbe_mac_X550_vf:
7134         case ixgbe_mac_X550EM_x_vf:
7135         case ixgbe_mac_X550EM_a_vf:
7136                 return IXGBE_VFRETA(reta_idx >> 2);
7137         default:
7138                 return IXGBE_RETA(reta_idx >> 2);
7139         }
7140 }
7141
7142 uint32_t
7143 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7144         switch (mac_type) {
7145         case ixgbe_mac_X550_vf:
7146         case ixgbe_mac_X550EM_x_vf:
7147         case ixgbe_mac_X550EM_a_vf:
7148                 return IXGBE_VFMRQC;
7149         default:
7150                 return IXGBE_MRQC;
7151         }
7152 }
7153
7154 uint32_t
7155 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7156         switch (mac_type) {
7157         case ixgbe_mac_X550_vf:
7158         case ixgbe_mac_X550EM_x_vf:
7159         case ixgbe_mac_X550EM_a_vf:
7160                 return IXGBE_VFRSSRK(i);
7161         default:
7162                 return IXGBE_RSSRK(i);
7163         }
7164 }
7165
7166 bool
7167 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7168         switch (mac_type) {
7169         case ixgbe_mac_82599_vf:
7170         case ixgbe_mac_X540_vf:
7171                 return 0;
7172         default:
7173                 return 1;
7174         }
7175 }
7176
7177 static int
7178 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7179                         struct rte_eth_dcb_info *dcb_info)
7180 {
7181         struct ixgbe_dcb_config *dcb_config =
7182                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7183         struct ixgbe_dcb_tc_config *tc;
7184         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7185         uint8_t nb_tcs;
7186         uint8_t i, j;
7187
7188         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7189                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7190         else
7191                 dcb_info->nb_tcs = 1;
7192
7193         tc_queue = &dcb_info->tc_queue;
7194         nb_tcs = dcb_info->nb_tcs;
7195
7196         if (dcb_config->vt_mode) { /* vt is enabled*/
7197                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7198                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7199                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7200                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7201                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7202                         for (j = 0; j < nb_tcs; j++) {
7203                                 tc_queue->tc_rxq[0][j].base = j;
7204                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7205                                 tc_queue->tc_txq[0][j].base = j;
7206                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7207                         }
7208                 } else {
7209                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7210                                 for (j = 0; j < nb_tcs; j++) {
7211                                         tc_queue->tc_rxq[i][j].base =
7212                                                 i * nb_tcs + j;
7213                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7214                                         tc_queue->tc_txq[i][j].base =
7215                                                 i * nb_tcs + j;
7216                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7217                                 }
7218                         }
7219                 }
7220         } else { /* vt is disabled*/
7221                 struct rte_eth_dcb_rx_conf *rx_conf =
7222                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7223                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7224                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7225                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7226                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7227                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7228                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7229                         }
7230                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7231                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7232                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7233                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7234                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7235                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7236                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7237                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7238                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7239                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7240                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7241                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7242                         }
7243                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7244                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7245                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7246                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7247                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7248                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7249                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7250                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7251                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7252                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7253                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7254                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7255                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7256                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7257                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7258                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7259                 }
7260         }
7261         for (i = 0; i < dcb_info->nb_tcs; i++) {
7262                 tc = &dcb_config->tc_config[i];
7263                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7264         }
7265         return 0;
7266 }
7267
7268 /* Update e-tag ether type */
7269 static int
7270 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7271                             uint16_t ether_type)
7272 {
7273         uint32_t etag_etype;
7274
7275         if (hw->mac.type != ixgbe_mac_X550 &&
7276             hw->mac.type != ixgbe_mac_X550EM_x &&
7277             hw->mac.type != ixgbe_mac_X550EM_a) {
7278                 return -ENOTSUP;
7279         }
7280
7281         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7282         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7283         etag_etype |= ether_type;
7284         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7285         IXGBE_WRITE_FLUSH(hw);
7286
7287         return 0;
7288 }
7289
7290 /* Config l2 tunnel ether type */
7291 static int
7292 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7293                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7294 {
7295         int ret = 0;
7296         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7297         struct ixgbe_l2_tn_info *l2_tn_info =
7298                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7299
7300         if (l2_tunnel == NULL)
7301                 return -EINVAL;
7302
7303         switch (l2_tunnel->l2_tunnel_type) {
7304         case RTE_L2_TUNNEL_TYPE_E_TAG:
7305                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7306                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7307                 break;
7308         default:
7309                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7310                 ret = -EINVAL;
7311                 break;
7312         }
7313
7314         return ret;
7315 }
7316
7317 /* Enable e-tag tunnel */
7318 static int
7319 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7320 {
7321         uint32_t etag_etype;
7322
7323         if (hw->mac.type != ixgbe_mac_X550 &&
7324             hw->mac.type != ixgbe_mac_X550EM_x &&
7325             hw->mac.type != ixgbe_mac_X550EM_a) {
7326                 return -ENOTSUP;
7327         }
7328
7329         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7330         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7331         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7332         IXGBE_WRITE_FLUSH(hw);
7333
7334         return 0;
7335 }
7336
7337 /* Enable l2 tunnel */
7338 static int
7339 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7340                            enum rte_eth_tunnel_type l2_tunnel_type)
7341 {
7342         int ret = 0;
7343         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7344         struct ixgbe_l2_tn_info *l2_tn_info =
7345                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7346
7347         switch (l2_tunnel_type) {
7348         case RTE_L2_TUNNEL_TYPE_E_TAG:
7349                 l2_tn_info->e_tag_en = TRUE;
7350                 ret = ixgbe_e_tag_enable(hw);
7351                 break;
7352         default:
7353                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7354                 ret = -EINVAL;
7355                 break;
7356         }
7357
7358         return ret;
7359 }
7360
7361 /* Disable e-tag tunnel */
7362 static int
7363 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7364 {
7365         uint32_t etag_etype;
7366
7367         if (hw->mac.type != ixgbe_mac_X550 &&
7368             hw->mac.type != ixgbe_mac_X550EM_x &&
7369             hw->mac.type != ixgbe_mac_X550EM_a) {
7370                 return -ENOTSUP;
7371         }
7372
7373         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7374         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7375         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7376         IXGBE_WRITE_FLUSH(hw);
7377
7378         return 0;
7379 }
7380
7381 /* Disable l2 tunnel */
7382 static int
7383 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7384                             enum rte_eth_tunnel_type l2_tunnel_type)
7385 {
7386         int ret = 0;
7387         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7388         struct ixgbe_l2_tn_info *l2_tn_info =
7389                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7390
7391         switch (l2_tunnel_type) {
7392         case RTE_L2_TUNNEL_TYPE_E_TAG:
7393                 l2_tn_info->e_tag_en = FALSE;
7394                 ret = ixgbe_e_tag_disable(hw);
7395                 break;
7396         default:
7397                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7398                 ret = -EINVAL;
7399                 break;
7400         }
7401
7402         return ret;
7403 }
7404
7405 static int
7406 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7407                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7408 {
7409         int ret = 0;
7410         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7411         uint32_t i, rar_entries;
7412         uint32_t rar_low, rar_high;
7413
7414         if (hw->mac.type != ixgbe_mac_X550 &&
7415             hw->mac.type != ixgbe_mac_X550EM_x &&
7416             hw->mac.type != ixgbe_mac_X550EM_a) {
7417                 return -ENOTSUP;
7418         }
7419
7420         rar_entries = ixgbe_get_num_rx_addrs(hw);
7421
7422         for (i = 1; i < rar_entries; i++) {
7423                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7424                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7425                 if ((rar_high & IXGBE_RAH_AV) &&
7426                     (rar_high & IXGBE_RAH_ADTYPE) &&
7427                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7428                      l2_tunnel->tunnel_id)) {
7429                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7430                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7431
7432                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7433
7434                         return ret;
7435                 }
7436         }
7437
7438         return ret;
7439 }
7440
7441 static int
7442 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7443                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7444 {
7445         int ret = 0;
7446         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7447         uint32_t i, rar_entries;
7448         uint32_t rar_low, rar_high;
7449
7450         if (hw->mac.type != ixgbe_mac_X550 &&
7451             hw->mac.type != ixgbe_mac_X550EM_x &&
7452             hw->mac.type != ixgbe_mac_X550EM_a) {
7453                 return -ENOTSUP;
7454         }
7455
7456         /* One entry for one tunnel. Try to remove potential existing entry. */
7457         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7458
7459         rar_entries = ixgbe_get_num_rx_addrs(hw);
7460
7461         for (i = 1; i < rar_entries; i++) {
7462                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7463                 if (rar_high & IXGBE_RAH_AV) {
7464                         continue;
7465                 } else {
7466                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7467                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7468                         rar_low = l2_tunnel->tunnel_id;
7469
7470                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7471                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7472
7473                         return ret;
7474                 }
7475         }
7476
7477         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7478                      " Please remove a rule before adding a new one.");
7479         return -EINVAL;
7480 }
7481
7482 static inline struct ixgbe_l2_tn_filter *
7483 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7484                           struct ixgbe_l2_tn_key *key)
7485 {
7486         int ret;
7487
7488         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7489         if (ret < 0)
7490                 return NULL;
7491
7492         return l2_tn_info->hash_map[ret];
7493 }
7494
7495 static inline int
7496 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7497                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7498 {
7499         int ret;
7500
7501         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7502                                &l2_tn_filter->key);
7503
7504         if (ret < 0) {
7505                 PMD_DRV_LOG(ERR,
7506                             "Failed to insert L2 tunnel filter"
7507                             " to hash table %d!",
7508                             ret);
7509                 return ret;
7510         }
7511
7512         l2_tn_info->hash_map[ret] = l2_tn_filter;
7513
7514         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7515
7516         return 0;
7517 }
7518
7519 static inline int
7520 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7521                           struct ixgbe_l2_tn_key *key)
7522 {
7523         int ret;
7524         struct ixgbe_l2_tn_filter *l2_tn_filter;
7525
7526         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7527
7528         if (ret < 0) {
7529                 PMD_DRV_LOG(ERR,
7530                             "No such L2 tunnel filter to delete %d!",
7531                             ret);
7532                 return ret;
7533         }
7534
7535         l2_tn_filter = l2_tn_info->hash_map[ret];
7536         l2_tn_info->hash_map[ret] = NULL;
7537
7538         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7539         rte_free(l2_tn_filter);
7540
7541         return 0;
7542 }
7543
7544 /* Add l2 tunnel filter */
7545 int
7546 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7547                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7548                                bool restore)
7549 {
7550         int ret;
7551         struct ixgbe_l2_tn_info *l2_tn_info =
7552                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7553         struct ixgbe_l2_tn_key key;
7554         struct ixgbe_l2_tn_filter *node;
7555
7556         if (!restore) {
7557                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7558                 key.tn_id = l2_tunnel->tunnel_id;
7559
7560                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7561
7562                 if (node) {
7563                         PMD_DRV_LOG(ERR,
7564                                     "The L2 tunnel filter already exists!");
7565                         return -EINVAL;
7566                 }
7567
7568                 node = rte_zmalloc("ixgbe_l2_tn",
7569                                    sizeof(struct ixgbe_l2_tn_filter),
7570                                    0);
7571                 if (!node)
7572                         return -ENOMEM;
7573
7574                 rte_memcpy(&node->key,
7575                                  &key,
7576                                  sizeof(struct ixgbe_l2_tn_key));
7577                 node->pool = l2_tunnel->pool;
7578                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7579                 if (ret < 0) {
7580                         rte_free(node);
7581                         return ret;
7582                 }
7583         }
7584
7585         switch (l2_tunnel->l2_tunnel_type) {
7586         case RTE_L2_TUNNEL_TYPE_E_TAG:
7587                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7588                 break;
7589         default:
7590                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7591                 ret = -EINVAL;
7592                 break;
7593         }
7594
7595         if ((!restore) && (ret < 0))
7596                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7597
7598         return ret;
7599 }
7600
7601 /* Delete l2 tunnel filter */
7602 int
7603 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7604                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7605 {
7606         int ret;
7607         struct ixgbe_l2_tn_info *l2_tn_info =
7608                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7609         struct ixgbe_l2_tn_key key;
7610
7611         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7612         key.tn_id = l2_tunnel->tunnel_id;
7613         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7614         if (ret < 0)
7615                 return ret;
7616
7617         switch (l2_tunnel->l2_tunnel_type) {
7618         case RTE_L2_TUNNEL_TYPE_E_TAG:
7619                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7620                 break;
7621         default:
7622                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7623                 ret = -EINVAL;
7624                 break;
7625         }
7626
7627         return ret;
7628 }
7629
7630 /**
7631  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7632  * @dev: pointer to rte_eth_dev structure
7633  * @filter_op:operation will be taken.
7634  * @arg: a pointer to specific structure corresponding to the filter_op
7635  */
7636 static int
7637 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7638                                   enum rte_filter_op filter_op,
7639                                   void *arg)
7640 {
7641         int ret;
7642
7643         if (filter_op == RTE_ETH_FILTER_NOP)
7644                 return 0;
7645
7646         if (arg == NULL) {
7647                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7648                             filter_op);
7649                 return -EINVAL;
7650         }
7651
7652         switch (filter_op) {
7653         case RTE_ETH_FILTER_ADD:
7654                 ret = ixgbe_dev_l2_tunnel_filter_add
7655                         (dev,
7656                          (struct rte_eth_l2_tunnel_conf *)arg,
7657                          FALSE);
7658                 break;
7659         case RTE_ETH_FILTER_DELETE:
7660                 ret = ixgbe_dev_l2_tunnel_filter_del
7661                         (dev,
7662                          (struct rte_eth_l2_tunnel_conf *)arg);
7663                 break;
7664         default:
7665                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7666                 ret = -EINVAL;
7667                 break;
7668         }
7669         return ret;
7670 }
7671
7672 static int
7673 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7674 {
7675         int ret = 0;
7676         uint32_t ctrl;
7677         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7678
7679         if (hw->mac.type != ixgbe_mac_X550 &&
7680             hw->mac.type != ixgbe_mac_X550EM_x &&
7681             hw->mac.type != ixgbe_mac_X550EM_a) {
7682                 return -ENOTSUP;
7683         }
7684
7685         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7686         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7687         if (en)
7688                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7689         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7690
7691         return ret;
7692 }
7693
7694 /* Enable l2 tunnel forwarding */
7695 static int
7696 ixgbe_dev_l2_tunnel_forwarding_enable
7697         (struct rte_eth_dev *dev,
7698          enum rte_eth_tunnel_type l2_tunnel_type)
7699 {
7700         struct ixgbe_l2_tn_info *l2_tn_info =
7701                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7702         int ret = 0;
7703
7704         switch (l2_tunnel_type) {
7705         case RTE_L2_TUNNEL_TYPE_E_TAG:
7706                 l2_tn_info->e_tag_fwd_en = TRUE;
7707                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7708                 break;
7709         default:
7710                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7711                 ret = -EINVAL;
7712                 break;
7713         }
7714
7715         return ret;
7716 }
7717
7718 /* Disable l2 tunnel forwarding */
7719 static int
7720 ixgbe_dev_l2_tunnel_forwarding_disable
7721         (struct rte_eth_dev *dev,
7722          enum rte_eth_tunnel_type l2_tunnel_type)
7723 {
7724         struct ixgbe_l2_tn_info *l2_tn_info =
7725                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7726         int ret = 0;
7727
7728         switch (l2_tunnel_type) {
7729         case RTE_L2_TUNNEL_TYPE_E_TAG:
7730                 l2_tn_info->e_tag_fwd_en = FALSE;
7731                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7732                 break;
7733         default:
7734                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7735                 ret = -EINVAL;
7736                 break;
7737         }
7738
7739         return ret;
7740 }
7741
7742 static int
7743 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7744                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7745                              bool en)
7746 {
7747         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7748         int ret = 0;
7749         uint32_t vmtir, vmvir;
7750         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7751
7752         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7753                 PMD_DRV_LOG(ERR,
7754                             "VF id %u should be less than %u",
7755                             l2_tunnel->vf_id,
7756                             pci_dev->max_vfs);
7757                 return -EINVAL;
7758         }
7759
7760         if (hw->mac.type != ixgbe_mac_X550 &&
7761             hw->mac.type != ixgbe_mac_X550EM_x &&
7762             hw->mac.type != ixgbe_mac_X550EM_a) {
7763                 return -ENOTSUP;
7764         }
7765
7766         if (en)
7767                 vmtir = l2_tunnel->tunnel_id;
7768         else
7769                 vmtir = 0;
7770
7771         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7772
7773         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7774         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7775         if (en)
7776                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7777         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7778
7779         return ret;
7780 }
7781
7782 /* Enable l2 tunnel tag insertion */
7783 static int
7784 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7785                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7786 {
7787         int ret = 0;
7788
7789         switch (l2_tunnel->l2_tunnel_type) {
7790         case RTE_L2_TUNNEL_TYPE_E_TAG:
7791                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7792                 break;
7793         default:
7794                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7795                 ret = -EINVAL;
7796                 break;
7797         }
7798
7799         return ret;
7800 }
7801
7802 /* Disable l2 tunnel tag insertion */
7803 static int
7804 ixgbe_dev_l2_tunnel_insertion_disable
7805         (struct rte_eth_dev *dev,
7806          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7807 {
7808         int ret = 0;
7809
7810         switch (l2_tunnel->l2_tunnel_type) {
7811         case RTE_L2_TUNNEL_TYPE_E_TAG:
7812                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7813                 break;
7814         default:
7815                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7816                 ret = -EINVAL;
7817                 break;
7818         }
7819
7820         return ret;
7821 }
7822
7823 static int
7824 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7825                              bool en)
7826 {
7827         int ret = 0;
7828         uint32_t qde;
7829         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7830
7831         if (hw->mac.type != ixgbe_mac_X550 &&
7832             hw->mac.type != ixgbe_mac_X550EM_x &&
7833             hw->mac.type != ixgbe_mac_X550EM_a) {
7834                 return -ENOTSUP;
7835         }
7836
7837         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7838         if (en)
7839                 qde |= IXGBE_QDE_STRIP_TAG;
7840         else
7841                 qde &= ~IXGBE_QDE_STRIP_TAG;
7842         qde &= ~IXGBE_QDE_READ;
7843         qde |= IXGBE_QDE_WRITE;
7844         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7845
7846         return ret;
7847 }
7848
7849 /* Enable l2 tunnel tag stripping */
7850 static int
7851 ixgbe_dev_l2_tunnel_stripping_enable
7852         (struct rte_eth_dev *dev,
7853          enum rte_eth_tunnel_type l2_tunnel_type)
7854 {
7855         int ret = 0;
7856
7857         switch (l2_tunnel_type) {
7858         case RTE_L2_TUNNEL_TYPE_E_TAG:
7859                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7860                 break;
7861         default:
7862                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7863                 ret = -EINVAL;
7864                 break;
7865         }
7866
7867         return ret;
7868 }
7869
7870 /* Disable l2 tunnel tag stripping */
7871 static int
7872 ixgbe_dev_l2_tunnel_stripping_disable
7873         (struct rte_eth_dev *dev,
7874          enum rte_eth_tunnel_type l2_tunnel_type)
7875 {
7876         int ret = 0;
7877
7878         switch (l2_tunnel_type) {
7879         case RTE_L2_TUNNEL_TYPE_E_TAG:
7880                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7881                 break;
7882         default:
7883                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7884                 ret = -EINVAL;
7885                 break;
7886         }
7887
7888         return ret;
7889 }
7890
7891 /* Enable/disable l2 tunnel offload functions */
7892 static int
7893 ixgbe_dev_l2_tunnel_offload_set
7894         (struct rte_eth_dev *dev,
7895          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7896          uint32_t mask,
7897          uint8_t en)
7898 {
7899         int ret = 0;
7900
7901         if (l2_tunnel == NULL)
7902                 return -EINVAL;
7903
7904         ret = -EINVAL;
7905         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7906                 if (en)
7907                         ret = ixgbe_dev_l2_tunnel_enable(
7908                                 dev,
7909                                 l2_tunnel->l2_tunnel_type);
7910                 else
7911                         ret = ixgbe_dev_l2_tunnel_disable(
7912                                 dev,
7913                                 l2_tunnel->l2_tunnel_type);
7914         }
7915
7916         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7917                 if (en)
7918                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7919                                 dev,
7920                                 l2_tunnel);
7921                 else
7922                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7923                                 dev,
7924                                 l2_tunnel);
7925         }
7926
7927         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7928                 if (en)
7929                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7930                                 dev,
7931                                 l2_tunnel->l2_tunnel_type);
7932                 else
7933                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7934                                 dev,
7935                                 l2_tunnel->l2_tunnel_type);
7936         }
7937
7938         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7939                 if (en)
7940                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7941                                 dev,
7942                                 l2_tunnel->l2_tunnel_type);
7943                 else
7944                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7945                                 dev,
7946                                 l2_tunnel->l2_tunnel_type);
7947         }
7948
7949         return ret;
7950 }
7951
7952 static int
7953 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7954                         uint16_t port)
7955 {
7956         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7957         IXGBE_WRITE_FLUSH(hw);
7958
7959         return 0;
7960 }
7961
7962 /* There's only one register for VxLAN UDP port.
7963  * So, we cannot add several ports. Will update it.
7964  */
7965 static int
7966 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7967                      uint16_t port)
7968 {
7969         if (port == 0) {
7970                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7971                 return -EINVAL;
7972         }
7973
7974         return ixgbe_update_vxlan_port(hw, port);
7975 }
7976
7977 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7978  * UDP port, it must have a value.
7979  * So, will reset it to the original value 0.
7980  */
7981 static int
7982 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7983                      uint16_t port)
7984 {
7985         uint16_t cur_port;
7986
7987         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7988
7989         if (cur_port != port) {
7990                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7991                 return -EINVAL;
7992         }
7993
7994         return ixgbe_update_vxlan_port(hw, 0);
7995 }
7996
7997 /* Add UDP tunneling port */
7998 static int
7999 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8000                               struct rte_eth_udp_tunnel *udp_tunnel)
8001 {
8002         int ret = 0;
8003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8004
8005         if (hw->mac.type != ixgbe_mac_X550 &&
8006             hw->mac.type != ixgbe_mac_X550EM_x &&
8007             hw->mac.type != ixgbe_mac_X550EM_a) {
8008                 return -ENOTSUP;
8009         }
8010
8011         if (udp_tunnel == NULL)
8012                 return -EINVAL;
8013
8014         switch (udp_tunnel->prot_type) {
8015         case RTE_TUNNEL_TYPE_VXLAN:
8016                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8017                 break;
8018
8019         case RTE_TUNNEL_TYPE_GENEVE:
8020         case RTE_TUNNEL_TYPE_TEREDO:
8021                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8022                 ret = -EINVAL;
8023                 break;
8024
8025         default:
8026                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8027                 ret = -EINVAL;
8028                 break;
8029         }
8030
8031         return ret;
8032 }
8033
8034 /* Remove UDP tunneling port */
8035 static int
8036 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8037                               struct rte_eth_udp_tunnel *udp_tunnel)
8038 {
8039         int ret = 0;
8040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8041
8042         if (hw->mac.type != ixgbe_mac_X550 &&
8043             hw->mac.type != ixgbe_mac_X550EM_x &&
8044             hw->mac.type != ixgbe_mac_X550EM_a) {
8045                 return -ENOTSUP;
8046         }
8047
8048         if (udp_tunnel == NULL)
8049                 return -EINVAL;
8050
8051         switch (udp_tunnel->prot_type) {
8052         case RTE_TUNNEL_TYPE_VXLAN:
8053                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8054                 break;
8055         case RTE_TUNNEL_TYPE_GENEVE:
8056         case RTE_TUNNEL_TYPE_TEREDO:
8057                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8058                 ret = -EINVAL;
8059                 break;
8060         default:
8061                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8062                 ret = -EINVAL;
8063                 break;
8064         }
8065
8066         return ret;
8067 }
8068
8069 static void
8070 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8071 {
8072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8073
8074         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8075 }
8076
8077 static void
8078 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8079 {
8080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8081
8082         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8083 }
8084
8085 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8086 {
8087         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8088         u32 in_msg = 0;
8089
8090         /* peek the message first */
8091         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8092
8093         /* PF reset VF event */
8094         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8095                 /* dummy mbx read to ack pf */
8096                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8097                         return;
8098                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8099                                               NULL);
8100         }
8101 }
8102
8103 static int
8104 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8105 {
8106         uint32_t eicr;
8107         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8108         struct ixgbe_interrupt *intr =
8109                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8110         ixgbevf_intr_disable(hw);
8111
8112         /* read-on-clear nic registers here */
8113         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8114         intr->flags = 0;
8115
8116         /* only one misc vector supported - mailbox */
8117         eicr &= IXGBE_VTEICR_MASK;
8118         if (eicr == IXGBE_MISC_VEC_ID)
8119                 intr->flags |= IXGBE_FLAG_MAILBOX;
8120
8121         return 0;
8122 }
8123
8124 static int
8125 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8126 {
8127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8128         struct ixgbe_interrupt *intr =
8129                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8130
8131         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8132                 ixgbevf_mbx_process(dev);
8133                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8134         }
8135
8136         ixgbevf_intr_enable(hw);
8137
8138         return 0;
8139 }
8140
8141 static void
8142 ixgbevf_dev_interrupt_handler(void *param)
8143 {
8144         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8145
8146         ixgbevf_dev_interrupt_get_status(dev);
8147         ixgbevf_dev_interrupt_action(dev);
8148 }
8149
8150 /**
8151  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8152  *  @hw: pointer to hardware structure
8153  *
8154  *  Stops the transmit data path and waits for the HW to internally empty
8155  *  the Tx security block
8156  **/
8157 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8158 {
8159 #define IXGBE_MAX_SECTX_POLL 40
8160
8161         int i;
8162         int sectxreg;
8163
8164         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8165         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8166         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8167         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8168                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8169                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8170                         break;
8171                 /* Use interrupt-safe sleep just in case */
8172                 usec_delay(1000);
8173         }
8174
8175         /* For informational purposes only */
8176         if (i >= IXGBE_MAX_SECTX_POLL)
8177                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8178                          "path fully disabled.  Continuing with init.");
8179
8180         return IXGBE_SUCCESS;
8181 }
8182
8183 /**
8184  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8185  *  @hw: pointer to hardware structure
8186  *
8187  *  Enables the transmit data path.
8188  **/
8189 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8190 {
8191         uint32_t sectxreg;
8192
8193         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8194         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8195         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8196         IXGBE_WRITE_FLUSH(hw);
8197
8198         return IXGBE_SUCCESS;
8199 }
8200
8201 /* restore n-tuple filter */
8202 static inline void
8203 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8204 {
8205         struct ixgbe_filter_info *filter_info =
8206                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8207         struct ixgbe_5tuple_filter *node;
8208
8209         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8210                 ixgbe_inject_5tuple_filter(dev, node);
8211         }
8212 }
8213
8214 /* restore ethernet type filter */
8215 static inline void
8216 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8217 {
8218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8219         struct ixgbe_filter_info *filter_info =
8220                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8221         int i;
8222
8223         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8224                 if (filter_info->ethertype_mask & (1 << i)) {
8225                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8226                                         filter_info->ethertype_filters[i].etqf);
8227                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8228                                         filter_info->ethertype_filters[i].etqs);
8229                         IXGBE_WRITE_FLUSH(hw);
8230                 }
8231         }
8232 }
8233
8234 /* restore SYN filter */
8235 static inline void
8236 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8237 {
8238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8239         struct ixgbe_filter_info *filter_info =
8240                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8241         uint32_t synqf;
8242
8243         synqf = filter_info->syn_info;
8244
8245         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8246                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8247                 IXGBE_WRITE_FLUSH(hw);
8248         }
8249 }
8250
8251 /* restore L2 tunnel filter */
8252 static inline void
8253 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8254 {
8255         struct ixgbe_l2_tn_info *l2_tn_info =
8256                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8257         struct ixgbe_l2_tn_filter *node;
8258         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8259
8260         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8261                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8262                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8263                 l2_tn_conf.pool           = node->pool;
8264                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8265         }
8266 }
8267
8268 /* restore rss filter */
8269 static inline void
8270 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8271 {
8272         struct ixgbe_filter_info *filter_info =
8273                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8274
8275         if (filter_info->rss_info.num)
8276                 ixgbe_config_rss_filter(dev,
8277                         &filter_info->rss_info, TRUE);
8278 }
8279
8280 static int
8281 ixgbe_filter_restore(struct rte_eth_dev *dev)
8282 {
8283         ixgbe_ntuple_filter_restore(dev);
8284         ixgbe_ethertype_filter_restore(dev);
8285         ixgbe_syn_filter_restore(dev);
8286         ixgbe_fdir_filter_restore(dev);
8287         ixgbe_l2_tn_filter_restore(dev);
8288         ixgbe_rss_filter_restore(dev);
8289
8290         return 0;
8291 }
8292
8293 static void
8294 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8295 {
8296         struct ixgbe_l2_tn_info *l2_tn_info =
8297                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8299
8300         if (l2_tn_info->e_tag_en)
8301                 (void)ixgbe_e_tag_enable(hw);
8302
8303         if (l2_tn_info->e_tag_fwd_en)
8304                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8305
8306         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8307 }
8308
8309 /* remove all the n-tuple filters */
8310 void
8311 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8312 {
8313         struct ixgbe_filter_info *filter_info =
8314                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8315         struct ixgbe_5tuple_filter *p_5tuple;
8316
8317         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8318                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8319 }
8320
8321 /* remove all the ether type filters */
8322 void
8323 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8324 {
8325         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8326         struct ixgbe_filter_info *filter_info =
8327                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8328         int i;
8329
8330         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8331                 if (filter_info->ethertype_mask & (1 << i) &&
8332                     !filter_info->ethertype_filters[i].conf) {
8333                         (void)ixgbe_ethertype_filter_remove(filter_info,
8334                                                             (uint8_t)i);
8335                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8336                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8337                         IXGBE_WRITE_FLUSH(hw);
8338                 }
8339         }
8340 }
8341
8342 /* remove the SYN filter */
8343 void
8344 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8345 {
8346         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8347         struct ixgbe_filter_info *filter_info =
8348                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8349
8350         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8351                 filter_info->syn_info = 0;
8352
8353                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8354                 IXGBE_WRITE_FLUSH(hw);
8355         }
8356 }
8357
8358 /* remove all the L2 tunnel filters */
8359 int
8360 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8361 {
8362         struct ixgbe_l2_tn_info *l2_tn_info =
8363                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8364         struct ixgbe_l2_tn_filter *l2_tn_filter;
8365         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8366         int ret = 0;
8367
8368         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8369                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8370                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8371                 l2_tn_conf.pool           = l2_tn_filter->pool;
8372                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8373                 if (ret < 0)
8374                         return ret;
8375         }
8376
8377         return 0;
8378 }
8379
8380 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8381 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8382 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8383 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8384 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8385 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8386
8387 RTE_INIT(ixgbe_init_log);
8388 static void
8389 ixgbe_init_log(void)
8390 {
8391         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8392         if (ixgbe_logtype_init >= 0)
8393                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8394         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8395         if (ixgbe_logtype_driver >= 0)
8396                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8397 }