drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define IXGBE_TIMINCA_16NS_SHIFT 24
 130 #define IXGBE_TIMINCA_INCVALUE   16000000
 131 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 132                                   | IXGBE_TIMINCA_INCVALUE)
 133
 134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 147                                 int wait_to_complete);
 148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 149                                 struct rte_eth_stats *stats);
 150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_xstats *xstats, unsigned n);
 152 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 153 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 155                                              uint16_t queue_id,
 156                                              uint8_t stat_idx,
 157                                              uint8_t is_rx);
 158 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 159                                struct rte_eth_dev_info *dev_info);
 160 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 161                                  struct rte_eth_dev_info *dev_info);
 162 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 163
 164 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 165                 uint16_t vlan_id, int on);
 166 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 167 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 168                 uint16_t queue, bool on);
 169 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 170                 int on);
 171 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 172 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 173 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 174 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 176
 177 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 179 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 180                                struct rte_eth_fc_conf *fc_conf);
 181 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 182                                struct rte_eth_fc_conf *fc_conf);
 183 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 184                 struct rte_eth_pfc_conf *pfc_conf);
 185 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 186                         struct rte_eth_rss_reta_entry64 *reta_conf,
 187                         uint16_t reta_size);
 188 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 189                         struct rte_eth_rss_reta_entry64 *reta_conf,
 190                         uint16_t reta_size);
 191 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 192 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 193 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 195 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 196 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 197                 void *param);
 198 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 199 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 200                 uint32_t index, uint32_t pool);
 201 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 202 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 203                                            struct ether_addr *mac_addr);
 204 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 205
 206 /* For Virtual Function support */
 207 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 208 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 209 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
 210 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
 211 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 212 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 213 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 214 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 215 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 216 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 217 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 218                 struct rte_eth_stats *stats);
 219 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 220 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 221                 uint16_t vlan_id, int on);
 222 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 223                 uint16_t queue, int on);
 224 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 225 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 226 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 227                                           void *param);
 228 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 229                                             uint16_t queue_id);
 230 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 231                                              uint16_t queue_id);
 232 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 233                                  uint8_t queue, uint8_t msix_vector);
 234 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 235
 236 /* For Eth VMDQ APIs support */
 237 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 238                 ether_addr* mac_addr,uint8_t on);
 239 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 240 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 241                 uint16_t rx_mask, uint8_t on);
 242 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 243 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 244 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 245                 uint64_t pool_mask,uint8_t vlan_on);
 246 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 247                 struct rte_eth_mirror_conf *mirror_conf,
 248                 uint8_t rule_id, uint8_t on);
 249 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 250                 uint8_t rule_id);
 251 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 252                                           uint16_t queue_id);
 253 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 254                                            uint16_t queue_id);
 255 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 256                                uint8_t queue, uint8_t msix_vector);
 257 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 258
 259 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 260                 uint16_t queue_idx, uint16_t tx_rate);
 261 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 262                 uint16_t tx_rate, uint64_t q_msk);
 263
 264 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 265                                  struct ether_addr *mac_addr,
 266                                  uint32_t index, uint32_t pool);
 267 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 268 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 269                                              struct ether_addr *mac_addr);
 270 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 271                         struct rte_eth_syn_filter *filter,
 272                         bool add);
 273 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 274                         struct rte_eth_syn_filter *filter);
 275 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 276                         enum rte_filter_op filter_op,
 277                         void *arg);
 278 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 279                         struct ixgbe_5tuple_filter *filter);
 280 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 281                         struct ixgbe_5tuple_filter *filter);
 282 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 283                         struct rte_eth_ntuple_filter *filter,
 284                         bool add);
 285 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 286                                 enum rte_filter_op filter_op,
 287                                 void *arg);
 288 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 289                         struct rte_eth_ntuple_filter *filter);
 290 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 291                         struct rte_eth_ethertype_filter *filter,
 292                         bool add);
 293 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 294                                 enum rte_filter_op filter_op,
 295                                 void *arg);
 296 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 297                         struct rte_eth_ethertype_filter *filter);
 298 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 299                      enum rte_filter_type filter_type,
 300                      enum rte_filter_op filter_op,
 301                      void *arg);
 302 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 303
 304 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 305                                       struct ether_addr *mc_addr_set,
 306                                       uint32_t nb_mc_addr);
 307
 308 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 309 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 310                             struct rte_dev_reg_info *regs);
 311 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 312 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 313                                 struct rte_dev_eeprom_info *eeprom);
 314 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 315                                 struct rte_dev_eeprom_info *eeprom);
 316
 317 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 318 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 319                                 struct rte_dev_reg_info *regs);
 320
 321 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 322 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 323 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 324                                             struct timespec *timestamp,
 325                                             uint32_t flags);
 326 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 327                                             struct timespec *timestamp);
 328
 329 /*
 330  * Define VF Stats MACRO for Non "cleared on read" register
 331  */
 332 #define UPDATE_VF_STAT(reg, last, cur)                          \
 333 {                                                               \
 334         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 335         cur += (latest - last) & UINT_MAX;                      \
 336         last = latest;                                          \
 337 }
 338
 339 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 340 {                                                                \
 341         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 342         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 343         u64 latest = ((new_msb << 32) | new_lsb);                \
 344         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 345         last = latest;                                           \
 346 }
 347
 348 #define IXGBE_SET_HWSTRIP(h, q) do{\
 349                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 350                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 351                 (h)->bitmap[idx] |= 1 << bit;\
 352         }while(0)
 353
 354 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 355                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 356                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 357                 (h)->bitmap[idx] &= ~(1 << bit);\
 358         }while(0)
 359
 360 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 361                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 362                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 363                 (r) = (h)->bitmap[idx] >> bit & 1;\
 364         }while(0)
 365
 366 /*
 367  * The set of PCI devices this driver supports
 368  */
 369 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 370
 371 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 372 #include "rte_pci_dev_ids.h"
 373
 374 { .vendor_id = 0, /* sentinel */ },
 375 };
 376
 377
 378 /*
 379  * The set of PCI devices this driver supports (for 82599 VF)
 380  */
 381 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 382
 383 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 384 #include "rte_pci_dev_ids.h"
 385 { .vendor_id = 0, /* sentinel */ },
 386
 387 };
 388
 389 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 390         .dev_configure        = ixgbe_dev_configure,
 391         .dev_start            = ixgbe_dev_start,
 392         .dev_stop             = ixgbe_dev_stop,
 393         .dev_set_link_up    = ixgbe_dev_set_link_up,
 394         .dev_set_link_down  = ixgbe_dev_set_link_down,
 395         .dev_close            = ixgbe_dev_close,
 396         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 397         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 398         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 399         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 400         .link_update          = ixgbe_dev_link_update,
 401         .stats_get            = ixgbe_dev_stats_get,
 402         .xstats_get           = ixgbe_dev_xstats_get,
 403         .stats_reset          = ixgbe_dev_stats_reset,
 404         .xstats_reset         = ixgbe_dev_xstats_reset,
 405         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 406         .dev_infos_get        = ixgbe_dev_info_get,
 407         .mtu_set              = ixgbe_dev_mtu_set,
 408         .vlan_filter_set      = ixgbe_vlan_filter_set,
 409         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 410         .vlan_offload_set     = ixgbe_vlan_offload_set,
 411         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 412         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 413         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 414         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 415         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 416         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 417         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 418         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 419         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 420         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 421         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 422         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 423         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 424         .dev_led_on           = ixgbe_dev_led_on,
 425         .dev_led_off          = ixgbe_dev_led_off,
 426         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 427         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 428         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 429         .mac_addr_add         = ixgbe_add_rar,
 430         .mac_addr_remove      = ixgbe_remove_rar,
 431         .mac_addr_set         = ixgbe_set_default_mac_addr,
 432         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 433         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 434         .mirror_rule_set      = ixgbe_mirror_rule_set,
 435         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 436         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 437         .set_vf_rx            = ixgbe_set_pool_rx,
 438         .set_vf_tx            = ixgbe_set_pool_tx,
 439         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 440         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 441         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 442         .reta_update          = ixgbe_dev_rss_reta_update,
 443         .reta_query           = ixgbe_dev_rss_reta_query,
 444 #ifdef RTE_NIC_BYPASS
 445         .bypass_init          = ixgbe_bypass_init,
 446         .bypass_state_set     = ixgbe_bypass_state_store,
 447         .bypass_state_show    = ixgbe_bypass_state_show,
 448         .bypass_event_set     = ixgbe_bypass_event_store,
 449         .bypass_event_show    = ixgbe_bypass_event_show,
 450         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 451         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 452         .bypass_ver_show      = ixgbe_bypass_ver_show,
 453         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 454 #endif /* RTE_NIC_BYPASS */
 455         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 456         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 457         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 458         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 459         .timesync_enable      = ixgbe_timesync_enable,
 460         .timesync_disable     = ixgbe_timesync_disable,
 461         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 462         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 463         .get_reg_length       = ixgbe_get_reg_length,
 464         .get_reg              = ixgbe_get_regs,
 465         .get_eeprom_length    = ixgbe_get_eeprom_length,
 466         .get_eeprom           = ixgbe_get_eeprom,
 467         .set_eeprom           = ixgbe_set_eeprom,
 468 };
 469
 470 /*
 471  * dev_ops for virtual function, bare necessities for basic vf
 472  * operation have been implemented
 473  */
 474 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 475         .dev_configure        = ixgbevf_dev_configure,
 476         .dev_start            = ixgbevf_dev_start,
 477         .dev_stop             = ixgbevf_dev_stop,
 478         .link_update          = ixgbe_dev_link_update,
 479         .stats_get            = ixgbevf_dev_stats_get,
 480         .stats_reset          = ixgbevf_dev_stats_reset,
 481         .dev_close            = ixgbevf_dev_close,
 482         .dev_infos_get        = ixgbevf_dev_info_get,
 483         .mtu_set              = ixgbevf_dev_set_mtu,
 484         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 485         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 486         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 487         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 488         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 489         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 490         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 491         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 492         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 493         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 494         .mac_addr_add         = ixgbevf_add_mac_addr,
 495         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 496         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 497         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 498         .get_reg_length       = ixgbevf_get_reg_length,
 499         .get_reg              = ixgbevf_get_regs,
 500         .reta_update          = ixgbe_dev_rss_reta_update,
 501         .reta_query           = ixgbe_dev_rss_reta_query,
 502         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 503         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 504 };
 505
 506 /* store statistics names and its offset in stats structure */
 507 struct rte_ixgbe_xstats_name_off {
 508         char name[RTE_ETH_XSTATS_NAME_SIZE];
 509         unsigned offset;
 510 };
 511
 512 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 513         {"rx_illegal_byte_err", offsetof(struct ixgbe_hw_stats, errbc)},
 514         {"rx_len_err", offsetof(struct ixgbe_hw_stats, rlec)},
 515         {"rx_undersize_count", offsetof(struct ixgbe_hw_stats, ruc)},
 516         {"rx_oversize_count", offsetof(struct ixgbe_hw_stats, roc)},
 517         {"rx_fragment_count", offsetof(struct ixgbe_hw_stats, rfc)},
 518         {"rx_jabber_count", offsetof(struct ixgbe_hw_stats, rjc)},
 519         {"l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 520         {"mac_local_fault", offsetof(struct ixgbe_hw_stats, mlfc)},
 521         {"mac_remote_fault", offsetof(struct ixgbe_hw_stats, mrfc)},
 522         {"mac_short_pkt_discard", offsetof(struct ixgbe_hw_stats, mspdc)},
 523         {"fccrc_error", offsetof(struct ixgbe_hw_stats, fccrc)},
 524         {"fcoe_drop", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 525         {"fc_last_error", offsetof(struct ixgbe_hw_stats, fclast)},
 526         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 527         {"rx_phy_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 528         {"mgmt_pkts_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 529         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 530         {"fdir_match", offsetof(struct ixgbe_hw_stats, fdirmatch)},
 531         {"fdir_miss", offsetof(struct ixgbe_hw_stats, fdirmiss)},
 532         {"tx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxontxc)},
 533         {"rx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 534         {"tx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 535         {"rx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 536 };
 537
 538 #define IXGBE_NB_XSTATS (sizeof(rte_ixgbe_stats_strings) /      \
 539                 sizeof(rte_ixgbe_stats_strings[0]))
 540
 541 /**
 542  * Atomically reads the link status information from global
 543  * structure rte_eth_dev.
 544  *
 545  * @param dev
 546  *   - Pointer to the structure rte_eth_dev to read from.
 547  *   - Pointer to the buffer to be saved with the link status.
 548  *
 549  * @return
 550  *   - On success, zero.
 551  *   - On failure, negative value.
 552  */
 553 static inline int
 554 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 555                                 struct rte_eth_link *link)
 556 {
 557         struct rte_eth_link *dst = link;
 558         struct rte_eth_link *src = &(dev->data->dev_link);
 559
 560         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 561                                         *(uint64_t *)src) == 0)
 562                 return -1;
 563
 564         return 0;
 565 }
 566
 567 /**
 568  * Atomically writes the link status information into global
 569  * structure rte_eth_dev.
 570  *
 571  * @param dev
 572  *   - Pointer to the structure rte_eth_dev to read from.
 573  *   - Pointer to the buffer to be saved with the link status.
 574  *
 575  * @return
 576  *   - On success, zero.
 577  *   - On failure, negative value.
 578  */
 579 static inline int
 580 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 581                                 struct rte_eth_link *link)
 582 {
 583         struct rte_eth_link *dst = &(dev->data->dev_link);
 584         struct rte_eth_link *src = link;
 585
 586         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 587                                         *(uint64_t *)src) == 0)
 588                 return -1;
 589
 590         return 0;
 591 }
 592
 593 /*
 594  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 595  */
 596 static inline int
 597 ixgbe_is_sfp(struct ixgbe_hw *hw)
 598 {
 599         switch (hw->phy.type) {
 600         case ixgbe_phy_sfp_avago:
 601         case ixgbe_phy_sfp_ftl:
 602         case ixgbe_phy_sfp_intel:
 603         case ixgbe_phy_sfp_unknown:
 604         case ixgbe_phy_sfp_passive_tyco:
 605         case ixgbe_phy_sfp_passive_unknown:
 606                 return 1;
 607         default:
 608                 return 0;
 609         }
 610 }
 611
 612 static inline int32_t
 613 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 614 {
 615         uint32_t ctrl_ext;
 616         int32_t status;
 617
 618         status = ixgbe_reset_hw(hw);
 619
 620         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 621         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 622         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 623         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 624         IXGBE_WRITE_FLUSH(hw);
 625
 626         return status;
 627 }
 628
 629 static inline void
 630 ixgbe_enable_intr(struct rte_eth_dev *dev)
 631 {
 632         struct ixgbe_interrupt *intr =
 633                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 634         struct ixgbe_hw *hw =
 635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 636
 637         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 638         IXGBE_WRITE_FLUSH(hw);
 639 }
 640
 641 /*
 642  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 643  */
 644 static void
 645 ixgbe_disable_intr(struct ixgbe_hw *hw)
 646 {
 647         PMD_INIT_FUNC_TRACE();
 648
 649         if (hw->mac.type == ixgbe_mac_82598EB) {
 650                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 651         } else {
 652                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 653                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 654                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 655         }
 656         IXGBE_WRITE_FLUSH(hw);
 657 }
 658
 659 /*
 660  * This function resets queue statistics mapping registers.
 661  * From Niantic datasheet, Initialization of Statistics section:
 662  * "...if software requires the queue counters, the RQSMR and TQSM registers
 663  * must be re-programmed following a device reset.
 664  */
 665 static void
 666 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 667 {
 668         uint32_t i;
 669
 670         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 671                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 672                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 673         }
 674 }
 675
 676
 677 static int
 678 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 679                                   uint16_t queue_id,
 680                                   uint8_t stat_idx,
 681                                   uint8_t is_rx)
 682 {
 683 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 684 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 685 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 686
 687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 688         struct ixgbe_stat_mapping_registers *stat_mappings =
 689                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 690         uint32_t qsmr_mask = 0;
 691         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 692         uint32_t q_map;
 693         uint8_t n, offset;
 694
 695         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 696                 (hw->mac.type != ixgbe_mac_X540) &&
 697                 (hw->mac.type != ixgbe_mac_X550) &&
 698                 (hw->mac.type != ixgbe_mac_X550EM_x))
 699                 return -ENOSYS;
 700
 701         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 702                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 703                      queue_id, stat_idx);
 704
 705         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 706         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 707                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 708                 return -EIO;
 709         }
 710         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 711
 712         /* Now clear any previous stat_idx set */
 713         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 714         if (!is_rx)
 715                 stat_mappings->tqsm[n] &= ~clearing_mask;
 716         else
 717                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 718
 719         q_map = (uint32_t)stat_idx;
 720         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 721         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 722         if (!is_rx)
 723                 stat_mappings->tqsm[n] |= qsmr_mask;
 724         else
 725                 stat_mappings->rqsmr[n] |= qsmr_mask;
 726
 727         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 728                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 729                      queue_id, stat_idx);
 730         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 731                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 732
 733         /* Now write the mapping in the appropriate register */
 734         if (is_rx) {
 735                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 736                              stat_mappings->rqsmr[n], n);
 737                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 738         }
 739         else {
 740                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 741                              stat_mappings->tqsm[n], n);
 742                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 743         }
 744         return 0;
 745 }
 746
 747 static void
 748 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 749 {
 750         struct ixgbe_stat_mapping_registers *stat_mappings =
 751                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753         int i;
 754
 755         /* write whatever was in stat mapping table to the NIC */
 756         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 757                 /* rx */
 758                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 759
 760                 /* tx */
 761                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 762         }
 763 }
 764
 765 static void
 766 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 767 {
 768         uint8_t i;
 769         struct ixgbe_dcb_tc_config *tc;
 770         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 771
 772         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 773         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 774         for (i = 0; i < dcb_max_tc; i++) {
 775                 tc = &dcb_config->tc_config[i];
 776                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 777                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 778                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 779                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 780                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 781                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 782                 tc->pfc = ixgbe_dcb_pfc_disabled;
 783         }
 784
 785         /* Initialize default user to priority mapping, UPx->TC0 */
 786         tc = &dcb_config->tc_config[0];
 787         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 788         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 789         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 790                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 791                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 792         }
 793         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 794         dcb_config->pfc_mode_enable = false;
 795         dcb_config->vt_mode = true;
 796         dcb_config->round_robin_enable = false;
 797         /* support all DCB capabilities in 82599 */
 798         dcb_config->support.capabilities = 0xFF;
 799
 800         /*we only support 4 Tcs for X540, X550 */
 801         if (hw->mac.type == ixgbe_mac_X540 ||
 802                 hw->mac.type == ixgbe_mac_X550 ||
 803                 hw->mac.type == ixgbe_mac_X550EM_x) {
 804                 dcb_config->num_tcs.pg_tcs = 4;
 805                 dcb_config->num_tcs.pfc_tcs = 4;
 806         }
 807 }
 808
 809 /*
 810  * Ensure that all locks are released before first NVM or PHY access
 811  */
 812 static void
 813 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 814 {
 815         uint16_t mask;
 816
 817         /*
 818          * Phy lock should not fail in this early stage. If this is the case,
 819          * it is due to an improper exit of the application.
 820          * So force the release of the faulty lock. Release of common lock
 821          * is done automatically by swfw_sync function.
 822          */
 823         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 824         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 825                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 826         }
 827         ixgbe_release_swfw_semaphore(hw, mask);
 828
 829         /*
 830          * These ones are more tricky since they are common to all ports; but
 831          * swfw_sync retries last long enough (1s) to be almost sure that if
 832          * lock can not be taken it is due to an improper lock of the
 833          * semaphore.
 834          */
 835         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 836         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 837                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 838         }
 839         ixgbe_release_swfw_semaphore(hw, mask);
 840 }
 841
 842 /*
 843  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 844  * It returns 0 on success.
 845  */
 846 static int
 847 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 848 {
 849         struct rte_pci_device *pci_dev;
 850         struct ixgbe_hw *hw =
 851                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 852         struct ixgbe_vfta * shadow_vfta =
 853                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 854         struct ixgbe_hwstrip *hwstrip =
 855                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 856         struct ixgbe_dcb_config *dcb_config =
 857                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 858         struct ixgbe_filter_info *filter_info =
 859                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 860         uint32_t ctrl_ext;
 861         uint16_t csum;
 862         int diag, i;
 863
 864         PMD_INIT_FUNC_TRACE();
 865
 866         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 867         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 868         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 869
 870         /*
 871          * For secondary processes, we don't initialise any further as primary
 872          * has already done this work. Only check we don't need a different
 873          * RX and TX function.
 874          */
 875         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 876                 struct ixgbe_tx_queue *txq;
 877                 /* TX queue function in primary, set by last queue initialized
 878                  * Tx queue may not initialized by primary process */
 879                 if (eth_dev->data->tx_queues) {
 880                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 881                         ixgbe_set_tx_function(eth_dev, txq);
 882                 } else {
 883                         /* Use default TX function if we get here */
 884                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 885                                              "Using default TX function.");
 886                 }
 887
 888                 ixgbe_set_rx_function(eth_dev);
 889
 890                 return 0;
 891         }
 892         pci_dev = eth_dev->pci_dev;
 893
 894         /* Vendor and Device ID need to be set before init of shared code */
 895         hw->device_id = pci_dev->id.device_id;
 896         hw->vendor_id = pci_dev->id.vendor_id;
 897         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 898         hw->allow_unsupported_sfp = 1;
 899
 900         /* Initialize the shared code (base driver) */
 901 #ifdef RTE_NIC_BYPASS
 902         diag = ixgbe_bypass_init_shared_code(hw);
 903 #else
 904         diag = ixgbe_init_shared_code(hw);
 905 #endif /* RTE_NIC_BYPASS */
 906
 907         if (diag != IXGBE_SUCCESS) {
 908                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 909                 return -EIO;
 910         }
 911
 912         /* pick up the PCI bus settings for reporting later */
 913         ixgbe_get_bus_info(hw);
 914
 915         /* Unlock any pending hardware semaphore */
 916         ixgbe_swfw_lock_reset(hw);
 917
 918         /* Initialize DCB configuration*/
 919         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 920         ixgbe_dcb_init(hw,dcb_config);
 921         /* Get Hardware Flow Control setting */
 922         hw->fc.requested_mode = ixgbe_fc_full;
 923         hw->fc.current_mode = ixgbe_fc_full;
 924         hw->fc.pause_time = IXGBE_FC_PAUSE;
 925         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 926                 hw->fc.low_water[i] = IXGBE_FC_LO;
 927                 hw->fc.high_water[i] = IXGBE_FC_HI;
 928         }
 929         hw->fc.send_xon = 1;
 930
 931         /* Make sure we have a good EEPROM before we read from it */
 932         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 933         if (diag != IXGBE_SUCCESS) {
 934                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 935                 return -EIO;
 936         }
 937
 938 #ifdef RTE_NIC_BYPASS
 939         diag = ixgbe_bypass_init_hw(hw);
 940 #else
 941         diag = ixgbe_init_hw(hw);
 942 #endif /* RTE_NIC_BYPASS */
 943
 944         /*
 945          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 946          * is called too soon after the kernel driver unbinding/binding occurs.
 947          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 948          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 949          * also called. See ixgbe_identify_phy_82599(). The reason for the
 950          * failure is not known, and only occuts when virtualisation features
 951          * are disabled in the bios. A delay of 100ms  was found to be enough by
 952          * trial-and-error, and is doubled to be safe.
 953          */
 954         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 955                 rte_delay_ms(200);
 956                 diag = ixgbe_init_hw(hw);
 957         }
 958
 959         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 960                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 961                     "LOM.  Please be aware there may be issues associated "
 962                     "with your hardware.");
 963                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 964                     "please contact your Intel or hardware representative "
 965                     "who provided you with this hardware.");
 966         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 967                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 968         if (diag) {
 969                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 970                 return -EIO;
 971         }
 972
 973         /* Reset the hw statistics */
 974         ixgbe_dev_stats_reset(eth_dev);
 975
 976         /* disable interrupt */
 977         ixgbe_disable_intr(hw);
 978
 979         /* reset mappings for queue statistics hw counters*/
 980         ixgbe_reset_qstat_mappings(hw);
 981
 982         /* Allocate memory for storing MAC addresses */
 983         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 984                         hw->mac.num_rar_entries, 0);
 985         if (eth_dev->data->mac_addrs == NULL) {
 986                 PMD_INIT_LOG(ERR,
 987                         "Failed to allocate %u bytes needed to store "
 988                         "MAC addresses",
 989                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 990                 return -ENOMEM;
 991         }
 992         /* Copy the permanent MAC address */
 993         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 994                         &eth_dev->data->mac_addrs[0]);
 995
 996         /* Allocate memory for storing hash filter MAC addresses */
 997         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 998                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 999         if (eth_dev->data->hash_mac_addrs == NULL) {
1000                 PMD_INIT_LOG(ERR,
1001                         "Failed to allocate %d bytes needed to store MAC addresses",
1002                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1003                 return -ENOMEM;
1004         }
1005
1006         /* initialize the vfta */
1007         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1008
1009         /* initialize the hw strip bitmap*/
1010         memset(hwstrip, 0, sizeof(*hwstrip));
1011
1012         /* initialize PF if max_vfs not zero */
1013         ixgbe_pf_host_init(eth_dev);
1014
1015         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1016         /* let hardware know driver is loaded */
1017         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1018         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1019         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1020         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1021         IXGBE_WRITE_FLUSH(hw);
1022
1023         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1024                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1025                              (int) hw->mac.type, (int) hw->phy.type,
1026                              (int) hw->phy.sfp_type);
1027         else
1028                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1029                              (int) hw->mac.type, (int) hw->phy.type);
1030
1031         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1032                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1033                         pci_dev->id.device_id);
1034
1035         /* enable support intr */
1036         ixgbe_enable_intr(eth_dev);
1037
1038         /* initialize 5tuple filter list */
1039         TAILQ_INIT(&filter_info->fivetuple_list);
1040         memset(filter_info->fivetuple_mask, 0,
1041                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1042
1043         return 0;
1044 }
1045
1046 static int
1047 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1048 {
1049         struct rte_pci_device *pci_dev;
1050         struct ixgbe_hw *hw;
1051
1052         PMD_INIT_FUNC_TRACE();
1053
1054         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1055                 return -EPERM;
1056
1057         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1058         pci_dev = eth_dev->pci_dev;
1059
1060         if (hw->adapter_stopped == 0)
1061                 ixgbe_dev_close(eth_dev);
1062
1063         eth_dev->dev_ops = NULL;
1064         eth_dev->rx_pkt_burst = NULL;
1065         eth_dev->tx_pkt_burst = NULL;
1066
1067         /* Unlock any pending hardware semaphore */
1068         ixgbe_swfw_lock_reset(hw);
1069
1070         /* disable uio intr before callback unregister */
1071         rte_intr_disable(&(pci_dev->intr_handle));
1072         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1073                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1074
1075         /* uninitialize PF if max_vfs not zero */
1076         ixgbe_pf_host_uninit(eth_dev);
1077
1078         rte_free(eth_dev->data->mac_addrs);
1079         eth_dev->data->mac_addrs = NULL;
1080
1081         rte_free(eth_dev->data->hash_mac_addrs);
1082         eth_dev->data->hash_mac_addrs = NULL;
1083
1084         return 0;
1085 }
1086
1087 /*
1088  * Negotiate mailbox API version with the PF.
1089  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1090  * Then we try to negotiate starting with the most recent one.
1091  * If all negotiation attempts fail, then we will proceed with
1092  * the default one (ixgbe_mbox_api_10).
1093  */
1094 static void
1095 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1096 {
1097         int32_t i;
1098
1099         /* start with highest supported, proceed down */
1100         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1101                 ixgbe_mbox_api_11,
1102                 ixgbe_mbox_api_10,
1103         };
1104
1105         for (i = 0;
1106                         i != RTE_DIM(sup_ver) &&
1107                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1108                         i++)
1109                 ;
1110 }
1111
1112 static void
1113 generate_random_mac_addr(struct ether_addr *mac_addr)
1114 {
1115         uint64_t random;
1116
1117         /* Set Organizationally Unique Identifier (OUI) prefix. */
1118         mac_addr->addr_bytes[0] = 0x00;
1119         mac_addr->addr_bytes[1] = 0x09;
1120         mac_addr->addr_bytes[2] = 0xC0;
1121         /* Force indication of locally assigned MAC address. */
1122         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1123         /* Generate the last 3 bytes of the MAC address with a random number. */
1124         random = rte_rand();
1125         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1126 }
1127
1128 /*
1129  * Virtual Function device init
1130  */
1131 static int
1132 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1133 {
1134         int diag;
1135         uint32_t tc, tcs;
1136         struct rte_pci_device *pci_dev;
1137         struct ixgbe_hw *hw =
1138                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1139         struct ixgbe_vfta * shadow_vfta =
1140                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1141         struct ixgbe_hwstrip *hwstrip =
1142                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1143         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1144
1145         PMD_INIT_FUNC_TRACE();
1146
1147         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1148         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1149         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1150
1151         /* for secondary processes, we don't initialise any further as primary
1152          * has already done this work. Only check we don't need a different
1153          * RX function */
1154         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1155                 if (eth_dev->data->scattered_rx)
1156                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1157                 return 0;
1158         }
1159
1160         pci_dev = eth_dev->pci_dev;
1161
1162         hw->device_id = pci_dev->id.device_id;
1163         hw->vendor_id = pci_dev->id.vendor_id;
1164         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1165
1166         /* initialize the vfta */
1167         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1168
1169         /* initialize the hw strip bitmap*/
1170         memset(hwstrip, 0, sizeof(*hwstrip));
1171
1172         /* Initialize the shared code (base driver) */
1173         diag = ixgbe_init_shared_code(hw);
1174         if (diag != IXGBE_SUCCESS) {
1175                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1176                 return -EIO;
1177         }
1178
1179         /* init_mailbox_params */
1180         hw->mbx.ops.init_params(hw);
1181
1182         /* Reset the hw statistics */
1183         ixgbevf_dev_stats_reset(eth_dev);
1184
1185         /* Disable the interrupts for VF */
1186         ixgbevf_intr_disable(hw);
1187
1188         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1189         diag = hw->mac.ops.reset_hw(hw);
1190
1191         /*
1192          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1193          * the underlying PF driver has not assigned a MAC address to the VF.
1194          * In this case, assign a random MAC address.
1195          */
1196         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1197                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1198                 return (diag);
1199         }
1200
1201         /* negotiate mailbox API version to use with the PF. */
1202         ixgbevf_negotiate_api(hw);
1203
1204         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1205         ixgbevf_get_queues(hw, &tcs, &tc);
1206
1207         /* Allocate memory for storing MAC addresses */
1208         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1209                         hw->mac.num_rar_entries, 0);
1210         if (eth_dev->data->mac_addrs == NULL) {
1211                 PMD_INIT_LOG(ERR,
1212                         "Failed to allocate %u bytes needed to store "
1213                         "MAC addresses",
1214                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1215                 return -ENOMEM;
1216         }
1217
1218         /* Generate a random MAC address, if none was assigned by PF. */
1219         if (is_zero_ether_addr(perm_addr)) {
1220                 generate_random_mac_addr(perm_addr);
1221                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1222                 if (diag) {
1223                         rte_free(eth_dev->data->mac_addrs);
1224                         eth_dev->data->mac_addrs = NULL;
1225                         return diag;
1226                 }
1227                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1228                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1229                              "%02x:%02x:%02x:%02x:%02x:%02x",
1230                              perm_addr->addr_bytes[0],
1231                              perm_addr->addr_bytes[1],
1232                              perm_addr->addr_bytes[2],
1233                              perm_addr->addr_bytes[3],
1234                              perm_addr->addr_bytes[4],
1235                              perm_addr->addr_bytes[5]);
1236         }
1237
1238         /* Copy the permanent MAC address */
1239         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1240
1241         /* reset the hardware with the new settings */
1242         diag = hw->mac.ops.start_hw(hw);
1243         switch (diag) {
1244                 case  0:
1245                         break;
1246
1247                 default:
1248                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1249                         return (-EIO);
1250         }
1251
1252         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1253                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1254                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1255
1256         return 0;
1257 }
1258
1259 /* Virtual Function device uninit */
1260
1261 static int
1262 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1263 {
1264         struct ixgbe_hw *hw;
1265         unsigned i;
1266
1267         PMD_INIT_FUNC_TRACE();
1268
1269         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1270                 return -EPERM;
1271
1272         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1273
1274         if (hw->adapter_stopped == 0)
1275                 ixgbevf_dev_close(eth_dev);
1276
1277         eth_dev->dev_ops = NULL;
1278         eth_dev->rx_pkt_burst = NULL;
1279         eth_dev->tx_pkt_burst = NULL;
1280
1281         /* Disable the interrupts for VF */
1282         ixgbevf_intr_disable(hw);
1283
1284         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1285                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1286                 eth_dev->data->rx_queues[i] = NULL;
1287         }
1288         eth_dev->data->nb_rx_queues = 0;
1289
1290         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1291                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1292                 eth_dev->data->tx_queues[i] = NULL;
1293         }
1294         eth_dev->data->nb_tx_queues = 0;
1295
1296         rte_free(eth_dev->data->mac_addrs);
1297         eth_dev->data->mac_addrs = NULL;
1298
1299         return 0;
1300 }
1301
1302 static struct eth_driver rte_ixgbe_pmd = {
1303         .pci_drv = {
1304                 .name = "rte_ixgbe_pmd",
1305                 .id_table = pci_id_ixgbe_map,
1306                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1307                         RTE_PCI_DRV_DETACHABLE,
1308         },
1309         .eth_dev_init = eth_ixgbe_dev_init,
1310         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1311         .dev_private_size = sizeof(struct ixgbe_adapter),
1312 };
1313
1314 /*
1315  * virtual function driver struct
1316  */
1317 static struct eth_driver rte_ixgbevf_pmd = {
1318         .pci_drv = {
1319                 .name = "rte_ixgbevf_pmd",
1320                 .id_table = pci_id_ixgbevf_map,
1321                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1322         },
1323         .eth_dev_init = eth_ixgbevf_dev_init,
1324         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1325         .dev_private_size = sizeof(struct ixgbe_adapter),
1326 };
1327
1328 /*
1329  * Driver initialization routine.
1330  * Invoked once at EAL init time.
1331  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1332  */
1333 static int
1334 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1335 {
1336         PMD_INIT_FUNC_TRACE();
1337
1338         rte_eth_driver_register(&rte_ixgbe_pmd);
1339         return 0;
1340 }
1341
1342 /*
1343  * VF Driver initialization routine.
1344  * Invoked one at EAL init time.
1345  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1346  */
1347 static int
1348 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1349 {
1350         PMD_INIT_FUNC_TRACE();
1351
1352         rte_eth_driver_register(&rte_ixgbevf_pmd);
1353         return (0);
1354 }
1355
1356 static int
1357 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1358 {
1359         struct ixgbe_hw *hw =
1360                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1361         struct ixgbe_vfta * shadow_vfta =
1362                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1363         uint32_t vfta;
1364         uint32_t vid_idx;
1365         uint32_t vid_bit;
1366
1367         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1368         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1369         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1370         if (on)
1371                 vfta |= vid_bit;
1372         else
1373                 vfta &= ~vid_bit;
1374         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1375
1376         /* update local VFTA copy */
1377         shadow_vfta->vfta[vid_idx] = vfta;
1378
1379         return 0;
1380 }
1381
1382 static void
1383 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1384 {
1385         if (on)
1386                 ixgbe_vlan_hw_strip_enable(dev, queue);
1387         else
1388                 ixgbe_vlan_hw_strip_disable(dev, queue);
1389 }
1390
1391 static void
1392 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1393 {
1394         struct ixgbe_hw *hw =
1395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396
1397         /* Only the high 16-bits is valid */
1398         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1399 }
1400
1401 void
1402 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1403 {
1404         struct ixgbe_hw *hw =
1405                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406         uint32_t vlnctrl;
1407
1408         PMD_INIT_FUNC_TRACE();
1409
1410         /* Filter Table Disable */
1411         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1412         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1413
1414         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1415 }
1416
1417 void
1418 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1419 {
1420         struct ixgbe_hw *hw =
1421                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422         struct ixgbe_vfta * shadow_vfta =
1423                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1424         uint32_t vlnctrl;
1425         uint16_t i;
1426
1427         PMD_INIT_FUNC_TRACE();
1428
1429         /* Filter Table Enable */
1430         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1431         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1432         vlnctrl |= IXGBE_VLNCTRL_VFE;
1433
1434         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1435
1436         /* write whatever is in local vfta copy */
1437         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1438                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1439 }
1440
1441 static void
1442 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1443 {
1444         struct ixgbe_hwstrip *hwstrip =
1445                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1446
1447         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1448                 return;
1449
1450         if (on)
1451                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1452         else
1453                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1454 }
1455
1456 static void
1457 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1458 {
1459         struct ixgbe_hw *hw =
1460                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461         uint32_t ctrl;
1462
1463         PMD_INIT_FUNC_TRACE();
1464
1465         if (hw->mac.type == ixgbe_mac_82598EB) {
1466                 /* No queue level support */
1467                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1468                 return;
1469         }
1470         else {
1471                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1472                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1473                 ctrl &= ~IXGBE_RXDCTL_VME;
1474                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1475         }
1476         /* record those setting for HW strip per queue */
1477         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1478 }
1479
1480 static void
1481 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1482 {
1483         struct ixgbe_hw *hw =
1484                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1485         uint32_t ctrl;
1486
1487         PMD_INIT_FUNC_TRACE();
1488
1489         if (hw->mac.type == ixgbe_mac_82598EB) {
1490                 /* No queue level supported */
1491                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1492                 return;
1493         }
1494         else {
1495                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1496                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1497                 ctrl |= IXGBE_RXDCTL_VME;
1498                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1499         }
1500         /* record those setting for HW strip per queue */
1501         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1502 }
1503
1504 void
1505 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1506 {
1507         struct ixgbe_hw *hw =
1508                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1509         uint32_t ctrl;
1510         uint16_t i;
1511
1512         PMD_INIT_FUNC_TRACE();
1513
1514         if (hw->mac.type == ixgbe_mac_82598EB) {
1515                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1516                 ctrl &= ~IXGBE_VLNCTRL_VME;
1517                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1518         }
1519         else {
1520                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1521                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1522                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1523                         ctrl &= ~IXGBE_RXDCTL_VME;
1524                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1525
1526                         /* record those setting for HW strip per queue */
1527                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1528                 }
1529         }
1530 }
1531
1532 void
1533 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1534 {
1535         struct ixgbe_hw *hw =
1536                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537         uint32_t ctrl;
1538         uint16_t i;
1539
1540         PMD_INIT_FUNC_TRACE();
1541
1542         if (hw->mac.type == ixgbe_mac_82598EB) {
1543                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1544                 ctrl |= IXGBE_VLNCTRL_VME;
1545                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1546         }
1547         else {
1548                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1549                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1550                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1551                         ctrl |= IXGBE_RXDCTL_VME;
1552                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1553
1554                         /* record those setting for HW strip per queue */
1555                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1556                 }
1557         }
1558 }
1559
1560 static void
1561 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1562 {
1563         struct ixgbe_hw *hw =
1564                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1565         uint32_t ctrl;
1566
1567         PMD_INIT_FUNC_TRACE();
1568
1569         /* DMATXCTRL: Geric Double VLAN Disable */
1570         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1571         ctrl &= ~IXGBE_DMATXCTL_GDV;
1572         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1573
1574         /* CTRL_EXT: Global Double VLAN Disable */
1575         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1576         ctrl &= ~IXGBE_EXTENDED_VLAN;
1577         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1578
1579 }
1580
1581 static void
1582 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1583 {
1584         struct ixgbe_hw *hw =
1585                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586         uint32_t ctrl;
1587
1588         PMD_INIT_FUNC_TRACE();
1589
1590         /* DMATXCTRL: Geric Double VLAN Enable */
1591         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1592         ctrl |= IXGBE_DMATXCTL_GDV;
1593         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1594
1595         /* CTRL_EXT: Global Double VLAN Enable */
1596         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1597         ctrl |= IXGBE_EXTENDED_VLAN;
1598         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1599
1600         /*
1601          * VET EXT field in the EXVET register = 0x8100 by default
1602          * So no need to change. Same to VT field of DMATXCTL register
1603          */
1604 }
1605
1606 static void
1607 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1608 {
1609         if(mask & ETH_VLAN_STRIP_MASK){
1610                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1611                         ixgbe_vlan_hw_strip_enable_all(dev);
1612                 else
1613                         ixgbe_vlan_hw_strip_disable_all(dev);
1614         }
1615
1616         if(mask & ETH_VLAN_FILTER_MASK){
1617                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1618                         ixgbe_vlan_hw_filter_enable(dev);
1619                 else
1620                         ixgbe_vlan_hw_filter_disable(dev);
1621         }
1622
1623         if(mask & ETH_VLAN_EXTEND_MASK){
1624                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1625                         ixgbe_vlan_hw_extend_enable(dev);
1626                 else
1627                         ixgbe_vlan_hw_extend_disable(dev);
1628         }
1629 }
1630
1631 static void
1632 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1633 {
1634         struct ixgbe_hw *hw =
1635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1637         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1638         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1639         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1640 }
1641
1642 static int
1643 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1644 {
1645         switch (nb_rx_q) {
1646         case 1:
1647         case 2:
1648                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1649                 break;
1650         case 4:
1651                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1652                 break;
1653         default:
1654                 return -EINVAL;
1655         }
1656
1657         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1658         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1659
1660         return 0;
1661 }
1662
1663 static int
1664 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1665 {
1666         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1667         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1668         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1669
1670         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1671                 /* check multi-queue mode */
1672                 switch (dev_conf->rxmode.mq_mode) {
1673                 case ETH_MQ_RX_VMDQ_DCB:
1674                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1675                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1676                         PMD_INIT_LOG(ERR, "SRIOV active,"
1677                                         " unsupported mq_mode rx %d.",
1678                                         dev_conf->rxmode.mq_mode);
1679                         return -EINVAL;
1680                 case ETH_MQ_RX_RSS:
1681                 case ETH_MQ_RX_VMDQ_RSS:
1682                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1683                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1684                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1685                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1686                                                 " invalid queue number"
1687                                                 " for VMDQ RSS, allowed"
1688                                                 " value are 1, 2 or 4.");
1689                                         return -EINVAL;
1690                                 }
1691                         break;
1692                 case ETH_MQ_RX_VMDQ_ONLY:
1693                 case ETH_MQ_RX_NONE:
1694                         /* if nothing mq mode configure, use default scheme */
1695                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1696                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1697                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1698                         break;
1699                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1700                         /* SRIOV only works in VMDq enable mode */
1701                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1702                                         " wrong mq_mode rx %d.",
1703                                         dev_conf->rxmode.mq_mode);
1704                         return -EINVAL;
1705                 }
1706
1707                 switch (dev_conf->txmode.mq_mode) {
1708                 case ETH_MQ_TX_VMDQ_DCB:
1709                         /* DCB VMDQ in SRIOV mode, not implement yet */
1710                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1711                                         " unsupported VMDQ mq_mode tx %d.",
1712                                         dev_conf->txmode.mq_mode);
1713                         return -EINVAL;
1714                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1715                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1716                         break;
1717                 }
1718
1719                 /* check valid queue number */
1720                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1721                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1722                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1723                                         " queue number must less equal to %d.",
1724                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1725                         return -EINVAL;
1726                 }
1727         } else {
1728                 /* check configuration for vmdb+dcb mode */
1729                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1730                         const struct rte_eth_vmdq_dcb_conf *conf;
1731
1732                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1733                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1734                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1735                                 return -EINVAL;
1736                         }
1737                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1738                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1739                                conf->nb_queue_pools == ETH_32_POOLS)) {
1740                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1741                                                 " nb_queue_pools must be %d or %d.",
1742                                                 ETH_16_POOLS, ETH_32_POOLS);
1743                                 return -EINVAL;
1744                         }
1745                 }
1746                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1747                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1748
1749                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1750                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1751                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1752                                 return -EINVAL;
1753                         }
1754                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1755                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1756                                conf->nb_queue_pools == ETH_32_POOLS)) {
1757                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1758                                                 " nb_queue_pools != %d and"
1759                                                 " nb_queue_pools != %d.",
1760                                                 ETH_16_POOLS, ETH_32_POOLS);
1761                                 return -EINVAL;
1762                         }
1763                 }
1764
1765                 /* For DCB mode check our configuration before we go further */
1766                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1767                         const struct rte_eth_dcb_rx_conf *conf;
1768
1769                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1770                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1771                                                  IXGBE_DCB_NB_QUEUES);
1772                                 return -EINVAL;
1773                         }
1774                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1775                         if (!(conf->nb_tcs == ETH_4_TCS ||
1776                                conf->nb_tcs == ETH_8_TCS)) {
1777                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1778                                                 " and nb_tcs != %d.",
1779                                                 ETH_4_TCS, ETH_8_TCS);
1780                                 return -EINVAL;
1781                         }
1782                 }
1783
1784                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1785                         const struct rte_eth_dcb_tx_conf *conf;
1786
1787                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1788                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1789                                                  IXGBE_DCB_NB_QUEUES);
1790                                 return -EINVAL;
1791                         }
1792                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1793                         if (!(conf->nb_tcs == ETH_4_TCS ||
1794                                conf->nb_tcs == ETH_8_TCS)) {
1795                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1796                                                 " and nb_tcs != %d.",
1797                                                 ETH_4_TCS, ETH_8_TCS);
1798                                 return -EINVAL;
1799                         }
1800                 }
1801         }
1802         return 0;
1803 }
1804
1805 static int
1806 ixgbe_dev_configure(struct rte_eth_dev *dev)
1807 {
1808         struct ixgbe_interrupt *intr =
1809                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1810         struct ixgbe_adapter *adapter =
1811                 (struct ixgbe_adapter *)dev->data->dev_private;
1812         int ret;
1813
1814         PMD_INIT_FUNC_TRACE();
1815         /* multipe queue mode checking */
1816         ret  = ixgbe_check_mq_mode(dev);
1817         if (ret != 0) {
1818                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1819                             ret);
1820                 return ret;
1821         }
1822
1823         /* set flag to update link status after init */
1824         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1825
1826         /*
1827          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1828          * allocation or vector Rx preconditions we will reset it.
1829          */
1830         adapter->rx_bulk_alloc_allowed = true;
1831         adapter->rx_vec_allowed = true;
1832
1833         return 0;
1834 }
1835
1836 /*
1837  * Configure device link speed and setup link.
1838  * It returns 0 on success.
1839  */
1840 static int
1841 ixgbe_dev_start(struct rte_eth_dev *dev)
1842 {
1843         struct ixgbe_hw *hw =
1844                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct ixgbe_vf_info *vfinfo =
1846                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1847         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1848         uint32_t intr_vector = 0;
1849         int err, link_up = 0, negotiate = 0;
1850         uint32_t speed = 0;
1851         int mask = 0;
1852         int status;
1853         uint16_t vf, idx;
1854
1855         PMD_INIT_FUNC_TRACE();
1856
1857         /* IXGBE devices don't support half duplex */
1858         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1859                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1860                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1861                              dev->data->dev_conf.link_duplex,
1862                              dev->data->port_id);
1863                 return -EINVAL;
1864         }
1865
1866         /* stop adapter */
1867         hw->adapter_stopped = 0;
1868         ixgbe_stop_adapter(hw);
1869
1870         /* reinitialize adapter
1871          * this calls reset and start */
1872         status = ixgbe_pf_reset_hw(hw);
1873         if (status != 0)
1874                 return -1;
1875         hw->mac.ops.start_hw(hw);
1876         hw->mac.get_link_status = true;
1877
1878         /* configure PF module if SRIOV enabled */
1879         ixgbe_pf_host_configure(dev);
1880
1881         /* check and configure queue intr-vector mapping */
1882         if (dev->data->dev_conf.intr_conf.rxq != 0)
1883                 intr_vector = dev->data->nb_rx_queues;
1884
1885         if (rte_intr_efd_enable(intr_handle, intr_vector))
1886                 return -1;
1887
1888         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1889                 intr_handle->intr_vec =
1890                         rte_zmalloc("intr_vec",
1891                                     dev->data->nb_rx_queues * sizeof(int),
1892                                     0);
1893                 if (intr_handle->intr_vec == NULL) {
1894                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1895                                      " intr_vec\n", dev->data->nb_rx_queues);
1896                         return -ENOMEM;
1897                 }
1898         }
1899
1900         /* confiugre msix for sleep until rx interrupt */
1901         ixgbe_configure_msix(dev);
1902
1903         /* initialize transmission unit */
1904         ixgbe_dev_tx_init(dev);
1905
1906         /* This can fail when allocating mbufs for descriptor rings */
1907         err = ixgbe_dev_rx_init(dev);
1908         if (err) {
1909                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1910                 goto error;
1911         }
1912
1913         err = ixgbe_dev_rxtx_start(dev);
1914         if (err < 0) {
1915                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1916                 goto error;
1917         }
1918
1919         /* Skip link setup if loopback mode is enabled for 82599. */
1920         if (hw->mac.type == ixgbe_mac_82599EB &&
1921                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1922                 goto skip_link_setup;
1923
1924         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1925                 err = hw->mac.ops.setup_sfp(hw);
1926                 if (err)
1927                         goto error;
1928         }
1929
1930         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1931                 /* Turn on the copper */
1932                 ixgbe_set_phy_power(hw, true);
1933         } else {
1934                 /* Turn on the laser */
1935                 ixgbe_enable_tx_laser(hw);
1936         }
1937
1938         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1939         if (err)
1940                 goto error;
1941         dev->data->dev_link.link_status = link_up;
1942
1943         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1944         if (err)
1945                 goto error;
1946
1947         switch(dev->data->dev_conf.link_speed) {
1948         case ETH_LINK_SPEED_AUTONEG:
1949                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1950                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1951                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1952                 break;
1953         case ETH_LINK_SPEED_100:
1954                 /*
1955                  * Invalid for 82598 but error will be detected by
1956                  * ixgbe_setup_link()
1957                  */
1958                 speed = IXGBE_LINK_SPEED_100_FULL;
1959                 break;
1960         case ETH_LINK_SPEED_1000:
1961                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1962                 break;
1963         case ETH_LINK_SPEED_10000:
1964                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1965                 break;
1966         default:
1967                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1968                              dev->data->dev_conf.link_speed,
1969                              dev->data->port_id);
1970                 goto error;
1971         }
1972
1973         err = ixgbe_setup_link(hw, speed, link_up);
1974         if (err)
1975                 goto error;
1976
1977 skip_link_setup:
1978
1979         /* check if lsc interrupt is enabled */
1980         if (dev->data->dev_conf.intr_conf.lsc != 0) {
1981                 if (rte_intr_allow_others(intr_handle)) {
1982                         rte_intr_callback_register(intr_handle,
1983                                                    ixgbe_dev_interrupt_handler,
1984                                                    (void *)dev);
1985                         ixgbe_dev_lsc_interrupt_setup(dev);
1986                 } else
1987                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1988                                      " no intr multiplex\n");
1989         }
1990
1991         /* check if rxq interrupt is enabled */
1992         if (dev->data->dev_conf.intr_conf.rxq != 0)
1993                 ixgbe_dev_rxq_interrupt_setup(dev);
1994
1995         /* enable uio/vfio intr/eventfd mapping */
1996         rte_intr_enable(intr_handle);
1997
1998         /* resume enabled intr since hw reset */
1999         ixgbe_enable_intr(dev);
2000
2001         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2002                 ETH_VLAN_EXTEND_MASK;
2003         ixgbe_vlan_offload_set(dev, mask);
2004
2005         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2006                 /* Enable vlan filtering for VMDq */
2007                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2008         }
2009
2010         /* Configure DCB hw */
2011         ixgbe_configure_dcb(dev);
2012
2013         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2014                 err = ixgbe_fdir_configure(dev);
2015                 if (err)
2016                         goto error;
2017         }
2018
2019         /* Restore vf rate limit */
2020         if (vfinfo != NULL) {
2021                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2022                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2023                                 if (vfinfo[vf].tx_rate[idx] != 0)
2024                                         ixgbe_set_vf_rate_limit(dev, vf,
2025                                                 vfinfo[vf].tx_rate[idx],
2026                                                 1 << idx);
2027         }
2028
2029         ixgbe_restore_statistics_mapping(dev);
2030
2031         return (0);
2032
2033 error:
2034         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2035         ixgbe_dev_clear_queues(dev);
2036         return -EIO;
2037 }
2038
2039 /*
2040  * Stop device: disable rx and tx functions to allow for reconfiguring.
2041  */
2042 static void
2043 ixgbe_dev_stop(struct rte_eth_dev *dev)
2044 {
2045         struct rte_eth_link link;
2046         struct ixgbe_hw *hw =
2047                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048         struct ixgbe_vf_info *vfinfo =
2049                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2050         struct ixgbe_filter_info *filter_info =
2051                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2052         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2053         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2054         int vf;
2055
2056         PMD_INIT_FUNC_TRACE();
2057
2058         /* disable interrupts */
2059         ixgbe_disable_intr(hw);
2060
2061         /* disable intr eventfd mapping */
2062         rte_intr_disable(intr_handle);
2063
2064         /* reset the NIC */
2065         ixgbe_pf_reset_hw(hw);
2066         hw->adapter_stopped = 0;
2067
2068         /* stop adapter */
2069         ixgbe_stop_adapter(hw);
2070
2071         for (vf = 0; vfinfo != NULL &&
2072                      vf < dev->pci_dev->max_vfs; vf++)
2073                 vfinfo[vf].clear_to_send = false;
2074
2075         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2076                 /* Turn off the copper */
2077                 ixgbe_set_phy_power(hw, false);
2078         } else {
2079                 /* Turn off the laser */
2080                 ixgbe_disable_tx_laser(hw);
2081         }
2082
2083         ixgbe_dev_clear_queues(dev);
2084
2085         /* Clear stored conf */
2086         dev->data->scattered_rx = 0;
2087         dev->data->lro = 0;
2088
2089         /* Clear recorded link status */
2090         memset(&link, 0, sizeof(link));
2091         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2092
2093         /* Remove all ntuple filters of the device */
2094         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2095              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2096                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2097                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2098                              p_5tuple, entries);
2099                 rte_free(p_5tuple);
2100         }
2101         memset(filter_info->fivetuple_mask, 0,
2102                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2103
2104         /* Clean datapath event and queue/vec mapping */
2105         rte_intr_efd_disable(intr_handle);
2106         if (intr_handle->intr_vec != NULL) {
2107                 rte_free(intr_handle->intr_vec);
2108                 intr_handle->intr_vec = NULL;
2109         }
2110 }
2111
2112 /*
2113  * Set device link up: enable tx.
2114  */
2115 static int
2116 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2117 {
2118         struct ixgbe_hw *hw =
2119                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120         if (hw->mac.type == ixgbe_mac_82599EB) {
2121 #ifdef RTE_NIC_BYPASS
2122                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2123                         /* Not suported in bypass mode */
2124                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2125                                      "by device id 0x%x", hw->device_id);
2126                         return -ENOTSUP;
2127                 }
2128 #endif
2129         }
2130
2131         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2132                 /* Turn on the copper */
2133                 ixgbe_set_phy_power(hw, true);
2134         } else {
2135                 /* Turn on the laser */
2136                 ixgbe_enable_tx_laser(hw);
2137         }
2138
2139         return 0;
2140 }
2141
2142 /*
2143  * Set device link down: disable tx.
2144  */
2145 static int
2146 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2147 {
2148         struct ixgbe_hw *hw =
2149                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         if (hw->mac.type == ixgbe_mac_82599EB) {
2151 #ifdef RTE_NIC_BYPASS
2152                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2153                         /* Not suported in bypass mode */
2154                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2155                                      "by device id 0x%x", hw->device_id);
2156                         return -ENOTSUP;
2157                 }
2158 #endif
2159         }
2160
2161         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2162                 /* Turn off the copper */
2163                 ixgbe_set_phy_power(hw, false);
2164         } else {
2165                 /* Turn off the laser */
2166                 ixgbe_disable_tx_laser(hw);
2167         }
2168
2169         return 0;
2170 }
2171
2172 /*
2173  * Reest and stop device.
2174  */
2175 static void
2176 ixgbe_dev_close(struct rte_eth_dev *dev)
2177 {
2178         struct ixgbe_hw *hw =
2179                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2180
2181         PMD_INIT_FUNC_TRACE();
2182
2183         ixgbe_pf_reset_hw(hw);
2184
2185         ixgbe_dev_stop(dev);
2186         hw->adapter_stopped = 1;
2187
2188         ixgbe_dev_free_queues(dev);
2189
2190         ixgbe_disable_pcie_master(hw);
2191
2192         /* reprogram the RAR[0] in case user changed it. */
2193         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2194 }
2195
2196 static void
2197 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2198                                                    *hw_stats, uint64_t *total_missed_rx,
2199                                                    uint64_t *total_qbrc, uint64_t *total_qprc,
2200                                                    uint64_t *total_qprdc)
2201 {
2202         uint32_t bprc, lxon, lxoff, total;
2203         unsigned i;
2204
2205         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2206         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2207         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2208         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2209
2210         for (i = 0; i < 8; i++) {
2211                 uint32_t mp;
2212                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2213                 /* global total per queue */
2214                 hw_stats->mpc[i] += mp;
2215                 /* Running comprehensive total for stats display */
2216                 *total_missed_rx += hw_stats->mpc[i];
2217                 if (hw->mac.type == ixgbe_mac_82598EB) {
2218                         hw_stats->rnbc[i] +=
2219                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2220                         hw_stats->pxonrxc[i] +=
2221                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2222                         hw_stats->pxoffrxc[i] +=
2223                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2224                 } else {
2225                         hw_stats->pxonrxc[i] +=
2226                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2227                         hw_stats->pxoffrxc[i] +=
2228                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2229                         hw_stats->pxon2offc[i] +=
2230                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2231                 }
2232                 hw_stats->pxontxc[i] +=
2233                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2234                 hw_stats->pxofftxc[i] +=
2235                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2236         }
2237         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2238                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2239                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2240                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2241                 hw_stats->qbrc[i] +=
2242                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2243                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2244                 hw_stats->qbtc[i] +=
2245                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2246                 *total_qprdc += hw_stats->qprdc[i] +=
2247                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2248
2249                 *total_qprc += hw_stats->qprc[i];
2250                 *total_qbrc += hw_stats->qbrc[i];
2251         }
2252         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2253         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2254         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2255
2256         /* Note that gprc counts missed packets */
2257         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2258
2259         if (hw->mac.type != ixgbe_mac_82598EB) {
2260                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2261                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2262                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2263                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2264                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2265                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2266                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2267                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2268         } else {
2269                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2270                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2271                 /* 82598 only has a counter in the high register */
2272                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2273                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2274                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2275         }
2276
2277         /*
2278          * Workaround: mprc hardware is incorrectly counting
2279          * broadcasts, so for now we subtract those.
2280          */
2281         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2282         hw_stats->bprc += bprc;
2283         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2284         if (hw->mac.type == ixgbe_mac_82598EB)
2285                 hw_stats->mprc -= bprc;
2286
2287         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2288         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2289         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2290         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2291         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2292         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2293
2294         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2295         hw_stats->lxontxc += lxon;
2296         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2297         hw_stats->lxofftxc += lxoff;
2298         total = lxon + lxoff;
2299
2300         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2301         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2302         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2303         hw_stats->gptc -= total;
2304         hw_stats->mptc -= total;
2305         hw_stats->ptc64 -= total;
2306         hw_stats->gotc -= total * ETHER_MIN_LEN;
2307
2308         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2309         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2310         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2311         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2312         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2313         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2314         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2315         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2316         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2317         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2318         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2319         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2320         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2321         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2322         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2323         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2324         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2325         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2326         /* Only read FCOE on 82599 */
2327         if (hw->mac.type != ixgbe_mac_82598EB) {
2328                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2329                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2330                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2331                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2332                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2333         }
2334
2335         /* Flow Director Stats registers */
2336         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2337         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2338 }
2339
2340 /*
2341  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2342  */
2343 static void
2344 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2345 {
2346         struct ixgbe_hw *hw =
2347                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2348         struct ixgbe_hw_stats *hw_stats =
2349                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2350         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2351         unsigned i;
2352
2353         total_missed_rx = 0;
2354         total_qbrc = 0;
2355         total_qprc = 0;
2356         total_qprdc = 0;
2357
2358         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2359                         &total_qprc, &total_qprdc);
2360
2361         if (stats == NULL)
2362                 return;
2363
2364         /* Fill out the rte_eth_stats statistics structure */
2365         stats->ipackets = total_qprc;
2366         stats->ibytes = total_qbrc;
2367         stats->opackets = hw_stats->gptc;
2368         stats->obytes = hw_stats->gotc;
2369
2370         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2371                 stats->q_ipackets[i] = hw_stats->qprc[i];
2372                 stats->q_opackets[i] = hw_stats->qptc[i];
2373                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2374                 stats->q_obytes[i] = hw_stats->qbtc[i];
2375                 stats->q_errors[i] = hw_stats->qprdc[i];
2376         }
2377
2378         /* Rx Errors */
2379         stats->ierrors  = hw_stats->crcerrs +
2380                           hw_stats->mspdc +
2381                           hw_stats->rlec +
2382                           hw_stats->ruc +
2383                           hw_stats->roc +
2384                           total_missed_rx +
2385                           hw_stats->illerrc +
2386                           hw_stats->errbc +
2387                           hw_stats->xec +
2388                           hw_stats->mlfc +
2389                           hw_stats->mrfc +
2390                           hw_stats->rfc +
2391                           hw_stats->fccrc +
2392                           hw_stats->fclast;
2393
2394         /* Tx Errors */
2395         stats->oerrors  = 0;
2396 }
2397
2398 static void
2399 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2400 {
2401         struct ixgbe_hw_stats *stats =
2402                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2403
2404         /* HW registers are cleared on read */
2405         ixgbe_dev_stats_get(dev, NULL);
2406
2407         /* Reset software totals */
2408         memset(stats, 0, sizeof(*stats));
2409 }
2410
2411 static int
2412 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2413                                          unsigned n)
2414 {
2415         struct ixgbe_hw *hw =
2416                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2417         struct ixgbe_hw_stats *hw_stats =
2418                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2419         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2420         unsigned i, count = IXGBE_NB_XSTATS;
2421
2422         if (n < count)
2423                 return count;
2424
2425         total_missed_rx = 0;
2426         total_qbrc = 0;
2427         total_qprc = 0;
2428         total_qprdc = 0;
2429
2430         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2431                                                            &total_qprc, &total_qprdc);
2432
2433         /* If this is a reset xstats is NULL, and we have cleared the
2434          * registers by reading them.
2435          */
2436         if (!xstats)
2437                 return 0;
2438
2439         /* Extended stats */
2440         for (i = 0; i < IXGBE_NB_XSTATS; i++) {
2441                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2442                                 "%s", rte_ixgbe_stats_strings[i].name);
2443                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2444                                                         rte_ixgbe_stats_strings[i].offset);
2445         }
2446
2447         return count;
2448 }
2449
2450 static void
2451 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2452 {
2453         struct ixgbe_hw_stats *stats =
2454                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2455
2456         /* HW registers are cleared on read */
2457         ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2458
2459         /* Reset software totals */
2460         memset(stats, 0, sizeof(*stats));
2461 }
2462
2463 static void
2464 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2465 {
2466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2467         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2468                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2469
2470         /* Good Rx packet, include VF loopback */
2471         UPDATE_VF_STAT(IXGBE_VFGPRC,
2472             hw_stats->last_vfgprc, hw_stats->vfgprc);
2473
2474         /* Good Rx octets, include VF loopback */
2475         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2476             hw_stats->last_vfgorc, hw_stats->vfgorc);
2477
2478         /* Good Tx packet, include VF loopback */
2479         UPDATE_VF_STAT(IXGBE_VFGPTC,
2480             hw_stats->last_vfgptc, hw_stats->vfgptc);
2481
2482         /* Good Tx octets, include VF loopback */
2483         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2484             hw_stats->last_vfgotc, hw_stats->vfgotc);
2485
2486         /* Rx Multicst Packet */
2487         UPDATE_VF_STAT(IXGBE_VFMPRC,
2488             hw_stats->last_vfmprc, hw_stats->vfmprc);
2489
2490         if (stats == NULL)
2491                 return;
2492
2493         stats->ipackets = hw_stats->vfgprc;
2494         stats->ibytes = hw_stats->vfgorc;
2495         stats->opackets = hw_stats->vfgptc;
2496         stats->obytes = hw_stats->vfgotc;
2497         stats->imcasts = hw_stats->vfmprc;
2498         /* stats->imcasts should be removed as imcasts is deprecated */
2499 }
2500
2501 static void
2502 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2503 {
2504         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2505                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2506
2507         /* Sync HW register to the last stats */
2508         ixgbevf_dev_stats_get(dev, NULL);
2509
2510         /* reset HW current stats*/
2511         hw_stats->vfgprc = 0;
2512         hw_stats->vfgorc = 0;
2513         hw_stats->vfgptc = 0;
2514         hw_stats->vfgotc = 0;
2515         hw_stats->vfmprc = 0;
2516
2517 }
2518
2519 static void
2520 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2521 {
2522         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523
2524         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2525         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2526         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2527         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2528         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2529         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2530         dev_info->max_vfs = dev->pci_dev->max_vfs;
2531         if (hw->mac.type == ixgbe_mac_82598EB)
2532                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2533         else
2534                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2535         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2536         dev_info->rx_offload_capa =
2537                 DEV_RX_OFFLOAD_VLAN_STRIP |
2538                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2539                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2540                 DEV_RX_OFFLOAD_TCP_CKSUM;
2541
2542         /*
2543          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2544          * mode.
2545          */
2546         if ((hw->mac.type == ixgbe_mac_82599EB ||
2547              hw->mac.type == ixgbe_mac_X540) &&
2548             !RTE_ETH_DEV_SRIOV(dev).active)
2549                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2550
2551         dev_info->tx_offload_capa =
2552                 DEV_TX_OFFLOAD_VLAN_INSERT |
2553                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2554                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2555                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2556                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2557                 DEV_TX_OFFLOAD_TCP_TSO;
2558
2559         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2560                 .rx_thresh = {
2561                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2562                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2563                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2564                 },
2565                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2566                 .rx_drop_en = 0,
2567         };
2568
2569         dev_info->default_txconf = (struct rte_eth_txconf) {
2570                 .tx_thresh = {
2571                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2572                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2573                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2574                 },
2575                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2576                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2577                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2578                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2579         };
2580         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2581         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2582         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2583 }
2584
2585 static void
2586 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2587                      struct rte_eth_dev_info *dev_info)
2588 {
2589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2590
2591         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2592         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2593         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2594         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2595         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2596         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2597         dev_info->max_vfs = dev->pci_dev->max_vfs;
2598         if (hw->mac.type == ixgbe_mac_82598EB)
2599                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2600         else
2601                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2602         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2603                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2604                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2605                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2606         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2607                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2608                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2609                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2610                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2611                                 DEV_TX_OFFLOAD_TCP_TSO;
2612
2613         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2614                 .rx_thresh = {
2615                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2616                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2617                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2618                 },
2619                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2620                 .rx_drop_en = 0,
2621         };
2622
2623         dev_info->default_txconf = (struct rte_eth_txconf) {
2624                 .tx_thresh = {
2625                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2626                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2627                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2628                 },
2629                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2630                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2631                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2632                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2633         };
2634 }
2635
2636 /* return 0 means link status changed, -1 means not changed */
2637 static int
2638 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2639 {
2640         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641         struct rte_eth_link link, old;
2642         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2643         int link_up;
2644         int diag;
2645
2646         link.link_status = 0;
2647         link.link_speed = 0;
2648         link.link_duplex = 0;
2649         memset(&old, 0, sizeof(old));
2650         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2651
2652         hw->mac.get_link_status = true;
2653
2654         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2655         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2656                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2657         else
2658                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2659
2660         if (diag != 0) {
2661                 link.link_speed = ETH_LINK_SPEED_100;
2662                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2663                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2664                 if (link.link_status == old.link_status)
2665                         return -1;
2666                 return 0;
2667         }
2668
2669         if (link_up == 0) {
2670                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2671                 if (link.link_status == old.link_status)
2672                         return -1;
2673                 return 0;
2674         }
2675         link.link_status = 1;
2676         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2677
2678         switch (link_speed) {
2679         default:
2680         case IXGBE_LINK_SPEED_UNKNOWN:
2681                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2682                 link.link_speed = ETH_LINK_SPEED_100;
2683                 break;
2684
2685         case IXGBE_LINK_SPEED_100_FULL:
2686                 link.link_speed = ETH_LINK_SPEED_100;
2687                 break;
2688
2689         case IXGBE_LINK_SPEED_1GB_FULL:
2690                 link.link_speed = ETH_LINK_SPEED_1000;
2691                 break;
2692
2693         case IXGBE_LINK_SPEED_10GB_FULL:
2694                 link.link_speed = ETH_LINK_SPEED_10000;
2695                 break;
2696         }
2697         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2698
2699         if (link.link_status == old.link_status)
2700                 return -1;
2701
2702         return 0;
2703 }
2704
2705 static void
2706 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2707 {
2708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2709         uint32_t fctrl;
2710
2711         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2712         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2713         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2714 }
2715
2716 static void
2717 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2718 {
2719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2720         uint32_t fctrl;
2721
2722         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2723         fctrl &= (~IXGBE_FCTRL_UPE);
2724         if (dev->data->all_multicast == 1)
2725                 fctrl |= IXGBE_FCTRL_MPE;
2726         else
2727                 fctrl &= (~IXGBE_FCTRL_MPE);
2728         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2729 }
2730
2731 static void
2732 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2733 {
2734         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2735         uint32_t fctrl;
2736
2737         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2738         fctrl |= IXGBE_FCTRL_MPE;
2739         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2740 }
2741
2742 static void
2743 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2744 {
2745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2746         uint32_t fctrl;
2747
2748         if (dev->data->promiscuous == 1)
2749                 return; /* must remain in all_multicast mode */
2750
2751         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2752         fctrl &= (~IXGBE_FCTRL_MPE);
2753         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2754 }
2755
2756 /**
2757  * It clears the interrupt causes and enables the interrupt.
2758  * It will be called once only during nic initialized.
2759  *
2760  * @param dev
2761  *  Pointer to struct rte_eth_dev.
2762  *
2763  * @return
2764  *  - On success, zero.
2765  *  - On failure, a negative value.
2766  */
2767 static int
2768 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2769 {
2770         struct ixgbe_interrupt *intr =
2771                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2772
2773         ixgbe_dev_link_status_print(dev);
2774         intr->mask |= IXGBE_EICR_LSC;
2775
2776         return 0;
2777 }
2778
2779 /**
2780  * It clears the interrupt causes and enables the interrupt.
2781  * It will be called once only during nic initialized.
2782  *
2783  * @param dev
2784  *  Pointer to struct rte_eth_dev.
2785  *
2786  * @return
2787  *  - On success, zero.
2788  *  - On failure, a negative value.
2789  */
2790 static int
2791 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2792 {
2793         struct ixgbe_interrupt *intr =
2794                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2795
2796         intr->mask |= IXGBE_EICR_RTX_QUEUE;
2797
2798         return 0;
2799 }
2800
2801 /*
2802  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2803  *
2804  * @param dev
2805  *  Pointer to struct rte_eth_dev.
2806  *
2807  * @return
2808  *  - On success, zero.
2809  *  - On failure, a negative value.
2810  */
2811 static int
2812 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2813 {
2814         uint32_t eicr;
2815         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2816         struct ixgbe_interrupt *intr =
2817                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2818
2819         /* clear all cause mask */
2820         ixgbe_disable_intr(hw);
2821
2822         /* read-on-clear nic registers here */
2823         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2824         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2825
2826         intr->flags = 0;
2827
2828         /* set flag for async link update */
2829         if (eicr & IXGBE_EICR_LSC)
2830                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2831
2832         if (eicr & IXGBE_EICR_MAILBOX)
2833                 intr->flags |= IXGBE_FLAG_MAILBOX;
2834
2835         return 0;
2836 }
2837
2838 static int
2839 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
2840 {
2841         uint32_t eicr;
2842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843         struct ixgbe_interrupt *intr =
2844                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2845
2846         /* clear all cause mask */
2847         ixgbevf_intr_disable(hw);
2848
2849         /* read-on-clear nic registers here */
2850         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
2851         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2852
2853         intr->flags = 0;
2854
2855         /* set flag for async link update */
2856         if (eicr & IXGBE_EICR_LSC)
2857                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2858
2859         return 0;
2860 }
2861
2862 /**
2863  * It gets and then prints the link status.
2864  *
2865  * @param dev
2866  *  Pointer to struct rte_eth_dev.
2867  *
2868  * @return
2869  *  - On success, zero.
2870  *  - On failure, a negative value.
2871  */
2872 static void
2873 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2874 {
2875         struct rte_eth_link link;
2876
2877         memset(&link, 0, sizeof(link));
2878         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2879         if (link.link_status) {
2880                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2881                                         (int)(dev->data->port_id),
2882                                         (unsigned)link.link_speed,
2883                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2884                                         "full-duplex" : "half-duplex");
2885         } else {
2886                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2887                                 (int)(dev->data->port_id));
2888         }
2889         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2890                                 dev->pci_dev->addr.domain,
2891                                 dev->pci_dev->addr.bus,
2892                                 dev->pci_dev->addr.devid,
2893                                 dev->pci_dev->addr.function);
2894 }
2895
2896 /*
2897  * It executes link_update after knowing an interrupt occurred.
2898  *
2899  * @param dev
2900  *  Pointer to struct rte_eth_dev.
2901  *
2902  * @return
2903  *  - On success, zero.
2904  *  - On failure, a negative value.
2905  */
2906 static int
2907 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2908 {
2909         struct ixgbe_interrupt *intr =
2910                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2911         int64_t timeout;
2912         struct rte_eth_link link;
2913         int intr_enable_delay = false;
2914
2915         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2916
2917         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2918                 ixgbe_pf_mbx_process(dev);
2919                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2920         }
2921
2922         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2923                 /* get the link status before link update, for predicting later */
2924                 memset(&link, 0, sizeof(link));
2925                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2926
2927                 ixgbe_dev_link_update(dev, 0);
2928
2929                 /* likely to up */
2930                 if (!link.link_status)
2931                         /* handle it 1 sec later, wait it being stable */
2932                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2933                 /* likely to down */
2934                 else
2935                         /* handle it 4 sec later, wait it being stable */
2936                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2937
2938                 ixgbe_dev_link_status_print(dev);
2939
2940                 intr_enable_delay = true;
2941         }
2942
2943         if (intr_enable_delay) {
2944                 if (rte_eal_alarm_set(timeout * 1000,
2945                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2946                         PMD_DRV_LOG(ERR, "Error setting alarm");
2947         } else {
2948                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2949                 ixgbe_enable_intr(dev);
2950                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2951         }
2952
2953
2954         return 0;
2955 }
2956
2957 static int
2958 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
2959 {
2960         struct ixgbe_hw *hw =
2961                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962
2963         PMD_DRV_LOG(DEBUG, "enable intr immediately");
2964         ixgbevf_intr_enable(hw);
2965         rte_intr_enable(&dev->pci_dev->intr_handle);
2966         return 0;
2967 }
2968
2969 /**
2970  * Interrupt handler which shall be registered for alarm callback for delayed
2971  * handling specific interrupt to wait for the stable nic state. As the
2972  * NIC interrupt state is not stable for ixgbe after link is just down,
2973  * it needs to wait 4 seconds to get the stable status.
2974  *
2975  * @param handle
2976  *  Pointer to interrupt handle.
2977  * @param param
2978  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2979  *
2980  * @return
2981  *  void
2982  */
2983 static void
2984 ixgbe_dev_interrupt_delayed_handler(void *param)
2985 {
2986         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2987         struct ixgbe_interrupt *intr =
2988                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2989         struct ixgbe_hw *hw =
2990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2991         uint32_t eicr;
2992
2993         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2994         if (eicr & IXGBE_EICR_MAILBOX)
2995                 ixgbe_pf_mbx_process(dev);
2996
2997         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2998                 ixgbe_dev_link_update(dev, 0);
2999                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3000                 ixgbe_dev_link_status_print(dev);
3001                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3002         }
3003
3004         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3005         ixgbe_enable_intr(dev);
3006         rte_intr_enable(&(dev->pci_dev->intr_handle));
3007 }
3008
3009 /**
3010  * Interrupt handler triggered by NIC  for handling
3011  * specific interrupt.
3012  *
3013  * @param handle
3014  *  Pointer to interrupt handle.
3015  * @param param
3016  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3017  *
3018  * @return
3019  *  void
3020  */
3021 static void
3022 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3023                             void *param)
3024 {
3025         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3026
3027         ixgbe_dev_interrupt_get_status(dev);
3028         ixgbe_dev_interrupt_action(dev);
3029 }
3030
3031 static void
3032 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3033                               void *param)
3034 {
3035         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3036
3037         ixgbevf_dev_interrupt_get_status(dev);
3038         ixgbevf_dev_interrupt_action(dev);
3039 }
3040
3041 static int
3042 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3043 {
3044         struct ixgbe_hw *hw;
3045
3046         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3047         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3048 }
3049
3050 static int
3051 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3052 {
3053         struct ixgbe_hw *hw;
3054
3055         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3056         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3057 }
3058
3059 static int
3060 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3061 {
3062         struct ixgbe_hw *hw;
3063         uint32_t mflcn_reg;
3064         uint32_t fccfg_reg;
3065         int rx_pause;
3066         int tx_pause;
3067
3068         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069
3070         fc_conf->pause_time = hw->fc.pause_time;
3071         fc_conf->high_water = hw->fc.high_water[0];
3072         fc_conf->low_water = hw->fc.low_water[0];
3073         fc_conf->send_xon = hw->fc.send_xon;
3074         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3075
3076         /*
3077          * Return rx_pause status according to actual setting of
3078          * MFLCN register.
3079          */
3080         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3081         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3082                 rx_pause = 1;
3083         else
3084                 rx_pause = 0;
3085
3086         /*
3087          * Return tx_pause status according to actual setting of
3088          * FCCFG register.
3089          */
3090         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3091         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3092                 tx_pause = 1;
3093         else
3094                 tx_pause = 0;
3095
3096         if (rx_pause && tx_pause)
3097                 fc_conf->mode = RTE_FC_FULL;
3098         else if (rx_pause)
3099                 fc_conf->mode = RTE_FC_RX_PAUSE;
3100         else if (tx_pause)
3101                 fc_conf->mode = RTE_FC_TX_PAUSE;
3102         else
3103                 fc_conf->mode = RTE_FC_NONE;
3104
3105         return 0;
3106 }
3107
3108 static int
3109 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3110 {
3111         struct ixgbe_hw *hw;
3112         int err;
3113         uint32_t rx_buf_size;
3114         uint32_t max_high_water;
3115         uint32_t mflcn;
3116         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3117                 ixgbe_fc_none,
3118                 ixgbe_fc_rx_pause,
3119                 ixgbe_fc_tx_pause,
3120                 ixgbe_fc_full
3121         };
3122
3123         PMD_INIT_FUNC_TRACE();
3124
3125         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3126         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3127         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3128
3129         /*
3130          * At least reserve one Ethernet frame for watermark
3131          * high_water/low_water in kilo bytes for ixgbe
3132          */
3133         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3134         if ((fc_conf->high_water > max_high_water) ||
3135                 (fc_conf->high_water < fc_conf->low_water)) {
3136                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3137                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3138                 return (-EINVAL);
3139         }
3140
3141         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3142         hw->fc.pause_time     = fc_conf->pause_time;
3143         hw->fc.high_water[0]  = fc_conf->high_water;
3144         hw->fc.low_water[0]   = fc_conf->low_water;
3145         hw->fc.send_xon       = fc_conf->send_xon;
3146         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3147
3148         err = ixgbe_fc_enable(hw);
3149
3150         /* Not negotiated is not an error case */
3151         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3152
3153                 /* check if we want to forward MAC frames - driver doesn't have native
3154                  * capability to do that, so we'll write the registers ourselves */
3155
3156                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3157
3158                 /* set or clear MFLCN.PMCF bit depending on configuration */
3159                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3160                         mflcn |= IXGBE_MFLCN_PMCF;
3161                 else
3162                         mflcn &= ~IXGBE_MFLCN_PMCF;
3163
3164                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3165                 IXGBE_WRITE_FLUSH(hw);
3166
3167                 return 0;
3168         }
3169
3170         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3171         return -EIO;
3172 }
3173
3174 /**
3175  *  ixgbe_pfc_enable_generic - Enable flow control
3176  *  @hw: pointer to hardware structure
3177  *  @tc_num: traffic class number
3178  *  Enable flow control according to the current settings.
3179  */
3180 static int
3181 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3182 {
3183         int ret_val = 0;
3184         uint32_t mflcn_reg, fccfg_reg;
3185         uint32_t reg;
3186         uint32_t fcrtl, fcrth;
3187         uint8_t i;
3188         uint8_t nb_rx_en;
3189
3190         /* Validate the water mark configuration */
3191         if (!hw->fc.pause_time) {
3192                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3193                 goto out;
3194         }
3195
3196         /* Low water mark of zero causes XOFF floods */
3197         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3198                  /* High/Low water can not be 0 */
3199                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3200                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3201                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3202                         goto out;
3203                 }
3204
3205                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3206                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3207                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3208                         goto out;
3209                 }
3210         }
3211         /* Negotiate the fc mode to use */
3212         ixgbe_fc_autoneg(hw);
3213
3214         /* Disable any previous flow control settings */
3215         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3216         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3217
3218         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3219         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3220
3221         switch (hw->fc.current_mode) {
3222         case ixgbe_fc_none:
3223                 /*
3224                  * If the count of enabled RX Priority Flow control >1,
3225                  * and the TX pause can not be disabled
3226                  */
3227                 nb_rx_en = 0;
3228                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3229                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3230                         if (reg & IXGBE_FCRTH_FCEN)
3231                                 nb_rx_en++;
3232                 }
3233                 if (nb_rx_en > 1)
3234                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3235                 break;
3236         case ixgbe_fc_rx_pause:
3237                 /*
3238                  * Rx Flow control is enabled and Tx Flow control is
3239                  * disabled by software override. Since there really
3240                  * isn't a way to advertise that we are capable of RX
3241                  * Pause ONLY, we will advertise that we support both
3242                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3243                  * disable the adapter's ability to send PAUSE frames.
3244                  */
3245                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3246                 /*
3247                  * If the count of enabled RX Priority Flow control >1,
3248                  * and the TX pause can not be disabled
3249                  */
3250                 nb_rx_en = 0;
3251                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3252                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3253                         if (reg & IXGBE_FCRTH_FCEN)
3254                                 nb_rx_en++;
3255                 }
3256                 if (nb_rx_en > 1)
3257                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3258                 break;
3259         case ixgbe_fc_tx_pause:
3260                 /*
3261                  * Tx Flow control is enabled, and Rx Flow control is
3262                  * disabled by software override.
3263                  */
3264                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3265                 break;
3266         case ixgbe_fc_full:
3267                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3268                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3269                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3270                 break;
3271         default:
3272                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3273                 ret_val = IXGBE_ERR_CONFIG;
3274                 goto out;
3275                 break;
3276         }
3277
3278         /* Set 802.3x based flow control settings. */
3279         mflcn_reg |= IXGBE_MFLCN_DPF;
3280         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3281         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3282
3283         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3284         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3285                 hw->fc.high_water[tc_num]) {
3286                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3287                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3288                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3289         } else {
3290                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3291                 /*
3292                  * In order to prevent Tx hangs when the internal Tx
3293                  * switch is enabled we must set the high water mark
3294                  * to the maximum FCRTH value.  This allows the Tx
3295                  * switch to function even under heavy Rx workloads.
3296                  */
3297                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3298         }
3299         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3300
3301         /* Configure pause time (2 TCs per register) */
3302         reg = hw->fc.pause_time * 0x00010001;
3303         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3304                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3305
3306         /* Configure flow control refresh threshold value */
3307         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3308
3309 out:
3310         return ret_val;
3311 }
3312
3313 static int
3314 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3315 {
3316         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3317         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3318
3319         if(hw->mac.type != ixgbe_mac_82598EB) {
3320                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3321         }
3322         return ret_val;
3323 }
3324
3325 static int
3326 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3327 {
3328         int err;
3329         uint32_t rx_buf_size;
3330         uint32_t max_high_water;
3331         uint8_t tc_num;
3332         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3333         struct ixgbe_hw *hw =
3334                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3335         struct ixgbe_dcb_config *dcb_config =
3336                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3337
3338         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3339                 ixgbe_fc_none,
3340                 ixgbe_fc_rx_pause,
3341                 ixgbe_fc_tx_pause,
3342                 ixgbe_fc_full
3343         };
3344
3345         PMD_INIT_FUNC_TRACE();
3346
3347         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3348         tc_num = map[pfc_conf->priority];
3349         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3350         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3351         /*
3352          * At least reserve one Ethernet frame for watermark
3353          * high_water/low_water in kilo bytes for ixgbe
3354          */
3355         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3356         if ((pfc_conf->fc.high_water > max_high_water) ||
3357             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3358                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3359                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3360                 return (-EINVAL);
3361         }
3362
3363         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3364         hw->fc.pause_time = pfc_conf->fc.pause_time;
3365         hw->fc.send_xon = pfc_conf->fc.send_xon;
3366         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3367         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3368
3369         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3370
3371         /* Not negotiated is not an error case */
3372         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3373                 return 0;
3374
3375         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3376         return -EIO;
3377 }
3378
3379 static int
3380 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3381                           struct rte_eth_rss_reta_entry64 *reta_conf,
3382                           uint16_t reta_size)
3383 {
3384         uint8_t i, j, mask;
3385         uint32_t reta, r;
3386         uint16_t idx, shift;
3387         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3388         uint16_t sp_reta_size;
3389         uint32_t reta_reg;
3390
3391         PMD_INIT_FUNC_TRACE();
3392
3393         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3394                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3395                         "NIC.");
3396                 return -ENOTSUP;
3397         }
3398
3399         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3400         if (reta_size != sp_reta_size) {
3401                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3402                         "(%d) doesn't match the number hardware can supported "
3403                         "(%d)\n", reta_size, sp_reta_size);
3404                 return -EINVAL;
3405         }
3406
3407         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3408                 idx = i / RTE_RETA_GROUP_SIZE;
3409                 shift = i % RTE_RETA_GROUP_SIZE;
3410                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3411                                                 IXGBE_4_BIT_MASK);
3412                 if (!mask)
3413                         continue;
3414                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3415                 if (mask == IXGBE_4_BIT_MASK)
3416                         r = 0;
3417                 else
3418                         r = IXGBE_READ_REG(hw, reta_reg);
3419                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3420                         if (mask & (0x1 << j))
3421                                 reta |= reta_conf[idx].reta[shift + j] <<
3422                                                         (CHAR_BIT * j);
3423                         else
3424                                 reta |= r & (IXGBE_8_BIT_MASK <<
3425                                                 (CHAR_BIT * j));
3426                 }
3427                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3428         }
3429
3430         return 0;
3431 }
3432
3433 static int
3434 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3435                          struct rte_eth_rss_reta_entry64 *reta_conf,
3436                          uint16_t reta_size)
3437 {
3438         uint8_t i, j, mask;
3439         uint32_t reta;
3440         uint16_t idx, shift;
3441         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442         uint16_t sp_reta_size;
3443         uint32_t reta_reg;
3444
3445         PMD_INIT_FUNC_TRACE();
3446         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3447         if (reta_size != sp_reta_size) {
3448                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3449                         "(%d) doesn't match the number hardware can supported "
3450                         "(%d)\n", reta_size, sp_reta_size);
3451                 return -EINVAL;
3452         }
3453
3454         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3455                 idx = i / RTE_RETA_GROUP_SIZE;
3456                 shift = i % RTE_RETA_GROUP_SIZE;
3457                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3458                                                 IXGBE_4_BIT_MASK);
3459                 if (!mask)
3460                         continue;
3461
3462                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3463                 reta = IXGBE_READ_REG(hw, reta_reg);
3464                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3465                         if (mask & (0x1 << j))
3466                                 reta_conf[idx].reta[shift + j] =
3467                                         ((reta >> (CHAR_BIT * j)) &
3468                                                 IXGBE_8_BIT_MASK);
3469                 }
3470         }
3471
3472         return 0;
3473 }
3474
3475 static void
3476 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3477                                 uint32_t index, uint32_t pool)
3478 {
3479         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3480         uint32_t enable_addr = 1;
3481
3482         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3483 }
3484
3485 static void
3486 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3487 {
3488         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3489
3490         ixgbe_clear_rar(hw, index);
3491 }
3492
3493 static void
3494 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3495 {
3496         ixgbe_remove_rar(dev, 0);
3497
3498         ixgbe_add_rar(dev, addr, 0, 0);
3499 }
3500
3501 static int
3502 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3503 {
3504         uint32_t hlreg0;
3505         uint32_t maxfrs;
3506         struct ixgbe_hw *hw;
3507         struct rte_eth_dev_info dev_info;
3508         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3509
3510         ixgbe_dev_info_get(dev, &dev_info);
3511
3512         /* check that mtu is within the allowed range */
3513         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3514                 return -EINVAL;
3515
3516         /* refuse mtu that requires the support of scattered packets when this
3517          * feature has not been enabled before. */
3518         if (!dev->data->scattered_rx &&
3519             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3520              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3521                 return -EINVAL;
3522
3523         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3524         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3525
3526         /* switch to jumbo mode if needed */
3527         if (frame_size > ETHER_MAX_LEN) {
3528                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3529                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3530         } else {
3531                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3532                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3533         }
3534         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3535
3536         /* update max frame size */
3537         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3538
3539         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3540         maxfrs &= 0x0000FFFF;
3541         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3542         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3543
3544         return 0;
3545 }
3546
3547 /*
3548  * Virtual Function operations
3549  */
3550 static void
3551 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3552 {
3553         PMD_INIT_FUNC_TRACE();
3554
3555         /* Clear interrupt mask to stop from interrupts being generated */
3556         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3557
3558         IXGBE_WRITE_FLUSH(hw);
3559 }
3560
3561 static void
3562 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3563 {
3564         PMD_INIT_FUNC_TRACE();
3565
3566         /* VF enable interrupt autoclean */
3567         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3568         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3569         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3570
3571         IXGBE_WRITE_FLUSH(hw);
3572 }
3573
3574 static int
3575 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3576 {
3577         struct rte_eth_conf* conf = &dev->data->dev_conf;
3578         struct ixgbe_adapter *adapter =
3579                         (struct ixgbe_adapter *)dev->data->dev_private;
3580
3581         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3582                      dev->data->port_id);
3583
3584         /*
3585          * VF has no ability to enable/disable HW CRC
3586          * Keep the persistent behavior the same as Host PF
3587          */
3588 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3589         if (!conf->rxmode.hw_strip_crc) {
3590                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3591                 conf->rxmode.hw_strip_crc = 1;
3592         }
3593 #else
3594         if (conf->rxmode.hw_strip_crc) {
3595                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3596                 conf->rxmode.hw_strip_crc = 0;
3597         }
3598 #endif
3599
3600         /*
3601          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3602          * allocation or vector Rx preconditions we will reset it.
3603          */
3604         adapter->rx_bulk_alloc_allowed = true;
3605         adapter->rx_vec_allowed = true;
3606
3607         return 0;
3608 }
3609
3610 static int
3611 ixgbevf_dev_start(struct rte_eth_dev *dev)
3612 {
3613         struct ixgbe_hw *hw =
3614                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3615         uint32_t intr_vector = 0;
3616         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3617
3618         int err, mask = 0;
3619
3620         PMD_INIT_FUNC_TRACE();
3621
3622         hw->mac.ops.reset_hw(hw);
3623         hw->mac.get_link_status = true;
3624
3625         /* negotiate mailbox API version to use with the PF. */
3626         ixgbevf_negotiate_api(hw);
3627
3628         ixgbevf_dev_tx_init(dev);
3629
3630         /* This can fail when allocating mbufs for descriptor rings */
3631         err = ixgbevf_dev_rx_init(dev);
3632         if (err) {
3633                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3634                 ixgbe_dev_clear_queues(dev);
3635                 return err;
3636         }
3637
3638         /* Set vfta */
3639         ixgbevf_set_vfta_all(dev,1);
3640
3641         /* Set HW strip */
3642         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3643                 ETH_VLAN_EXTEND_MASK;
3644         ixgbevf_vlan_offload_set(dev, mask);
3645
3646         ixgbevf_dev_rxtx_start(dev);
3647
3648         /* check and configure queue intr-vector mapping */
3649         if (dev->data->dev_conf.intr_conf.rxq != 0)
3650                 intr_vector = dev->data->nb_rx_queues;
3651
3652         if (rte_intr_efd_enable(intr_handle, intr_vector))
3653                 return -1;
3654
3655         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3656                 intr_handle->intr_vec =
3657                         rte_zmalloc("intr_vec",
3658                                     dev->data->nb_rx_queues * sizeof(int), 0);
3659                 if (intr_handle->intr_vec == NULL) {
3660                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3661                                      " intr_vec\n", dev->data->nb_rx_queues);
3662                         return -ENOMEM;
3663                 }
3664         }
3665         ixgbevf_configure_msix(dev);
3666
3667         if (dev->data->dev_conf.intr_conf.lsc != 0) {
3668                 if (rte_intr_allow_others(intr_handle))
3669                         rte_intr_callback_register(intr_handle,
3670                                         ixgbevf_dev_interrupt_handler,
3671                                         (void *)dev);
3672                 else
3673                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
3674                                      " no intr multiplex\n");
3675         }
3676
3677         rte_intr_enable(intr_handle);
3678
3679         /* Re-enable interrupt for VF */
3680         ixgbevf_intr_enable(hw);
3681
3682         return 0;
3683 }
3684
3685 static void
3686 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3687 {
3688         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3689         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3690
3691         PMD_INIT_FUNC_TRACE();
3692
3693         hw->adapter_stopped = 1;
3694         ixgbe_stop_adapter(hw);
3695
3696         /*
3697           * Clear what we set, but we still keep shadow_vfta to
3698           * restore after device starts
3699           */
3700         ixgbevf_set_vfta_all(dev,0);
3701
3702         /* Clear stored conf */
3703         dev->data->scattered_rx = 0;
3704
3705         ixgbe_dev_clear_queues(dev);
3706
3707         /* disable intr eventfd mapping */
3708         rte_intr_disable(intr_handle);
3709
3710         /* Clean datapath event and queue/vec mapping */
3711         rte_intr_efd_disable(intr_handle);
3712         if (intr_handle->intr_vec != NULL) {
3713                 rte_free(intr_handle->intr_vec);
3714                 intr_handle->intr_vec = NULL;
3715         }
3716 }
3717
3718 static void
3719 ixgbevf_dev_close(struct rte_eth_dev *dev)
3720 {
3721         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3722         struct rte_pci_device *pci_dev;
3723
3724         PMD_INIT_FUNC_TRACE();
3725
3726         ixgbe_reset_hw(hw);
3727
3728         ixgbevf_dev_stop(dev);
3729
3730         ixgbe_dev_free_queues(dev);
3731
3732         /* reprogram the RAR[0] in case user changed it. */
3733         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3734
3735         pci_dev = dev->pci_dev;
3736         if (pci_dev->intr_handle.intr_vec) {
3737                 rte_free(pci_dev->intr_handle.intr_vec);
3738                 pci_dev->intr_handle.intr_vec = NULL;
3739         }
3740 }
3741
3742 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3743 {
3744         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3745         struct ixgbe_vfta * shadow_vfta =
3746                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3747         int i = 0, j = 0, vfta = 0, mask = 1;
3748
3749         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3750                 vfta = shadow_vfta->vfta[i];
3751                 if(vfta){
3752                         mask = 1;
3753                         for (j = 0; j < 32; j++){
3754                                 if(vfta & mask)
3755                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3756                                 mask<<=1;
3757                         }
3758                 }
3759         }
3760
3761 }
3762
3763 static int
3764 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3765 {
3766         struct ixgbe_hw *hw =
3767                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3768         struct ixgbe_vfta * shadow_vfta =
3769                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3770         uint32_t vid_idx = 0;
3771         uint32_t vid_bit = 0;
3772         int ret = 0;
3773
3774         PMD_INIT_FUNC_TRACE();
3775
3776         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3777         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3778         if(ret){
3779                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3780                 return ret;
3781         }
3782         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3783         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3784
3785         /* Save what we set and retore it after device reset */
3786         if (on)
3787                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3788         else
3789                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3790
3791         return 0;
3792 }
3793
3794 static void
3795 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3796 {
3797         struct ixgbe_hw *hw =
3798                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3799         uint32_t ctrl;
3800
3801         PMD_INIT_FUNC_TRACE();
3802
3803         if(queue >= hw->mac.max_rx_queues)
3804                 return;
3805
3806         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3807         if(on)
3808                 ctrl |= IXGBE_RXDCTL_VME;
3809         else
3810                 ctrl &= ~IXGBE_RXDCTL_VME;
3811         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3812
3813         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3814 }
3815
3816 static void
3817 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3818 {
3819         struct ixgbe_hw *hw =
3820                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3821         uint16_t i;
3822         int on = 0;
3823
3824         /* VF function only support hw strip feature, others are not support */
3825         if(mask & ETH_VLAN_STRIP_MASK){
3826                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3827
3828                 for(i=0; i < hw->mac.max_rx_queues; i++)
3829                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3830         }
3831 }
3832
3833 static int
3834 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3835 {
3836         uint32_t reg_val;
3837
3838         /* we only need to do this if VMDq is enabled */
3839         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3840         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3841                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3842                 return (-1);
3843         }
3844
3845         return 0;
3846 }
3847
3848 static uint32_t
3849 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3850 {
3851         uint32_t vector = 0;
3852         switch (hw->mac.mc_filter_type) {
3853         case 0:   /* use bits [47:36] of the address */
3854                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3855                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3856                 break;
3857         case 1:   /* use bits [46:35] of the address */
3858                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3859                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3860                 break;
3861         case 2:   /* use bits [45:34] of the address */
3862                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3863                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3864                 break;
3865         case 3:   /* use bits [43:32] of the address */
3866                 vector = ((uc_addr->addr_bytes[4]) |
3867                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3868                 break;
3869         default:  /* Invalid mc_filter_type */
3870                 break;
3871         }
3872
3873         /* vector can only be 12-bits or boundary will be exceeded */
3874         vector &= 0xFFF;
3875         return vector;
3876 }
3877
3878 static int
3879 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3880                                uint8_t on)
3881 {
3882         uint32_t vector;
3883         uint32_t uta_idx;
3884         uint32_t reg_val;
3885         uint32_t uta_shift;
3886         uint32_t rc;
3887         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3888         const uint32_t ixgbe_uta_bit_shift = 5;
3889         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3890         const uint32_t bit1 = 0x1;
3891
3892         struct ixgbe_hw *hw =
3893                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3894         struct ixgbe_uta_info *uta_info =
3895                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3896
3897         /* The UTA table only exists on 82599 hardware and newer */
3898         if (hw->mac.type < ixgbe_mac_82599EB)
3899                 return (-ENOTSUP);
3900
3901         vector = ixgbe_uta_vector(hw,mac_addr);
3902         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3903         uta_shift = vector & ixgbe_uta_bit_mask;
3904
3905         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3906         if(rc == on)
3907                 return 0;
3908
3909         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3910         if (on) {
3911                 uta_info->uta_in_use++;
3912                 reg_val |= (bit1 << uta_shift);
3913                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3914         } else {
3915                 uta_info->uta_in_use--;
3916                 reg_val &= ~(bit1 << uta_shift);
3917                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3918         }
3919
3920         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3921
3922         if (uta_info->uta_in_use > 0)
3923                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3924                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3925         else
3926                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3927
3928         return 0;
3929 }
3930
3931 static int
3932 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3933 {
3934         int i;
3935         struct ixgbe_hw *hw =
3936                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3937         struct ixgbe_uta_info *uta_info =
3938                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3939
3940         /* The UTA table only exists on 82599 hardware and newer */
3941         if (hw->mac.type < ixgbe_mac_82599EB)
3942                 return (-ENOTSUP);
3943
3944         if(on) {
3945                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3946                         uta_info->uta_shadow[i] = ~0;
3947                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3948                 }
3949         } else {
3950                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3951                         uta_info->uta_shadow[i] = 0;
3952                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3953                 }
3954         }
3955         return 0;
3956
3957 }
3958
3959 uint32_t
3960 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3961 {
3962         uint32_t new_val = orig_val;
3963
3964         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3965                 new_val |= IXGBE_VMOLR_AUPE;
3966         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3967                 new_val |= IXGBE_VMOLR_ROMPE;
3968         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3969                 new_val |= IXGBE_VMOLR_ROPE;
3970         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3971                 new_val |= IXGBE_VMOLR_BAM;
3972         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3973                 new_val |= IXGBE_VMOLR_MPE;
3974
3975         return new_val;
3976 }
3977
3978 static int
3979 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3980                                uint16_t rx_mask, uint8_t on)
3981 {
3982         int val = 0;
3983
3984         struct ixgbe_hw *hw =
3985                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3986         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3987
3988         if (hw->mac.type == ixgbe_mac_82598EB) {
3989                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3990                              " on 82599 hardware and newer");
3991                 return (-ENOTSUP);
3992         }
3993         if (ixgbe_vmdq_mode_check(hw) < 0)
3994                 return (-ENOTSUP);
3995
3996         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3997
3998         if (on)
3999                 vmolr |= val;
4000         else
4001                 vmolr &= ~val;
4002
4003         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4004
4005         return 0;
4006 }
4007
4008 static int
4009 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4010 {
4011         uint32_t reg,addr;
4012         uint32_t val;
4013         const uint8_t bit1 = 0x1;
4014
4015         struct ixgbe_hw *hw =
4016                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4017
4018         if (ixgbe_vmdq_mode_check(hw) < 0)
4019                 return (-ENOTSUP);
4020
4021         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4022         reg = IXGBE_READ_REG(hw, addr);
4023         val = bit1 << pool;
4024
4025         if (on)
4026                 reg |= val;
4027         else
4028                 reg &= ~val;
4029
4030         IXGBE_WRITE_REG(hw, addr,reg);
4031
4032         return 0;
4033 }
4034
4035 static int
4036 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4037 {
4038         uint32_t reg,addr;
4039         uint32_t val;
4040         const uint8_t bit1 = 0x1;
4041
4042         struct ixgbe_hw *hw =
4043                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4044
4045         if (ixgbe_vmdq_mode_check(hw) < 0)
4046                 return (-ENOTSUP);
4047
4048         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4049         reg = IXGBE_READ_REG(hw, addr);
4050         val = bit1 << pool;
4051
4052         if (on)
4053                 reg |= val;
4054         else
4055                 reg &= ~val;
4056
4057         IXGBE_WRITE_REG(hw, addr,reg);
4058
4059         return 0;
4060 }
4061
4062 static int
4063 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4064                         uint64_t pool_mask, uint8_t vlan_on)
4065 {
4066         int ret = 0;
4067         uint16_t pool_idx;
4068         struct ixgbe_hw *hw =
4069                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4070
4071         if (ixgbe_vmdq_mode_check(hw) < 0)
4072                 return (-ENOTSUP);
4073         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4074                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4075                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4076                         if (ret < 0)
4077                                 return ret;
4078         }
4079
4080         return ret;
4081 }
4082
4083 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4084 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4085 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4086 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4087 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4088         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4089         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4090
4091 static int
4092 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4093                         struct rte_eth_mirror_conf *mirror_conf,
4094                         uint8_t rule_id, uint8_t on)
4095 {
4096         uint32_t mr_ctl,vlvf;
4097         uint32_t mp_lsb = 0;
4098         uint32_t mv_msb = 0;
4099         uint32_t mv_lsb = 0;
4100         uint32_t mp_msb = 0;
4101         uint8_t i = 0;
4102         int reg_index = 0;
4103         uint64_t vlan_mask = 0;
4104
4105         const uint8_t pool_mask_offset = 32;
4106         const uint8_t vlan_mask_offset = 32;
4107         const uint8_t dst_pool_offset = 8;
4108         const uint8_t rule_mr_offset  = 4;
4109         const uint8_t mirror_rule_mask= 0x0F;
4110
4111         struct ixgbe_mirror_info *mr_info =
4112                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4113         struct ixgbe_hw *hw =
4114                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4115         uint8_t mirror_type = 0;
4116
4117         if (ixgbe_vmdq_mode_check(hw) < 0)
4118                 return -ENOTSUP;
4119
4120         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4121                 return -EINVAL;
4122
4123         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4124                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4125                         mirror_conf->rule_type);
4126                 return -EINVAL;
4127         }
4128
4129         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4130                 mirror_type |= IXGBE_MRCTL_VLME;
4131                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4132                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4133                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4134                                 /* search vlan id related pool vlan filter index */
4135                                 reg_index = ixgbe_find_vlvf_slot(hw,
4136                                                 mirror_conf->vlan.vlan_id[i]);
4137                                 if(reg_index < 0)
4138                                         return -EINVAL;
4139                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4140                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4141                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4142                                       mirror_conf->vlan.vlan_id[i]))
4143                                         vlan_mask |= (1ULL << reg_index);
4144                                 else
4145                                         return -EINVAL;
4146                         }
4147                 }
4148
4149                 if (on) {
4150                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4151                         mv_msb = vlan_mask >> vlan_mask_offset;
4152
4153                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4154                                                 mirror_conf->vlan.vlan_mask;
4155                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4156                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4157                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4158                                                 mirror_conf->vlan.vlan_id[i];
4159                         }
4160                 } else {
4161                         mv_lsb = 0;
4162                         mv_msb = 0;
4163                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4164                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4165                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4166                 }
4167         }
4168
4169         /*
4170          * if enable pool mirror, write related pool mask register,if disable
4171          * pool mirror, clear PFMRVM register
4172          */
4173         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4174                 mirror_type |= IXGBE_MRCTL_VPME;
4175                 if (on) {
4176                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4177                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4178                         mr_info->mr_conf[rule_id].pool_mask =
4179                                         mirror_conf->pool_mask;
4180
4181                 } else {
4182                         mp_lsb = 0;
4183                         mp_msb = 0;
4184                         mr_info->mr_conf[rule_id].pool_mask = 0;
4185                 }
4186         }
4187         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4188                 mirror_type |= IXGBE_MRCTL_UPME;
4189         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4190                 mirror_type |= IXGBE_MRCTL_DPME;
4191
4192         /* read  mirror control register and recalculate it */
4193         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4194
4195         if (on) {
4196                 mr_ctl |= mirror_type;
4197                 mr_ctl &= mirror_rule_mask;
4198                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4199         } else
4200                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4201
4202         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4203         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4204
4205         /* write mirrror control  register */
4206         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4207
4208         /* write pool mirrror control  register */
4209         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4210                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4211                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4212                                 mp_msb);
4213         }
4214         /* write VLAN mirrror control  register */
4215         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4216                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4217                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4218                                 mv_msb);
4219         }
4220
4221         return 0;
4222 }
4223
4224 static int
4225 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4226 {
4227         int mr_ctl = 0;
4228         uint32_t lsb_val = 0;
4229         uint32_t msb_val = 0;
4230         const uint8_t rule_mr_offset = 4;
4231
4232         struct ixgbe_hw *hw =
4233                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4234         struct ixgbe_mirror_info *mr_info =
4235                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4236
4237         if (ixgbe_vmdq_mode_check(hw) < 0)
4238                 return (-ENOTSUP);
4239
4240         memset(&mr_info->mr_conf[rule_id], 0,
4241                 sizeof(struct rte_eth_mirror_conf));
4242
4243         /* clear PFVMCTL register */
4244         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4245
4246         /* clear pool mask register */
4247         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4248         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4249
4250         /* clear vlan mask register */
4251         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4252         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4253
4254         return 0;
4255 }
4256
4257 static int
4258 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4259 {
4260         uint32_t mask;
4261         struct ixgbe_hw *hw =
4262                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4263
4264         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4265         mask |= (1 << queue_id);
4266         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4267
4268         rte_intr_enable(&dev->pci_dev->intr_handle);
4269
4270         return 0;
4271 }
4272
4273 static int
4274 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4275 {
4276         uint32_t mask;
4277         struct ixgbe_hw *hw =
4278                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4279
4280         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4281         mask &= ~(1 << queue_id);
4282         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4283
4284         return 0;
4285 }
4286
4287 static int
4288 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4289 {
4290         uint32_t mask;
4291         struct ixgbe_hw *hw =
4292                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293         struct ixgbe_interrupt *intr =
4294                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4295
4296         if (queue_id < 16) {
4297                 ixgbe_disable_intr(hw);
4298                 intr->mask |= (1 << queue_id);
4299                 ixgbe_enable_intr(dev);
4300         } else if (queue_id < 32) {
4301                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4302                 mask &= (1 << queue_id);
4303                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4304         } else if (queue_id < 64) {
4305                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4306                 mask &= (1 << (queue_id - 32));
4307                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4308         }
4309         rte_intr_enable(&dev->pci_dev->intr_handle);
4310
4311         return 0;
4312 }
4313
4314 static int
4315 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4316 {
4317         uint32_t mask;
4318         struct ixgbe_hw *hw =
4319                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4320         struct ixgbe_interrupt *intr =
4321                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4322
4323         if (queue_id < 16) {
4324                 ixgbe_disable_intr(hw);
4325                 intr->mask &= ~(1 << queue_id);
4326                 ixgbe_enable_intr(dev);
4327         } else if (queue_id < 32) {
4328                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4329                 mask &= ~(1 << queue_id);
4330                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4331         } else if (queue_id < 64) {
4332                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4333                 mask &= ~(1 << (queue_id - 32));
4334                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4335         }
4336
4337         return 0;
4338 }
4339
4340 static void
4341 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4342                      uint8_t queue, uint8_t msix_vector)
4343 {
4344         uint32_t tmp, idx;
4345
4346         if (direction == -1) {
4347                 /* other causes */
4348                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4349                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4350                 tmp &= ~0xFF;
4351                 tmp |= msix_vector;
4352                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4353         } else {
4354                 /* rx or tx cause */
4355                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4356                 idx = ((16 * (queue & 1)) + (8 * direction));
4357                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4358                 tmp &= ~(0xFF << idx);
4359                 tmp |= (msix_vector << idx);
4360                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4361         }
4362 }
4363
4364 /**
4365  * set the IVAR registers, mapping interrupt causes to vectors
4366  * @param hw
4367  *  pointer to ixgbe_hw struct
4368  * @direction
4369  *  0 for Rx, 1 for Tx, -1 for other causes
4370  * @queue
4371  *  queue to map the corresponding interrupt to
4372  * @msix_vector
4373  *  the vector to map to the corresponding queue
4374  */
4375 static void
4376 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4377                    uint8_t queue, uint8_t msix_vector)
4378 {
4379         uint32_t tmp, idx;
4380
4381         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4382         if (hw->mac.type == ixgbe_mac_82598EB) {
4383                 if (direction == -1)
4384                         direction = 0;
4385                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4386                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4387                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4388                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4389                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4390         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4391                         (hw->mac.type == ixgbe_mac_X540)) {
4392                 if (direction == -1) {
4393                         /* other causes */
4394                         idx = ((queue & 1) * 8);
4395                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4396                         tmp &= ~(0xFF << idx);
4397                         tmp |= (msix_vector << idx);
4398                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4399                 } else {
4400                         /* rx or tx causes */
4401                         idx = ((16 * (queue & 1)) + (8 * direction));
4402                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4403                         tmp &= ~(0xFF << idx);
4404                         tmp |= (msix_vector << idx);
4405                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4406                 }
4407         }
4408 }
4409
4410 static void
4411 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4412 {
4413         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4414         struct ixgbe_hw *hw =
4415                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4416         uint32_t q_idx;
4417         uint32_t vector_idx = 0;
4418
4419         /* won't configure msix register if no mapping is done
4420          * between intr vector and event fd.
4421          */
4422         if (!rte_intr_dp_is_en(intr_handle))
4423                 return;
4424
4425         /* Configure all RX queues of VF */
4426         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4427                 /* Force all queue use vector 0,
4428                  * as IXGBE_VF_MAXMSIVECOTR = 1
4429                  */
4430                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4431                 intr_handle->intr_vec[q_idx] = vector_idx;
4432         }
4433
4434         /* Configure VF Rx queue ivar */
4435         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4436 }
4437
4438 /**
4439  * Sets up the hardware to properly generate MSI-X interrupts
4440  * @hw
4441  *  board private structure
4442  */
4443 static void
4444 ixgbe_configure_msix(struct rte_eth_dev *dev)
4445 {
4446         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4447         struct ixgbe_hw *hw =
4448                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4449         uint32_t queue_id, vec = 0;
4450         uint32_t mask;
4451         uint32_t gpie;
4452
4453         /* won't configure msix register if no mapping is done
4454          * between intr vector and event fd
4455          */
4456         if (!rte_intr_dp_is_en(intr_handle))
4457                 return;
4458
4459         /* setup GPIE for MSI-x mode */
4460         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4461         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4462                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4463         /* auto clearing and auto setting corresponding bits in EIMS
4464          * when MSI-X interrupt is triggered
4465          */
4466         if (hw->mac.type == ixgbe_mac_82598EB) {
4467                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4468         } else {
4469                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4470                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4471         }
4472         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4473
4474         /* Populate the IVAR table and set the ITR values to the
4475          * corresponding register.
4476          */
4477         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4478              queue_id++) {
4479                 /* by default, 1:1 mapping */
4480                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4481                 intr_handle->intr_vec[queue_id] = vec;
4482                 if (vec < intr_handle->nb_efd - 1)
4483                         vec++;
4484         }
4485
4486         switch (hw->mac.type) {
4487         case ixgbe_mac_82598EB:
4488                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4489                                    intr_handle->max_intr - 1);
4490                 break;
4491         case ixgbe_mac_82599EB:
4492         case ixgbe_mac_X540:
4493                 ixgbe_set_ivar_map(hw, -1, 1, intr_handle->max_intr - 1);
4494                 break;
4495         default:
4496                 break;
4497         }
4498         IXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id),
4499                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4500
4501         /* set up to autoclear timer, and the vectors */
4502         mask = IXGBE_EIMS_ENABLE_MASK;
4503         mask &= ~(IXGBE_EIMS_OTHER |
4504                   IXGBE_EIMS_MAILBOX |
4505                   IXGBE_EIMS_LSC);
4506
4507         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4508 }
4509
4510 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4511         uint16_t queue_idx, uint16_t tx_rate)
4512 {
4513         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4514         uint32_t rf_dec, rf_int;
4515         uint32_t bcnrc_val;
4516         uint16_t link_speed = dev->data->dev_link.link_speed;
4517
4518         if (queue_idx >= hw->mac.max_tx_queues)
4519                 return -EINVAL;
4520
4521         if (tx_rate != 0) {
4522                 /* Calculate the rate factor values to set */
4523                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4524                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4525                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4526
4527                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4528                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4529                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4530                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4531         } else {
4532                 bcnrc_val = 0;
4533         }
4534
4535         /*
4536          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4537          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4538          * set as 0x4.
4539          */
4540         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4541                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4542                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4543                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4544                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4545         else
4546                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4547                         IXGBE_MMW_SIZE_DEFAULT);
4548
4549         /* Set RTTBCNRC of queue X */
4550         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4551         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4552         IXGBE_WRITE_FLUSH(hw);
4553
4554         return 0;
4555 }
4556
4557 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4558         uint16_t tx_rate, uint64_t q_msk)
4559 {
4560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4561         struct ixgbe_vf_info *vfinfo =
4562                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4563         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4564         uint32_t queue_stride =
4565                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4566         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4567         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4568         uint16_t total_rate = 0;
4569
4570         if (queue_end >= hw->mac.max_tx_queues)
4571                 return -EINVAL;
4572
4573         if (vfinfo != NULL) {
4574                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4575                         if (vf_idx == vf)
4576                                 continue;
4577                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4578                                 idx++)
4579                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4580                 }
4581         } else
4582                 return -EINVAL;
4583
4584         /* Store tx_rate for this vf. */
4585         for (idx = 0; idx < nb_q_per_pool; idx++) {
4586                 if (((uint64_t)0x1 << idx) & q_msk) {
4587                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4588                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4589                         total_rate += tx_rate;
4590                 }
4591         }
4592
4593         if (total_rate > dev->data->dev_link.link_speed) {
4594                 /*
4595                  * Reset stored TX rate of the VF if it causes exceed
4596                  * link speed.
4597                  */
4598                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4599                 return -EINVAL;
4600         }
4601
4602         /* Set RTTBCNRC of each queue/pool for vf X  */
4603         for (; queue_idx <= queue_end; queue_idx++) {
4604                 if (0x1 & q_msk)
4605                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4606                 q_msk = q_msk >> 1;
4607         }
4608
4609         return 0;
4610 }
4611
4612 static void
4613 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4614                      __attribute__((unused)) uint32_t index,
4615                      __attribute__((unused)) uint32_t pool)
4616 {
4617         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4618         int diag;
4619
4620         /*
4621          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4622          * operation. Trap this case to avoid exhausting the [very limited]
4623          * set of PF resources used to store VF MAC addresses.
4624          */
4625         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4626                 return;
4627         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4628         if (diag == 0)
4629                 return;
4630         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4631 }
4632
4633 static void
4634 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4635 {
4636         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4637         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4638         struct ether_addr *mac_addr;
4639         uint32_t i;
4640         int diag;
4641
4642         /*
4643          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4644          * not support the deletion of a given MAC address.
4645          * Instead, it imposes to delete all MAC addresses, then to add again
4646          * all MAC addresses with the exception of the one to be deleted.
4647          */
4648         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4649
4650         /*
4651          * Add again all MAC addresses, with the exception of the deleted one
4652          * and of the permanent MAC address.
4653          */
4654         for (i = 0, mac_addr = dev->data->mac_addrs;
4655              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4656                 /* Skip the deleted MAC address */
4657                 if (i == index)
4658                         continue;
4659                 /* Skip NULL MAC addresses */
4660                 if (is_zero_ether_addr(mac_addr))
4661                         continue;
4662                 /* Skip the permanent MAC address */
4663                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4664                         continue;
4665                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4666                 if (diag != 0)
4667                         PMD_DRV_LOG(ERR,
4668                                     "Adding again MAC address "
4669                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4670                                     "diag=%d",
4671                                     mac_addr->addr_bytes[0],
4672                                     mac_addr->addr_bytes[1],
4673                                     mac_addr->addr_bytes[2],
4674                                     mac_addr->addr_bytes[3],
4675                                     mac_addr->addr_bytes[4],
4676                                     mac_addr->addr_bytes[5],
4677                                     diag);
4678         }
4679 }
4680
4681 static void
4682 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4683 {
4684         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685
4686         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4687 }
4688
4689 #define MAC_TYPE_FILTER_SUP(type)    do {\
4690         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4691                 (type) != ixgbe_mac_X550)\
4692                 return -ENOTSUP;\
4693 } while (0)
4694
4695 static int
4696 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4697                         struct rte_eth_syn_filter *filter,
4698                         bool add)
4699 {
4700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4701         uint32_t synqf;
4702
4703         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4704                 return -EINVAL;
4705
4706         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4707
4708         if (add) {
4709                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4710                         return -EINVAL;
4711                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4712                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4713
4714                 if (filter->hig_pri)
4715                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4716                 else
4717                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4718         } else {
4719                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4720                         return -ENOENT;
4721                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4722         }
4723         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4724         IXGBE_WRITE_FLUSH(hw);
4725         return 0;
4726 }
4727
4728 static int
4729 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4730                         struct rte_eth_syn_filter *filter)
4731 {
4732         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4733         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4734
4735         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4736                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4737                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4738                 return 0;
4739         }
4740         return -ENOENT;
4741 }
4742
4743 static int
4744 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4745                         enum rte_filter_op filter_op,
4746                         void *arg)
4747 {
4748         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4749         int ret;
4750
4751         MAC_TYPE_FILTER_SUP(hw->mac.type);
4752
4753         if (filter_op == RTE_ETH_FILTER_NOP)
4754                 return 0;
4755
4756         if (arg == NULL) {
4757                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4758                             filter_op);
4759                 return -EINVAL;
4760         }
4761
4762         switch (filter_op) {
4763         case RTE_ETH_FILTER_ADD:
4764                 ret = ixgbe_syn_filter_set(dev,
4765                                 (struct rte_eth_syn_filter *)arg,
4766                                 TRUE);
4767                 break;
4768         case RTE_ETH_FILTER_DELETE:
4769                 ret = ixgbe_syn_filter_set(dev,
4770                                 (struct rte_eth_syn_filter *)arg,
4771                                 FALSE);
4772                 break;
4773         case RTE_ETH_FILTER_GET:
4774                 ret = ixgbe_syn_filter_get(dev,
4775                                 (struct rte_eth_syn_filter *)arg);
4776                 break;
4777         default:
4778                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4779                 ret = -EINVAL;
4780                 break;
4781         }
4782
4783         return ret;
4784 }
4785
4786
4787 static inline enum ixgbe_5tuple_protocol
4788 convert_protocol_type(uint8_t protocol_value)
4789 {
4790         if (protocol_value == IPPROTO_TCP)
4791                 return IXGBE_FILTER_PROTOCOL_TCP;
4792         else if (protocol_value == IPPROTO_UDP)
4793                 return IXGBE_FILTER_PROTOCOL_UDP;
4794         else if (protocol_value == IPPROTO_SCTP)
4795                 return IXGBE_FILTER_PROTOCOL_SCTP;
4796         else
4797                 return IXGBE_FILTER_PROTOCOL_NONE;
4798 }
4799
4800 /*
4801  * add a 5tuple filter
4802  *
4803  * @param
4804  * dev: Pointer to struct rte_eth_dev.
4805  * index: the index the filter allocates.
4806  * filter: ponter to the filter that will be added.
4807  * rx_queue: the queue id the filter assigned to.
4808  *
4809  * @return
4810  *    - On success, zero.
4811  *    - On failure, a negative value.
4812  */
4813 static int
4814 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4815                         struct ixgbe_5tuple_filter *filter)
4816 {
4817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4818         struct ixgbe_filter_info *filter_info =
4819                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4820         int i, idx, shift;
4821         uint32_t ftqf, sdpqf;
4822         uint32_t l34timir = 0;
4823         uint8_t mask = 0xff;
4824
4825         /*
4826          * look for an unused 5tuple filter index,
4827          * and insert the filter to list.
4828          */
4829         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4830                 idx = i / (sizeof(uint32_t) * NBBY);
4831                 shift = i % (sizeof(uint32_t) * NBBY);
4832                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
4833                         filter_info->fivetuple_mask[idx] |= 1 << shift;
4834                         filter->index = i;
4835                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4836                                           filter,
4837                                           entries);
4838                         break;
4839                 }
4840         }
4841         if (i >= IXGBE_MAX_FTQF_FILTERS) {
4842                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4843                 return -ENOSYS;
4844         }
4845
4846         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
4847                                 IXGBE_SDPQF_DSTPORT_SHIFT);
4848         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
4849
4850         ftqf = (uint32_t)(filter->filter_info.proto &
4851                 IXGBE_FTQF_PROTOCOL_MASK);
4852         ftqf |= (uint32_t)((filter->filter_info.priority &
4853                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
4854         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
4855                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
4856         if (filter->filter_info.dst_ip_mask == 0)
4857                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
4858         if (filter->filter_info.src_port_mask == 0)
4859                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
4860         if (filter->filter_info.dst_port_mask == 0)
4861                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
4862         if (filter->filter_info.proto_mask == 0)
4863                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
4864         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
4865         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
4866         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
4867
4868         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
4869         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
4870         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
4871         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
4872
4873         l34timir |= IXGBE_L34T_IMIR_RESERVE;
4874         l34timir |= (uint32_t)(filter->queue <<
4875                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
4876         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
4877         return 0;
4878 }
4879
4880 /*
4881  * remove a 5tuple filter
4882  *
4883  * @param
4884  * dev: Pointer to struct rte_eth_dev.
4885  * filter: the pointer of the filter will be removed.
4886  */
4887 static void
4888 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
4889                         struct ixgbe_5tuple_filter *filter)
4890 {
4891         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4892         struct ixgbe_filter_info *filter_info =
4893                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4894         uint16_t index = filter->index;
4895
4896         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
4897                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
4898         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4899         rte_free(filter);
4900
4901         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4902         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4903         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4904         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4905         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4906 }
4907
4908 static int
4909 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4910 {
4911         struct ixgbe_hw *hw;
4912         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4913
4914         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4915
4916         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4917                 return -EINVAL;
4918
4919         /* refuse mtu that requires the support of scattered packets when this
4920          * feature has not been enabled before. */
4921         if (!dev->data->scattered_rx &&
4922             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4923              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4924                 return -EINVAL;
4925
4926         /*
4927          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4928          * request of the version 2.0 of the mailbox API.
4929          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4930          * of the mailbox API.
4931          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4932          * prior to 3.11.33 which contains the following change:
4933          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4934          */
4935         ixgbevf_rlpml_set_vf(hw, max_frame);
4936
4937         /* update max frame size */
4938         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4939         return 0;
4940 }
4941
4942 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
4943         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4944                 return -ENOTSUP;\
4945 } while (0)
4946
4947 static inline struct ixgbe_5tuple_filter *
4948 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4949                         struct ixgbe_5tuple_filter_info *key)
4950 {
4951         struct ixgbe_5tuple_filter *it;
4952
4953         TAILQ_FOREACH(it, filter_list, entries) {
4954                 if (memcmp(key, &it->filter_info,
4955                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4956                         return it;
4957                 }
4958         }
4959         return NULL;
4960 }
4961
4962 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4963 static inline int
4964 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4965                         struct ixgbe_5tuple_filter_info *filter_info)
4966 {
4967         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4968                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4969                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4970                 return -EINVAL;
4971
4972         switch (filter->dst_ip_mask) {
4973         case UINT32_MAX:
4974                 filter_info->dst_ip_mask = 0;
4975                 filter_info->dst_ip = filter->dst_ip;
4976                 break;
4977         case 0:
4978                 filter_info->dst_ip_mask = 1;
4979                 break;
4980         default:
4981                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4982                 return -EINVAL;
4983         }
4984
4985         switch (filter->src_ip_mask) {
4986         case UINT32_MAX:
4987                 filter_info->src_ip_mask = 0;
4988                 filter_info->src_ip = filter->src_ip;
4989                 break;
4990         case 0:
4991                 filter_info->src_ip_mask = 1;
4992                 break;
4993         default:
4994                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4995                 return -EINVAL;
4996         }
4997
4998         switch (filter->dst_port_mask) {
4999         case UINT16_MAX:
5000                 filter_info->dst_port_mask = 0;
5001                 filter_info->dst_port = filter->dst_port;
5002                 break;
5003         case 0:
5004                 filter_info->dst_port_mask = 1;
5005                 break;
5006         default:
5007                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5008                 return -EINVAL;
5009         }
5010
5011         switch (filter->src_port_mask) {
5012         case UINT16_MAX:
5013                 filter_info->src_port_mask = 0;
5014                 filter_info->src_port = filter->src_port;
5015                 break;
5016         case 0:
5017                 filter_info->src_port_mask = 1;
5018                 break;
5019         default:
5020                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5021                 return -EINVAL;
5022         }
5023
5024         switch (filter->proto_mask) {
5025         case UINT8_MAX:
5026                 filter_info->proto_mask = 0;
5027                 filter_info->proto =
5028                         convert_protocol_type(filter->proto);
5029                 break;
5030         case 0:
5031                 filter_info->proto_mask = 1;
5032                 break;
5033         default:
5034                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5035                 return -EINVAL;
5036         }
5037
5038         filter_info->priority = (uint8_t)filter->priority;
5039         return 0;
5040 }
5041
5042 /*
5043  * add or delete a ntuple filter
5044  *
5045  * @param
5046  * dev: Pointer to struct rte_eth_dev.
5047  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5048  * add: if true, add filter, if false, remove filter
5049  *
5050  * @return
5051  *    - On success, zero.
5052  *    - On failure, a negative value.
5053  */
5054 static int
5055 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5056                         struct rte_eth_ntuple_filter *ntuple_filter,
5057                         bool add)
5058 {
5059         struct ixgbe_filter_info *filter_info =
5060                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5061         struct ixgbe_5tuple_filter_info filter_5tuple;
5062         struct ixgbe_5tuple_filter *filter;
5063         int ret;
5064
5065         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5066                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5067                 return -EINVAL;
5068         }
5069
5070         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5071         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5072         if (ret < 0)
5073                 return ret;
5074
5075         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5076                                          &filter_5tuple);
5077         if (filter != NULL && add) {
5078                 PMD_DRV_LOG(ERR, "filter exists.");
5079                 return -EEXIST;
5080         }
5081         if (filter == NULL && !add) {
5082                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5083                 return -ENOENT;
5084         }
5085
5086         if (add) {
5087                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5088                                 sizeof(struct ixgbe_5tuple_filter), 0);
5089                 if (filter == NULL)
5090                         return -ENOMEM;
5091                 (void)rte_memcpy(&filter->filter_info,
5092                                  &filter_5tuple,
5093                                  sizeof(struct ixgbe_5tuple_filter_info));
5094                 filter->queue = ntuple_filter->queue;
5095                 ret = ixgbe_add_5tuple_filter(dev, filter);
5096                 if (ret < 0) {
5097                         rte_free(filter);
5098                         return ret;
5099                 }
5100         } else
5101                 ixgbe_remove_5tuple_filter(dev, filter);
5102
5103         return 0;
5104 }
5105
5106 /*
5107  * get a ntuple filter
5108  *
5109  * @param
5110  * dev: Pointer to struct rte_eth_dev.
5111  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5112  *
5113  * @return
5114  *    - On success, zero.
5115  *    - On failure, a negative value.
5116  */
5117 static int
5118 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5119                         struct rte_eth_ntuple_filter *ntuple_filter)
5120 {
5121         struct ixgbe_filter_info *filter_info =
5122                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5123         struct ixgbe_5tuple_filter_info filter_5tuple;
5124         struct ixgbe_5tuple_filter *filter;
5125         int ret;
5126
5127         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5128                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5129                 return -EINVAL;
5130         }
5131
5132         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5133         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5134         if (ret < 0)
5135                 return ret;
5136
5137         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5138                                          &filter_5tuple);
5139         if (filter == NULL) {
5140                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5141                 return -ENOENT;
5142         }
5143         ntuple_filter->queue = filter->queue;
5144         return 0;
5145 }
5146
5147 /*
5148  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5149  * @dev: pointer to rte_eth_dev structure
5150  * @filter_op:operation will be taken.
5151  * @arg: a pointer to specific structure corresponding to the filter_op
5152  *
5153  * @return
5154  *    - On success, zero.
5155  *    - On failure, a negative value.
5156  */
5157 static int
5158 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5159                                 enum rte_filter_op filter_op,
5160                                 void *arg)
5161 {
5162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5163         int ret;
5164
5165         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5166
5167         if (filter_op == RTE_ETH_FILTER_NOP)
5168                 return 0;
5169
5170         if (arg == NULL) {
5171                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5172                             filter_op);
5173                 return -EINVAL;
5174         }
5175
5176         switch (filter_op) {
5177         case RTE_ETH_FILTER_ADD:
5178                 ret = ixgbe_add_del_ntuple_filter(dev,
5179                         (struct rte_eth_ntuple_filter *)arg,
5180                         TRUE);
5181                 break;
5182         case RTE_ETH_FILTER_DELETE:
5183                 ret = ixgbe_add_del_ntuple_filter(dev,
5184                         (struct rte_eth_ntuple_filter *)arg,
5185                         FALSE);
5186                 break;
5187         case RTE_ETH_FILTER_GET:
5188                 ret = ixgbe_get_ntuple_filter(dev,
5189                         (struct rte_eth_ntuple_filter *)arg);
5190                 break;
5191         default:
5192                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5193                 ret = -EINVAL;
5194                 break;
5195         }
5196         return ret;
5197 }
5198
5199 static inline int
5200 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5201                         uint16_t ethertype)
5202 {
5203         int i;
5204
5205         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5206                 if (filter_info->ethertype_filters[i] == ethertype &&
5207                     (filter_info->ethertype_mask & (1 << i)))
5208                         return i;
5209         }
5210         return -1;
5211 }
5212
5213 static inline int
5214 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5215                         uint16_t ethertype)
5216 {
5217         int i;
5218
5219         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5220                 if (!(filter_info->ethertype_mask & (1 << i))) {
5221                         filter_info->ethertype_mask |= 1 << i;
5222                         filter_info->ethertype_filters[i] = ethertype;
5223                         return i;
5224                 }
5225         }
5226         return -1;
5227 }
5228
5229 static inline int
5230 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5231                         uint8_t idx)
5232 {
5233         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5234                 return -1;
5235         filter_info->ethertype_mask &= ~(1 << idx);
5236         filter_info->ethertype_filters[idx] = 0;
5237         return idx;
5238 }
5239
5240 static int
5241 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5242                         struct rte_eth_ethertype_filter *filter,
5243                         bool add)
5244 {
5245         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5246         struct ixgbe_filter_info *filter_info =
5247                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5248         uint32_t etqf = 0;
5249         uint32_t etqs = 0;
5250         int ret;
5251
5252         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5253                 return -EINVAL;
5254
5255         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5256                 filter->ether_type == ETHER_TYPE_IPv6) {
5257                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5258                         " ethertype filter.", filter->ether_type);
5259                 return -EINVAL;
5260         }
5261
5262         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5263                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5264                 return -EINVAL;
5265         }
5266         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5267                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5268                 return -EINVAL;
5269         }
5270
5271         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5272         if (ret >= 0 && add) {
5273                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5274                             filter->ether_type);
5275                 return -EEXIST;
5276         }
5277         if (ret < 0 && !add) {
5278                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5279                             filter->ether_type);
5280                 return -ENOENT;
5281         }
5282
5283         if (add) {
5284                 ret = ixgbe_ethertype_filter_insert(filter_info,
5285                         filter->ether_type);
5286                 if (ret < 0) {
5287                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5288                         return -ENOSYS;
5289                 }
5290                 etqf = IXGBE_ETQF_FILTER_EN;
5291                 etqf |= (uint32_t)filter->ether_type;
5292                 etqs |= (uint32_t)((filter->queue <<
5293                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5294                                     IXGBE_ETQS_RX_QUEUE);
5295                 etqs |= IXGBE_ETQS_QUEUE_EN;
5296         } else {
5297                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5298                 if (ret < 0)
5299                         return -ENOSYS;
5300         }
5301         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5302         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5303         IXGBE_WRITE_FLUSH(hw);
5304
5305         return 0;
5306 }
5307
5308 static int
5309 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5310                         struct rte_eth_ethertype_filter *filter)
5311 {
5312         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5313         struct ixgbe_filter_info *filter_info =
5314                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5315         uint32_t etqf, etqs;
5316         int ret;
5317
5318         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5319         if (ret < 0) {
5320                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5321                             filter->ether_type);
5322                 return -ENOENT;
5323         }
5324
5325         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5326         if (etqf & IXGBE_ETQF_FILTER_EN) {
5327                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5328                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5329                 filter->flags = 0;
5330                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5331                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5332                 return 0;
5333         }
5334         return -ENOENT;
5335 }
5336
5337 /*
5338  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5339  * @dev: pointer to rte_eth_dev structure
5340  * @filter_op:operation will be taken.
5341  * @arg: a pointer to specific structure corresponding to the filter_op
5342  */
5343 static int
5344 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5345                                 enum rte_filter_op filter_op,
5346                                 void *arg)
5347 {
5348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5349         int ret;
5350
5351         MAC_TYPE_FILTER_SUP(hw->mac.type);
5352
5353         if (filter_op == RTE_ETH_FILTER_NOP)
5354                 return 0;
5355
5356         if (arg == NULL) {
5357                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5358                             filter_op);
5359                 return -EINVAL;
5360         }
5361
5362         switch (filter_op) {
5363         case RTE_ETH_FILTER_ADD:
5364                 ret = ixgbe_add_del_ethertype_filter(dev,
5365                         (struct rte_eth_ethertype_filter *)arg,
5366                         TRUE);
5367                 break;
5368         case RTE_ETH_FILTER_DELETE:
5369                 ret = ixgbe_add_del_ethertype_filter(dev,
5370                         (struct rte_eth_ethertype_filter *)arg,
5371                         FALSE);
5372                 break;
5373         case RTE_ETH_FILTER_GET:
5374                 ret = ixgbe_get_ethertype_filter(dev,
5375                         (struct rte_eth_ethertype_filter *)arg);
5376                 break;
5377         default:
5378                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5379                 ret = -EINVAL;
5380                 break;
5381         }
5382         return ret;
5383 }
5384
5385 static int
5386 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5387                      enum rte_filter_type filter_type,
5388                      enum rte_filter_op filter_op,
5389                      void *arg)
5390 {
5391         int ret = -EINVAL;
5392
5393         switch (filter_type) {
5394         case RTE_ETH_FILTER_NTUPLE:
5395                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5396                 break;
5397         case RTE_ETH_FILTER_ETHERTYPE:
5398                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5399                 break;
5400         case RTE_ETH_FILTER_SYN:
5401                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5402                 break;
5403         case RTE_ETH_FILTER_FDIR:
5404                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5405                 break;
5406         default:
5407                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5408                                                         filter_type);
5409                 break;
5410         }
5411
5412         return ret;
5413 }
5414
5415 static u8 *
5416 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5417                         u8 **mc_addr_ptr, u32 *vmdq)
5418 {
5419         u8 *mc_addr;
5420
5421         *vmdq = 0;
5422         mc_addr = *mc_addr_ptr;
5423         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5424         return mc_addr;
5425 }
5426
5427 static int
5428 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5429                           struct ether_addr *mc_addr_set,
5430                           uint32_t nb_mc_addr)
5431 {
5432         struct ixgbe_hw *hw;
5433         u8 *mc_addr_list;
5434
5435         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5436         mc_addr_list = (u8 *)mc_addr_set;
5437         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5438                                          ixgbe_dev_addr_list_itr, TRUE);
5439 }
5440
5441 static int
5442 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5443 {
5444         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5445         uint32_t tsync_ctl;
5446         uint32_t tsauxc;
5447
5448         /* Enable system time for platforms where it isn't on by default. */
5449         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5450         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5451         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5452
5453         /* Start incrementing the register used to timestamp PTP packets. */
5454         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5455
5456         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5457         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5458                         (ETHER_TYPE_1588 |
5459                          IXGBE_ETQF_FILTER_EN |
5460                          IXGBE_ETQF_1588));
5461
5462         /* Enable timestamping of received PTP packets. */
5463         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5464         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5465         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5466
5467         /* Enable timestamping of transmitted PTP packets. */
5468         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5469         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5470         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5471
5472         return 0;
5473 }
5474
5475 static int
5476 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5477 {
5478         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5479         uint32_t tsync_ctl;
5480
5481         /* Disable timestamping of transmitted PTP packets. */
5482         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5483         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5484         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5485
5486         /* Disable timestamping of received PTP packets. */
5487         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5488         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5489         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5490
5491         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5492         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5493
5494         /* Stop incrementating the System Time registers. */
5495         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5496
5497         return 0;
5498 }
5499
5500 static int
5501 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5502                                  struct timespec *timestamp,
5503                                  uint32_t flags __rte_unused)
5504 {
5505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5506         uint32_t tsync_rxctl;
5507         uint32_t rx_stmpl;
5508         uint32_t rx_stmph;
5509
5510         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5511         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5512                 return -EINVAL;
5513
5514         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5515         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5516
5517         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5518         timestamp->tv_nsec = 0;
5519
5520         return  0;
5521 }
5522
5523 static int
5524 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5525                                  struct timespec *timestamp)
5526 {
5527         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5528         uint32_t tsync_txctl;
5529         uint32_t tx_stmpl;
5530         uint32_t tx_stmph;
5531
5532         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5533         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5534                 return -EINVAL;
5535
5536         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5537         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5538
5539         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5540         timestamp->tv_nsec = 0;
5541
5542         return  0;
5543 }
5544
5545 static int
5546 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5547 {
5548         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5549         int count = 0;
5550         int g_ind = 0;
5551         const struct reg_info *reg_group;
5552         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5553                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5554
5555         while ((reg_group = reg_set[g_ind++]))
5556                 count += ixgbe_regs_group_count(reg_group);
5557
5558         return count;
5559 }
5560
5561 static int
5562 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5563 {
5564         int count = 0;
5565         int g_ind = 0;
5566         const struct reg_info *reg_group;
5567
5568         while ((reg_group = ixgbevf_regs[g_ind++]))
5569                 count += ixgbe_regs_group_count(reg_group);
5570
5571         return count;
5572 }
5573
5574 static int
5575 ixgbe_get_regs(struct rte_eth_dev *dev,
5576               struct rte_dev_reg_info *regs)
5577 {
5578         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5579         uint32_t *data = regs->data;
5580         int g_ind = 0;
5581         int count = 0;
5582         const struct reg_info *reg_group;
5583         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5584                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5585
5586         /* Support only full register dump */
5587         if ((regs->length == 0) ||
5588             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5589                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5590                         hw->device_id;
5591                 while ((reg_group = reg_set[g_ind++]))
5592                         count += ixgbe_read_regs_group(dev, &data[count],
5593                                 reg_group);
5594                 return 0;
5595         }
5596
5597         return -ENOTSUP;
5598 }
5599
5600 static int
5601 ixgbevf_get_regs(struct rte_eth_dev *dev,
5602                 struct rte_dev_reg_info *regs)
5603 {
5604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5605         uint32_t *data = regs->data;
5606         int g_ind = 0;
5607         int count = 0;
5608         const struct reg_info *reg_group;
5609
5610         /* Support only full register dump */
5611         if ((regs->length == 0) ||
5612             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5613                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5614                         hw->device_id;
5615                 while ((reg_group = ixgbevf_regs[g_ind++]))
5616                         count += ixgbe_read_regs_group(dev, &data[count],
5617                                                       reg_group);
5618                 return 0;
5619         }
5620
5621         return -ENOTSUP;
5622 }
5623
5624 static int
5625 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5626 {
5627         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5628
5629         /* Return unit is byte count */
5630         return hw->eeprom.word_size * 2;
5631 }
5632
5633 static int
5634 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5635                 struct rte_dev_eeprom_info *in_eeprom)
5636 {
5637         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5638         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5639         uint16_t *data = in_eeprom->data;
5640         int first, length;
5641
5642         first = in_eeprom->offset >> 1;
5643         length = in_eeprom->length >> 1;
5644         if ((first > hw->eeprom.word_size) ||
5645             ((first + length) > hw->eeprom.word_size))
5646                 return -EINVAL;
5647
5648         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5649
5650         return eeprom->ops.read_buffer(hw, first, length, data);
5651 }
5652
5653 static int
5654 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5655                 struct rte_dev_eeprom_info *in_eeprom)
5656 {
5657         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5658         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5659         uint16_t *data = in_eeprom->data;
5660         int first, length;
5661
5662         first = in_eeprom->offset >> 1;
5663         length = in_eeprom->length >> 1;
5664         if ((first > hw->eeprom.word_size) ||
5665             ((first + length) > hw->eeprom.word_size))
5666                 return -EINVAL;
5667
5668         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5669
5670         return eeprom->ops.write_buffer(hw,  first, length, data);
5671 }
5672
5673 uint16_t
5674 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5675         switch (mac_type) {
5676         case ixgbe_mac_X550:
5677         case ixgbe_mac_X550EM_x:
5678                 return ETH_RSS_RETA_SIZE_512;
5679         case ixgbe_mac_X550_vf:
5680         case ixgbe_mac_X550EM_x_vf:
5681                 return ETH_RSS_RETA_SIZE_64;
5682         default:
5683                 return ETH_RSS_RETA_SIZE_128;
5684         }
5685 }
5686
5687 uint32_t
5688 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5689         switch (mac_type) {
5690         case ixgbe_mac_X550:
5691         case ixgbe_mac_X550EM_x:
5692                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5693                         return IXGBE_RETA(reta_idx >> 2);
5694                 else
5695                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5696         case ixgbe_mac_X550_vf:
5697         case ixgbe_mac_X550EM_x_vf:
5698                 return IXGBE_VFRETA(reta_idx >> 2);
5699         default:
5700                 return IXGBE_RETA(reta_idx >> 2);
5701         }
5702 }
5703
5704 uint32_t
5705 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5706         switch (mac_type) {
5707         case ixgbe_mac_X550_vf:
5708         case ixgbe_mac_X550EM_x_vf:
5709                 return IXGBE_VFMRQC;
5710         default:
5711                 return IXGBE_MRQC;
5712         }
5713 }
5714
5715 uint32_t
5716 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5717         switch (mac_type) {
5718         case ixgbe_mac_X550_vf:
5719         case ixgbe_mac_X550EM_x_vf:
5720                 return IXGBE_VFRSSRK(i);
5721         default:
5722                 return IXGBE_RSSRK(i);
5723         }
5724 }
5725
5726 bool
5727 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5728         switch (mac_type) {
5729         case ixgbe_mac_82599_vf:
5730         case ixgbe_mac_X540_vf:
5731                 return 0;
5732         default:
5733                 return 1;
5734         }
5735 }
5736
5737
5738 static struct rte_driver rte_ixgbe_driver = {
5739         .type = PMD_PDEV,
5740         .init = rte_ixgbe_pmd_init,
5741 };
5742
5743 static struct rte_driver rte_ixgbevf_driver = {
5744         .type = PMD_PDEV,
5745         .init = rte_ixgbevf_pmd_init,
5746 };
5747
5748 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5749 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);