drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 /* Additional timesync values. */
 104 #define NSEC_PER_SEC             1000000000L
 105 #define IXGBE_INCVAL_10GB        0x66666666
 106 #define IXGBE_INCVAL_1GB         0x40000000
 107 #define IXGBE_INCVAL_100         0x50000000
 108 #define IXGBE_INCVAL_SHIFT_10GB  28
 109 #define IXGBE_INCVAL_SHIFT_1GB   24
 110 #define IXGBE_INCVAL_SHIFT_100   21
 111 #define IXGBE_INCVAL_SHIFT_82599 7
 112 #define IXGBE_INCPER_SHIFT_82599 24
 113
 114 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 117 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 118 #define IXGBE_ETAG_ETYPE                       0x00005084
 119 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 120 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 121 #define IXGBE_RAH_ADTYPE                       0x40000000
 122 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 123 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 124 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 125 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 126 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 127 #define IXGBE_VTEICR_MASK                      0x07
 128
 129 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 130 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 131
 132 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 133 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 151                                 int wait_to_complete);
 152 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 153                                 struct rte_eth_stats *stats);
 154 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 155                                 struct rte_eth_xstat *xstats, unsigned n);
 156 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 157                                   struct rte_eth_xstat *xstats, unsigned n);
 158 static int
 159 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 160                 uint64_t *values, unsigned int n);
 161 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 163 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names,
 165         unsigned int size);
 166 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 168 static int ixgbe_dev_xstats_get_names_by_id(
 169         struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         const uint64_t *ids,
 172         unsigned int limit);
 173 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 174                                              uint16_t queue_id,
 175                                              uint8_t stat_idx,
 176                                              uint8_t is_rx);
 177 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 178                                  size_t fw_size);
 179 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 180                                struct rte_eth_dev_info *dev_info);
 181 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 182 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 183                                  struct rte_eth_dev_info *dev_info);
 184 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 185
 186 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 187                 uint16_t vlan_id, int on);
 188 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 189                                enum rte_vlan_type vlan_type,
 190                                uint16_t tpid_id);
 191 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 192                 uint16_t queue, bool on);
 193 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 194                 int on);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 221                                       struct rte_intr_handle *handle);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 225                          uint32_t index, uint32_t pool);
 226 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 227 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 228                                            struct ether_addr *mac_addr);
 229 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 230 static bool is_device_supported(struct rte_eth_dev *dev,
 231                                 struct rte_pci_driver *drv);
 232
 233 /* For Virtual Function support */
 234 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 235 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 236 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 237 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 238 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 239                                    int wait_to_complete);
 240 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 242 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 245 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 255                                             uint16_t queue_id);
 256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 257                                              uint16_t queue_id);
 258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 259                                  uint8_t queue, uint8_t msix_vector);
 260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 263
 264 /* For Eth VMDQ APIs support */
 265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 266                 ether_addr * mac_addr, uint8_t on);
 267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 268 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 269                 struct rte_eth_mirror_conf *mirror_conf,
 270                 uint8_t rule_id, uint8_t on);
 271 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 272                 uint8_t rule_id);
 273 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 274                                           uint16_t queue_id);
 275 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 276                                            uint16_t queue_id);
 277 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 278                                uint8_t queue, uint8_t msix_vector);
 279 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 280
 281 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 282                                 struct ether_addr *mac_addr,
 283                                 uint32_t index, uint32_t pool);
 284 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 285 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 286                                              struct ether_addr *mac_addr);
 287 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 288                         struct rte_eth_syn_filter *filter);
 289 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 290                         enum rte_filter_op filter_op,
 291                         void *arg);
 292 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 293                         struct ixgbe_5tuple_filter *filter);
 294 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 295                         struct ixgbe_5tuple_filter *filter);
 296 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 297                                 enum rte_filter_op filter_op,
 298                                 void *arg);
 299 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 300                         struct rte_eth_ntuple_filter *filter);
 301 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 302                                 enum rte_filter_op filter_op,
 303                                 void *arg);
 304 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 305                         struct rte_eth_ethertype_filter *filter);
 306 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 307                      enum rte_filter_type filter_type,
 308                      enum rte_filter_op filter_op,
 309                      void *arg);
 310 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 311
 312 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 313                                       struct ether_addr *mc_addr_set,
 314                                       uint32_t nb_mc_addr);
 315 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 316                                    struct rte_eth_dcb_info *dcb_info);
 317
 318 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 319 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 320                             struct rte_dev_reg_info *regs);
 321 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 323                                 struct rte_dev_eeprom_info *eeprom);
 324 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 325                                 struct rte_dev_eeprom_info *eeprom);
 326
 327 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 328                                  struct rte_eth_dev_module_info *modinfo);
 329 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 330                                    struct rte_dev_eeprom_info *info);
 331
 332 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 334                                 struct rte_dev_reg_info *regs);
 335
 336 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 339                                             struct timespec *timestamp,
 340                                             uint32_t flags);
 341 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 342                                             struct timespec *timestamp);
 343 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 344 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 345                                    struct timespec *timestamp);
 346 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 347                                    const struct timespec *timestamp);
 348 static void ixgbevf_dev_interrupt_handler(void *param);
 349
 350 static int ixgbe_dev_l2_tunnel_eth_type_conf
 351         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 352 static int ixgbe_dev_l2_tunnel_offload_set
 353         (struct rte_eth_dev *dev,
 354          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 355          uint32_t mask,
 356          uint8_t en);
 357 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 358                                              enum rte_filter_op filter_op,
 359                                              void *arg);
 360
 361 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 364                                          struct rte_eth_udp_tunnel *udp_tunnel);
 365 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 366 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 367
 368 /*
 369  * Define VF Stats MACRO for Non "cleared on read" register
 370  */
 371 #define UPDATE_VF_STAT(reg, last, cur)                          \
 372 {                                                               \
 373         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 374         cur += (latest - last) & UINT_MAX;                      \
 375         last = latest;                                          \
 376 }
 377
 378 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 379 {                                                                \
 380         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 381         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 382         u64 latest = ((new_msb << 32) | new_lsb);                \
 383         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 384         last = latest;                                           \
 385 }
 386
 387 #define IXGBE_SET_HWSTRIP(h, q) do {\
 388                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 389                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 390                 (h)->bitmap[idx] |= 1 << bit;\
 391         } while (0)
 392
 393 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 394                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 395                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 396                 (h)->bitmap[idx] &= ~(1 << bit);\
 397         } while (0)
 398
 399 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 400                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 402                 (r) = (h)->bitmap[idx] >> bit & 1;\
 403         } while (0)
 404
 405 int ixgbe_logtype_init;
 406 int ixgbe_logtype_driver;
 407
 408 /*
 409  * The set of PCI devices this driver supports
 410  */
 411 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 460 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 462 #endif
 463         { .vendor_id = 0, /* sentinel */ },
 464 };
 465
 466 /*
 467  * The set of PCI devices this driver supports (for 82599 VF)
 468  */
 469 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 480         { .vendor_id = 0, /* sentinel */ },
 481 };
 482
 483 static const struct rte_eth_desc_lim rx_desc_lim = {
 484         .nb_max = IXGBE_MAX_RING_DESC,
 485         .nb_min = IXGBE_MIN_RING_DESC,
 486         .nb_align = IXGBE_RXD_ALIGN,
 487 };
 488
 489 static const struct rte_eth_desc_lim tx_desc_lim = {
 490         .nb_max = IXGBE_MAX_RING_DESC,
 491         .nb_min = IXGBE_MIN_RING_DESC,
 492         .nb_align = IXGBE_TXD_ALIGN,
 493         .nb_seg_max = IXGBE_TX_MAX_SEG,
 494         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 495 };
 496
 497 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 498         .dev_configure        = ixgbe_dev_configure,
 499         .dev_start            = ixgbe_dev_start,
 500         .dev_stop             = ixgbe_dev_stop,
 501         .dev_set_link_up    = ixgbe_dev_set_link_up,
 502         .dev_set_link_down  = ixgbe_dev_set_link_down,
 503         .dev_close            = ixgbe_dev_close,
 504         .dev_reset            = ixgbe_dev_reset,
 505         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 506         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 507         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 508         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 509         .link_update          = ixgbe_dev_link_update,
 510         .stats_get            = ixgbe_dev_stats_get,
 511         .xstats_get           = ixgbe_dev_xstats_get,
 512         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 513         .stats_reset          = ixgbe_dev_stats_reset,
 514         .xstats_reset         = ixgbe_dev_xstats_reset,
 515         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 516         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 517         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 518         .fw_version_get       = ixgbe_fw_version_get,
 519         .dev_infos_get        = ixgbe_dev_info_get,
 520         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 521         .mtu_set              = ixgbe_dev_mtu_set,
 522         .vlan_filter_set      = ixgbe_vlan_filter_set,
 523         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 524         .vlan_offload_set     = ixgbe_vlan_offload_set,
 525         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 526         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 527         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 528         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 529         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 530         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 531         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 532         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 533         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 534         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 535         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 536         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 537         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 538         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 539         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 540         .dev_led_on           = ixgbe_dev_led_on,
 541         .dev_led_off          = ixgbe_dev_led_off,
 542         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 543         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 544         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 545         .mac_addr_add         = ixgbe_add_rar,
 546         .mac_addr_remove      = ixgbe_remove_rar,
 547         .mac_addr_set         = ixgbe_set_default_mac_addr,
 548         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 549         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 550         .mirror_rule_set      = ixgbe_mirror_rule_set,
 551         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 552         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 553         .reta_update          = ixgbe_dev_rss_reta_update,
 554         .reta_query           = ixgbe_dev_rss_reta_query,
 555         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 556         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 557         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 558         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 559         .rxq_info_get         = ixgbe_rxq_info_get,
 560         .txq_info_get         = ixgbe_txq_info_get,
 561         .timesync_enable      = ixgbe_timesync_enable,
 562         .timesync_disable     = ixgbe_timesync_disable,
 563         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 564         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 565         .get_reg              = ixgbe_get_regs,
 566         .get_eeprom_length    = ixgbe_get_eeprom_length,
 567         .get_eeprom           = ixgbe_get_eeprom,
 568         .set_eeprom           = ixgbe_set_eeprom,
 569         .get_module_info      = ixgbe_get_module_info,
 570         .get_module_eeprom    = ixgbe_get_module_eeprom,
 571         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 572         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 573         .timesync_read_time   = ixgbe_timesync_read_time,
 574         .timesync_write_time  = ixgbe_timesync_write_time,
 575         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 576         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 577         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 578         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 579         .tm_ops_get           = ixgbe_tm_ops_get,
 580 };
 581
 582 /*
 583  * dev_ops for virtual function, bare necessities for basic vf
 584  * operation have been implemented
 585  */
 586 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 587         .dev_configure        = ixgbevf_dev_configure,
 588         .dev_start            = ixgbevf_dev_start,
 589         .dev_stop             = ixgbevf_dev_stop,
 590         .link_update          = ixgbevf_dev_link_update,
 591         .stats_get            = ixgbevf_dev_stats_get,
 592         .xstats_get           = ixgbevf_dev_xstats_get,
 593         .stats_reset          = ixgbevf_dev_stats_reset,
 594         .xstats_reset         = ixgbevf_dev_stats_reset,
 595         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 596         .dev_close            = ixgbevf_dev_close,
 597         .dev_reset            = ixgbevf_dev_reset,
 598         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 599         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 600         .dev_infos_get        = ixgbevf_dev_info_get,
 601         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 602         .mtu_set              = ixgbevf_dev_set_mtu,
 603         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 604         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 605         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 606         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 607         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 608         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 609         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 610         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 611         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 612         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 613         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 614         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 615         .mac_addr_add         = ixgbevf_add_mac_addr,
 616         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 617         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 618         .rxq_info_get         = ixgbe_rxq_info_get,
 619         .txq_info_get         = ixgbe_txq_info_get,
 620         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 621         .get_reg              = ixgbevf_get_regs,
 622         .reta_update          = ixgbe_dev_rss_reta_update,
 623         .reta_query           = ixgbe_dev_rss_reta_query,
 624         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 625         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 626 };
 627
 628 /* store statistics names and its offset in stats structure */
 629 struct rte_ixgbe_xstats_name_off {
 630         char name[RTE_ETH_XSTATS_NAME_SIZE];
 631         unsigned offset;
 632 };
 633
 634 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 635         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 636         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 637         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 638         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 639         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 640         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 641         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 642         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 643         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 644         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 645         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 646         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 647         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 648         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 649         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 650                 prc1023)},
 651         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 652                 prc1522)},
 653         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 654         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 655         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 656         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 657         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 658         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 659         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 660         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 661         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 662         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 663         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 664         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 665         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 666         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 667         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 668         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 669         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 670                 ptc1023)},
 671         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 672                 ptc1522)},
 673         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 674         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 675         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 676         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 677
 678         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 679                 fdirustat_add)},
 680         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 681                 fdirustat_remove)},
 682         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 683                 fdirfstat_fadd)},
 684         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 685                 fdirfstat_fremove)},
 686         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 687                 fdirmatch)},
 688         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 689                 fdirmiss)},
 690
 691         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 692         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 693         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 694                 fclast)},
 695         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 696         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 697         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 698         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 699         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 700                 fcoe_noddp)},
 701         {"rx_fcoe_no_direct_data_placement_ext_buff",
 702                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 703
 704         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxontxc)},
 706         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxonrxc)},
 708         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 709                 lxofftxc)},
 710         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 711                 lxoffrxc)},
 712         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 713 };
 714
 715 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 716                            sizeof(rte_ixgbe_stats_strings[0]))
 717
 718 /* MACsec statistics */
 719 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 720         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_untagged)},
 722         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_pkts_encrypted)},
 724         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_pkts_protected)},
 726         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 727                 out_octets_encrypted)},
 728         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 729                 out_octets_protected)},
 730         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_untagged)},
 732         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_badtag)},
 734         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 735                 in_pkts_nosci)},
 736         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_unknownsci)},
 738         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 739                 in_octets_decrypted)},
 740         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 741                 in_octets_validated)},
 742         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_unchecked)},
 744         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_delayed)},
 746         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_late)},
 748         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_ok)},
 750         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_invalid)},
 752         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notvalid)},
 754         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_unusedsa)},
 756         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_notusingsa)},
 758 };
 759
 760 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 761                            sizeof(rte_ixgbe_macsec_strings[0]))
 762
 763 /* Per-queue statistics */
 764 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 765         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 766         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 767         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 768         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 769 };
 770
 771 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 772                            sizeof(rte_ixgbe_rxq_strings[0]))
 773 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 774
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 776         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 777         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 778         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 779                 pxon2offc)},
 780 };
 781
 782 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 783                            sizeof(rte_ixgbe_txq_strings[0]))
 784 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 785
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 787         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 788 };
 789
 790 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 791                 sizeof(rte_ixgbevf_stats_strings[0]))
 792
 793 /*
 794  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 795  */
 796 static inline int
 797 ixgbe_is_sfp(struct ixgbe_hw *hw)
 798 {
 799         switch (hw->phy.type) {
 800         case ixgbe_phy_sfp_avago:
 801         case ixgbe_phy_sfp_ftl:
 802         case ixgbe_phy_sfp_intel:
 803         case ixgbe_phy_sfp_unknown:
 804         case ixgbe_phy_sfp_passive_tyco:
 805         case ixgbe_phy_sfp_passive_unknown:
 806                 return 1;
 807         default:
 808                 return 0;
 809         }
 810 }
 811
 812 static inline int32_t
 813 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 814 {
 815         uint32_t ctrl_ext;
 816         int32_t status;
 817
 818         status = ixgbe_reset_hw(hw);
 819
 820         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 821         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 822         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 823         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 824         IXGBE_WRITE_FLUSH(hw);
 825
 826         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 827                 status = IXGBE_SUCCESS;
 828         return status;
 829 }
 830
 831 static inline void
 832 ixgbe_enable_intr(struct rte_eth_dev *dev)
 833 {
 834         struct ixgbe_interrupt *intr =
 835                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 836         struct ixgbe_hw *hw =
 837                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 838
 839         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 840         IXGBE_WRITE_FLUSH(hw);
 841 }
 842
 843 /*
 844  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 845  */
 846 static void
 847 ixgbe_disable_intr(struct ixgbe_hw *hw)
 848 {
 849         PMD_INIT_FUNC_TRACE();
 850
 851         if (hw->mac.type == ixgbe_mac_82598EB) {
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 853         } else {
 854                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 857         }
 858         IXGBE_WRITE_FLUSH(hw);
 859 }
 860
 861 /*
 862  * This function resets queue statistics mapping registers.
 863  * From Niantic datasheet, Initialization of Statistics section:
 864  * "...if software requires the queue counters, the RQSMR and TQSM registers
 865  * must be re-programmed following a device reset.
 866  */
 867 static void
 868 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 869 {
 870         uint32_t i;
 871
 872         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 873                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 874                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 875         }
 876 }
 877
 878
 879 static int
 880 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 881                                   uint16_t queue_id,
 882                                   uint8_t stat_idx,
 883                                   uint8_t is_rx)
 884 {
 885 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 886 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 887 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 888
 889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 890         struct ixgbe_stat_mapping_registers *stat_mappings =
 891                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 892         uint32_t qsmr_mask = 0;
 893         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 894         uint32_t q_map;
 895         uint8_t n, offset;
 896
 897         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 898                 (hw->mac.type != ixgbe_mac_X540) &&
 899                 (hw->mac.type != ixgbe_mac_X550) &&
 900                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_a))
 902                 return -ENOSYS;
 903
 904         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 905                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 906                      queue_id, stat_idx);
 907
 908         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 909         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 910                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 911                 return -EIO;
 912         }
 913         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 914
 915         /* Now clear any previous stat_idx set */
 916         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 917         if (!is_rx)
 918                 stat_mappings->tqsm[n] &= ~clearing_mask;
 919         else
 920                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 921
 922         q_map = (uint32_t)stat_idx;
 923         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 924         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 925         if (!is_rx)
 926                 stat_mappings->tqsm[n] |= qsmr_mask;
 927         else
 928                 stat_mappings->rqsmr[n] |= qsmr_mask;
 929
 930         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 931                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 932                      queue_id, stat_idx);
 933         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 934                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 935
 936         /* Now write the mapping in the appropriate register */
 937         if (is_rx) {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 939                              stat_mappings->rqsmr[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 941         } else {
 942                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 943                              stat_mappings->tqsm[n], n);
 944                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 945         }
 946         return 0;
 947 }
 948
 949 static void
 950 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 951 {
 952         struct ixgbe_stat_mapping_registers *stat_mappings =
 953                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 955         int i;
 956
 957         /* write whatever was in stat mapping table to the NIC */
 958         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 959                 /* rx */
 960                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 961
 962                 /* tx */
 963                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 964         }
 965 }
 966
 967 static void
 968 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 969 {
 970         uint8_t i;
 971         struct ixgbe_dcb_tc_config *tc;
 972         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 973
 974         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 975         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 976         for (i = 0; i < dcb_max_tc; i++) {
 977                 tc = &dcb_config->tc_config[i];
 978                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 980                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 981                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 983                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 984                 tc->pfc = ixgbe_dcb_pfc_disabled;
 985         }
 986
 987         /* Initialize default user to priority mapping, UPx->TC0 */
 988         tc = &dcb_config->tc_config[0];
 989         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 990         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 992                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 993                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 994         }
 995         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 996         dcb_config->pfc_mode_enable = false;
 997         dcb_config->vt_mode = true;
 998         dcb_config->round_robin_enable = false;
 999         /* support all DCB capabilities in 82599 */
1000         dcb_config->support.capabilities = 0xFF;
1001
1002         /*we only support 4 Tcs for X540, X550 */
1003         if (hw->mac.type == ixgbe_mac_X540 ||
1004                 hw->mac.type == ixgbe_mac_X550 ||
1005                 hw->mac.type == ixgbe_mac_X550EM_x ||
1006                 hw->mac.type == ixgbe_mac_X550EM_a) {
1007                 dcb_config->num_tcs.pg_tcs = 4;
1008                 dcb_config->num_tcs.pfc_tcs = 4;
1009         }
1010 }
1011
1012 /*
1013  * Ensure that all locks are released before first NVM or PHY access
1014  */
1015 static void
1016 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1017 {
1018         uint16_t mask;
1019
1020         /*
1021          * Phy lock should not fail in this early stage. If this is the case,
1022          * it is due to an improper exit of the application.
1023          * So force the release of the faulty lock. Release of common lock
1024          * is done automatically by swfw_sync function.
1025          */
1026         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1027         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1028                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1029         }
1030         ixgbe_release_swfw_semaphore(hw, mask);
1031
1032         /*
1033          * These ones are more tricky since they are common to all ports; but
1034          * swfw_sync retries last long enough (1s) to be almost sure that if
1035          * lock can not be taken it is due to an improper lock of the
1036          * semaphore.
1037          */
1038         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1039         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1040                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1041         }
1042         ixgbe_release_swfw_semaphore(hw, mask);
1043 }
1044
1045 /*
1046  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1047  * It returns 0 on success.
1048  */
1049 static int
1050 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1051 {
1052         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1053         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1054         struct ixgbe_hw *hw =
1055                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1056         struct ixgbe_vfta *shadow_vfta =
1057                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1058         struct ixgbe_hwstrip *hwstrip =
1059                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1060         struct ixgbe_dcb_config *dcb_config =
1061                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1062         struct ixgbe_filter_info *filter_info =
1063                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1064         struct ixgbe_bw_conf *bw_conf =
1065                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1066         uint32_t ctrl_ext;
1067         uint16_t csum;
1068         int diag, i;
1069
1070         PMD_INIT_FUNC_TRACE();
1071
1072         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1073         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1074         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1075         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1076
1077         /*
1078          * For secondary processes, we don't initialise any further as primary
1079          * has already done this work. Only check we don't need a different
1080          * RX and TX function.
1081          */
1082         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1083                 struct ixgbe_tx_queue *txq;
1084                 /* TX queue function in primary, set by last queue initialized
1085                  * Tx queue may not initialized by primary process
1086                  */
1087                 if (eth_dev->data->tx_queues) {
1088                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1089                         ixgbe_set_tx_function(eth_dev, txq);
1090                 } else {
1091                         /* Use default TX function if we get here */
1092                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1093                                      "Using default TX function.");
1094                 }
1095
1096                 ixgbe_set_rx_function(eth_dev);
1097
1098                 return 0;
1099         }
1100
1101         rte_eth_copy_pci_info(eth_dev, pci_dev);
1102
1103         /* Vendor and Device ID need to be set before init of shared code */
1104         hw->device_id = pci_dev->id.device_id;
1105         hw->vendor_id = pci_dev->id.vendor_id;
1106         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1107         hw->allow_unsupported_sfp = 1;
1108
1109         /* Initialize the shared code (base driver) */
1110 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1111         diag = ixgbe_bypass_init_shared_code(hw);
1112 #else
1113         diag = ixgbe_init_shared_code(hw);
1114 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1115
1116         if (diag != IXGBE_SUCCESS) {
1117                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1118                 return -EIO;
1119         }
1120
1121         /* pick up the PCI bus settings for reporting later */
1122         ixgbe_get_bus_info(hw);
1123
1124         /* Unlock any pending hardware semaphore */
1125         ixgbe_swfw_lock_reset(hw);
1126
1127 #ifdef RTE_LIBRTE_SECURITY
1128         /* Initialize security_ctx only for primary process*/
1129         if (ixgbe_ipsec_ctx_create(eth_dev))
1130                 return -ENOMEM;
1131 #endif
1132
1133         /* Initialize DCB configuration*/
1134         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1135         ixgbe_dcb_init(hw, dcb_config);
1136         /* Get Hardware Flow Control setting */
1137         hw->fc.requested_mode = ixgbe_fc_full;
1138         hw->fc.current_mode = ixgbe_fc_full;
1139         hw->fc.pause_time = IXGBE_FC_PAUSE;
1140         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1141                 hw->fc.low_water[i] = IXGBE_FC_LO;
1142                 hw->fc.high_water[i] = IXGBE_FC_HI;
1143         }
1144         hw->fc.send_xon = 1;
1145
1146         /* Make sure we have a good EEPROM before we read from it */
1147         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1150                 return -EIO;
1151         }
1152
1153 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1154         diag = ixgbe_bypass_init_hw(hw);
1155 #else
1156         diag = ixgbe_init_hw(hw);
1157 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1158
1159         /*
1160          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1161          * is called too soon after the kernel driver unbinding/binding occurs.
1162          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1163          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1164          * also called. See ixgbe_identify_phy_82599(). The reason for the
1165          * failure is not known, and only occuts when virtualisation features
1166          * are disabled in the bios. A delay of 100ms  was found to be enough by
1167          * trial-and-error, and is doubled to be safe.
1168          */
1169         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1170                 rte_delay_ms(200);
1171                 diag = ixgbe_init_hw(hw);
1172         }
1173
1174         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1175                 diag = IXGBE_SUCCESS;
1176
1177         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1178                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1179                              "LOM.  Please be aware there may be issues associated "
1180                              "with your hardware.");
1181                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1182                              "please contact your Intel or hardware representative "
1183                              "who provided you with this hardware.");
1184         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1185                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1186         if (diag) {
1187                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1188                 return -EIO;
1189         }
1190
1191         /* Reset the hw statistics */
1192         ixgbe_dev_stats_reset(eth_dev);
1193
1194         /* disable interrupt */
1195         ixgbe_disable_intr(hw);
1196
1197         /* reset mappings for queue statistics hw counters*/
1198         ixgbe_reset_qstat_mappings(hw);
1199
1200         /* Allocate memory for storing MAC addresses */
1201         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1202                                                hw->mac.num_rar_entries, 0);
1203         if (eth_dev->data->mac_addrs == NULL) {
1204                 PMD_INIT_LOG(ERR,
1205                              "Failed to allocate %u bytes needed to store "
1206                              "MAC addresses",
1207                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1208                 return -ENOMEM;
1209         }
1210         /* Copy the permanent MAC address */
1211         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1212                         &eth_dev->data->mac_addrs[0]);
1213
1214         /* Allocate memory for storing hash filter MAC addresses */
1215         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1216                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1217         if (eth_dev->data->hash_mac_addrs == NULL) {
1218                 PMD_INIT_LOG(ERR,
1219                              "Failed to allocate %d bytes needed to store MAC addresses",
1220                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1221                 return -ENOMEM;
1222         }
1223
1224         /* initialize the vfta */
1225         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1226
1227         /* initialize the hw strip bitmap*/
1228         memset(hwstrip, 0, sizeof(*hwstrip));
1229
1230         /* initialize PF if max_vfs not zero */
1231         ixgbe_pf_host_init(eth_dev);
1232
1233         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1234         /* let hardware know driver is loaded */
1235         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1236         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1237         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1238         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1239         IXGBE_WRITE_FLUSH(hw);
1240
1241         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type,
1244                              (int) hw->phy.sfp_type);
1245         else
1246                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1247                              (int) hw->mac.type, (int) hw->phy.type);
1248
1249         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1250                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1251                      pci_dev->id.device_id);
1252
1253         rte_intr_callback_register(intr_handle,
1254                                    ixgbe_dev_interrupt_handler, eth_dev);
1255
1256         /* enable uio/vfio intr/eventfd mapping */
1257         rte_intr_enable(intr_handle);
1258
1259         /* enable support intr */
1260         ixgbe_enable_intr(eth_dev);
1261
1262         /* initialize filter info */
1263         memset(filter_info, 0,
1264                sizeof(struct ixgbe_filter_info));
1265
1266         /* initialize 5tuple filter list */
1267         TAILQ_INIT(&filter_info->fivetuple_list);
1268
1269         /* initialize flow director filter list & hash */
1270         ixgbe_fdir_filter_init(eth_dev);
1271
1272         /* initialize l2 tunnel filter list & hash */
1273         ixgbe_l2_tn_filter_init(eth_dev);
1274
1275         /* initialize flow filter lists */
1276         ixgbe_filterlist_init();
1277
1278         /* initialize bandwidth configuration info */
1279         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1280
1281         /* initialize Traffic Manager configuration */
1282         ixgbe_tm_conf_init(eth_dev);
1283
1284         return 0;
1285 }
1286
1287 static int
1288 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1289 {
1290         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1291         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1292         struct ixgbe_hw *hw;
1293         int retries = 0;
1294         int ret;
1295
1296         PMD_INIT_FUNC_TRACE();
1297
1298         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1299                 return -EPERM;
1300
1301         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1302
1303         if (hw->adapter_stopped == 0)
1304                 ixgbe_dev_close(eth_dev);
1305
1306         eth_dev->dev_ops = NULL;
1307         eth_dev->rx_pkt_burst = NULL;
1308         eth_dev->tx_pkt_burst = NULL;
1309
1310         /* Unlock any pending hardware semaphore */
1311         ixgbe_swfw_lock_reset(hw);
1312
1313         /* disable uio intr before callback unregister */
1314         rte_intr_disable(intr_handle);
1315
1316         do {
1317                 ret = rte_intr_callback_unregister(intr_handle,
1318                                 ixgbe_dev_interrupt_handler, eth_dev);
1319                 if (ret >= 0) {
1320                         break;
1321                 } else if (ret != -EAGAIN) {
1322                         PMD_INIT_LOG(ERR,
1323                                 "intr callback unregister failed: %d",
1324                                 ret);
1325                         return ret;
1326                 }
1327                 rte_delay_ms(100);
1328         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1329
1330         /* uninitialize PF if max_vfs not zero */
1331         ixgbe_pf_host_uninit(eth_dev);
1332
1333         rte_free(eth_dev->data->mac_addrs);
1334         eth_dev->data->mac_addrs = NULL;
1335
1336         rte_free(eth_dev->data->hash_mac_addrs);
1337         eth_dev->data->hash_mac_addrs = NULL;
1338
1339         /* remove all the fdir filters & hash */
1340         ixgbe_fdir_filter_uninit(eth_dev);
1341
1342         /* remove all the L2 tunnel filters & hash */
1343         ixgbe_l2_tn_filter_uninit(eth_dev);
1344
1345         /* Remove all ntuple filters of the device */
1346         ixgbe_ntuple_filter_uninit(eth_dev);
1347
1348         /* clear all the filters list */
1349         ixgbe_filterlist_flush();
1350
1351         /* Remove all Traffic Manager configuration */
1352         ixgbe_tm_conf_uninit(eth_dev);
1353
1354 #ifdef RTE_LIBRTE_SECURITY
1355         rte_free(eth_dev->security_ctx);
1356 #endif
1357
1358         return 0;
1359 }
1360
1361 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1362 {
1363         struct ixgbe_filter_info *filter_info =
1364                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1365         struct ixgbe_5tuple_filter *p_5tuple;
1366
1367         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1368                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1369                              p_5tuple,
1370                              entries);
1371                 rte_free(p_5tuple);
1372         }
1373         memset(filter_info->fivetuple_mask, 0,
1374                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1375
1376         return 0;
1377 }
1378
1379 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1380 {
1381         struct ixgbe_hw_fdir_info *fdir_info =
1382                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1383         struct ixgbe_fdir_filter *fdir_filter;
1384
1385                 if (fdir_info->hash_map)
1386                 rte_free(fdir_info->hash_map);
1387         if (fdir_info->hash_handle)
1388                 rte_hash_free(fdir_info->hash_handle);
1389
1390         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1391                 TAILQ_REMOVE(&fdir_info->fdir_list,
1392                              fdir_filter,
1393                              entries);
1394                 rte_free(fdir_filter);
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1401 {
1402         struct ixgbe_l2_tn_info *l2_tn_info =
1403                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1404         struct ixgbe_l2_tn_filter *l2_tn_filter;
1405
1406         if (l2_tn_info->hash_map)
1407                 rte_free(l2_tn_info->hash_map);
1408         if (l2_tn_info->hash_handle)
1409                 rte_hash_free(l2_tn_info->hash_handle);
1410
1411         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1412                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1413                              l2_tn_filter,
1414                              entries);
1415                 rte_free(l2_tn_filter);
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1422 {
1423         struct ixgbe_hw_fdir_info *fdir_info =
1424                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1425         char fdir_hash_name[RTE_HASH_NAMESIZE];
1426         struct rte_hash_parameters fdir_hash_params = {
1427                 .name = fdir_hash_name,
1428                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1429                 .key_len = sizeof(union ixgbe_atr_input),
1430                 .hash_func = rte_hash_crc,
1431                 .hash_func_init_val = 0,
1432                 .socket_id = rte_socket_id(),
1433         };
1434
1435         TAILQ_INIT(&fdir_info->fdir_list);
1436         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1437                  "fdir_%s", eth_dev->device->name);
1438         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1439         if (!fdir_info->hash_handle) {
1440                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1441                 return -EINVAL;
1442         }
1443         fdir_info->hash_map = rte_zmalloc("ixgbe",
1444                                           sizeof(struct ixgbe_fdir_filter *) *
1445                                           IXGBE_MAX_FDIR_FILTER_NUM,
1446                                           0);
1447         if (!fdir_info->hash_map) {
1448                 PMD_INIT_LOG(ERR,
1449                              "Failed to allocate memory for fdir hash map!");
1450                 return -ENOMEM;
1451         }
1452         fdir_info->mask_added = FALSE;
1453
1454         return 0;
1455 }
1456
1457 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1458 {
1459         struct ixgbe_l2_tn_info *l2_tn_info =
1460                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1461         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1462         struct rte_hash_parameters l2_tn_hash_params = {
1463                 .name = l2_tn_hash_name,
1464                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1465                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1466                 .hash_func = rte_hash_crc,
1467                 .hash_func_init_val = 0,
1468                 .socket_id = rte_socket_id(),
1469         };
1470
1471         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1472         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1473                  "l2_tn_%s", eth_dev->device->name);
1474         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1475         if (!l2_tn_info->hash_handle) {
1476                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1477                 return -EINVAL;
1478         }
1479         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1480                                    sizeof(struct ixgbe_l2_tn_filter *) *
1481                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1482                                    0);
1483         if (!l2_tn_info->hash_map) {
1484                 PMD_INIT_LOG(ERR,
1485                         "Failed to allocate memory for L2 TN hash map!");
1486                 return -ENOMEM;
1487         }
1488         l2_tn_info->e_tag_en = FALSE;
1489         l2_tn_info->e_tag_fwd_en = FALSE;
1490         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1491
1492         return 0;
1493 }
1494 /*
1495  * Negotiate mailbox API version with the PF.
1496  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1497  * Then we try to negotiate starting with the most recent one.
1498  * If all negotiation attempts fail, then we will proceed with
1499  * the default one (ixgbe_mbox_api_10).
1500  */
1501 static void
1502 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1503 {
1504         int32_t i;
1505
1506         /* start with highest supported, proceed down */
1507         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1508                 ixgbe_mbox_api_12,
1509                 ixgbe_mbox_api_11,
1510                 ixgbe_mbox_api_10,
1511         };
1512
1513         for (i = 0;
1514                         i != RTE_DIM(sup_ver) &&
1515                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1516                         i++)
1517                 ;
1518 }
1519
1520 static void
1521 generate_random_mac_addr(struct ether_addr *mac_addr)
1522 {
1523         uint64_t random;
1524
1525         /* Set Organizationally Unique Identifier (OUI) prefix. */
1526         mac_addr->addr_bytes[0] = 0x00;
1527         mac_addr->addr_bytes[1] = 0x09;
1528         mac_addr->addr_bytes[2] = 0xC0;
1529         /* Force indication of locally assigned MAC address. */
1530         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1531         /* Generate the last 3 bytes of the MAC address with a random number. */
1532         random = rte_rand();
1533         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1534 }
1535
1536 /*
1537  * Virtual Function device init
1538  */
1539 static int
1540 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1541 {
1542         int diag;
1543         uint32_t tc, tcs;
1544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1546         struct ixgbe_hw *hw =
1547                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1548         struct ixgbe_vfta *shadow_vfta =
1549                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1550         struct ixgbe_hwstrip *hwstrip =
1551                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1552         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1553
1554         PMD_INIT_FUNC_TRACE();
1555
1556         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1557         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1558         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1559
1560         /* for secondary processes, we don't initialise any further as primary
1561          * has already done this work. Only check we don't need a different
1562          * RX function
1563          */
1564         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1565                 struct ixgbe_tx_queue *txq;
1566                 /* TX queue function in primary, set by last queue initialized
1567                  * Tx queue may not initialized by primary process
1568                  */
1569                 if (eth_dev->data->tx_queues) {
1570                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1571                         ixgbe_set_tx_function(eth_dev, txq);
1572                 } else {
1573                         /* Use default TX function if we get here */
1574                         PMD_INIT_LOG(NOTICE,
1575                                      "No TX queues configured yet. Using default TX function.");
1576                 }
1577
1578                 ixgbe_set_rx_function(eth_dev);
1579
1580                 return 0;
1581         }
1582
1583         rte_eth_copy_pci_info(eth_dev, pci_dev);
1584
1585         hw->device_id = pci_dev->id.device_id;
1586         hw->vendor_id = pci_dev->id.vendor_id;
1587         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1588
1589         /* initialize the vfta */
1590         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1591
1592         /* initialize the hw strip bitmap*/
1593         memset(hwstrip, 0, sizeof(*hwstrip));
1594
1595         /* Initialize the shared code (base driver) */
1596         diag = ixgbe_init_shared_code(hw);
1597         if (diag != IXGBE_SUCCESS) {
1598                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1599                 return -EIO;
1600         }
1601
1602         /* init_mailbox_params */
1603         hw->mbx.ops.init_params(hw);
1604
1605         /* Reset the hw statistics */
1606         ixgbevf_dev_stats_reset(eth_dev);
1607
1608         /* Disable the interrupts for VF */
1609         ixgbevf_intr_disable(hw);
1610
1611         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1612         diag = hw->mac.ops.reset_hw(hw);
1613
1614         /*
1615          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1616          * the underlying PF driver has not assigned a MAC address to the VF.
1617          * In this case, assign a random MAC address.
1618          */
1619         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1620                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1621                 return diag;
1622         }
1623
1624         /* negotiate mailbox API version to use with the PF. */
1625         ixgbevf_negotiate_api(hw);
1626
1627         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1628         ixgbevf_get_queues(hw, &tcs, &tc);
1629
1630         /* Allocate memory for storing MAC addresses */
1631         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1632                                                hw->mac.num_rar_entries, 0);
1633         if (eth_dev->data->mac_addrs == NULL) {
1634                 PMD_INIT_LOG(ERR,
1635                              "Failed to allocate %u bytes needed to store "
1636                              "MAC addresses",
1637                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1638                 return -ENOMEM;
1639         }
1640
1641         /* Generate a random MAC address, if none was assigned by PF. */
1642         if (is_zero_ether_addr(perm_addr)) {
1643                 generate_random_mac_addr(perm_addr);
1644                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1645                 if (diag) {
1646                         rte_free(eth_dev->data->mac_addrs);
1647                         eth_dev->data->mac_addrs = NULL;
1648                         return diag;
1649                 }
1650                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1651                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1652                              "%02x:%02x:%02x:%02x:%02x:%02x",
1653                              perm_addr->addr_bytes[0],
1654                              perm_addr->addr_bytes[1],
1655                              perm_addr->addr_bytes[2],
1656                              perm_addr->addr_bytes[3],
1657                              perm_addr->addr_bytes[4],
1658                              perm_addr->addr_bytes[5]);
1659         }
1660
1661         /* Copy the permanent MAC address */
1662         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1663
1664         /* reset the hardware with the new settings */
1665         diag = hw->mac.ops.start_hw(hw);
1666         switch (diag) {
1667         case  0:
1668                 break;
1669
1670         default:
1671                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1672                 return -EIO;
1673         }
1674
1675         rte_intr_callback_register(intr_handle,
1676                                    ixgbevf_dev_interrupt_handler, eth_dev);
1677         rte_intr_enable(intr_handle);
1678         ixgbevf_intr_enable(hw);
1679
1680         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1681                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1682                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1683
1684         return 0;
1685 }
1686
1687 /* Virtual Function device uninit */
1688
1689 static int
1690 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1691 {
1692         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1693         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1694         struct ixgbe_hw *hw;
1695
1696         PMD_INIT_FUNC_TRACE();
1697
1698         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1699                 return -EPERM;
1700
1701         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1702
1703         if (hw->adapter_stopped == 0)
1704                 ixgbevf_dev_close(eth_dev);
1705
1706         eth_dev->dev_ops = NULL;
1707         eth_dev->rx_pkt_burst = NULL;
1708         eth_dev->tx_pkt_burst = NULL;
1709
1710         /* Disable the interrupts for VF */
1711         ixgbevf_intr_disable(hw);
1712
1713         rte_free(eth_dev->data->mac_addrs);
1714         eth_dev->data->mac_addrs = NULL;
1715
1716         rte_intr_disable(intr_handle);
1717         rte_intr_callback_unregister(intr_handle,
1718                                      ixgbevf_dev_interrupt_handler, eth_dev);
1719
1720         return 0;
1721 }
1722
1723 static int
1724 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1725                 struct rte_pci_device *pci_dev)
1726 {
1727         char name[RTE_ETH_NAME_MAX_LEN];
1728         struct rte_eth_dev *pf_ethdev;
1729         struct rte_eth_devargs eth_da;
1730         int i, retval;
1731
1732         if (pci_dev->device.devargs) {
1733                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1734                                 &eth_da);
1735                 if (retval)
1736                         return retval;
1737         } else
1738                 memset(&eth_da, 0, sizeof(eth_da));
1739
1740         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1741                 sizeof(struct ixgbe_adapter),
1742                 eth_dev_pci_specific_init, pci_dev,
1743                 eth_ixgbe_dev_init, NULL);
1744
1745         if (retval || eth_da.nb_representor_ports < 1)
1746                 return retval;
1747
1748         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1749         if (pf_ethdev == NULL)
1750                 return -ENODEV;
1751
1752         /* probe VF representor ports */
1753         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1754                 struct ixgbe_vf_info *vfinfo;
1755                 struct ixgbe_vf_representor representor;
1756
1757                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1758                         pf_ethdev->data->dev_private);
1759                 if (vfinfo == NULL) {
1760                         PMD_DRV_LOG(ERR,
1761                                 "no virtual functions supported by PF");
1762                         break;
1763                 }
1764
1765                 representor.vf_id = eth_da.representor_ports[i];
1766                 representor.switch_domain_id = vfinfo->switch_domain_id;
1767                 representor.pf_ethdev = pf_ethdev;
1768
1769                 /* representor port net_bdf_port */
1770                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1771                         pci_dev->device.name,
1772                         eth_da.representor_ports[i]);
1773
1774                 retval = rte_eth_dev_create(&pci_dev->device, name,
1775                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1776                         ixgbe_vf_representor_init, &representor);
1777
1778                 if (retval)
1779                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1780                                 "representor %s.", name);
1781         }
1782
1783         return 0;
1784 }
1785
1786 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1787 {
1788         struct rte_eth_dev *ethdev;
1789
1790         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1791         if (!ethdev)
1792                 return -ENODEV;
1793
1794         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1795                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1796         else
1797                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1798 }
1799
1800 static struct rte_pci_driver rte_ixgbe_pmd = {
1801         .id_table = pci_id_ixgbe_map,
1802         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1803                      RTE_PCI_DRV_IOVA_AS_VA,
1804         .probe = eth_ixgbe_pci_probe,
1805         .remove = eth_ixgbe_pci_remove,
1806 };
1807
1808 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1809         struct rte_pci_device *pci_dev)
1810 {
1811         return rte_eth_dev_pci_generic_probe(pci_dev,
1812                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1813 }
1814
1815 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1816 {
1817         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1818 }
1819
1820 /*
1821  * virtual function driver struct
1822  */
1823 static struct rte_pci_driver rte_ixgbevf_pmd = {
1824         .id_table = pci_id_ixgbevf_map,
1825         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1826         .probe = eth_ixgbevf_pci_probe,
1827         .remove = eth_ixgbevf_pci_remove,
1828 };
1829
1830 static int
1831 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1832 {
1833         struct ixgbe_hw *hw =
1834                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         struct ixgbe_vfta *shadow_vfta =
1836                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1837         uint32_t vfta;
1838         uint32_t vid_idx;
1839         uint32_t vid_bit;
1840
1841         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1842         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1843         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1844         if (on)
1845                 vfta |= vid_bit;
1846         else
1847                 vfta &= ~vid_bit;
1848         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1849
1850         /* update local VFTA copy */
1851         shadow_vfta->vfta[vid_idx] = vfta;
1852
1853         return 0;
1854 }
1855
1856 static void
1857 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1858 {
1859         if (on)
1860                 ixgbe_vlan_hw_strip_enable(dev, queue);
1861         else
1862                 ixgbe_vlan_hw_strip_disable(dev, queue);
1863 }
1864
1865 static int
1866 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1867                     enum rte_vlan_type vlan_type,
1868                     uint16_t tpid)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         int ret = 0;
1873         uint32_t reg;
1874         uint32_t qinq;
1875
1876         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1877         qinq &= IXGBE_DMATXCTL_GDV;
1878
1879         switch (vlan_type) {
1880         case ETH_VLAN_TYPE_INNER:
1881                 if (qinq) {
1882                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1889                 } else {
1890                         ret = -ENOTSUP;
1891                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1892                                     " by single VLAN");
1893                 }
1894                 break;
1895         case ETH_VLAN_TYPE_OUTER:
1896                 if (qinq) {
1897                         /* Only the high 16-bits is valid */
1898                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1899                                         IXGBE_EXVET_VET_EXT_SHIFT);
1900                 } else {
1901                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1902                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1903                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1904                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1905                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1906                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1907                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1908                 }
1909
1910                 break;
1911         default:
1912                 ret = -EINVAL;
1913                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1914                 break;
1915         }
1916
1917         return ret;
1918 }
1919
1920 void
1921 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1922 {
1923         struct ixgbe_hw *hw =
1924                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925         uint32_t vlnctrl;
1926
1927         PMD_INIT_FUNC_TRACE();
1928
1929         /* Filter Table Disable */
1930         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1932
1933         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1934 }
1935
1936 void
1937 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1938 {
1939         struct ixgbe_hw *hw =
1940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct ixgbe_vfta *shadow_vfta =
1942                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1943         uint32_t vlnctrl;
1944         uint16_t i;
1945
1946         PMD_INIT_FUNC_TRACE();
1947
1948         /* Filter Table Enable */
1949         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1950         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1951         vlnctrl |= IXGBE_VLNCTRL_VFE;
1952
1953         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1954
1955         /* write whatever is in local vfta copy */
1956         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1957                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1958 }
1959
1960 static void
1961 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1962 {
1963         struct ixgbe_hwstrip *hwstrip =
1964                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1965         struct ixgbe_rx_queue *rxq;
1966
1967         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1968                 return;
1969
1970         if (on)
1971                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1972         else
1973                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1974
1975         if (queue >= dev->data->nb_rx_queues)
1976                 return;
1977
1978         rxq = dev->data->rx_queues[queue];
1979
1980         if (on)
1981                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1982         else
1983                 rxq->vlan_flags = PKT_RX_VLAN;
1984 }
1985
1986 static void
1987 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1988 {
1989         struct ixgbe_hw *hw =
1990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         uint32_t ctrl;
1992
1993         PMD_INIT_FUNC_TRACE();
1994
1995         if (hw->mac.type == ixgbe_mac_82598EB) {
1996                 /* No queue level support */
1997                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1998                 return;
1999         }
2000
2001         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2002         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2003         ctrl &= ~IXGBE_RXDCTL_VME;
2004         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2005
2006         /* record those setting for HW strip per queue */
2007         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2008 }
2009
2010 static void
2011 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2012 {
2013         struct ixgbe_hw *hw =
2014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2015         uint32_t ctrl;
2016
2017         PMD_INIT_FUNC_TRACE();
2018
2019         if (hw->mac.type == ixgbe_mac_82598EB) {
2020                 /* No queue level supported */
2021                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2022                 return;
2023         }
2024
2025         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2026         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2027         ctrl |= IXGBE_RXDCTL_VME;
2028         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2029
2030         /* record those setting for HW strip per queue */
2031         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2032 }
2033
2034 static void
2035 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2036 {
2037         struct ixgbe_hw *hw =
2038                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039         uint32_t ctrl;
2040
2041         PMD_INIT_FUNC_TRACE();
2042
2043         /* DMATXCTRL: Geric Double VLAN Disable */
2044         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2045         ctrl &= ~IXGBE_DMATXCTL_GDV;
2046         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2047
2048         /* CTRL_EXT: Global Double VLAN Disable */
2049         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2050         ctrl &= ~IXGBE_EXTENDED_VLAN;
2051         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2052
2053 }
2054
2055 static void
2056 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2057 {
2058         struct ixgbe_hw *hw =
2059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         uint32_t ctrl;
2061
2062         PMD_INIT_FUNC_TRACE();
2063
2064         /* DMATXCTRL: Geric Double VLAN Enable */
2065         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2066         ctrl |= IXGBE_DMATXCTL_GDV;
2067         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2068
2069         /* CTRL_EXT: Global Double VLAN Enable */
2070         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2071         ctrl |= IXGBE_EXTENDED_VLAN;
2072         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2073
2074         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2075         if (hw->mac.type == ixgbe_mac_X550 ||
2076             hw->mac.type == ixgbe_mac_X550EM_x ||
2077             hw->mac.type == ixgbe_mac_X550EM_a) {
2078                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2079                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2080                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2081         }
2082
2083         /*
2084          * VET EXT field in the EXVET register = 0x8100 by default
2085          * So no need to change. Same to VT field of DMATXCTL register
2086          */
2087 }
2088
2089 void
2090 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2091 {
2092         struct ixgbe_hw *hw =
2093                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2094         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2095         uint32_t ctrl;
2096         uint16_t i;
2097         struct ixgbe_rx_queue *rxq;
2098         bool on;
2099
2100         PMD_INIT_FUNC_TRACE();
2101
2102         if (hw->mac.type == ixgbe_mac_82598EB) {
2103                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2104                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2105                         ctrl |= IXGBE_VLNCTRL_VME;
2106                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2107                 } else {
2108                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2109                         ctrl &= ~IXGBE_VLNCTRL_VME;
2110                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2111                 }
2112         } else {
2113                 /*
2114                  * Other 10G NIC, the VLAN strip can be setup
2115                  * per queue in RXDCTL
2116                  */
2117                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2118                         rxq = dev->data->rx_queues[i];
2119                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2120                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2121                                 ctrl |= IXGBE_RXDCTL_VME;
2122                                 on = TRUE;
2123                         } else {
2124                                 ctrl &= ~IXGBE_RXDCTL_VME;
2125                                 on = FALSE;
2126                         }
2127                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2128
2129                         /* record those setting for HW strip per queue */
2130                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2131                 }
2132         }
2133 }
2134
2135 static int
2136 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2137 {
2138         struct rte_eth_rxmode *rxmode;
2139         rxmode = &dev->data->dev_conf.rxmode;
2140
2141         if (mask & ETH_VLAN_STRIP_MASK) {
2142                 ixgbe_vlan_hw_strip_config(dev);
2143         }
2144
2145         if (mask & ETH_VLAN_FILTER_MASK) {
2146                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2147                         ixgbe_vlan_hw_filter_enable(dev);
2148                 else
2149                         ixgbe_vlan_hw_filter_disable(dev);
2150         }
2151
2152         if (mask & ETH_VLAN_EXTEND_MASK) {
2153                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2154                         ixgbe_vlan_hw_extend_enable(dev);
2155                 else
2156                         ixgbe_vlan_hw_extend_disable(dev);
2157         }
2158
2159         return 0;
2160 }
2161
2162 static void
2163 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2164 {
2165         struct ixgbe_hw *hw =
2166                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2168         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2169
2170         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2171         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2172 }
2173
2174 static int
2175 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2176 {
2177         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2178
2179         switch (nb_rx_q) {
2180         case 1:
2181         case 2:
2182                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2183                 break;
2184         case 4:
2185                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2186                 break;
2187         default:
2188                 return -EINVAL;
2189         }
2190
2191         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2192                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2193         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2194                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2195         return 0;
2196 }
2197
2198 static int
2199 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2200 {
2201         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2202         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2204         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2205
2206         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2207                 /* check multi-queue mode */
2208                 switch (dev_conf->rxmode.mq_mode) {
2209                 case ETH_MQ_RX_VMDQ_DCB:
2210                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2211                         break;
2212                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2213                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2214                         PMD_INIT_LOG(ERR, "SRIOV active,"
2215                                         " unsupported mq_mode rx %d.",
2216                                         dev_conf->rxmode.mq_mode);
2217                         return -EINVAL;
2218                 case ETH_MQ_RX_RSS:
2219                 case ETH_MQ_RX_VMDQ_RSS:
2220                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2221                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2222                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2223                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2224                                                 " invalid queue number"
2225                                                 " for VMDQ RSS, allowed"
2226                                                 " value are 1, 2 or 4.");
2227                                         return -EINVAL;
2228                                 }
2229                         break;
2230                 case ETH_MQ_RX_VMDQ_ONLY:
2231                 case ETH_MQ_RX_NONE:
2232                         /* if nothing mq mode configure, use default scheme */
2233                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2234                         break;
2235                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2236                         /* SRIOV only works in VMDq enable mode */
2237                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2238                                         " wrong mq_mode rx %d.",
2239                                         dev_conf->rxmode.mq_mode);
2240                         return -EINVAL;
2241                 }
2242
2243                 switch (dev_conf->txmode.mq_mode) {
2244                 case ETH_MQ_TX_VMDQ_DCB:
2245                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2246                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2247                         break;
2248                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2249                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2250                         break;
2251                 }
2252
2253                 /* check valid queue number */
2254                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2255                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2256                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2257                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2258                                         " must be less than or equal to %d.",
2259                                         nb_rx_q, nb_tx_q,
2260                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2261                         return -EINVAL;
2262                 }
2263         } else {
2264                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2265                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2266                                           " not supported.");
2267                         return -EINVAL;
2268                 }
2269                 /* check configuration for vmdb+dcb mode */
2270                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2271                         const struct rte_eth_vmdq_dcb_conf *conf;
2272
2273                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2274                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2275                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2276                                 return -EINVAL;
2277                         }
2278                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2279                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2280                                conf->nb_queue_pools == ETH_32_POOLS)) {
2281                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2282                                                 " nb_queue_pools must be %d or %d.",
2283                                                 ETH_16_POOLS, ETH_32_POOLS);
2284                                 return -EINVAL;
2285                         }
2286                 }
2287                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2288                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2289
2290                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2291                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2292                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2293                                 return -EINVAL;
2294                         }
2295                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2296                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2297                                conf->nb_queue_pools == ETH_32_POOLS)) {
2298                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2299                                                 " nb_queue_pools != %d and"
2300                                                 " nb_queue_pools != %d.",
2301                                                 ETH_16_POOLS, ETH_32_POOLS);
2302                                 return -EINVAL;
2303                         }
2304                 }
2305
2306                 /* For DCB mode check our configuration before we go further */
2307                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2308                         const struct rte_eth_dcb_rx_conf *conf;
2309
2310                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2311                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2312                                                  IXGBE_DCB_NB_QUEUES);
2313                                 return -EINVAL;
2314                         }
2315                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2316                         if (!(conf->nb_tcs == ETH_4_TCS ||
2317                                conf->nb_tcs == ETH_8_TCS)) {
2318                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2319                                                 " and nb_tcs != %d.",
2320                                                 ETH_4_TCS, ETH_8_TCS);
2321                                 return -EINVAL;
2322                         }
2323                 }
2324
2325                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2326                         const struct rte_eth_dcb_tx_conf *conf;
2327
2328                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2329                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2330                                                  IXGBE_DCB_NB_QUEUES);
2331                                 return -EINVAL;
2332                         }
2333                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2334                         if (!(conf->nb_tcs == ETH_4_TCS ||
2335                                conf->nb_tcs == ETH_8_TCS)) {
2336                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2337                                                 " and nb_tcs != %d.",
2338                                                 ETH_4_TCS, ETH_8_TCS);
2339                                 return -EINVAL;
2340                         }
2341                 }
2342
2343                 /*
2344                  * When DCB/VT is off, maximum number of queues changes,
2345                  * except for 82598EB, which remains constant.
2346                  */
2347                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2348                                 hw->mac.type != ixgbe_mac_82598EB) {
2349                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2350                                 PMD_INIT_LOG(ERR,
2351                                              "Neither VT nor DCB are enabled, "
2352                                              "nb_tx_q > %d.",
2353                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2354                                 return -EINVAL;
2355                         }
2356                 }
2357         }
2358         return 0;
2359 }
2360
2361 static int
2362 ixgbe_dev_configure(struct rte_eth_dev *dev)
2363 {
2364         struct ixgbe_interrupt *intr =
2365                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2366         struct ixgbe_adapter *adapter =
2367                 (struct ixgbe_adapter *)dev->data->dev_private;
2368         struct rte_eth_dev_info dev_info;
2369         uint64_t rx_offloads;
2370         uint64_t tx_offloads;
2371         int ret;
2372
2373         PMD_INIT_FUNC_TRACE();
2374         /* multipe queue mode checking */
2375         ret  = ixgbe_check_mq_mode(dev);
2376         if (ret != 0) {
2377                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2378                             ret);
2379                 return ret;
2380         }
2381
2382         ixgbe_dev_info_get(dev, &dev_info);
2383         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2384         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2385                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2386                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2387                             rx_offloads, dev_info.rx_offload_capa);
2388                 return -ENOTSUP;
2389         }
2390         tx_offloads = dev->data->dev_conf.txmode.offloads;
2391         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2392                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2393                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2394                             tx_offloads, dev_info.tx_offload_capa);
2395                 return -ENOTSUP;
2396         }
2397
2398         /* set flag to update link status after init */
2399         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2400
2401         /*
2402          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2403          * allocation or vector Rx preconditions we will reset it.
2404          */
2405         adapter->rx_bulk_alloc_allowed = true;
2406         adapter->rx_vec_allowed = true;
2407
2408         return 0;
2409 }
2410
2411 static void
2412 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2413 {
2414         struct ixgbe_hw *hw =
2415                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2416         struct ixgbe_interrupt *intr =
2417                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2418         uint32_t gpie;
2419
2420         /* only set up it on X550EM_X */
2421         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2422                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2423                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2424                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2425                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2426                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2427         }
2428 }
2429
2430 int
2431 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2432                         uint16_t tx_rate, uint64_t q_msk)
2433 {
2434         struct ixgbe_hw *hw;
2435         struct ixgbe_vf_info *vfinfo;
2436         struct rte_eth_link link;
2437         uint8_t  nb_q_per_pool;
2438         uint32_t queue_stride;
2439         uint32_t queue_idx, idx = 0, vf_idx;
2440         uint32_t queue_end;
2441         uint16_t total_rate = 0;
2442         struct rte_pci_device *pci_dev;
2443
2444         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2445         rte_eth_link_get_nowait(dev->data->port_id, &link);
2446
2447         if (vf >= pci_dev->max_vfs)
2448                 return -EINVAL;
2449
2450         if (tx_rate > link.link_speed)
2451                 return -EINVAL;
2452
2453         if (q_msk == 0)
2454                 return 0;
2455
2456         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2458         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2459         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2460         queue_idx = vf * queue_stride;
2461         queue_end = queue_idx + nb_q_per_pool - 1;
2462         if (queue_end >= hw->mac.max_tx_queues)
2463                 return -EINVAL;
2464
2465         if (vfinfo) {
2466                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2467                         if (vf_idx == vf)
2468                                 continue;
2469                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2470                                 idx++)
2471                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2472                 }
2473         } else {
2474                 return -EINVAL;
2475         }
2476
2477         /* Store tx_rate for this vf. */
2478         for (idx = 0; idx < nb_q_per_pool; idx++) {
2479                 if (((uint64_t)0x1 << idx) & q_msk) {
2480                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2481                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2482                         total_rate += tx_rate;
2483                 }
2484         }
2485
2486         if (total_rate > dev->data->dev_link.link_speed) {
2487                 /* Reset stored TX rate of the VF if it causes exceed
2488                  * link speed.
2489                  */
2490                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2491                 return -EINVAL;
2492         }
2493
2494         /* Set RTTBCNRC of each queue/pool for vf X  */
2495         for (; queue_idx <= queue_end; queue_idx++) {
2496                 if (0x1 & q_msk)
2497                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2498                 q_msk = q_msk >> 1;
2499         }
2500
2501         return 0;
2502 }
2503
2504 /*
2505  * Configure device link speed and setup link.
2506  * It returns 0 on success.
2507  */
2508 static int
2509 ixgbe_dev_start(struct rte_eth_dev *dev)
2510 {
2511         struct ixgbe_hw *hw =
2512                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513         struct ixgbe_vf_info *vfinfo =
2514                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2515         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2516         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2517         uint32_t intr_vector = 0;
2518         int err, link_up = 0, negotiate = 0;
2519         uint32_t speed = 0;
2520         uint32_t allowed_speeds = 0;
2521         int mask = 0;
2522         int status;
2523         uint16_t vf, idx;
2524         uint32_t *link_speeds;
2525         struct ixgbe_tm_conf *tm_conf =
2526                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2527
2528         PMD_INIT_FUNC_TRACE();
2529
2530         /* IXGBE devices don't support:
2531         *    - half duplex (checked afterwards for valid speeds)
2532         *    - fixed speed: TODO implement
2533         */
2534         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2535                 PMD_INIT_LOG(ERR,
2536                 "Invalid link_speeds for port %u, fix speed not supported",
2537                                 dev->data->port_id);
2538                 return -EINVAL;
2539         }
2540
2541         /* disable uio/vfio intr/eventfd mapping */
2542         rte_intr_disable(intr_handle);
2543
2544         /* stop adapter */
2545         hw->adapter_stopped = 0;
2546         ixgbe_stop_adapter(hw);
2547
2548         /* reinitialize adapter
2549          * this calls reset and start
2550          */
2551         status = ixgbe_pf_reset_hw(hw);
2552         if (status != 0)
2553                 return -1;
2554         hw->mac.ops.start_hw(hw);
2555         hw->mac.get_link_status = true;
2556
2557         /* configure PF module if SRIOV enabled */
2558         ixgbe_pf_host_configure(dev);
2559
2560         ixgbe_dev_phy_intr_setup(dev);
2561
2562         /* check and configure queue intr-vector mapping */
2563         if ((rte_intr_cap_multiple(intr_handle) ||
2564              !RTE_ETH_DEV_SRIOV(dev).active) &&
2565             dev->data->dev_conf.intr_conf.rxq != 0) {
2566                 intr_vector = dev->data->nb_rx_queues;
2567                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2568                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2569                                         IXGBE_MAX_INTR_QUEUE_NUM);
2570                         return -ENOTSUP;
2571                 }
2572                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2573                         return -1;
2574         }
2575
2576         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2577                 intr_handle->intr_vec =
2578                         rte_zmalloc("intr_vec",
2579                                     dev->data->nb_rx_queues * sizeof(int), 0);
2580                 if (intr_handle->intr_vec == NULL) {
2581                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2582                                      " intr_vec", dev->data->nb_rx_queues);
2583                         return -ENOMEM;
2584                 }
2585         }
2586
2587         /* confiugre msix for sleep until rx interrupt */
2588         ixgbe_configure_msix(dev);
2589
2590         /* initialize transmission unit */
2591         ixgbe_dev_tx_init(dev);
2592
2593         /* This can fail when allocating mbufs for descriptor rings */
2594         err = ixgbe_dev_rx_init(dev);
2595         if (err) {
2596                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2597                 goto error;
2598         }
2599
2600         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2601                 ETH_VLAN_EXTEND_MASK;
2602         err = ixgbe_vlan_offload_set(dev, mask);
2603         if (err) {
2604                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2605                 goto error;
2606         }
2607
2608         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2609                 /* Enable vlan filtering for VMDq */
2610                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2611         }
2612
2613         /* Configure DCB hw */
2614         ixgbe_configure_dcb(dev);
2615
2616         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2617                 err = ixgbe_fdir_configure(dev);
2618                 if (err)
2619                         goto error;
2620         }
2621
2622         /* Restore vf rate limit */
2623         if (vfinfo != NULL) {
2624                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2625                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2626                                 if (vfinfo[vf].tx_rate[idx] != 0)
2627                                         ixgbe_set_vf_rate_limit(
2628                                                 dev, vf,
2629                                                 vfinfo[vf].tx_rate[idx],
2630                                                 1 << idx);
2631         }
2632
2633         ixgbe_restore_statistics_mapping(dev);
2634
2635         err = ixgbe_dev_rxtx_start(dev);
2636         if (err < 0) {
2637                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2638                 goto error;
2639         }
2640
2641         /* Skip link setup if loopback mode is enabled for 82599. */
2642         if (hw->mac.type == ixgbe_mac_82599EB &&
2643                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2644                 goto skip_link_setup;
2645
2646         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2647                 err = hw->mac.ops.setup_sfp(hw);
2648                 if (err)
2649                         goto error;
2650         }
2651
2652         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2653                 /* Turn on the copper */
2654                 ixgbe_set_phy_power(hw, true);
2655         } else {
2656                 /* Turn on the laser */
2657                 ixgbe_enable_tx_laser(hw);
2658         }
2659
2660         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2661         if (err)
2662                 goto error;
2663         dev->data->dev_link.link_status = link_up;
2664
2665         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2666         if (err)
2667                 goto error;
2668
2669         switch (hw->mac.type) {
2670         case ixgbe_mac_X550:
2671         case ixgbe_mac_X550EM_x:
2672         case ixgbe_mac_X550EM_a:
2673                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2674                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2675                         ETH_LINK_SPEED_10G;
2676                 break;
2677         default:
2678                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2679                         ETH_LINK_SPEED_10G;
2680         }
2681
2682         link_speeds = &dev->data->dev_conf.link_speeds;
2683         if (*link_speeds & ~allowed_speeds) {
2684                 PMD_INIT_LOG(ERR, "Invalid link setting");
2685                 goto error;
2686         }
2687
2688         speed = 0x0;
2689         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2690                 switch (hw->mac.type) {
2691                 case ixgbe_mac_82598EB:
2692                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2693                         break;
2694                 case ixgbe_mac_82599EB:
2695                 case ixgbe_mac_X540:
2696                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2697                         break;
2698                 case ixgbe_mac_X550:
2699                 case ixgbe_mac_X550EM_x:
2700                 case ixgbe_mac_X550EM_a:
2701                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2702                         break;
2703                 default:
2704                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2705                 }
2706         } else {
2707                 if (*link_speeds & ETH_LINK_SPEED_10G)
2708                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2709                 if (*link_speeds & ETH_LINK_SPEED_5G)
2710                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2711                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2712                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2713                 if (*link_speeds & ETH_LINK_SPEED_1G)
2714                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2715                 if (*link_speeds & ETH_LINK_SPEED_100M)
2716                         speed |= IXGBE_LINK_SPEED_100_FULL;
2717         }
2718
2719         err = ixgbe_setup_link(hw, speed, link_up);
2720         if (err)
2721                 goto error;
2722
2723         ixgbe_dev_link_update(dev, 0);
2724
2725 skip_link_setup:
2726
2727         if (rte_intr_allow_others(intr_handle)) {
2728                 /* check if lsc interrupt is enabled */
2729                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2730                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2731                 else
2732                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2733                 ixgbe_dev_macsec_interrupt_setup(dev);
2734         } else {
2735                 rte_intr_callback_unregister(intr_handle,
2736                                              ixgbe_dev_interrupt_handler, dev);
2737                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2738                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2739                                      " no intr multiplex");
2740         }
2741
2742         /* check if rxq interrupt is enabled */
2743         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2744             rte_intr_dp_is_en(intr_handle))
2745                 ixgbe_dev_rxq_interrupt_setup(dev);
2746
2747         /* enable uio/vfio intr/eventfd mapping */
2748         rte_intr_enable(intr_handle);
2749
2750         /* resume enabled intr since hw reset */
2751         ixgbe_enable_intr(dev);
2752         ixgbe_l2_tunnel_conf(dev);
2753         ixgbe_filter_restore(dev);
2754
2755         if (tm_conf->root && !tm_conf->committed)
2756                 PMD_DRV_LOG(WARNING,
2757                             "please call hierarchy_commit() "
2758                             "before starting the port");
2759
2760         return 0;
2761
2762 error:
2763         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2764         ixgbe_dev_clear_queues(dev);
2765         return -EIO;
2766 }
2767
2768 /*
2769  * Stop device: disable rx and tx functions to allow for reconfiguring.
2770  */
2771 static void
2772 ixgbe_dev_stop(struct rte_eth_dev *dev)
2773 {
2774         struct rte_eth_link link;
2775         struct ixgbe_hw *hw =
2776                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2777         struct ixgbe_vf_info *vfinfo =
2778                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2779         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2780         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2781         int vf;
2782         struct ixgbe_tm_conf *tm_conf =
2783                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2784
2785         PMD_INIT_FUNC_TRACE();
2786
2787         /* disable interrupts */
2788         ixgbe_disable_intr(hw);
2789
2790         /* reset the NIC */
2791         ixgbe_pf_reset_hw(hw);
2792         hw->adapter_stopped = 0;
2793
2794         /* stop adapter */
2795         ixgbe_stop_adapter(hw);
2796
2797         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2798                 vfinfo[vf].clear_to_send = false;
2799
2800         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2801                 /* Turn off the copper */
2802                 ixgbe_set_phy_power(hw, false);
2803         } else {
2804                 /* Turn off the laser */
2805                 ixgbe_disable_tx_laser(hw);
2806         }
2807
2808         ixgbe_dev_clear_queues(dev);
2809
2810         /* Clear stored conf */
2811         dev->data->scattered_rx = 0;
2812         dev->data->lro = 0;
2813
2814         /* Clear recorded link status */
2815         memset(&link, 0, sizeof(link));
2816         rte_eth_linkstatus_set(dev, &link);
2817
2818         if (!rte_intr_allow_others(intr_handle))
2819                 /* resume to the default handler */
2820                 rte_intr_callback_register(intr_handle,
2821                                            ixgbe_dev_interrupt_handler,
2822                                            (void *)dev);
2823
2824         /* Clean datapath event and queue/vec mapping */
2825         rte_intr_efd_disable(intr_handle);
2826         if (intr_handle->intr_vec != NULL) {
2827                 rte_free(intr_handle->intr_vec);
2828                 intr_handle->intr_vec = NULL;
2829         }
2830
2831         /* reset hierarchy commit */
2832         tm_conf->committed = false;
2833 }
2834
2835 /*
2836  * Set device link up: enable tx.
2837  */
2838 static int
2839 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2840 {
2841         struct ixgbe_hw *hw =
2842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843         if (hw->mac.type == ixgbe_mac_82599EB) {
2844 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2845                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2846                         /* Not suported in bypass mode */
2847                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2848                                      "by device id 0x%x", hw->device_id);
2849                         return -ENOTSUP;
2850                 }
2851 #endif
2852         }
2853
2854         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2855                 /* Turn on the copper */
2856                 ixgbe_set_phy_power(hw, true);
2857         } else {
2858                 /* Turn on the laser */
2859                 ixgbe_enable_tx_laser(hw);
2860         }
2861
2862         return 0;
2863 }
2864
2865 /*
2866  * Set device link down: disable tx.
2867  */
2868 static int
2869 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2870 {
2871         struct ixgbe_hw *hw =
2872                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873         if (hw->mac.type == ixgbe_mac_82599EB) {
2874 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2875                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2876                         /* Not suported in bypass mode */
2877                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2878                                      "by device id 0x%x", hw->device_id);
2879                         return -ENOTSUP;
2880                 }
2881 #endif
2882         }
2883
2884         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2885                 /* Turn off the copper */
2886                 ixgbe_set_phy_power(hw, false);
2887         } else {
2888                 /* Turn off the laser */
2889                 ixgbe_disable_tx_laser(hw);
2890         }
2891
2892         return 0;
2893 }
2894
2895 /*
2896  * Reset and stop device.
2897  */
2898 static void
2899 ixgbe_dev_close(struct rte_eth_dev *dev)
2900 {
2901         struct ixgbe_hw *hw =
2902                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2903
2904         PMD_INIT_FUNC_TRACE();
2905
2906         ixgbe_pf_reset_hw(hw);
2907
2908         ixgbe_dev_stop(dev);
2909         hw->adapter_stopped = 1;
2910
2911         ixgbe_dev_free_queues(dev);
2912
2913         ixgbe_disable_pcie_master(hw);
2914
2915         /* reprogram the RAR[0] in case user changed it. */
2916         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2917 }
2918
2919 /*
2920  * Reset PF device.
2921  */
2922 static int
2923 ixgbe_dev_reset(struct rte_eth_dev *dev)
2924 {
2925         int ret;
2926
2927         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2928          * its VF to make them align with it. The detailed notification
2929          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2930          * To avoid unexpected behavior in VF, currently reset of PF with
2931          * SR-IOV activation is not supported. It might be supported later.
2932          */
2933         if (dev->data->sriov.active)
2934                 return -ENOTSUP;
2935
2936         ret = eth_ixgbe_dev_uninit(dev);
2937         if (ret)
2938                 return ret;
2939
2940         ret = eth_ixgbe_dev_init(dev, NULL);
2941
2942         return ret;
2943 }
2944
2945 static void
2946 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2947                            struct ixgbe_hw_stats *hw_stats,
2948                            struct ixgbe_macsec_stats *macsec_stats,
2949                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2950                            uint64_t *total_qprc, uint64_t *total_qprdc)
2951 {
2952         uint32_t bprc, lxon, lxoff, total;
2953         uint32_t delta_gprc = 0;
2954         unsigned i;
2955         /* Workaround for RX byte count not including CRC bytes when CRC
2956          * strip is enabled. CRC bytes are removed from counters when crc_strip
2957          * is disabled.
2958          */
2959         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2960                         IXGBE_HLREG0_RXCRCSTRP);
2961
2962         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2963         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2964         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2965         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2966
2967         for (i = 0; i < 8; i++) {
2968                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2969
2970                 /* global total per queue */
2971                 hw_stats->mpc[i] += mp;
2972                 /* Running comprehensive total for stats display */
2973                 *total_missed_rx += hw_stats->mpc[i];
2974                 if (hw->mac.type == ixgbe_mac_82598EB) {
2975                         hw_stats->rnbc[i] +=
2976                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2977                         hw_stats->pxonrxc[i] +=
2978                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2979                         hw_stats->pxoffrxc[i] +=
2980                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2981                 } else {
2982                         hw_stats->pxonrxc[i] +=
2983                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2984                         hw_stats->pxoffrxc[i] +=
2985                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2986                         hw_stats->pxon2offc[i] +=
2987                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2988                 }
2989                 hw_stats->pxontxc[i] +=
2990                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2991                 hw_stats->pxofftxc[i] +=
2992                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2993         }
2994         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2995                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2996                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2997                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2998
2999                 delta_gprc += delta_qprc;
3000
3001                 hw_stats->qprc[i] += delta_qprc;
3002                 hw_stats->qptc[i] += delta_qptc;
3003
3004                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3005                 hw_stats->qbrc[i] +=
3006                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3007                 if (crc_strip == 0)
3008                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3009
3010                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3011                 hw_stats->qbtc[i] +=
3012                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3013
3014                 hw_stats->qprdc[i] += delta_qprdc;
3015                 *total_qprdc += hw_stats->qprdc[i];
3016
3017                 *total_qprc += hw_stats->qprc[i];
3018                 *total_qbrc += hw_stats->qbrc[i];
3019         }
3020         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3021         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3022         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3023
3024         /*
3025          * An errata states that gprc actually counts good + missed packets:
3026          * Workaround to set gprc to summated queue packet receives
3027          */
3028         hw_stats->gprc = *total_qprc;
3029
3030         if (hw->mac.type != ixgbe_mac_82598EB) {
3031                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3032                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3033                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3034                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3035                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3036                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3037                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3038                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3039         } else {
3040                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3041                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3042                 /* 82598 only has a counter in the high register */
3043                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3044                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3045                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3046         }
3047         uint64_t old_tpr = hw_stats->tpr;
3048
3049         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3050         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3051
3052         if (crc_strip == 0)
3053                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3054
3055         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3056         hw_stats->gptc += delta_gptc;
3057         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3058         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3059
3060         /*
3061          * Workaround: mprc hardware is incorrectly counting
3062          * broadcasts, so for now we subtract those.
3063          */
3064         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3065         hw_stats->bprc += bprc;
3066         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3067         if (hw->mac.type == ixgbe_mac_82598EB)
3068                 hw_stats->mprc -= bprc;
3069
3070         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3071         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3072         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3073         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3074         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3075         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3076
3077         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3078         hw_stats->lxontxc += lxon;
3079         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3080         hw_stats->lxofftxc += lxoff;
3081         total = lxon + lxoff;
3082
3083         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3084         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3085         hw_stats->gptc -= total;
3086         hw_stats->mptc -= total;
3087         hw_stats->ptc64 -= total;
3088         hw_stats->gotc -= total * ETHER_MIN_LEN;
3089
3090         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3091         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3092         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3093         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3094         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3095         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3096         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3097         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3098         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3099         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3100         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3101         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3102         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3103         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3104         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3105         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3106         /* Only read FCOE on 82599 */
3107         if (hw->mac.type != ixgbe_mac_82598EB) {
3108                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3109                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3110                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3111                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3112                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3113         }
3114
3115         /* Flow Director Stats registers */
3116         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3117         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3118
3119         /* MACsec Stats registers */
3120         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3121         macsec_stats->out_pkts_encrypted +=
3122                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3123         macsec_stats->out_pkts_protected +=
3124                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3125         macsec_stats->out_octets_encrypted +=
3126                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3127         macsec_stats->out_octets_protected +=
3128                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3129         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3130         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3131         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3132         macsec_stats->in_pkts_unknownsci +=
3133                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3134         macsec_stats->in_octets_decrypted +=
3135                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3136         macsec_stats->in_octets_validated +=
3137                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3138         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3139         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3140         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3141         for (i = 0; i < 2; i++) {
3142                 macsec_stats->in_pkts_ok +=
3143                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3144                 macsec_stats->in_pkts_invalid +=
3145                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3146                 macsec_stats->in_pkts_notvalid +=
3147                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3148         }
3149         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3150         macsec_stats->in_pkts_notusingsa +=
3151                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3152 }
3153
3154 /*
3155  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3156  */
3157 static int
3158 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3159 {
3160         struct ixgbe_hw *hw =
3161                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3162         struct ixgbe_hw_stats *hw_stats =
3163                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3164         struct ixgbe_macsec_stats *macsec_stats =
3165                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3166                                 dev->data->dev_private);
3167         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3168         unsigned i;
3169
3170         total_missed_rx = 0;
3171         total_qbrc = 0;
3172         total_qprc = 0;
3173         total_qprdc = 0;
3174
3175         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3176                         &total_qbrc, &total_qprc, &total_qprdc);
3177
3178         if (stats == NULL)
3179                 return -EINVAL;
3180
3181         /* Fill out the rte_eth_stats statistics structure */
3182         stats->ipackets = total_qprc;
3183         stats->ibytes = total_qbrc;
3184         stats->opackets = hw_stats->gptc;
3185         stats->obytes = hw_stats->gotc;
3186
3187         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3188                 stats->q_ipackets[i] = hw_stats->qprc[i];
3189                 stats->q_opackets[i] = hw_stats->qptc[i];
3190                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3191                 stats->q_obytes[i] = hw_stats->qbtc[i];
3192                 stats->q_errors[i] = hw_stats->qprdc[i];
3193         }
3194
3195         /* Rx Errors */
3196         stats->imissed  = total_missed_rx;
3197         stats->ierrors  = hw_stats->crcerrs +
3198                           hw_stats->mspdc +
3199                           hw_stats->rlec +
3200                           hw_stats->ruc +
3201                           hw_stats->roc +
3202                           hw_stats->illerrc +
3203                           hw_stats->errbc +
3204                           hw_stats->rfc +
3205                           hw_stats->fccrc +
3206                           hw_stats->fclast;
3207
3208         /* Tx Errors */
3209         stats->oerrors  = 0;
3210         return 0;
3211 }
3212
3213 static void
3214 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3215 {
3216         struct ixgbe_hw_stats *stats =
3217                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3218
3219         /* HW registers are cleared on read */
3220         ixgbe_dev_stats_get(dev, NULL);
3221
3222         /* Reset software totals */
3223         memset(stats, 0, sizeof(*stats));
3224 }
3225
3226 /* This function calculates the number of xstats based on the current config */
3227 static unsigned
3228 ixgbe_xstats_calc_num(void) {
3229         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3230                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3231                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3232 }
3233
3234 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3235         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3236 {
3237         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3238         unsigned stat, i, count;
3239
3240         if (xstats_names != NULL) {
3241                 count = 0;
3242
3243                 /* Note: limit >= cnt_stats checked upstream
3244                  * in rte_eth_xstats_names()
3245                  */
3246
3247                 /* Extended stats from ixgbe_hw_stats */
3248                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3249                         snprintf(xstats_names[count].name,
3250                                 sizeof(xstats_names[count].name),
3251                                 "%s",
3252                                 rte_ixgbe_stats_strings[i].name);
3253                         count++;
3254                 }
3255
3256                 /* MACsec Stats */
3257                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3258                         snprintf(xstats_names[count].name,
3259                                 sizeof(xstats_names[count].name),
3260                                 "%s",
3261                                 rte_ixgbe_macsec_strings[i].name);
3262                         count++;
3263                 }
3264
3265                 /* RX Priority Stats */
3266                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3267                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3268                                 snprintf(xstats_names[count].name,
3269                                         sizeof(xstats_names[count].name),
3270                                         "rx_priority%u_%s", i,
3271                                         rte_ixgbe_rxq_strings[stat].name);
3272                                 count++;
3273                         }
3274                 }
3275
3276                 /* TX Priority Stats */
3277                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3278                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3279                                 snprintf(xstats_names[count].name,
3280                                         sizeof(xstats_names[count].name),
3281                                         "tx_priority%u_%s", i,
3282                                         rte_ixgbe_txq_strings[stat].name);
3283                                 count++;
3284                         }
3285                 }
3286         }
3287         return cnt_stats;
3288 }
3289
3290 static int ixgbe_dev_xstats_get_names_by_id(
3291         struct rte_eth_dev *dev,
3292         struct rte_eth_xstat_name *xstats_names,
3293         const uint64_t *ids,
3294         unsigned int limit)
3295 {
3296         if (!ids) {
3297                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3298                 unsigned int stat, i, count;
3299
3300                 if (xstats_names != NULL) {
3301                         count = 0;
3302
3303                         /* Note: limit >= cnt_stats checked upstream
3304                          * in rte_eth_xstats_names()
3305                          */
3306
3307                         /* Extended stats from ixgbe_hw_stats */
3308                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3309                                 snprintf(xstats_names[count].name,
3310                                         sizeof(xstats_names[count].name),
3311                                         "%s",
3312                                         rte_ixgbe_stats_strings[i].name);
3313                                 count++;
3314                         }
3315
3316                         /* MACsec Stats */
3317                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3318                                 snprintf(xstats_names[count].name,
3319                                         sizeof(xstats_names[count].name),
3320                                         "%s",
3321                                         rte_ixgbe_macsec_strings[i].name);
3322                                 count++;
3323                         }
3324
3325                         /* RX Priority Stats */
3326                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3327                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3328                                         snprintf(xstats_names[count].name,
3329                                             sizeof(xstats_names[count].name),
3330                                             "rx_priority%u_%s", i,
3331                                             rte_ixgbe_rxq_strings[stat].name);
3332                                         count++;
3333                                 }
3334                         }
3335
3336                         /* TX Priority Stats */
3337                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3338                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3339                                         snprintf(xstats_names[count].name,
3340                                             sizeof(xstats_names[count].name),
3341                                             "tx_priority%u_%s", i,
3342                                             rte_ixgbe_txq_strings[stat].name);
3343                                         count++;
3344                                 }
3345                         }
3346                 }
3347                 return cnt_stats;
3348         }
3349
3350         uint16_t i;
3351         uint16_t size = ixgbe_xstats_calc_num();
3352         struct rte_eth_xstat_name xstats_names_copy[size];
3353
3354         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3355                         size);
3356
3357         for (i = 0; i < limit; i++) {
3358                 if (ids[i] >= size) {
3359                         PMD_INIT_LOG(ERR, "id value isn't valid");
3360                         return -1;
3361                 }
3362                 strcpy(xstats_names[i].name,
3363                                 xstats_names_copy[ids[i]].name);
3364         }
3365         return limit;
3366 }
3367
3368 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3369         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3370 {
3371         unsigned i;
3372
3373         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3374                 return -ENOMEM;
3375
3376         if (xstats_names != NULL)
3377                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3378                         snprintf(xstats_names[i].name,
3379                                 sizeof(xstats_names[i].name),
3380                                 "%s", rte_ixgbevf_stats_strings[i].name);
3381         return IXGBEVF_NB_XSTATS;
3382 }
3383
3384 static int
3385 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3386                                          unsigned n)
3387 {
3388         struct ixgbe_hw *hw =
3389                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3390         struct ixgbe_hw_stats *hw_stats =
3391                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3392         struct ixgbe_macsec_stats *macsec_stats =
3393                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3394                                 dev->data->dev_private);
3395         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3396         unsigned i, stat, count = 0;
3397
3398         count = ixgbe_xstats_calc_num();
3399
3400         if (n < count)
3401                 return count;
3402
3403         total_missed_rx = 0;
3404         total_qbrc = 0;
3405         total_qprc = 0;
3406         total_qprdc = 0;
3407
3408         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3409                         &total_qbrc, &total_qprc, &total_qprdc);
3410
3411         /* If this is a reset xstats is NULL, and we have cleared the
3412          * registers by reading them.
3413          */
3414         if (!xstats)
3415                 return 0;
3416
3417         /* Extended stats from ixgbe_hw_stats */
3418         count = 0;
3419         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3420                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3421                                 rte_ixgbe_stats_strings[i].offset);
3422                 xstats[count].id = count;
3423                 count++;
3424         }
3425
3426         /* MACsec Stats */
3427         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3428                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3429                                 rte_ixgbe_macsec_strings[i].offset);
3430                 xstats[count].id = count;
3431                 count++;
3432         }
3433
3434         /* RX Priority Stats */
3435         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3436                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3437                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3438                                         rte_ixgbe_rxq_strings[stat].offset +
3439                                         (sizeof(uint64_t) * i));
3440                         xstats[count].id = count;
3441                         count++;
3442                 }
3443         }
3444
3445         /* TX Priority Stats */
3446         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3447                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3448                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3449                                         rte_ixgbe_txq_strings[stat].offset +
3450                                         (sizeof(uint64_t) * i));
3451                         xstats[count].id = count;
3452                         count++;
3453                 }
3454         }
3455         return count;
3456 }
3457
3458 static int
3459 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3460                 uint64_t *values, unsigned int n)
3461 {
3462         if (!ids) {
3463                 struct ixgbe_hw *hw =
3464                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3465                 struct ixgbe_hw_stats *hw_stats =
3466                                 IXGBE_DEV_PRIVATE_TO_STATS(
3467                                                 dev->data->dev_private);
3468                 struct ixgbe_macsec_stats *macsec_stats =
3469                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3470                                         dev->data->dev_private);
3471                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3472                 unsigned int i, stat, count = 0;
3473
3474                 count = ixgbe_xstats_calc_num();
3475
3476                 if (!ids && n < count)
3477                         return count;
3478
3479                 total_missed_rx = 0;
3480                 total_qbrc = 0;
3481                 total_qprc = 0;
3482                 total_qprdc = 0;
3483
3484                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3485                                 &total_missed_rx, &total_qbrc, &total_qprc,
3486                                 &total_qprdc);
3487
3488                 /* If this is a reset xstats is NULL, and we have cleared the
3489                  * registers by reading them.
3490                  */
3491                 if (!ids && !values)
3492                         return 0;
3493
3494                 /* Extended stats from ixgbe_hw_stats */
3495                 count = 0;
3496                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3497                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3498                                         rte_ixgbe_stats_strings[i].offset);
3499                         count++;
3500                 }
3501
3502                 /* MACsec Stats */
3503                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3504                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3505                                         rte_ixgbe_macsec_strings[i].offset);
3506                         count++;
3507                 }
3508
3509                 /* RX Priority Stats */
3510                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3511                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3512                                 values[count] =
3513                                         *(uint64_t *)(((char *)hw_stats) +
3514                                         rte_ixgbe_rxq_strings[stat].offset +
3515                                         (sizeof(uint64_t) * i));
3516                                 count++;
3517                         }
3518                 }
3519
3520                 /* TX Priority Stats */
3521                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3522                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3523                                 values[count] =
3524                                         *(uint64_t *)(((char *)hw_stats) +
3525                                         rte_ixgbe_txq_strings[stat].offset +
3526                                         (sizeof(uint64_t) * i));
3527                                 count++;
3528                         }
3529                 }
3530                 return count;
3531         }
3532
3533         uint16_t i;
3534         uint16_t size = ixgbe_xstats_calc_num();
3535         uint64_t values_copy[size];
3536
3537         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3538
3539         for (i = 0; i < n; i++) {
3540                 if (ids[i] >= size) {
3541                         PMD_INIT_LOG(ERR, "id value isn't valid");
3542                         return -1;
3543                 }
3544                 values[i] = values_copy[ids[i]];
3545         }
3546         return n;
3547 }
3548
3549 static void
3550 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3551 {
3552         struct ixgbe_hw_stats *stats =
3553                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3554         struct ixgbe_macsec_stats *macsec_stats =
3555                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3556                                 dev->data->dev_private);
3557
3558         unsigned count = ixgbe_xstats_calc_num();
3559
3560         /* HW registers are cleared on read */
3561         ixgbe_dev_xstats_get(dev, NULL, count);
3562
3563         /* Reset software totals */
3564         memset(stats, 0, sizeof(*stats));
3565         memset(macsec_stats, 0, sizeof(*macsec_stats));
3566 }
3567
3568 static void
3569 ixgbevf_update_stats(struct rte_eth_dev *dev)
3570 {
3571         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3573                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3574
3575         /* Good Rx packet, include VF loopback */
3576         UPDATE_VF_STAT(IXGBE_VFGPRC,
3577             hw_stats->last_vfgprc, hw_stats->vfgprc);
3578
3579         /* Good Rx octets, include VF loopback */
3580         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3581             hw_stats->last_vfgorc, hw_stats->vfgorc);
3582
3583         /* Good Tx packet, include VF loopback */
3584         UPDATE_VF_STAT(IXGBE_VFGPTC,
3585             hw_stats->last_vfgptc, hw_stats->vfgptc);
3586
3587         /* Good Tx octets, include VF loopback */
3588         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3589             hw_stats->last_vfgotc, hw_stats->vfgotc);
3590
3591         /* Rx Multicst Packet */
3592         UPDATE_VF_STAT(IXGBE_VFMPRC,
3593             hw_stats->last_vfmprc, hw_stats->vfmprc);
3594 }
3595
3596 static int
3597 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3598                        unsigned n)
3599 {
3600         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3601                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3602         unsigned i;
3603
3604         if (n < IXGBEVF_NB_XSTATS)
3605                 return IXGBEVF_NB_XSTATS;
3606
3607         ixgbevf_update_stats(dev);
3608
3609         if (!xstats)
3610                 return 0;
3611
3612         /* Extended stats */
3613         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3614                 xstats[i].id = i;
3615                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3616                         rte_ixgbevf_stats_strings[i].offset);
3617         }
3618
3619         return IXGBEVF_NB_XSTATS;
3620 }
3621
3622 static int
3623 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3624 {
3625         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3626                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3627
3628         ixgbevf_update_stats(dev);
3629
3630         if (stats == NULL)
3631                 return -EINVAL;
3632
3633         stats->ipackets = hw_stats->vfgprc;
3634         stats->ibytes = hw_stats->vfgorc;
3635         stats->opackets = hw_stats->vfgptc;
3636         stats->obytes = hw_stats->vfgotc;
3637         return 0;
3638 }
3639
3640 static void
3641 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3642 {
3643         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3644                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3645
3646         /* Sync HW register to the last stats */
3647         ixgbevf_dev_stats_get(dev, NULL);
3648
3649         /* reset HW current stats*/
3650         hw_stats->vfgprc = 0;
3651         hw_stats->vfgorc = 0;
3652         hw_stats->vfgptc = 0;
3653         hw_stats->vfgotc = 0;
3654 }
3655
3656 static int
3657 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3658 {
3659         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3660         u16 eeprom_verh, eeprom_verl;
3661         u32 etrack_id;
3662         int ret;
3663
3664         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3665         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3666
3667         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3668         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3669
3670         ret += 1; /* add the size of '\0' */
3671         if (fw_size < (u32)ret)
3672                 return ret;
3673         else
3674                 return 0;
3675 }
3676
3677 static void
3678 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3679 {
3680         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3683
3684         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3685         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3686         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3687                 /*
3688                  * When DCB/VT is off, maximum number of queues changes,
3689                  * except for 82598EB, which remains constant.
3690                  */
3691                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3692                                 hw->mac.type != ixgbe_mac_82598EB)
3693                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3694         }
3695         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3696         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3697         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3698         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3699         dev_info->max_vfs = pci_dev->max_vfs;
3700         if (hw->mac.type == ixgbe_mac_82598EB)
3701                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3702         else
3703                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3704         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3705         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3706         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3707                                      dev_info->rx_queue_offload_capa);
3708         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3709         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3710
3711         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3712                 .rx_thresh = {
3713                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3714                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3715                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3716                 },
3717                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3718                 .rx_drop_en = 0,
3719                 .offloads = 0,
3720         };
3721
3722         dev_info->default_txconf = (struct rte_eth_txconf) {
3723                 .tx_thresh = {
3724                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3725                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3726                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3727                 },
3728                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3729                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3730                 .offloads = 0,
3731         };
3732
3733         dev_info->rx_desc_lim = rx_desc_lim;
3734         dev_info->tx_desc_lim = tx_desc_lim;
3735
3736         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3737         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3738         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3739
3740         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3741         if (hw->mac.type == ixgbe_mac_X540 ||
3742             hw->mac.type == ixgbe_mac_X540_vf ||
3743             hw->mac.type == ixgbe_mac_X550 ||
3744             hw->mac.type == ixgbe_mac_X550_vf) {
3745                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3746         }
3747         if (hw->mac.type == ixgbe_mac_X550) {
3748                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3749                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3750         }
3751 }
3752
3753 static const uint32_t *
3754 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3755 {
3756         static const uint32_t ptypes[] = {
3757                 /* For non-vec functions,
3758                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3759                  * for vec functions,
3760                  * refers to _recv_raw_pkts_vec().
3761                  */
3762                 RTE_PTYPE_L2_ETHER,
3763                 RTE_PTYPE_L3_IPV4,
3764                 RTE_PTYPE_L3_IPV4_EXT,
3765                 RTE_PTYPE_L3_IPV6,
3766                 RTE_PTYPE_L3_IPV6_EXT,
3767                 RTE_PTYPE_L4_SCTP,
3768                 RTE_PTYPE_L4_TCP,
3769                 RTE_PTYPE_L4_UDP,
3770                 RTE_PTYPE_TUNNEL_IP,
3771                 RTE_PTYPE_INNER_L3_IPV6,
3772                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3773                 RTE_PTYPE_INNER_L4_TCP,
3774                 RTE_PTYPE_INNER_L4_UDP,
3775                 RTE_PTYPE_UNKNOWN
3776         };
3777
3778         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3779             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3780             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3781             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3782                 return ptypes;
3783
3784 #if defined(RTE_ARCH_X86)
3785         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3786             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3787                 return ptypes;
3788 #endif
3789         return NULL;
3790 }
3791
3792 static void
3793 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3794                      struct rte_eth_dev_info *dev_info)
3795 {
3796         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3797         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3798
3799         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3800         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3801         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3802         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3803         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3804         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3805         dev_info->max_vfs = pci_dev->max_vfs;
3806         if (hw->mac.type == ixgbe_mac_82598EB)
3807                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3808         else
3809                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3810         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3811         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3812                                      dev_info->rx_queue_offload_capa);
3813         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3814         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3815
3816         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3817                 .rx_thresh = {
3818                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3819                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3820                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3821                 },
3822                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3823                 .rx_drop_en = 0,
3824                 .offloads = 0,
3825         };
3826
3827         dev_info->default_txconf = (struct rte_eth_txconf) {
3828                 .tx_thresh = {
3829                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3830                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3831                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3832                 },
3833                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3834                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3835                 .offloads = 0,
3836         };
3837
3838         dev_info->rx_desc_lim = rx_desc_lim;
3839         dev_info->tx_desc_lim = tx_desc_lim;
3840 }
3841
3842 static int
3843 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3844                    int *link_up, int wait_to_complete)
3845 {
3846         /**
3847          * for a quick link status checking, wait_to_compelet == 0,
3848          * skip PF link status checking
3849          */
3850         bool no_pflink_check = wait_to_complete == 0;
3851         struct ixgbe_mbx_info *mbx = &hw->mbx;
3852         struct ixgbe_mac_info *mac = &hw->mac;
3853         uint32_t links_reg, in_msg;
3854         int ret_val = 0;
3855
3856         /* If we were hit with a reset drop the link */
3857         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3858                 mac->get_link_status = true;
3859
3860         if (!mac->get_link_status)
3861                 goto out;
3862
3863         /* if link status is down no point in checking to see if pf is up */
3864         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3865         if (!(links_reg & IXGBE_LINKS_UP))
3866                 goto out;
3867
3868         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3869          * before the link status is correct
3870          */
3871         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3872                 int i;
3873
3874                 for (i = 0; i < 5; i++) {
3875                         rte_delay_us(100);
3876                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3877
3878                         if (!(links_reg & IXGBE_LINKS_UP))
3879                                 goto out;
3880                 }
3881         }
3882
3883         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3884         case IXGBE_LINKS_SPEED_10G_82599:
3885                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3886                 if (hw->mac.type >= ixgbe_mac_X550) {
3887                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3888                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3889                 }
3890                 break;
3891         case IXGBE_LINKS_SPEED_1G_82599:
3892                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3893                 break;
3894         case IXGBE_LINKS_SPEED_100_82599:
3895                 *speed = IXGBE_LINK_SPEED_100_FULL;
3896                 if (hw->mac.type == ixgbe_mac_X550) {
3897                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3898                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3899                 }
3900                 break;
3901         case IXGBE_LINKS_SPEED_10_X550EM_A:
3902                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3903                 /* Since Reserved in older MAC's */
3904                 if (hw->mac.type >= ixgbe_mac_X550)
3905                         *speed = IXGBE_LINK_SPEED_10_FULL;
3906                 break;
3907         default:
3908                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3909         }
3910
3911         if (no_pflink_check) {
3912                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3913                         mac->get_link_status = true;
3914                 else
3915                         mac->get_link_status = false;
3916
3917                 goto out;
3918         }
3919         /* if the read failed it could just be a mailbox collision, best wait
3920          * until we are called again and don't report an error
3921          */
3922         if (mbx->ops.read(hw, &in_msg, 1, 0))
3923                 goto out;
3924
3925         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3926                 /* msg is not CTS and is NACK we must have lost CTS status */
3927                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3928                         ret_val = -1;
3929                 goto out;
3930         }
3931
3932         /* the pf is talking, if we timed out in the past we reinit */
3933         if (!mbx->timeout) {
3934                 ret_val = -1;
3935                 goto out;
3936         }
3937
3938         /* if we passed all the tests above then the link is up and we no
3939          * longer need to check for link
3940          */
3941         mac->get_link_status = false;
3942
3943 out:
3944         *link_up = !mac->get_link_status;
3945         return ret_val;
3946 }
3947
3948 /* return 0 means link status changed, -1 means not changed */
3949 int
3950 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3951                             int wait_to_complete, int vf)
3952 {
3953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3954         struct rte_eth_link link;
3955         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3956         struct ixgbe_interrupt *intr =
3957                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3958         int link_up;
3959         int diag;
3960         u32 speed = 0;
3961         int wait = 1;
3962         bool autoneg = false;
3963
3964         memset(&link, 0, sizeof(link));
3965         link.link_status = ETH_LINK_DOWN;
3966         link.link_speed = ETH_SPEED_NUM_NONE;
3967         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3968         link.link_autoneg = ETH_LINK_AUTONEG;
3969
3970         hw->mac.get_link_status = true;
3971
3972         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3973                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3974                 speed = hw->phy.autoneg_advertised;
3975                 if (!speed)
3976                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3977                 ixgbe_setup_link(hw, speed, true);
3978         }
3979
3980         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3981         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3982                 wait = 0;
3983
3984         if (vf)
3985                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3986         else
3987                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3988
3989         if (diag != 0) {
3990                 link.link_speed = ETH_SPEED_NUM_100M;
3991                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3992                 return rte_eth_linkstatus_set(dev, &link);
3993         }
3994
3995         if (link_up == 0) {
3996                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3997                 return rte_eth_linkstatus_set(dev, &link);
3998         }
3999
4000         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4001         link.link_status = ETH_LINK_UP;
4002         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4003
4004         switch (link_speed) {
4005         default:
4006         case IXGBE_LINK_SPEED_UNKNOWN:
4007                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4008                 link.link_speed = ETH_SPEED_NUM_100M;
4009                 break;
4010
4011         case IXGBE_LINK_SPEED_100_FULL:
4012                 link.link_speed = ETH_SPEED_NUM_100M;
4013                 break;
4014
4015         case IXGBE_LINK_SPEED_1GB_FULL:
4016                 link.link_speed = ETH_SPEED_NUM_1G;
4017                 break;
4018
4019         case IXGBE_LINK_SPEED_2_5GB_FULL:
4020                 link.link_speed = ETH_SPEED_NUM_2_5G;
4021                 break;
4022
4023         case IXGBE_LINK_SPEED_5GB_FULL:
4024                 link.link_speed = ETH_SPEED_NUM_5G;
4025                 break;
4026
4027         case IXGBE_LINK_SPEED_10GB_FULL:
4028                 link.link_speed = ETH_SPEED_NUM_10G;
4029                 break;
4030         }
4031
4032         return rte_eth_linkstatus_set(dev, &link);
4033 }
4034
4035 static int
4036 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4037 {
4038         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4039 }
4040
4041 static int
4042 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4043 {
4044         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4045 }
4046
4047 static void
4048 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4049 {
4050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4051         uint32_t fctrl;
4052
4053         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4054         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4055         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4056 }
4057
4058 static void
4059 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4060 {
4061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4062         uint32_t fctrl;
4063
4064         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4065         fctrl &= (~IXGBE_FCTRL_UPE);
4066         if (dev->data->all_multicast == 1)
4067                 fctrl |= IXGBE_FCTRL_MPE;
4068         else
4069                 fctrl &= (~IXGBE_FCTRL_MPE);
4070         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4071 }
4072
4073 static void
4074 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4075 {
4076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4077         uint32_t fctrl;
4078
4079         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4080         fctrl |= IXGBE_FCTRL_MPE;
4081         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4082 }
4083
4084 static void
4085 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4086 {
4087         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4088         uint32_t fctrl;
4089
4090         if (dev->data->promiscuous == 1)
4091                 return; /* must remain in all_multicast mode */
4092
4093         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4094         fctrl &= (~IXGBE_FCTRL_MPE);
4095         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4096 }
4097
4098 /**
4099  * It clears the interrupt causes and enables the interrupt.
4100  * It will be called once only during nic initialized.
4101  *
4102  * @param dev
4103  *  Pointer to struct rte_eth_dev.
4104  * @param on
4105  *  Enable or Disable.
4106  *
4107  * @return
4108  *  - On success, zero.
4109  *  - On failure, a negative value.
4110  */
4111 static int
4112 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4113 {
4114         struct ixgbe_interrupt *intr =
4115                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4116
4117         ixgbe_dev_link_status_print(dev);
4118         if (on)
4119                 intr->mask |= IXGBE_EICR_LSC;
4120         else
4121                 intr->mask &= ~IXGBE_EICR_LSC;
4122
4123         return 0;
4124 }
4125
4126 /**
4127  * It clears the interrupt causes and enables the interrupt.
4128  * It will be called once only during nic initialized.
4129  *
4130  * @param dev
4131  *  Pointer to struct rte_eth_dev.
4132  *
4133  * @return
4134  *  - On success, zero.
4135  *  - On failure, a negative value.
4136  */
4137 static int
4138 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4139 {
4140         struct ixgbe_interrupt *intr =
4141                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4142
4143         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4144
4145         return 0;
4146 }
4147
4148 /**
4149  * It clears the interrupt causes and enables the interrupt.
4150  * It will be called once only during nic initialized.
4151  *
4152  * @param dev
4153  *  Pointer to struct rte_eth_dev.
4154  *
4155  * @return
4156  *  - On success, zero.
4157  *  - On failure, a negative value.
4158  */
4159 static int
4160 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4161 {
4162         struct ixgbe_interrupt *intr =
4163                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4164
4165         intr->mask |= IXGBE_EICR_LINKSEC;
4166
4167         return 0;
4168 }
4169
4170 /*
4171  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4172  *
4173  * @param dev
4174  *  Pointer to struct rte_eth_dev.
4175  *
4176  * @return
4177  *  - On success, zero.
4178  *  - On failure, a negative value.
4179  */
4180 static int
4181 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4182 {
4183         uint32_t eicr;
4184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4185         struct ixgbe_interrupt *intr =
4186                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4187
4188         /* clear all cause mask */
4189         ixgbe_disable_intr(hw);
4190
4191         /* read-on-clear nic registers here */
4192         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4193         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4194
4195         intr->flags = 0;
4196
4197         /* set flag for async link update */
4198         if (eicr & IXGBE_EICR_LSC)
4199                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4200
4201         if (eicr & IXGBE_EICR_MAILBOX)
4202                 intr->flags |= IXGBE_FLAG_MAILBOX;
4203
4204         if (eicr & IXGBE_EICR_LINKSEC)
4205                 intr->flags |= IXGBE_FLAG_MACSEC;
4206
4207         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4208             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4209             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4210                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4211
4212         return 0;
4213 }
4214
4215 /**
4216  * It gets and then prints the link status.
4217  *
4218  * @param dev
4219  *  Pointer to struct rte_eth_dev.
4220  *
4221  * @return
4222  *  - On success, zero.
4223  *  - On failure, a negative value.
4224  */
4225 static void
4226 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4227 {
4228         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4229         struct rte_eth_link link;
4230
4231         rte_eth_linkstatus_get(dev, &link);
4232
4233         if (link.link_status) {
4234                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4235                                         (int)(dev->data->port_id),
4236                                         (unsigned)link.link_speed,
4237                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4238                                         "full-duplex" : "half-duplex");
4239         } else {
4240                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4241                                 (int)(dev->data->port_id));
4242         }
4243         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4244                                 pci_dev->addr.domain,
4245                                 pci_dev->addr.bus,
4246                                 pci_dev->addr.devid,
4247                                 pci_dev->addr.function);
4248 }
4249
4250 /*
4251  * It executes link_update after knowing an interrupt occurred.
4252  *
4253  * @param dev
4254  *  Pointer to struct rte_eth_dev.
4255  *
4256  * @return
4257  *  - On success, zero.
4258  *  - On failure, a negative value.
4259  */
4260 static int
4261 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4262                            struct rte_intr_handle *intr_handle)
4263 {
4264         struct ixgbe_interrupt *intr =
4265                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4266         int64_t timeout;
4267         struct ixgbe_hw *hw =
4268                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4269
4270         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4271
4272         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4273                 ixgbe_pf_mbx_process(dev);
4274                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4275         }
4276
4277         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4278                 ixgbe_handle_lasi(hw);
4279                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4280         }
4281
4282         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4283                 struct rte_eth_link link;
4284
4285                 /* get the link status before link update, for predicting later */
4286                 rte_eth_linkstatus_get(dev, &link);
4287
4288                 ixgbe_dev_link_update(dev, 0);
4289
4290                 /* likely to up */
4291                 if (!link.link_status)
4292                         /* handle it 1 sec later, wait it being stable */
4293                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4294                 /* likely to down */
4295                 else
4296                         /* handle it 4 sec later, wait it being stable */
4297                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4298
4299                 ixgbe_dev_link_status_print(dev);
4300                 if (rte_eal_alarm_set(timeout * 1000,
4301                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4302                         PMD_DRV_LOG(ERR, "Error setting alarm");
4303                 else {
4304                         /* remember original mask */
4305                         intr->mask_original = intr->mask;
4306                         /* only disable lsc interrupt */
4307                         intr->mask &= ~IXGBE_EIMS_LSC;
4308                 }
4309         }
4310
4311         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4312         ixgbe_enable_intr(dev);
4313         rte_intr_enable(intr_handle);
4314
4315         return 0;
4316 }
4317
4318 /**
4319  * Interrupt handler which shall be registered for alarm callback for delayed
4320  * handling specific interrupt to wait for the stable nic state. As the
4321  * NIC interrupt state is not stable for ixgbe after link is just down,
4322  * it needs to wait 4 seconds to get the stable status.
4323  *
4324  * @param handle
4325  *  Pointer to interrupt handle.
4326  * @param param
4327  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4328  *
4329  * @return
4330  *  void
4331  */
4332 static void
4333 ixgbe_dev_interrupt_delayed_handler(void *param)
4334 {
4335         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4336         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4337         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4338         struct ixgbe_interrupt *intr =
4339                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4340         struct ixgbe_hw *hw =
4341                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342         uint32_t eicr;
4343
4344         ixgbe_disable_intr(hw);
4345
4346         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4347         if (eicr & IXGBE_EICR_MAILBOX)
4348                 ixgbe_pf_mbx_process(dev);
4349
4350         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4351                 ixgbe_handle_lasi(hw);
4352                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4353         }
4354
4355         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4356                 ixgbe_dev_link_update(dev, 0);
4357                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4358                 ixgbe_dev_link_status_print(dev);
4359                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4360                                               NULL);
4361         }
4362
4363         if (intr->flags & IXGBE_FLAG_MACSEC) {
4364                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4365                                               NULL);
4366                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4367         }
4368
4369         /* restore original mask */
4370         intr->mask = intr->mask_original;
4371         intr->mask_original = 0;
4372
4373         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4374         ixgbe_enable_intr(dev);
4375         rte_intr_enable(intr_handle);
4376 }
4377
4378 /**
4379  * Interrupt handler triggered by NIC  for handling
4380  * specific interrupt.
4381  *
4382  * @param handle
4383  *  Pointer to interrupt handle.
4384  * @param param
4385  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4386  *
4387  * @return
4388  *  void
4389  */
4390 static void
4391 ixgbe_dev_interrupt_handler(void *param)
4392 {
4393         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4394
4395         ixgbe_dev_interrupt_get_status(dev);
4396         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4397 }
4398
4399 static int
4400 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4401 {
4402         struct ixgbe_hw *hw;
4403
4404         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4405         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4406 }
4407
4408 static int
4409 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4410 {
4411         struct ixgbe_hw *hw;
4412
4413         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4414         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4415 }
4416
4417 static int
4418 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4419 {
4420         struct ixgbe_hw *hw;
4421         uint32_t mflcn_reg;
4422         uint32_t fccfg_reg;
4423         int rx_pause;
4424         int tx_pause;
4425
4426         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4427
4428         fc_conf->pause_time = hw->fc.pause_time;
4429         fc_conf->high_water = hw->fc.high_water[0];
4430         fc_conf->low_water = hw->fc.low_water[0];
4431         fc_conf->send_xon = hw->fc.send_xon;
4432         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4433
4434         /*
4435          * Return rx_pause status according to actual setting of
4436          * MFLCN register.
4437          */
4438         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4439         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4440                 rx_pause = 1;
4441         else
4442                 rx_pause = 0;
4443
4444         /*
4445          * Return tx_pause status according to actual setting of
4446          * FCCFG register.
4447          */
4448         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4449         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4450                 tx_pause = 1;
4451         else
4452                 tx_pause = 0;
4453
4454         if (rx_pause && tx_pause)
4455                 fc_conf->mode = RTE_FC_FULL;
4456         else if (rx_pause)
4457                 fc_conf->mode = RTE_FC_RX_PAUSE;
4458         else if (tx_pause)
4459                 fc_conf->mode = RTE_FC_TX_PAUSE;
4460         else
4461                 fc_conf->mode = RTE_FC_NONE;
4462
4463         return 0;
4464 }
4465
4466 static int
4467 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4468 {
4469         struct ixgbe_hw *hw;
4470         int err;
4471         uint32_t rx_buf_size;
4472         uint32_t max_high_water;
4473         uint32_t mflcn;
4474         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4475                 ixgbe_fc_none,
4476                 ixgbe_fc_rx_pause,
4477                 ixgbe_fc_tx_pause,
4478                 ixgbe_fc_full
4479         };
4480
4481         PMD_INIT_FUNC_TRACE();
4482
4483         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4485         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4486
4487         /*
4488          * At least reserve one Ethernet frame for watermark
4489          * high_water/low_water in kilo bytes for ixgbe
4490          */
4491         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4492         if ((fc_conf->high_water > max_high_water) ||
4493                 (fc_conf->high_water < fc_conf->low_water)) {
4494                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4495                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4496                 return -EINVAL;
4497         }
4498
4499         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4500         hw->fc.pause_time     = fc_conf->pause_time;
4501         hw->fc.high_water[0]  = fc_conf->high_water;
4502         hw->fc.low_water[0]   = fc_conf->low_water;
4503         hw->fc.send_xon       = fc_conf->send_xon;
4504         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4505
4506         err = ixgbe_fc_enable(hw);
4507
4508         /* Not negotiated is not an error case */
4509         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4510
4511                 /* check if we want to forward MAC frames - driver doesn't have native
4512                  * capability to do that, so we'll write the registers ourselves */
4513
4514                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4515
4516                 /* set or clear MFLCN.PMCF bit depending on configuration */
4517                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4518                         mflcn |= IXGBE_MFLCN_PMCF;
4519                 else
4520                         mflcn &= ~IXGBE_MFLCN_PMCF;
4521
4522                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4523                 IXGBE_WRITE_FLUSH(hw);
4524
4525                 return 0;
4526         }
4527
4528         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4529         return -EIO;
4530 }
4531
4532 /**
4533  *  ixgbe_pfc_enable_generic - Enable flow control
4534  *  @hw: pointer to hardware structure
4535  *  @tc_num: traffic class number
4536  *  Enable flow control according to the current settings.
4537  */
4538 static int
4539 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4540 {
4541         int ret_val = 0;
4542         uint32_t mflcn_reg, fccfg_reg;
4543         uint32_t reg;
4544         uint32_t fcrtl, fcrth;
4545         uint8_t i;
4546         uint8_t nb_rx_en;
4547
4548         /* Validate the water mark configuration */
4549         if (!hw->fc.pause_time) {
4550                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4551                 goto out;
4552         }
4553
4554         /* Low water mark of zero causes XOFF floods */
4555         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4556                  /* High/Low water can not be 0 */
4557                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4558                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4559                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4560                         goto out;
4561                 }
4562
4563                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4564                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4565                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4566                         goto out;
4567                 }
4568         }
4569         /* Negotiate the fc mode to use */
4570         ixgbe_fc_autoneg(hw);
4571
4572         /* Disable any previous flow control settings */
4573         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4574         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4575
4576         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4577         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4578
4579         switch (hw->fc.current_mode) {
4580         case ixgbe_fc_none:
4581                 /*
4582                  * If the count of enabled RX Priority Flow control >1,
4583                  * and the TX pause can not be disabled
4584                  */
4585                 nb_rx_en = 0;
4586                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4587                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4588                         if (reg & IXGBE_FCRTH_FCEN)
4589                                 nb_rx_en++;
4590                 }
4591                 if (nb_rx_en > 1)
4592                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4593                 break;
4594         case ixgbe_fc_rx_pause:
4595                 /*
4596                  * Rx Flow control is enabled and Tx Flow control is
4597                  * disabled by software override. Since there really
4598                  * isn't a way to advertise that we are capable of RX
4599                  * Pause ONLY, we will advertise that we support both
4600                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4601                  * disable the adapter's ability to send PAUSE frames.
4602                  */
4603                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4604                 /*
4605                  * If the count of enabled RX Priority Flow control >1,
4606                  * and the TX pause can not be disabled
4607                  */
4608                 nb_rx_en = 0;
4609                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4610                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4611                         if (reg & IXGBE_FCRTH_FCEN)
4612                                 nb_rx_en++;
4613                 }
4614                 if (nb_rx_en > 1)
4615                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4616                 break;
4617         case ixgbe_fc_tx_pause:
4618                 /*
4619                  * Tx Flow control is enabled, and Rx Flow control is
4620                  * disabled by software override.
4621                  */
4622                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4623                 break;
4624         case ixgbe_fc_full:
4625                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4626                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4627                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4628                 break;
4629         default:
4630                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4631                 ret_val = IXGBE_ERR_CONFIG;
4632                 goto out;
4633         }
4634
4635         /* Set 802.3x based flow control settings. */
4636         mflcn_reg |= IXGBE_MFLCN_DPF;
4637         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4638         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4639
4640         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4641         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4642                 hw->fc.high_water[tc_num]) {
4643                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4644                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4645                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4646         } else {
4647                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4648                 /*
4649                  * In order to prevent Tx hangs when the internal Tx
4650                  * switch is enabled we must set the high water mark
4651                  * to the maximum FCRTH value.  This allows the Tx
4652                  * switch to function even under heavy Rx workloads.
4653                  */
4654                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4655         }
4656         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4657
4658         /* Configure pause time (2 TCs per register) */
4659         reg = hw->fc.pause_time * 0x00010001;
4660         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4661                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4662
4663         /* Configure flow control refresh threshold value */
4664         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4665
4666 out:
4667         return ret_val;
4668 }
4669
4670 static int
4671 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4672 {
4673         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4674         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4675
4676         if (hw->mac.type != ixgbe_mac_82598EB) {
4677                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4678         }
4679         return ret_val;
4680 }
4681
4682 static int
4683 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4684 {
4685         int err;
4686         uint32_t rx_buf_size;
4687         uint32_t max_high_water;
4688         uint8_t tc_num;
4689         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4690         struct ixgbe_hw *hw =
4691                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4692         struct ixgbe_dcb_config *dcb_config =
4693                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4694
4695         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4696                 ixgbe_fc_none,
4697                 ixgbe_fc_rx_pause,
4698                 ixgbe_fc_tx_pause,
4699                 ixgbe_fc_full
4700         };
4701
4702         PMD_INIT_FUNC_TRACE();
4703
4704         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4705         tc_num = map[pfc_conf->priority];
4706         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4707         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4708         /*
4709          * At least reserve one Ethernet frame for watermark
4710          * high_water/low_water in kilo bytes for ixgbe
4711          */
4712         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4713         if ((pfc_conf->fc.high_water > max_high_water) ||
4714             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4715                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4716                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4717                 return -EINVAL;
4718         }
4719
4720         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4721         hw->fc.pause_time = pfc_conf->fc.pause_time;
4722         hw->fc.send_xon = pfc_conf->fc.send_xon;
4723         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4724         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4725
4726         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4727
4728         /* Not negotiated is not an error case */
4729         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4730                 return 0;
4731
4732         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4733         return -EIO;
4734 }
4735
4736 static int
4737 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4738                           struct rte_eth_rss_reta_entry64 *reta_conf,
4739                           uint16_t reta_size)
4740 {
4741         uint16_t i, sp_reta_size;
4742         uint8_t j, mask;
4743         uint32_t reta, r;
4744         uint16_t idx, shift;
4745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4746         uint32_t reta_reg;
4747
4748         PMD_INIT_FUNC_TRACE();
4749
4750         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4751                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4752                         "NIC.");
4753                 return -ENOTSUP;
4754         }
4755
4756         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4757         if (reta_size != sp_reta_size) {
4758                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4759                         "(%d) doesn't match the number hardware can supported "
4760                         "(%d)", reta_size, sp_reta_size);
4761                 return -EINVAL;
4762         }
4763
4764         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4765                 idx = i / RTE_RETA_GROUP_SIZE;
4766                 shift = i % RTE_RETA_GROUP_SIZE;
4767                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4768                                                 IXGBE_4_BIT_MASK);
4769                 if (!mask)
4770                         continue;
4771                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4772                 if (mask == IXGBE_4_BIT_MASK)
4773                         r = 0;
4774                 else
4775                         r = IXGBE_READ_REG(hw, reta_reg);
4776                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4777                         if (mask & (0x1 << j))
4778                                 reta |= reta_conf[idx].reta[shift + j] <<
4779                                                         (CHAR_BIT * j);
4780                         else
4781                                 reta |= r & (IXGBE_8_BIT_MASK <<
4782                                                 (CHAR_BIT * j));
4783                 }
4784                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4785         }
4786
4787         return 0;
4788 }
4789
4790 static int
4791 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4792                          struct rte_eth_rss_reta_entry64 *reta_conf,
4793                          uint16_t reta_size)
4794 {
4795         uint16_t i, sp_reta_size;
4796         uint8_t j, mask;
4797         uint32_t reta;
4798         uint16_t idx, shift;
4799         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800         uint32_t reta_reg;
4801
4802         PMD_INIT_FUNC_TRACE();
4803         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4804         if (reta_size != sp_reta_size) {
4805                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4806                         "(%d) doesn't match the number hardware can supported "
4807                         "(%d)", reta_size, sp_reta_size);
4808                 return -EINVAL;
4809         }
4810
4811         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4812                 idx = i / RTE_RETA_GROUP_SIZE;
4813                 shift = i % RTE_RETA_GROUP_SIZE;
4814                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4815                                                 IXGBE_4_BIT_MASK);
4816                 if (!mask)
4817                         continue;
4818
4819                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4820                 reta = IXGBE_READ_REG(hw, reta_reg);
4821                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4822                         if (mask & (0x1 << j))
4823                                 reta_conf[idx].reta[shift + j] =
4824                                         ((reta >> (CHAR_BIT * j)) &
4825                                                 IXGBE_8_BIT_MASK);
4826                 }
4827         }
4828
4829         return 0;
4830 }
4831
4832 static int
4833 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4834                                 uint32_t index, uint32_t pool)
4835 {
4836         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4837         uint32_t enable_addr = 1;
4838
4839         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4840                              pool, enable_addr);
4841 }
4842
4843 static void
4844 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4845 {
4846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4847
4848         ixgbe_clear_rar(hw, index);
4849 }
4850
4851 static int
4852 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4853 {
4854         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4855
4856         ixgbe_remove_rar(dev, 0);
4857         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4858
4859         return 0;
4860 }
4861
4862 static bool
4863 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4864 {
4865         if (strcmp(dev->device->driver->name, drv->driver.name))
4866                 return false;
4867
4868         return true;
4869 }
4870
4871 bool
4872 is_ixgbe_supported(struct rte_eth_dev *dev)
4873 {
4874         return is_device_supported(dev, &rte_ixgbe_pmd);
4875 }
4876
4877 static int
4878 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4879 {
4880         uint32_t hlreg0;
4881         uint32_t maxfrs;
4882         struct ixgbe_hw *hw;
4883         struct rte_eth_dev_info dev_info;
4884         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4885         struct rte_eth_dev_data *dev_data = dev->data;
4886
4887         ixgbe_dev_info_get(dev, &dev_info);
4888
4889         /* check that mtu is within the allowed range */
4890         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4891                 return -EINVAL;
4892
4893         /* If device is started, refuse mtu that requires the support of
4894          * scattered packets when this feature has not been enabled before.
4895          */
4896         if (dev_data->dev_started && !dev_data->scattered_rx &&
4897             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4898              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4899                 PMD_INIT_LOG(ERR, "Stop port first.");
4900                 return -EINVAL;
4901         }
4902
4903         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4904         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4905
4906         /* switch to jumbo mode if needed */
4907         if (frame_size > ETHER_MAX_LEN) {
4908                 dev->data->dev_conf.rxmode.offloads |=
4909                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4910                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4911         } else {
4912                 dev->data->dev_conf.rxmode.offloads &=
4913                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4914                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4915         }
4916         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4917
4918         /* update max frame size */
4919         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4920
4921         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4922         maxfrs &= 0x0000FFFF;
4923         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4924         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4925
4926         return 0;
4927 }
4928
4929 /*
4930  * Virtual Function operations
4931  */
4932 static void
4933 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4934 {
4935         PMD_INIT_FUNC_TRACE();
4936
4937         /* Clear interrupt mask to stop from interrupts being generated */
4938         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4939
4940         IXGBE_WRITE_FLUSH(hw);
4941 }
4942
4943 static void
4944 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4945 {
4946         PMD_INIT_FUNC_TRACE();
4947
4948         /* VF enable interrupt autoclean */
4949         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4950         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4951         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4952
4953         IXGBE_WRITE_FLUSH(hw);
4954 }
4955
4956 static int
4957 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4958 {
4959         struct rte_eth_conf *conf = &dev->data->dev_conf;
4960         struct ixgbe_adapter *adapter =
4961                         (struct ixgbe_adapter *)dev->data->dev_private;
4962         struct rte_eth_dev_info dev_info;
4963         uint64_t rx_offloads;
4964         uint64_t tx_offloads;
4965
4966         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4967                      dev->data->port_id);
4968
4969         ixgbevf_dev_info_get(dev, &dev_info);
4970         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4971         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4972                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4973                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4974                             rx_offloads, dev_info.rx_offload_capa);
4975                 return -ENOTSUP;
4976         }
4977         tx_offloads = dev->data->dev_conf.txmode.offloads;
4978         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4979                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4980                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4981                             tx_offloads, dev_info.tx_offload_capa);
4982                 return -ENOTSUP;
4983         }
4984
4985         /*
4986          * VF has no ability to enable/disable HW CRC
4987          * Keep the persistent behavior the same as Host PF
4988          */
4989 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4990         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4991                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4992                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4993         }
4994 #else
4995         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4996                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4997                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4998         }
4999 #endif
5000
5001         /*
5002          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5003          * allocation or vector Rx preconditions we will reset it.
5004          */
5005         adapter->rx_bulk_alloc_allowed = true;
5006         adapter->rx_vec_allowed = true;
5007
5008         return 0;
5009 }
5010
5011 static int
5012 ixgbevf_dev_start(struct rte_eth_dev *dev)
5013 {
5014         struct ixgbe_hw *hw =
5015                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5016         uint32_t intr_vector = 0;
5017         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5018         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5019
5020         int err, mask = 0;
5021
5022         PMD_INIT_FUNC_TRACE();
5023
5024         err = hw->mac.ops.reset_hw(hw);
5025         if (err) {
5026                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5027                 return err;
5028         }
5029         hw->mac.get_link_status = true;
5030
5031         /* negotiate mailbox API version to use with the PF. */
5032         ixgbevf_negotiate_api(hw);
5033
5034         ixgbevf_dev_tx_init(dev);
5035
5036         /* This can fail when allocating mbufs for descriptor rings */
5037         err = ixgbevf_dev_rx_init(dev);
5038         if (err) {
5039                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5040                 ixgbe_dev_clear_queues(dev);
5041                 return err;
5042         }
5043
5044         /* Set vfta */
5045         ixgbevf_set_vfta_all(dev, 1);
5046
5047         /* Set HW strip */
5048         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5049                 ETH_VLAN_EXTEND_MASK;
5050         err = ixgbevf_vlan_offload_set(dev, mask);
5051         if (err) {
5052                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5053                 ixgbe_dev_clear_queues(dev);
5054                 return err;
5055         }
5056
5057         ixgbevf_dev_rxtx_start(dev);
5058
5059         ixgbevf_dev_link_update(dev, 0);
5060
5061         /* check and configure queue intr-vector mapping */
5062         if (rte_intr_cap_multiple(intr_handle) &&
5063             dev->data->dev_conf.intr_conf.rxq) {
5064                 /* According to datasheet, only vector 0/1/2 can be used,
5065                  * now only one vector is used for Rx queue
5066                  */
5067                 intr_vector = 1;
5068                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5069                         return -1;
5070         }
5071
5072         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5073                 intr_handle->intr_vec =
5074                         rte_zmalloc("intr_vec",
5075                                     dev->data->nb_rx_queues * sizeof(int), 0);
5076                 if (intr_handle->intr_vec == NULL) {
5077                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5078                                      " intr_vec", dev->data->nb_rx_queues);
5079                         return -ENOMEM;
5080                 }
5081         }
5082         ixgbevf_configure_msix(dev);
5083
5084         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5085          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5086          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5087          * is not cleared, it will fail when following rte_intr_enable( ) tries
5088          * to map Rx queue interrupt to other VFIO vectors.
5089          * So clear uio/vfio intr/evevnfd first to avoid failure.
5090          */
5091         rte_intr_disable(intr_handle);
5092
5093         rte_intr_enable(intr_handle);
5094
5095         /* Re-enable interrupt for VF */
5096         ixgbevf_intr_enable(hw);
5097
5098         return 0;
5099 }
5100
5101 static void
5102 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5103 {
5104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5105         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5106         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5107
5108         PMD_INIT_FUNC_TRACE();
5109
5110         ixgbevf_intr_disable(hw);
5111
5112         hw->adapter_stopped = 1;
5113         ixgbe_stop_adapter(hw);
5114
5115         /*
5116           * Clear what we set, but we still keep shadow_vfta to
5117           * restore after device starts
5118           */
5119         ixgbevf_set_vfta_all(dev, 0);
5120
5121         /* Clear stored conf */
5122         dev->data->scattered_rx = 0;
5123
5124         ixgbe_dev_clear_queues(dev);
5125
5126         /* Clean datapath event and queue/vec mapping */
5127         rte_intr_efd_disable(intr_handle);
5128         if (intr_handle->intr_vec != NULL) {
5129                 rte_free(intr_handle->intr_vec);
5130                 intr_handle->intr_vec = NULL;
5131         }
5132 }
5133
5134 static void
5135 ixgbevf_dev_close(struct rte_eth_dev *dev)
5136 {
5137         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5138
5139         PMD_INIT_FUNC_TRACE();
5140
5141         ixgbe_reset_hw(hw);
5142
5143         ixgbevf_dev_stop(dev);
5144
5145         ixgbe_dev_free_queues(dev);
5146
5147         /**
5148          * Remove the VF MAC address ro ensure
5149          * that the VF traffic goes to the PF
5150          * after stop, close and detach of the VF
5151          **/
5152         ixgbevf_remove_mac_addr(dev, 0);
5153 }
5154
5155 /*
5156  * Reset VF device
5157  */
5158 static int
5159 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5160 {
5161         int ret;
5162
5163         ret = eth_ixgbevf_dev_uninit(dev);
5164         if (ret)
5165                 return ret;
5166
5167         ret = eth_ixgbevf_dev_init(dev);
5168
5169         return ret;
5170 }
5171
5172 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5173 {
5174         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5175         struct ixgbe_vfta *shadow_vfta =
5176                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5177         int i = 0, j = 0, vfta = 0, mask = 1;
5178
5179         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5180                 vfta = shadow_vfta->vfta[i];
5181                 if (vfta) {
5182                         mask = 1;
5183                         for (j = 0; j < 32; j++) {
5184                                 if (vfta & mask)
5185                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5186                                                        on, false);
5187                                 mask <<= 1;
5188                         }
5189                 }
5190         }
5191
5192 }
5193
5194 static int
5195 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5196 {
5197         struct ixgbe_hw *hw =
5198                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5199         struct ixgbe_vfta *shadow_vfta =
5200                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5201         uint32_t vid_idx = 0;
5202         uint32_t vid_bit = 0;
5203         int ret = 0;
5204
5205         PMD_INIT_FUNC_TRACE();
5206
5207         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5208         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5209         if (ret) {
5210                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5211                 return ret;
5212         }
5213         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5214         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5215
5216         /* Save what we set and retore it after device reset */
5217         if (on)
5218                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5219         else
5220                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5221
5222         return 0;
5223 }
5224
5225 static void
5226 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5227 {
5228         struct ixgbe_hw *hw =
5229                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5230         uint32_t ctrl;
5231
5232         PMD_INIT_FUNC_TRACE();
5233
5234         if (queue >= hw->mac.max_rx_queues)
5235                 return;
5236
5237         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5238         if (on)
5239                 ctrl |= IXGBE_RXDCTL_VME;
5240         else
5241                 ctrl &= ~IXGBE_RXDCTL_VME;
5242         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5243
5244         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5245 }
5246
5247 static int
5248 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5249 {
5250         struct ixgbe_rx_queue *rxq;
5251         uint16_t i;
5252         int on = 0;
5253
5254         /* VF function only support hw strip feature, others are not support */
5255         if (mask & ETH_VLAN_STRIP_MASK) {
5256                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5257                         rxq = dev->data->rx_queues[i];
5258                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5259                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5260                 }
5261         }
5262
5263         return 0;
5264 }
5265
5266 int
5267 ixgbe_vt_check(struct ixgbe_hw *hw)
5268 {
5269         uint32_t reg_val;
5270
5271         /* if Virtualization Technology is enabled */
5272         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5273         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5274                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5275                 return -1;
5276         }
5277
5278         return 0;
5279 }
5280
5281 static uint32_t
5282 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5283 {
5284         uint32_t vector = 0;
5285
5286         switch (hw->mac.mc_filter_type) {
5287         case 0:   /* use bits [47:36] of the address */
5288                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5289                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5290                 break;
5291         case 1:   /* use bits [46:35] of the address */
5292                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5293                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5294                 break;
5295         case 2:   /* use bits [45:34] of the address */
5296                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5297                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5298                 break;
5299         case 3:   /* use bits [43:32] of the address */
5300                 vector = ((uc_addr->addr_bytes[4]) |
5301                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5302                 break;
5303         default:  /* Invalid mc_filter_type */
5304                 break;
5305         }
5306
5307         /* vector can only be 12-bits or boundary will be exceeded */
5308         vector &= 0xFFF;
5309         return vector;
5310 }
5311
5312 static int
5313 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5314                         uint8_t on)
5315 {
5316         uint32_t vector;
5317         uint32_t uta_idx;
5318         uint32_t reg_val;
5319         uint32_t uta_shift;
5320         uint32_t rc;
5321         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5322         const uint32_t ixgbe_uta_bit_shift = 5;
5323         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5324         const uint32_t bit1 = 0x1;
5325
5326         struct ixgbe_hw *hw =
5327                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5328         struct ixgbe_uta_info *uta_info =
5329                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5330
5331         /* The UTA table only exists on 82599 hardware and newer */
5332         if (hw->mac.type < ixgbe_mac_82599EB)
5333                 return -ENOTSUP;
5334
5335         vector = ixgbe_uta_vector(hw, mac_addr);
5336         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5337         uta_shift = vector & ixgbe_uta_bit_mask;
5338
5339         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5340         if (rc == on)
5341                 return 0;
5342
5343         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5344         if (on) {
5345                 uta_info->uta_in_use++;
5346                 reg_val |= (bit1 << uta_shift);
5347                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5348         } else {
5349                 uta_info->uta_in_use--;
5350                 reg_val &= ~(bit1 << uta_shift);
5351                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5352         }
5353
5354         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5355
5356         if (uta_info->uta_in_use > 0)
5357                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5358                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5359         else
5360                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5361
5362         return 0;
5363 }
5364
5365 static int
5366 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5367 {
5368         int i;
5369         struct ixgbe_hw *hw =
5370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5371         struct ixgbe_uta_info *uta_info =
5372                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5373
5374         /* The UTA table only exists on 82599 hardware and newer */
5375         if (hw->mac.type < ixgbe_mac_82599EB)
5376                 return -ENOTSUP;
5377
5378         if (on) {
5379                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5380                         uta_info->uta_shadow[i] = ~0;
5381                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5382                 }
5383         } else {
5384                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5385                         uta_info->uta_shadow[i] = 0;
5386                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5387                 }
5388         }
5389         return 0;
5390
5391 }
5392
5393 uint32_t
5394 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5395 {
5396         uint32_t new_val = orig_val;
5397
5398         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5399                 new_val |= IXGBE_VMOLR_AUPE;
5400         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5401                 new_val |= IXGBE_VMOLR_ROMPE;
5402         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5403                 new_val |= IXGBE_VMOLR_ROPE;
5404         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5405                 new_val |= IXGBE_VMOLR_BAM;
5406         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5407                 new_val |= IXGBE_VMOLR_MPE;
5408
5409         return new_val;
5410 }
5411
5412 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5413 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5414 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5415 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5416 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5417         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5418         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5419
5420 static int
5421 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5422                       struct rte_eth_mirror_conf *mirror_conf,
5423                       uint8_t rule_id, uint8_t on)
5424 {
5425         uint32_t mr_ctl, vlvf;
5426         uint32_t mp_lsb = 0;
5427         uint32_t mv_msb = 0;
5428         uint32_t mv_lsb = 0;
5429         uint32_t mp_msb = 0;
5430         uint8_t i = 0;
5431         int reg_index = 0;
5432         uint64_t vlan_mask = 0;
5433
5434         const uint8_t pool_mask_offset = 32;
5435         const uint8_t vlan_mask_offset = 32;
5436         const uint8_t dst_pool_offset = 8;
5437         const uint8_t rule_mr_offset  = 4;
5438         const uint8_t mirror_rule_mask = 0x0F;
5439
5440         struct ixgbe_mirror_info *mr_info =
5441                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5442         struct ixgbe_hw *hw =
5443                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5444         uint8_t mirror_type = 0;
5445
5446         if (ixgbe_vt_check(hw) < 0)
5447                 return -ENOTSUP;
5448
5449         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5450                 return -EINVAL;
5451
5452         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5453                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5454                             mirror_conf->rule_type);
5455                 return -EINVAL;
5456         }
5457
5458         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5459                 mirror_type |= IXGBE_MRCTL_VLME;
5460                 /* Check if vlan id is valid and find conresponding VLAN ID
5461                  * index in VLVF
5462                  */
5463                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5464                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5465                                 /* search vlan id related pool vlan filter
5466                                  * index
5467                                  */
5468                                 reg_index = ixgbe_find_vlvf_slot(
5469                                                 hw,
5470                                                 mirror_conf->vlan.vlan_id[i],
5471                                                 false);
5472                                 if (reg_index < 0)
5473                                         return -EINVAL;
5474                                 vlvf = IXGBE_READ_REG(hw,
5475                                                       IXGBE_VLVF(reg_index));
5476                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5477                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5478                                       mirror_conf->vlan.vlan_id[i]))
5479                                         vlan_mask |= (1ULL << reg_index);
5480                                 else
5481                                         return -EINVAL;
5482                         }
5483                 }
5484
5485                 if (on) {
5486                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5487                         mv_msb = vlan_mask >> vlan_mask_offset;
5488
5489                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5490                                                 mirror_conf->vlan.vlan_mask;
5491                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5492                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5493                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5494                                                 mirror_conf->vlan.vlan_id[i];
5495                         }
5496                 } else {
5497                         mv_lsb = 0;
5498                         mv_msb = 0;
5499                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5500                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5501                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5502                 }
5503         }
5504
5505         /**
5506          * if enable pool mirror, write related pool mask register,if disable
5507          * pool mirror, clear PFMRVM register
5508          */
5509         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5510                 mirror_type |= IXGBE_MRCTL_VPME;
5511                 if (on) {
5512                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5513                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5514                         mr_info->mr_conf[rule_id].pool_mask =
5515                                         mirror_conf->pool_mask;
5516
5517                 } else {
5518                         mp_lsb = 0;
5519                         mp_msb = 0;
5520                         mr_info->mr_conf[rule_id].pool_mask = 0;
5521                 }
5522         }
5523         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5524                 mirror_type |= IXGBE_MRCTL_UPME;
5525         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5526                 mirror_type |= IXGBE_MRCTL_DPME;
5527
5528         /* read  mirror control register and recalculate it */
5529         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5530
5531         if (on) {
5532                 mr_ctl |= mirror_type;
5533                 mr_ctl &= mirror_rule_mask;
5534                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5535         } else {
5536                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5537         }
5538
5539         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5540         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5541
5542         /* write mirrror control  register */
5543         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5544
5545         /* write pool mirrror control  register */
5546         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5547                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5548                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5549                                 mp_msb);
5550         }
5551         /* write VLAN mirrror control  register */
5552         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5553                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5554                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5555                                 mv_msb);
5556         }
5557
5558         return 0;
5559 }
5560
5561 static int
5562 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5563 {
5564         int mr_ctl = 0;
5565         uint32_t lsb_val = 0;
5566         uint32_t msb_val = 0;
5567         const uint8_t rule_mr_offset = 4;
5568
5569         struct ixgbe_hw *hw =
5570                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5571         struct ixgbe_mirror_info *mr_info =
5572                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5573
5574         if (ixgbe_vt_check(hw) < 0)
5575                 return -ENOTSUP;
5576
5577         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5578                 return -EINVAL;
5579
5580         memset(&mr_info->mr_conf[rule_id], 0,
5581                sizeof(struct rte_eth_mirror_conf));
5582
5583         /* clear PFVMCTL register */
5584         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5585
5586         /* clear pool mask register */
5587         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5588         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5589
5590         /* clear vlan mask register */
5591         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5592         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5593
5594         return 0;
5595 }
5596
5597 static int
5598 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5599 {
5600         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5601         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5602         uint32_t mask;
5603         struct ixgbe_hw *hw =
5604                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5605         uint32_t vec = IXGBE_MISC_VEC_ID;
5606
5607         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5608         if (rte_intr_allow_others(intr_handle))
5609                 vec = IXGBE_RX_VEC_START;
5610         mask |= (1 << vec);
5611         RTE_SET_USED(queue_id);
5612         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5613
5614         rte_intr_enable(intr_handle);
5615
5616         return 0;
5617 }
5618
5619 static int
5620 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5621 {
5622         uint32_t mask;
5623         struct ixgbe_hw *hw =
5624                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5625         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5626         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5627         uint32_t vec = IXGBE_MISC_VEC_ID;
5628
5629         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5630         if (rte_intr_allow_others(intr_handle))
5631                 vec = IXGBE_RX_VEC_START;
5632         mask &= ~(1 << vec);
5633         RTE_SET_USED(queue_id);
5634         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5635
5636         return 0;
5637 }
5638
5639 static int
5640 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5641 {
5642         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5643         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5644         uint32_t mask;
5645         struct ixgbe_hw *hw =
5646                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5647         struct ixgbe_interrupt *intr =
5648                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5649
5650         if (queue_id < 16) {
5651                 ixgbe_disable_intr(hw);
5652                 intr->mask |= (1 << queue_id);
5653                 ixgbe_enable_intr(dev);
5654         } else if (queue_id < 32) {
5655                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5656                 mask &= (1 << queue_id);
5657                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5658         } else if (queue_id < 64) {
5659                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5660                 mask &= (1 << (queue_id - 32));
5661                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5662         }
5663         rte_intr_enable(intr_handle);
5664
5665         return 0;
5666 }
5667
5668 static int
5669 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5670 {
5671         uint32_t mask;
5672         struct ixgbe_hw *hw =
5673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5674         struct ixgbe_interrupt *intr =
5675                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5676
5677         if (queue_id < 16) {
5678                 ixgbe_disable_intr(hw);
5679                 intr->mask &= ~(1 << queue_id);
5680                 ixgbe_enable_intr(dev);
5681         } else if (queue_id < 32) {
5682                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5683                 mask &= ~(1 << queue_id);
5684                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5685         } else if (queue_id < 64) {
5686                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5687                 mask &= ~(1 << (queue_id - 32));
5688                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5689         }
5690
5691         return 0;
5692 }
5693
5694 static void
5695 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5696                      uint8_t queue, uint8_t msix_vector)
5697 {
5698         uint32_t tmp, idx;
5699
5700         if (direction == -1) {
5701                 /* other causes */
5702                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5703                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5704                 tmp &= ~0xFF;
5705                 tmp |= msix_vector;
5706                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5707         } else {
5708                 /* rx or tx cause */
5709                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5710                 idx = ((16 * (queue & 1)) + (8 * direction));
5711                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5712                 tmp &= ~(0xFF << idx);
5713                 tmp |= (msix_vector << idx);
5714                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5715         }
5716 }
5717
5718 /**
5719  * set the IVAR registers, mapping interrupt causes to vectors
5720  * @param hw
5721  *  pointer to ixgbe_hw struct
5722  * @direction
5723  *  0 for Rx, 1 for Tx, -1 for other causes
5724  * @queue
5725  *  queue to map the corresponding interrupt to
5726  * @msix_vector
5727  *  the vector to map to the corresponding queue
5728  */
5729 static void
5730 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5731                    uint8_t queue, uint8_t msix_vector)
5732 {
5733         uint32_t tmp, idx;
5734
5735         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5736         if (hw->mac.type == ixgbe_mac_82598EB) {
5737                 if (direction == -1)
5738                         direction = 0;
5739                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5740                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5741                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5742                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5743                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5744         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5745                         (hw->mac.type == ixgbe_mac_X540) ||
5746                         (hw->mac.type == ixgbe_mac_X550)) {
5747                 if (direction == -1) {
5748                         /* other causes */
5749                         idx = ((queue & 1) * 8);
5750                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5751                         tmp &= ~(0xFF << idx);
5752                         tmp |= (msix_vector << idx);
5753                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5754                 } else {
5755                         /* rx or tx causes */
5756                         idx = ((16 * (queue & 1)) + (8 * direction));
5757                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5758                         tmp &= ~(0xFF << idx);
5759                         tmp |= (msix_vector << idx);
5760                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5761                 }
5762         }
5763 }
5764
5765 static void
5766 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5767 {
5768         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5769         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5770         struct ixgbe_hw *hw =
5771                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5772         uint32_t q_idx;
5773         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5774         uint32_t base = IXGBE_MISC_VEC_ID;
5775
5776         /* Configure VF other cause ivar */
5777         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5778
5779         /* won't configure msix register if no mapping is done
5780          * between intr vector and event fd.
5781          */
5782         if (!rte_intr_dp_is_en(intr_handle))
5783                 return;
5784
5785         if (rte_intr_allow_others(intr_handle)) {
5786                 base = IXGBE_RX_VEC_START;
5787                 vector_idx = IXGBE_RX_VEC_START;
5788         }
5789
5790         /* Configure all RX queues of VF */
5791         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5792                 /* Force all queue use vector 0,
5793                  * as IXGBE_VF_MAXMSIVECOTR = 1
5794                  */
5795                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5796                 intr_handle->intr_vec[q_idx] = vector_idx;
5797                 if (vector_idx < base + intr_handle->nb_efd - 1)
5798                         vector_idx++;
5799         }
5800 }
5801
5802 /**
5803  * Sets up the hardware to properly generate MSI-X interrupts
5804  * @hw
5805  *  board private structure
5806  */
5807 static void
5808 ixgbe_configure_msix(struct rte_eth_dev *dev)
5809 {
5810         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5811         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5812         struct ixgbe_hw *hw =
5813                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5814         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5815         uint32_t vec = IXGBE_MISC_VEC_ID;
5816         uint32_t mask;
5817         uint32_t gpie;
5818
5819         /* won't configure msix register if no mapping is done
5820          * between intr vector and event fd
5821          */
5822         if (!rte_intr_dp_is_en(intr_handle))
5823                 return;
5824
5825         if (rte_intr_allow_others(intr_handle))
5826                 vec = base = IXGBE_RX_VEC_START;
5827
5828         /* setup GPIE for MSI-x mode */
5829         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5830         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5831                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5832         /* auto clearing and auto setting corresponding bits in EIMS
5833          * when MSI-X interrupt is triggered
5834          */
5835         if (hw->mac.type == ixgbe_mac_82598EB) {
5836                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5837         } else {
5838                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5839                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5840         }
5841         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5842
5843         /* Populate the IVAR table and set the ITR values to the
5844          * corresponding register.
5845          */
5846         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5847              queue_id++) {
5848                 /* by default, 1:1 mapping */
5849                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5850                 intr_handle->intr_vec[queue_id] = vec;
5851                 if (vec < base + intr_handle->nb_efd - 1)
5852                         vec++;
5853         }
5854
5855         switch (hw->mac.type) {
5856         case ixgbe_mac_82598EB:
5857                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5858                                    IXGBE_MISC_VEC_ID);
5859                 break;
5860         case ixgbe_mac_82599EB:
5861         case ixgbe_mac_X540:
5862         case ixgbe_mac_X550:
5863                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5864                 break;
5865         default:
5866                 break;
5867         }
5868         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5869                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5870
5871         /* set up to autoclear timer, and the vectors */
5872         mask = IXGBE_EIMS_ENABLE_MASK;
5873         mask &= ~(IXGBE_EIMS_OTHER |
5874                   IXGBE_EIMS_MAILBOX |
5875                   IXGBE_EIMS_LSC);
5876
5877         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5878 }
5879
5880 int
5881 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5882                            uint16_t queue_idx, uint16_t tx_rate)
5883 {
5884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5885         struct rte_eth_rxmode *rxmode;
5886         uint32_t rf_dec, rf_int;
5887         uint32_t bcnrc_val;
5888         uint16_t link_speed = dev->data->dev_link.link_speed;
5889
5890         if (queue_idx >= hw->mac.max_tx_queues)
5891                 return -EINVAL;
5892
5893         if (tx_rate != 0) {
5894                 /* Calculate the rate factor values to set */
5895                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5896                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5897                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5898
5899                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5900                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5901                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5902                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5903         } else {
5904                 bcnrc_val = 0;
5905         }
5906
5907         rxmode = &dev->data->dev_conf.rxmode;
5908         /*
5909          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5910          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5911          * set as 0x4.
5912          */
5913         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5914             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5915                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5916                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5917         else
5918                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5919                         IXGBE_MMW_SIZE_DEFAULT);
5920
5921         /* Set RTTBCNRC of queue X */
5922         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5923         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5924         IXGBE_WRITE_FLUSH(hw);
5925
5926         return 0;
5927 }
5928
5929 static int
5930 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5931                      __attribute__((unused)) uint32_t index,
5932                      __attribute__((unused)) uint32_t pool)
5933 {
5934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5935         int diag;
5936
5937         /*
5938          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5939          * operation. Trap this case to avoid exhausting the [very limited]
5940          * set of PF resources used to store VF MAC addresses.
5941          */
5942         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5943                 return -1;
5944         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5945         if (diag != 0)
5946                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5947                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5948                             mac_addr->addr_bytes[0],
5949                             mac_addr->addr_bytes[1],
5950                             mac_addr->addr_bytes[2],
5951                             mac_addr->addr_bytes[3],
5952                             mac_addr->addr_bytes[4],
5953                             mac_addr->addr_bytes[5],
5954                             diag);
5955         return diag;
5956 }
5957
5958 static void
5959 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5960 {
5961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5962         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5963         struct ether_addr *mac_addr;
5964         uint32_t i;
5965         int diag;
5966
5967         /*
5968          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5969          * not support the deletion of a given MAC address.
5970          * Instead, it imposes to delete all MAC addresses, then to add again
5971          * all MAC addresses with the exception of the one to be deleted.
5972          */
5973         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5974
5975         /*
5976          * Add again all MAC addresses, with the exception of the deleted one
5977          * and of the permanent MAC address.
5978          */
5979         for (i = 0, mac_addr = dev->data->mac_addrs;
5980              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5981                 /* Skip the deleted MAC address */
5982                 if (i == index)
5983                         continue;
5984                 /* Skip NULL MAC addresses */
5985                 if (is_zero_ether_addr(mac_addr))
5986                         continue;
5987                 /* Skip the permanent MAC address */
5988                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5989                         continue;
5990                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5991                 if (diag != 0)
5992                         PMD_DRV_LOG(ERR,
5993                                     "Adding again MAC address "
5994                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5995                                     "diag=%d",
5996                                     mac_addr->addr_bytes[0],
5997                                     mac_addr->addr_bytes[1],
5998                                     mac_addr->addr_bytes[2],
5999                                     mac_addr->addr_bytes[3],
6000                                     mac_addr->addr_bytes[4],
6001                                     mac_addr->addr_bytes[5],
6002                                     diag);
6003         }
6004 }
6005
6006 static int
6007 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6008 {
6009         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6010
6011         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6012
6013         return 0;
6014 }
6015
6016 int
6017 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6018                         struct rte_eth_syn_filter *filter,
6019                         bool add)
6020 {
6021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6022         struct ixgbe_filter_info *filter_info =
6023                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6024         uint32_t syn_info;
6025         uint32_t synqf;
6026
6027         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6028                 return -EINVAL;
6029
6030         syn_info = filter_info->syn_info;
6031
6032         if (add) {
6033                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6034                         return -EINVAL;
6035                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6036                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6037
6038                 if (filter->hig_pri)
6039                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6040                 else
6041                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6042         } else {
6043                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6044                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6045                         return -ENOENT;
6046                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6047         }
6048
6049         filter_info->syn_info = synqf;
6050         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6051         IXGBE_WRITE_FLUSH(hw);
6052         return 0;
6053 }
6054
6055 static int
6056 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6057                         struct rte_eth_syn_filter *filter)
6058 {
6059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6060         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6061
6062         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6063                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6064                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6065                 return 0;
6066         }
6067         return -ENOENT;
6068 }
6069
6070 static int
6071 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6072                         enum rte_filter_op filter_op,
6073                         void *arg)
6074 {
6075         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6076         int ret;
6077
6078         MAC_TYPE_FILTER_SUP(hw->mac.type);
6079
6080         if (filter_op == RTE_ETH_FILTER_NOP)
6081                 return 0;
6082
6083         if (arg == NULL) {
6084                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6085                             filter_op);
6086                 return -EINVAL;
6087         }
6088
6089         switch (filter_op) {
6090         case RTE_ETH_FILTER_ADD:
6091                 ret = ixgbe_syn_filter_set(dev,
6092                                 (struct rte_eth_syn_filter *)arg,
6093                                 TRUE);
6094                 break;
6095         case RTE_ETH_FILTER_DELETE:
6096                 ret = ixgbe_syn_filter_set(dev,
6097                                 (struct rte_eth_syn_filter *)arg,
6098                                 FALSE);
6099                 break;
6100         case RTE_ETH_FILTER_GET:
6101                 ret = ixgbe_syn_filter_get(dev,
6102                                 (struct rte_eth_syn_filter *)arg);
6103                 break;
6104         default:
6105                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6106                 ret = -EINVAL;
6107                 break;
6108         }
6109
6110         return ret;
6111 }
6112
6113
6114 static inline enum ixgbe_5tuple_protocol
6115 convert_protocol_type(uint8_t protocol_value)
6116 {
6117         if (protocol_value == IPPROTO_TCP)
6118                 return IXGBE_FILTER_PROTOCOL_TCP;
6119         else if (protocol_value == IPPROTO_UDP)
6120                 return IXGBE_FILTER_PROTOCOL_UDP;
6121         else if (protocol_value == IPPROTO_SCTP)
6122                 return IXGBE_FILTER_PROTOCOL_SCTP;
6123         else
6124                 return IXGBE_FILTER_PROTOCOL_NONE;
6125 }
6126
6127 /* inject a 5-tuple filter to HW */
6128 static inline void
6129 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6130                            struct ixgbe_5tuple_filter *filter)
6131 {
6132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6133         int i;
6134         uint32_t ftqf, sdpqf;
6135         uint32_t l34timir = 0;
6136         uint8_t mask = 0xff;
6137
6138         i = filter->index;
6139
6140         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6141                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6142         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6143
6144         ftqf = (uint32_t)(filter->filter_info.proto &
6145                 IXGBE_FTQF_PROTOCOL_MASK);
6146         ftqf |= (uint32_t)((filter->filter_info.priority &
6147                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6148         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6149                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6150         if (filter->filter_info.dst_ip_mask == 0)
6151                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6152         if (filter->filter_info.src_port_mask == 0)
6153                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6154         if (filter->filter_info.dst_port_mask == 0)
6155                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6156         if (filter->filter_info.proto_mask == 0)
6157                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6158         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6159         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6160         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6161
6162         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6163         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6164         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6165         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6166
6167         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6168         l34timir |= (uint32_t)(filter->queue <<
6169                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6170         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6171 }
6172
6173 /*
6174  * add a 5tuple filter
6175  *
6176  * @param
6177  * dev: Pointer to struct rte_eth_dev.
6178  * index: the index the filter allocates.
6179  * filter: ponter to the filter that will be added.
6180  * rx_queue: the queue id the filter assigned to.
6181  *
6182  * @return
6183  *    - On success, zero.
6184  *    - On failure, a negative value.
6185  */
6186 static int
6187 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6188                         struct ixgbe_5tuple_filter *filter)
6189 {
6190         struct ixgbe_filter_info *filter_info =
6191                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6192         int i, idx, shift;
6193
6194         /*
6195          * look for an unused 5tuple filter index,
6196          * and insert the filter to list.
6197          */
6198         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6199                 idx = i / (sizeof(uint32_t) * NBBY);
6200                 shift = i % (sizeof(uint32_t) * NBBY);
6201                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6202                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6203                         filter->index = i;
6204                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6205                                           filter,
6206                                           entries);
6207                         break;
6208                 }
6209         }
6210         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6211                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6212                 return -ENOSYS;
6213         }
6214
6215         ixgbe_inject_5tuple_filter(dev, filter);
6216
6217         return 0;
6218 }
6219
6220 /*
6221  * remove a 5tuple filter
6222  *
6223  * @param
6224  * dev: Pointer to struct rte_eth_dev.
6225  * filter: the pointer of the filter will be removed.
6226  */
6227 static void
6228 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6229                         struct ixgbe_5tuple_filter *filter)
6230 {
6231         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6232         struct ixgbe_filter_info *filter_info =
6233                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6234         uint16_t index = filter->index;
6235
6236         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6237                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6238         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6239         rte_free(filter);
6240
6241         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6242         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6243         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6244         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6245         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6246 }
6247
6248 static int
6249 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6250 {
6251         struct ixgbe_hw *hw;
6252         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6253         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6254
6255         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6256
6257         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6258                 return -EINVAL;
6259
6260         /* refuse mtu that requires the support of scattered packets when this
6261          * feature has not been enabled before.
6262          */
6263         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6264             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6265              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6266                 return -EINVAL;
6267
6268         /*
6269          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6270          * request of the version 2.0 of the mailbox API.
6271          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6272          * of the mailbox API.
6273          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6274          * prior to 3.11.33 which contains the following change:
6275          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6276          */
6277         ixgbevf_rlpml_set_vf(hw, max_frame);
6278
6279         /* update max frame size */
6280         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6281         return 0;
6282 }
6283
6284 static inline struct ixgbe_5tuple_filter *
6285 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6286                         struct ixgbe_5tuple_filter_info *key)
6287 {
6288         struct ixgbe_5tuple_filter *it;
6289
6290         TAILQ_FOREACH(it, filter_list, entries) {
6291                 if (memcmp(key, &it->filter_info,
6292                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6293                         return it;
6294                 }
6295         }
6296         return NULL;
6297 }
6298
6299 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6300 static inline int
6301 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6302                         struct ixgbe_5tuple_filter_info *filter_info)
6303 {
6304         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6305                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6306                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6307                 return -EINVAL;
6308
6309         switch (filter->dst_ip_mask) {
6310         case UINT32_MAX:
6311                 filter_info->dst_ip_mask = 0;
6312                 filter_info->dst_ip = filter->dst_ip;
6313                 break;
6314         case 0:
6315                 filter_info->dst_ip_mask = 1;
6316                 break;
6317         default:
6318                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6319                 return -EINVAL;
6320         }
6321
6322         switch (filter->src_ip_mask) {
6323         case UINT32_MAX:
6324                 filter_info->src_ip_mask = 0;
6325                 filter_info->src_ip = filter->src_ip;
6326                 break;
6327         case 0:
6328                 filter_info->src_ip_mask = 1;
6329                 break;
6330         default:
6331                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6332                 return -EINVAL;
6333         }
6334
6335         switch (filter->dst_port_mask) {
6336         case UINT16_MAX:
6337                 filter_info->dst_port_mask = 0;
6338                 filter_info->dst_port = filter->dst_port;
6339                 break;
6340         case 0:
6341                 filter_info->dst_port_mask = 1;
6342                 break;
6343         default:
6344                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6345                 return -EINVAL;
6346         }
6347
6348         switch (filter->src_port_mask) {
6349         case UINT16_MAX:
6350                 filter_info->src_port_mask = 0;
6351                 filter_info->src_port = filter->src_port;
6352                 break;
6353         case 0:
6354                 filter_info->src_port_mask = 1;
6355                 break;
6356         default:
6357                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6358                 return -EINVAL;
6359         }
6360
6361         switch (filter->proto_mask) {
6362         case UINT8_MAX:
6363                 filter_info->proto_mask = 0;
6364                 filter_info->proto =
6365                         convert_protocol_type(filter->proto);
6366                 break;
6367         case 0:
6368                 filter_info->proto_mask = 1;
6369                 break;
6370         default:
6371                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6372                 return -EINVAL;
6373         }
6374
6375         filter_info->priority = (uint8_t)filter->priority;
6376         return 0;
6377 }
6378
6379 /*
6380  * add or delete a ntuple filter
6381  *
6382  * @param
6383  * dev: Pointer to struct rte_eth_dev.
6384  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6385  * add: if true, add filter, if false, remove filter
6386  *
6387  * @return
6388  *    - On success, zero.
6389  *    - On failure, a negative value.
6390  */
6391 int
6392 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6393                         struct rte_eth_ntuple_filter *ntuple_filter,
6394                         bool add)
6395 {
6396         struct ixgbe_filter_info *filter_info =
6397                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6398         struct ixgbe_5tuple_filter_info filter_5tuple;
6399         struct ixgbe_5tuple_filter *filter;
6400         int ret;
6401
6402         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6403                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6404                 return -EINVAL;
6405         }
6406
6407         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6408         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6409         if (ret < 0)
6410                 return ret;
6411
6412         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6413                                          &filter_5tuple);
6414         if (filter != NULL && add) {
6415                 PMD_DRV_LOG(ERR, "filter exists.");
6416                 return -EEXIST;
6417         }
6418         if (filter == NULL && !add) {
6419                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6420                 return -ENOENT;
6421         }
6422
6423         if (add) {
6424                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6425                                 sizeof(struct ixgbe_5tuple_filter), 0);
6426                 if (filter == NULL)
6427                         return -ENOMEM;
6428                 rte_memcpy(&filter->filter_info,
6429                                  &filter_5tuple,
6430                                  sizeof(struct ixgbe_5tuple_filter_info));
6431                 filter->queue = ntuple_filter->queue;
6432                 ret = ixgbe_add_5tuple_filter(dev, filter);
6433                 if (ret < 0) {
6434                         rte_free(filter);
6435                         return ret;
6436                 }
6437         } else
6438                 ixgbe_remove_5tuple_filter(dev, filter);
6439
6440         return 0;
6441 }
6442
6443 /*
6444  * get a ntuple filter
6445  *
6446  * @param
6447  * dev: Pointer to struct rte_eth_dev.
6448  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6449  *
6450  * @return
6451  *    - On success, zero.
6452  *    - On failure, a negative value.
6453  */
6454 static int
6455 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6456                         struct rte_eth_ntuple_filter *ntuple_filter)
6457 {
6458         struct ixgbe_filter_info *filter_info =
6459                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6460         struct ixgbe_5tuple_filter_info filter_5tuple;
6461         struct ixgbe_5tuple_filter *filter;
6462         int ret;
6463
6464         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6465                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6466                 return -EINVAL;
6467         }
6468
6469         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6470         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6471         if (ret < 0)
6472                 return ret;
6473
6474         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6475                                          &filter_5tuple);
6476         if (filter == NULL) {
6477                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6478                 return -ENOENT;
6479         }
6480         ntuple_filter->queue = filter->queue;
6481         return 0;
6482 }
6483
6484 /*
6485  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6486  * @dev: pointer to rte_eth_dev structure
6487  * @filter_op:operation will be taken.
6488  * @arg: a pointer to specific structure corresponding to the filter_op
6489  *
6490  * @return
6491  *    - On success, zero.
6492  *    - On failure, a negative value.
6493  */
6494 static int
6495 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6496                                 enum rte_filter_op filter_op,
6497                                 void *arg)
6498 {
6499         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6500         int ret;
6501
6502         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6503
6504         if (filter_op == RTE_ETH_FILTER_NOP)
6505                 return 0;
6506
6507         if (arg == NULL) {
6508                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6509                             filter_op);
6510                 return -EINVAL;
6511         }
6512
6513         switch (filter_op) {
6514         case RTE_ETH_FILTER_ADD:
6515                 ret = ixgbe_add_del_ntuple_filter(dev,
6516                         (struct rte_eth_ntuple_filter *)arg,
6517                         TRUE);
6518                 break;
6519         case RTE_ETH_FILTER_DELETE:
6520                 ret = ixgbe_add_del_ntuple_filter(dev,
6521                         (struct rte_eth_ntuple_filter *)arg,
6522                         FALSE);
6523                 break;
6524         case RTE_ETH_FILTER_GET:
6525                 ret = ixgbe_get_ntuple_filter(dev,
6526                         (struct rte_eth_ntuple_filter *)arg);
6527                 break;
6528         default:
6529                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6530                 ret = -EINVAL;
6531                 break;
6532         }
6533         return ret;
6534 }
6535
6536 int
6537 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6538                         struct rte_eth_ethertype_filter *filter,
6539                         bool add)
6540 {
6541         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6542         struct ixgbe_filter_info *filter_info =
6543                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6544         uint32_t etqf = 0;
6545         uint32_t etqs = 0;
6546         int ret;
6547         struct ixgbe_ethertype_filter ethertype_filter;
6548
6549         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6550                 return -EINVAL;
6551
6552         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6553                 filter->ether_type == ETHER_TYPE_IPv6) {
6554                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6555                         " ethertype filter.", filter->ether_type);
6556                 return -EINVAL;
6557         }
6558
6559         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6560                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6561                 return -EINVAL;
6562         }
6563         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6564                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6565                 return -EINVAL;
6566         }
6567
6568         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6569         if (ret >= 0 && add) {
6570                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6571                             filter->ether_type);
6572                 return -EEXIST;
6573         }
6574         if (ret < 0 && !add) {
6575                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6576                             filter->ether_type);
6577                 return -ENOENT;
6578         }
6579
6580         if (add) {
6581                 etqf = IXGBE_ETQF_FILTER_EN;
6582                 etqf |= (uint32_t)filter->ether_type;
6583                 etqs |= (uint32_t)((filter->queue <<
6584                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6585                                     IXGBE_ETQS_RX_QUEUE);
6586                 etqs |= IXGBE_ETQS_QUEUE_EN;
6587
6588                 ethertype_filter.ethertype = filter->ether_type;
6589                 ethertype_filter.etqf = etqf;
6590                 ethertype_filter.etqs = etqs;
6591                 ethertype_filter.conf = FALSE;
6592                 ret = ixgbe_ethertype_filter_insert(filter_info,
6593                                                     &ethertype_filter);
6594                 if (ret < 0) {
6595                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6596                         return -ENOSPC;
6597                 }
6598         } else {
6599                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6600                 if (ret < 0)
6601                         return -ENOSYS;
6602         }
6603         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6604         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6605         IXGBE_WRITE_FLUSH(hw);
6606
6607         return 0;
6608 }
6609
6610 static int
6611 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6612                         struct rte_eth_ethertype_filter *filter)
6613 {
6614         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6615         struct ixgbe_filter_info *filter_info =
6616                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6617         uint32_t etqf, etqs;
6618         int ret;
6619
6620         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6621         if (ret < 0) {
6622                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6623                             filter->ether_type);
6624                 return -ENOENT;
6625         }
6626
6627         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6628         if (etqf & IXGBE_ETQF_FILTER_EN) {
6629                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6630                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6631                 filter->flags = 0;
6632                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6633                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6634                 return 0;
6635         }
6636         return -ENOENT;
6637 }
6638
6639 /*
6640  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6641  * @dev: pointer to rte_eth_dev structure
6642  * @filter_op:operation will be taken.
6643  * @arg: a pointer to specific structure corresponding to the filter_op
6644  */
6645 static int
6646 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6647                                 enum rte_filter_op filter_op,
6648                                 void *arg)
6649 {
6650         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6651         int ret;
6652
6653         MAC_TYPE_FILTER_SUP(hw->mac.type);
6654
6655         if (filter_op == RTE_ETH_FILTER_NOP)
6656                 return 0;
6657
6658         if (arg == NULL) {
6659                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6660                             filter_op);
6661                 return -EINVAL;
6662         }
6663
6664         switch (filter_op) {
6665         case RTE_ETH_FILTER_ADD:
6666                 ret = ixgbe_add_del_ethertype_filter(dev,
6667                         (struct rte_eth_ethertype_filter *)arg,
6668                         TRUE);
6669                 break;
6670         case RTE_ETH_FILTER_DELETE:
6671                 ret = ixgbe_add_del_ethertype_filter(dev,
6672                         (struct rte_eth_ethertype_filter *)arg,
6673                         FALSE);
6674                 break;
6675         case RTE_ETH_FILTER_GET:
6676                 ret = ixgbe_get_ethertype_filter(dev,
6677                         (struct rte_eth_ethertype_filter *)arg);
6678                 break;
6679         default:
6680                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6681                 ret = -EINVAL;
6682                 break;
6683         }
6684         return ret;
6685 }
6686
6687 static int
6688 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6689                      enum rte_filter_type filter_type,
6690                      enum rte_filter_op filter_op,
6691                      void *arg)
6692 {
6693         int ret = 0;
6694
6695         switch (filter_type) {
6696         case RTE_ETH_FILTER_NTUPLE:
6697                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6698                 break;
6699         case RTE_ETH_FILTER_ETHERTYPE:
6700                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6701                 break;
6702         case RTE_ETH_FILTER_SYN:
6703                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6704                 break;
6705         case RTE_ETH_FILTER_FDIR:
6706                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6707                 break;
6708         case RTE_ETH_FILTER_L2_TUNNEL:
6709                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6710                 break;
6711         case RTE_ETH_FILTER_GENERIC:
6712                 if (filter_op != RTE_ETH_FILTER_GET)
6713                         return -EINVAL;
6714                 *(const void **)arg = &ixgbe_flow_ops;
6715                 break;
6716         default:
6717                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6718                                                         filter_type);
6719                 ret = -EINVAL;
6720                 break;
6721         }
6722
6723         return ret;
6724 }
6725
6726 static u8 *
6727 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6728                         u8 **mc_addr_ptr, u32 *vmdq)
6729 {
6730         u8 *mc_addr;
6731
6732         *vmdq = 0;
6733         mc_addr = *mc_addr_ptr;
6734         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6735         return mc_addr;
6736 }
6737
6738 static int
6739 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6740                           struct ether_addr *mc_addr_set,
6741                           uint32_t nb_mc_addr)
6742 {
6743         struct ixgbe_hw *hw;
6744         u8 *mc_addr_list;
6745
6746         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6747         mc_addr_list = (u8 *)mc_addr_set;
6748         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6749                                          ixgbe_dev_addr_list_itr, TRUE);
6750 }
6751
6752 static uint64_t
6753 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6754 {
6755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6756         uint64_t systime_cycles;
6757
6758         switch (hw->mac.type) {
6759         case ixgbe_mac_X550:
6760         case ixgbe_mac_X550EM_x:
6761         case ixgbe_mac_X550EM_a:
6762                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6763                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6764                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6765                                 * NSEC_PER_SEC;
6766                 break;
6767         default:
6768                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6769                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6770                                 << 32;
6771         }
6772
6773         return systime_cycles;
6774 }
6775
6776 static uint64_t
6777 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6778 {
6779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6780         uint64_t rx_tstamp_cycles;
6781
6782         switch (hw->mac.type) {
6783         case ixgbe_mac_X550:
6784         case ixgbe_mac_X550EM_x:
6785         case ixgbe_mac_X550EM_a:
6786                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6787                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6788                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6789                                 * NSEC_PER_SEC;
6790                 break;
6791         default:
6792                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6793                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6794                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6795                                 << 32;
6796         }
6797
6798         return rx_tstamp_cycles;
6799 }
6800
6801 static uint64_t
6802 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6803 {
6804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6805         uint64_t tx_tstamp_cycles;
6806
6807         switch (hw->mac.type) {
6808         case ixgbe_mac_X550:
6809         case ixgbe_mac_X550EM_x:
6810         case ixgbe_mac_X550EM_a:
6811                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6812                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6813                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6814                                 * NSEC_PER_SEC;
6815                 break;
6816         default:
6817                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6818                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6819                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6820                                 << 32;
6821         }
6822
6823         return tx_tstamp_cycles;
6824 }
6825
6826 static void
6827 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6828 {
6829         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6830         struct ixgbe_adapter *adapter =
6831                 (struct ixgbe_adapter *)dev->data->dev_private;
6832         struct rte_eth_link link;
6833         uint32_t incval = 0;
6834         uint32_t shift = 0;
6835
6836         /* Get current link speed. */
6837         ixgbe_dev_link_update(dev, 1);
6838         rte_eth_linkstatus_get(dev, &link);
6839
6840         switch (link.link_speed) {
6841         case ETH_SPEED_NUM_100M:
6842                 incval = IXGBE_INCVAL_100;
6843                 shift = IXGBE_INCVAL_SHIFT_100;
6844                 break;
6845         case ETH_SPEED_NUM_1G:
6846                 incval = IXGBE_INCVAL_1GB;
6847                 shift = IXGBE_INCVAL_SHIFT_1GB;
6848                 break;
6849         case ETH_SPEED_NUM_10G:
6850         default:
6851                 incval = IXGBE_INCVAL_10GB;
6852                 shift = IXGBE_INCVAL_SHIFT_10GB;
6853                 break;
6854         }
6855
6856         switch (hw->mac.type) {
6857         case ixgbe_mac_X550:
6858         case ixgbe_mac_X550EM_x:
6859         case ixgbe_mac_X550EM_a:
6860                 /* Independent of link speed. */
6861                 incval = 1;
6862                 /* Cycles read will be interpreted as ns. */
6863                 shift = 0;
6864                 /* Fall-through */
6865         case ixgbe_mac_X540:
6866                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6867                 break;
6868         case ixgbe_mac_82599EB:
6869                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6870                 shift -= IXGBE_INCVAL_SHIFT_82599;
6871                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6872                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6873                 break;
6874         default:
6875                 /* Not supported. */
6876                 return;
6877         }
6878
6879         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6880         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6881         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6882
6883         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6884         adapter->systime_tc.cc_shift = shift;
6885         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6886
6887         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6888         adapter->rx_tstamp_tc.cc_shift = shift;
6889         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6890
6891         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6892         adapter->tx_tstamp_tc.cc_shift = shift;
6893         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6894 }
6895
6896 static int
6897 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6898 {
6899         struct ixgbe_adapter *adapter =
6900                         (struct ixgbe_adapter *)dev->data->dev_private;
6901
6902         adapter->systime_tc.nsec += delta;
6903         adapter->rx_tstamp_tc.nsec += delta;
6904         adapter->tx_tstamp_tc.nsec += delta;
6905
6906         return 0;
6907 }
6908
6909 static int
6910 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6911 {
6912         uint64_t ns;
6913         struct ixgbe_adapter *adapter =
6914                         (struct ixgbe_adapter *)dev->data->dev_private;
6915
6916         ns = rte_timespec_to_ns(ts);
6917         /* Set the timecounters to a new value. */
6918         adapter->systime_tc.nsec = ns;
6919         adapter->rx_tstamp_tc.nsec = ns;
6920         adapter->tx_tstamp_tc.nsec = ns;
6921
6922         return 0;
6923 }
6924
6925 static int
6926 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6927 {
6928         uint64_t ns, systime_cycles;
6929         struct ixgbe_adapter *adapter =
6930                         (struct ixgbe_adapter *)dev->data->dev_private;
6931
6932         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6933         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6934         *ts = rte_ns_to_timespec(ns);
6935
6936         return 0;
6937 }
6938
6939 static int
6940 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6941 {
6942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6943         uint32_t tsync_ctl;
6944         uint32_t tsauxc;
6945
6946         /* Stop the timesync system time. */
6947         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6948         /* Reset the timesync system time value. */
6949         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6950         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6951
6952         /* Enable system time for platforms where it isn't on by default. */
6953         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6954         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6955         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6956
6957         ixgbe_start_timecounters(dev);
6958
6959         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6960         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6961                         (ETHER_TYPE_1588 |
6962                          IXGBE_ETQF_FILTER_EN |
6963                          IXGBE_ETQF_1588));
6964
6965         /* Enable timestamping of received PTP packets. */
6966         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6967         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6968         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6969
6970         /* Enable timestamping of transmitted PTP packets. */
6971         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6972         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6973         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6974
6975         IXGBE_WRITE_FLUSH(hw);
6976
6977         return 0;
6978 }
6979
6980 static int
6981 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6982 {
6983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6984         uint32_t tsync_ctl;
6985
6986         /* Disable timestamping of transmitted PTP packets. */
6987         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6988         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6989         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6990
6991         /* Disable timestamping of received PTP packets. */
6992         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6993         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6994         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6995
6996         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6997         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6998
6999         /* Stop incrementating the System Time registers. */
7000         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7001
7002         return 0;
7003 }
7004
7005 static int
7006 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7007                                  struct timespec *timestamp,
7008                                  uint32_t flags __rte_unused)
7009 {
7010         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7011         struct ixgbe_adapter *adapter =
7012                 (struct ixgbe_adapter *)dev->data->dev_private;
7013         uint32_t tsync_rxctl;
7014         uint64_t rx_tstamp_cycles;
7015         uint64_t ns;
7016
7017         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7018         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7019                 return -EINVAL;
7020
7021         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7022         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7023         *timestamp = rte_ns_to_timespec(ns);
7024
7025         return  0;
7026 }
7027
7028 static int
7029 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7030                                  struct timespec *timestamp)
7031 {
7032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7033         struct ixgbe_adapter *adapter =
7034                 (struct ixgbe_adapter *)dev->data->dev_private;
7035         uint32_t tsync_txctl;
7036         uint64_t tx_tstamp_cycles;
7037         uint64_t ns;
7038
7039         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7040         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7041                 return -EINVAL;
7042
7043         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7044         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7045         *timestamp = rte_ns_to_timespec(ns);
7046
7047         return 0;
7048 }
7049
7050 static int
7051 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7052 {
7053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7054         int count = 0;
7055         int g_ind = 0;
7056         const struct reg_info *reg_group;
7057         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7058                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7059
7060         while ((reg_group = reg_set[g_ind++]))
7061                 count += ixgbe_regs_group_count(reg_group);
7062
7063         return count;
7064 }
7065
7066 static int
7067 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7068 {
7069         int count = 0;
7070         int g_ind = 0;
7071         const struct reg_info *reg_group;
7072
7073         while ((reg_group = ixgbevf_regs[g_ind++]))
7074                 count += ixgbe_regs_group_count(reg_group);
7075
7076         return count;
7077 }
7078
7079 static int
7080 ixgbe_get_regs(struct rte_eth_dev *dev,
7081               struct rte_dev_reg_info *regs)
7082 {
7083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7084         uint32_t *data = regs->data;
7085         int g_ind = 0;
7086         int count = 0;
7087         const struct reg_info *reg_group;
7088         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7089                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7090
7091         if (data == NULL) {
7092                 regs->length = ixgbe_get_reg_length(dev);
7093                 regs->width = sizeof(uint32_t);
7094                 return 0;
7095         }
7096
7097         /* Support only full register dump */
7098         if ((regs->length == 0) ||
7099             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7100                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7101                         hw->device_id;
7102                 while ((reg_group = reg_set[g_ind++]))
7103                         count += ixgbe_read_regs_group(dev, &data[count],
7104                                 reg_group);
7105                 return 0;
7106         }
7107
7108         return -ENOTSUP;
7109 }
7110
7111 static int
7112 ixgbevf_get_regs(struct rte_eth_dev *dev,
7113                 struct rte_dev_reg_info *regs)
7114 {
7115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7116         uint32_t *data = regs->data;
7117         int g_ind = 0;
7118         int count = 0;
7119         const struct reg_info *reg_group;
7120
7121         if (data == NULL) {
7122                 regs->length = ixgbevf_get_reg_length(dev);
7123                 regs->width = sizeof(uint32_t);
7124                 return 0;
7125         }
7126
7127         /* Support only full register dump */
7128         if ((regs->length == 0) ||
7129             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7130                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7131                         hw->device_id;
7132                 while ((reg_group = ixgbevf_regs[g_ind++]))
7133                         count += ixgbe_read_regs_group(dev, &data[count],
7134                                                       reg_group);
7135                 return 0;
7136         }
7137
7138         return -ENOTSUP;
7139 }
7140
7141 static int
7142 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7143 {
7144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7145
7146         /* Return unit is byte count */
7147         return hw->eeprom.word_size * 2;
7148 }
7149
7150 static int
7151 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7152                 struct rte_dev_eeprom_info *in_eeprom)
7153 {
7154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7155         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7156         uint16_t *data = in_eeprom->data;
7157         int first, length;
7158
7159         first = in_eeprom->offset >> 1;
7160         length = in_eeprom->length >> 1;
7161         if ((first > hw->eeprom.word_size) ||
7162             ((first + length) > hw->eeprom.word_size))
7163                 return -EINVAL;
7164
7165         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7166
7167         return eeprom->ops.read_buffer(hw, first, length, data);
7168 }
7169
7170 static int
7171 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7172                 struct rte_dev_eeprom_info *in_eeprom)
7173 {
7174         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7175         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7176         uint16_t *data = in_eeprom->data;
7177         int first, length;
7178
7179         first = in_eeprom->offset >> 1;
7180         length = in_eeprom->length >> 1;
7181         if ((first > hw->eeprom.word_size) ||
7182             ((first + length) > hw->eeprom.word_size))
7183                 return -EINVAL;
7184
7185         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7186
7187         return eeprom->ops.write_buffer(hw,  first, length, data);
7188 }
7189
7190 static int
7191 ixgbe_get_module_info(struct rte_eth_dev *dev,
7192                       struct rte_eth_dev_module_info *modinfo)
7193 {
7194         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7195         uint32_t status;
7196         uint8_t sff8472_rev, addr_mode;
7197         bool page_swap = false;
7198
7199         /* Check whether we support SFF-8472 or not */
7200         status = hw->phy.ops.read_i2c_eeprom(hw,
7201                                              IXGBE_SFF_SFF_8472_COMP,
7202                                              &sff8472_rev);
7203         if (status != 0)
7204                 return -EIO;
7205
7206         /* addressing mode is not supported */
7207         status = hw->phy.ops.read_i2c_eeprom(hw,
7208                                              IXGBE_SFF_SFF_8472_SWAP,
7209                                              &addr_mode);
7210         if (status != 0)
7211                 return -EIO;
7212
7213         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7214                 PMD_DRV_LOG(ERR,
7215                             "Address change required to access page 0xA2, "
7216                             "but not supported. Please report the module "
7217                             "type to the driver maintainers.");
7218                 page_swap = true;
7219         }
7220
7221         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7222                 /* We have a SFP, but it does not support SFF-8472 */
7223                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7224                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7225         } else {
7226                 /* We have a SFP which supports a revision of SFF-8472. */
7227                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7228                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7229         }
7230
7231         return 0;
7232 }
7233
7234 static int
7235 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7236                         struct rte_dev_eeprom_info *info)
7237 {
7238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7239         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7240         uint8_t databyte = 0xFF;
7241         uint8_t *data = info->data;
7242         uint32_t i = 0;
7243
7244         if (info->length == 0)
7245                 return -EINVAL;
7246
7247         for (i = info->offset; i < info->offset + info->length; i++) {
7248                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7249                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7250                 else
7251                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7252
7253                 if (status != 0)
7254                         return -EIO;
7255
7256                 data[i - info->offset] = databyte;
7257         }
7258
7259         return 0;
7260 }
7261
7262 uint16_t
7263 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7264         switch (mac_type) {
7265         case ixgbe_mac_X550:
7266         case ixgbe_mac_X550EM_x:
7267         case ixgbe_mac_X550EM_a:
7268                 return ETH_RSS_RETA_SIZE_512;
7269         case ixgbe_mac_X550_vf:
7270         case ixgbe_mac_X550EM_x_vf:
7271         case ixgbe_mac_X550EM_a_vf:
7272                 return ETH_RSS_RETA_SIZE_64;
7273         default:
7274                 return ETH_RSS_RETA_SIZE_128;
7275         }
7276 }
7277
7278 uint32_t
7279 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7280         switch (mac_type) {
7281         case ixgbe_mac_X550:
7282         case ixgbe_mac_X550EM_x:
7283         case ixgbe_mac_X550EM_a:
7284                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7285                         return IXGBE_RETA(reta_idx >> 2);
7286                 else
7287                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7288         case ixgbe_mac_X550_vf:
7289         case ixgbe_mac_X550EM_x_vf:
7290         case ixgbe_mac_X550EM_a_vf:
7291                 return IXGBE_VFRETA(reta_idx >> 2);
7292         default:
7293                 return IXGBE_RETA(reta_idx >> 2);
7294         }
7295 }
7296
7297 uint32_t
7298 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7299         switch (mac_type) {
7300         case ixgbe_mac_X550_vf:
7301         case ixgbe_mac_X550EM_x_vf:
7302         case ixgbe_mac_X550EM_a_vf:
7303                 return IXGBE_VFMRQC;
7304         default:
7305                 return IXGBE_MRQC;
7306         }
7307 }
7308
7309 uint32_t
7310 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7311         switch (mac_type) {
7312         case ixgbe_mac_X550_vf:
7313         case ixgbe_mac_X550EM_x_vf:
7314         case ixgbe_mac_X550EM_a_vf:
7315                 return IXGBE_VFRSSRK(i);
7316         default:
7317                 return IXGBE_RSSRK(i);
7318         }
7319 }
7320
7321 bool
7322 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7323         switch (mac_type) {
7324         case ixgbe_mac_82599_vf:
7325         case ixgbe_mac_X540_vf:
7326                 return 0;
7327         default:
7328                 return 1;
7329         }
7330 }
7331
7332 static int
7333 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7334                         struct rte_eth_dcb_info *dcb_info)
7335 {
7336         struct ixgbe_dcb_config *dcb_config =
7337                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7338         struct ixgbe_dcb_tc_config *tc;
7339         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7340         uint8_t nb_tcs;
7341         uint8_t i, j;
7342
7343         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7344                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7345         else
7346                 dcb_info->nb_tcs = 1;
7347
7348         tc_queue = &dcb_info->tc_queue;
7349         nb_tcs = dcb_info->nb_tcs;
7350
7351         if (dcb_config->vt_mode) { /* vt is enabled*/
7352                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7353                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7354                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7355                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7356                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7357                         for (j = 0; j < nb_tcs; j++) {
7358                                 tc_queue->tc_rxq[0][j].base = j;
7359                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7360                                 tc_queue->tc_txq[0][j].base = j;
7361                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7362                         }
7363                 } else {
7364                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7365                                 for (j = 0; j < nb_tcs; j++) {
7366                                         tc_queue->tc_rxq[i][j].base =
7367                                                 i * nb_tcs + j;
7368                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7369                                         tc_queue->tc_txq[i][j].base =
7370                                                 i * nb_tcs + j;
7371                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7372                                 }
7373                         }
7374                 }
7375         } else { /* vt is disabled*/
7376                 struct rte_eth_dcb_rx_conf *rx_conf =
7377                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7378                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7379                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7380                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7381                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7382                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7383                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7384                         }
7385                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7386                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7387                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7388                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7389                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7390                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7391                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7392                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7393                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7394                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7395                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7396                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7397                         }
7398                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7399                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7400                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7401                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7402                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7403                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7404                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7405                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7406                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7407                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7408                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7409                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7410                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7411                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7412                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7413                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7414                 }
7415         }
7416         for (i = 0; i < dcb_info->nb_tcs; i++) {
7417                 tc = &dcb_config->tc_config[i];
7418                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7419         }
7420         return 0;
7421 }
7422
7423 /* Update e-tag ether type */
7424 static int
7425 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7426                             uint16_t ether_type)
7427 {
7428         uint32_t etag_etype;
7429
7430         if (hw->mac.type != ixgbe_mac_X550 &&
7431             hw->mac.type != ixgbe_mac_X550EM_x &&
7432             hw->mac.type != ixgbe_mac_X550EM_a) {
7433                 return -ENOTSUP;
7434         }
7435
7436         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7437         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7438         etag_etype |= ether_type;
7439         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7440         IXGBE_WRITE_FLUSH(hw);
7441
7442         return 0;
7443 }
7444
7445 /* Config l2 tunnel ether type */
7446 static int
7447 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7448                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7449 {
7450         int ret = 0;
7451         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7452         struct ixgbe_l2_tn_info *l2_tn_info =
7453                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7454
7455         if (l2_tunnel == NULL)
7456                 return -EINVAL;
7457
7458         switch (l2_tunnel->l2_tunnel_type) {
7459         case RTE_L2_TUNNEL_TYPE_E_TAG:
7460                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7461                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7462                 break;
7463         default:
7464                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7465                 ret = -EINVAL;
7466                 break;
7467         }
7468
7469         return ret;
7470 }
7471
7472 /* Enable e-tag tunnel */
7473 static int
7474 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7475 {
7476         uint32_t etag_etype;
7477
7478         if (hw->mac.type != ixgbe_mac_X550 &&
7479             hw->mac.type != ixgbe_mac_X550EM_x &&
7480             hw->mac.type != ixgbe_mac_X550EM_a) {
7481                 return -ENOTSUP;
7482         }
7483
7484         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7485         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7486         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7487         IXGBE_WRITE_FLUSH(hw);
7488
7489         return 0;
7490 }
7491
7492 /* Enable l2 tunnel */
7493 static int
7494 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7495                            enum rte_eth_tunnel_type l2_tunnel_type)
7496 {
7497         int ret = 0;
7498         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7499         struct ixgbe_l2_tn_info *l2_tn_info =
7500                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7501
7502         switch (l2_tunnel_type) {
7503         case RTE_L2_TUNNEL_TYPE_E_TAG:
7504                 l2_tn_info->e_tag_en = TRUE;
7505                 ret = ixgbe_e_tag_enable(hw);
7506                 break;
7507         default:
7508                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7509                 ret = -EINVAL;
7510                 break;
7511         }
7512
7513         return ret;
7514 }
7515
7516 /* Disable e-tag tunnel */
7517 static int
7518 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7519 {
7520         uint32_t etag_etype;
7521
7522         if (hw->mac.type != ixgbe_mac_X550 &&
7523             hw->mac.type != ixgbe_mac_X550EM_x &&
7524             hw->mac.type != ixgbe_mac_X550EM_a) {
7525                 return -ENOTSUP;
7526         }
7527
7528         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7529         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7530         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7531         IXGBE_WRITE_FLUSH(hw);
7532
7533         return 0;
7534 }
7535
7536 /* Disable l2 tunnel */
7537 static int
7538 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7539                             enum rte_eth_tunnel_type l2_tunnel_type)
7540 {
7541         int ret = 0;
7542         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7543         struct ixgbe_l2_tn_info *l2_tn_info =
7544                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7545
7546         switch (l2_tunnel_type) {
7547         case RTE_L2_TUNNEL_TYPE_E_TAG:
7548                 l2_tn_info->e_tag_en = FALSE;
7549                 ret = ixgbe_e_tag_disable(hw);
7550                 break;
7551         default:
7552                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7553                 ret = -EINVAL;
7554                 break;
7555         }
7556
7557         return ret;
7558 }
7559
7560 static int
7561 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7562                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7563 {
7564         int ret = 0;
7565         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7566         uint32_t i, rar_entries;
7567         uint32_t rar_low, rar_high;
7568
7569         if (hw->mac.type != ixgbe_mac_X550 &&
7570             hw->mac.type != ixgbe_mac_X550EM_x &&
7571             hw->mac.type != ixgbe_mac_X550EM_a) {
7572                 return -ENOTSUP;
7573         }
7574
7575         rar_entries = ixgbe_get_num_rx_addrs(hw);
7576
7577         for (i = 1; i < rar_entries; i++) {
7578                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7579                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7580                 if ((rar_high & IXGBE_RAH_AV) &&
7581                     (rar_high & IXGBE_RAH_ADTYPE) &&
7582                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7583                      l2_tunnel->tunnel_id)) {
7584                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7585                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7586
7587                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7588
7589                         return ret;
7590                 }
7591         }
7592
7593         return ret;
7594 }
7595
7596 static int
7597 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7598                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7599 {
7600         int ret = 0;
7601         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7602         uint32_t i, rar_entries;
7603         uint32_t rar_low, rar_high;
7604
7605         if (hw->mac.type != ixgbe_mac_X550 &&
7606             hw->mac.type != ixgbe_mac_X550EM_x &&
7607             hw->mac.type != ixgbe_mac_X550EM_a) {
7608                 return -ENOTSUP;
7609         }
7610
7611         /* One entry for one tunnel. Try to remove potential existing entry. */
7612         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7613
7614         rar_entries = ixgbe_get_num_rx_addrs(hw);
7615
7616         for (i = 1; i < rar_entries; i++) {
7617                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7618                 if (rar_high & IXGBE_RAH_AV) {
7619                         continue;
7620                 } else {
7621                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7622                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7623                         rar_low = l2_tunnel->tunnel_id;
7624
7625                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7626                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7627
7628                         return ret;
7629                 }
7630         }
7631
7632         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7633                      " Please remove a rule before adding a new one.");
7634         return -EINVAL;
7635 }
7636
7637 static inline struct ixgbe_l2_tn_filter *
7638 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7639                           struct ixgbe_l2_tn_key *key)
7640 {
7641         int ret;
7642
7643         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7644         if (ret < 0)
7645                 return NULL;
7646
7647         return l2_tn_info->hash_map[ret];
7648 }
7649
7650 static inline int
7651 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7652                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7653 {
7654         int ret;
7655
7656         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7657                                &l2_tn_filter->key);
7658
7659         if (ret < 0) {
7660                 PMD_DRV_LOG(ERR,
7661                             "Failed to insert L2 tunnel filter"
7662                             " to hash table %d!",
7663                             ret);
7664                 return ret;
7665         }
7666
7667         l2_tn_info->hash_map[ret] = l2_tn_filter;
7668
7669         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7670
7671         return 0;
7672 }
7673
7674 static inline int
7675 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7676                           struct ixgbe_l2_tn_key *key)
7677 {
7678         int ret;
7679         struct ixgbe_l2_tn_filter *l2_tn_filter;
7680
7681         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7682
7683         if (ret < 0) {
7684                 PMD_DRV_LOG(ERR,
7685                             "No such L2 tunnel filter to delete %d!",
7686                             ret);
7687                 return ret;
7688         }
7689
7690         l2_tn_filter = l2_tn_info->hash_map[ret];
7691         l2_tn_info->hash_map[ret] = NULL;
7692
7693         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7694         rte_free(l2_tn_filter);
7695
7696         return 0;
7697 }
7698
7699 /* Add l2 tunnel filter */
7700 int
7701 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7702                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7703                                bool restore)
7704 {
7705         int ret;
7706         struct ixgbe_l2_tn_info *l2_tn_info =
7707                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7708         struct ixgbe_l2_tn_key key;
7709         struct ixgbe_l2_tn_filter *node;
7710
7711         if (!restore) {
7712                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7713                 key.tn_id = l2_tunnel->tunnel_id;
7714
7715                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7716
7717                 if (node) {
7718                         PMD_DRV_LOG(ERR,
7719                                     "The L2 tunnel filter already exists!");
7720                         return -EINVAL;
7721                 }
7722
7723                 node = rte_zmalloc("ixgbe_l2_tn",
7724                                    sizeof(struct ixgbe_l2_tn_filter),
7725                                    0);
7726                 if (!node)
7727                         return -ENOMEM;
7728
7729                 rte_memcpy(&node->key,
7730                                  &key,
7731                                  sizeof(struct ixgbe_l2_tn_key));
7732                 node->pool = l2_tunnel->pool;
7733                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7734                 if (ret < 0) {
7735                         rte_free(node);
7736                         return ret;
7737                 }
7738         }
7739
7740         switch (l2_tunnel->l2_tunnel_type) {
7741         case RTE_L2_TUNNEL_TYPE_E_TAG:
7742                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7743                 break;
7744         default:
7745                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7746                 ret = -EINVAL;
7747                 break;
7748         }
7749
7750         if ((!restore) && (ret < 0))
7751                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7752
7753         return ret;
7754 }
7755
7756 /* Delete l2 tunnel filter */
7757 int
7758 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7759                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7760 {
7761         int ret;
7762         struct ixgbe_l2_tn_info *l2_tn_info =
7763                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7764         struct ixgbe_l2_tn_key key;
7765
7766         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7767         key.tn_id = l2_tunnel->tunnel_id;
7768         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7769         if (ret < 0)
7770                 return ret;
7771
7772         switch (l2_tunnel->l2_tunnel_type) {
7773         case RTE_L2_TUNNEL_TYPE_E_TAG:
7774                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7775                 break;
7776         default:
7777                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7778                 ret = -EINVAL;
7779                 break;
7780         }
7781
7782         return ret;
7783 }
7784
7785 /**
7786  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7787  * @dev: pointer to rte_eth_dev structure
7788  * @filter_op:operation will be taken.
7789  * @arg: a pointer to specific structure corresponding to the filter_op
7790  */
7791 static int
7792 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7793                                   enum rte_filter_op filter_op,
7794                                   void *arg)
7795 {
7796         int ret;
7797
7798         if (filter_op == RTE_ETH_FILTER_NOP)
7799                 return 0;
7800
7801         if (arg == NULL) {
7802                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7803                             filter_op);
7804                 return -EINVAL;
7805         }
7806
7807         switch (filter_op) {
7808         case RTE_ETH_FILTER_ADD:
7809                 ret = ixgbe_dev_l2_tunnel_filter_add
7810                         (dev,
7811                          (struct rte_eth_l2_tunnel_conf *)arg,
7812                          FALSE);
7813                 break;
7814         case RTE_ETH_FILTER_DELETE:
7815                 ret = ixgbe_dev_l2_tunnel_filter_del
7816                         (dev,
7817                          (struct rte_eth_l2_tunnel_conf *)arg);
7818                 break;
7819         default:
7820                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7821                 ret = -EINVAL;
7822                 break;
7823         }
7824         return ret;
7825 }
7826
7827 static int
7828 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7829 {
7830         int ret = 0;
7831         uint32_t ctrl;
7832         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7833
7834         if (hw->mac.type != ixgbe_mac_X550 &&
7835             hw->mac.type != ixgbe_mac_X550EM_x &&
7836             hw->mac.type != ixgbe_mac_X550EM_a) {
7837                 return -ENOTSUP;
7838         }
7839
7840         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7841         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7842         if (en)
7843                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7844         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7845
7846         return ret;
7847 }
7848
7849 /* Enable l2 tunnel forwarding */
7850 static int
7851 ixgbe_dev_l2_tunnel_forwarding_enable
7852         (struct rte_eth_dev *dev,
7853          enum rte_eth_tunnel_type l2_tunnel_type)
7854 {
7855         struct ixgbe_l2_tn_info *l2_tn_info =
7856                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7857         int ret = 0;
7858
7859         switch (l2_tunnel_type) {
7860         case RTE_L2_TUNNEL_TYPE_E_TAG:
7861                 l2_tn_info->e_tag_fwd_en = TRUE;
7862                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7863                 break;
7864         default:
7865                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7866                 ret = -EINVAL;
7867                 break;
7868         }
7869
7870         return ret;
7871 }
7872
7873 /* Disable l2 tunnel forwarding */
7874 static int
7875 ixgbe_dev_l2_tunnel_forwarding_disable
7876         (struct rte_eth_dev *dev,
7877          enum rte_eth_tunnel_type l2_tunnel_type)
7878 {
7879         struct ixgbe_l2_tn_info *l2_tn_info =
7880                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7881         int ret = 0;
7882
7883         switch (l2_tunnel_type) {
7884         case RTE_L2_TUNNEL_TYPE_E_TAG:
7885                 l2_tn_info->e_tag_fwd_en = FALSE;
7886                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7887                 break;
7888         default:
7889                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7890                 ret = -EINVAL;
7891                 break;
7892         }
7893
7894         return ret;
7895 }
7896
7897 static int
7898 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7899                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7900                              bool en)
7901 {
7902         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7903         int ret = 0;
7904         uint32_t vmtir, vmvir;
7905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7906
7907         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7908                 PMD_DRV_LOG(ERR,
7909                             "VF id %u should be less than %u",
7910                             l2_tunnel->vf_id,
7911                             pci_dev->max_vfs);
7912                 return -EINVAL;
7913         }
7914
7915         if (hw->mac.type != ixgbe_mac_X550 &&
7916             hw->mac.type != ixgbe_mac_X550EM_x &&
7917             hw->mac.type != ixgbe_mac_X550EM_a) {
7918                 return -ENOTSUP;
7919         }
7920
7921         if (en)
7922                 vmtir = l2_tunnel->tunnel_id;
7923         else
7924                 vmtir = 0;
7925
7926         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7927
7928         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7929         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7930         if (en)
7931                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7932         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7933
7934         return ret;
7935 }
7936
7937 /* Enable l2 tunnel tag insertion */
7938 static int
7939 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7940                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7941 {
7942         int ret = 0;
7943
7944         switch (l2_tunnel->l2_tunnel_type) {
7945         case RTE_L2_TUNNEL_TYPE_E_TAG:
7946                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7947                 break;
7948         default:
7949                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7950                 ret = -EINVAL;
7951                 break;
7952         }
7953
7954         return ret;
7955 }
7956
7957 /* Disable l2 tunnel tag insertion */
7958 static int
7959 ixgbe_dev_l2_tunnel_insertion_disable
7960         (struct rte_eth_dev *dev,
7961          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7962 {
7963         int ret = 0;
7964
7965         switch (l2_tunnel->l2_tunnel_type) {
7966         case RTE_L2_TUNNEL_TYPE_E_TAG:
7967                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7968                 break;
7969         default:
7970                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7971                 ret = -EINVAL;
7972                 break;
7973         }
7974
7975         return ret;
7976 }
7977
7978 static int
7979 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7980                              bool en)
7981 {
7982         int ret = 0;
7983         uint32_t qde;
7984         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7985
7986         if (hw->mac.type != ixgbe_mac_X550 &&
7987             hw->mac.type != ixgbe_mac_X550EM_x &&
7988             hw->mac.type != ixgbe_mac_X550EM_a) {
7989                 return -ENOTSUP;
7990         }
7991
7992         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7993         if (en)
7994                 qde |= IXGBE_QDE_STRIP_TAG;
7995         else
7996                 qde &= ~IXGBE_QDE_STRIP_TAG;
7997         qde &= ~IXGBE_QDE_READ;
7998         qde |= IXGBE_QDE_WRITE;
7999         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8000
8001         return ret;
8002 }
8003
8004 /* Enable l2 tunnel tag stripping */
8005 static int
8006 ixgbe_dev_l2_tunnel_stripping_enable
8007         (struct rte_eth_dev *dev,
8008          enum rte_eth_tunnel_type l2_tunnel_type)
8009 {
8010         int ret = 0;
8011
8012         switch (l2_tunnel_type) {
8013         case RTE_L2_TUNNEL_TYPE_E_TAG:
8014                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8015                 break;
8016         default:
8017                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8018                 ret = -EINVAL;
8019                 break;
8020         }
8021
8022         return ret;
8023 }
8024
8025 /* Disable l2 tunnel tag stripping */
8026 static int
8027 ixgbe_dev_l2_tunnel_stripping_disable
8028         (struct rte_eth_dev *dev,
8029          enum rte_eth_tunnel_type l2_tunnel_type)
8030 {
8031         int ret = 0;
8032
8033         switch (l2_tunnel_type) {
8034         case RTE_L2_TUNNEL_TYPE_E_TAG:
8035                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8036                 break;
8037         default:
8038                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8039                 ret = -EINVAL;
8040                 break;
8041         }
8042
8043         return ret;
8044 }
8045
8046 /* Enable/disable l2 tunnel offload functions */
8047 static int
8048 ixgbe_dev_l2_tunnel_offload_set
8049         (struct rte_eth_dev *dev,
8050          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8051          uint32_t mask,
8052          uint8_t en)
8053 {
8054         int ret = 0;
8055
8056         if (l2_tunnel == NULL)
8057                 return -EINVAL;
8058
8059         ret = -EINVAL;
8060         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8061                 if (en)
8062                         ret = ixgbe_dev_l2_tunnel_enable(
8063                                 dev,
8064                                 l2_tunnel->l2_tunnel_type);
8065                 else
8066                         ret = ixgbe_dev_l2_tunnel_disable(
8067                                 dev,
8068                                 l2_tunnel->l2_tunnel_type);
8069         }
8070
8071         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8072                 if (en)
8073                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8074                                 dev,
8075                                 l2_tunnel);
8076                 else
8077                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8078                                 dev,
8079                                 l2_tunnel);
8080         }
8081
8082         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8083                 if (en)
8084                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8085                                 dev,
8086                                 l2_tunnel->l2_tunnel_type);
8087                 else
8088                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8089                                 dev,
8090                                 l2_tunnel->l2_tunnel_type);
8091         }
8092
8093         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8094                 if (en)
8095                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8096                                 dev,
8097                                 l2_tunnel->l2_tunnel_type);
8098                 else
8099                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8100                                 dev,
8101                                 l2_tunnel->l2_tunnel_type);
8102         }
8103
8104         return ret;
8105 }
8106
8107 static int
8108 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8109                         uint16_t port)
8110 {
8111         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8112         IXGBE_WRITE_FLUSH(hw);
8113
8114         return 0;
8115 }
8116
8117 /* There's only one register for VxLAN UDP port.
8118  * So, we cannot add several ports. Will update it.
8119  */
8120 static int
8121 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8122                      uint16_t port)
8123 {
8124         if (port == 0) {
8125                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8126                 return -EINVAL;
8127         }
8128
8129         return ixgbe_update_vxlan_port(hw, port);
8130 }
8131
8132 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8133  * UDP port, it must have a value.
8134  * So, will reset it to the original value 0.
8135  */
8136 static int
8137 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8138                      uint16_t port)
8139 {
8140         uint16_t cur_port;
8141
8142         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8143
8144         if (cur_port != port) {
8145                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8146                 return -EINVAL;
8147         }
8148
8149         return ixgbe_update_vxlan_port(hw, 0);
8150 }
8151
8152 /* Add UDP tunneling port */
8153 static int
8154 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8155                               struct rte_eth_udp_tunnel *udp_tunnel)
8156 {
8157         int ret = 0;
8158         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8159
8160         if (hw->mac.type != ixgbe_mac_X550 &&
8161             hw->mac.type != ixgbe_mac_X550EM_x &&
8162             hw->mac.type != ixgbe_mac_X550EM_a) {
8163                 return -ENOTSUP;
8164         }
8165
8166         if (udp_tunnel == NULL)
8167                 return -EINVAL;
8168
8169         switch (udp_tunnel->prot_type) {
8170         case RTE_TUNNEL_TYPE_VXLAN:
8171                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8172                 break;
8173
8174         case RTE_TUNNEL_TYPE_GENEVE:
8175         case RTE_TUNNEL_TYPE_TEREDO:
8176                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8177                 ret = -EINVAL;
8178                 break;
8179
8180         default:
8181                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8182                 ret = -EINVAL;
8183                 break;
8184         }
8185
8186         return ret;
8187 }
8188
8189 /* Remove UDP tunneling port */
8190 static int
8191 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8192                               struct rte_eth_udp_tunnel *udp_tunnel)
8193 {
8194         int ret = 0;
8195         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8196
8197         if (hw->mac.type != ixgbe_mac_X550 &&
8198             hw->mac.type != ixgbe_mac_X550EM_x &&
8199             hw->mac.type != ixgbe_mac_X550EM_a) {
8200                 return -ENOTSUP;
8201         }
8202
8203         if (udp_tunnel == NULL)
8204                 return -EINVAL;
8205
8206         switch (udp_tunnel->prot_type) {
8207         case RTE_TUNNEL_TYPE_VXLAN:
8208                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8209                 break;
8210         case RTE_TUNNEL_TYPE_GENEVE:
8211         case RTE_TUNNEL_TYPE_TEREDO:
8212                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8213                 ret = -EINVAL;
8214                 break;
8215         default:
8216                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8217                 ret = -EINVAL;
8218                 break;
8219         }
8220
8221         return ret;
8222 }
8223
8224 static void
8225 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8226 {
8227         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8228
8229         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8230 }
8231
8232 static void
8233 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8234 {
8235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8236
8237         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8238 }
8239
8240 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8241 {
8242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8243         u32 in_msg = 0;
8244
8245         /* peek the message first */
8246         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8247
8248         /* PF reset VF event */
8249         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8250                 /* dummy mbx read to ack pf */
8251                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8252                         return;
8253                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8254                                               NULL);
8255         }
8256 }
8257
8258 static int
8259 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8260 {
8261         uint32_t eicr;
8262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8263         struct ixgbe_interrupt *intr =
8264                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8265         ixgbevf_intr_disable(hw);
8266
8267         /* read-on-clear nic registers here */
8268         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8269         intr->flags = 0;
8270
8271         /* only one misc vector supported - mailbox */
8272         eicr &= IXGBE_VTEICR_MASK;
8273         if (eicr == IXGBE_MISC_VEC_ID)
8274                 intr->flags |= IXGBE_FLAG_MAILBOX;
8275
8276         return 0;
8277 }
8278
8279 static int
8280 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8281 {
8282         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8283         struct ixgbe_interrupt *intr =
8284                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8285
8286         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8287                 ixgbevf_mbx_process(dev);
8288                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8289         }
8290
8291         ixgbevf_intr_enable(hw);
8292
8293         return 0;
8294 }
8295
8296 static void
8297 ixgbevf_dev_interrupt_handler(void *param)
8298 {
8299         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8300
8301         ixgbevf_dev_interrupt_get_status(dev);
8302         ixgbevf_dev_interrupt_action(dev);
8303 }
8304
8305 /**
8306  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8307  *  @hw: pointer to hardware structure
8308  *
8309  *  Stops the transmit data path and waits for the HW to internally empty
8310  *  the Tx security block
8311  **/
8312 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8313 {
8314 #define IXGBE_MAX_SECTX_POLL 40
8315
8316         int i;
8317         int sectxreg;
8318
8319         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8320         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8321         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8322         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8323                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8324                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8325                         break;
8326                 /* Use interrupt-safe sleep just in case */
8327                 usec_delay(1000);
8328         }
8329
8330         /* For informational purposes only */
8331         if (i >= IXGBE_MAX_SECTX_POLL)
8332                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8333                          "path fully disabled.  Continuing with init.");
8334
8335         return IXGBE_SUCCESS;
8336 }
8337
8338 /**
8339  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8340  *  @hw: pointer to hardware structure
8341  *
8342  *  Enables the transmit data path.
8343  **/
8344 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8345 {
8346         uint32_t sectxreg;
8347
8348         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8349         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8350         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8351         IXGBE_WRITE_FLUSH(hw);
8352
8353         return IXGBE_SUCCESS;
8354 }
8355
8356 /* restore n-tuple filter */
8357 static inline void
8358 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8359 {
8360         struct ixgbe_filter_info *filter_info =
8361                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8362         struct ixgbe_5tuple_filter *node;
8363
8364         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8365                 ixgbe_inject_5tuple_filter(dev, node);
8366         }
8367 }
8368
8369 /* restore ethernet type filter */
8370 static inline void
8371 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8372 {
8373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8374         struct ixgbe_filter_info *filter_info =
8375                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8376         int i;
8377
8378         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8379                 if (filter_info->ethertype_mask & (1 << i)) {
8380                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8381                                         filter_info->ethertype_filters[i].etqf);
8382                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8383                                         filter_info->ethertype_filters[i].etqs);
8384                         IXGBE_WRITE_FLUSH(hw);
8385                 }
8386         }
8387 }
8388
8389 /* restore SYN filter */
8390 static inline void
8391 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8392 {
8393         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8394         struct ixgbe_filter_info *filter_info =
8395                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8396         uint32_t synqf;
8397
8398         synqf = filter_info->syn_info;
8399
8400         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8401                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8402                 IXGBE_WRITE_FLUSH(hw);
8403         }
8404 }
8405
8406 /* restore L2 tunnel filter */
8407 static inline void
8408 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8409 {
8410         struct ixgbe_l2_tn_info *l2_tn_info =
8411                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8412         struct ixgbe_l2_tn_filter *node;
8413         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8414
8415         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8416                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8417                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8418                 l2_tn_conf.pool           = node->pool;
8419                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8420         }
8421 }
8422
8423 /* restore rss filter */
8424 static inline void
8425 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8426 {
8427         struct ixgbe_filter_info *filter_info =
8428                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8429
8430         if (filter_info->rss_info.conf.queue_num)
8431                 ixgbe_config_rss_filter(dev,
8432                         &filter_info->rss_info, TRUE);
8433 }
8434
8435 static int
8436 ixgbe_filter_restore(struct rte_eth_dev *dev)
8437 {
8438         ixgbe_ntuple_filter_restore(dev);
8439         ixgbe_ethertype_filter_restore(dev);
8440         ixgbe_syn_filter_restore(dev);
8441         ixgbe_fdir_filter_restore(dev);
8442         ixgbe_l2_tn_filter_restore(dev);
8443         ixgbe_rss_filter_restore(dev);
8444
8445         return 0;
8446 }
8447
8448 static void
8449 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8450 {
8451         struct ixgbe_l2_tn_info *l2_tn_info =
8452                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8453         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8454
8455         if (l2_tn_info->e_tag_en)
8456                 (void)ixgbe_e_tag_enable(hw);
8457
8458         if (l2_tn_info->e_tag_fwd_en)
8459                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8460
8461         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8462 }
8463
8464 /* remove all the n-tuple filters */
8465 void
8466 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8467 {
8468         struct ixgbe_filter_info *filter_info =
8469                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8470         struct ixgbe_5tuple_filter *p_5tuple;
8471
8472         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8473                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8474 }
8475
8476 /* remove all the ether type filters */
8477 void
8478 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8479 {
8480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8481         struct ixgbe_filter_info *filter_info =
8482                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8483         int i;
8484
8485         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8486                 if (filter_info->ethertype_mask & (1 << i) &&
8487                     !filter_info->ethertype_filters[i].conf) {
8488                         (void)ixgbe_ethertype_filter_remove(filter_info,
8489                                                             (uint8_t)i);
8490                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8491                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8492                         IXGBE_WRITE_FLUSH(hw);
8493                 }
8494         }
8495 }
8496
8497 /* remove the SYN filter */
8498 void
8499 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8500 {
8501         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8502         struct ixgbe_filter_info *filter_info =
8503                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8504
8505         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8506                 filter_info->syn_info = 0;
8507
8508                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8509                 IXGBE_WRITE_FLUSH(hw);
8510         }
8511 }
8512
8513 /* remove all the L2 tunnel filters */
8514 int
8515 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8516 {
8517         struct ixgbe_l2_tn_info *l2_tn_info =
8518                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8519         struct ixgbe_l2_tn_filter *l2_tn_filter;
8520         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8521         int ret = 0;
8522
8523         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8524                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8525                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8526                 l2_tn_conf.pool           = l2_tn_filter->pool;
8527                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8528                 if (ret < 0)
8529                         return ret;
8530         }
8531
8532         return 0;
8533 }
8534
8535 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8536 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8537 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8538 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8539 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8540 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8541
8542 RTE_INIT(ixgbe_init_log);
8543 static void
8544 ixgbe_init_log(void)
8545 {
8546         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8547         if (ixgbe_logtype_init >= 0)
8548                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8549         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8550         if (ixgbe_logtype_driver >= 0)
8551                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8552 }