drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 142 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 143 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 144 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 147 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 154                                 int wait_to_complete);
 155 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *stats);
 157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstats *xstats, unsigned n);
 159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 160                                   struct rte_eth_xstats *xstats, unsigned n);
 161 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 163 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 164                                              uint16_t queue_id,
 165                                              uint8_t stat_idx,
 166                                              uint8_t is_rx);
 167 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 168                                struct rte_eth_dev_info *dev_info);
 169 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 170                                  struct rte_eth_dev_info *dev_info);
 171 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 172
 173 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 174                 uint16_t vlan_id, int on);
 175 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 176 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 177                 uint16_t queue, bool on);
 178 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 179                 int on);
 180 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 181 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 182 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 183 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 184 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 185
 186 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 187 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 188 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 189                                struct rte_eth_fc_conf *fc_conf);
 190 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 191                                struct rte_eth_fc_conf *fc_conf);
 192 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 193                 struct rte_eth_pfc_conf *pfc_conf);
 194 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 195                         struct rte_eth_rss_reta_entry64 *reta_conf,
 196                         uint16_t reta_size);
 197 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 198                         struct rte_eth_rss_reta_entry64 *reta_conf,
 199                         uint16_t reta_size);
 200 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 201 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 203 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 204 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 205 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 206                 void *param);
 207 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 208 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 209                 uint32_t index, uint32_t pool);
 210 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 211 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 212                                            struct ether_addr *mac_addr);
 213 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 214
 215 /* For Virtual Function support */
 216 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 219 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 220 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 221 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 222 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 223 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 224 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 225                 struct rte_eth_stats *stats);
 226 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 227 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 228                 uint16_t vlan_id, int on);
 229 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 230                 uint16_t queue, int on);
 231 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 232 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 233 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 234                                             uint16_t queue_id);
 235 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 236                                              uint16_t queue_id);
 237 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 238                                  uint8_t queue, uint8_t msix_vector);
 239 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 240
 241 /* For Eth VMDQ APIs support */
 242 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 243                 ether_addr* mac_addr,uint8_t on);
 244 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 245 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 246                 uint16_t rx_mask, uint8_t on);
 247 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 248 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 249 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 250                 uint64_t pool_mask,uint8_t vlan_on);
 251 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 252                 struct rte_eth_mirror_conf *mirror_conf,
 253                 uint8_t rule_id, uint8_t on);
 254 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 255                 uint8_t rule_id);
 256 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 257                                           uint16_t queue_id);
 258 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 259                                            uint16_t queue_id);
 260 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 261                                uint8_t queue, uint8_t msix_vector);
 262 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 263
 264 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 265                 uint16_t queue_idx, uint16_t tx_rate);
 266 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 267                 uint16_t tx_rate, uint64_t q_msk);
 268
 269 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 270                                  struct ether_addr *mac_addr,
 271                                  uint32_t index, uint32_t pool);
 272 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 273 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                                              struct ether_addr *mac_addr);
 275 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 276                         struct rte_eth_syn_filter *filter,
 277                         bool add);
 278 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 279                         struct rte_eth_syn_filter *filter);
 280 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 281                         enum rte_filter_op filter_op,
 282                         void *arg);
 283 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 284                         struct ixgbe_5tuple_filter *filter);
 285 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 286                         struct ixgbe_5tuple_filter *filter);
 287 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 288                         struct rte_eth_ntuple_filter *filter,
 289                         bool add);
 290 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 291                                 enum rte_filter_op filter_op,
 292                                 void *arg);
 293 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 294                         struct rte_eth_ntuple_filter *filter);
 295 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 296                         struct rte_eth_ethertype_filter *filter,
 297                         bool add);
 298 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 299                                 enum rte_filter_op filter_op,
 300                                 void *arg);
 301 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 302                         struct rte_eth_ethertype_filter *filter);
 303 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 304                      enum rte_filter_type filter_type,
 305                      enum rte_filter_op filter_op,
 306                      void *arg);
 307 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 308
 309 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 310                                       struct ether_addr *mc_addr_set,
 311                                       uint32_t nb_mc_addr);
 312 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 313                                    struct rte_eth_dcb_info *dcb_info);
 314
 315 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 316 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 317                             struct rte_dev_reg_info *regs);
 318 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 319 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 320                                 struct rte_dev_eeprom_info *eeprom);
 321 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 322                                 struct rte_dev_eeprom_info *eeprom);
 323
 324 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 325 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 326                                 struct rte_dev_reg_info *regs);
 327
 328 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 329 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 330 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 331                                             struct timespec *timestamp,
 332                                             uint32_t flags);
 333 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 334                                             struct timespec *timestamp);
 335 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 336 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 337                                    struct timespec *timestamp);
 338 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 339                                    const struct timespec *timestamp);
 340
 341 /*
 342  * Define VF Stats MACRO for Non "cleared on read" register
 343  */
 344 #define UPDATE_VF_STAT(reg, last, cur)                          \
 345 {                                                               \
 346         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 347         cur += (latest - last) & UINT_MAX;                      \
 348         last = latest;                                          \
 349 }
 350
 351 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 352 {                                                                \
 353         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 354         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 355         u64 latest = ((new_msb << 32) | new_lsb);                \
 356         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 357         last = latest;                                           \
 358 }
 359
 360 #define IXGBE_SET_HWSTRIP(h, q) do{\
 361                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 362                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 363                 (h)->bitmap[idx] |= 1 << bit;\
 364         }while(0)
 365
 366 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 367                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 368                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 369                 (h)->bitmap[idx] &= ~(1 << bit);\
 370         }while(0)
 371
 372 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 373                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 374                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 375                 (r) = (h)->bitmap[idx] >> bit & 1;\
 376         }while(0)
 377
 378 /*
 379  * The set of PCI devices this driver supports
 380  */
 381 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 382
 383 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 384 #include "rte_pci_dev_ids.h"
 385
 386 { .vendor_id = 0, /* sentinel */ },
 387 };
 388
 389
 390 /*
 391  * The set of PCI devices this driver supports (for 82599 VF)
 392  */
 393 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 394
 395 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 396 #include "rte_pci_dev_ids.h"
 397 { .vendor_id = 0, /* sentinel */ },
 398
 399 };
 400
 401 static const struct rte_eth_desc_lim rx_desc_lim = {
 402         .nb_max = IXGBE_MAX_RING_DESC,
 403         .nb_min = IXGBE_MIN_RING_DESC,
 404         .nb_align = IXGBE_RXD_ALIGN,
 405 };
 406
 407 static const struct rte_eth_desc_lim tx_desc_lim = {
 408         .nb_max = IXGBE_MAX_RING_DESC,
 409         .nb_min = IXGBE_MIN_RING_DESC,
 410         .nb_align = IXGBE_TXD_ALIGN,
 411 };
 412
 413 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 414         .dev_configure        = ixgbe_dev_configure,
 415         .dev_start            = ixgbe_dev_start,
 416         .dev_stop             = ixgbe_dev_stop,
 417         .dev_set_link_up    = ixgbe_dev_set_link_up,
 418         .dev_set_link_down  = ixgbe_dev_set_link_down,
 419         .dev_close            = ixgbe_dev_close,
 420         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 421         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 422         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 423         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 424         .link_update          = ixgbe_dev_link_update,
 425         .stats_get            = ixgbe_dev_stats_get,
 426         .xstats_get           = ixgbe_dev_xstats_get,
 427         .stats_reset          = ixgbe_dev_stats_reset,
 428         .xstats_reset         = ixgbe_dev_xstats_reset,
 429         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 430         .dev_infos_get        = ixgbe_dev_info_get,
 431         .mtu_set              = ixgbe_dev_mtu_set,
 432         .vlan_filter_set      = ixgbe_vlan_filter_set,
 433         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 434         .vlan_offload_set     = ixgbe_vlan_offload_set,
 435         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 436         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 437         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 438         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 439         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 440         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 441         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 442         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 443         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 444         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 445         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 446         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 447         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 448         .dev_led_on           = ixgbe_dev_led_on,
 449         .dev_led_off          = ixgbe_dev_led_off,
 450         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 451         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 452         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 453         .mac_addr_add         = ixgbe_add_rar,
 454         .mac_addr_remove      = ixgbe_remove_rar,
 455         .mac_addr_set         = ixgbe_set_default_mac_addr,
 456         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 457         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 458         .mirror_rule_set      = ixgbe_mirror_rule_set,
 459         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 460         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 461         .set_vf_rx            = ixgbe_set_pool_rx,
 462         .set_vf_tx            = ixgbe_set_pool_tx,
 463         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 464         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 465         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 466         .reta_update          = ixgbe_dev_rss_reta_update,
 467         .reta_query           = ixgbe_dev_rss_reta_query,
 468 #ifdef RTE_NIC_BYPASS
 469         .bypass_init          = ixgbe_bypass_init,
 470         .bypass_state_set     = ixgbe_bypass_state_store,
 471         .bypass_state_show    = ixgbe_bypass_state_show,
 472         .bypass_event_set     = ixgbe_bypass_event_store,
 473         .bypass_event_show    = ixgbe_bypass_event_show,
 474         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 475         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 476         .bypass_ver_show      = ixgbe_bypass_ver_show,
 477         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 478 #endif /* RTE_NIC_BYPASS */
 479         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 480         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 481         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 482         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 483         .rxq_info_get         = ixgbe_rxq_info_get,
 484         .txq_info_get         = ixgbe_txq_info_get,
 485         .timesync_enable      = ixgbe_timesync_enable,
 486         .timesync_disable     = ixgbe_timesync_disable,
 487         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 488         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 489         .get_reg_length       = ixgbe_get_reg_length,
 490         .get_reg              = ixgbe_get_regs,
 491         .get_eeprom_length    = ixgbe_get_eeprom_length,
 492         .get_eeprom           = ixgbe_get_eeprom,
 493         .set_eeprom           = ixgbe_set_eeprom,
 494         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 495         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 496         .timesync_read_time   = ixgbe_timesync_read_time,
 497         .timesync_write_time  = ixgbe_timesync_write_time,
 498 };
 499
 500 /*
 501  * dev_ops for virtual function, bare necessities for basic vf
 502  * operation have been implemented
 503  */
 504 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 505         .dev_configure        = ixgbevf_dev_configure,
 506         .dev_start            = ixgbevf_dev_start,
 507         .dev_stop             = ixgbevf_dev_stop,
 508         .link_update          = ixgbe_dev_link_update,
 509         .stats_get            = ixgbevf_dev_stats_get,
 510         .xstats_get           = ixgbevf_dev_xstats_get,
 511         .stats_reset          = ixgbevf_dev_stats_reset,
 512         .xstats_reset         = ixgbevf_dev_stats_reset,
 513         .dev_close            = ixgbevf_dev_close,
 514         .dev_infos_get        = ixgbevf_dev_info_get,
 515         .mtu_set              = ixgbevf_dev_set_mtu,
 516         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 517         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 518         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 519         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 520         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 521         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 522         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 523         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 524         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 525         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 526         .mac_addr_add         = ixgbevf_add_mac_addr,
 527         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 528         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 529         .rxq_info_get         = ixgbe_rxq_info_get,
 530         .txq_info_get         = ixgbe_txq_info_get,
 531         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 532         .get_reg_length       = ixgbevf_get_reg_length,
 533         .get_reg              = ixgbevf_get_regs,
 534         .reta_update          = ixgbe_dev_rss_reta_update,
 535         .reta_query           = ixgbe_dev_rss_reta_query,
 536         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 537         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 538 };
 539
 540 /* store statistics names and its offset in stats structure */
 541 struct rte_ixgbe_xstats_name_off {
 542         char name[RTE_ETH_XSTATS_NAME_SIZE];
 543         unsigned offset;
 544 };
 545
 546 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 547         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 548         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 549         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 550         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 551         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 552         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 553         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 554         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 555         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 556         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 557         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 558         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 559         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 560         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 561         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 562                 prc1023)},
 563         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 564                 prc1522)},
 565         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 566         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 567         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 568         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 569         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 570         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 571         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 572         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 573         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 574         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 575         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 576         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 577         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 578         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 579         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 580         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 581         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 582                 ptc1023)},
 583         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 584                 ptc1522)},
 585         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 586         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 587         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 588         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 589
 590         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 591                 fdirustat_add)},
 592         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 593                 fdirustat_remove)},
 594         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 595                 fdirfstat_fadd)},
 596         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 597                 fdirfstat_fremove)},
 598         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 599                 fdirmatch)},
 600         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 601                 fdirmiss)},
 602
 603         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 604         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 605         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 606                 fclast)},
 607         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 608         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 609         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 610         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 611         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 612                 fcoe_noddp)},
 613         {"rx_fcoe_no_direct_data_placement_ext_buff",
 614                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 615
 616         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 617                 lxontxc)},
 618         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 619                 lxonrxc)},
 620         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 621                 lxofftxc)},
 622         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 623                 lxoffrxc)},
 624         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 625 };
 626
 627 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 628                            sizeof(rte_ixgbe_stats_strings[0]))
 629
 630 /* Per-queue statistics */
 631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 632         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 633         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 634         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 635         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 636 };
 637
 638 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 639                            sizeof(rte_ixgbe_rxq_strings[0]))
 640
 641 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 642         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 643         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 644         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 645                 pxon2offc)},
 646 };
 647
 648 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 649                            sizeof(rte_ixgbe_txq_strings[0]))
 650
 651 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 652         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 653 };
 654
 655 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 656                 sizeof(rte_ixgbevf_stats_strings[0]))
 657
 658 /**
 659  * Atomically reads the link status information from global
 660  * structure rte_eth_dev.
 661  *
 662  * @param dev
 663  *   - Pointer to the structure rte_eth_dev to read from.
 664  *   - Pointer to the buffer to be saved with the link status.
 665  *
 666  * @return
 667  *   - On success, zero.
 668  *   - On failure, negative value.
 669  */
 670 static inline int
 671 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 672                                 struct rte_eth_link *link)
 673 {
 674         struct rte_eth_link *dst = link;
 675         struct rte_eth_link *src = &(dev->data->dev_link);
 676
 677         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 678                                         *(uint64_t *)src) == 0)
 679                 return -1;
 680
 681         return 0;
 682 }
 683
 684 /**
 685  * Atomically writes the link status information into global
 686  * structure rte_eth_dev.
 687  *
 688  * @param dev
 689  *   - Pointer to the structure rte_eth_dev to read from.
 690  *   - Pointer to the buffer to be saved with the link status.
 691  *
 692  * @return
 693  *   - On success, zero.
 694  *   - On failure, negative value.
 695  */
 696 static inline int
 697 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 698                                 struct rte_eth_link *link)
 699 {
 700         struct rte_eth_link *dst = &(dev->data->dev_link);
 701         struct rte_eth_link *src = link;
 702
 703         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 704                                         *(uint64_t *)src) == 0)
 705                 return -1;
 706
 707         return 0;
 708 }
 709
 710 /*
 711  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 712  */
 713 static inline int
 714 ixgbe_is_sfp(struct ixgbe_hw *hw)
 715 {
 716         switch (hw->phy.type) {
 717         case ixgbe_phy_sfp_avago:
 718         case ixgbe_phy_sfp_ftl:
 719         case ixgbe_phy_sfp_intel:
 720         case ixgbe_phy_sfp_unknown:
 721         case ixgbe_phy_sfp_passive_tyco:
 722         case ixgbe_phy_sfp_passive_unknown:
 723                 return 1;
 724         default:
 725                 return 0;
 726         }
 727 }
 728
 729 static inline int32_t
 730 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 731 {
 732         uint32_t ctrl_ext;
 733         int32_t status;
 734
 735         status = ixgbe_reset_hw(hw);
 736
 737         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 738         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 739         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 740         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 741         IXGBE_WRITE_FLUSH(hw);
 742
 743         return status;
 744 }
 745
 746 static inline void
 747 ixgbe_enable_intr(struct rte_eth_dev *dev)
 748 {
 749         struct ixgbe_interrupt *intr =
 750                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 751         struct ixgbe_hw *hw =
 752                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753
 754         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 755         IXGBE_WRITE_FLUSH(hw);
 756 }
 757
 758 /*
 759  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 760  */
 761 static void
 762 ixgbe_disable_intr(struct ixgbe_hw *hw)
 763 {
 764         PMD_INIT_FUNC_TRACE();
 765
 766         if (hw->mac.type == ixgbe_mac_82598EB) {
 767                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 768         } else {
 769                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 770                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 771                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 772         }
 773         IXGBE_WRITE_FLUSH(hw);
 774 }
 775
 776 /*
 777  * This function resets queue statistics mapping registers.
 778  * From Niantic datasheet, Initialization of Statistics section:
 779  * "...if software requires the queue counters, the RQSMR and TQSM registers
 780  * must be re-programmed following a device reset.
 781  */
 782 static void
 783 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 784 {
 785         uint32_t i;
 786
 787         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 788                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 789                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 790         }
 791 }
 792
 793
 794 static int
 795 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 796                                   uint16_t queue_id,
 797                                   uint8_t stat_idx,
 798                                   uint8_t is_rx)
 799 {
 800 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 801 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 802 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 803
 804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 805         struct ixgbe_stat_mapping_registers *stat_mappings =
 806                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 807         uint32_t qsmr_mask = 0;
 808         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 809         uint32_t q_map;
 810         uint8_t n, offset;
 811
 812         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 813                 (hw->mac.type != ixgbe_mac_X540) &&
 814                 (hw->mac.type != ixgbe_mac_X550) &&
 815                 (hw->mac.type != ixgbe_mac_X550EM_x))
 816                 return -ENOSYS;
 817
 818         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 819                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 820                      queue_id, stat_idx);
 821
 822         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 823         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 824                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 825                 return -EIO;
 826         }
 827         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 828
 829         /* Now clear any previous stat_idx set */
 830         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 831         if (!is_rx)
 832                 stat_mappings->tqsm[n] &= ~clearing_mask;
 833         else
 834                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 835
 836         q_map = (uint32_t)stat_idx;
 837         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 838         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 839         if (!is_rx)
 840                 stat_mappings->tqsm[n] |= qsmr_mask;
 841         else
 842                 stat_mappings->rqsmr[n] |= qsmr_mask;
 843
 844         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 845                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 846                      queue_id, stat_idx);
 847         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 848                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 849
 850         /* Now write the mapping in the appropriate register */
 851         if (is_rx) {
 852                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 853                              stat_mappings->rqsmr[n], n);
 854                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 855         }
 856         else {
 857                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 858                              stat_mappings->tqsm[n], n);
 859                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 860         }
 861         return 0;
 862 }
 863
 864 static void
 865 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 866 {
 867         struct ixgbe_stat_mapping_registers *stat_mappings =
 868                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 869         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 870         int i;
 871
 872         /* write whatever was in stat mapping table to the NIC */
 873         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 /* rx */
 875                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 876
 877                 /* tx */
 878                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 879         }
 880 }
 881
 882 static void
 883 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 884 {
 885         uint8_t i;
 886         struct ixgbe_dcb_tc_config *tc;
 887         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 888
 889         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 890         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 891         for (i = 0; i < dcb_max_tc; i++) {
 892                 tc = &dcb_config->tc_config[i];
 893                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 894                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 895                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 896                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 897                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 898                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 899                 tc->pfc = ixgbe_dcb_pfc_disabled;
 900         }
 901
 902         /* Initialize default user to priority mapping, UPx->TC0 */
 903         tc = &dcb_config->tc_config[0];
 904         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 905         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 906         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 907                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 908                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 909         }
 910         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 911         dcb_config->pfc_mode_enable = false;
 912         dcb_config->vt_mode = true;
 913         dcb_config->round_robin_enable = false;
 914         /* support all DCB capabilities in 82599 */
 915         dcb_config->support.capabilities = 0xFF;
 916
 917         /*we only support 4 Tcs for X540, X550 */
 918         if (hw->mac.type == ixgbe_mac_X540 ||
 919                 hw->mac.type == ixgbe_mac_X550 ||
 920                 hw->mac.type == ixgbe_mac_X550EM_x) {
 921                 dcb_config->num_tcs.pg_tcs = 4;
 922                 dcb_config->num_tcs.pfc_tcs = 4;
 923         }
 924 }
 925
 926 /*
 927  * Ensure that all locks are released before first NVM or PHY access
 928  */
 929 static void
 930 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 931 {
 932         uint16_t mask;
 933
 934         /*
 935          * Phy lock should not fail in this early stage. If this is the case,
 936          * it is due to an improper exit of the application.
 937          * So force the release of the faulty lock. Release of common lock
 938          * is done automatically by swfw_sync function.
 939          */
 940         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 941         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 942                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 943         }
 944         ixgbe_release_swfw_semaphore(hw, mask);
 945
 946         /*
 947          * These ones are more tricky since they are common to all ports; but
 948          * swfw_sync retries last long enough (1s) to be almost sure that if
 949          * lock can not be taken it is due to an improper lock of the
 950          * semaphore.
 951          */
 952         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 953         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 954                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 955         }
 956         ixgbe_release_swfw_semaphore(hw, mask);
 957 }
 958
 959 /*
 960  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 961  * It returns 0 on success.
 962  */
 963 static int
 964 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 965 {
 966         struct rte_pci_device *pci_dev;
 967         struct ixgbe_hw *hw =
 968                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 969         struct ixgbe_vfta * shadow_vfta =
 970                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 971         struct ixgbe_hwstrip *hwstrip =
 972                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 973         struct ixgbe_dcb_config *dcb_config =
 974                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 975         struct ixgbe_filter_info *filter_info =
 976                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 977         uint32_t ctrl_ext;
 978         uint16_t csum;
 979         int diag, i;
 980
 981         PMD_INIT_FUNC_TRACE();
 982
 983         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 984         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 985         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 986
 987         /*
 988          * For secondary processes, we don't initialise any further as primary
 989          * has already done this work. Only check we don't need a different
 990          * RX and TX function.
 991          */
 992         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 993                 struct ixgbe_tx_queue *txq;
 994                 /* TX queue function in primary, set by last queue initialized
 995                  * Tx queue may not initialized by primary process */
 996                 if (eth_dev->data->tx_queues) {
 997                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 998                         ixgbe_set_tx_function(eth_dev, txq);
 999                 } else {
1000                         /* Use default TX function if we get here */
1001                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1002                                              "Using default TX function.");
1003                 }
1004
1005                 ixgbe_set_rx_function(eth_dev);
1006
1007                 return 0;
1008         }
1009         pci_dev = eth_dev->pci_dev;
1010
1011         rte_eth_copy_pci_info(eth_dev, pci_dev);
1012
1013         /* Vendor and Device ID need to be set before init of shared code */
1014         hw->device_id = pci_dev->id.device_id;
1015         hw->vendor_id = pci_dev->id.vendor_id;
1016         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1017         hw->allow_unsupported_sfp = 1;
1018
1019         /* Initialize the shared code (base driver) */
1020 #ifdef RTE_NIC_BYPASS
1021         diag = ixgbe_bypass_init_shared_code(hw);
1022 #else
1023         diag = ixgbe_init_shared_code(hw);
1024 #endif /* RTE_NIC_BYPASS */
1025
1026         if (diag != IXGBE_SUCCESS) {
1027                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1028                 return -EIO;
1029         }
1030
1031         /* pick up the PCI bus settings for reporting later */
1032         ixgbe_get_bus_info(hw);
1033
1034         /* Unlock any pending hardware semaphore */
1035         ixgbe_swfw_lock_reset(hw);
1036
1037         /* Initialize DCB configuration*/
1038         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1039         ixgbe_dcb_init(hw,dcb_config);
1040         /* Get Hardware Flow Control setting */
1041         hw->fc.requested_mode = ixgbe_fc_full;
1042         hw->fc.current_mode = ixgbe_fc_full;
1043         hw->fc.pause_time = IXGBE_FC_PAUSE;
1044         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1045                 hw->fc.low_water[i] = IXGBE_FC_LO;
1046                 hw->fc.high_water[i] = IXGBE_FC_HI;
1047         }
1048         hw->fc.send_xon = 1;
1049
1050         /* Make sure we have a good EEPROM before we read from it */
1051         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1052         if (diag != IXGBE_SUCCESS) {
1053                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1054                 return -EIO;
1055         }
1056
1057 #ifdef RTE_NIC_BYPASS
1058         diag = ixgbe_bypass_init_hw(hw);
1059 #else
1060         diag = ixgbe_init_hw(hw);
1061 #endif /* RTE_NIC_BYPASS */
1062
1063         /*
1064          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1065          * is called too soon after the kernel driver unbinding/binding occurs.
1066          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1067          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1068          * also called. See ixgbe_identify_phy_82599(). The reason for the
1069          * failure is not known, and only occuts when virtualisation features
1070          * are disabled in the bios. A delay of 100ms  was found to be enough by
1071          * trial-and-error, and is doubled to be safe.
1072          */
1073         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1074                 rte_delay_ms(200);
1075                 diag = ixgbe_init_hw(hw);
1076         }
1077
1078         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1079                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1080                     "LOM.  Please be aware there may be issues associated "
1081                     "with your hardware.");
1082                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1083                     "please contact your Intel or hardware representative "
1084                     "who provided you with this hardware.");
1085         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1086                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1087         if (diag) {
1088                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1089                 return -EIO;
1090         }
1091
1092         /* Reset the hw statistics */
1093         ixgbe_dev_stats_reset(eth_dev);
1094
1095         /* disable interrupt */
1096         ixgbe_disable_intr(hw);
1097
1098         /* reset mappings for queue statistics hw counters*/
1099         ixgbe_reset_qstat_mappings(hw);
1100
1101         /* Allocate memory for storing MAC addresses */
1102         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1103                         hw->mac.num_rar_entries, 0);
1104         if (eth_dev->data->mac_addrs == NULL) {
1105                 PMD_INIT_LOG(ERR,
1106                         "Failed to allocate %u bytes needed to store "
1107                         "MAC addresses",
1108                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1109                 return -ENOMEM;
1110         }
1111         /* Copy the permanent MAC address */
1112         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1113                         &eth_dev->data->mac_addrs[0]);
1114
1115         /* Allocate memory for storing hash filter MAC addresses */
1116         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1117                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1118         if (eth_dev->data->hash_mac_addrs == NULL) {
1119                 PMD_INIT_LOG(ERR,
1120                         "Failed to allocate %d bytes needed to store MAC addresses",
1121                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1122                 return -ENOMEM;
1123         }
1124
1125         /* initialize the vfta */
1126         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1127
1128         /* initialize the hw strip bitmap*/
1129         memset(hwstrip, 0, sizeof(*hwstrip));
1130
1131         /* initialize PF if max_vfs not zero */
1132         ixgbe_pf_host_init(eth_dev);
1133
1134         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1135         /* let hardware know driver is loaded */
1136         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1137         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1138         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1139         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1140         IXGBE_WRITE_FLUSH(hw);
1141
1142         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1143                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1144                              (int) hw->mac.type, (int) hw->phy.type,
1145                              (int) hw->phy.sfp_type);
1146         else
1147                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1148                              (int) hw->mac.type, (int) hw->phy.type);
1149
1150         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1151                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1152                         pci_dev->id.device_id);
1153
1154         rte_intr_callback_register(&pci_dev->intr_handle,
1155                                    ixgbe_dev_interrupt_handler,
1156                                    (void *)eth_dev);
1157
1158         /* enable uio/vfio intr/eventfd mapping */
1159         rte_intr_enable(&pci_dev->intr_handle);
1160
1161         /* enable support intr */
1162         ixgbe_enable_intr(eth_dev);
1163
1164         /* initialize 5tuple filter list */
1165         TAILQ_INIT(&filter_info->fivetuple_list);
1166         memset(filter_info->fivetuple_mask, 0,
1167                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1168
1169         return 0;
1170 }
1171
1172 static int
1173 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1174 {
1175         struct rte_pci_device *pci_dev;
1176         struct ixgbe_hw *hw;
1177
1178         PMD_INIT_FUNC_TRACE();
1179
1180         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1181                 return -EPERM;
1182
1183         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1184         pci_dev = eth_dev->pci_dev;
1185
1186         if (hw->adapter_stopped == 0)
1187                 ixgbe_dev_close(eth_dev);
1188
1189         eth_dev->dev_ops = NULL;
1190         eth_dev->rx_pkt_burst = NULL;
1191         eth_dev->tx_pkt_burst = NULL;
1192
1193         /* Unlock any pending hardware semaphore */
1194         ixgbe_swfw_lock_reset(hw);
1195
1196         /* disable uio intr before callback unregister */
1197         rte_intr_disable(&(pci_dev->intr_handle));
1198         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1199                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1200
1201         /* uninitialize PF if max_vfs not zero */
1202         ixgbe_pf_host_uninit(eth_dev);
1203
1204         rte_free(eth_dev->data->mac_addrs);
1205         eth_dev->data->mac_addrs = NULL;
1206
1207         rte_free(eth_dev->data->hash_mac_addrs);
1208         eth_dev->data->hash_mac_addrs = NULL;
1209
1210         return 0;
1211 }
1212
1213 /*
1214  * Negotiate mailbox API version with the PF.
1215  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1216  * Then we try to negotiate starting with the most recent one.
1217  * If all negotiation attempts fail, then we will proceed with
1218  * the default one (ixgbe_mbox_api_10).
1219  */
1220 static void
1221 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1222 {
1223         int32_t i;
1224
1225         /* start with highest supported, proceed down */
1226         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1227                 ixgbe_mbox_api_11,
1228                 ixgbe_mbox_api_10,
1229         };
1230
1231         for (i = 0;
1232                         i != RTE_DIM(sup_ver) &&
1233                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1234                         i++)
1235                 ;
1236 }
1237
1238 static void
1239 generate_random_mac_addr(struct ether_addr *mac_addr)
1240 {
1241         uint64_t random;
1242
1243         /* Set Organizationally Unique Identifier (OUI) prefix. */
1244         mac_addr->addr_bytes[0] = 0x00;
1245         mac_addr->addr_bytes[1] = 0x09;
1246         mac_addr->addr_bytes[2] = 0xC0;
1247         /* Force indication of locally assigned MAC address. */
1248         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1249         /* Generate the last 3 bytes of the MAC address with a random number. */
1250         random = rte_rand();
1251         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1252 }
1253
1254 /*
1255  * Virtual Function device init
1256  */
1257 static int
1258 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1259 {
1260         int diag;
1261         uint32_t tc, tcs;
1262         struct rte_pci_device *pci_dev;
1263         struct ixgbe_hw *hw =
1264                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1265         struct ixgbe_vfta * shadow_vfta =
1266                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1267         struct ixgbe_hwstrip *hwstrip =
1268                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1269         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1270
1271         PMD_INIT_FUNC_TRACE();
1272
1273         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1274         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1275         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1276
1277         /* for secondary processes, we don't initialise any further as primary
1278          * has already done this work. Only check we don't need a different
1279          * RX function */
1280         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1281                 if (eth_dev->data->scattered_rx)
1282                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1283                 return 0;
1284         }
1285
1286         pci_dev = eth_dev->pci_dev;
1287
1288         rte_eth_copy_pci_info(eth_dev, pci_dev);
1289
1290         hw->device_id = pci_dev->id.device_id;
1291         hw->vendor_id = pci_dev->id.vendor_id;
1292         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1293
1294         /* initialize the vfta */
1295         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1296
1297         /* initialize the hw strip bitmap*/
1298         memset(hwstrip, 0, sizeof(*hwstrip));
1299
1300         /* Initialize the shared code (base driver) */
1301         diag = ixgbe_init_shared_code(hw);
1302         if (diag != IXGBE_SUCCESS) {
1303                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1304                 return -EIO;
1305         }
1306
1307         /* init_mailbox_params */
1308         hw->mbx.ops.init_params(hw);
1309
1310         /* Reset the hw statistics */
1311         ixgbevf_dev_stats_reset(eth_dev);
1312
1313         /* Disable the interrupts for VF */
1314         ixgbevf_intr_disable(hw);
1315
1316         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1317         diag = hw->mac.ops.reset_hw(hw);
1318
1319         /*
1320          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1321          * the underlying PF driver has not assigned a MAC address to the VF.
1322          * In this case, assign a random MAC address.
1323          */
1324         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1325                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1326                 return (diag);
1327         }
1328
1329         /* negotiate mailbox API version to use with the PF. */
1330         ixgbevf_negotiate_api(hw);
1331
1332         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1333         ixgbevf_get_queues(hw, &tcs, &tc);
1334
1335         /* Allocate memory for storing MAC addresses */
1336         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1337                         hw->mac.num_rar_entries, 0);
1338         if (eth_dev->data->mac_addrs == NULL) {
1339                 PMD_INIT_LOG(ERR,
1340                         "Failed to allocate %u bytes needed to store "
1341                         "MAC addresses",
1342                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1343                 return -ENOMEM;
1344         }
1345
1346         /* Generate a random MAC address, if none was assigned by PF. */
1347         if (is_zero_ether_addr(perm_addr)) {
1348                 generate_random_mac_addr(perm_addr);
1349                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1350                 if (diag) {
1351                         rte_free(eth_dev->data->mac_addrs);
1352                         eth_dev->data->mac_addrs = NULL;
1353                         return diag;
1354                 }
1355                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1356                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1357                              "%02x:%02x:%02x:%02x:%02x:%02x",
1358                              perm_addr->addr_bytes[0],
1359                              perm_addr->addr_bytes[1],
1360                              perm_addr->addr_bytes[2],
1361                              perm_addr->addr_bytes[3],
1362                              perm_addr->addr_bytes[4],
1363                              perm_addr->addr_bytes[5]);
1364         }
1365
1366         /* Copy the permanent MAC address */
1367         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1368
1369         /* reset the hardware with the new settings */
1370         diag = hw->mac.ops.start_hw(hw);
1371         switch (diag) {
1372                 case  0:
1373                         break;
1374
1375                 default:
1376                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1377                         return (-EIO);
1378         }
1379
1380         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1381                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1382                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1383
1384         return 0;
1385 }
1386
1387 /* Virtual Function device uninit */
1388
1389 static int
1390 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1391 {
1392         struct ixgbe_hw *hw;
1393         unsigned i;
1394
1395         PMD_INIT_FUNC_TRACE();
1396
1397         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1398                 return -EPERM;
1399
1400         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1401
1402         if (hw->adapter_stopped == 0)
1403                 ixgbevf_dev_close(eth_dev);
1404
1405         eth_dev->dev_ops = NULL;
1406         eth_dev->rx_pkt_burst = NULL;
1407         eth_dev->tx_pkt_burst = NULL;
1408
1409         /* Disable the interrupts for VF */
1410         ixgbevf_intr_disable(hw);
1411
1412         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1413                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1414                 eth_dev->data->rx_queues[i] = NULL;
1415         }
1416         eth_dev->data->nb_rx_queues = 0;
1417
1418         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1419                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1420                 eth_dev->data->tx_queues[i] = NULL;
1421         }
1422         eth_dev->data->nb_tx_queues = 0;
1423
1424         rte_free(eth_dev->data->mac_addrs);
1425         eth_dev->data->mac_addrs = NULL;
1426
1427         return 0;
1428 }
1429
1430 static struct eth_driver rte_ixgbe_pmd = {
1431         .pci_drv = {
1432                 .name = "rte_ixgbe_pmd",
1433                 .id_table = pci_id_ixgbe_map,
1434                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1435                         RTE_PCI_DRV_DETACHABLE,
1436         },
1437         .eth_dev_init = eth_ixgbe_dev_init,
1438         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1439         .dev_private_size = sizeof(struct ixgbe_adapter),
1440 };
1441
1442 /*
1443  * virtual function driver struct
1444  */
1445 static struct eth_driver rte_ixgbevf_pmd = {
1446         .pci_drv = {
1447                 .name = "rte_ixgbevf_pmd",
1448                 .id_table = pci_id_ixgbevf_map,
1449                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1450         },
1451         .eth_dev_init = eth_ixgbevf_dev_init,
1452         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1453         .dev_private_size = sizeof(struct ixgbe_adapter),
1454 };
1455
1456 /*
1457  * Driver initialization routine.
1458  * Invoked once at EAL init time.
1459  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1460  */
1461 static int
1462 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1463 {
1464         PMD_INIT_FUNC_TRACE();
1465
1466         rte_eth_driver_register(&rte_ixgbe_pmd);
1467         return 0;
1468 }
1469
1470 /*
1471  * VF Driver initialization routine.
1472  * Invoked one at EAL init time.
1473  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1474  */
1475 static int
1476 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1477 {
1478         PMD_INIT_FUNC_TRACE();
1479
1480         rte_eth_driver_register(&rte_ixgbevf_pmd);
1481         return (0);
1482 }
1483
1484 static int
1485 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1486 {
1487         struct ixgbe_hw *hw =
1488                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489         struct ixgbe_vfta * shadow_vfta =
1490                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1491         uint32_t vfta;
1492         uint32_t vid_idx;
1493         uint32_t vid_bit;
1494
1495         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1496         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1497         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1498         if (on)
1499                 vfta |= vid_bit;
1500         else
1501                 vfta &= ~vid_bit;
1502         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1503
1504         /* update local VFTA copy */
1505         shadow_vfta->vfta[vid_idx] = vfta;
1506
1507         return 0;
1508 }
1509
1510 static void
1511 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1512 {
1513         if (on)
1514                 ixgbe_vlan_hw_strip_enable(dev, queue);
1515         else
1516                 ixgbe_vlan_hw_strip_disable(dev, queue);
1517 }
1518
1519 static void
1520 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1521 {
1522         struct ixgbe_hw *hw =
1523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524
1525         /* Only the high 16-bits is valid */
1526         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1527 }
1528
1529 void
1530 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1531 {
1532         struct ixgbe_hw *hw =
1533                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1534         uint32_t vlnctrl;
1535
1536         PMD_INIT_FUNC_TRACE();
1537
1538         /* Filter Table Disable */
1539         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1540         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1541
1542         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1543 }
1544
1545 void
1546 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1547 {
1548         struct ixgbe_hw *hw =
1549                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550         struct ixgbe_vfta * shadow_vfta =
1551                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1552         uint32_t vlnctrl;
1553         uint16_t i;
1554
1555         PMD_INIT_FUNC_TRACE();
1556
1557         /* Filter Table Enable */
1558         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1559         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1560         vlnctrl |= IXGBE_VLNCTRL_VFE;
1561
1562         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1563
1564         /* write whatever is in local vfta copy */
1565         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1566                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1567 }
1568
1569 static void
1570 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1571 {
1572         struct ixgbe_hwstrip *hwstrip =
1573                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1574
1575         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1576                 return;
1577
1578         if (on)
1579                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1580         else
1581                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1582 }
1583
1584 static void
1585 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1586 {
1587         struct ixgbe_hw *hw =
1588                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1589         uint32_t ctrl;
1590
1591         PMD_INIT_FUNC_TRACE();
1592
1593         if (hw->mac.type == ixgbe_mac_82598EB) {
1594                 /* No queue level support */
1595                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1596                 return;
1597         }
1598         else {
1599                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1600                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1601                 ctrl &= ~IXGBE_RXDCTL_VME;
1602                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1603         }
1604         /* record those setting for HW strip per queue */
1605         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1606 }
1607
1608 static void
1609 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1610 {
1611         struct ixgbe_hw *hw =
1612                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613         uint32_t ctrl;
1614
1615         PMD_INIT_FUNC_TRACE();
1616
1617         if (hw->mac.type == ixgbe_mac_82598EB) {
1618                 /* No queue level supported */
1619                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1620                 return;
1621         }
1622         else {
1623                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1624                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1625                 ctrl |= IXGBE_RXDCTL_VME;
1626                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1627         }
1628         /* record those setting for HW strip per queue */
1629         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1630 }
1631
1632 void
1633 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1634 {
1635         struct ixgbe_hw *hw =
1636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         uint32_t ctrl;
1638         uint16_t i;
1639
1640         PMD_INIT_FUNC_TRACE();
1641
1642         if (hw->mac.type == ixgbe_mac_82598EB) {
1643                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1644                 ctrl &= ~IXGBE_VLNCTRL_VME;
1645                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1646         }
1647         else {
1648                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1649                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1650                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1651                         ctrl &= ~IXGBE_RXDCTL_VME;
1652                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1653
1654                         /* record those setting for HW strip per queue */
1655                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1656                 }
1657         }
1658 }
1659
1660 void
1661 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1662 {
1663         struct ixgbe_hw *hw =
1664                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665         uint32_t ctrl;
1666         uint16_t i;
1667
1668         PMD_INIT_FUNC_TRACE();
1669
1670         if (hw->mac.type == ixgbe_mac_82598EB) {
1671                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1672                 ctrl |= IXGBE_VLNCTRL_VME;
1673                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1674         }
1675         else {
1676                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1677                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1678                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1679                         ctrl |= IXGBE_RXDCTL_VME;
1680                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1681
1682                         /* record those setting for HW strip per queue */
1683                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1684                 }
1685         }
1686 }
1687
1688 static void
1689 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1690 {
1691         struct ixgbe_hw *hw =
1692                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1693         uint32_t ctrl;
1694
1695         PMD_INIT_FUNC_TRACE();
1696
1697         /* DMATXCTRL: Geric Double VLAN Disable */
1698         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1699         ctrl &= ~IXGBE_DMATXCTL_GDV;
1700         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1701
1702         /* CTRL_EXT: Global Double VLAN Disable */
1703         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1704         ctrl &= ~IXGBE_EXTENDED_VLAN;
1705         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1706
1707 }
1708
1709 static void
1710 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1711 {
1712         struct ixgbe_hw *hw =
1713                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1714         uint32_t ctrl;
1715
1716         PMD_INIT_FUNC_TRACE();
1717
1718         /* DMATXCTRL: Geric Double VLAN Enable */
1719         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1720         ctrl |= IXGBE_DMATXCTL_GDV;
1721         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1722
1723         /* CTRL_EXT: Global Double VLAN Enable */
1724         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1725         ctrl |= IXGBE_EXTENDED_VLAN;
1726         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1727
1728         /*
1729          * VET EXT field in the EXVET register = 0x8100 by default
1730          * So no need to change. Same to VT field of DMATXCTL register
1731          */
1732 }
1733
1734 static void
1735 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1736 {
1737         if(mask & ETH_VLAN_STRIP_MASK){
1738                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1739                         ixgbe_vlan_hw_strip_enable_all(dev);
1740                 else
1741                         ixgbe_vlan_hw_strip_disable_all(dev);
1742         }
1743
1744         if(mask & ETH_VLAN_FILTER_MASK){
1745                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1746                         ixgbe_vlan_hw_filter_enable(dev);
1747                 else
1748                         ixgbe_vlan_hw_filter_disable(dev);
1749         }
1750
1751         if(mask & ETH_VLAN_EXTEND_MASK){
1752                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1753                         ixgbe_vlan_hw_extend_enable(dev);
1754                 else
1755                         ixgbe_vlan_hw_extend_disable(dev);
1756         }
1757 }
1758
1759 static void
1760 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1761 {
1762         struct ixgbe_hw *hw =
1763                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1765         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1766         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1767         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1768 }
1769
1770 static int
1771 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1772 {
1773         switch (nb_rx_q) {
1774         case 1:
1775         case 2:
1776                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1777                 break;
1778         case 4:
1779                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1780                 break;
1781         default:
1782                 return -EINVAL;
1783         }
1784
1785         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1786         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1787
1788         return 0;
1789 }
1790
1791 static int
1792 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1793 {
1794         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1795         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1796         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1797
1798         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1799                 /* check multi-queue mode */
1800                 switch (dev_conf->rxmode.mq_mode) {
1801                 case ETH_MQ_RX_VMDQ_DCB:
1802                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1803                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1804                         PMD_INIT_LOG(ERR, "SRIOV active,"
1805                                         " unsupported mq_mode rx %d.",
1806                                         dev_conf->rxmode.mq_mode);
1807                         return -EINVAL;
1808                 case ETH_MQ_RX_RSS:
1809                 case ETH_MQ_RX_VMDQ_RSS:
1810                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1811                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1812                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1813                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1814                                                 " invalid queue number"
1815                                                 " for VMDQ RSS, allowed"
1816                                                 " value are 1, 2 or 4.");
1817                                         return -EINVAL;
1818                                 }
1819                         break;
1820                 case ETH_MQ_RX_VMDQ_ONLY:
1821                 case ETH_MQ_RX_NONE:
1822                         /* if nothing mq mode configure, use default scheme */
1823                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1824                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1825                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1826                         break;
1827                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1828                         /* SRIOV only works in VMDq enable mode */
1829                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1830                                         " wrong mq_mode rx %d.",
1831                                         dev_conf->rxmode.mq_mode);
1832                         return -EINVAL;
1833                 }
1834
1835                 switch (dev_conf->txmode.mq_mode) {
1836                 case ETH_MQ_TX_VMDQ_DCB:
1837                         /* DCB VMDQ in SRIOV mode, not implement yet */
1838                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1839                                         " unsupported VMDQ mq_mode tx %d.",
1840                                         dev_conf->txmode.mq_mode);
1841                         return -EINVAL;
1842                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1843                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1844                         break;
1845                 }
1846
1847                 /* check valid queue number */
1848                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1849                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1850                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1851                                         " queue number must less equal to %d.",
1852                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1853                         return -EINVAL;
1854                 }
1855         } else {
1856                 /* check configuration for vmdb+dcb mode */
1857                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1858                         const struct rte_eth_vmdq_dcb_conf *conf;
1859
1860                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1861                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1862                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1863                                 return -EINVAL;
1864                         }
1865                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1866                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1867                                conf->nb_queue_pools == ETH_32_POOLS)) {
1868                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1869                                                 " nb_queue_pools must be %d or %d.",
1870                                                 ETH_16_POOLS, ETH_32_POOLS);
1871                                 return -EINVAL;
1872                         }
1873                 }
1874                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1875                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1876
1877                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1878                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1879                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1880                                 return -EINVAL;
1881                         }
1882                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1883                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1884                                conf->nb_queue_pools == ETH_32_POOLS)) {
1885                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1886                                                 " nb_queue_pools != %d and"
1887                                                 " nb_queue_pools != %d.",
1888                                                 ETH_16_POOLS, ETH_32_POOLS);
1889                                 return -EINVAL;
1890                         }
1891                 }
1892
1893                 /* For DCB mode check our configuration before we go further */
1894                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1895                         const struct rte_eth_dcb_rx_conf *conf;
1896
1897                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1898                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1899                                                  IXGBE_DCB_NB_QUEUES);
1900                                 return -EINVAL;
1901                         }
1902                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1903                         if (!(conf->nb_tcs == ETH_4_TCS ||
1904                                conf->nb_tcs == ETH_8_TCS)) {
1905                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1906                                                 " and nb_tcs != %d.",
1907                                                 ETH_4_TCS, ETH_8_TCS);
1908                                 return -EINVAL;
1909                         }
1910                 }
1911
1912                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1913                         const struct rte_eth_dcb_tx_conf *conf;
1914
1915                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1916                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1917                                                  IXGBE_DCB_NB_QUEUES);
1918                                 return -EINVAL;
1919                         }
1920                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1921                         if (!(conf->nb_tcs == ETH_4_TCS ||
1922                                conf->nb_tcs == ETH_8_TCS)) {
1923                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1924                                                 " and nb_tcs != %d.",
1925                                                 ETH_4_TCS, ETH_8_TCS);
1926                                 return -EINVAL;
1927                         }
1928                 }
1929         }
1930         return 0;
1931 }
1932
1933 static int
1934 ixgbe_dev_configure(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_interrupt *intr =
1937                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1938         struct ixgbe_adapter *adapter =
1939                 (struct ixgbe_adapter *)dev->data->dev_private;
1940         int ret;
1941
1942         PMD_INIT_FUNC_TRACE();
1943         /* multipe queue mode checking */
1944         ret  = ixgbe_check_mq_mode(dev);
1945         if (ret != 0) {
1946                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1947                             ret);
1948                 return ret;
1949         }
1950
1951         /* set flag to update link status after init */
1952         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1953
1954         /*
1955          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1956          * allocation or vector Rx preconditions we will reset it.
1957          */
1958         adapter->rx_bulk_alloc_allowed = true;
1959         adapter->rx_vec_allowed = true;
1960
1961         return 0;
1962 }
1963
1964 /*
1965  * Configure device link speed and setup link.
1966  * It returns 0 on success.
1967  */
1968 static int
1969 ixgbe_dev_start(struct rte_eth_dev *dev)
1970 {
1971         struct ixgbe_hw *hw =
1972                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973         struct ixgbe_vf_info *vfinfo =
1974                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1975         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1976         uint32_t intr_vector = 0;
1977         int err, link_up = 0, negotiate = 0;
1978         uint32_t speed = 0;
1979         int mask = 0;
1980         int status;
1981         uint16_t vf, idx;
1982
1983         PMD_INIT_FUNC_TRACE();
1984
1985         /* IXGBE devices don't support half duplex */
1986         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1987                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1988                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1989                              dev->data->dev_conf.link_duplex,
1990                              dev->data->port_id);
1991                 return -EINVAL;
1992         }
1993
1994         /* disable uio/vfio intr/eventfd mapping */
1995         rte_intr_disable(intr_handle);
1996
1997         /* stop adapter */
1998         hw->adapter_stopped = 0;
1999         ixgbe_stop_adapter(hw);
2000
2001         /* reinitialize adapter
2002          * this calls reset and start */
2003         status = ixgbe_pf_reset_hw(hw);
2004         if (status != 0)
2005                 return -1;
2006         hw->mac.ops.start_hw(hw);
2007         hw->mac.get_link_status = true;
2008
2009         /* configure PF module if SRIOV enabled */
2010         ixgbe_pf_host_configure(dev);
2011
2012         /* check and configure queue intr-vector mapping */
2013         if ((rte_intr_cap_multiple(intr_handle) ||
2014              !RTE_ETH_DEV_SRIOV(dev).active) &&
2015             dev->data->dev_conf.intr_conf.rxq != 0) {
2016                 intr_vector = dev->data->nb_rx_queues;
2017                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2018                         return -1;
2019         }
2020
2021         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2022                 intr_handle->intr_vec =
2023                         rte_zmalloc("intr_vec",
2024                                     dev->data->nb_rx_queues * sizeof(int), 0);
2025                 if (intr_handle->intr_vec == NULL) {
2026                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2027                                      " intr_vec\n", dev->data->nb_rx_queues);
2028                         return -ENOMEM;
2029                 }
2030         }
2031
2032         /* confiugre msix for sleep until rx interrupt */
2033         ixgbe_configure_msix(dev);
2034
2035         /* initialize transmission unit */
2036         ixgbe_dev_tx_init(dev);
2037
2038         /* This can fail when allocating mbufs for descriptor rings */
2039         err = ixgbe_dev_rx_init(dev);
2040         if (err) {
2041                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2042                 goto error;
2043         }
2044
2045         err = ixgbe_dev_rxtx_start(dev);
2046         if (err < 0) {
2047                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2048                 goto error;
2049         }
2050
2051         /* Skip link setup if loopback mode is enabled for 82599. */
2052         if (hw->mac.type == ixgbe_mac_82599EB &&
2053                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2054                 goto skip_link_setup;
2055
2056         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2057                 err = hw->mac.ops.setup_sfp(hw);
2058                 if (err)
2059                         goto error;
2060         }
2061
2062         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2063                 /* Turn on the copper */
2064                 ixgbe_set_phy_power(hw, true);
2065         } else {
2066                 /* Turn on the laser */
2067                 ixgbe_enable_tx_laser(hw);
2068         }
2069
2070         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2071         if (err)
2072                 goto error;
2073         dev->data->dev_link.link_status = link_up;
2074
2075         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2076         if (err)
2077                 goto error;
2078
2079         switch(dev->data->dev_conf.link_speed) {
2080         case ETH_LINK_SPEED_AUTONEG:
2081                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2082                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2083                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2084                 break;
2085         case ETH_LINK_SPEED_100:
2086                 /*
2087                  * Invalid for 82598 but error will be detected by
2088                  * ixgbe_setup_link()
2089                  */
2090                 speed = IXGBE_LINK_SPEED_100_FULL;
2091                 break;
2092         case ETH_LINK_SPEED_1000:
2093                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2094                 break;
2095         case ETH_LINK_SPEED_10000:
2096                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2097                 break;
2098         default:
2099                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2100                              dev->data->dev_conf.link_speed,
2101                              dev->data->port_id);
2102                 goto error;
2103         }
2104
2105         err = ixgbe_setup_link(hw, speed, link_up);
2106         if (err)
2107                 goto error;
2108
2109 skip_link_setup:
2110
2111         if (rte_intr_allow_others(intr_handle)) {
2112                 /* check if lsc interrupt is enabled */
2113                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2114                         ixgbe_dev_lsc_interrupt_setup(dev);
2115         } else {
2116                 rte_intr_callback_unregister(intr_handle,
2117                                              ixgbe_dev_interrupt_handler,
2118                                              (void *)dev);
2119                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2120                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2121                                      " no intr multiplex\n");
2122         }
2123
2124         /* check if rxq interrupt is enabled */
2125         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2126             rte_intr_dp_is_en(intr_handle))
2127                 ixgbe_dev_rxq_interrupt_setup(dev);
2128
2129         /* enable uio/vfio intr/eventfd mapping */
2130         rte_intr_enable(intr_handle);
2131
2132         /* resume enabled intr since hw reset */
2133         ixgbe_enable_intr(dev);
2134
2135         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2136                 ETH_VLAN_EXTEND_MASK;
2137         ixgbe_vlan_offload_set(dev, mask);
2138
2139         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2140                 /* Enable vlan filtering for VMDq */
2141                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2142         }
2143
2144         /* Configure DCB hw */
2145         ixgbe_configure_dcb(dev);
2146
2147         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2148                 err = ixgbe_fdir_configure(dev);
2149                 if (err)
2150                         goto error;
2151         }
2152
2153         /* Restore vf rate limit */
2154         if (vfinfo != NULL) {
2155                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2156                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2157                                 if (vfinfo[vf].tx_rate[idx] != 0)
2158                                         ixgbe_set_vf_rate_limit(dev, vf,
2159                                                 vfinfo[vf].tx_rate[idx],
2160                                                 1 << idx);
2161         }
2162
2163         ixgbe_restore_statistics_mapping(dev);
2164
2165         return (0);
2166
2167 error:
2168         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2169         ixgbe_dev_clear_queues(dev);
2170         return -EIO;
2171 }
2172
2173 /*
2174  * Stop device: disable rx and tx functions to allow for reconfiguring.
2175  */
2176 static void
2177 ixgbe_dev_stop(struct rte_eth_dev *dev)
2178 {
2179         struct rte_eth_link link;
2180         struct ixgbe_hw *hw =
2181                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182         struct ixgbe_vf_info *vfinfo =
2183                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2184         struct ixgbe_filter_info *filter_info =
2185                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2186         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2187         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2188         int vf;
2189
2190         PMD_INIT_FUNC_TRACE();
2191
2192         /* disable interrupts */
2193         ixgbe_disable_intr(hw);
2194
2195         /* disable intr eventfd mapping */
2196         rte_intr_disable(intr_handle);
2197
2198         /* reset the NIC */
2199         ixgbe_pf_reset_hw(hw);
2200         hw->adapter_stopped = 0;
2201
2202         /* stop adapter */
2203         ixgbe_stop_adapter(hw);
2204
2205         for (vf = 0; vfinfo != NULL &&
2206                      vf < dev->pci_dev->max_vfs; vf++)
2207                 vfinfo[vf].clear_to_send = false;
2208
2209         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2210                 /* Turn off the copper */
2211                 ixgbe_set_phy_power(hw, false);
2212         } else {
2213                 /* Turn off the laser */
2214                 ixgbe_disable_tx_laser(hw);
2215         }
2216
2217         ixgbe_dev_clear_queues(dev);
2218
2219         /* Clear stored conf */
2220         dev->data->scattered_rx = 0;
2221         dev->data->lro = 0;
2222
2223         /* Clear recorded link status */
2224         memset(&link, 0, sizeof(link));
2225         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2226
2227         /* Remove all ntuple filters of the device */
2228         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2229              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2230                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2231                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2232                              p_5tuple, entries);
2233                 rte_free(p_5tuple);
2234         }
2235         memset(filter_info->fivetuple_mask, 0,
2236                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2237
2238         if (!rte_intr_allow_others(intr_handle))
2239                 /* resume to the default handler */
2240                 rte_intr_callback_register(intr_handle,
2241                                            ixgbe_dev_interrupt_handler,
2242                                            (void *)dev);
2243
2244         /* Clean datapath event and queue/vec mapping */
2245         rte_intr_efd_disable(intr_handle);
2246         if (intr_handle->intr_vec != NULL) {
2247                 rte_free(intr_handle->intr_vec);
2248                 intr_handle->intr_vec = NULL;
2249         }
2250 }
2251
2252 /*
2253  * Set device link up: enable tx.
2254  */
2255 static int
2256 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2257 {
2258         struct ixgbe_hw *hw =
2259                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2260         if (hw->mac.type == ixgbe_mac_82599EB) {
2261 #ifdef RTE_NIC_BYPASS
2262                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2263                         /* Not suported in bypass mode */
2264                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2265                                      "by device id 0x%x", hw->device_id);
2266                         return -ENOTSUP;
2267                 }
2268 #endif
2269         }
2270
2271         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2272                 /* Turn on the copper */
2273                 ixgbe_set_phy_power(hw, true);
2274         } else {
2275                 /* Turn on the laser */
2276                 ixgbe_enable_tx_laser(hw);
2277         }
2278
2279         return 0;
2280 }
2281
2282 /*
2283  * Set device link down: disable tx.
2284  */
2285 static int
2286 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2287 {
2288         struct ixgbe_hw *hw =
2289                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2290         if (hw->mac.type == ixgbe_mac_82599EB) {
2291 #ifdef RTE_NIC_BYPASS
2292                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2293                         /* Not suported in bypass mode */
2294                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2295                                      "by device id 0x%x", hw->device_id);
2296                         return -ENOTSUP;
2297                 }
2298 #endif
2299         }
2300
2301         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2302                 /* Turn off the copper */
2303                 ixgbe_set_phy_power(hw, false);
2304         } else {
2305                 /* Turn off the laser */
2306                 ixgbe_disable_tx_laser(hw);
2307         }
2308
2309         return 0;
2310 }
2311
2312 /*
2313  * Reest and stop device.
2314  */
2315 static void
2316 ixgbe_dev_close(struct rte_eth_dev *dev)
2317 {
2318         struct ixgbe_hw *hw =
2319                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320
2321         PMD_INIT_FUNC_TRACE();
2322
2323         ixgbe_pf_reset_hw(hw);
2324
2325         ixgbe_dev_stop(dev);
2326         hw->adapter_stopped = 1;
2327
2328         ixgbe_dev_free_queues(dev);
2329
2330         ixgbe_disable_pcie_master(hw);
2331
2332         /* reprogram the RAR[0] in case user changed it. */
2333         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2334 }
2335
2336 static void
2337 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2338                            struct ixgbe_hw_stats *hw_stats,
2339                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2340                            uint64_t *total_qprc, uint64_t *total_qprdc)
2341 {
2342         uint32_t bprc, lxon, lxoff, total;
2343         uint32_t delta_gprc = 0;
2344         unsigned i;
2345         /* Workaround for RX byte count not including CRC bytes when CRC
2346 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2347          * is disabled.
2348 +        */
2349         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2350                         IXGBE_HLREG0_RXCRCSTRP);
2351
2352         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2353         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2354         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2355         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2356
2357         for (i = 0; i < 8; i++) {
2358                 uint32_t mp;
2359                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2360                 /* global total per queue */
2361                 hw_stats->mpc[i] += mp;
2362                 /* Running comprehensive total for stats display */
2363                 *total_missed_rx += hw_stats->mpc[i];
2364                 if (hw->mac.type == ixgbe_mac_82598EB) {
2365                         hw_stats->rnbc[i] +=
2366                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2367                         hw_stats->pxonrxc[i] +=
2368                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2369                         hw_stats->pxoffrxc[i] +=
2370                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2371                 } else {
2372                         hw_stats->pxonrxc[i] +=
2373                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2374                         hw_stats->pxoffrxc[i] +=
2375                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2376                         hw_stats->pxon2offc[i] +=
2377                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2378                 }
2379                 hw_stats->pxontxc[i] +=
2380                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2381                 hw_stats->pxofftxc[i] +=
2382                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2383         }
2384         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2385                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2386                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2387                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2388
2389                 delta_gprc += delta_qprc;
2390
2391                 hw_stats->qprc[i] += delta_qprc;
2392                 hw_stats->qptc[i] += delta_qptc;
2393
2394                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2395                 hw_stats->qbrc[i] +=
2396                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2397                 if (crc_strip == 0)
2398                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2399
2400                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2401                 hw_stats->qbtc[i] +=
2402                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2403
2404                 hw_stats->qprdc[i] += delta_qprdc;
2405                 *total_qprdc += hw_stats->qprdc[i];
2406
2407                 *total_qprc += hw_stats->qprc[i];
2408                 *total_qbrc += hw_stats->qbrc[i];
2409         }
2410         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2411         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2412         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2413
2414         /*
2415          * An errata states that gprc actually counts good + missed packets:
2416          * Workaround to set gprc to summated queue packet receives
2417          */
2418         hw_stats->gprc = *total_qprc;
2419
2420         if (hw->mac.type != ixgbe_mac_82598EB) {
2421                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2422                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2423                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2424                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2425                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2426                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2427                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2428                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2429         } else {
2430                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2431                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2432                 /* 82598 only has a counter in the high register */
2433                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2434                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2435                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2436         }
2437         uint64_t old_tpr = hw_stats->tpr;
2438
2439         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2440         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2441
2442         if (crc_strip == 0)
2443                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2444
2445         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2446         hw_stats->gptc += delta_gptc;
2447         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2448         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2449
2450         /*
2451          * Workaround: mprc hardware is incorrectly counting
2452          * broadcasts, so for now we subtract those.
2453          */
2454         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2455         hw_stats->bprc += bprc;
2456         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2457         if (hw->mac.type == ixgbe_mac_82598EB)
2458                 hw_stats->mprc -= bprc;
2459
2460         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2461         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2462         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2463         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2464         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2465         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2466
2467         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2468         hw_stats->lxontxc += lxon;
2469         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2470         hw_stats->lxofftxc += lxoff;
2471         total = lxon + lxoff;
2472
2473         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2474         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2475         hw_stats->gptc -= total;
2476         hw_stats->mptc -= total;
2477         hw_stats->ptc64 -= total;
2478         hw_stats->gotc -= total * ETHER_MIN_LEN;
2479
2480         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2481         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2482         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2483         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2484         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2485         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2486         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2487         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2488         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2489         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2490         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2491         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2492         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2493         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2494         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2495         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2496         /* Only read FCOE on 82599 */
2497         if (hw->mac.type != ixgbe_mac_82598EB) {
2498                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2499                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2500                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2501                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2502                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2503         }
2504
2505         /* Flow Director Stats registers */
2506         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2507         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2508 }
2509
2510 /*
2511  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2512  */
2513 static void
2514 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2515 {
2516         struct ixgbe_hw *hw =
2517                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518         struct ixgbe_hw_stats *hw_stats =
2519                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2520         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2521         unsigned i;
2522
2523         total_missed_rx = 0;
2524         total_qbrc = 0;
2525         total_qprc = 0;
2526         total_qprdc = 0;
2527
2528         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2529                         &total_qprc, &total_qprdc);
2530
2531         if (stats == NULL)
2532                 return;
2533
2534         /* Fill out the rte_eth_stats statistics structure */
2535         stats->ipackets = total_qprc;
2536         stats->ibytes = total_qbrc;
2537         stats->opackets = hw_stats->gptc;
2538         stats->obytes = hw_stats->gotc;
2539
2540         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2541                 stats->q_ipackets[i] = hw_stats->qprc[i];
2542                 stats->q_opackets[i] = hw_stats->qptc[i];
2543                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2544                 stats->q_obytes[i] = hw_stats->qbtc[i];
2545                 stats->q_errors[i] = hw_stats->qprdc[i];
2546         }
2547
2548         /* Rx Errors */
2549         stats->ierrors  = hw_stats->crcerrs +
2550                           hw_stats->mspdc +
2551                           hw_stats->rlec +
2552                           hw_stats->ruc +
2553                           hw_stats->roc +
2554                           total_missed_rx +
2555                           hw_stats->illerrc +
2556                           hw_stats->errbc +
2557                           hw_stats->rfc +
2558                           hw_stats->fccrc +
2559                           hw_stats->fclast;
2560
2561         /* Tx Errors */
2562         stats->oerrors  = 0;
2563 }
2564
2565 static void
2566 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2567 {
2568         struct ixgbe_hw_stats *stats =
2569                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2570
2571         /* HW registers are cleared on read */
2572         ixgbe_dev_stats_get(dev, NULL);
2573
2574         /* Reset software totals */
2575         memset(stats, 0, sizeof(*stats));
2576 }
2577
2578 /* This function calculates the number of xstats based on the current config */
2579 static unsigned
2580 ixgbe_xstats_calc_num(void) {
2581         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2582                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2583 }
2584
2585 static int
2586 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2587                                          unsigned n)
2588 {
2589         struct ixgbe_hw *hw =
2590                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591         struct ixgbe_hw_stats *hw_stats =
2592                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2593         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2594         unsigned i, stat, count = 0;
2595
2596         count = ixgbe_xstats_calc_num();
2597
2598         if (n < count)
2599                 return count;
2600
2601         total_missed_rx = 0;
2602         total_qbrc = 0;
2603         total_qprc = 0;
2604         total_qprdc = 0;
2605
2606         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2607                                    &total_qprc, &total_qprdc);
2608
2609         /* If this is a reset xstats is NULL, and we have cleared the
2610          * registers by reading them.
2611          */
2612         if (!xstats)
2613                 return 0;
2614
2615         /* Extended stats from ixgbe_hw_stats */
2616         count = 0;
2617         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2618                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2619                          rte_ixgbe_stats_strings[i].name);
2620                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2621                                 rte_ixgbe_stats_strings[i].offset);
2622                 count++;
2623         }
2624
2625         /* RX Priority Stats */
2626         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2627                 for (i = 0; i < 8; i++) {
2628                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2629                                  "rx_priority%u_%s", i,
2630                                  rte_ixgbe_rxq_strings[stat].name);
2631                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2632                                         rte_ixgbe_rxq_strings[stat].offset +
2633                                         (sizeof(uint64_t) * i));
2634                         count++;
2635                 }
2636         }
2637
2638         /* TX Priority Stats */
2639         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2640                 for (i = 0; i < 8; i++) {
2641                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2642                                  "tx_priority%u_%s", i,
2643                                  rte_ixgbe_txq_strings[stat].name);
2644                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2645                                         rte_ixgbe_txq_strings[stat].offset +
2646                                         (sizeof(uint64_t) * i));
2647                         count++;
2648                 }
2649         }
2650
2651         return count;
2652 }
2653
2654 static void
2655 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2656 {
2657         struct ixgbe_hw_stats *stats =
2658                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2659
2660         unsigned count = ixgbe_xstats_calc_num();
2661
2662         /* HW registers are cleared on read */
2663         ixgbe_dev_xstats_get(dev, NULL, count);
2664
2665         /* Reset software totals */
2666         memset(stats, 0, sizeof(*stats));
2667 }
2668
2669 static void
2670 ixgbevf_update_stats(struct rte_eth_dev *dev)
2671 {
2672         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2673         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2674                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2675
2676         /* Good Rx packet, include VF loopback */
2677         UPDATE_VF_STAT(IXGBE_VFGPRC,
2678             hw_stats->last_vfgprc, hw_stats->vfgprc);
2679
2680         /* Good Rx octets, include VF loopback */
2681         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2682             hw_stats->last_vfgorc, hw_stats->vfgorc);
2683
2684         /* Good Tx packet, include VF loopback */
2685         UPDATE_VF_STAT(IXGBE_VFGPTC,
2686             hw_stats->last_vfgptc, hw_stats->vfgptc);
2687
2688         /* Good Tx octets, include VF loopback */
2689         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2690             hw_stats->last_vfgotc, hw_stats->vfgotc);
2691
2692         /* Rx Multicst Packet */
2693         UPDATE_VF_STAT(IXGBE_VFMPRC,
2694             hw_stats->last_vfmprc, hw_stats->vfmprc);
2695 }
2696
2697 static int
2698 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2699                        unsigned n)
2700 {
2701         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2702                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2703         unsigned i;
2704
2705         if (n < IXGBEVF_NB_XSTATS)
2706                 return IXGBEVF_NB_XSTATS;
2707
2708         ixgbevf_update_stats(dev);
2709
2710         if (!xstats)
2711                 return 0;
2712
2713         /* Extended stats */
2714         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2715                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2716                          "%s", rte_ixgbevf_stats_strings[i].name);
2717                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2718                         rte_ixgbevf_stats_strings[i].offset);
2719         }
2720
2721         return IXGBEVF_NB_XSTATS;
2722 }
2723
2724 static void
2725 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2726 {
2727         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2728                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2729
2730         ixgbevf_update_stats(dev);
2731
2732         if (stats == NULL)
2733                 return;
2734
2735         stats->ipackets = hw_stats->vfgprc;
2736         stats->ibytes = hw_stats->vfgorc;
2737         stats->opackets = hw_stats->vfgptc;
2738         stats->obytes = hw_stats->vfgotc;
2739         stats->imcasts = hw_stats->vfmprc;
2740         /* stats->imcasts should be removed as imcasts is deprecated */
2741 }
2742
2743 static void
2744 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2745 {
2746         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2747                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2748
2749         /* Sync HW register to the last stats */
2750         ixgbevf_dev_stats_get(dev, NULL);
2751
2752         /* reset HW current stats*/
2753         hw_stats->vfgprc = 0;
2754         hw_stats->vfgorc = 0;
2755         hw_stats->vfgptc = 0;
2756         hw_stats->vfgotc = 0;
2757         hw_stats->vfmprc = 0;
2758
2759 }
2760
2761 static void
2762 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2763 {
2764         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765
2766         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2767         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2768         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2769         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2770         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2771         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2772         dev_info->max_vfs = dev->pci_dev->max_vfs;
2773         if (hw->mac.type == ixgbe_mac_82598EB)
2774                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2775         else
2776                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2777         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2778         dev_info->rx_offload_capa =
2779                 DEV_RX_OFFLOAD_VLAN_STRIP |
2780                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2781                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2782                 DEV_RX_OFFLOAD_TCP_CKSUM;
2783
2784         /*
2785          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2786          * mode.
2787          */
2788         if ((hw->mac.type == ixgbe_mac_82599EB ||
2789              hw->mac.type == ixgbe_mac_X540) &&
2790             !RTE_ETH_DEV_SRIOV(dev).active)
2791                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2792
2793         dev_info->tx_offload_capa =
2794                 DEV_TX_OFFLOAD_VLAN_INSERT |
2795                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2796                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2797                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2798                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2799                 DEV_TX_OFFLOAD_TCP_TSO;
2800
2801         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2802                 .rx_thresh = {
2803                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2804                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2805                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2806                 },
2807                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2808                 .rx_drop_en = 0,
2809         };
2810
2811         dev_info->default_txconf = (struct rte_eth_txconf) {
2812                 .tx_thresh = {
2813                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2814                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2815                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2816                 },
2817                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2818                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2819                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2820                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2821         };
2822
2823         dev_info->rx_desc_lim = rx_desc_lim;
2824         dev_info->tx_desc_lim = tx_desc_lim;
2825
2826         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2827         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2828         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2829 }
2830
2831 static void
2832 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2833                      struct rte_eth_dev_info *dev_info)
2834 {
2835         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836
2837         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2838         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2839         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2840         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2841         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2842         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2843         dev_info->max_vfs = dev->pci_dev->max_vfs;
2844         if (hw->mac.type == ixgbe_mac_82598EB)
2845                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2846         else
2847                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2848         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2849                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2850                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2851                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2852         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2853                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2854                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2855                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2856                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2857                                 DEV_TX_OFFLOAD_TCP_TSO;
2858
2859         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2860                 .rx_thresh = {
2861                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2862                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2863                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2864                 },
2865                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2866                 .rx_drop_en = 0,
2867         };
2868
2869         dev_info->default_txconf = (struct rte_eth_txconf) {
2870                 .tx_thresh = {
2871                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2872                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2873                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2874                 },
2875                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2876                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2877                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2878                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2879         };
2880
2881         dev_info->rx_desc_lim = rx_desc_lim;
2882         dev_info->tx_desc_lim = tx_desc_lim;
2883 }
2884
2885 /* return 0 means link status changed, -1 means not changed */
2886 static int
2887 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2888 {
2889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890         struct rte_eth_link link, old;
2891         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2892         int link_up;
2893         int diag;
2894
2895         link.link_status = 0;
2896         link.link_speed = 0;
2897         link.link_duplex = 0;
2898         memset(&old, 0, sizeof(old));
2899         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2900
2901         hw->mac.get_link_status = true;
2902
2903         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2904         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2905                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2906         else
2907                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2908
2909         if (diag != 0) {
2910                 link.link_speed = ETH_LINK_SPEED_100;
2911                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2912                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2913                 if (link.link_status == old.link_status)
2914                         return -1;
2915                 return 0;
2916         }
2917
2918         if (link_up == 0) {
2919                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2920                 if (link.link_status == old.link_status)
2921                         return -1;
2922                 return 0;
2923         }
2924         link.link_status = 1;
2925         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2926
2927         switch (link_speed) {
2928         default:
2929         case IXGBE_LINK_SPEED_UNKNOWN:
2930                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2931                 link.link_speed = ETH_LINK_SPEED_100;
2932                 break;
2933
2934         case IXGBE_LINK_SPEED_100_FULL:
2935                 link.link_speed = ETH_LINK_SPEED_100;
2936                 break;
2937
2938         case IXGBE_LINK_SPEED_1GB_FULL:
2939                 link.link_speed = ETH_LINK_SPEED_1000;
2940                 break;
2941
2942         case IXGBE_LINK_SPEED_10GB_FULL:
2943                 link.link_speed = ETH_LINK_SPEED_10000;
2944                 break;
2945         }
2946         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2947
2948         if (link.link_status == old.link_status)
2949                 return -1;
2950
2951         return 0;
2952 }
2953
2954 static void
2955 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2956 {
2957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2958         uint32_t fctrl;
2959
2960         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2961         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2962         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2963 }
2964
2965 static void
2966 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2967 {
2968         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969         uint32_t fctrl;
2970
2971         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2972         fctrl &= (~IXGBE_FCTRL_UPE);
2973         if (dev->data->all_multicast == 1)
2974                 fctrl |= IXGBE_FCTRL_MPE;
2975         else
2976                 fctrl &= (~IXGBE_FCTRL_MPE);
2977         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2978 }
2979
2980 static void
2981 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2982 {
2983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984         uint32_t fctrl;
2985
2986         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2987         fctrl |= IXGBE_FCTRL_MPE;
2988         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2989 }
2990
2991 static void
2992 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2993 {
2994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2995         uint32_t fctrl;
2996
2997         if (dev->data->promiscuous == 1)
2998                 return; /* must remain in all_multicast mode */
2999
3000         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3001         fctrl &= (~IXGBE_FCTRL_MPE);
3002         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3003 }
3004
3005 /**
3006  * It clears the interrupt causes and enables the interrupt.
3007  * It will be called once only during nic initialized.
3008  *
3009  * @param dev
3010  *  Pointer to struct rte_eth_dev.
3011  *
3012  * @return
3013  *  - On success, zero.
3014  *  - On failure, a negative value.
3015  */
3016 static int
3017 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3018 {
3019         struct ixgbe_interrupt *intr =
3020                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3021
3022         ixgbe_dev_link_status_print(dev);
3023         intr->mask |= IXGBE_EICR_LSC;
3024
3025         return 0;
3026 }
3027
3028 /**
3029  * It clears the interrupt causes and enables the interrupt.
3030  * It will be called once only during nic initialized.
3031  *
3032  * @param dev
3033  *  Pointer to struct rte_eth_dev.
3034  *
3035  * @return
3036  *  - On success, zero.
3037  *  - On failure, a negative value.
3038  */
3039 static int
3040 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3041 {
3042         struct ixgbe_interrupt *intr =
3043                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3044
3045         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3046
3047         return 0;
3048 }
3049
3050 /*
3051  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3052  *
3053  * @param dev
3054  *  Pointer to struct rte_eth_dev.
3055  *
3056  * @return
3057  *  - On success, zero.
3058  *  - On failure, a negative value.
3059  */
3060 static int
3061 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3062 {
3063         uint32_t eicr;
3064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3065         struct ixgbe_interrupt *intr =
3066                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3067
3068         /* clear all cause mask */
3069         ixgbe_disable_intr(hw);
3070
3071         /* read-on-clear nic registers here */
3072         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3073         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3074
3075         intr->flags = 0;
3076
3077         /* set flag for async link update */
3078         if (eicr & IXGBE_EICR_LSC)
3079                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3080
3081         if (eicr & IXGBE_EICR_MAILBOX)
3082                 intr->flags |= IXGBE_FLAG_MAILBOX;
3083
3084         return 0;
3085 }
3086
3087 /**
3088  * It gets and then prints the link status.
3089  *
3090  * @param dev
3091  *  Pointer to struct rte_eth_dev.
3092  *
3093  * @return
3094  *  - On success, zero.
3095  *  - On failure, a negative value.
3096  */
3097 static void
3098 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3099 {
3100         struct rte_eth_link link;
3101
3102         memset(&link, 0, sizeof(link));
3103         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3104         if (link.link_status) {
3105                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3106                                         (int)(dev->data->port_id),
3107                                         (unsigned)link.link_speed,
3108                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3109                                         "full-duplex" : "half-duplex");
3110         } else {
3111                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3112                                 (int)(dev->data->port_id));
3113         }
3114         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3115                                 dev->pci_dev->addr.domain,
3116                                 dev->pci_dev->addr.bus,
3117                                 dev->pci_dev->addr.devid,
3118                                 dev->pci_dev->addr.function);
3119 }
3120
3121 /*
3122  * It executes link_update after knowing an interrupt occurred.
3123  *
3124  * @param dev
3125  *  Pointer to struct rte_eth_dev.
3126  *
3127  * @return
3128  *  - On success, zero.
3129  *  - On failure, a negative value.
3130  */
3131 static int
3132 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3133 {
3134         struct ixgbe_interrupt *intr =
3135                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3136         int64_t timeout;
3137         struct rte_eth_link link;
3138         int intr_enable_delay = false;
3139
3140         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3141
3142         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3143                 ixgbe_pf_mbx_process(dev);
3144                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3145         }
3146
3147         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3148                 /* get the link status before link update, for predicting later */
3149                 memset(&link, 0, sizeof(link));
3150                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3151
3152                 ixgbe_dev_link_update(dev, 0);
3153
3154                 /* likely to up */
3155                 if (!link.link_status)
3156                         /* handle it 1 sec later, wait it being stable */
3157                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3158                 /* likely to down */
3159                 else
3160                         /* handle it 4 sec later, wait it being stable */
3161                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3162
3163                 ixgbe_dev_link_status_print(dev);
3164
3165                 intr_enable_delay = true;
3166         }
3167
3168         if (intr_enable_delay) {
3169                 if (rte_eal_alarm_set(timeout * 1000,
3170                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3171                         PMD_DRV_LOG(ERR, "Error setting alarm");
3172         } else {
3173                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3174                 ixgbe_enable_intr(dev);
3175                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3176         }
3177
3178
3179         return 0;
3180 }
3181
3182 /**
3183  * Interrupt handler which shall be registered for alarm callback for delayed
3184  * handling specific interrupt to wait for the stable nic state. As the
3185  * NIC interrupt state is not stable for ixgbe after link is just down,
3186  * it needs to wait 4 seconds to get the stable status.
3187  *
3188  * @param handle
3189  *  Pointer to interrupt handle.
3190  * @param param
3191  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3192  *
3193  * @return
3194  *  void
3195  */
3196 static void
3197 ixgbe_dev_interrupt_delayed_handler(void *param)
3198 {
3199         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3200         struct ixgbe_interrupt *intr =
3201                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3202         struct ixgbe_hw *hw =
3203                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3204         uint32_t eicr;
3205
3206         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3207         if (eicr & IXGBE_EICR_MAILBOX)
3208                 ixgbe_pf_mbx_process(dev);
3209
3210         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3211                 ixgbe_dev_link_update(dev, 0);
3212                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3213                 ixgbe_dev_link_status_print(dev);
3214                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3215         }
3216
3217         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3218         ixgbe_enable_intr(dev);
3219         rte_intr_enable(&(dev->pci_dev->intr_handle));
3220 }
3221
3222 /**
3223  * Interrupt handler triggered by NIC  for handling
3224  * specific interrupt.
3225  *
3226  * @param handle
3227  *  Pointer to interrupt handle.
3228  * @param param
3229  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3230  *
3231  * @return
3232  *  void
3233  */
3234 static void
3235 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3236                             void *param)
3237 {
3238         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3239
3240         ixgbe_dev_interrupt_get_status(dev);
3241         ixgbe_dev_interrupt_action(dev);
3242 }
3243
3244 static int
3245 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3246 {
3247         struct ixgbe_hw *hw;
3248
3249         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3250         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3251 }
3252
3253 static int
3254 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3255 {
3256         struct ixgbe_hw *hw;
3257
3258         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3259         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3260 }
3261
3262 static int
3263 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3264 {
3265         struct ixgbe_hw *hw;
3266         uint32_t mflcn_reg;
3267         uint32_t fccfg_reg;
3268         int rx_pause;
3269         int tx_pause;
3270
3271         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3272
3273         fc_conf->pause_time = hw->fc.pause_time;
3274         fc_conf->high_water = hw->fc.high_water[0];
3275         fc_conf->low_water = hw->fc.low_water[0];
3276         fc_conf->send_xon = hw->fc.send_xon;
3277         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3278
3279         /*
3280          * Return rx_pause status according to actual setting of
3281          * MFLCN register.
3282          */
3283         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3284         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3285                 rx_pause = 1;
3286         else
3287                 rx_pause = 0;
3288
3289         /*
3290          * Return tx_pause status according to actual setting of
3291          * FCCFG register.
3292          */
3293         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3294         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3295                 tx_pause = 1;
3296         else
3297                 tx_pause = 0;
3298
3299         if (rx_pause && tx_pause)
3300                 fc_conf->mode = RTE_FC_FULL;
3301         else if (rx_pause)
3302                 fc_conf->mode = RTE_FC_RX_PAUSE;
3303         else if (tx_pause)
3304                 fc_conf->mode = RTE_FC_TX_PAUSE;
3305         else
3306                 fc_conf->mode = RTE_FC_NONE;
3307
3308         return 0;
3309 }
3310
3311 static int
3312 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3313 {
3314         struct ixgbe_hw *hw;
3315         int err;
3316         uint32_t rx_buf_size;
3317         uint32_t max_high_water;
3318         uint32_t mflcn;
3319         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3320                 ixgbe_fc_none,
3321                 ixgbe_fc_rx_pause,
3322                 ixgbe_fc_tx_pause,
3323                 ixgbe_fc_full
3324         };
3325
3326         PMD_INIT_FUNC_TRACE();
3327
3328         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3329         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3330         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3331
3332         /*
3333          * At least reserve one Ethernet frame for watermark
3334          * high_water/low_water in kilo bytes for ixgbe
3335          */
3336         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3337         if ((fc_conf->high_water > max_high_water) ||
3338                 (fc_conf->high_water < fc_conf->low_water)) {
3339                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3340                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3341                 return (-EINVAL);
3342         }
3343
3344         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3345         hw->fc.pause_time     = fc_conf->pause_time;
3346         hw->fc.high_water[0]  = fc_conf->high_water;
3347         hw->fc.low_water[0]   = fc_conf->low_water;
3348         hw->fc.send_xon       = fc_conf->send_xon;
3349         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3350
3351         err = ixgbe_fc_enable(hw);
3352
3353         /* Not negotiated is not an error case */
3354         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3355
3356                 /* check if we want to forward MAC frames - driver doesn't have native
3357                  * capability to do that, so we'll write the registers ourselves */
3358
3359                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3360
3361                 /* set or clear MFLCN.PMCF bit depending on configuration */
3362                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3363                         mflcn |= IXGBE_MFLCN_PMCF;
3364                 else
3365                         mflcn &= ~IXGBE_MFLCN_PMCF;
3366
3367                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3368                 IXGBE_WRITE_FLUSH(hw);
3369
3370                 return 0;
3371         }
3372
3373         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3374         return -EIO;
3375 }
3376
3377 /**
3378  *  ixgbe_pfc_enable_generic - Enable flow control
3379  *  @hw: pointer to hardware structure
3380  *  @tc_num: traffic class number
3381  *  Enable flow control according to the current settings.
3382  */
3383 static int
3384 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3385 {
3386         int ret_val = 0;
3387         uint32_t mflcn_reg, fccfg_reg;
3388         uint32_t reg;
3389         uint32_t fcrtl, fcrth;
3390         uint8_t i;
3391         uint8_t nb_rx_en;
3392
3393         /* Validate the water mark configuration */
3394         if (!hw->fc.pause_time) {
3395                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3396                 goto out;
3397         }
3398
3399         /* Low water mark of zero causes XOFF floods */
3400         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3401                  /* High/Low water can not be 0 */
3402                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3403                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3404                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3405                         goto out;
3406                 }
3407
3408                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3409                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3410                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3411                         goto out;
3412                 }
3413         }
3414         /* Negotiate the fc mode to use */
3415         ixgbe_fc_autoneg(hw);
3416
3417         /* Disable any previous flow control settings */
3418         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3419         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3420
3421         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3422         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3423
3424         switch (hw->fc.current_mode) {
3425         case ixgbe_fc_none:
3426                 /*
3427                  * If the count of enabled RX Priority Flow control >1,
3428                  * and the TX pause can not be disabled
3429                  */
3430                 nb_rx_en = 0;
3431                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3432                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3433                         if (reg & IXGBE_FCRTH_FCEN)
3434                                 nb_rx_en++;
3435                 }
3436                 if (nb_rx_en > 1)
3437                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3438                 break;
3439         case ixgbe_fc_rx_pause:
3440                 /*
3441                  * Rx Flow control is enabled and Tx Flow control is
3442                  * disabled by software override. Since there really
3443                  * isn't a way to advertise that we are capable of RX
3444                  * Pause ONLY, we will advertise that we support both
3445                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3446                  * disable the adapter's ability to send PAUSE frames.
3447                  */
3448                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3449                 /*
3450                  * If the count of enabled RX Priority Flow control >1,
3451                  * and the TX pause can not be disabled
3452                  */
3453                 nb_rx_en = 0;
3454                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3455                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3456                         if (reg & IXGBE_FCRTH_FCEN)
3457                                 nb_rx_en++;
3458                 }
3459                 if (nb_rx_en > 1)
3460                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3461                 break;
3462         case ixgbe_fc_tx_pause:
3463                 /*
3464                  * Tx Flow control is enabled, and Rx Flow control is
3465                  * disabled by software override.
3466                  */
3467                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3468                 break;
3469         case ixgbe_fc_full:
3470                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3471                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3472                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3473                 break;
3474         default:
3475                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3476                 ret_val = IXGBE_ERR_CONFIG;
3477                 goto out;
3478                 break;
3479         }
3480
3481         /* Set 802.3x based flow control settings. */
3482         mflcn_reg |= IXGBE_MFLCN_DPF;
3483         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3484         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3485
3486         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3487         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3488                 hw->fc.high_water[tc_num]) {
3489                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3490                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3491                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3492         } else {
3493                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3494                 /*
3495                  * In order to prevent Tx hangs when the internal Tx
3496                  * switch is enabled we must set the high water mark
3497                  * to the maximum FCRTH value.  This allows the Tx
3498                  * switch to function even under heavy Rx workloads.
3499                  */
3500                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3501         }
3502         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3503
3504         /* Configure pause time (2 TCs per register) */
3505         reg = hw->fc.pause_time * 0x00010001;
3506         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3507                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3508
3509         /* Configure flow control refresh threshold value */
3510         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3511
3512 out:
3513         return ret_val;
3514 }
3515
3516 static int
3517 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3518 {
3519         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3520         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3521
3522         if(hw->mac.type != ixgbe_mac_82598EB) {
3523                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3524         }
3525         return ret_val;
3526 }
3527
3528 static int
3529 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3530 {
3531         int err;
3532         uint32_t rx_buf_size;
3533         uint32_t max_high_water;
3534         uint8_t tc_num;
3535         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3536         struct ixgbe_hw *hw =
3537                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3538         struct ixgbe_dcb_config *dcb_config =
3539                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3540
3541         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3542                 ixgbe_fc_none,
3543                 ixgbe_fc_rx_pause,
3544                 ixgbe_fc_tx_pause,
3545                 ixgbe_fc_full
3546         };
3547
3548         PMD_INIT_FUNC_TRACE();
3549
3550         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3551         tc_num = map[pfc_conf->priority];
3552         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3553         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3554         /*
3555          * At least reserve one Ethernet frame for watermark
3556          * high_water/low_water in kilo bytes for ixgbe
3557          */
3558         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3559         if ((pfc_conf->fc.high_water > max_high_water) ||
3560             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3561                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3562                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3563                 return (-EINVAL);
3564         }
3565
3566         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3567         hw->fc.pause_time = pfc_conf->fc.pause_time;
3568         hw->fc.send_xon = pfc_conf->fc.send_xon;
3569         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3570         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3571
3572         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3573
3574         /* Not negotiated is not an error case */
3575         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3576                 return 0;
3577
3578         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3579         return -EIO;
3580 }
3581
3582 static int
3583 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3584                           struct rte_eth_rss_reta_entry64 *reta_conf,
3585                           uint16_t reta_size)
3586 {
3587         uint8_t i, j, mask;
3588         uint32_t reta, r;
3589         uint16_t idx, shift;
3590         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3591         uint16_t sp_reta_size;
3592         uint32_t reta_reg;
3593
3594         PMD_INIT_FUNC_TRACE();
3595
3596         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3597                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3598                         "NIC.");
3599                 return -ENOTSUP;
3600         }
3601
3602         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3603         if (reta_size != sp_reta_size) {
3604                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3605                         "(%d) doesn't match the number hardware can supported "
3606                         "(%d)\n", reta_size, sp_reta_size);
3607                 return -EINVAL;
3608         }
3609
3610         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3611                 idx = i / RTE_RETA_GROUP_SIZE;
3612                 shift = i % RTE_RETA_GROUP_SIZE;
3613                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3614                                                 IXGBE_4_BIT_MASK);
3615                 if (!mask)
3616                         continue;
3617                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3618                 if (mask == IXGBE_4_BIT_MASK)
3619                         r = 0;
3620                 else
3621                         r = IXGBE_READ_REG(hw, reta_reg);
3622                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3623                         if (mask & (0x1 << j))
3624                                 reta |= reta_conf[idx].reta[shift + j] <<
3625                                                         (CHAR_BIT * j);
3626                         else
3627                                 reta |= r & (IXGBE_8_BIT_MASK <<
3628                                                 (CHAR_BIT * j));
3629                 }
3630                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3631         }
3632
3633         return 0;
3634 }
3635
3636 static int
3637 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3638                          struct rte_eth_rss_reta_entry64 *reta_conf,
3639                          uint16_t reta_size)
3640 {
3641         uint8_t i, j, mask;
3642         uint32_t reta;
3643         uint16_t idx, shift;
3644         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645         uint16_t sp_reta_size;
3646         uint32_t reta_reg;
3647
3648         PMD_INIT_FUNC_TRACE();
3649         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3650         if (reta_size != sp_reta_size) {
3651                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3652                         "(%d) doesn't match the number hardware can supported "
3653                         "(%d)\n", reta_size, sp_reta_size);
3654                 return -EINVAL;
3655         }
3656
3657         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3658                 idx = i / RTE_RETA_GROUP_SIZE;
3659                 shift = i % RTE_RETA_GROUP_SIZE;
3660                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3661                                                 IXGBE_4_BIT_MASK);
3662                 if (!mask)
3663                         continue;
3664
3665                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3666                 reta = IXGBE_READ_REG(hw, reta_reg);
3667                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3668                         if (mask & (0x1 << j))
3669                                 reta_conf[idx].reta[shift + j] =
3670                                         ((reta >> (CHAR_BIT * j)) &
3671                                                 IXGBE_8_BIT_MASK);
3672                 }
3673         }
3674
3675         return 0;
3676 }
3677
3678 static void
3679 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3680                                 uint32_t index, uint32_t pool)
3681 {
3682         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3683         uint32_t enable_addr = 1;
3684
3685         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3686 }
3687
3688 static void
3689 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3690 {
3691         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3692
3693         ixgbe_clear_rar(hw, index);
3694 }
3695
3696 static void
3697 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3698 {
3699         ixgbe_remove_rar(dev, 0);
3700
3701         ixgbe_add_rar(dev, addr, 0, 0);
3702 }
3703
3704 static int
3705 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3706 {
3707         uint32_t hlreg0;
3708         uint32_t maxfrs;
3709         struct ixgbe_hw *hw;
3710         struct rte_eth_dev_info dev_info;
3711         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3712
3713         ixgbe_dev_info_get(dev, &dev_info);
3714
3715         /* check that mtu is within the allowed range */
3716         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3717                 return -EINVAL;
3718
3719         /* refuse mtu that requires the support of scattered packets when this
3720          * feature has not been enabled before. */
3721         if (!dev->data->scattered_rx &&
3722             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3723              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3724                 return -EINVAL;
3725
3726         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3727         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3728
3729         /* switch to jumbo mode if needed */
3730         if (frame_size > ETHER_MAX_LEN) {
3731                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3732                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3733         } else {
3734                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3735                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3736         }
3737         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3738
3739         /* update max frame size */
3740         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3741
3742         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3743         maxfrs &= 0x0000FFFF;
3744         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3745         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3746
3747         return 0;
3748 }
3749
3750 /*
3751  * Virtual Function operations
3752  */
3753 static void
3754 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3755 {
3756         PMD_INIT_FUNC_TRACE();
3757
3758         /* Clear interrupt mask to stop from interrupts being generated */
3759         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3760
3761         IXGBE_WRITE_FLUSH(hw);
3762 }
3763
3764 static void
3765 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3766 {
3767         PMD_INIT_FUNC_TRACE();
3768
3769         /* VF enable interrupt autoclean */
3770         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3771         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3772         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3773
3774         IXGBE_WRITE_FLUSH(hw);
3775 }
3776
3777 static int
3778 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3779 {
3780         struct rte_eth_conf* conf = &dev->data->dev_conf;
3781         struct ixgbe_adapter *adapter =
3782                         (struct ixgbe_adapter *)dev->data->dev_private;
3783
3784         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3785                      dev->data->port_id);
3786
3787         /*
3788          * VF has no ability to enable/disable HW CRC
3789          * Keep the persistent behavior the same as Host PF
3790          */
3791 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3792         if (!conf->rxmode.hw_strip_crc) {
3793                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3794                 conf->rxmode.hw_strip_crc = 1;
3795         }
3796 #else
3797         if (conf->rxmode.hw_strip_crc) {
3798                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3799                 conf->rxmode.hw_strip_crc = 0;
3800         }
3801 #endif
3802
3803         /*
3804          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3805          * allocation or vector Rx preconditions we will reset it.
3806          */
3807         adapter->rx_bulk_alloc_allowed = true;
3808         adapter->rx_vec_allowed = true;
3809
3810         return 0;
3811 }
3812
3813 static int
3814 ixgbevf_dev_start(struct rte_eth_dev *dev)
3815 {
3816         struct ixgbe_hw *hw =
3817                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3818         uint32_t intr_vector = 0;
3819         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3820
3821         int err, mask = 0;
3822
3823         PMD_INIT_FUNC_TRACE();
3824
3825         hw->mac.ops.reset_hw(hw);
3826         hw->mac.get_link_status = true;
3827
3828         /* negotiate mailbox API version to use with the PF. */
3829         ixgbevf_negotiate_api(hw);
3830
3831         ixgbevf_dev_tx_init(dev);
3832
3833         /* This can fail when allocating mbufs for descriptor rings */
3834         err = ixgbevf_dev_rx_init(dev);
3835         if (err) {
3836                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3837                 ixgbe_dev_clear_queues(dev);
3838                 return err;
3839         }
3840
3841         /* Set vfta */
3842         ixgbevf_set_vfta_all(dev,1);
3843
3844         /* Set HW strip */
3845         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3846                 ETH_VLAN_EXTEND_MASK;
3847         ixgbevf_vlan_offload_set(dev, mask);
3848
3849         ixgbevf_dev_rxtx_start(dev);
3850
3851         /* check and configure queue intr-vector mapping */
3852         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3853                 intr_vector = dev->data->nb_rx_queues;
3854                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3855                         return -1;
3856         }
3857
3858         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3859                 intr_handle->intr_vec =
3860                         rte_zmalloc("intr_vec",
3861                                     dev->data->nb_rx_queues * sizeof(int), 0);
3862                 if (intr_handle->intr_vec == NULL) {
3863                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3864                                      " intr_vec\n", dev->data->nb_rx_queues);
3865                         return -ENOMEM;
3866                 }
3867         }
3868         ixgbevf_configure_msix(dev);
3869
3870         rte_intr_enable(intr_handle);
3871
3872         /* Re-enable interrupt for VF */
3873         ixgbevf_intr_enable(hw);
3874
3875         return 0;
3876 }
3877
3878 static void
3879 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3880 {
3881         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3882         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3883
3884         PMD_INIT_FUNC_TRACE();
3885
3886         hw->adapter_stopped = 1;
3887         ixgbe_stop_adapter(hw);
3888
3889         /*
3890           * Clear what we set, but we still keep shadow_vfta to
3891           * restore after device starts
3892           */
3893         ixgbevf_set_vfta_all(dev,0);
3894
3895         /* Clear stored conf */
3896         dev->data->scattered_rx = 0;
3897
3898         ixgbe_dev_clear_queues(dev);
3899
3900         /* disable intr eventfd mapping */
3901         rte_intr_disable(intr_handle);
3902
3903         /* Clean datapath event and queue/vec mapping */
3904         rte_intr_efd_disable(intr_handle);
3905         if (intr_handle->intr_vec != NULL) {
3906                 rte_free(intr_handle->intr_vec);
3907                 intr_handle->intr_vec = NULL;
3908         }
3909 }
3910
3911 static void
3912 ixgbevf_dev_close(struct rte_eth_dev *dev)
3913 {
3914         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3915
3916         PMD_INIT_FUNC_TRACE();
3917
3918         ixgbe_reset_hw(hw);
3919
3920         ixgbevf_dev_stop(dev);
3921
3922         ixgbe_dev_free_queues(dev);
3923
3924         /* reprogram the RAR[0] in case user changed it. */
3925         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3926 }
3927
3928 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3929 {
3930         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3931         struct ixgbe_vfta * shadow_vfta =
3932                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3933         int i = 0, j = 0, vfta = 0, mask = 1;
3934
3935         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3936                 vfta = shadow_vfta->vfta[i];
3937                 if(vfta){
3938                         mask = 1;
3939                         for (j = 0; j < 32; j++){
3940                                 if(vfta & mask)
3941                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3942                                 mask<<=1;
3943                         }
3944                 }
3945         }
3946
3947 }
3948
3949 static int
3950 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3951 {
3952         struct ixgbe_hw *hw =
3953                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3954         struct ixgbe_vfta * shadow_vfta =
3955                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3956         uint32_t vid_idx = 0;
3957         uint32_t vid_bit = 0;
3958         int ret = 0;
3959
3960         PMD_INIT_FUNC_TRACE();
3961
3962         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3963         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3964         if(ret){
3965                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3966                 return ret;
3967         }
3968         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3969         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3970
3971         /* Save what we set and retore it after device reset */
3972         if (on)
3973                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3974         else
3975                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3976
3977         return 0;
3978 }
3979
3980 static void
3981 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3982 {
3983         struct ixgbe_hw *hw =
3984                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3985         uint32_t ctrl;
3986
3987         PMD_INIT_FUNC_TRACE();
3988
3989         if(queue >= hw->mac.max_rx_queues)
3990                 return;
3991
3992         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3993         if(on)
3994                 ctrl |= IXGBE_RXDCTL_VME;
3995         else
3996                 ctrl &= ~IXGBE_RXDCTL_VME;
3997         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3998
3999         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4000 }
4001
4002 static void
4003 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4004 {
4005         struct ixgbe_hw *hw =
4006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4007         uint16_t i;
4008         int on = 0;
4009
4010         /* VF function only support hw strip feature, others are not support */
4011         if(mask & ETH_VLAN_STRIP_MASK){
4012                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4013
4014                 for(i=0; i < hw->mac.max_rx_queues; i++)
4015                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4016         }
4017 }
4018
4019 static int
4020 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4021 {
4022         uint32_t reg_val;
4023
4024         /* we only need to do this if VMDq is enabled */
4025         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4026         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4027                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4028                 return (-1);
4029         }
4030
4031         return 0;
4032 }
4033
4034 static uint32_t
4035 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4036 {
4037         uint32_t vector = 0;
4038         switch (hw->mac.mc_filter_type) {
4039         case 0:   /* use bits [47:36] of the address */
4040                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4041                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4042                 break;
4043         case 1:   /* use bits [46:35] of the address */
4044                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4045                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4046                 break;
4047         case 2:   /* use bits [45:34] of the address */
4048                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4049                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4050                 break;
4051         case 3:   /* use bits [43:32] of the address */
4052                 vector = ((uc_addr->addr_bytes[4]) |
4053                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4054                 break;
4055         default:  /* Invalid mc_filter_type */
4056                 break;
4057         }
4058
4059         /* vector can only be 12-bits or boundary will be exceeded */
4060         vector &= 0xFFF;
4061         return vector;
4062 }
4063
4064 static int
4065 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4066                                uint8_t on)
4067 {
4068         uint32_t vector;
4069         uint32_t uta_idx;
4070         uint32_t reg_val;
4071         uint32_t uta_shift;
4072         uint32_t rc;
4073         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4074         const uint32_t ixgbe_uta_bit_shift = 5;
4075         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4076         const uint32_t bit1 = 0x1;
4077
4078         struct ixgbe_hw *hw =
4079                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4080         struct ixgbe_uta_info *uta_info =
4081                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4082
4083         /* The UTA table only exists on 82599 hardware and newer */
4084         if (hw->mac.type < ixgbe_mac_82599EB)
4085                 return (-ENOTSUP);
4086
4087         vector = ixgbe_uta_vector(hw,mac_addr);
4088         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4089         uta_shift = vector & ixgbe_uta_bit_mask;
4090
4091         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4092         if(rc == on)
4093                 return 0;
4094
4095         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4096         if (on) {
4097                 uta_info->uta_in_use++;
4098                 reg_val |= (bit1 << uta_shift);
4099                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4100         } else {
4101                 uta_info->uta_in_use--;
4102                 reg_val &= ~(bit1 << uta_shift);
4103                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4104         }
4105
4106         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4107
4108         if (uta_info->uta_in_use > 0)
4109                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4110                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4111         else
4112                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4113
4114         return 0;
4115 }
4116
4117 static int
4118 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4119 {
4120         int i;
4121         struct ixgbe_hw *hw =
4122                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4123         struct ixgbe_uta_info *uta_info =
4124                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4125
4126         /* The UTA table only exists on 82599 hardware and newer */
4127         if (hw->mac.type < ixgbe_mac_82599EB)
4128                 return (-ENOTSUP);
4129
4130         if(on) {
4131                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4132                         uta_info->uta_shadow[i] = ~0;
4133                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4134                 }
4135         } else {
4136                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4137                         uta_info->uta_shadow[i] = 0;
4138                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4139                 }
4140         }
4141         return 0;
4142
4143 }
4144
4145 uint32_t
4146 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4147 {
4148         uint32_t new_val = orig_val;
4149
4150         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4151                 new_val |= IXGBE_VMOLR_AUPE;
4152         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4153                 new_val |= IXGBE_VMOLR_ROMPE;
4154         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4155                 new_val |= IXGBE_VMOLR_ROPE;
4156         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4157                 new_val |= IXGBE_VMOLR_BAM;
4158         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4159                 new_val |= IXGBE_VMOLR_MPE;
4160
4161         return new_val;
4162 }
4163
4164 static int
4165 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4166                                uint16_t rx_mask, uint8_t on)
4167 {
4168         int val = 0;
4169
4170         struct ixgbe_hw *hw =
4171                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4172         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4173
4174         if (hw->mac.type == ixgbe_mac_82598EB) {
4175                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4176                              " on 82599 hardware and newer");
4177                 return (-ENOTSUP);
4178         }
4179         if (ixgbe_vmdq_mode_check(hw) < 0)
4180                 return (-ENOTSUP);
4181
4182         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4183
4184         if (on)
4185                 vmolr |= val;
4186         else
4187                 vmolr &= ~val;
4188
4189         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4190
4191         return 0;
4192 }
4193
4194 static int
4195 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4196 {
4197         uint32_t reg,addr;
4198         uint32_t val;
4199         const uint8_t bit1 = 0x1;
4200
4201         struct ixgbe_hw *hw =
4202                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4203
4204         if (ixgbe_vmdq_mode_check(hw) < 0)
4205                 return (-ENOTSUP);
4206
4207         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4208         reg = IXGBE_READ_REG(hw, addr);
4209         val = bit1 << pool;
4210
4211         if (on)
4212                 reg |= val;
4213         else
4214                 reg &= ~val;
4215
4216         IXGBE_WRITE_REG(hw, addr,reg);
4217
4218         return 0;
4219 }
4220
4221 static int
4222 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4223 {
4224         uint32_t reg,addr;
4225         uint32_t val;
4226         const uint8_t bit1 = 0x1;
4227
4228         struct ixgbe_hw *hw =
4229                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4230
4231         if (ixgbe_vmdq_mode_check(hw) < 0)
4232                 return (-ENOTSUP);
4233
4234         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4235         reg = IXGBE_READ_REG(hw, addr);
4236         val = bit1 << pool;
4237
4238         if (on)
4239                 reg |= val;
4240         else
4241                 reg &= ~val;
4242
4243         IXGBE_WRITE_REG(hw, addr,reg);
4244
4245         return 0;
4246 }
4247
4248 static int
4249 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4250                         uint64_t pool_mask, uint8_t vlan_on)
4251 {
4252         int ret = 0;
4253         uint16_t pool_idx;
4254         struct ixgbe_hw *hw =
4255                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4256
4257         if (ixgbe_vmdq_mode_check(hw) < 0)
4258                 return (-ENOTSUP);
4259         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4260                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4261                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4262                         if (ret < 0)
4263                                 return ret;
4264         }
4265
4266         return ret;
4267 }
4268
4269 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4270 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4271 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4272 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4273 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4274         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4275         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4276
4277 static int
4278 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4279                         struct rte_eth_mirror_conf *mirror_conf,
4280                         uint8_t rule_id, uint8_t on)
4281 {
4282         uint32_t mr_ctl,vlvf;
4283         uint32_t mp_lsb = 0;
4284         uint32_t mv_msb = 0;
4285         uint32_t mv_lsb = 0;
4286         uint32_t mp_msb = 0;
4287         uint8_t i = 0;
4288         int reg_index = 0;
4289         uint64_t vlan_mask = 0;
4290
4291         const uint8_t pool_mask_offset = 32;
4292         const uint8_t vlan_mask_offset = 32;
4293         const uint8_t dst_pool_offset = 8;
4294         const uint8_t rule_mr_offset  = 4;
4295         const uint8_t mirror_rule_mask= 0x0F;
4296
4297         struct ixgbe_mirror_info *mr_info =
4298                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4299         struct ixgbe_hw *hw =
4300                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4301         uint8_t mirror_type = 0;
4302
4303         if (ixgbe_vmdq_mode_check(hw) < 0)
4304                 return -ENOTSUP;
4305
4306         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4307                 return -EINVAL;
4308
4309         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4310                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4311                         mirror_conf->rule_type);
4312                 return -EINVAL;
4313         }
4314
4315         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4316                 mirror_type |= IXGBE_MRCTL_VLME;
4317                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4318                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4319                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4320                                 /* search vlan id related pool vlan filter index */
4321                                 reg_index = ixgbe_find_vlvf_slot(hw,
4322                                                 mirror_conf->vlan.vlan_id[i]);
4323                                 if(reg_index < 0)
4324                                         return -EINVAL;
4325                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4326                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4327                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4328                                       mirror_conf->vlan.vlan_id[i]))
4329                                         vlan_mask |= (1ULL << reg_index);
4330                                 else
4331                                         return -EINVAL;
4332                         }
4333                 }
4334
4335                 if (on) {
4336                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4337                         mv_msb = vlan_mask >> vlan_mask_offset;
4338
4339                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4340                                                 mirror_conf->vlan.vlan_mask;
4341                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4342                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4343                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4344                                                 mirror_conf->vlan.vlan_id[i];
4345                         }
4346                 } else {
4347                         mv_lsb = 0;
4348                         mv_msb = 0;
4349                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4350                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4351                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4352                 }
4353         }
4354
4355         /*
4356          * if enable pool mirror, write related pool mask register,if disable
4357          * pool mirror, clear PFMRVM register
4358          */
4359         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4360                 mirror_type |= IXGBE_MRCTL_VPME;
4361                 if (on) {
4362                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4363                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4364                         mr_info->mr_conf[rule_id].pool_mask =
4365                                         mirror_conf->pool_mask;
4366
4367                 } else {
4368                         mp_lsb = 0;
4369                         mp_msb = 0;
4370                         mr_info->mr_conf[rule_id].pool_mask = 0;
4371                 }
4372         }
4373         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4374                 mirror_type |= IXGBE_MRCTL_UPME;
4375         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4376                 mirror_type |= IXGBE_MRCTL_DPME;
4377
4378         /* read  mirror control register and recalculate it */
4379         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4380
4381         if (on) {
4382                 mr_ctl |= mirror_type;
4383                 mr_ctl &= mirror_rule_mask;
4384                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4385         } else
4386                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4387
4388         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4389         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4390
4391         /* write mirrror control  register */
4392         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4393
4394         /* write pool mirrror control  register */
4395         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4396                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4397                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4398                                 mp_msb);
4399         }
4400         /* write VLAN mirrror control  register */
4401         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4402                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4403                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4404                                 mv_msb);
4405         }
4406
4407         return 0;
4408 }
4409
4410 static int
4411 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4412 {
4413         int mr_ctl = 0;
4414         uint32_t lsb_val = 0;
4415         uint32_t msb_val = 0;
4416         const uint8_t rule_mr_offset = 4;
4417
4418         struct ixgbe_hw *hw =
4419                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4420         struct ixgbe_mirror_info *mr_info =
4421                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4422
4423         if (ixgbe_vmdq_mode_check(hw) < 0)
4424                 return (-ENOTSUP);
4425
4426         memset(&mr_info->mr_conf[rule_id], 0,
4427                 sizeof(struct rte_eth_mirror_conf));
4428
4429         /* clear PFVMCTL register */
4430         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4431
4432         /* clear pool mask register */
4433         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4434         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4435
4436         /* clear vlan mask register */
4437         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4438         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4439
4440         return 0;
4441 }
4442
4443 static int
4444 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4445 {
4446         uint32_t mask;
4447         struct ixgbe_hw *hw =
4448                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4449
4450         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4451         mask |= (1 << IXGBE_MISC_VEC_ID);
4452         RTE_SET_USED(queue_id);
4453         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4454
4455         rte_intr_enable(&dev->pci_dev->intr_handle);
4456
4457         return 0;
4458 }
4459
4460 static int
4461 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4462 {
4463         uint32_t mask;
4464         struct ixgbe_hw *hw =
4465                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4466
4467         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4468         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4469         RTE_SET_USED(queue_id);
4470         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4471
4472         return 0;
4473 }
4474
4475 static int
4476 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4477 {
4478         uint32_t mask;
4479         struct ixgbe_hw *hw =
4480                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481         struct ixgbe_interrupt *intr =
4482                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4483
4484         if (queue_id < 16) {
4485                 ixgbe_disable_intr(hw);
4486                 intr->mask |= (1 << queue_id);
4487                 ixgbe_enable_intr(dev);
4488         } else if (queue_id < 32) {
4489                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4490                 mask &= (1 << queue_id);
4491                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4492         } else if (queue_id < 64) {
4493                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4494                 mask &= (1 << (queue_id - 32));
4495                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4496         }
4497         rte_intr_enable(&dev->pci_dev->intr_handle);
4498
4499         return 0;
4500 }
4501
4502 static int
4503 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4504 {
4505         uint32_t mask;
4506         struct ixgbe_hw *hw =
4507                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508         struct ixgbe_interrupt *intr =
4509                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4510
4511         if (queue_id < 16) {
4512                 ixgbe_disable_intr(hw);
4513                 intr->mask &= ~(1 << queue_id);
4514                 ixgbe_enable_intr(dev);
4515         } else if (queue_id < 32) {
4516                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4517                 mask &= ~(1 << queue_id);
4518                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4519         } else if (queue_id < 64) {
4520                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4521                 mask &= ~(1 << (queue_id - 32));
4522                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4523         }
4524
4525         return 0;
4526 }
4527
4528 static void
4529 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4530                      uint8_t queue, uint8_t msix_vector)
4531 {
4532         uint32_t tmp, idx;
4533
4534         if (direction == -1) {
4535                 /* other causes */
4536                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4537                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4538                 tmp &= ~0xFF;
4539                 tmp |= msix_vector;
4540                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4541         } else {
4542                 /* rx or tx cause */
4543                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4544                 idx = ((16 * (queue & 1)) + (8 * direction));
4545                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4546                 tmp &= ~(0xFF << idx);
4547                 tmp |= (msix_vector << idx);
4548                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4549         }
4550 }
4551
4552 /**
4553  * set the IVAR registers, mapping interrupt causes to vectors
4554  * @param hw
4555  *  pointer to ixgbe_hw struct
4556  * @direction
4557  *  0 for Rx, 1 for Tx, -1 for other causes
4558  * @queue
4559  *  queue to map the corresponding interrupt to
4560  * @msix_vector
4561  *  the vector to map to the corresponding queue
4562  */
4563 static void
4564 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4565                    uint8_t queue, uint8_t msix_vector)
4566 {
4567         uint32_t tmp, idx;
4568
4569         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4570         if (hw->mac.type == ixgbe_mac_82598EB) {
4571                 if (direction == -1)
4572                         direction = 0;
4573                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4574                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4575                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4576                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4577                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4578         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4579                         (hw->mac.type == ixgbe_mac_X540)) {
4580                 if (direction == -1) {
4581                         /* other causes */
4582                         idx = ((queue & 1) * 8);
4583                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4584                         tmp &= ~(0xFF << idx);
4585                         tmp |= (msix_vector << idx);
4586                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4587                 } else {
4588                         /* rx or tx causes */
4589                         idx = ((16 * (queue & 1)) + (8 * direction));
4590                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4591                         tmp &= ~(0xFF << idx);
4592                         tmp |= (msix_vector << idx);
4593                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4594                 }
4595         }
4596 }
4597
4598 static void
4599 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4600 {
4601         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4602         struct ixgbe_hw *hw =
4603                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4604         uint32_t q_idx;
4605         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4606
4607         /* won't configure msix register if no mapping is done
4608          * between intr vector and event fd.
4609          */
4610         if (!rte_intr_dp_is_en(intr_handle))
4611                 return;
4612
4613         /* Configure all RX queues of VF */
4614         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4615                 /* Force all queue use vector 0,
4616                  * as IXGBE_VF_MAXMSIVECOTR = 1
4617                  */
4618                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4619                 intr_handle->intr_vec[q_idx] = vector_idx;
4620         }
4621
4622         /* Configure VF other cause ivar */
4623         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4624 }
4625
4626 /**
4627  * Sets up the hardware to properly generate MSI-X interrupts
4628  * @hw
4629  *  board private structure
4630  */
4631 static void
4632 ixgbe_configure_msix(struct rte_eth_dev *dev)
4633 {
4634         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4635         struct ixgbe_hw *hw =
4636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4637         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4638         uint32_t vec = IXGBE_MISC_VEC_ID;
4639         uint32_t mask;
4640         uint32_t gpie;
4641
4642         /* won't configure msix register if no mapping is done
4643          * between intr vector and event fd
4644          */
4645         if (!rte_intr_dp_is_en(intr_handle))
4646                 return;
4647
4648         if (rte_intr_allow_others(intr_handle))
4649                 vec = base = IXGBE_RX_VEC_START;
4650
4651         /* setup GPIE for MSI-x mode */
4652         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4653         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4654                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4655         /* auto clearing and auto setting corresponding bits in EIMS
4656          * when MSI-X interrupt is triggered
4657          */
4658         if (hw->mac.type == ixgbe_mac_82598EB) {
4659                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4660         } else {
4661                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4662                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4663         }
4664         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4665
4666         /* Populate the IVAR table and set the ITR values to the
4667          * corresponding register.
4668          */
4669         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4670              queue_id++) {
4671                 /* by default, 1:1 mapping */
4672                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4673                 intr_handle->intr_vec[queue_id] = vec;
4674                 if (vec < base + intr_handle->nb_efd - 1)
4675                         vec++;
4676         }
4677
4678         switch (hw->mac.type) {
4679         case ixgbe_mac_82598EB:
4680                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4681                                    IXGBE_MISC_VEC_ID);
4682                 break;
4683         case ixgbe_mac_82599EB:
4684         case ixgbe_mac_X540:
4685                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4686                 break;
4687         default:
4688                 break;
4689         }
4690         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4691                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4692
4693         /* set up to autoclear timer, and the vectors */
4694         mask = IXGBE_EIMS_ENABLE_MASK;
4695         mask &= ~(IXGBE_EIMS_OTHER |
4696                   IXGBE_EIMS_MAILBOX |
4697                   IXGBE_EIMS_LSC);
4698
4699         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4700 }
4701
4702 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4703         uint16_t queue_idx, uint16_t tx_rate)
4704 {
4705         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4706         uint32_t rf_dec, rf_int;
4707         uint32_t bcnrc_val;
4708         uint16_t link_speed = dev->data->dev_link.link_speed;
4709
4710         if (queue_idx >= hw->mac.max_tx_queues)
4711                 return -EINVAL;
4712
4713         if (tx_rate != 0) {
4714                 /* Calculate the rate factor values to set */
4715                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4716                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4717                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4718
4719                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4720                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4721                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4722                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4723         } else {
4724                 bcnrc_val = 0;
4725         }
4726
4727         /*
4728          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4729          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4730          * set as 0x4.
4731          */
4732         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4733                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4734                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4735                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4736                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4737         else
4738                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4739                         IXGBE_MMW_SIZE_DEFAULT);
4740
4741         /* Set RTTBCNRC of queue X */
4742         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4743         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4744         IXGBE_WRITE_FLUSH(hw);
4745
4746         return 0;
4747 }
4748
4749 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4750         uint16_t tx_rate, uint64_t q_msk)
4751 {
4752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4753         struct ixgbe_vf_info *vfinfo =
4754                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4755         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4756         uint32_t queue_stride =
4757                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4758         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4759         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4760         uint16_t total_rate = 0;
4761
4762         if (queue_end >= hw->mac.max_tx_queues)
4763                 return -EINVAL;
4764
4765         if (vfinfo != NULL) {
4766                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4767                         if (vf_idx == vf)
4768                                 continue;
4769                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4770                                 idx++)
4771                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4772                 }
4773         } else
4774                 return -EINVAL;
4775
4776         /* Store tx_rate for this vf. */
4777         for (idx = 0; idx < nb_q_per_pool; idx++) {
4778                 if (((uint64_t)0x1 << idx) & q_msk) {
4779                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4780                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4781                         total_rate += tx_rate;
4782                 }
4783         }
4784
4785         if (total_rate > dev->data->dev_link.link_speed) {
4786                 /*
4787                  * Reset stored TX rate of the VF if it causes exceed
4788                  * link speed.
4789                  */
4790                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4791                 return -EINVAL;
4792         }
4793
4794         /* Set RTTBCNRC of each queue/pool for vf X  */
4795         for (; queue_idx <= queue_end; queue_idx++) {
4796                 if (0x1 & q_msk)
4797                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4798                 q_msk = q_msk >> 1;
4799         }
4800
4801         return 0;
4802 }
4803
4804 static void
4805 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4806                      __attribute__((unused)) uint32_t index,
4807                      __attribute__((unused)) uint32_t pool)
4808 {
4809         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4810         int diag;
4811
4812         /*
4813          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4814          * operation. Trap this case to avoid exhausting the [very limited]
4815          * set of PF resources used to store VF MAC addresses.
4816          */
4817         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4818                 return;
4819         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4820         if (diag == 0)
4821                 return;
4822         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4823 }
4824
4825 static void
4826 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4827 {
4828         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4830         struct ether_addr *mac_addr;
4831         uint32_t i;
4832         int diag;
4833
4834         /*
4835          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4836          * not support the deletion of a given MAC address.
4837          * Instead, it imposes to delete all MAC addresses, then to add again
4838          * all MAC addresses with the exception of the one to be deleted.
4839          */
4840         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4841
4842         /*
4843          * Add again all MAC addresses, with the exception of the deleted one
4844          * and of the permanent MAC address.
4845          */
4846         for (i = 0, mac_addr = dev->data->mac_addrs;
4847              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4848                 /* Skip the deleted MAC address */
4849                 if (i == index)
4850                         continue;
4851                 /* Skip NULL MAC addresses */
4852                 if (is_zero_ether_addr(mac_addr))
4853                         continue;
4854                 /* Skip the permanent MAC address */
4855                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4856                         continue;
4857                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4858                 if (diag != 0)
4859                         PMD_DRV_LOG(ERR,
4860                                     "Adding again MAC address "
4861                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4862                                     "diag=%d",
4863                                     mac_addr->addr_bytes[0],
4864                                     mac_addr->addr_bytes[1],
4865                                     mac_addr->addr_bytes[2],
4866                                     mac_addr->addr_bytes[3],
4867                                     mac_addr->addr_bytes[4],
4868                                     mac_addr->addr_bytes[5],
4869                                     diag);
4870         }
4871 }
4872
4873 static void
4874 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4875 {
4876         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4877
4878         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4879 }
4880
4881 #define MAC_TYPE_FILTER_SUP(type)    do {\
4882         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4883                 (type) != ixgbe_mac_X550)\
4884                 return -ENOTSUP;\
4885 } while (0)
4886
4887 static int
4888 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4889                         struct rte_eth_syn_filter *filter,
4890                         bool add)
4891 {
4892         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4893         uint32_t synqf;
4894
4895         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4896                 return -EINVAL;
4897
4898         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4899
4900         if (add) {
4901                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4902                         return -EINVAL;
4903                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4904                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4905
4906                 if (filter->hig_pri)
4907                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4908                 else
4909                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4910         } else {
4911                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4912                         return -ENOENT;
4913                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4914         }
4915         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4916         IXGBE_WRITE_FLUSH(hw);
4917         return 0;
4918 }
4919
4920 static int
4921 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4922                         struct rte_eth_syn_filter *filter)
4923 {
4924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4925         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4926
4927         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4928                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4929                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4930                 return 0;
4931         }
4932         return -ENOENT;
4933 }
4934
4935 static int
4936 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4937                         enum rte_filter_op filter_op,
4938                         void *arg)
4939 {
4940         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4941         int ret;
4942
4943         MAC_TYPE_FILTER_SUP(hw->mac.type);
4944
4945         if (filter_op == RTE_ETH_FILTER_NOP)
4946                 return 0;
4947
4948         if (arg == NULL) {
4949                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4950                             filter_op);
4951                 return -EINVAL;
4952         }
4953
4954         switch (filter_op) {
4955         case RTE_ETH_FILTER_ADD:
4956                 ret = ixgbe_syn_filter_set(dev,
4957                                 (struct rte_eth_syn_filter *)arg,
4958                                 TRUE);
4959                 break;
4960         case RTE_ETH_FILTER_DELETE:
4961                 ret = ixgbe_syn_filter_set(dev,
4962                                 (struct rte_eth_syn_filter *)arg,
4963                                 FALSE);
4964                 break;
4965         case RTE_ETH_FILTER_GET:
4966                 ret = ixgbe_syn_filter_get(dev,
4967                                 (struct rte_eth_syn_filter *)arg);
4968                 break;
4969         default:
4970                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4971                 ret = -EINVAL;
4972                 break;
4973         }
4974
4975         return ret;
4976 }
4977
4978
4979 static inline enum ixgbe_5tuple_protocol
4980 convert_protocol_type(uint8_t protocol_value)
4981 {
4982         if (protocol_value == IPPROTO_TCP)
4983                 return IXGBE_FILTER_PROTOCOL_TCP;
4984         else if (protocol_value == IPPROTO_UDP)
4985                 return IXGBE_FILTER_PROTOCOL_UDP;
4986         else if (protocol_value == IPPROTO_SCTP)
4987                 return IXGBE_FILTER_PROTOCOL_SCTP;
4988         else
4989                 return IXGBE_FILTER_PROTOCOL_NONE;
4990 }
4991
4992 /*
4993  * add a 5tuple filter
4994  *
4995  * @param
4996  * dev: Pointer to struct rte_eth_dev.
4997  * index: the index the filter allocates.
4998  * filter: ponter to the filter that will be added.
4999  * rx_queue: the queue id the filter assigned to.
5000  *
5001  * @return
5002  *    - On success, zero.
5003  *    - On failure, a negative value.
5004  */
5005 static int
5006 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5007                         struct ixgbe_5tuple_filter *filter)
5008 {
5009         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5010         struct ixgbe_filter_info *filter_info =
5011                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5012         int i, idx, shift;
5013         uint32_t ftqf, sdpqf;
5014         uint32_t l34timir = 0;
5015         uint8_t mask = 0xff;
5016
5017         /*
5018          * look for an unused 5tuple filter index,
5019          * and insert the filter to list.
5020          */
5021         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5022                 idx = i / (sizeof(uint32_t) * NBBY);
5023                 shift = i % (sizeof(uint32_t) * NBBY);
5024                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5025                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5026                         filter->index = i;
5027                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5028                                           filter,
5029                                           entries);
5030                         break;
5031                 }
5032         }
5033         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5034                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5035                 return -ENOSYS;
5036         }
5037
5038         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5039                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5040         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5041
5042         ftqf = (uint32_t)(filter->filter_info.proto &
5043                 IXGBE_FTQF_PROTOCOL_MASK);
5044         ftqf |= (uint32_t)((filter->filter_info.priority &
5045                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5046         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5047                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5048         if (filter->filter_info.dst_ip_mask == 0)
5049                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5050         if (filter->filter_info.src_port_mask == 0)
5051                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5052         if (filter->filter_info.dst_port_mask == 0)
5053                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5054         if (filter->filter_info.proto_mask == 0)
5055                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5056         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5057         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5058         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5059
5060         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5061         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5062         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5063         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5064
5065         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5066         l34timir |= (uint32_t)(filter->queue <<
5067                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5068         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5069         return 0;
5070 }
5071
5072 /*
5073  * remove a 5tuple filter
5074  *
5075  * @param
5076  * dev: Pointer to struct rte_eth_dev.
5077  * filter: the pointer of the filter will be removed.
5078  */
5079 static void
5080 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5081                         struct ixgbe_5tuple_filter *filter)
5082 {
5083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084         struct ixgbe_filter_info *filter_info =
5085                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5086         uint16_t index = filter->index;
5087
5088         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5089                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5090         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5091         rte_free(filter);
5092
5093         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5094         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5095         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5096         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5097         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5098 }
5099
5100 static int
5101 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5102 {
5103         struct ixgbe_hw *hw;
5104         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5105
5106         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5107
5108         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5109                 return -EINVAL;
5110
5111         /* refuse mtu that requires the support of scattered packets when this
5112          * feature has not been enabled before. */
5113         if (!dev->data->scattered_rx &&
5114             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5115              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5116                 return -EINVAL;
5117
5118         /*
5119          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5120          * request of the version 2.0 of the mailbox API.
5121          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5122          * of the mailbox API.
5123          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5124          * prior to 3.11.33 which contains the following change:
5125          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5126          */
5127         ixgbevf_rlpml_set_vf(hw, max_frame);
5128
5129         /* update max frame size */
5130         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5131         return 0;
5132 }
5133
5134 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5135         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5136                 return -ENOTSUP;\
5137 } while (0)
5138
5139 static inline struct ixgbe_5tuple_filter *
5140 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5141                         struct ixgbe_5tuple_filter_info *key)
5142 {
5143         struct ixgbe_5tuple_filter *it;
5144
5145         TAILQ_FOREACH(it, filter_list, entries) {
5146                 if (memcmp(key, &it->filter_info,
5147                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5148                         return it;
5149                 }
5150         }
5151         return NULL;
5152 }
5153
5154 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5155 static inline int
5156 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5157                         struct ixgbe_5tuple_filter_info *filter_info)
5158 {
5159         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5160                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5161                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5162                 return -EINVAL;
5163
5164         switch (filter->dst_ip_mask) {
5165         case UINT32_MAX:
5166                 filter_info->dst_ip_mask = 0;
5167                 filter_info->dst_ip = filter->dst_ip;
5168                 break;
5169         case 0:
5170                 filter_info->dst_ip_mask = 1;
5171                 break;
5172         default:
5173                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5174                 return -EINVAL;
5175         }
5176
5177         switch (filter->src_ip_mask) {
5178         case UINT32_MAX:
5179                 filter_info->src_ip_mask = 0;
5180                 filter_info->src_ip = filter->src_ip;
5181                 break;
5182         case 0:
5183                 filter_info->src_ip_mask = 1;
5184                 break;
5185         default:
5186                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5187                 return -EINVAL;
5188         }
5189
5190         switch (filter->dst_port_mask) {
5191         case UINT16_MAX:
5192                 filter_info->dst_port_mask = 0;
5193                 filter_info->dst_port = filter->dst_port;
5194                 break;
5195         case 0:
5196                 filter_info->dst_port_mask = 1;
5197                 break;
5198         default:
5199                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5200                 return -EINVAL;
5201         }
5202
5203         switch (filter->src_port_mask) {
5204         case UINT16_MAX:
5205                 filter_info->src_port_mask = 0;
5206                 filter_info->src_port = filter->src_port;
5207                 break;
5208         case 0:
5209                 filter_info->src_port_mask = 1;
5210                 break;
5211         default:
5212                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5213                 return -EINVAL;
5214         }
5215
5216         switch (filter->proto_mask) {
5217         case UINT8_MAX:
5218                 filter_info->proto_mask = 0;
5219                 filter_info->proto =
5220                         convert_protocol_type(filter->proto);
5221                 break;
5222         case 0:
5223                 filter_info->proto_mask = 1;
5224                 break;
5225         default:
5226                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5227                 return -EINVAL;
5228         }
5229
5230         filter_info->priority = (uint8_t)filter->priority;
5231         return 0;
5232 }
5233
5234 /*
5235  * add or delete a ntuple filter
5236  *
5237  * @param
5238  * dev: Pointer to struct rte_eth_dev.
5239  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5240  * add: if true, add filter, if false, remove filter
5241  *
5242  * @return
5243  *    - On success, zero.
5244  *    - On failure, a negative value.
5245  */
5246 static int
5247 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5248                         struct rte_eth_ntuple_filter *ntuple_filter,
5249                         bool add)
5250 {
5251         struct ixgbe_filter_info *filter_info =
5252                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5253         struct ixgbe_5tuple_filter_info filter_5tuple;
5254         struct ixgbe_5tuple_filter *filter;
5255         int ret;
5256
5257         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5258                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5259                 return -EINVAL;
5260         }
5261
5262         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5263         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5264         if (ret < 0)
5265                 return ret;
5266
5267         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5268                                          &filter_5tuple);
5269         if (filter != NULL && add) {
5270                 PMD_DRV_LOG(ERR, "filter exists.");
5271                 return -EEXIST;
5272         }
5273         if (filter == NULL && !add) {
5274                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5275                 return -ENOENT;
5276         }
5277
5278         if (add) {
5279                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5280                                 sizeof(struct ixgbe_5tuple_filter), 0);
5281                 if (filter == NULL)
5282                         return -ENOMEM;
5283                 (void)rte_memcpy(&filter->filter_info,
5284                                  &filter_5tuple,
5285                                  sizeof(struct ixgbe_5tuple_filter_info));
5286                 filter->queue = ntuple_filter->queue;
5287                 ret = ixgbe_add_5tuple_filter(dev, filter);
5288                 if (ret < 0) {
5289                         rte_free(filter);
5290                         return ret;
5291                 }
5292         } else
5293                 ixgbe_remove_5tuple_filter(dev, filter);
5294
5295         return 0;
5296 }
5297
5298 /*
5299  * get a ntuple filter
5300  *
5301  * @param
5302  * dev: Pointer to struct rte_eth_dev.
5303  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5304  *
5305  * @return
5306  *    - On success, zero.
5307  *    - On failure, a negative value.
5308  */
5309 static int
5310 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5311                         struct rte_eth_ntuple_filter *ntuple_filter)
5312 {
5313         struct ixgbe_filter_info *filter_info =
5314                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5315         struct ixgbe_5tuple_filter_info filter_5tuple;
5316         struct ixgbe_5tuple_filter *filter;
5317         int ret;
5318
5319         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5320                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5321                 return -EINVAL;
5322         }
5323
5324         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5325         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5326         if (ret < 0)
5327                 return ret;
5328
5329         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5330                                          &filter_5tuple);
5331         if (filter == NULL) {
5332                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5333                 return -ENOENT;
5334         }
5335         ntuple_filter->queue = filter->queue;
5336         return 0;
5337 }
5338
5339 /*
5340  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5341  * @dev: pointer to rte_eth_dev structure
5342  * @filter_op:operation will be taken.
5343  * @arg: a pointer to specific structure corresponding to the filter_op
5344  *
5345  * @return
5346  *    - On success, zero.
5347  *    - On failure, a negative value.
5348  */
5349 static int
5350 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5351                                 enum rte_filter_op filter_op,
5352                                 void *arg)
5353 {
5354         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5355         int ret;
5356
5357         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5358
5359         if (filter_op == RTE_ETH_FILTER_NOP)
5360                 return 0;
5361
5362         if (arg == NULL) {
5363                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5364                             filter_op);
5365                 return -EINVAL;
5366         }
5367
5368         switch (filter_op) {
5369         case RTE_ETH_FILTER_ADD:
5370                 ret = ixgbe_add_del_ntuple_filter(dev,
5371                         (struct rte_eth_ntuple_filter *)arg,
5372                         TRUE);
5373                 break;
5374         case RTE_ETH_FILTER_DELETE:
5375                 ret = ixgbe_add_del_ntuple_filter(dev,
5376                         (struct rte_eth_ntuple_filter *)arg,
5377                         FALSE);
5378                 break;
5379         case RTE_ETH_FILTER_GET:
5380                 ret = ixgbe_get_ntuple_filter(dev,
5381                         (struct rte_eth_ntuple_filter *)arg);
5382                 break;
5383         default:
5384                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5385                 ret = -EINVAL;
5386                 break;
5387         }
5388         return ret;
5389 }
5390
5391 static inline int
5392 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5393                         uint16_t ethertype)
5394 {
5395         int i;
5396
5397         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5398                 if (filter_info->ethertype_filters[i] == ethertype &&
5399                     (filter_info->ethertype_mask & (1 << i)))
5400                         return i;
5401         }
5402         return -1;
5403 }
5404
5405 static inline int
5406 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5407                         uint16_t ethertype)
5408 {
5409         int i;
5410
5411         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5412                 if (!(filter_info->ethertype_mask & (1 << i))) {
5413                         filter_info->ethertype_mask |= 1 << i;
5414                         filter_info->ethertype_filters[i] = ethertype;
5415                         return i;
5416                 }
5417         }
5418         return -1;
5419 }
5420
5421 static inline int
5422 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5423                         uint8_t idx)
5424 {
5425         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5426                 return -1;
5427         filter_info->ethertype_mask &= ~(1 << idx);
5428         filter_info->ethertype_filters[idx] = 0;
5429         return idx;
5430 }
5431
5432 static int
5433 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5434                         struct rte_eth_ethertype_filter *filter,
5435                         bool add)
5436 {
5437         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5438         struct ixgbe_filter_info *filter_info =
5439                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5440         uint32_t etqf = 0;
5441         uint32_t etqs = 0;
5442         int ret;
5443
5444         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5445                 return -EINVAL;
5446
5447         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5448                 filter->ether_type == ETHER_TYPE_IPv6) {
5449                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5450                         " ethertype filter.", filter->ether_type);
5451                 return -EINVAL;
5452         }
5453
5454         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5455                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5456                 return -EINVAL;
5457         }
5458         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5459                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5460                 return -EINVAL;
5461         }
5462
5463         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5464         if (ret >= 0 && add) {
5465                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5466                             filter->ether_type);
5467                 return -EEXIST;
5468         }
5469         if (ret < 0 && !add) {
5470                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5471                             filter->ether_type);
5472                 return -ENOENT;
5473         }
5474
5475         if (add) {
5476                 ret = ixgbe_ethertype_filter_insert(filter_info,
5477                         filter->ether_type);
5478                 if (ret < 0) {
5479                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5480                         return -ENOSYS;
5481                 }
5482                 etqf = IXGBE_ETQF_FILTER_EN;
5483                 etqf |= (uint32_t)filter->ether_type;
5484                 etqs |= (uint32_t)((filter->queue <<
5485                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5486                                     IXGBE_ETQS_RX_QUEUE);
5487                 etqs |= IXGBE_ETQS_QUEUE_EN;
5488         } else {
5489                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5490                 if (ret < 0)
5491                         return -ENOSYS;
5492         }
5493         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5494         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5495         IXGBE_WRITE_FLUSH(hw);
5496
5497         return 0;
5498 }
5499
5500 static int
5501 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5502                         struct rte_eth_ethertype_filter *filter)
5503 {
5504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5505         struct ixgbe_filter_info *filter_info =
5506                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5507         uint32_t etqf, etqs;
5508         int ret;
5509
5510         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5511         if (ret < 0) {
5512                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5513                             filter->ether_type);
5514                 return -ENOENT;
5515         }
5516
5517         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5518         if (etqf & IXGBE_ETQF_FILTER_EN) {
5519                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5520                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5521                 filter->flags = 0;
5522                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5523                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5524                 return 0;
5525         }
5526         return -ENOENT;
5527 }
5528
5529 /*
5530  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5531  * @dev: pointer to rte_eth_dev structure
5532  * @filter_op:operation will be taken.
5533  * @arg: a pointer to specific structure corresponding to the filter_op
5534  */
5535 static int
5536 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5537                                 enum rte_filter_op filter_op,
5538                                 void *arg)
5539 {
5540         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5541         int ret;
5542
5543         MAC_TYPE_FILTER_SUP(hw->mac.type);
5544
5545         if (filter_op == RTE_ETH_FILTER_NOP)
5546                 return 0;
5547
5548         if (arg == NULL) {
5549                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5550                             filter_op);
5551                 return -EINVAL;
5552         }
5553
5554         switch (filter_op) {
5555         case RTE_ETH_FILTER_ADD:
5556                 ret = ixgbe_add_del_ethertype_filter(dev,
5557                         (struct rte_eth_ethertype_filter *)arg,
5558                         TRUE);
5559                 break;
5560         case RTE_ETH_FILTER_DELETE:
5561                 ret = ixgbe_add_del_ethertype_filter(dev,
5562                         (struct rte_eth_ethertype_filter *)arg,
5563                         FALSE);
5564                 break;
5565         case RTE_ETH_FILTER_GET:
5566                 ret = ixgbe_get_ethertype_filter(dev,
5567                         (struct rte_eth_ethertype_filter *)arg);
5568                 break;
5569         default:
5570                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5571                 ret = -EINVAL;
5572                 break;
5573         }
5574         return ret;
5575 }
5576
5577 static int
5578 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5579                      enum rte_filter_type filter_type,
5580                      enum rte_filter_op filter_op,
5581                      void *arg)
5582 {
5583         int ret = -EINVAL;
5584
5585         switch (filter_type) {
5586         case RTE_ETH_FILTER_NTUPLE:
5587                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5588                 break;
5589         case RTE_ETH_FILTER_ETHERTYPE:
5590                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5591                 break;
5592         case RTE_ETH_FILTER_SYN:
5593                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5594                 break;
5595         case RTE_ETH_FILTER_FDIR:
5596                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5597                 break;
5598         default:
5599                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5600                                                         filter_type);
5601                 break;
5602         }
5603
5604         return ret;
5605 }
5606
5607 static u8 *
5608 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5609                         u8 **mc_addr_ptr, u32 *vmdq)
5610 {
5611         u8 *mc_addr;
5612
5613         *vmdq = 0;
5614         mc_addr = *mc_addr_ptr;
5615         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5616         return mc_addr;
5617 }
5618
5619 static int
5620 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5621                           struct ether_addr *mc_addr_set,
5622                           uint32_t nb_mc_addr)
5623 {
5624         struct ixgbe_hw *hw;
5625         u8 *mc_addr_list;
5626
5627         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5628         mc_addr_list = (u8 *)mc_addr_set;
5629         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5630                                          ixgbe_dev_addr_list_itr, TRUE);
5631 }
5632
5633 static uint64_t
5634 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5635 {
5636         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5637         uint64_t systime_cycles;
5638
5639         switch (hw->mac.type) {
5640         case ixgbe_mac_X550:
5641                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5642                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5643                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5644                                 * NSEC_PER_SEC;
5645                 break;
5646         default:
5647                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5648                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5649                                 << 32;
5650         }
5651
5652         return systime_cycles;
5653 }
5654
5655 static uint64_t
5656 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5657 {
5658         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5659         uint64_t rx_tstamp_cycles;
5660
5661         switch (hw->mac.type) {
5662         case ixgbe_mac_X550:
5663                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5664                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5665                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5666                                 * NSEC_PER_SEC;
5667                 break;
5668         default:
5669                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5670                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5671                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5672                                 << 32;
5673         }
5674
5675         return rx_tstamp_cycles;
5676 }
5677
5678 static uint64_t
5679 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5680 {
5681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5682         uint64_t tx_tstamp_cycles;
5683
5684         switch (hw->mac.type) {
5685         case ixgbe_mac_X550:
5686                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5687                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5688                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5689                                 * NSEC_PER_SEC;
5690                 break;
5691         default:
5692                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5693                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5694                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5695                                 << 32;
5696         }
5697
5698         return tx_tstamp_cycles;
5699 }
5700
5701 static void
5702 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5703 {
5704         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5705         struct ixgbe_adapter *adapter =
5706                 (struct ixgbe_adapter *)dev->data->dev_private;
5707         struct rte_eth_link link;
5708         uint32_t incval = 0;
5709         uint32_t shift = 0;
5710
5711         /* Get current link speed. */
5712         memset(&link, 0, sizeof(link));
5713         ixgbe_dev_link_update(dev, 1);
5714         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5715
5716         switch (link.link_speed) {
5717         case ETH_LINK_SPEED_100:
5718                 incval = IXGBE_INCVAL_100;
5719                 shift = IXGBE_INCVAL_SHIFT_100;
5720                 break;
5721         case ETH_LINK_SPEED_1000:
5722                 incval = IXGBE_INCVAL_1GB;
5723                 shift = IXGBE_INCVAL_SHIFT_1GB;
5724                 break;
5725         case ETH_LINK_SPEED_10000:
5726         default:
5727                 incval = IXGBE_INCVAL_10GB;
5728                 shift = IXGBE_INCVAL_SHIFT_10GB;
5729                 break;
5730         }
5731
5732         switch (hw->mac.type) {
5733         case ixgbe_mac_X550:
5734                 /* Independent of link speed. */
5735                 incval = 1;
5736                 /* Cycles read will be interpreted as ns. */
5737                 shift = 0;
5738                 /* Fall-through */
5739         case ixgbe_mac_X540:
5740                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5741                 break;
5742         case ixgbe_mac_82599EB:
5743                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5744                 shift -= IXGBE_INCVAL_SHIFT_82599;
5745                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5746                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5747                 break;
5748         default:
5749                 /* Not supported. */
5750                 return;
5751         }
5752
5753         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5754         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5755         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5756
5757         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5758         adapter->systime_tc.cc_shift = shift;
5759         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5760
5761         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5762         adapter->rx_tstamp_tc.cc_shift = shift;
5763         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5764
5765         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5766         adapter->tx_tstamp_tc.cc_shift = shift;
5767         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5768 }
5769
5770 static int
5771 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5772 {
5773         struct ixgbe_adapter *adapter =
5774                         (struct ixgbe_adapter *)dev->data->dev_private;
5775
5776         adapter->systime_tc.nsec += delta;
5777         adapter->rx_tstamp_tc.nsec += delta;
5778         adapter->tx_tstamp_tc.nsec += delta;
5779
5780         return 0;
5781 }
5782
5783 static int
5784 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5785 {
5786         uint64_t ns;
5787         struct ixgbe_adapter *adapter =
5788                         (struct ixgbe_adapter *)dev->data->dev_private;
5789
5790         ns = rte_timespec_to_ns(ts);
5791         /* Set the timecounters to a new value. */
5792         adapter->systime_tc.nsec = ns;
5793         adapter->rx_tstamp_tc.nsec = ns;
5794         adapter->tx_tstamp_tc.nsec = ns;
5795
5796         return 0;
5797 }
5798
5799 static int
5800 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5801 {
5802         uint64_t ns, systime_cycles;
5803         struct ixgbe_adapter *adapter =
5804                         (struct ixgbe_adapter *)dev->data->dev_private;
5805
5806         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5807         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5808         *ts = rte_ns_to_timespec(ns);
5809
5810         return 0;
5811 }
5812
5813 static int
5814 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5815 {
5816         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5817         uint32_t tsync_ctl;
5818         uint32_t tsauxc;
5819
5820         /* Stop the timesync system time. */
5821         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5822         /* Reset the timesync system time value. */
5823         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5824         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5825
5826         /* Enable system time for platforms where it isn't on by default. */
5827         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5828         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5829         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5830
5831         ixgbe_start_timecounters(dev);
5832
5833         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5834         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5835                         (ETHER_TYPE_1588 |
5836                          IXGBE_ETQF_FILTER_EN |
5837                          IXGBE_ETQF_1588));
5838
5839         /* Enable timestamping of received PTP packets. */
5840         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5841         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5842         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5843
5844         /* Enable timestamping of transmitted PTP packets. */
5845         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5846         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5847         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5848
5849         IXGBE_WRITE_FLUSH(hw);
5850
5851         return 0;
5852 }
5853
5854 static int
5855 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5856 {
5857         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5858         uint32_t tsync_ctl;
5859
5860         /* Disable timestamping of transmitted PTP packets. */
5861         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5862         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5863         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5864
5865         /* Disable timestamping of received PTP packets. */
5866         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5867         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5868         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5869
5870         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5871         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5872
5873         /* Stop incrementating the System Time registers. */
5874         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5875
5876         return 0;
5877 }
5878
5879 static int
5880 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5881                                  struct timespec *timestamp,
5882                                  uint32_t flags __rte_unused)
5883 {
5884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5885         struct ixgbe_adapter *adapter =
5886                 (struct ixgbe_adapter *)dev->data->dev_private;
5887         uint32_t tsync_rxctl;
5888         uint64_t rx_tstamp_cycles;
5889         uint64_t ns;
5890
5891         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5892         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5893                 return -EINVAL;
5894
5895         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
5896         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5897         *timestamp = rte_ns_to_timespec(ns);
5898
5899         return  0;
5900 }
5901
5902 static int
5903 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5904                                  struct timespec *timestamp)
5905 {
5906         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5907         struct ixgbe_adapter *adapter =
5908                 (struct ixgbe_adapter *)dev->data->dev_private;
5909         uint32_t tsync_txctl;
5910         uint64_t tx_tstamp_cycles;
5911         uint64_t ns;
5912
5913         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5914         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5915                 return -EINVAL;
5916
5917         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
5918         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5919         *timestamp = rte_ns_to_timespec(ns);
5920
5921         return 0;
5922 }
5923
5924 static int
5925 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5926 {
5927         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5928         int count = 0;
5929         int g_ind = 0;
5930         const struct reg_info *reg_group;
5931         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5932                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5933
5934         while ((reg_group = reg_set[g_ind++]))
5935                 count += ixgbe_regs_group_count(reg_group);
5936
5937         return count;
5938 }
5939
5940 static int
5941 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5942 {
5943         int count = 0;
5944         int g_ind = 0;
5945         const struct reg_info *reg_group;
5946
5947         while ((reg_group = ixgbevf_regs[g_ind++]))
5948                 count += ixgbe_regs_group_count(reg_group);
5949
5950         return count;
5951 }
5952
5953 static int
5954 ixgbe_get_regs(struct rte_eth_dev *dev,
5955               struct rte_dev_reg_info *regs)
5956 {
5957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5958         uint32_t *data = regs->data;
5959         int g_ind = 0;
5960         int count = 0;
5961         const struct reg_info *reg_group;
5962         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5963                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5964
5965         /* Support only full register dump */
5966         if ((regs->length == 0) ||
5967             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5968                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5969                         hw->device_id;
5970                 while ((reg_group = reg_set[g_ind++]))
5971                         count += ixgbe_read_regs_group(dev, &data[count],
5972                                 reg_group);
5973                 return 0;
5974         }
5975
5976         return -ENOTSUP;
5977 }
5978
5979 static int
5980 ixgbevf_get_regs(struct rte_eth_dev *dev,
5981                 struct rte_dev_reg_info *regs)
5982 {
5983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5984         uint32_t *data = regs->data;
5985         int g_ind = 0;
5986         int count = 0;
5987         const struct reg_info *reg_group;
5988
5989         /* Support only full register dump */
5990         if ((regs->length == 0) ||
5991             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5992                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5993                         hw->device_id;
5994                 while ((reg_group = ixgbevf_regs[g_ind++]))
5995                         count += ixgbe_read_regs_group(dev, &data[count],
5996                                                       reg_group);
5997                 return 0;
5998         }
5999
6000         return -ENOTSUP;
6001 }
6002
6003 static int
6004 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6005 {
6006         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6007
6008         /* Return unit is byte count */
6009         return hw->eeprom.word_size * 2;
6010 }
6011
6012 static int
6013 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6014                 struct rte_dev_eeprom_info *in_eeprom)
6015 {
6016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6017         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6018         uint16_t *data = in_eeprom->data;
6019         int first, length;
6020
6021         first = in_eeprom->offset >> 1;
6022         length = in_eeprom->length >> 1;
6023         if ((first > hw->eeprom.word_size) ||
6024             ((first + length) > hw->eeprom.word_size))
6025                 return -EINVAL;
6026
6027         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6028
6029         return eeprom->ops.read_buffer(hw, first, length, data);
6030 }
6031
6032 static int
6033 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6034                 struct rte_dev_eeprom_info *in_eeprom)
6035 {
6036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6037         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6038         uint16_t *data = in_eeprom->data;
6039         int first, length;
6040
6041         first = in_eeprom->offset >> 1;
6042         length = in_eeprom->length >> 1;
6043         if ((first > hw->eeprom.word_size) ||
6044             ((first + length) > hw->eeprom.word_size))
6045                 return -EINVAL;
6046
6047         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6048
6049         return eeprom->ops.write_buffer(hw,  first, length, data);
6050 }
6051
6052 uint16_t
6053 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6054         switch (mac_type) {
6055         case ixgbe_mac_X550:
6056         case ixgbe_mac_X550EM_x:
6057                 return ETH_RSS_RETA_SIZE_512;
6058         case ixgbe_mac_X550_vf:
6059         case ixgbe_mac_X550EM_x_vf:
6060                 return ETH_RSS_RETA_SIZE_64;
6061         default:
6062                 return ETH_RSS_RETA_SIZE_128;
6063         }
6064 }
6065
6066 uint32_t
6067 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6068         switch (mac_type) {
6069         case ixgbe_mac_X550:
6070         case ixgbe_mac_X550EM_x:
6071                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6072                         return IXGBE_RETA(reta_idx >> 2);
6073                 else
6074                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6075         case ixgbe_mac_X550_vf:
6076         case ixgbe_mac_X550EM_x_vf:
6077                 return IXGBE_VFRETA(reta_idx >> 2);
6078         default:
6079                 return IXGBE_RETA(reta_idx >> 2);
6080         }
6081 }
6082
6083 uint32_t
6084 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6085         switch (mac_type) {
6086         case ixgbe_mac_X550_vf:
6087         case ixgbe_mac_X550EM_x_vf:
6088                 return IXGBE_VFMRQC;
6089         default:
6090                 return IXGBE_MRQC;
6091         }
6092 }
6093
6094 uint32_t
6095 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6096         switch (mac_type) {
6097         case ixgbe_mac_X550_vf:
6098         case ixgbe_mac_X550EM_x_vf:
6099                 return IXGBE_VFRSSRK(i);
6100         default:
6101                 return IXGBE_RSSRK(i);
6102         }
6103 }
6104
6105 bool
6106 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6107         switch (mac_type) {
6108         case ixgbe_mac_82599_vf:
6109         case ixgbe_mac_X540_vf:
6110                 return 0;
6111         default:
6112                 return 1;
6113         }
6114 }
6115
6116 static int
6117 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6118                         struct rte_eth_dcb_info *dcb_info)
6119 {
6120         struct ixgbe_dcb_config *dcb_config =
6121                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6122         struct ixgbe_dcb_tc_config *tc;
6123         uint8_t i, j;
6124
6125         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6126                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6127         else
6128                 dcb_info->nb_tcs = 1;
6129
6130         if (dcb_config->vt_mode) { /* vt is enabled*/
6131                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6132                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6133                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6134                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6135                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6136                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6137                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6138                                                 i * dcb_info->nb_tcs + j;
6139                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6140                                 dcb_info->tc_queue.tc_txq[i][j].base =
6141                                                 i * dcb_info->nb_tcs + j;
6142                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6143                         }
6144                 }
6145         } else { /* vt is disabled*/
6146                 struct rte_eth_dcb_rx_conf *rx_conf =
6147                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6148                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6149                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6150                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6151                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6152                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6153                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6154                         }
6155                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6156                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6157                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6158                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6159                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6160                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6161                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6162                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6163                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6164                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6165                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6166                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6167                         }
6168                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6169                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6170                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6171                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6172                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6173                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6174                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6175                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6176                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6177                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6178                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6179                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6180                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6181                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6182                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6183                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6184                 }
6185         }
6186         for (i = 0; i < dcb_info->nb_tcs; i++) {
6187                 tc = &dcb_config->tc_config[i];
6188                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6189         }
6190         return 0;
6191 }
6192
6193 static struct rte_driver rte_ixgbe_driver = {
6194         .type = PMD_PDEV,
6195         .init = rte_ixgbe_pmd_init,
6196 };
6197
6198 static struct rte_driver rte_ixgbevf_driver = {
6199         .type = PMD_PDEV,
6200         .init = rte_ixgbevf_pmd_init,
6201 };
6202
6203 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6204 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);