drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <rte_ethdev.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIBRTE_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "ixgbe_regs.h"
  49
  50 /*
  51  * High threshold controlling when to start sending XOFF frames. Must be at
  52  * least 8 bytes less than receive packet buffer size. This value is in units
  53  * of 1024 bytes.
  54  */
  55 #define IXGBE_FC_HI    0x80
  56
  57 /*
  58  * Low threshold controlling when to start sending XON frames. This value is
  59  * in units of 1024 bytes.
  60  */
  61 #define IXGBE_FC_LO    0x40
  62
  63 /* Default minimum inter-interrupt interval for EITR configuration */
  64 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  65
  66 /* Timer value included in XOFF frames. */
  67 #define IXGBE_FC_PAUSE 0x680
  68
  69 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  70 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  71 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  72
  73 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  74 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  75 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  76
  77 /*
  78  *  Default values for RX/TX configuration
  79  */
  80 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  81 #define IXGBE_DEFAULT_RX_PTHRESH      8
  82 #define IXGBE_DEFAULT_RX_HTHRESH      8
  83 #define IXGBE_DEFAULT_RX_WTHRESH      0
  84
  85 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  86 #define IXGBE_DEFAULT_TX_PTHRESH      32
  87 #define IXGBE_DEFAULT_TX_HTHRESH      0
  88 #define IXGBE_DEFAULT_TX_WTHRESH      0
  89 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  90
  91 /* Bit shift and mask */
  92 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  93 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  94 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  95 #define IXGBE_8_BIT_MASK   UINT8_MAX
  96
  97 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  98
  99 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 100
 101 #define IXGBE_HKEY_MAX_INDEX 10
 102
 103 /* Additional timesync values. */
 104 #define NSEC_PER_SEC             1000000000L
 105 #define IXGBE_INCVAL_10GB        0x66666666
 106 #define IXGBE_INCVAL_1GB         0x40000000
 107 #define IXGBE_INCVAL_100         0x50000000
 108 #define IXGBE_INCVAL_SHIFT_10GB  28
 109 #define IXGBE_INCVAL_SHIFT_1GB   24
 110 #define IXGBE_INCVAL_SHIFT_100   21
 111 #define IXGBE_INCVAL_SHIFT_82599 7
 112 #define IXGBE_INCPER_SHIFT_82599 24
 113
 114 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 117 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 118 #define DEFAULT_ETAG_ETYPE                     0x893f
 119 #define IXGBE_ETAG_ETYPE                       0x00005084
 120 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 121 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 122 #define IXGBE_RAH_ADTYPE                       0x40000000
 123 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 124 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 125 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 126 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 127 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 128 #define IXGBE_VTEICR_MASK                      0x07
 129
 130 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 131 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 132
 133 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 134 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 140 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 141 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 144 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 152                                 int wait_to_complete);
 153 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 154                                 struct rte_eth_stats *stats);
 155 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_xstat *xstats, unsigned n);
 157 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 158                                   struct rte_eth_xstat *xstats, unsigned n);
 159 static int
 160 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 161                 uint64_t *values, unsigned int n);
 162 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 163 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 164 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 165         struct rte_eth_xstat_name *xstats_names,
 166         unsigned int size);
 167 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 168         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 169 static int ixgbe_dev_xstats_get_names_by_id(
 170         struct rte_eth_dev *dev,
 171         struct rte_eth_xstat_name *xstats_names,
 172         const uint64_t *ids,
 173         unsigned int limit);
 174 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 175                                              uint16_t queue_id,
 176                                              uint8_t stat_idx,
 177                                              uint8_t is_rx);
 178 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 179                                  size_t fw_size);
 180 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 181                                struct rte_eth_dev_info *dev_info);
 182 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 183 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 184                                  struct rte_eth_dev_info *dev_info);
 185 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 186
 187 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 188                 uint16_t vlan_id, int on);
 189 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 190                                enum rte_vlan_type vlan_type,
 191                                uint16_t tpid_id);
 192 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 193                 uint16_t queue, bool on);
 194 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 195                 int on);
 196 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 197 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 199 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 200 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 201
 202 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 203 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 204 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_fc_conf *fc_conf);
 206 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 209                 struct rte_eth_pfc_conf *pfc_conf);
 210 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 211                         struct rte_eth_rss_reta_entry64 *reta_conf,
 212                         uint16_t reta_size);
 213 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 214                         struct rte_eth_rss_reta_entry64 *reta_conf,
 215                         uint16_t reta_size);
 216 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 218 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 222                                       struct rte_intr_handle *handle);
 223 static void ixgbe_dev_interrupt_handler(void *param);
 224 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 226                          uint32_t index, uint32_t pool);
 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 228 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 229                                            struct ether_addr *mac_addr);
 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 231 static bool is_device_supported(struct rte_eth_dev *dev,
 232                                 struct rte_pci_driver *drv);
 233
 234 /* For Virtual Function support */
 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 237 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 238 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 240                                    int wait_to_complete);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr * mac_addr, uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 269 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 270                 struct rte_eth_mirror_conf *mirror_conf,
 271                 uint8_t rule_id, uint8_t on);
 272 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 273                 uint8_t rule_id);
 274 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                           uint16_t queue_id);
 276 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                            uint16_t queue_id);
 278 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 279                                uint8_t queue, uint8_t msix_vector);
 280 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 281
 282 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 283                                 struct ether_addr *mac_addr,
 284                                 uint32_t index, uint32_t pool);
 285 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 286 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 287                                              struct ether_addr *mac_addr);
 288 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 289                         struct rte_eth_syn_filter *filter);
 290 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 291                         enum rte_filter_op filter_op,
 292                         void *arg);
 293 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 294                         struct ixgbe_5tuple_filter *filter);
 295 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 298                                 enum rte_filter_op filter_op,
 299                                 void *arg);
 300 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 301                         struct rte_eth_ntuple_filter *filter);
 302 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 303                                 enum rte_filter_op filter_op,
 304                                 void *arg);
 305 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 306                         struct rte_eth_ethertype_filter *filter);
 307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 308                      enum rte_filter_type filter_type,
 309                      enum rte_filter_op filter_op,
 310                      void *arg);
 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 312
 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 314                                       struct ether_addr *mc_addr_set,
 315                                       uint32_t nb_mc_addr);
 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 317                                    struct rte_eth_dcb_info *dcb_info);
 318
 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 321                             struct rte_dev_reg_info *regs);
 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327
 328 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 329 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 330                                 struct rte_dev_reg_info *regs);
 331
 332 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 333 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 334 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 335                                             struct timespec *timestamp,
 336                                             uint32_t flags);
 337 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 338                                             struct timespec *timestamp);
 339 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 340 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 341                                    struct timespec *timestamp);
 342 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 343                                    const struct timespec *timestamp);
 344 static void ixgbevf_dev_interrupt_handler(void *param);
 345
 346 static int ixgbe_dev_l2_tunnel_eth_type_conf
 347         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 348 static int ixgbe_dev_l2_tunnel_offload_set
 349         (struct rte_eth_dev *dev,
 350          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 351          uint32_t mask,
 352          uint8_t en);
 353 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 354                                              enum rte_filter_op filter_op,
 355                                              void *arg);
 356
 357 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 358                                          struct rte_eth_udp_tunnel *udp_tunnel);
 359 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 360                                          struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 362 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 363
 364 /*
 365  * Define VF Stats MACRO for Non "cleared on read" register
 366  */
 367 #define UPDATE_VF_STAT(reg, last, cur)                          \
 368 {                                                               \
 369         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 370         cur += (latest - last) & UINT_MAX;                      \
 371         last = latest;                                          \
 372 }
 373
 374 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 375 {                                                                \
 376         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 377         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 378         u64 latest = ((new_msb << 32) | new_lsb);                \
 379         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 380         last = latest;                                           \
 381 }
 382
 383 #define IXGBE_SET_HWSTRIP(h, q) do {\
 384                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 385                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 386                 (h)->bitmap[idx] |= 1 << bit;\
 387         } while (0)
 388
 389 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 390                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 391                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 392                 (h)->bitmap[idx] &= ~(1 << bit);\
 393         } while (0)
 394
 395 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 396                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 397                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 398                 (r) = (h)->bitmap[idx] >> bit & 1;\
 399         } while (0)
 400
 401 int ixgbe_logtype_init;
 402 int ixgbe_logtype_driver;
 403
 404 /*
 405  * The set of PCI devices this driver supports
 406  */
 407 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 408         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 456 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 458 #endif
 459         { .vendor_id = 0, /* sentinel */ },
 460 };
 461
 462 /*
 463  * The set of PCI devices this driver supports (for 82599 VF)
 464  */
 465 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 476         { .vendor_id = 0, /* sentinel */ },
 477 };
 478
 479 static const struct rte_eth_desc_lim rx_desc_lim = {
 480         .nb_max = IXGBE_MAX_RING_DESC,
 481         .nb_min = IXGBE_MIN_RING_DESC,
 482         .nb_align = IXGBE_RXD_ALIGN,
 483 };
 484
 485 static const struct rte_eth_desc_lim tx_desc_lim = {
 486         .nb_max = IXGBE_MAX_RING_DESC,
 487         .nb_min = IXGBE_MIN_RING_DESC,
 488         .nb_align = IXGBE_TXD_ALIGN,
 489         .nb_seg_max = IXGBE_TX_MAX_SEG,
 490         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 491 };
 492
 493 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 494         .dev_configure        = ixgbe_dev_configure,
 495         .dev_start            = ixgbe_dev_start,
 496         .dev_stop             = ixgbe_dev_stop,
 497         .dev_set_link_up    = ixgbe_dev_set_link_up,
 498         .dev_set_link_down  = ixgbe_dev_set_link_down,
 499         .dev_close            = ixgbe_dev_close,
 500         .dev_reset            = ixgbe_dev_reset,
 501         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 502         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 503         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 504         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 505         .link_update          = ixgbe_dev_link_update,
 506         .stats_get            = ixgbe_dev_stats_get,
 507         .xstats_get           = ixgbe_dev_xstats_get,
 508         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 509         .stats_reset          = ixgbe_dev_stats_reset,
 510         .xstats_reset         = ixgbe_dev_xstats_reset,
 511         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 512         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 513         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 514         .fw_version_get       = ixgbe_fw_version_get,
 515         .dev_infos_get        = ixgbe_dev_info_get,
 516         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 517         .mtu_set              = ixgbe_dev_mtu_set,
 518         .vlan_filter_set      = ixgbe_vlan_filter_set,
 519         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 520         .vlan_offload_set     = ixgbe_vlan_offload_set,
 521         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 522         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 523         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 524         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 525         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 526         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 527         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 528         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 529         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 530         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 531         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 532         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 533         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 534         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 535         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 536         .dev_led_on           = ixgbe_dev_led_on,
 537         .dev_led_off          = ixgbe_dev_led_off,
 538         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 539         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 540         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 541         .mac_addr_add         = ixgbe_add_rar,
 542         .mac_addr_remove      = ixgbe_remove_rar,
 543         .mac_addr_set         = ixgbe_set_default_mac_addr,
 544         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 545         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 546         .mirror_rule_set      = ixgbe_mirror_rule_set,
 547         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 548         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 549         .reta_update          = ixgbe_dev_rss_reta_update,
 550         .reta_query           = ixgbe_dev_rss_reta_query,
 551         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 552         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 553         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 554         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 555         .rxq_info_get         = ixgbe_rxq_info_get,
 556         .txq_info_get         = ixgbe_txq_info_get,
 557         .timesync_enable      = ixgbe_timesync_enable,
 558         .timesync_disable     = ixgbe_timesync_disable,
 559         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 560         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 561         .get_reg              = ixgbe_get_regs,
 562         .get_eeprom_length    = ixgbe_get_eeprom_length,
 563         .get_eeprom           = ixgbe_get_eeprom,
 564         .set_eeprom           = ixgbe_set_eeprom,
 565         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 566         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 567         .timesync_read_time   = ixgbe_timesync_read_time,
 568         .timesync_write_time  = ixgbe_timesync_write_time,
 569         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 570         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 571         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 572         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 573         .tm_ops_get           = ixgbe_tm_ops_get,
 574 };
 575
 576 /*
 577  * dev_ops for virtual function, bare necessities for basic vf
 578  * operation have been implemented
 579  */
 580 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 581         .dev_configure        = ixgbevf_dev_configure,
 582         .dev_start            = ixgbevf_dev_start,
 583         .dev_stop             = ixgbevf_dev_stop,
 584         .link_update          = ixgbevf_dev_link_update,
 585         .stats_get            = ixgbevf_dev_stats_get,
 586         .xstats_get           = ixgbevf_dev_xstats_get,
 587         .stats_reset          = ixgbevf_dev_stats_reset,
 588         .xstats_reset         = ixgbevf_dev_stats_reset,
 589         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 590         .dev_close            = ixgbevf_dev_close,
 591         .dev_reset            = ixgbevf_dev_reset,
 592         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 593         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 594         .dev_infos_get        = ixgbevf_dev_info_get,
 595         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 596         .mtu_set              = ixgbevf_dev_set_mtu,
 597         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 598         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 599         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 600         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 601         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 602         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 603         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 604         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 605         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 606         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 607         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 608         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 609         .mac_addr_add         = ixgbevf_add_mac_addr,
 610         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 611         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 612         .rxq_info_get         = ixgbe_rxq_info_get,
 613         .txq_info_get         = ixgbe_txq_info_get,
 614         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 615         .get_reg              = ixgbevf_get_regs,
 616         .reta_update          = ixgbe_dev_rss_reta_update,
 617         .reta_query           = ixgbe_dev_rss_reta_query,
 618         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 619         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 620 };
 621
 622 /* store statistics names and its offset in stats structure */
 623 struct rte_ixgbe_xstats_name_off {
 624         char name[RTE_ETH_XSTATS_NAME_SIZE];
 625         unsigned offset;
 626 };
 627
 628 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 629         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 630         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 631         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 632         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 633         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 634         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 635         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 636         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 637         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 638         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 639         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 640         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 641         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 642         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 643         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 644                 prc1023)},
 645         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 646                 prc1522)},
 647         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 648         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 649         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 650         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 651         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 652         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 653         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 654         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 655         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 656         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 657         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 658         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 659         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 660         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 661         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 662         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 663         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 664                 ptc1023)},
 665         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 666                 ptc1522)},
 667         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 668         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 669         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 670         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 671
 672         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 673                 fdirustat_add)},
 674         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 675                 fdirustat_remove)},
 676         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 677                 fdirfstat_fadd)},
 678         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 679                 fdirfstat_fremove)},
 680         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 681                 fdirmatch)},
 682         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 683                 fdirmiss)},
 684
 685         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 686         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 687         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 688                 fclast)},
 689         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 690         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 691         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 692         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 693         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 694                 fcoe_noddp)},
 695         {"rx_fcoe_no_direct_data_placement_ext_buff",
 696                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 697
 698         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 699                 lxontxc)},
 700         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 701                 lxonrxc)},
 702         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 703                 lxofftxc)},
 704         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxoffrxc)},
 706         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 707 };
 708
 709 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 710                            sizeof(rte_ixgbe_stats_strings[0]))
 711
 712 /* MACsec statistics */
 713 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 714         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 715                 out_pkts_untagged)},
 716         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 717                 out_pkts_encrypted)},
 718         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 719                 out_pkts_protected)},
 720         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 721                 out_octets_encrypted)},
 722         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 723                 out_octets_protected)},
 724         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 725                 in_pkts_untagged)},
 726         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_badtag)},
 728         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_nosci)},
 730         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_unknownsci)},
 732         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 733                 in_octets_decrypted)},
 734         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 735                 in_octets_validated)},
 736         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_unchecked)},
 738         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_delayed)},
 740         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_late)},
 742         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_ok)},
 744         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_invalid)},
 746         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_notvalid)},
 748         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_unusedsa)},
 750         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_notusingsa)},
 752 };
 753
 754 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 755                            sizeof(rte_ixgbe_macsec_strings[0]))
 756
 757 /* Per-queue statistics */
 758 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 759         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 760         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 761         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 762         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 763 };
 764
 765 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 766                            sizeof(rte_ixgbe_rxq_strings[0]))
 767 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 768
 769 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 770         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 771         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 772         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 773                 pxon2offc)},
 774 };
 775
 776 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 777                            sizeof(rte_ixgbe_txq_strings[0]))
 778 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 779
 780 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 781         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 782 };
 783
 784 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 785                 sizeof(rte_ixgbevf_stats_strings[0]))
 786
 787 /**
 788  * Atomically reads the link status information from global
 789  * structure rte_eth_dev.
 790  *
 791  * @param dev
 792  *   - Pointer to the structure rte_eth_dev to read from.
 793  *   - Pointer to the buffer to be saved with the link status.
 794  *
 795  * @return
 796  *   - On success, zero.
 797  *   - On failure, negative value.
 798  */
 799 static inline int
 800 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 801                                 struct rte_eth_link *link)
 802 {
 803         struct rte_eth_link *dst = link;
 804         struct rte_eth_link *src = &(dev->data->dev_link);
 805
 806         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 807                                         *(uint64_t *)src) == 0)
 808                 return -1;
 809
 810         return 0;
 811 }
 812
 813 /**
 814  * Atomically writes the link status information into global
 815  * structure rte_eth_dev.
 816  *
 817  * @param dev
 818  *   - Pointer to the structure rte_eth_dev to read from.
 819  *   - Pointer to the buffer to be saved with the link status.
 820  *
 821  * @return
 822  *   - On success, zero.
 823  *   - On failure, negative value.
 824  */
 825 static inline int
 826 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 827                                 struct rte_eth_link *link)
 828 {
 829         struct rte_eth_link *dst = &(dev->data->dev_link);
 830         struct rte_eth_link *src = link;
 831
 832         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 833                                         *(uint64_t *)src) == 0)
 834                 return -1;
 835
 836         return 0;
 837 }
 838
 839 /*
 840  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 841  */
 842 static inline int
 843 ixgbe_is_sfp(struct ixgbe_hw *hw)
 844 {
 845         switch (hw->phy.type) {
 846         case ixgbe_phy_sfp_avago:
 847         case ixgbe_phy_sfp_ftl:
 848         case ixgbe_phy_sfp_intel:
 849         case ixgbe_phy_sfp_unknown:
 850         case ixgbe_phy_sfp_passive_tyco:
 851         case ixgbe_phy_sfp_passive_unknown:
 852                 return 1;
 853         default:
 854                 return 0;
 855         }
 856 }
 857
 858 static inline int32_t
 859 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 860 {
 861         uint32_t ctrl_ext;
 862         int32_t status;
 863
 864         status = ixgbe_reset_hw(hw);
 865
 866         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 867         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 868         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 869         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 870         IXGBE_WRITE_FLUSH(hw);
 871
 872         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 873                 status = IXGBE_SUCCESS;
 874         return status;
 875 }
 876
 877 static inline void
 878 ixgbe_enable_intr(struct rte_eth_dev *dev)
 879 {
 880         struct ixgbe_interrupt *intr =
 881                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 882         struct ixgbe_hw *hw =
 883                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 884
 885         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 886         IXGBE_WRITE_FLUSH(hw);
 887 }
 888
 889 /*
 890  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 891  */
 892 static void
 893 ixgbe_disable_intr(struct ixgbe_hw *hw)
 894 {
 895         PMD_INIT_FUNC_TRACE();
 896
 897         if (hw->mac.type == ixgbe_mac_82598EB) {
 898                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 899         } else {
 900                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 901                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 902                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 903         }
 904         IXGBE_WRITE_FLUSH(hw);
 905 }
 906
 907 /*
 908  * This function resets queue statistics mapping registers.
 909  * From Niantic datasheet, Initialization of Statistics section:
 910  * "...if software requires the queue counters, the RQSMR and TQSM registers
 911  * must be re-programmed following a device reset.
 912  */
 913 static void
 914 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 915 {
 916         uint32_t i;
 917
 918         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 919                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 920                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 921         }
 922 }
 923
 924
 925 static int
 926 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 927                                   uint16_t queue_id,
 928                                   uint8_t stat_idx,
 929                                   uint8_t is_rx)
 930 {
 931 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 932 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 933 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 934
 935         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 936         struct ixgbe_stat_mapping_registers *stat_mappings =
 937                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 938         uint32_t qsmr_mask = 0;
 939         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 940         uint32_t q_map;
 941         uint8_t n, offset;
 942
 943         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 944                 (hw->mac.type != ixgbe_mac_X540) &&
 945                 (hw->mac.type != ixgbe_mac_X550) &&
 946                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 947                 (hw->mac.type != ixgbe_mac_X550EM_a))
 948                 return -ENOSYS;
 949
 950         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 951                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 952                      queue_id, stat_idx);
 953
 954         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 955         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 956                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 957                 return -EIO;
 958         }
 959         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 960
 961         /* Now clear any previous stat_idx set */
 962         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 963         if (!is_rx)
 964                 stat_mappings->tqsm[n] &= ~clearing_mask;
 965         else
 966                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 967
 968         q_map = (uint32_t)stat_idx;
 969         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 970         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 971         if (!is_rx)
 972                 stat_mappings->tqsm[n] |= qsmr_mask;
 973         else
 974                 stat_mappings->rqsmr[n] |= qsmr_mask;
 975
 976         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 977                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 978                      queue_id, stat_idx);
 979         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 980                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 981
 982         /* Now write the mapping in the appropriate register */
 983         if (is_rx) {
 984                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 985                              stat_mappings->rqsmr[n], n);
 986                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 987         } else {
 988                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 989                              stat_mappings->tqsm[n], n);
 990                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 991         }
 992         return 0;
 993 }
 994
 995 static void
 996 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 997 {
 998         struct ixgbe_stat_mapping_registers *stat_mappings =
 999                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1001         int i;
1002
1003         /* write whatever was in stat mapping table to the NIC */
1004         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1005                 /* rx */
1006                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1007
1008                 /* tx */
1009                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1010         }
1011 }
1012
1013 static void
1014 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1015 {
1016         uint8_t i;
1017         struct ixgbe_dcb_tc_config *tc;
1018         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1019
1020         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1021         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1022         for (i = 0; i < dcb_max_tc; i++) {
1023                 tc = &dcb_config->tc_config[i];
1024                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1025                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1026                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1027                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1028                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1029                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1030                 tc->pfc = ixgbe_dcb_pfc_disabled;
1031         }
1032
1033         /* Initialize default user to priority mapping, UPx->TC0 */
1034         tc = &dcb_config->tc_config[0];
1035         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1036         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1037         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1038                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1039                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1040         }
1041         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1042         dcb_config->pfc_mode_enable = false;
1043         dcb_config->vt_mode = true;
1044         dcb_config->round_robin_enable = false;
1045         /* support all DCB capabilities in 82599 */
1046         dcb_config->support.capabilities = 0xFF;
1047
1048         /*we only support 4 Tcs for X540, X550 */
1049         if (hw->mac.type == ixgbe_mac_X540 ||
1050                 hw->mac.type == ixgbe_mac_X550 ||
1051                 hw->mac.type == ixgbe_mac_X550EM_x ||
1052                 hw->mac.type == ixgbe_mac_X550EM_a) {
1053                 dcb_config->num_tcs.pg_tcs = 4;
1054                 dcb_config->num_tcs.pfc_tcs = 4;
1055         }
1056 }
1057
1058 /*
1059  * Ensure that all locks are released before first NVM or PHY access
1060  */
1061 static void
1062 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1063 {
1064         uint16_t mask;
1065
1066         /*
1067          * Phy lock should not fail in this early stage. If this is the case,
1068          * it is due to an improper exit of the application.
1069          * So force the release of the faulty lock. Release of common lock
1070          * is done automatically by swfw_sync function.
1071          */
1072         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1073         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1074                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1075         }
1076         ixgbe_release_swfw_semaphore(hw, mask);
1077
1078         /*
1079          * These ones are more tricky since they are common to all ports; but
1080          * swfw_sync retries last long enough (1s) to be almost sure that if
1081          * lock can not be taken it is due to an improper lock of the
1082          * semaphore.
1083          */
1084         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1085         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1086                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1087         }
1088         ixgbe_release_swfw_semaphore(hw, mask);
1089 }
1090
1091 /*
1092  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1093  * It returns 0 on success.
1094  */
1095 static int
1096 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1097 {
1098         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1099         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1100         struct ixgbe_hw *hw =
1101                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1102         struct ixgbe_vfta *shadow_vfta =
1103                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1104         struct ixgbe_hwstrip *hwstrip =
1105                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1106         struct ixgbe_dcb_config *dcb_config =
1107                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1108         struct ixgbe_filter_info *filter_info =
1109                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1110         struct ixgbe_bw_conf *bw_conf =
1111                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1112         uint32_t ctrl_ext;
1113         uint16_t csum;
1114         int diag, i;
1115
1116         PMD_INIT_FUNC_TRACE();
1117
1118         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1119         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1120         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1121         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1122
1123         /*
1124          * For secondary processes, we don't initialise any further as primary
1125          * has already done this work. Only check we don't need a different
1126          * RX and TX function.
1127          */
1128         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1129                 struct ixgbe_tx_queue *txq;
1130                 /* TX queue function in primary, set by last queue initialized
1131                  * Tx queue may not initialized by primary process
1132                  */
1133                 if (eth_dev->data->tx_queues) {
1134                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1135                         ixgbe_set_tx_function(eth_dev, txq);
1136                 } else {
1137                         /* Use default TX function if we get here */
1138                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1139                                      "Using default TX function.");
1140                 }
1141
1142                 ixgbe_set_rx_function(eth_dev);
1143
1144                 return 0;
1145         }
1146
1147 #ifdef RTE_LIBRTE_SECURITY
1148         /* Initialize security_ctx only for primary process*/
1149         eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1150         if (eth_dev->security_ctx == NULL)
1151                 return -ENOMEM;
1152 #endif
1153
1154         rte_eth_copy_pci_info(eth_dev, pci_dev);
1155
1156         /* Vendor and Device ID need to be set before init of shared code */
1157         hw->device_id = pci_dev->id.device_id;
1158         hw->vendor_id = pci_dev->id.vendor_id;
1159         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1160         hw->allow_unsupported_sfp = 1;
1161
1162         /* Initialize the shared code (base driver) */
1163 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1164         diag = ixgbe_bypass_init_shared_code(hw);
1165 #else
1166         diag = ixgbe_init_shared_code(hw);
1167 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1168
1169         if (diag != IXGBE_SUCCESS) {
1170                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1171                 return -EIO;
1172         }
1173
1174         /* pick up the PCI bus settings for reporting later */
1175         ixgbe_get_bus_info(hw);
1176
1177         /* Unlock any pending hardware semaphore */
1178         ixgbe_swfw_lock_reset(hw);
1179
1180         /* Initialize DCB configuration*/
1181         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1182         ixgbe_dcb_init(hw, dcb_config);
1183         /* Get Hardware Flow Control setting */
1184         hw->fc.requested_mode = ixgbe_fc_full;
1185         hw->fc.current_mode = ixgbe_fc_full;
1186         hw->fc.pause_time = IXGBE_FC_PAUSE;
1187         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1188                 hw->fc.low_water[i] = IXGBE_FC_LO;
1189                 hw->fc.high_water[i] = IXGBE_FC_HI;
1190         }
1191         hw->fc.send_xon = 1;
1192
1193         /* Make sure we have a good EEPROM before we read from it */
1194         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1195         if (diag != IXGBE_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1197                 return -EIO;
1198         }
1199
1200 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1201         diag = ixgbe_bypass_init_hw(hw);
1202 #else
1203         diag = ixgbe_init_hw(hw);
1204 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1205
1206         /*
1207          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1208          * is called too soon after the kernel driver unbinding/binding occurs.
1209          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1210          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1211          * also called. See ixgbe_identify_phy_82599(). The reason for the
1212          * failure is not known, and only occuts when virtualisation features
1213          * are disabled in the bios. A delay of 100ms  was found to be enough by
1214          * trial-and-error, and is doubled to be safe.
1215          */
1216         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1217                 rte_delay_ms(200);
1218                 diag = ixgbe_init_hw(hw);
1219         }
1220
1221         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1222                 diag = IXGBE_SUCCESS;
1223
1224         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1225                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1226                              "LOM.  Please be aware there may be issues associated "
1227                              "with your hardware.");
1228                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1229                              "please contact your Intel or hardware representative "
1230                              "who provided you with this hardware.");
1231         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1232                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1233         if (diag) {
1234                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1235                 return -EIO;
1236         }
1237
1238         /* Reset the hw statistics */
1239         ixgbe_dev_stats_reset(eth_dev);
1240
1241         /* disable interrupt */
1242         ixgbe_disable_intr(hw);
1243
1244         /* reset mappings for queue statistics hw counters*/
1245         ixgbe_reset_qstat_mappings(hw);
1246
1247         /* Allocate memory for storing MAC addresses */
1248         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1249                                                hw->mac.num_rar_entries, 0);
1250         if (eth_dev->data->mac_addrs == NULL) {
1251                 PMD_INIT_LOG(ERR,
1252                              "Failed to allocate %u bytes needed to store "
1253                              "MAC addresses",
1254                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1255                 return -ENOMEM;
1256         }
1257         /* Copy the permanent MAC address */
1258         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1259                         &eth_dev->data->mac_addrs[0]);
1260
1261         /* Allocate memory for storing hash filter MAC addresses */
1262         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1263                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1264         if (eth_dev->data->hash_mac_addrs == NULL) {
1265                 PMD_INIT_LOG(ERR,
1266                              "Failed to allocate %d bytes needed to store MAC addresses",
1267                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1268                 return -ENOMEM;
1269         }
1270
1271         /* initialize the vfta */
1272         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1273
1274         /* initialize the hw strip bitmap*/
1275         memset(hwstrip, 0, sizeof(*hwstrip));
1276
1277         /* initialize PF if max_vfs not zero */
1278         ixgbe_pf_host_init(eth_dev);
1279
1280         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1281         /* let hardware know driver is loaded */
1282         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1283         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1284         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1285         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1286         IXGBE_WRITE_FLUSH(hw);
1287
1288         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1289                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1290                              (int) hw->mac.type, (int) hw->phy.type,
1291                              (int) hw->phy.sfp_type);
1292         else
1293                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1294                              (int) hw->mac.type, (int) hw->phy.type);
1295
1296         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1297                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1298                      pci_dev->id.device_id);
1299
1300         rte_intr_callback_register(intr_handle,
1301                                    ixgbe_dev_interrupt_handler, eth_dev);
1302
1303         /* enable uio/vfio intr/eventfd mapping */
1304         rte_intr_enable(intr_handle);
1305
1306         /* enable support intr */
1307         ixgbe_enable_intr(eth_dev);
1308
1309         /* initialize filter info */
1310         memset(filter_info, 0,
1311                sizeof(struct ixgbe_filter_info));
1312
1313         /* initialize 5tuple filter list */
1314         TAILQ_INIT(&filter_info->fivetuple_list);
1315
1316         /* initialize flow director filter list & hash */
1317         ixgbe_fdir_filter_init(eth_dev);
1318
1319         /* initialize l2 tunnel filter list & hash */
1320         ixgbe_l2_tn_filter_init(eth_dev);
1321
1322         /* initialize flow filter lists */
1323         ixgbe_filterlist_init();
1324
1325         /* initialize bandwidth configuration info */
1326         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1327
1328         /* initialize Traffic Manager configuration */
1329         ixgbe_tm_conf_init(eth_dev);
1330
1331         return 0;
1332 }
1333
1334 static int
1335 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1336 {
1337         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1338         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1339         struct ixgbe_hw *hw;
1340
1341         PMD_INIT_FUNC_TRACE();
1342
1343         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1344                 return -EPERM;
1345
1346         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1347
1348         if (hw->adapter_stopped == 0)
1349                 ixgbe_dev_close(eth_dev);
1350
1351         eth_dev->dev_ops = NULL;
1352         eth_dev->rx_pkt_burst = NULL;
1353         eth_dev->tx_pkt_burst = NULL;
1354
1355         /* Unlock any pending hardware semaphore */
1356         ixgbe_swfw_lock_reset(hw);
1357
1358         /* disable uio intr before callback unregister */
1359         rte_intr_disable(intr_handle);
1360         rte_intr_callback_unregister(intr_handle,
1361                                      ixgbe_dev_interrupt_handler, eth_dev);
1362
1363         /* uninitialize PF if max_vfs not zero */
1364         ixgbe_pf_host_uninit(eth_dev);
1365
1366         rte_free(eth_dev->data->mac_addrs);
1367         eth_dev->data->mac_addrs = NULL;
1368
1369         rte_free(eth_dev->data->hash_mac_addrs);
1370         eth_dev->data->hash_mac_addrs = NULL;
1371
1372         /* remove all the fdir filters & hash */
1373         ixgbe_fdir_filter_uninit(eth_dev);
1374
1375         /* remove all the L2 tunnel filters & hash */
1376         ixgbe_l2_tn_filter_uninit(eth_dev);
1377
1378         /* Remove all ntuple filters of the device */
1379         ixgbe_ntuple_filter_uninit(eth_dev);
1380
1381         /* clear all the filters list */
1382         ixgbe_filterlist_flush();
1383
1384         /* Remove all Traffic Manager configuration */
1385         ixgbe_tm_conf_uninit(eth_dev);
1386
1387 #ifdef RTE_LIBRTE_SECURITY
1388         rte_free(eth_dev->security_ctx);
1389 #endif
1390
1391         return 0;
1392 }
1393
1394 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1395 {
1396         struct ixgbe_filter_info *filter_info =
1397                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1398         struct ixgbe_5tuple_filter *p_5tuple;
1399
1400         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1401                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1402                              p_5tuple,
1403                              entries);
1404                 rte_free(p_5tuple);
1405         }
1406         memset(filter_info->fivetuple_mask, 0,
1407                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1408
1409         return 0;
1410 }
1411
1412 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1413 {
1414         struct ixgbe_hw_fdir_info *fdir_info =
1415                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1416         struct ixgbe_fdir_filter *fdir_filter;
1417
1418                 if (fdir_info->hash_map)
1419                 rte_free(fdir_info->hash_map);
1420         if (fdir_info->hash_handle)
1421                 rte_hash_free(fdir_info->hash_handle);
1422
1423         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1424                 TAILQ_REMOVE(&fdir_info->fdir_list,
1425                              fdir_filter,
1426                              entries);
1427                 rte_free(fdir_filter);
1428         }
1429
1430         return 0;
1431 }
1432
1433 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1434 {
1435         struct ixgbe_l2_tn_info *l2_tn_info =
1436                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1437         struct ixgbe_l2_tn_filter *l2_tn_filter;
1438
1439         if (l2_tn_info->hash_map)
1440                 rte_free(l2_tn_info->hash_map);
1441         if (l2_tn_info->hash_handle)
1442                 rte_hash_free(l2_tn_info->hash_handle);
1443
1444         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1445                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1446                              l2_tn_filter,
1447                              entries);
1448                 rte_free(l2_tn_filter);
1449         }
1450
1451         return 0;
1452 }
1453
1454 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1455 {
1456         struct ixgbe_hw_fdir_info *fdir_info =
1457                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1458         char fdir_hash_name[RTE_HASH_NAMESIZE];
1459         struct rte_hash_parameters fdir_hash_params = {
1460                 .name = fdir_hash_name,
1461                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1462                 .key_len = sizeof(union ixgbe_atr_input),
1463                 .hash_func = rte_hash_crc,
1464                 .hash_func_init_val = 0,
1465                 .socket_id = rte_socket_id(),
1466         };
1467
1468         TAILQ_INIT(&fdir_info->fdir_list);
1469         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1470                  "fdir_%s", eth_dev->device->name);
1471         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1472         if (!fdir_info->hash_handle) {
1473                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1474                 return -EINVAL;
1475         }
1476         fdir_info->hash_map = rte_zmalloc("ixgbe",
1477                                           sizeof(struct ixgbe_fdir_filter *) *
1478                                           IXGBE_MAX_FDIR_FILTER_NUM,
1479                                           0);
1480         if (!fdir_info->hash_map) {
1481                 PMD_INIT_LOG(ERR,
1482                              "Failed to allocate memory for fdir hash map!");
1483                 return -ENOMEM;
1484         }
1485         fdir_info->mask_added = FALSE;
1486
1487         return 0;
1488 }
1489
1490 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1491 {
1492         struct ixgbe_l2_tn_info *l2_tn_info =
1493                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1494         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1495         struct rte_hash_parameters l2_tn_hash_params = {
1496                 .name = l2_tn_hash_name,
1497                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1498                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1499                 .hash_func = rte_hash_crc,
1500                 .hash_func_init_val = 0,
1501                 .socket_id = rte_socket_id(),
1502         };
1503
1504         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1505         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1506                  "l2_tn_%s", eth_dev->device->name);
1507         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1508         if (!l2_tn_info->hash_handle) {
1509                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1510                 return -EINVAL;
1511         }
1512         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1513                                    sizeof(struct ixgbe_l2_tn_filter *) *
1514                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1515                                    0);
1516         if (!l2_tn_info->hash_map) {
1517                 PMD_INIT_LOG(ERR,
1518                         "Failed to allocate memory for L2 TN hash map!");
1519                 return -ENOMEM;
1520         }
1521         l2_tn_info->e_tag_en = FALSE;
1522         l2_tn_info->e_tag_fwd_en = FALSE;
1523         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1524
1525         return 0;
1526 }
1527 /*
1528  * Negotiate mailbox API version with the PF.
1529  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1530  * Then we try to negotiate starting with the most recent one.
1531  * If all negotiation attempts fail, then we will proceed with
1532  * the default one (ixgbe_mbox_api_10).
1533  */
1534 static void
1535 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1536 {
1537         int32_t i;
1538
1539         /* start with highest supported, proceed down */
1540         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1541                 ixgbe_mbox_api_12,
1542                 ixgbe_mbox_api_11,
1543                 ixgbe_mbox_api_10,
1544         };
1545
1546         for (i = 0;
1547                         i != RTE_DIM(sup_ver) &&
1548                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1549                         i++)
1550                 ;
1551 }
1552
1553 static void
1554 generate_random_mac_addr(struct ether_addr *mac_addr)
1555 {
1556         uint64_t random;
1557
1558         /* Set Organizationally Unique Identifier (OUI) prefix. */
1559         mac_addr->addr_bytes[0] = 0x00;
1560         mac_addr->addr_bytes[1] = 0x09;
1561         mac_addr->addr_bytes[2] = 0xC0;
1562         /* Force indication of locally assigned MAC address. */
1563         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1564         /* Generate the last 3 bytes of the MAC address with a random number. */
1565         random = rte_rand();
1566         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1567 }
1568
1569 /*
1570  * Virtual Function device init
1571  */
1572 static int
1573 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1574 {
1575         int diag;
1576         uint32_t tc, tcs;
1577         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1578         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1579         struct ixgbe_hw *hw =
1580                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1581         struct ixgbe_vfta *shadow_vfta =
1582                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1583         struct ixgbe_hwstrip *hwstrip =
1584                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1585         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1586
1587         PMD_INIT_FUNC_TRACE();
1588
1589         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1590         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1591         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1592
1593         /* for secondary processes, we don't initialise any further as primary
1594          * has already done this work. Only check we don't need a different
1595          * RX function
1596          */
1597         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1598                 struct ixgbe_tx_queue *txq;
1599                 /* TX queue function in primary, set by last queue initialized
1600                  * Tx queue may not initialized by primary process
1601                  */
1602                 if (eth_dev->data->tx_queues) {
1603                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1604                         ixgbe_set_tx_function(eth_dev, txq);
1605                 } else {
1606                         /* Use default TX function if we get here */
1607                         PMD_INIT_LOG(NOTICE,
1608                                      "No TX queues configured yet. Using default TX function.");
1609                 }
1610
1611                 ixgbe_set_rx_function(eth_dev);
1612
1613                 return 0;
1614         }
1615
1616         rte_eth_copy_pci_info(eth_dev, pci_dev);
1617
1618         hw->device_id = pci_dev->id.device_id;
1619         hw->vendor_id = pci_dev->id.vendor_id;
1620         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1621
1622         /* initialize the vfta */
1623         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1624
1625         /* initialize the hw strip bitmap*/
1626         memset(hwstrip, 0, sizeof(*hwstrip));
1627
1628         /* Initialize the shared code (base driver) */
1629         diag = ixgbe_init_shared_code(hw);
1630         if (diag != IXGBE_SUCCESS) {
1631                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1632                 return -EIO;
1633         }
1634
1635         /* init_mailbox_params */
1636         hw->mbx.ops.init_params(hw);
1637
1638         /* Reset the hw statistics */
1639         ixgbevf_dev_stats_reset(eth_dev);
1640
1641         /* Disable the interrupts for VF */
1642         ixgbevf_intr_disable(hw);
1643
1644         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1645         diag = hw->mac.ops.reset_hw(hw);
1646
1647         /*
1648          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1649          * the underlying PF driver has not assigned a MAC address to the VF.
1650          * In this case, assign a random MAC address.
1651          */
1652         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1653                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1654                 return diag;
1655         }
1656
1657         /* negotiate mailbox API version to use with the PF. */
1658         ixgbevf_negotiate_api(hw);
1659
1660         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1661         ixgbevf_get_queues(hw, &tcs, &tc);
1662
1663         /* Allocate memory for storing MAC addresses */
1664         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1665                                                hw->mac.num_rar_entries, 0);
1666         if (eth_dev->data->mac_addrs == NULL) {
1667                 PMD_INIT_LOG(ERR,
1668                              "Failed to allocate %u bytes needed to store "
1669                              "MAC addresses",
1670                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1671                 return -ENOMEM;
1672         }
1673
1674         /* Generate a random MAC address, if none was assigned by PF. */
1675         if (is_zero_ether_addr(perm_addr)) {
1676                 generate_random_mac_addr(perm_addr);
1677                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1678                 if (diag) {
1679                         rte_free(eth_dev->data->mac_addrs);
1680                         eth_dev->data->mac_addrs = NULL;
1681                         return diag;
1682                 }
1683                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1684                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1685                              "%02x:%02x:%02x:%02x:%02x:%02x",
1686                              perm_addr->addr_bytes[0],
1687                              perm_addr->addr_bytes[1],
1688                              perm_addr->addr_bytes[2],
1689                              perm_addr->addr_bytes[3],
1690                              perm_addr->addr_bytes[4],
1691                              perm_addr->addr_bytes[5]);
1692         }
1693
1694         /* Copy the permanent MAC address */
1695         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1696
1697         /* reset the hardware with the new settings */
1698         diag = hw->mac.ops.start_hw(hw);
1699         switch (diag) {
1700         case  0:
1701                 break;
1702
1703         default:
1704                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1705                 return -EIO;
1706         }
1707
1708         rte_intr_callback_register(intr_handle,
1709                                    ixgbevf_dev_interrupt_handler, eth_dev);
1710         rte_intr_enable(intr_handle);
1711         ixgbevf_intr_enable(hw);
1712
1713         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1714                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1715                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1716
1717         return 0;
1718 }
1719
1720 /* Virtual Function device uninit */
1721
1722 static int
1723 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1724 {
1725         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1726         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1727         struct ixgbe_hw *hw;
1728
1729         PMD_INIT_FUNC_TRACE();
1730
1731         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1732                 return -EPERM;
1733
1734         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1735
1736         if (hw->adapter_stopped == 0)
1737                 ixgbevf_dev_close(eth_dev);
1738
1739         eth_dev->dev_ops = NULL;
1740         eth_dev->rx_pkt_burst = NULL;
1741         eth_dev->tx_pkt_burst = NULL;
1742
1743         /* Disable the interrupts for VF */
1744         ixgbevf_intr_disable(hw);
1745
1746         rte_free(eth_dev->data->mac_addrs);
1747         eth_dev->data->mac_addrs = NULL;
1748
1749         rte_intr_disable(intr_handle);
1750         rte_intr_callback_unregister(intr_handle,
1751                                      ixgbevf_dev_interrupt_handler, eth_dev);
1752
1753         return 0;
1754 }
1755
1756 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1757         struct rte_pci_device *pci_dev)
1758 {
1759         return rte_eth_dev_pci_generic_probe(pci_dev,
1760                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1761 }
1762
1763 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1764 {
1765         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1766 }
1767
1768 static struct rte_pci_driver rte_ixgbe_pmd = {
1769         .id_table = pci_id_ixgbe_map,
1770         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1771                      RTE_PCI_DRV_IOVA_AS_VA,
1772         .probe = eth_ixgbe_pci_probe,
1773         .remove = eth_ixgbe_pci_remove,
1774 };
1775
1776 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1777         struct rte_pci_device *pci_dev)
1778 {
1779         return rte_eth_dev_pci_generic_probe(pci_dev,
1780                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1781 }
1782
1783 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1784 {
1785         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1786 }
1787
1788 /*
1789  * virtual function driver struct
1790  */
1791 static struct rte_pci_driver rte_ixgbevf_pmd = {
1792         .id_table = pci_id_ixgbevf_map,
1793         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1794         .probe = eth_ixgbevf_pci_probe,
1795         .remove = eth_ixgbevf_pci_remove,
1796 };
1797
1798 static int
1799 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1800 {
1801         struct ixgbe_hw *hw =
1802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803         struct ixgbe_vfta *shadow_vfta =
1804                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1805         uint32_t vfta;
1806         uint32_t vid_idx;
1807         uint32_t vid_bit;
1808
1809         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1810         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1811         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1812         if (on)
1813                 vfta |= vid_bit;
1814         else
1815                 vfta &= ~vid_bit;
1816         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1817
1818         /* update local VFTA copy */
1819         shadow_vfta->vfta[vid_idx] = vfta;
1820
1821         return 0;
1822 }
1823
1824 static void
1825 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1826 {
1827         if (on)
1828                 ixgbe_vlan_hw_strip_enable(dev, queue);
1829         else
1830                 ixgbe_vlan_hw_strip_disable(dev, queue);
1831 }
1832
1833 static int
1834 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1835                     enum rte_vlan_type vlan_type,
1836                     uint16_t tpid)
1837 {
1838         struct ixgbe_hw *hw =
1839                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         int ret = 0;
1841         uint32_t reg;
1842         uint32_t qinq;
1843
1844         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1845         qinq &= IXGBE_DMATXCTL_GDV;
1846
1847         switch (vlan_type) {
1848         case ETH_VLAN_TYPE_INNER:
1849                 if (qinq) {
1850                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1851                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1852                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1853                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1854                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1855                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1856                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1857                 } else {
1858                         ret = -ENOTSUP;
1859                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1860                                     " by single VLAN");
1861                 }
1862                 break;
1863         case ETH_VLAN_TYPE_OUTER:
1864                 if (qinq) {
1865                         /* Only the high 16-bits is valid */
1866                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1867                                         IXGBE_EXVET_VET_EXT_SHIFT);
1868                 } else {
1869                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1870                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1871                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1872                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1873                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1874                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1875                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1876                 }
1877
1878                 break;
1879         default:
1880                 ret = -EINVAL;
1881                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1882                 break;
1883         }
1884
1885         return ret;
1886 }
1887
1888 void
1889 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1890 {
1891         struct ixgbe_hw *hw =
1892                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1893         uint32_t vlnctrl;
1894
1895         PMD_INIT_FUNC_TRACE();
1896
1897         /* Filter Table Disable */
1898         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1899         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1900
1901         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1902 }
1903
1904 void
1905 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1906 {
1907         struct ixgbe_hw *hw =
1908                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct ixgbe_vfta *shadow_vfta =
1910                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1911         uint32_t vlnctrl;
1912         uint16_t i;
1913
1914         PMD_INIT_FUNC_TRACE();
1915
1916         /* Filter Table Enable */
1917         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1918         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1919         vlnctrl |= IXGBE_VLNCTRL_VFE;
1920
1921         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1922
1923         /* write whatever is in local vfta copy */
1924         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1925                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1926 }
1927
1928 static void
1929 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1930 {
1931         struct ixgbe_hwstrip *hwstrip =
1932                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1933         struct ixgbe_rx_queue *rxq;
1934
1935         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1936                 return;
1937
1938         if (on)
1939                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1940         else
1941                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1942
1943         if (queue >= dev->data->nb_rx_queues)
1944                 return;
1945
1946         rxq = dev->data->rx_queues[queue];
1947
1948         if (on)
1949                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1950         else
1951                 rxq->vlan_flags = PKT_RX_VLAN;
1952 }
1953
1954 static void
1955 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1956 {
1957         struct ixgbe_hw *hw =
1958                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959         uint32_t ctrl;
1960
1961         PMD_INIT_FUNC_TRACE();
1962
1963         if (hw->mac.type == ixgbe_mac_82598EB) {
1964                 /* No queue level support */
1965                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1966                 return;
1967         }
1968
1969         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1970         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1971         ctrl &= ~IXGBE_RXDCTL_VME;
1972         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1973
1974         /* record those setting for HW strip per queue */
1975         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1976 }
1977
1978 static void
1979 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1980 {
1981         struct ixgbe_hw *hw =
1982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983         uint32_t ctrl;
1984
1985         PMD_INIT_FUNC_TRACE();
1986
1987         if (hw->mac.type == ixgbe_mac_82598EB) {
1988                 /* No queue level supported */
1989                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1990                 return;
1991         }
1992
1993         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1994         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1995         ctrl |= IXGBE_RXDCTL_VME;
1996         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1997
1998         /* record those setting for HW strip per queue */
1999         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2000 }
2001
2002 void
2003 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2004 {
2005         struct ixgbe_hw *hw =
2006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2007         uint32_t ctrl;
2008         uint16_t i;
2009         struct ixgbe_rx_queue *rxq;
2010
2011         PMD_INIT_FUNC_TRACE();
2012
2013         if (hw->mac.type == ixgbe_mac_82598EB) {
2014                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2015                 ctrl &= ~IXGBE_VLNCTRL_VME;
2016                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2017         } else {
2018                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2019                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2020                         rxq = dev->data->rx_queues[i];
2021                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2022                         ctrl &= ~IXGBE_RXDCTL_VME;
2023                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2024
2025                         /* record those setting for HW strip per queue */
2026                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2027                 }
2028         }
2029 }
2030
2031 void
2032 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2033 {
2034         struct ixgbe_hw *hw =
2035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         uint32_t ctrl;
2037         uint16_t i;
2038         struct ixgbe_rx_queue *rxq;
2039
2040         PMD_INIT_FUNC_TRACE();
2041
2042         if (hw->mac.type == ixgbe_mac_82598EB) {
2043                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2044                 ctrl |= IXGBE_VLNCTRL_VME;
2045                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2046         } else {
2047                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2048                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2049                         rxq = dev->data->rx_queues[i];
2050                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2051                         ctrl |= IXGBE_RXDCTL_VME;
2052                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2053
2054                         /* record those setting for HW strip per queue */
2055                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2056                 }
2057         }
2058 }
2059
2060 static void
2061 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2062 {
2063         struct ixgbe_hw *hw =
2064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         uint32_t ctrl;
2066
2067         PMD_INIT_FUNC_TRACE();
2068
2069         /* DMATXCTRL: Geric Double VLAN Disable */
2070         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2071         ctrl &= ~IXGBE_DMATXCTL_GDV;
2072         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2073
2074         /* CTRL_EXT: Global Double VLAN Disable */
2075         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2076         ctrl &= ~IXGBE_EXTENDED_VLAN;
2077         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2078
2079 }
2080
2081 static void
2082 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2083 {
2084         struct ixgbe_hw *hw =
2085                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2086         uint32_t ctrl;
2087
2088         PMD_INIT_FUNC_TRACE();
2089
2090         /* DMATXCTRL: Geric Double VLAN Enable */
2091         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2092         ctrl |= IXGBE_DMATXCTL_GDV;
2093         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2094
2095         /* CTRL_EXT: Global Double VLAN Enable */
2096         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2097         ctrl |= IXGBE_EXTENDED_VLAN;
2098         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2099
2100         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2101         if (hw->mac.type == ixgbe_mac_X550 ||
2102             hw->mac.type == ixgbe_mac_X550EM_x ||
2103             hw->mac.type == ixgbe_mac_X550EM_a) {
2104                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2105                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2106                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2107         }
2108
2109         /*
2110          * VET EXT field in the EXVET register = 0x8100 by default
2111          * So no need to change. Same to VT field of DMATXCTL register
2112          */
2113 }
2114
2115 static int
2116 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2117 {
2118         if (mask & ETH_VLAN_STRIP_MASK) {
2119                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2120                         ixgbe_vlan_hw_strip_enable_all(dev);
2121                 else
2122                         ixgbe_vlan_hw_strip_disable_all(dev);
2123         }
2124
2125         if (mask & ETH_VLAN_FILTER_MASK) {
2126                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2127                         ixgbe_vlan_hw_filter_enable(dev);
2128                 else
2129                         ixgbe_vlan_hw_filter_disable(dev);
2130         }
2131
2132         if (mask & ETH_VLAN_EXTEND_MASK) {
2133                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2134                         ixgbe_vlan_hw_extend_enable(dev);
2135                 else
2136                         ixgbe_vlan_hw_extend_disable(dev);
2137         }
2138
2139         return 0;
2140 }
2141
2142 static void
2143 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2144 {
2145         struct ixgbe_hw *hw =
2146                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2147         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2148         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2149
2150         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2151         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2152 }
2153
2154 static int
2155 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2156 {
2157         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2158
2159         switch (nb_rx_q) {
2160         case 1:
2161         case 2:
2162                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2163                 break;
2164         case 4:
2165                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2166                 break;
2167         default:
2168                 return -EINVAL;
2169         }
2170
2171         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2172         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2173
2174         return 0;
2175 }
2176
2177 static int
2178 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2179 {
2180         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2181         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2183         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2184
2185         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2186                 /* check multi-queue mode */
2187                 switch (dev_conf->rxmode.mq_mode) {
2188                 case ETH_MQ_RX_VMDQ_DCB:
2189                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2190                         break;
2191                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2192                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2193                         PMD_INIT_LOG(ERR, "SRIOV active,"
2194                                         " unsupported mq_mode rx %d.",
2195                                         dev_conf->rxmode.mq_mode);
2196                         return -EINVAL;
2197                 case ETH_MQ_RX_RSS:
2198                 case ETH_MQ_RX_VMDQ_RSS:
2199                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2200                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2201                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2202                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2203                                                 " invalid queue number"
2204                                                 " for VMDQ RSS, allowed"
2205                                                 " value are 1, 2 or 4.");
2206                                         return -EINVAL;
2207                                 }
2208                         break;
2209                 case ETH_MQ_RX_VMDQ_ONLY:
2210                 case ETH_MQ_RX_NONE:
2211                         /* if nothing mq mode configure, use default scheme */
2212                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2213                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2214                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2215                         break;
2216                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2217                         /* SRIOV only works in VMDq enable mode */
2218                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2219                                         " wrong mq_mode rx %d.",
2220                                         dev_conf->rxmode.mq_mode);
2221                         return -EINVAL;
2222                 }
2223
2224                 switch (dev_conf->txmode.mq_mode) {
2225                 case ETH_MQ_TX_VMDQ_DCB:
2226                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2227                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2228                         break;
2229                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2230                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2231                         break;
2232                 }
2233
2234                 /* check valid queue number */
2235                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2236                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2237                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2238                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2239                                         " must be less than or equal to %d.",
2240                                         nb_rx_q, nb_tx_q,
2241                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2242                         return -EINVAL;
2243                 }
2244         } else {
2245                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2246                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2247                                           " not supported.");
2248                         return -EINVAL;
2249                 }
2250                 /* check configuration for vmdb+dcb mode */
2251                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2252                         const struct rte_eth_vmdq_dcb_conf *conf;
2253
2254                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2255                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2256                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2257                                 return -EINVAL;
2258                         }
2259                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2260                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2261                                conf->nb_queue_pools == ETH_32_POOLS)) {
2262                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2263                                                 " nb_queue_pools must be %d or %d.",
2264                                                 ETH_16_POOLS, ETH_32_POOLS);
2265                                 return -EINVAL;
2266                         }
2267                 }
2268                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2269                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2270
2271                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2272                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2273                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2274                                 return -EINVAL;
2275                         }
2276                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2277                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2278                                conf->nb_queue_pools == ETH_32_POOLS)) {
2279                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2280                                                 " nb_queue_pools != %d and"
2281                                                 " nb_queue_pools != %d.",
2282                                                 ETH_16_POOLS, ETH_32_POOLS);
2283                                 return -EINVAL;
2284                         }
2285                 }
2286
2287                 /* For DCB mode check our configuration before we go further */
2288                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2289                         const struct rte_eth_dcb_rx_conf *conf;
2290
2291                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2292                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2293                                                  IXGBE_DCB_NB_QUEUES);
2294                                 return -EINVAL;
2295                         }
2296                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2297                         if (!(conf->nb_tcs == ETH_4_TCS ||
2298                                conf->nb_tcs == ETH_8_TCS)) {
2299                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2300                                                 " and nb_tcs != %d.",
2301                                                 ETH_4_TCS, ETH_8_TCS);
2302                                 return -EINVAL;
2303                         }
2304                 }
2305
2306                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2307                         const struct rte_eth_dcb_tx_conf *conf;
2308
2309                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2310                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2311                                                  IXGBE_DCB_NB_QUEUES);
2312                                 return -EINVAL;
2313                         }
2314                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2315                         if (!(conf->nb_tcs == ETH_4_TCS ||
2316                                conf->nb_tcs == ETH_8_TCS)) {
2317                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2318                                                 " and nb_tcs != %d.",
2319                                                 ETH_4_TCS, ETH_8_TCS);
2320                                 return -EINVAL;
2321                         }
2322                 }
2323
2324                 /*
2325                  * When DCB/VT is off, maximum number of queues changes,
2326                  * except for 82598EB, which remains constant.
2327                  */
2328                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2329                                 hw->mac.type != ixgbe_mac_82598EB) {
2330                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2331                                 PMD_INIT_LOG(ERR,
2332                                              "Neither VT nor DCB are enabled, "
2333                                              "nb_tx_q > %d.",
2334                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2335                                 return -EINVAL;
2336                         }
2337                 }
2338         }
2339         return 0;
2340 }
2341
2342 static int
2343 ixgbe_dev_configure(struct rte_eth_dev *dev)
2344 {
2345         struct ixgbe_interrupt *intr =
2346                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2347         struct ixgbe_adapter *adapter =
2348                 (struct ixgbe_adapter *)dev->data->dev_private;
2349         int ret;
2350
2351         PMD_INIT_FUNC_TRACE();
2352         /* multipe queue mode checking */
2353         ret  = ixgbe_check_mq_mode(dev);
2354         if (ret != 0) {
2355                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2356                             ret);
2357                 return ret;
2358         }
2359
2360         /* set flag to update link status after init */
2361         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2362
2363         /*
2364          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2365          * allocation or vector Rx preconditions we will reset it.
2366          */
2367         adapter->rx_bulk_alloc_allowed = true;
2368         adapter->rx_vec_allowed = true;
2369
2370         return 0;
2371 }
2372
2373 static void
2374 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2375 {
2376         struct ixgbe_hw *hw =
2377                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2378         struct ixgbe_interrupt *intr =
2379                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2380         uint32_t gpie;
2381
2382         /* only set up it on X550EM_X */
2383         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2384                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2385                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2386                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2387                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2388                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2389         }
2390 }
2391
2392 int
2393 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2394                         uint16_t tx_rate, uint64_t q_msk)
2395 {
2396         struct ixgbe_hw *hw;
2397         struct ixgbe_vf_info *vfinfo;
2398         struct rte_eth_link link;
2399         uint8_t  nb_q_per_pool;
2400         uint32_t queue_stride;
2401         uint32_t queue_idx, idx = 0, vf_idx;
2402         uint32_t queue_end;
2403         uint16_t total_rate = 0;
2404         struct rte_pci_device *pci_dev;
2405
2406         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2407         rte_eth_link_get_nowait(dev->data->port_id, &link);
2408
2409         if (vf >= pci_dev->max_vfs)
2410                 return -EINVAL;
2411
2412         if (tx_rate > link.link_speed)
2413                 return -EINVAL;
2414
2415         if (q_msk == 0)
2416                 return 0;
2417
2418         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2420         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2421         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2422         queue_idx = vf * queue_stride;
2423         queue_end = queue_idx + nb_q_per_pool - 1;
2424         if (queue_end >= hw->mac.max_tx_queues)
2425                 return -EINVAL;
2426
2427         if (vfinfo) {
2428                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2429                         if (vf_idx == vf)
2430                                 continue;
2431                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2432                                 idx++)
2433                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2434                 }
2435         } else {
2436                 return -EINVAL;
2437         }
2438
2439         /* Store tx_rate for this vf. */
2440         for (idx = 0; idx < nb_q_per_pool; idx++) {
2441                 if (((uint64_t)0x1 << idx) & q_msk) {
2442                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2443                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2444                         total_rate += tx_rate;
2445                 }
2446         }
2447
2448         if (total_rate > dev->data->dev_link.link_speed) {
2449                 /* Reset stored TX rate of the VF if it causes exceed
2450                  * link speed.
2451                  */
2452                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2453                 return -EINVAL;
2454         }
2455
2456         /* Set RTTBCNRC of each queue/pool for vf X  */
2457         for (; queue_idx <= queue_end; queue_idx++) {
2458                 if (0x1 & q_msk)
2459                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2460                 q_msk = q_msk >> 1;
2461         }
2462
2463         return 0;
2464 }
2465
2466 /*
2467  * Configure device link speed and setup link.
2468  * It returns 0 on success.
2469  */
2470 static int
2471 ixgbe_dev_start(struct rte_eth_dev *dev)
2472 {
2473         struct ixgbe_hw *hw =
2474                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475         struct ixgbe_vf_info *vfinfo =
2476                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2477         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2478         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2479         uint32_t intr_vector = 0;
2480         int err, link_up = 0, negotiate = 0;
2481         uint32_t speed = 0;
2482         int mask = 0;
2483         int status;
2484         uint16_t vf, idx;
2485         uint32_t *link_speeds;
2486         struct ixgbe_tm_conf *tm_conf =
2487                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2488
2489         PMD_INIT_FUNC_TRACE();
2490
2491         /* IXGBE devices don't support:
2492         *    - half duplex (checked afterwards for valid speeds)
2493         *    - fixed speed: TODO implement
2494         */
2495         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2496                 PMD_INIT_LOG(ERR,
2497                 "Invalid link_speeds for port %u, fix speed not supported",
2498                                 dev->data->port_id);
2499                 return -EINVAL;
2500         }
2501
2502         /* disable uio/vfio intr/eventfd mapping */
2503         rte_intr_disable(intr_handle);
2504
2505         /* stop adapter */
2506         hw->adapter_stopped = 0;
2507         ixgbe_stop_adapter(hw);
2508
2509         /* reinitialize adapter
2510          * this calls reset and start
2511          */
2512         status = ixgbe_pf_reset_hw(hw);
2513         if (status != 0)
2514                 return -1;
2515         hw->mac.ops.start_hw(hw);
2516         hw->mac.get_link_status = true;
2517
2518         /* configure PF module if SRIOV enabled */
2519         ixgbe_pf_host_configure(dev);
2520
2521         ixgbe_dev_phy_intr_setup(dev);
2522
2523         /* check and configure queue intr-vector mapping */
2524         if ((rte_intr_cap_multiple(intr_handle) ||
2525              !RTE_ETH_DEV_SRIOV(dev).active) &&
2526             dev->data->dev_conf.intr_conf.rxq != 0) {
2527                 intr_vector = dev->data->nb_rx_queues;
2528                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2529                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2530                                         IXGBE_MAX_INTR_QUEUE_NUM);
2531                         return -ENOTSUP;
2532                 }
2533                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2534                         return -1;
2535         }
2536
2537         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2538                 intr_handle->intr_vec =
2539                         rte_zmalloc("intr_vec",
2540                                     dev->data->nb_rx_queues * sizeof(int), 0);
2541                 if (intr_handle->intr_vec == NULL) {
2542                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2543                                      " intr_vec", dev->data->nb_rx_queues);
2544                         return -ENOMEM;
2545                 }
2546         }
2547
2548         /* confiugre msix for sleep until rx interrupt */
2549         ixgbe_configure_msix(dev);
2550
2551         /* initialize transmission unit */
2552         ixgbe_dev_tx_init(dev);
2553
2554         /* This can fail when allocating mbufs for descriptor rings */
2555         err = ixgbe_dev_rx_init(dev);
2556         if (err) {
2557                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2558                 goto error;
2559         }
2560
2561         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2562                 ETH_VLAN_EXTEND_MASK;
2563         err = ixgbe_vlan_offload_set(dev, mask);
2564         if (err) {
2565                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2566                 goto error;
2567         }
2568
2569         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2570                 /* Enable vlan filtering for VMDq */
2571                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2572         }
2573
2574         /* Configure DCB hw */
2575         ixgbe_configure_dcb(dev);
2576
2577         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2578                 err = ixgbe_fdir_configure(dev);
2579                 if (err)
2580                         goto error;
2581         }
2582
2583         /* Restore vf rate limit */
2584         if (vfinfo != NULL) {
2585                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2586                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2587                                 if (vfinfo[vf].tx_rate[idx] != 0)
2588                                         ixgbe_set_vf_rate_limit(
2589                                                 dev, vf,
2590                                                 vfinfo[vf].tx_rate[idx],
2591                                                 1 << idx);
2592         }
2593
2594         ixgbe_restore_statistics_mapping(dev);
2595
2596         err = ixgbe_dev_rxtx_start(dev);
2597         if (err < 0) {
2598                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2599                 goto error;
2600         }
2601
2602         /* Skip link setup if loopback mode is enabled for 82599. */
2603         if (hw->mac.type == ixgbe_mac_82599EB &&
2604                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2605                 goto skip_link_setup;
2606
2607         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2608                 err = hw->mac.ops.setup_sfp(hw);
2609                 if (err)
2610                         goto error;
2611         }
2612
2613         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2614                 /* Turn on the copper */
2615                 ixgbe_set_phy_power(hw, true);
2616         } else {
2617                 /* Turn on the laser */
2618                 ixgbe_enable_tx_laser(hw);
2619         }
2620
2621         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2622         if (err)
2623                 goto error;
2624         dev->data->dev_link.link_status = link_up;
2625
2626         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2627         if (err)
2628                 goto error;
2629
2630         link_speeds = &dev->data->dev_conf.link_speeds;
2631         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2632                         ETH_LINK_SPEED_10G)) {
2633                 PMD_INIT_LOG(ERR, "Invalid link setting");
2634                 goto error;
2635         }
2636
2637         speed = 0x0;
2638         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2639                 switch (hw->mac.type) {
2640                 case ixgbe_mac_82598EB:
2641                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2642                         break;
2643                 case ixgbe_mac_82599EB:
2644                 case ixgbe_mac_X540:
2645                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2646                         break;
2647                 case ixgbe_mac_X550:
2648                 case ixgbe_mac_X550EM_x:
2649                 case ixgbe_mac_X550EM_a:
2650                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2651                         break;
2652                 default:
2653                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2654                 }
2655         } else {
2656                 if (*link_speeds & ETH_LINK_SPEED_10G)
2657                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2658                 if (*link_speeds & ETH_LINK_SPEED_1G)
2659                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2660                 if (*link_speeds & ETH_LINK_SPEED_100M)
2661                         speed |= IXGBE_LINK_SPEED_100_FULL;
2662         }
2663
2664         err = ixgbe_setup_link(hw, speed, link_up);
2665         if (err)
2666                 goto error;
2667
2668 skip_link_setup:
2669
2670         if (rte_intr_allow_others(intr_handle)) {
2671                 /* check if lsc interrupt is enabled */
2672                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2673                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2674                 else
2675                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2676                 ixgbe_dev_macsec_interrupt_setup(dev);
2677         } else {
2678                 rte_intr_callback_unregister(intr_handle,
2679                                              ixgbe_dev_interrupt_handler, dev);
2680                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2681                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2682                                      " no intr multiplex");
2683         }
2684
2685         /* check if rxq interrupt is enabled */
2686         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2687             rte_intr_dp_is_en(intr_handle))
2688                 ixgbe_dev_rxq_interrupt_setup(dev);
2689
2690         /* enable uio/vfio intr/eventfd mapping */
2691         rte_intr_enable(intr_handle);
2692
2693         /* resume enabled intr since hw reset */
2694         ixgbe_enable_intr(dev);
2695         ixgbe_l2_tunnel_conf(dev);
2696         ixgbe_filter_restore(dev);
2697
2698         if (tm_conf->root && !tm_conf->committed)
2699                 PMD_DRV_LOG(WARNING,
2700                             "please call hierarchy_commit() "
2701                             "before starting the port");
2702
2703         return 0;
2704
2705 error:
2706         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2707         ixgbe_dev_clear_queues(dev);
2708         return -EIO;
2709 }
2710
2711 /*
2712  * Stop device: disable rx and tx functions to allow for reconfiguring.
2713  */
2714 static void
2715 ixgbe_dev_stop(struct rte_eth_dev *dev)
2716 {
2717         struct rte_eth_link link;
2718         struct ixgbe_hw *hw =
2719                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2720         struct ixgbe_vf_info *vfinfo =
2721                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2722         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2723         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2724         int vf;
2725         struct ixgbe_tm_conf *tm_conf =
2726                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2727
2728         PMD_INIT_FUNC_TRACE();
2729
2730         /* disable interrupts */
2731         ixgbe_disable_intr(hw);
2732
2733         /* reset the NIC */
2734         ixgbe_pf_reset_hw(hw);
2735         hw->adapter_stopped = 0;
2736
2737         /* stop adapter */
2738         ixgbe_stop_adapter(hw);
2739
2740         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2741                 vfinfo[vf].clear_to_send = false;
2742
2743         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2744                 /* Turn off the copper */
2745                 ixgbe_set_phy_power(hw, false);
2746         } else {
2747                 /* Turn off the laser */
2748                 ixgbe_disable_tx_laser(hw);
2749         }
2750
2751         ixgbe_dev_clear_queues(dev);
2752
2753         /* Clear stored conf */
2754         dev->data->scattered_rx = 0;
2755         dev->data->lro = 0;
2756
2757         /* Clear recorded link status */
2758         memset(&link, 0, sizeof(link));
2759         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2760
2761         if (!rte_intr_allow_others(intr_handle))
2762                 /* resume to the default handler */
2763                 rte_intr_callback_register(intr_handle,
2764                                            ixgbe_dev_interrupt_handler,
2765                                            (void *)dev);
2766
2767         /* Clean datapath event and queue/vec mapping */
2768         rte_intr_efd_disable(intr_handle);
2769         if (intr_handle->intr_vec != NULL) {
2770                 rte_free(intr_handle->intr_vec);
2771                 intr_handle->intr_vec = NULL;
2772         }
2773
2774         /* reset hierarchy commit */
2775         tm_conf->committed = false;
2776 }
2777
2778 /*
2779  * Set device link up: enable tx.
2780  */
2781 static int
2782 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2783 {
2784         struct ixgbe_hw *hw =
2785                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786         if (hw->mac.type == ixgbe_mac_82599EB) {
2787 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2788                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2789                         /* Not suported in bypass mode */
2790                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2791                                      "by device id 0x%x", hw->device_id);
2792                         return -ENOTSUP;
2793                 }
2794 #endif
2795         }
2796
2797         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2798                 /* Turn on the copper */
2799                 ixgbe_set_phy_power(hw, true);
2800         } else {
2801                 /* Turn on the laser */
2802                 ixgbe_enable_tx_laser(hw);
2803         }
2804
2805         return 0;
2806 }
2807
2808 /*
2809  * Set device link down: disable tx.
2810  */
2811 static int
2812 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2813 {
2814         struct ixgbe_hw *hw =
2815                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2816         if (hw->mac.type == ixgbe_mac_82599EB) {
2817 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2818                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2819                         /* Not suported in bypass mode */
2820                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2821                                      "by device id 0x%x", hw->device_id);
2822                         return -ENOTSUP;
2823                 }
2824 #endif
2825         }
2826
2827         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2828                 /* Turn off the copper */
2829                 ixgbe_set_phy_power(hw, false);
2830         } else {
2831                 /* Turn off the laser */
2832                 ixgbe_disable_tx_laser(hw);
2833         }
2834
2835         return 0;
2836 }
2837
2838 /*
2839  * Reset and stop device.
2840  */
2841 static void
2842 ixgbe_dev_close(struct rte_eth_dev *dev)
2843 {
2844         struct ixgbe_hw *hw =
2845                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2846
2847         PMD_INIT_FUNC_TRACE();
2848
2849         ixgbe_pf_reset_hw(hw);
2850
2851         ixgbe_dev_stop(dev);
2852         hw->adapter_stopped = 1;
2853
2854         ixgbe_dev_free_queues(dev);
2855
2856         ixgbe_disable_pcie_master(hw);
2857
2858         /* reprogram the RAR[0] in case user changed it. */
2859         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2860 }
2861
2862 /*
2863  * Reset PF device.
2864  */
2865 static int
2866 ixgbe_dev_reset(struct rte_eth_dev *dev)
2867 {
2868         int ret;
2869
2870         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2871          * its VF to make them align with it. The detailed notification
2872          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2873          * To avoid unexpected behavior in VF, currently reset of PF with
2874          * SR-IOV activation is not supported. It might be supported later.
2875          */
2876         if (dev->data->sriov.active)
2877                 return -ENOTSUP;
2878
2879         ret = eth_ixgbe_dev_uninit(dev);
2880         if (ret)
2881                 return ret;
2882
2883         ret = eth_ixgbe_dev_init(dev);
2884
2885         return ret;
2886 }
2887
2888 static void
2889 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2890                            struct ixgbe_hw_stats *hw_stats,
2891                            struct ixgbe_macsec_stats *macsec_stats,
2892                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2893                            uint64_t *total_qprc, uint64_t *total_qprdc)
2894 {
2895         uint32_t bprc, lxon, lxoff, total;
2896         uint32_t delta_gprc = 0;
2897         unsigned i;
2898         /* Workaround for RX byte count not including CRC bytes when CRC
2899          * strip is enabled. CRC bytes are removed from counters when crc_strip
2900          * is disabled.
2901          */
2902         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2903                         IXGBE_HLREG0_RXCRCSTRP);
2904
2905         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2906         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2907         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2908         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2909
2910         for (i = 0; i < 8; i++) {
2911                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2912
2913                 /* global total per queue */
2914                 hw_stats->mpc[i] += mp;
2915                 /* Running comprehensive total for stats display */
2916                 *total_missed_rx += hw_stats->mpc[i];
2917                 if (hw->mac.type == ixgbe_mac_82598EB) {
2918                         hw_stats->rnbc[i] +=
2919                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2920                         hw_stats->pxonrxc[i] +=
2921                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2922                         hw_stats->pxoffrxc[i] +=
2923                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2924                 } else {
2925                         hw_stats->pxonrxc[i] +=
2926                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2927                         hw_stats->pxoffrxc[i] +=
2928                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2929                         hw_stats->pxon2offc[i] +=
2930                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2931                 }
2932                 hw_stats->pxontxc[i] +=
2933                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2934                 hw_stats->pxofftxc[i] +=
2935                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2936         }
2937         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2938                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2939                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2940                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2941
2942                 delta_gprc += delta_qprc;
2943
2944                 hw_stats->qprc[i] += delta_qprc;
2945                 hw_stats->qptc[i] += delta_qptc;
2946
2947                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2948                 hw_stats->qbrc[i] +=
2949                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2950                 if (crc_strip == 0)
2951                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2952
2953                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2954                 hw_stats->qbtc[i] +=
2955                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2956
2957                 hw_stats->qprdc[i] += delta_qprdc;
2958                 *total_qprdc += hw_stats->qprdc[i];
2959
2960                 *total_qprc += hw_stats->qprc[i];
2961                 *total_qbrc += hw_stats->qbrc[i];
2962         }
2963         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2964         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2965         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2966
2967         /*
2968          * An errata states that gprc actually counts good + missed packets:
2969          * Workaround to set gprc to summated queue packet receives
2970          */
2971         hw_stats->gprc = *total_qprc;
2972
2973         if (hw->mac.type != ixgbe_mac_82598EB) {
2974                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2975                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2976                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2977                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2978                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2979                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2980                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2981                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2982         } else {
2983                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2984                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2985                 /* 82598 only has a counter in the high register */
2986                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2987                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2988                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2989         }
2990         uint64_t old_tpr = hw_stats->tpr;
2991
2992         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2993         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2994
2995         if (crc_strip == 0)
2996                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2997
2998         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2999         hw_stats->gptc += delta_gptc;
3000         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3001         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3002
3003         /*
3004          * Workaround: mprc hardware is incorrectly counting
3005          * broadcasts, so for now we subtract those.
3006          */
3007         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3008         hw_stats->bprc += bprc;
3009         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3010         if (hw->mac.type == ixgbe_mac_82598EB)
3011                 hw_stats->mprc -= bprc;
3012
3013         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3014         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3015         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3016         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3017         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3018         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3019
3020         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3021         hw_stats->lxontxc += lxon;
3022         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3023         hw_stats->lxofftxc += lxoff;
3024         total = lxon + lxoff;
3025
3026         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3027         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3028         hw_stats->gptc -= total;
3029         hw_stats->mptc -= total;
3030         hw_stats->ptc64 -= total;
3031         hw_stats->gotc -= total * ETHER_MIN_LEN;
3032
3033         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3034         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3035         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3036         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3037         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3038         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3039         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3040         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3041         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3042         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3043         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3044         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3045         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3046         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3047         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3048         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3049         /* Only read FCOE on 82599 */
3050         if (hw->mac.type != ixgbe_mac_82598EB) {
3051                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3052                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3053                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3054                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3055                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3056         }
3057
3058         /* Flow Director Stats registers */
3059         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3060         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3061
3062         /* MACsec Stats registers */
3063         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3064         macsec_stats->out_pkts_encrypted +=
3065                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3066         macsec_stats->out_pkts_protected +=
3067                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3068         macsec_stats->out_octets_encrypted +=
3069                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3070         macsec_stats->out_octets_protected +=
3071                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3072         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3073         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3074         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3075         macsec_stats->in_pkts_unknownsci +=
3076                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3077         macsec_stats->in_octets_decrypted +=
3078                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3079         macsec_stats->in_octets_validated +=
3080                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3081         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3082         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3083         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3084         for (i = 0; i < 2; i++) {
3085                 macsec_stats->in_pkts_ok +=
3086                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3087                 macsec_stats->in_pkts_invalid +=
3088                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3089                 macsec_stats->in_pkts_notvalid +=
3090                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3091         }
3092         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3093         macsec_stats->in_pkts_notusingsa +=
3094                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3095 }
3096
3097 /*
3098  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3099  */
3100 static int
3101 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3102 {
3103         struct ixgbe_hw *hw =
3104                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3105         struct ixgbe_hw_stats *hw_stats =
3106                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3107         struct ixgbe_macsec_stats *macsec_stats =
3108                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3109                                 dev->data->dev_private);
3110         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3111         unsigned i;
3112
3113         total_missed_rx = 0;
3114         total_qbrc = 0;
3115         total_qprc = 0;
3116         total_qprdc = 0;
3117
3118         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3119                         &total_qbrc, &total_qprc, &total_qprdc);
3120
3121         if (stats == NULL)
3122                 return -EINVAL;
3123
3124         /* Fill out the rte_eth_stats statistics structure */
3125         stats->ipackets = total_qprc;
3126         stats->ibytes = total_qbrc;
3127         stats->opackets = hw_stats->gptc;
3128         stats->obytes = hw_stats->gotc;
3129
3130         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3131                 stats->q_ipackets[i] = hw_stats->qprc[i];
3132                 stats->q_opackets[i] = hw_stats->qptc[i];
3133                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3134                 stats->q_obytes[i] = hw_stats->qbtc[i];
3135                 stats->q_errors[i] = hw_stats->qprdc[i];
3136         }
3137
3138         /* Rx Errors */
3139         stats->imissed  = total_missed_rx;
3140         stats->ierrors  = hw_stats->crcerrs +
3141                           hw_stats->mspdc +
3142                           hw_stats->rlec +
3143                           hw_stats->ruc +
3144                           hw_stats->roc +
3145                           hw_stats->illerrc +
3146                           hw_stats->errbc +
3147                           hw_stats->rfc +
3148                           hw_stats->fccrc +
3149                           hw_stats->fclast;
3150
3151         /* Tx Errors */
3152         stats->oerrors  = 0;
3153         return 0;
3154 }
3155
3156 static void
3157 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3158 {
3159         struct ixgbe_hw_stats *stats =
3160                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3161
3162         /* HW registers are cleared on read */
3163         ixgbe_dev_stats_get(dev, NULL);
3164
3165         /* Reset software totals */
3166         memset(stats, 0, sizeof(*stats));
3167 }
3168
3169 /* This function calculates the number of xstats based on the current config */
3170 static unsigned
3171 ixgbe_xstats_calc_num(void) {
3172         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3173                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3174                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3175 }
3176
3177 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3178         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3179 {
3180         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3181         unsigned stat, i, count;
3182
3183         if (xstats_names != NULL) {
3184                 count = 0;
3185
3186                 /* Note: limit >= cnt_stats checked upstream
3187                  * in rte_eth_xstats_names()
3188                  */
3189
3190                 /* Extended stats from ixgbe_hw_stats */
3191                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3192                         snprintf(xstats_names[count].name,
3193                                 sizeof(xstats_names[count].name),
3194                                 "%s",
3195                                 rte_ixgbe_stats_strings[i].name);
3196                         count++;
3197                 }
3198
3199                 /* MACsec Stats */
3200                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3201                         snprintf(xstats_names[count].name,
3202                                 sizeof(xstats_names[count].name),
3203                                 "%s",
3204                                 rte_ixgbe_macsec_strings[i].name);
3205                         count++;
3206                 }
3207
3208                 /* RX Priority Stats */
3209                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3210                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3211                                 snprintf(xstats_names[count].name,
3212                                         sizeof(xstats_names[count].name),
3213                                         "rx_priority%u_%s", i,
3214                                         rte_ixgbe_rxq_strings[stat].name);
3215                                 count++;
3216                         }
3217                 }
3218
3219                 /* TX Priority Stats */
3220                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3221                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3222                                 snprintf(xstats_names[count].name,
3223                                         sizeof(xstats_names[count].name),
3224                                         "tx_priority%u_%s", i,
3225                                         rte_ixgbe_txq_strings[stat].name);
3226                                 count++;
3227                         }
3228                 }
3229         }
3230         return cnt_stats;
3231 }
3232
3233 static int ixgbe_dev_xstats_get_names_by_id(
3234         struct rte_eth_dev *dev,
3235         struct rte_eth_xstat_name *xstats_names,
3236         const uint64_t *ids,
3237         unsigned int limit)
3238 {
3239         if (!ids) {
3240                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3241                 unsigned int stat, i, count;
3242
3243                 if (xstats_names != NULL) {
3244                         count = 0;
3245
3246                         /* Note: limit >= cnt_stats checked upstream
3247                          * in rte_eth_xstats_names()
3248                          */
3249
3250                         /* Extended stats from ixgbe_hw_stats */
3251                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3252                                 snprintf(xstats_names[count].name,
3253                                         sizeof(xstats_names[count].name),
3254                                         "%s",
3255                                         rte_ixgbe_stats_strings[i].name);
3256                                 count++;
3257                         }
3258
3259                         /* MACsec Stats */
3260                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3261                                 snprintf(xstats_names[count].name,
3262                                         sizeof(xstats_names[count].name),
3263                                         "%s",
3264                                         rte_ixgbe_macsec_strings[i].name);
3265                                 count++;
3266                         }
3267
3268                         /* RX Priority Stats */
3269                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3270                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3271                                         snprintf(xstats_names[count].name,
3272                                             sizeof(xstats_names[count].name),
3273                                             "rx_priority%u_%s", i,
3274                                             rte_ixgbe_rxq_strings[stat].name);
3275                                         count++;
3276                                 }
3277                         }
3278
3279                         /* TX Priority Stats */
3280                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3281                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3282                                         snprintf(xstats_names[count].name,
3283                                             sizeof(xstats_names[count].name),
3284                                             "tx_priority%u_%s", i,
3285                                             rte_ixgbe_txq_strings[stat].name);
3286                                         count++;
3287                                 }
3288                         }
3289                 }
3290                 return cnt_stats;
3291         }
3292
3293         uint16_t i;
3294         uint16_t size = ixgbe_xstats_calc_num();
3295         struct rte_eth_xstat_name xstats_names_copy[size];
3296
3297         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3298                         size);
3299
3300         for (i = 0; i < limit; i++) {
3301                 if (ids[i] >= size) {
3302                         PMD_INIT_LOG(ERR, "id value isn't valid");
3303                         return -1;
3304                 }
3305                 strcpy(xstats_names[i].name,
3306                                 xstats_names_copy[ids[i]].name);
3307         }
3308         return limit;
3309 }
3310
3311 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3312         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3313 {
3314         unsigned i;
3315
3316         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3317                 return -ENOMEM;
3318
3319         if (xstats_names != NULL)
3320                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3321                         snprintf(xstats_names[i].name,
3322                                 sizeof(xstats_names[i].name),
3323                                 "%s", rte_ixgbevf_stats_strings[i].name);
3324         return IXGBEVF_NB_XSTATS;
3325 }
3326
3327 static int
3328 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3329                                          unsigned n)
3330 {
3331         struct ixgbe_hw *hw =
3332                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3333         struct ixgbe_hw_stats *hw_stats =
3334                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3335         struct ixgbe_macsec_stats *macsec_stats =
3336                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3337                                 dev->data->dev_private);
3338         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3339         unsigned i, stat, count = 0;
3340
3341         count = ixgbe_xstats_calc_num();
3342
3343         if (n < count)
3344                 return count;
3345
3346         total_missed_rx = 0;
3347         total_qbrc = 0;
3348         total_qprc = 0;
3349         total_qprdc = 0;
3350
3351         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3352                         &total_qbrc, &total_qprc, &total_qprdc);
3353
3354         /* If this is a reset xstats is NULL, and we have cleared the
3355          * registers by reading them.
3356          */
3357         if (!xstats)
3358                 return 0;
3359
3360         /* Extended stats from ixgbe_hw_stats */
3361         count = 0;
3362         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3363                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3364                                 rte_ixgbe_stats_strings[i].offset);
3365                 xstats[count].id = count;
3366                 count++;
3367         }
3368
3369         /* MACsec Stats */
3370         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3371                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3372                                 rte_ixgbe_macsec_strings[i].offset);
3373                 xstats[count].id = count;
3374                 count++;
3375         }
3376
3377         /* RX Priority Stats */
3378         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3379                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3380                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3381                                         rte_ixgbe_rxq_strings[stat].offset +
3382                                         (sizeof(uint64_t) * i));
3383                         xstats[count].id = count;
3384                         count++;
3385                 }
3386         }
3387
3388         /* TX Priority Stats */
3389         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3390                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3391                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3392                                         rte_ixgbe_txq_strings[stat].offset +
3393                                         (sizeof(uint64_t) * i));
3394                         xstats[count].id = count;
3395                         count++;
3396                 }
3397         }
3398         return count;
3399 }
3400
3401 static int
3402 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3403                 uint64_t *values, unsigned int n)
3404 {
3405         if (!ids) {
3406                 struct ixgbe_hw *hw =
3407                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3408                 struct ixgbe_hw_stats *hw_stats =
3409                                 IXGBE_DEV_PRIVATE_TO_STATS(
3410                                                 dev->data->dev_private);
3411                 struct ixgbe_macsec_stats *macsec_stats =
3412                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3413                                         dev->data->dev_private);
3414                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3415                 unsigned int i, stat, count = 0;
3416
3417                 count = ixgbe_xstats_calc_num();
3418
3419                 if (!ids && n < count)
3420                         return count;
3421
3422                 total_missed_rx = 0;
3423                 total_qbrc = 0;
3424                 total_qprc = 0;
3425                 total_qprdc = 0;
3426
3427                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3428                                 &total_missed_rx, &total_qbrc, &total_qprc,
3429                                 &total_qprdc);
3430
3431                 /* If this is a reset xstats is NULL, and we have cleared the
3432                  * registers by reading them.
3433                  */
3434                 if (!ids && !values)
3435                         return 0;
3436
3437                 /* Extended stats from ixgbe_hw_stats */
3438                 count = 0;
3439                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3440                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3441                                         rte_ixgbe_stats_strings[i].offset);
3442                         count++;
3443                 }
3444
3445                 /* MACsec Stats */
3446                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3447                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3448                                         rte_ixgbe_macsec_strings[i].offset);
3449                         count++;
3450                 }
3451
3452                 /* RX Priority Stats */
3453                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3454                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3455                                 values[count] =
3456                                         *(uint64_t *)(((char *)hw_stats) +
3457                                         rte_ixgbe_rxq_strings[stat].offset +
3458                                         (sizeof(uint64_t) * i));
3459                                 count++;
3460                         }
3461                 }
3462
3463                 /* TX Priority Stats */
3464                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3465                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3466                                 values[count] =
3467                                         *(uint64_t *)(((char *)hw_stats) +
3468                                         rte_ixgbe_txq_strings[stat].offset +
3469                                         (sizeof(uint64_t) * i));
3470                                 count++;
3471                         }
3472                 }
3473                 return count;
3474         }
3475
3476         uint16_t i;
3477         uint16_t size = ixgbe_xstats_calc_num();
3478         uint64_t values_copy[size];
3479
3480         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3481
3482         for (i = 0; i < n; i++) {
3483                 if (ids[i] >= size) {
3484                         PMD_INIT_LOG(ERR, "id value isn't valid");
3485                         return -1;
3486                 }
3487                 values[i] = values_copy[ids[i]];
3488         }
3489         return n;
3490 }
3491
3492 static void
3493 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3494 {
3495         struct ixgbe_hw_stats *stats =
3496                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3497         struct ixgbe_macsec_stats *macsec_stats =
3498                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3499                                 dev->data->dev_private);
3500
3501         unsigned count = ixgbe_xstats_calc_num();
3502
3503         /* HW registers are cleared on read */
3504         ixgbe_dev_xstats_get(dev, NULL, count);
3505
3506         /* Reset software totals */
3507         memset(stats, 0, sizeof(*stats));
3508         memset(macsec_stats, 0, sizeof(*macsec_stats));
3509 }
3510
3511 static void
3512 ixgbevf_update_stats(struct rte_eth_dev *dev)
3513 {
3514         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3516                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3517
3518         /* Good Rx packet, include VF loopback */
3519         UPDATE_VF_STAT(IXGBE_VFGPRC,
3520             hw_stats->last_vfgprc, hw_stats->vfgprc);
3521
3522         /* Good Rx octets, include VF loopback */
3523         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3524             hw_stats->last_vfgorc, hw_stats->vfgorc);
3525
3526         /* Good Tx packet, include VF loopback */
3527         UPDATE_VF_STAT(IXGBE_VFGPTC,
3528             hw_stats->last_vfgptc, hw_stats->vfgptc);
3529
3530         /* Good Tx octets, include VF loopback */
3531         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3532             hw_stats->last_vfgotc, hw_stats->vfgotc);
3533
3534         /* Rx Multicst Packet */
3535         UPDATE_VF_STAT(IXGBE_VFMPRC,
3536             hw_stats->last_vfmprc, hw_stats->vfmprc);
3537 }
3538
3539 static int
3540 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3541                        unsigned n)
3542 {
3543         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3544                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3545         unsigned i;
3546
3547         if (n < IXGBEVF_NB_XSTATS)
3548                 return IXGBEVF_NB_XSTATS;
3549
3550         ixgbevf_update_stats(dev);
3551
3552         if (!xstats)
3553                 return 0;
3554
3555         /* Extended stats */
3556         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3557                 xstats[i].id = i;
3558                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3559                         rte_ixgbevf_stats_strings[i].offset);
3560         }
3561
3562         return IXGBEVF_NB_XSTATS;
3563 }
3564
3565 static int
3566 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3567 {
3568         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3569                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3570
3571         ixgbevf_update_stats(dev);
3572
3573         if (stats == NULL)
3574                 return -EINVAL;
3575
3576         stats->ipackets = hw_stats->vfgprc;
3577         stats->ibytes = hw_stats->vfgorc;
3578         stats->opackets = hw_stats->vfgptc;
3579         stats->obytes = hw_stats->vfgotc;
3580         return 0;
3581 }
3582
3583 static void
3584 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3585 {
3586         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3587                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3588
3589         /* Sync HW register to the last stats */
3590         ixgbevf_dev_stats_get(dev, NULL);
3591
3592         /* reset HW current stats*/
3593         hw_stats->vfgprc = 0;
3594         hw_stats->vfgorc = 0;
3595         hw_stats->vfgptc = 0;
3596         hw_stats->vfgotc = 0;
3597 }
3598
3599 static int
3600 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3601 {
3602         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3603         u16 eeprom_verh, eeprom_verl;
3604         u32 etrack_id;
3605         int ret;
3606
3607         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3608         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3609
3610         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3611         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3612
3613         ret += 1; /* add the size of '\0' */
3614         if (fw_size < (u32)ret)
3615                 return ret;
3616         else
3617                 return 0;
3618 }
3619
3620 static void
3621 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3622 {
3623         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3624         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3625         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3626
3627         dev_info->pci_dev = pci_dev;
3628         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3629         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3630         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3631                 /*
3632                  * When DCB/VT is off, maximum number of queues changes,
3633                  * except for 82598EB, which remains constant.
3634                  */
3635                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3636                                 hw->mac.type != ixgbe_mac_82598EB)
3637                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3638         }
3639         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3640         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3641         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3642         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3643         dev_info->max_vfs = pci_dev->max_vfs;
3644         if (hw->mac.type == ixgbe_mac_82598EB)
3645                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3646         else
3647                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3648         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3649         dev_info->rx_offload_capa =
3650                 DEV_RX_OFFLOAD_VLAN_STRIP |
3651                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3652                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3653                 DEV_RX_OFFLOAD_TCP_CKSUM;
3654
3655         /*
3656          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3657          * mode.
3658          */
3659         if ((hw->mac.type == ixgbe_mac_82599EB ||
3660              hw->mac.type == ixgbe_mac_X540) &&
3661             !RTE_ETH_DEV_SRIOV(dev).active)
3662                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3663
3664         if (hw->mac.type == ixgbe_mac_82599EB ||
3665             hw->mac.type == ixgbe_mac_X540)
3666                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3667
3668         if (hw->mac.type == ixgbe_mac_X550 ||
3669             hw->mac.type == ixgbe_mac_X550EM_x ||
3670             hw->mac.type == ixgbe_mac_X550EM_a)
3671                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3672
3673         dev_info->tx_offload_capa =
3674                 DEV_TX_OFFLOAD_VLAN_INSERT |
3675                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3676                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3677                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3678                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3679                 DEV_TX_OFFLOAD_TCP_TSO;
3680
3681         if (hw->mac.type == ixgbe_mac_82599EB ||
3682             hw->mac.type == ixgbe_mac_X540)
3683                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3684
3685         if (hw->mac.type == ixgbe_mac_X550 ||
3686             hw->mac.type == ixgbe_mac_X550EM_x ||
3687             hw->mac.type == ixgbe_mac_X550EM_a)
3688                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3689
3690 #ifdef RTE_LIBRTE_SECURITY
3691         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3692         dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3693 #endif
3694
3695         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3696                 .rx_thresh = {
3697                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3698                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3699                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3700                 },
3701                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3702                 .rx_drop_en = 0,
3703         };
3704
3705         dev_info->default_txconf = (struct rte_eth_txconf) {
3706                 .tx_thresh = {
3707                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3708                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3709                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3710                 },
3711                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3712                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3713                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3714                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3715         };
3716
3717         dev_info->rx_desc_lim = rx_desc_lim;
3718         dev_info->tx_desc_lim = tx_desc_lim;
3719
3720         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3721         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3722         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3723
3724         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3725         if (hw->mac.type == ixgbe_mac_X540 ||
3726             hw->mac.type == ixgbe_mac_X540_vf ||
3727             hw->mac.type == ixgbe_mac_X550 ||
3728             hw->mac.type == ixgbe_mac_X550_vf) {
3729                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3730         }
3731         if (hw->mac.type == ixgbe_mac_X550) {
3732                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3733                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3734         }
3735 }
3736
3737 static const uint32_t *
3738 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3739 {
3740         static const uint32_t ptypes[] = {
3741                 /* For non-vec functions,
3742                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3743                  * for vec functions,
3744                  * refers to _recv_raw_pkts_vec().
3745                  */
3746                 RTE_PTYPE_L2_ETHER,
3747                 RTE_PTYPE_L3_IPV4,
3748                 RTE_PTYPE_L3_IPV4_EXT,
3749                 RTE_PTYPE_L3_IPV6,
3750                 RTE_PTYPE_L3_IPV6_EXT,
3751                 RTE_PTYPE_L4_SCTP,
3752                 RTE_PTYPE_L4_TCP,
3753                 RTE_PTYPE_L4_UDP,
3754                 RTE_PTYPE_TUNNEL_IP,
3755                 RTE_PTYPE_INNER_L3_IPV6,
3756                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3757                 RTE_PTYPE_INNER_L4_TCP,
3758                 RTE_PTYPE_INNER_L4_UDP,
3759                 RTE_PTYPE_UNKNOWN
3760         };
3761
3762         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3763             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3764             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3765             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3766                 return ptypes;
3767
3768 #if defined(RTE_ARCH_X86)
3769         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3770             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3771                 return ptypes;
3772 #endif
3773         return NULL;
3774 }
3775
3776 static void
3777 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3778                      struct rte_eth_dev_info *dev_info)
3779 {
3780         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3781         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782
3783         dev_info->pci_dev = pci_dev;
3784         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3785         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3786         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3787         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3788         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3789         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3790         dev_info->max_vfs = pci_dev->max_vfs;
3791         if (hw->mac.type == ixgbe_mac_82598EB)
3792                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3793         else
3794                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3795         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3796                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3797                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3798                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3799         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3800                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3801                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3802                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3803                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3804                                 DEV_TX_OFFLOAD_TCP_TSO;
3805
3806         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3807                 .rx_thresh = {
3808                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3809                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3810                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3811                 },
3812                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3813                 .rx_drop_en = 0,
3814         };
3815
3816         dev_info->default_txconf = (struct rte_eth_txconf) {
3817                 .tx_thresh = {
3818                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3819                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3820                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3821                 },
3822                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3823                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3824                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3825                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3826         };
3827
3828         dev_info->rx_desc_lim = rx_desc_lim;
3829         dev_info->tx_desc_lim = tx_desc_lim;
3830 }
3831
3832 static int
3833 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3834                    int *link_up, int wait_to_complete)
3835 {
3836         /**
3837          * for a quick link status checking, wait_to_compelet == 0,
3838          * skip PF link status checking
3839          */
3840         bool no_pflink_check = wait_to_complete == 0;
3841         struct ixgbe_mbx_info *mbx = &hw->mbx;
3842         struct ixgbe_mac_info *mac = &hw->mac;
3843         uint32_t links_reg, in_msg;
3844         int ret_val = 0;
3845
3846         /* If we were hit with a reset drop the link */
3847         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3848                 mac->get_link_status = true;
3849
3850         if (!mac->get_link_status)
3851                 goto out;
3852
3853         /* if link status is down no point in checking to see if pf is up */
3854         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3855         if (!(links_reg & IXGBE_LINKS_UP))
3856                 goto out;
3857
3858         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3859          * before the link status is correct
3860          */
3861         if (mac->type == ixgbe_mac_82599_vf) {
3862                 int i;
3863
3864                 for (i = 0; i < 5; i++) {
3865                         rte_delay_us(100);
3866                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3867
3868                         if (!(links_reg & IXGBE_LINKS_UP))
3869                                 goto out;
3870                 }
3871         }
3872
3873         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3874         case IXGBE_LINKS_SPEED_10G_82599:
3875                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3876                 if (hw->mac.type >= ixgbe_mac_X550) {
3877                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3878                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3879                 }
3880                 break;
3881         case IXGBE_LINKS_SPEED_1G_82599:
3882                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3883                 break;
3884         case IXGBE_LINKS_SPEED_100_82599:
3885                 *speed = IXGBE_LINK_SPEED_100_FULL;
3886                 if (hw->mac.type == ixgbe_mac_X550) {
3887                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3888                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3889                 }
3890                 break;
3891         case IXGBE_LINKS_SPEED_10_X550EM_A:
3892                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3893                 /* Since Reserved in older MAC's */
3894                 if (hw->mac.type >= ixgbe_mac_X550)
3895                         *speed = IXGBE_LINK_SPEED_10_FULL;
3896                 break;
3897         default:
3898                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3899         }
3900
3901         if (no_pflink_check) {
3902                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3903                         mac->get_link_status = true;
3904                 else
3905                         mac->get_link_status = false;
3906
3907                 goto out;
3908         }
3909         /* if the read failed it could just be a mailbox collision, best wait
3910          * until we are called again and don't report an error
3911          */
3912         if (mbx->ops.read(hw, &in_msg, 1, 0))
3913                 goto out;
3914
3915         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3916                 /* msg is not CTS and is NACK we must have lost CTS status */
3917                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3918                         ret_val = -1;
3919                 goto out;
3920         }
3921
3922         /* the pf is talking, if we timed out in the past we reinit */
3923         if (!mbx->timeout) {
3924                 ret_val = -1;
3925                 goto out;
3926         }
3927
3928         /* if we passed all the tests above then the link is up and we no
3929          * longer need to check for link
3930          */
3931         mac->get_link_status = false;
3932
3933 out:
3934         *link_up = !mac->get_link_status;
3935         return ret_val;
3936 }
3937
3938 /* return 0 means link status changed, -1 means not changed */
3939 static int
3940 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3941                             int wait_to_complete, int vf)
3942 {
3943         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944         struct rte_eth_link link, old;
3945         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3946         struct ixgbe_interrupt *intr =
3947                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3948         int link_up;
3949         int diag;
3950         u32 speed = 0;
3951         int wait = 1;
3952         bool autoneg = false;
3953
3954         link.link_status = ETH_LINK_DOWN;
3955         link.link_speed = 0;
3956         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3957         link.link_autoneg = ETH_LINK_AUTONEG;
3958         memset(&old, 0, sizeof(old));
3959         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3960
3961         hw->mac.get_link_status = true;
3962
3963         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3964                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3965                 speed = hw->phy.autoneg_advertised;
3966                 if (!speed)
3967                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3968                 ixgbe_setup_link(hw, speed, true);
3969         }
3970
3971         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3972         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3973                 wait = 0;
3974
3975         if (vf)
3976                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3977         else
3978                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3979
3980         if (diag != 0) {
3981                 link.link_speed = ETH_SPEED_NUM_100M;
3982                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3983                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3984                 if (link.link_status == old.link_status)
3985                         return -1;
3986                 return 0;
3987         }
3988
3989         if (link_up == 0) {
3990                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3991                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3992                 if (link.link_status == old.link_status)
3993                         return -1;
3994                 return 0;
3995         }
3996         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3997         link.link_status = ETH_LINK_UP;
3998         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3999
4000         switch (link_speed) {
4001         default:
4002         case IXGBE_LINK_SPEED_UNKNOWN:
4003                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4004                 link.link_speed = ETH_SPEED_NUM_100M;
4005                 break;
4006
4007         case IXGBE_LINK_SPEED_100_FULL:
4008                 link.link_speed = ETH_SPEED_NUM_100M;
4009                 break;
4010
4011         case IXGBE_LINK_SPEED_1GB_FULL:
4012                 link.link_speed = ETH_SPEED_NUM_1G;
4013                 break;
4014
4015         case IXGBE_LINK_SPEED_2_5GB_FULL:
4016                 link.link_speed = ETH_SPEED_NUM_2_5G;
4017                 break;
4018
4019         case IXGBE_LINK_SPEED_5GB_FULL:
4020                 link.link_speed = ETH_SPEED_NUM_5G;
4021                 break;
4022
4023         case IXGBE_LINK_SPEED_10GB_FULL:
4024                 link.link_speed = ETH_SPEED_NUM_10G;
4025                 break;
4026         }
4027         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4028
4029         if (link.link_status == old.link_status)
4030                 return -1;
4031
4032         return 0;
4033 }
4034
4035 static int
4036 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4037 {
4038         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4039 }
4040
4041 static int
4042 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4043 {
4044         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4045 }
4046
4047 static void
4048 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4049 {
4050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4051         uint32_t fctrl;
4052
4053         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4054         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4055         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4056 }
4057
4058 static void
4059 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4060 {
4061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4062         uint32_t fctrl;
4063
4064         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4065         fctrl &= (~IXGBE_FCTRL_UPE);
4066         if (dev->data->all_multicast == 1)
4067                 fctrl |= IXGBE_FCTRL_MPE;
4068         else
4069                 fctrl &= (~IXGBE_FCTRL_MPE);
4070         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4071 }
4072
4073 static void
4074 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4075 {
4076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4077         uint32_t fctrl;
4078
4079         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4080         fctrl |= IXGBE_FCTRL_MPE;
4081         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4082 }
4083
4084 static void
4085 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4086 {
4087         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4088         uint32_t fctrl;
4089
4090         if (dev->data->promiscuous == 1)
4091                 return; /* must remain in all_multicast mode */
4092
4093         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4094         fctrl &= (~IXGBE_FCTRL_MPE);
4095         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4096 }
4097
4098 /**
4099  * It clears the interrupt causes and enables the interrupt.
4100  * It will be called once only during nic initialized.
4101  *
4102  * @param dev
4103  *  Pointer to struct rte_eth_dev.
4104  * @param on
4105  *  Enable or Disable.
4106  *
4107  * @return
4108  *  - On success, zero.
4109  *  - On failure, a negative value.
4110  */
4111 static int
4112 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4113 {
4114         struct ixgbe_interrupt *intr =
4115                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4116
4117         ixgbe_dev_link_status_print(dev);
4118         if (on)
4119                 intr->mask |= IXGBE_EICR_LSC;
4120         else
4121                 intr->mask &= ~IXGBE_EICR_LSC;
4122
4123         return 0;
4124 }
4125
4126 /**
4127  * It clears the interrupt causes and enables the interrupt.
4128  * It will be called once only during nic initialized.
4129  *
4130  * @param dev
4131  *  Pointer to struct rte_eth_dev.
4132  *
4133  * @return
4134  *  - On success, zero.
4135  *  - On failure, a negative value.
4136  */
4137 static int
4138 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4139 {
4140         struct ixgbe_interrupt *intr =
4141                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4142
4143         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4144
4145         return 0;
4146 }
4147
4148 /**
4149  * It clears the interrupt causes and enables the interrupt.
4150  * It will be called once only during nic initialized.
4151  *
4152  * @param dev
4153  *  Pointer to struct rte_eth_dev.
4154  *
4155  * @return
4156  *  - On success, zero.
4157  *  - On failure, a negative value.
4158  */
4159 static int
4160 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4161 {
4162         struct ixgbe_interrupt *intr =
4163                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4164
4165         intr->mask |= IXGBE_EICR_LINKSEC;
4166
4167         return 0;
4168 }
4169
4170 /*
4171  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4172  *
4173  * @param dev
4174  *  Pointer to struct rte_eth_dev.
4175  *
4176  * @return
4177  *  - On success, zero.
4178  *  - On failure, a negative value.
4179  */
4180 static int
4181 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4182 {
4183         uint32_t eicr;
4184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4185         struct ixgbe_interrupt *intr =
4186                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4187
4188         /* clear all cause mask */
4189         ixgbe_disable_intr(hw);
4190
4191         /* read-on-clear nic registers here */
4192         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4193         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4194
4195         intr->flags = 0;
4196
4197         /* set flag for async link update */
4198         if (eicr & IXGBE_EICR_LSC)
4199                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4200
4201         if (eicr & IXGBE_EICR_MAILBOX)
4202                 intr->flags |= IXGBE_FLAG_MAILBOX;
4203
4204         if (eicr & IXGBE_EICR_LINKSEC)
4205                 intr->flags |= IXGBE_FLAG_MACSEC;
4206
4207         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4208             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4209             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4210                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4211
4212         return 0;
4213 }
4214
4215 /**
4216  * It gets and then prints the link status.
4217  *
4218  * @param dev
4219  *  Pointer to struct rte_eth_dev.
4220  *
4221  * @return
4222  *  - On success, zero.
4223  *  - On failure, a negative value.
4224  */
4225 static void
4226 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4227 {
4228         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4229         struct rte_eth_link link;
4230
4231         memset(&link, 0, sizeof(link));
4232         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4233         if (link.link_status) {
4234                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4235                                         (int)(dev->data->port_id),
4236                                         (unsigned)link.link_speed,
4237                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4238                                         "full-duplex" : "half-duplex");
4239         } else {
4240                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4241                                 (int)(dev->data->port_id));
4242         }
4243         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4244                                 pci_dev->addr.domain,
4245                                 pci_dev->addr.bus,
4246                                 pci_dev->addr.devid,
4247                                 pci_dev->addr.function);
4248 }
4249
4250 /*
4251  * It executes link_update after knowing an interrupt occurred.
4252  *
4253  * @param dev
4254  *  Pointer to struct rte_eth_dev.
4255  *
4256  * @return
4257  *  - On success, zero.
4258  *  - On failure, a negative value.
4259  */
4260 static int
4261 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4262                            struct rte_intr_handle *intr_handle)
4263 {
4264         struct ixgbe_interrupt *intr =
4265                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4266         int64_t timeout;
4267         struct rte_eth_link link;
4268         struct ixgbe_hw *hw =
4269                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4270
4271         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4272
4273         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4274                 ixgbe_pf_mbx_process(dev);
4275                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4276         }
4277
4278         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4279                 ixgbe_handle_lasi(hw);
4280                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4281         }
4282
4283         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4284                 /* get the link status before link update, for predicting later */
4285                 memset(&link, 0, sizeof(link));
4286                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4287
4288                 ixgbe_dev_link_update(dev, 0);
4289
4290                 /* likely to up */
4291                 if (!link.link_status)
4292                         /* handle it 1 sec later, wait it being stable */
4293                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4294                 /* likely to down */
4295                 else
4296                         /* handle it 4 sec later, wait it being stable */
4297                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4298
4299                 ixgbe_dev_link_status_print(dev);
4300                 if (rte_eal_alarm_set(timeout * 1000,
4301                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4302                         PMD_DRV_LOG(ERR, "Error setting alarm");
4303                 else {
4304                         /* remember original mask */
4305                         intr->mask_original = intr->mask;
4306                         /* only disable lsc interrupt */
4307                         intr->mask &= ~IXGBE_EIMS_LSC;
4308                 }
4309         }
4310
4311         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4312         ixgbe_enable_intr(dev);
4313         rte_intr_enable(intr_handle);
4314
4315         return 0;
4316 }
4317
4318 /**
4319  * Interrupt handler which shall be registered for alarm callback for delayed
4320  * handling specific interrupt to wait for the stable nic state. As the
4321  * NIC interrupt state is not stable for ixgbe after link is just down,
4322  * it needs to wait 4 seconds to get the stable status.
4323  *
4324  * @param handle
4325  *  Pointer to interrupt handle.
4326  * @param param
4327  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4328  *
4329  * @return
4330  *  void
4331  */
4332 static void
4333 ixgbe_dev_interrupt_delayed_handler(void *param)
4334 {
4335         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4336         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4337         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4338         struct ixgbe_interrupt *intr =
4339                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4340         struct ixgbe_hw *hw =
4341                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342         uint32_t eicr;
4343
4344         ixgbe_disable_intr(hw);
4345
4346         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4347         if (eicr & IXGBE_EICR_MAILBOX)
4348                 ixgbe_pf_mbx_process(dev);
4349
4350         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4351                 ixgbe_handle_lasi(hw);
4352                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4353         }
4354
4355         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4356                 ixgbe_dev_link_update(dev, 0);
4357                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4358                 ixgbe_dev_link_status_print(dev);
4359                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4360                                               NULL, NULL);
4361         }
4362
4363         if (intr->flags & IXGBE_FLAG_MACSEC) {
4364                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4365                                               NULL, NULL);
4366                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4367         }
4368
4369         /* restore original mask */
4370         intr->mask = intr->mask_original;
4371         intr->mask_original = 0;
4372
4373         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4374         ixgbe_enable_intr(dev);
4375         rte_intr_enable(intr_handle);
4376 }
4377
4378 /**
4379  * Interrupt handler triggered by NIC  for handling
4380  * specific interrupt.
4381  *
4382  * @param handle
4383  *  Pointer to interrupt handle.
4384  * @param param
4385  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4386  *
4387  * @return
4388  *  void
4389  */
4390 static void
4391 ixgbe_dev_interrupt_handler(void *param)
4392 {
4393         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4394
4395         ixgbe_dev_interrupt_get_status(dev);
4396         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4397 }
4398
4399 static int
4400 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4401 {
4402         struct ixgbe_hw *hw;
4403
4404         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4405         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4406 }
4407
4408 static int
4409 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4410 {
4411         struct ixgbe_hw *hw;
4412
4413         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4414         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4415 }
4416
4417 static int
4418 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4419 {
4420         struct ixgbe_hw *hw;
4421         uint32_t mflcn_reg;
4422         uint32_t fccfg_reg;
4423         int rx_pause;
4424         int tx_pause;
4425
4426         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4427
4428         fc_conf->pause_time = hw->fc.pause_time;
4429         fc_conf->high_water = hw->fc.high_water[0];
4430         fc_conf->low_water = hw->fc.low_water[0];
4431         fc_conf->send_xon = hw->fc.send_xon;
4432         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4433
4434         /*
4435          * Return rx_pause status according to actual setting of
4436          * MFLCN register.
4437          */
4438         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4439         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4440                 rx_pause = 1;
4441         else
4442                 rx_pause = 0;
4443
4444         /*
4445          * Return tx_pause status according to actual setting of
4446          * FCCFG register.
4447          */
4448         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4449         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4450                 tx_pause = 1;
4451         else
4452                 tx_pause = 0;
4453
4454         if (rx_pause && tx_pause)
4455                 fc_conf->mode = RTE_FC_FULL;
4456         else if (rx_pause)
4457                 fc_conf->mode = RTE_FC_RX_PAUSE;
4458         else if (tx_pause)
4459                 fc_conf->mode = RTE_FC_TX_PAUSE;
4460         else
4461                 fc_conf->mode = RTE_FC_NONE;
4462
4463         return 0;
4464 }
4465
4466 static int
4467 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4468 {
4469         struct ixgbe_hw *hw;
4470         int err;
4471         uint32_t rx_buf_size;
4472         uint32_t max_high_water;
4473         uint32_t mflcn;
4474         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4475                 ixgbe_fc_none,
4476                 ixgbe_fc_rx_pause,
4477                 ixgbe_fc_tx_pause,
4478                 ixgbe_fc_full
4479         };
4480
4481         PMD_INIT_FUNC_TRACE();
4482
4483         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4485         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4486
4487         /*
4488          * At least reserve one Ethernet frame for watermark
4489          * high_water/low_water in kilo bytes for ixgbe
4490          */
4491         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4492         if ((fc_conf->high_water > max_high_water) ||
4493                 (fc_conf->high_water < fc_conf->low_water)) {
4494                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4495                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4496                 return -EINVAL;
4497         }
4498
4499         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4500         hw->fc.pause_time     = fc_conf->pause_time;
4501         hw->fc.high_water[0]  = fc_conf->high_water;
4502         hw->fc.low_water[0]   = fc_conf->low_water;
4503         hw->fc.send_xon       = fc_conf->send_xon;
4504         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4505
4506         err = ixgbe_fc_enable(hw);
4507
4508         /* Not negotiated is not an error case */
4509         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4510
4511                 /* check if we want to forward MAC frames - driver doesn't have native
4512                  * capability to do that, so we'll write the registers ourselves */
4513
4514                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4515
4516                 /* set or clear MFLCN.PMCF bit depending on configuration */
4517                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4518                         mflcn |= IXGBE_MFLCN_PMCF;
4519                 else
4520                         mflcn &= ~IXGBE_MFLCN_PMCF;
4521
4522                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4523                 IXGBE_WRITE_FLUSH(hw);
4524
4525                 return 0;
4526         }
4527
4528         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4529         return -EIO;
4530 }
4531
4532 /**
4533  *  ixgbe_pfc_enable_generic - Enable flow control
4534  *  @hw: pointer to hardware structure
4535  *  @tc_num: traffic class number
4536  *  Enable flow control according to the current settings.
4537  */
4538 static int
4539 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4540 {
4541         int ret_val = 0;
4542         uint32_t mflcn_reg, fccfg_reg;
4543         uint32_t reg;
4544         uint32_t fcrtl, fcrth;
4545         uint8_t i;
4546         uint8_t nb_rx_en;
4547
4548         /* Validate the water mark configuration */
4549         if (!hw->fc.pause_time) {
4550                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4551                 goto out;
4552         }
4553
4554         /* Low water mark of zero causes XOFF floods */
4555         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4556                  /* High/Low water can not be 0 */
4557                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4558                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4559                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4560                         goto out;
4561                 }
4562
4563                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4564                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4565                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4566                         goto out;
4567                 }
4568         }
4569         /* Negotiate the fc mode to use */
4570         ixgbe_fc_autoneg(hw);
4571
4572         /* Disable any previous flow control settings */
4573         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4574         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4575
4576         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4577         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4578
4579         switch (hw->fc.current_mode) {
4580         case ixgbe_fc_none:
4581                 /*
4582                  * If the count of enabled RX Priority Flow control >1,
4583                  * and the TX pause can not be disabled
4584                  */
4585                 nb_rx_en = 0;
4586                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4587                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4588                         if (reg & IXGBE_FCRTH_FCEN)
4589                                 nb_rx_en++;
4590                 }
4591                 if (nb_rx_en > 1)
4592                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4593                 break;
4594         case ixgbe_fc_rx_pause:
4595                 /*
4596                  * Rx Flow control is enabled and Tx Flow control is
4597                  * disabled by software override. Since there really
4598                  * isn't a way to advertise that we are capable of RX
4599                  * Pause ONLY, we will advertise that we support both
4600                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4601                  * disable the adapter's ability to send PAUSE frames.
4602                  */
4603                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4604                 /*
4605                  * If the count of enabled RX Priority Flow control >1,
4606                  * and the TX pause can not be disabled
4607                  */
4608                 nb_rx_en = 0;
4609                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4610                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4611                         if (reg & IXGBE_FCRTH_FCEN)
4612                                 nb_rx_en++;
4613                 }
4614                 if (nb_rx_en > 1)
4615                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4616                 break;
4617         case ixgbe_fc_tx_pause:
4618                 /*
4619                  * Tx Flow control is enabled, and Rx Flow control is
4620                  * disabled by software override.
4621                  */
4622                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4623                 break;
4624         case ixgbe_fc_full:
4625                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4626                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4627                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4628                 break;
4629         default:
4630                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4631                 ret_val = IXGBE_ERR_CONFIG;
4632                 goto out;
4633         }
4634
4635         /* Set 802.3x based flow control settings. */
4636         mflcn_reg |= IXGBE_MFLCN_DPF;
4637         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4638         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4639
4640         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4641         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4642                 hw->fc.high_water[tc_num]) {
4643                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4644                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4645                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4646         } else {
4647                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4648                 /*
4649                  * In order to prevent Tx hangs when the internal Tx
4650                  * switch is enabled we must set the high water mark
4651                  * to the maximum FCRTH value.  This allows the Tx
4652                  * switch to function even under heavy Rx workloads.
4653                  */
4654                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4655         }
4656         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4657
4658         /* Configure pause time (2 TCs per register) */
4659         reg = hw->fc.pause_time * 0x00010001;
4660         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4661                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4662
4663         /* Configure flow control refresh threshold value */
4664         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4665
4666 out:
4667         return ret_val;
4668 }
4669
4670 static int
4671 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4672 {
4673         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4674         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4675
4676         if (hw->mac.type != ixgbe_mac_82598EB) {
4677                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4678         }
4679         return ret_val;
4680 }
4681
4682 static int
4683 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4684 {
4685         int err;
4686         uint32_t rx_buf_size;
4687         uint32_t max_high_water;
4688         uint8_t tc_num;
4689         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4690         struct ixgbe_hw *hw =
4691                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4692         struct ixgbe_dcb_config *dcb_config =
4693                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4694
4695         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4696                 ixgbe_fc_none,
4697                 ixgbe_fc_rx_pause,
4698                 ixgbe_fc_tx_pause,
4699                 ixgbe_fc_full
4700         };
4701
4702         PMD_INIT_FUNC_TRACE();
4703
4704         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4705         tc_num = map[pfc_conf->priority];
4706         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4707         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4708         /*
4709          * At least reserve one Ethernet frame for watermark
4710          * high_water/low_water in kilo bytes for ixgbe
4711          */
4712         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4713         if ((pfc_conf->fc.high_water > max_high_water) ||
4714             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4715                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4716                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4717                 return -EINVAL;
4718         }
4719
4720         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4721         hw->fc.pause_time = pfc_conf->fc.pause_time;
4722         hw->fc.send_xon = pfc_conf->fc.send_xon;
4723         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4724         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4725
4726         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4727
4728         /* Not negotiated is not an error case */
4729         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4730                 return 0;
4731
4732         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4733         return -EIO;
4734 }
4735
4736 static int
4737 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4738                           struct rte_eth_rss_reta_entry64 *reta_conf,
4739                           uint16_t reta_size)
4740 {
4741         uint16_t i, sp_reta_size;
4742         uint8_t j, mask;
4743         uint32_t reta, r;
4744         uint16_t idx, shift;
4745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4746         uint32_t reta_reg;
4747
4748         PMD_INIT_FUNC_TRACE();
4749
4750         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4751                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4752                         "NIC.");
4753                 return -ENOTSUP;
4754         }
4755
4756         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4757         if (reta_size != sp_reta_size) {
4758                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4759                         "(%d) doesn't match the number hardware can supported "
4760                         "(%d)", reta_size, sp_reta_size);
4761                 return -EINVAL;
4762         }
4763
4764         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4765                 idx = i / RTE_RETA_GROUP_SIZE;
4766                 shift = i % RTE_RETA_GROUP_SIZE;
4767                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4768                                                 IXGBE_4_BIT_MASK);
4769                 if (!mask)
4770                         continue;
4771                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4772                 if (mask == IXGBE_4_BIT_MASK)
4773                         r = 0;
4774                 else
4775                         r = IXGBE_READ_REG(hw, reta_reg);
4776                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4777                         if (mask & (0x1 << j))
4778                                 reta |= reta_conf[idx].reta[shift + j] <<
4779                                                         (CHAR_BIT * j);
4780                         else
4781                                 reta |= r & (IXGBE_8_BIT_MASK <<
4782                                                 (CHAR_BIT * j));
4783                 }
4784                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4785         }
4786
4787         return 0;
4788 }
4789
4790 static int
4791 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4792                          struct rte_eth_rss_reta_entry64 *reta_conf,
4793                          uint16_t reta_size)
4794 {
4795         uint16_t i, sp_reta_size;
4796         uint8_t j, mask;
4797         uint32_t reta;
4798         uint16_t idx, shift;
4799         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800         uint32_t reta_reg;
4801
4802         PMD_INIT_FUNC_TRACE();
4803         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4804         if (reta_size != sp_reta_size) {
4805                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4806                         "(%d) doesn't match the number hardware can supported "
4807                         "(%d)", reta_size, sp_reta_size);
4808                 return -EINVAL;
4809         }
4810
4811         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4812                 idx = i / RTE_RETA_GROUP_SIZE;
4813                 shift = i % RTE_RETA_GROUP_SIZE;
4814                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4815                                                 IXGBE_4_BIT_MASK);
4816                 if (!mask)
4817                         continue;
4818
4819                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4820                 reta = IXGBE_READ_REG(hw, reta_reg);
4821                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4822                         if (mask & (0x1 << j))
4823                                 reta_conf[idx].reta[shift + j] =
4824                                         ((reta >> (CHAR_BIT * j)) &
4825                                                 IXGBE_8_BIT_MASK);
4826                 }
4827         }
4828
4829         return 0;
4830 }
4831
4832 static int
4833 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4834                                 uint32_t index, uint32_t pool)
4835 {
4836         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4837         uint32_t enable_addr = 1;
4838
4839         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4840                              pool, enable_addr);
4841 }
4842
4843 static void
4844 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4845 {
4846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4847
4848         ixgbe_clear_rar(hw, index);
4849 }
4850
4851 static void
4852 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4853 {
4854         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4855
4856         ixgbe_remove_rar(dev, 0);
4857
4858         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4859 }
4860
4861 static bool
4862 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4863 {
4864         if (strcmp(dev->device->driver->name, drv->driver.name))
4865                 return false;
4866
4867         return true;
4868 }
4869
4870 bool
4871 is_ixgbe_supported(struct rte_eth_dev *dev)
4872 {
4873         return is_device_supported(dev, &rte_ixgbe_pmd);
4874 }
4875
4876 static int
4877 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4878 {
4879         uint32_t hlreg0;
4880         uint32_t maxfrs;
4881         struct ixgbe_hw *hw;
4882         struct rte_eth_dev_info dev_info;
4883         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4884         struct rte_eth_dev_data *dev_data = dev->data;
4885
4886         ixgbe_dev_info_get(dev, &dev_info);
4887
4888         /* check that mtu is within the allowed range */
4889         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4890                 return -EINVAL;
4891
4892         /* If device is started, refuse mtu that requires the support of
4893          * scattered packets when this feature has not been enabled before.
4894          */
4895         if (dev_data->dev_started && !dev_data->scattered_rx &&
4896             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4897              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4898                 PMD_INIT_LOG(ERR, "Stop port first.");
4899                 return -EINVAL;
4900         }
4901
4902         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4903         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4904
4905         /* switch to jumbo mode if needed */
4906         if (frame_size > ETHER_MAX_LEN) {
4907                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4908                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4909         } else {
4910                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4911                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4912         }
4913         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4914
4915         /* update max frame size */
4916         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4917
4918         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4919         maxfrs &= 0x0000FFFF;
4920         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4921         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4922
4923         return 0;
4924 }
4925
4926 /*
4927  * Virtual Function operations
4928  */
4929 static void
4930 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4931 {
4932         PMD_INIT_FUNC_TRACE();
4933
4934         /* Clear interrupt mask to stop from interrupts being generated */
4935         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4936
4937         IXGBE_WRITE_FLUSH(hw);
4938 }
4939
4940 static void
4941 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4942 {
4943         PMD_INIT_FUNC_TRACE();
4944
4945         /* VF enable interrupt autoclean */
4946         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4947         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4948         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4949
4950         IXGBE_WRITE_FLUSH(hw);
4951 }
4952
4953 static int
4954 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4955 {
4956         struct rte_eth_conf *conf = &dev->data->dev_conf;
4957         struct ixgbe_adapter *adapter =
4958                         (struct ixgbe_adapter *)dev->data->dev_private;
4959
4960         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4961                      dev->data->port_id);
4962
4963         /*
4964          * VF has no ability to enable/disable HW CRC
4965          * Keep the persistent behavior the same as Host PF
4966          */
4967 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4968         if (!conf->rxmode.hw_strip_crc) {
4969                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4970                 conf->rxmode.hw_strip_crc = 1;
4971         }
4972 #else
4973         if (conf->rxmode.hw_strip_crc) {
4974                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4975                 conf->rxmode.hw_strip_crc = 0;
4976         }
4977 #endif
4978
4979         /*
4980          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4981          * allocation or vector Rx preconditions we will reset it.
4982          */
4983         adapter->rx_bulk_alloc_allowed = true;
4984         adapter->rx_vec_allowed = true;
4985
4986         return 0;
4987 }
4988
4989 static int
4990 ixgbevf_dev_start(struct rte_eth_dev *dev)
4991 {
4992         struct ixgbe_hw *hw =
4993                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4994         uint32_t intr_vector = 0;
4995         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4996         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4997
4998         int err, mask = 0;
4999
5000         PMD_INIT_FUNC_TRACE();
5001
5002         hw->mac.ops.reset_hw(hw);
5003         hw->mac.get_link_status = true;
5004
5005         /* negotiate mailbox API version to use with the PF. */
5006         ixgbevf_negotiate_api(hw);
5007
5008         ixgbevf_dev_tx_init(dev);
5009
5010         /* This can fail when allocating mbufs for descriptor rings */
5011         err = ixgbevf_dev_rx_init(dev);
5012         if (err) {
5013                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5014                 ixgbe_dev_clear_queues(dev);
5015                 return err;
5016         }
5017
5018         /* Set vfta */
5019         ixgbevf_set_vfta_all(dev, 1);
5020
5021         /* Set HW strip */
5022         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5023                 ETH_VLAN_EXTEND_MASK;
5024         err = ixgbevf_vlan_offload_set(dev, mask);
5025         if (err) {
5026                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5027                 ixgbe_dev_clear_queues(dev);
5028                 return err;
5029         }
5030
5031         ixgbevf_dev_rxtx_start(dev);
5032
5033         /* check and configure queue intr-vector mapping */
5034         if (dev->data->dev_conf.intr_conf.rxq != 0) {
5035                 /* According to datasheet, only vector 0/1/2 can be used,
5036                  * now only one vector is used for Rx queue
5037                  */
5038                 intr_vector = 1;
5039                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5040                         return -1;
5041         }
5042
5043         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5044                 intr_handle->intr_vec =
5045                         rte_zmalloc("intr_vec",
5046                                     dev->data->nb_rx_queues * sizeof(int), 0);
5047                 if (intr_handle->intr_vec == NULL) {
5048                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5049                                      " intr_vec", dev->data->nb_rx_queues);
5050                         return -ENOMEM;
5051                 }
5052         }
5053         ixgbevf_configure_msix(dev);
5054
5055         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5056          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5057          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5058          * is not cleared, it will fail when following rte_intr_enable( ) tries
5059          * to map Rx queue interrupt to other VFIO vectors.
5060          * So clear uio/vfio intr/evevnfd first to avoid failure.
5061          */
5062         rte_intr_disable(intr_handle);
5063
5064         rte_intr_enable(intr_handle);
5065
5066         /* Re-enable interrupt for VF */
5067         ixgbevf_intr_enable(hw);
5068
5069         return 0;
5070 }
5071
5072 static void
5073 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5074 {
5075         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5076         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5077         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5078
5079         PMD_INIT_FUNC_TRACE();
5080
5081         ixgbevf_intr_disable(hw);
5082
5083         hw->adapter_stopped = 1;
5084         ixgbe_stop_adapter(hw);
5085
5086         /*
5087           * Clear what we set, but we still keep shadow_vfta to
5088           * restore after device starts
5089           */
5090         ixgbevf_set_vfta_all(dev, 0);
5091
5092         /* Clear stored conf */
5093         dev->data->scattered_rx = 0;
5094
5095         ixgbe_dev_clear_queues(dev);
5096
5097         /* Clean datapath event and queue/vec mapping */
5098         rte_intr_efd_disable(intr_handle);
5099         if (intr_handle->intr_vec != NULL) {
5100                 rte_free(intr_handle->intr_vec);
5101                 intr_handle->intr_vec = NULL;
5102         }
5103 }
5104
5105 static void
5106 ixgbevf_dev_close(struct rte_eth_dev *dev)
5107 {
5108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109
5110         PMD_INIT_FUNC_TRACE();
5111
5112         ixgbe_reset_hw(hw);
5113
5114         ixgbevf_dev_stop(dev);
5115
5116         ixgbe_dev_free_queues(dev);
5117
5118         /**
5119          * Remove the VF MAC address ro ensure
5120          * that the VF traffic goes to the PF
5121          * after stop, close and detach of the VF
5122          **/
5123         ixgbevf_remove_mac_addr(dev, 0);
5124 }
5125
5126 /*
5127  * Reset VF device
5128  */
5129 static int
5130 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5131 {
5132         int ret;
5133
5134         ret = eth_ixgbevf_dev_uninit(dev);
5135         if (ret)
5136                 return ret;
5137
5138         ret = eth_ixgbevf_dev_init(dev);
5139
5140         return ret;
5141 }
5142
5143 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5144 {
5145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5146         struct ixgbe_vfta *shadow_vfta =
5147                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5148         int i = 0, j = 0, vfta = 0, mask = 1;
5149
5150         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5151                 vfta = shadow_vfta->vfta[i];
5152                 if (vfta) {
5153                         mask = 1;
5154                         for (j = 0; j < 32; j++) {
5155                                 if (vfta & mask)
5156                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5157                                                        on, false);
5158                                 mask <<= 1;
5159                         }
5160                 }
5161         }
5162
5163 }
5164
5165 static int
5166 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5167 {
5168         struct ixgbe_hw *hw =
5169                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5170         struct ixgbe_vfta *shadow_vfta =
5171                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5172         uint32_t vid_idx = 0;
5173         uint32_t vid_bit = 0;
5174         int ret = 0;
5175
5176         PMD_INIT_FUNC_TRACE();
5177
5178         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5179         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5180         if (ret) {
5181                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5182                 return ret;
5183         }
5184         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5185         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5186
5187         /* Save what we set and retore it after device reset */
5188         if (on)
5189                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5190         else
5191                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5192
5193         return 0;
5194 }
5195
5196 static void
5197 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5198 {
5199         struct ixgbe_hw *hw =
5200                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201         uint32_t ctrl;
5202
5203         PMD_INIT_FUNC_TRACE();
5204
5205         if (queue >= hw->mac.max_rx_queues)
5206                 return;
5207
5208         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5209         if (on)
5210                 ctrl |= IXGBE_RXDCTL_VME;
5211         else
5212                 ctrl &= ~IXGBE_RXDCTL_VME;
5213         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5214
5215         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5216 }
5217
5218 static int
5219 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5220 {
5221         struct ixgbe_hw *hw =
5222                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5223         uint16_t i;
5224         int on = 0;
5225
5226         /* VF function only support hw strip feature, others are not support */
5227         if (mask & ETH_VLAN_STRIP_MASK) {
5228                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5229
5230                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5231                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5232         }
5233
5234         return 0;
5235 }
5236
5237 int
5238 ixgbe_vt_check(struct ixgbe_hw *hw)
5239 {
5240         uint32_t reg_val;
5241
5242         /* if Virtualization Technology is enabled */
5243         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5244         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5245                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5246                 return -1;
5247         }
5248
5249         return 0;
5250 }
5251
5252 static uint32_t
5253 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5254 {
5255         uint32_t vector = 0;
5256
5257         switch (hw->mac.mc_filter_type) {
5258         case 0:   /* use bits [47:36] of the address */
5259                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5260                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5261                 break;
5262         case 1:   /* use bits [46:35] of the address */
5263                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5264                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5265                 break;
5266         case 2:   /* use bits [45:34] of the address */
5267                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5268                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5269                 break;
5270         case 3:   /* use bits [43:32] of the address */
5271                 vector = ((uc_addr->addr_bytes[4]) |
5272                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5273                 break;
5274         default:  /* Invalid mc_filter_type */
5275                 break;
5276         }
5277
5278         /* vector can only be 12-bits or boundary will be exceeded */
5279         vector &= 0xFFF;
5280         return vector;
5281 }
5282
5283 static int
5284 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5285                         uint8_t on)
5286 {
5287         uint32_t vector;
5288         uint32_t uta_idx;
5289         uint32_t reg_val;
5290         uint32_t uta_shift;
5291         uint32_t rc;
5292         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5293         const uint32_t ixgbe_uta_bit_shift = 5;
5294         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5295         const uint32_t bit1 = 0x1;
5296
5297         struct ixgbe_hw *hw =
5298                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5299         struct ixgbe_uta_info *uta_info =
5300                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5301
5302         /* The UTA table only exists on 82599 hardware and newer */
5303         if (hw->mac.type < ixgbe_mac_82599EB)
5304                 return -ENOTSUP;
5305
5306         vector = ixgbe_uta_vector(hw, mac_addr);
5307         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5308         uta_shift = vector & ixgbe_uta_bit_mask;
5309
5310         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5311         if (rc == on)
5312                 return 0;
5313
5314         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5315         if (on) {
5316                 uta_info->uta_in_use++;
5317                 reg_val |= (bit1 << uta_shift);
5318                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5319         } else {
5320                 uta_info->uta_in_use--;
5321                 reg_val &= ~(bit1 << uta_shift);
5322                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5323         }
5324
5325         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5326
5327         if (uta_info->uta_in_use > 0)
5328                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5329                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5330         else
5331                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5332
5333         return 0;
5334 }
5335
5336 static int
5337 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5338 {
5339         int i;
5340         struct ixgbe_hw *hw =
5341                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5342         struct ixgbe_uta_info *uta_info =
5343                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5344
5345         /* The UTA table only exists on 82599 hardware and newer */
5346         if (hw->mac.type < ixgbe_mac_82599EB)
5347                 return -ENOTSUP;
5348
5349         if (on) {
5350                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5351                         uta_info->uta_shadow[i] = ~0;
5352                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5353                 }
5354         } else {
5355                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5356                         uta_info->uta_shadow[i] = 0;
5357                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5358                 }
5359         }
5360         return 0;
5361
5362 }
5363
5364 uint32_t
5365 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5366 {
5367         uint32_t new_val = orig_val;
5368
5369         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5370                 new_val |= IXGBE_VMOLR_AUPE;
5371         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5372                 new_val |= IXGBE_VMOLR_ROMPE;
5373         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5374                 new_val |= IXGBE_VMOLR_ROPE;
5375         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5376                 new_val |= IXGBE_VMOLR_BAM;
5377         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5378                 new_val |= IXGBE_VMOLR_MPE;
5379
5380         return new_val;
5381 }
5382
5383 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5384 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5385 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5386 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5387 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5388         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5389         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5390
5391 static int
5392 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5393                       struct rte_eth_mirror_conf *mirror_conf,
5394                       uint8_t rule_id, uint8_t on)
5395 {
5396         uint32_t mr_ctl, vlvf;
5397         uint32_t mp_lsb = 0;
5398         uint32_t mv_msb = 0;
5399         uint32_t mv_lsb = 0;
5400         uint32_t mp_msb = 0;
5401         uint8_t i = 0;
5402         int reg_index = 0;
5403         uint64_t vlan_mask = 0;
5404
5405         const uint8_t pool_mask_offset = 32;
5406         const uint8_t vlan_mask_offset = 32;
5407         const uint8_t dst_pool_offset = 8;
5408         const uint8_t rule_mr_offset  = 4;
5409         const uint8_t mirror_rule_mask = 0x0F;
5410
5411         struct ixgbe_mirror_info *mr_info =
5412                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5413         struct ixgbe_hw *hw =
5414                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5415         uint8_t mirror_type = 0;
5416
5417         if (ixgbe_vt_check(hw) < 0)
5418                 return -ENOTSUP;
5419
5420         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5421                 return -EINVAL;
5422
5423         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5424                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5425                             mirror_conf->rule_type);
5426                 return -EINVAL;
5427         }
5428
5429         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5430                 mirror_type |= IXGBE_MRCTL_VLME;
5431                 /* Check if vlan id is valid and find conresponding VLAN ID
5432                  * index in VLVF
5433                  */
5434                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5435                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5436                                 /* search vlan id related pool vlan filter
5437                                  * index
5438                                  */
5439                                 reg_index = ixgbe_find_vlvf_slot(
5440                                                 hw,
5441                                                 mirror_conf->vlan.vlan_id[i],
5442                                                 false);
5443                                 if (reg_index < 0)
5444                                         return -EINVAL;
5445                                 vlvf = IXGBE_READ_REG(hw,
5446                                                       IXGBE_VLVF(reg_index));
5447                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5448                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5449                                       mirror_conf->vlan.vlan_id[i]))
5450                                         vlan_mask |= (1ULL << reg_index);
5451                                 else
5452                                         return -EINVAL;
5453                         }
5454                 }
5455
5456                 if (on) {
5457                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5458                         mv_msb = vlan_mask >> vlan_mask_offset;
5459
5460                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5461                                                 mirror_conf->vlan.vlan_mask;
5462                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5463                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5464                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5465                                                 mirror_conf->vlan.vlan_id[i];
5466                         }
5467                 } else {
5468                         mv_lsb = 0;
5469                         mv_msb = 0;
5470                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5471                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5472                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5473                 }
5474         }
5475
5476         /**
5477          * if enable pool mirror, write related pool mask register,if disable
5478          * pool mirror, clear PFMRVM register
5479          */
5480         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5481                 mirror_type |= IXGBE_MRCTL_VPME;
5482                 if (on) {
5483                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5484                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5485                         mr_info->mr_conf[rule_id].pool_mask =
5486                                         mirror_conf->pool_mask;
5487
5488                 } else {
5489                         mp_lsb = 0;
5490                         mp_msb = 0;
5491                         mr_info->mr_conf[rule_id].pool_mask = 0;
5492                 }
5493         }
5494         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5495                 mirror_type |= IXGBE_MRCTL_UPME;
5496         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5497                 mirror_type |= IXGBE_MRCTL_DPME;
5498
5499         /* read  mirror control register and recalculate it */
5500         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5501
5502         if (on) {
5503                 mr_ctl |= mirror_type;
5504                 mr_ctl &= mirror_rule_mask;
5505                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5506         } else {
5507                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5508         }
5509
5510         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5511         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5512
5513         /* write mirrror control  register */
5514         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5515
5516         /* write pool mirrror control  register */
5517         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5518                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5519                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5520                                 mp_msb);
5521         }
5522         /* write VLAN mirrror control  register */
5523         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5524                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5525                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5526                                 mv_msb);
5527         }
5528
5529         return 0;
5530 }
5531
5532 static int
5533 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5534 {
5535         int mr_ctl = 0;
5536         uint32_t lsb_val = 0;
5537         uint32_t msb_val = 0;
5538         const uint8_t rule_mr_offset = 4;
5539
5540         struct ixgbe_hw *hw =
5541                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5542         struct ixgbe_mirror_info *mr_info =
5543                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5544
5545         if (ixgbe_vt_check(hw) < 0)
5546                 return -ENOTSUP;
5547
5548         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5549                 return -EINVAL;
5550
5551         memset(&mr_info->mr_conf[rule_id], 0,
5552                sizeof(struct rte_eth_mirror_conf));
5553
5554         /* clear PFVMCTL register */
5555         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5556
5557         /* clear pool mask register */
5558         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5559         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5560
5561         /* clear vlan mask register */
5562         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5563         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5564
5565         return 0;
5566 }
5567
5568 static int
5569 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5570 {
5571         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5572         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5573         uint32_t mask;
5574         struct ixgbe_hw *hw =
5575                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5576         uint32_t vec = IXGBE_MISC_VEC_ID;
5577
5578         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5579         if (rte_intr_allow_others(intr_handle))
5580                 vec = IXGBE_RX_VEC_START;
5581         mask |= (1 << vec);
5582         RTE_SET_USED(queue_id);
5583         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5584
5585         rte_intr_enable(intr_handle);
5586
5587         return 0;
5588 }
5589
5590 static int
5591 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5592 {
5593         uint32_t mask;
5594         struct ixgbe_hw *hw =
5595                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5596         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5597         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5598         uint32_t vec = IXGBE_MISC_VEC_ID;
5599
5600         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5601         if (rte_intr_allow_others(intr_handle))
5602                 vec = IXGBE_RX_VEC_START;
5603         mask &= ~(1 << vec);
5604         RTE_SET_USED(queue_id);
5605         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5606
5607         return 0;
5608 }
5609
5610 static int
5611 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5612 {
5613         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5614         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5615         uint32_t mask;
5616         struct ixgbe_hw *hw =
5617                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5618         struct ixgbe_interrupt *intr =
5619                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5620
5621         if (queue_id < 16) {
5622                 ixgbe_disable_intr(hw);
5623                 intr->mask |= (1 << queue_id);
5624                 ixgbe_enable_intr(dev);
5625         } else if (queue_id < 32) {
5626                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5627                 mask &= (1 << queue_id);
5628                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5629         } else if (queue_id < 64) {
5630                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5631                 mask &= (1 << (queue_id - 32));
5632                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5633         }
5634         rte_intr_enable(intr_handle);
5635
5636         return 0;
5637 }
5638
5639 static int
5640 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5641 {
5642         uint32_t mask;
5643         struct ixgbe_hw *hw =
5644                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5645         struct ixgbe_interrupt *intr =
5646                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5647
5648         if (queue_id < 16) {
5649                 ixgbe_disable_intr(hw);
5650                 intr->mask &= ~(1 << queue_id);
5651                 ixgbe_enable_intr(dev);
5652         } else if (queue_id < 32) {
5653                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5654                 mask &= ~(1 << queue_id);
5655                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5656         } else if (queue_id < 64) {
5657                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5658                 mask &= ~(1 << (queue_id - 32));
5659                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5660         }
5661
5662         return 0;
5663 }
5664
5665 static void
5666 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5667                      uint8_t queue, uint8_t msix_vector)
5668 {
5669         uint32_t tmp, idx;
5670
5671         if (direction == -1) {
5672                 /* other causes */
5673                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5674                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5675                 tmp &= ~0xFF;
5676                 tmp |= msix_vector;
5677                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5678         } else {
5679                 /* rx or tx cause */
5680                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5681                 idx = ((16 * (queue & 1)) + (8 * direction));
5682                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5683                 tmp &= ~(0xFF << idx);
5684                 tmp |= (msix_vector << idx);
5685                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5686         }
5687 }
5688
5689 /**
5690  * set the IVAR registers, mapping interrupt causes to vectors
5691  * @param hw
5692  *  pointer to ixgbe_hw struct
5693  * @direction
5694  *  0 for Rx, 1 for Tx, -1 for other causes
5695  * @queue
5696  *  queue to map the corresponding interrupt to
5697  * @msix_vector
5698  *  the vector to map to the corresponding queue
5699  */
5700 static void
5701 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5702                    uint8_t queue, uint8_t msix_vector)
5703 {
5704         uint32_t tmp, idx;
5705
5706         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5707         if (hw->mac.type == ixgbe_mac_82598EB) {
5708                 if (direction == -1)
5709                         direction = 0;
5710                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5711                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5712                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5713                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5714                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5715         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5716                         (hw->mac.type == ixgbe_mac_X540) ||
5717                         (hw->mac.type == ixgbe_mac_X550)) {
5718                 if (direction == -1) {
5719                         /* other causes */
5720                         idx = ((queue & 1) * 8);
5721                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5722                         tmp &= ~(0xFF << idx);
5723                         tmp |= (msix_vector << idx);
5724                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5725                 } else {
5726                         /* rx or tx causes */
5727                         idx = ((16 * (queue & 1)) + (8 * direction));
5728                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5729                         tmp &= ~(0xFF << idx);
5730                         tmp |= (msix_vector << idx);
5731                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5732                 }
5733         }
5734 }
5735
5736 static void
5737 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5738 {
5739         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5740         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5741         struct ixgbe_hw *hw =
5742                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5743         uint32_t q_idx;
5744         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5745         uint32_t base = IXGBE_MISC_VEC_ID;
5746
5747         /* Configure VF other cause ivar */
5748         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5749
5750         /* won't configure msix register if no mapping is done
5751          * between intr vector and event fd.
5752          */
5753         if (!rte_intr_dp_is_en(intr_handle))
5754                 return;
5755
5756         if (rte_intr_allow_others(intr_handle)) {
5757                 base = IXGBE_RX_VEC_START;
5758                 vector_idx = IXGBE_RX_VEC_START;
5759         }
5760
5761         /* Configure all RX queues of VF */
5762         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5763                 /* Force all queue use vector 0,
5764                  * as IXGBE_VF_MAXMSIVECOTR = 1
5765                  */
5766                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5767                 intr_handle->intr_vec[q_idx] = vector_idx;
5768                 if (vector_idx < base + intr_handle->nb_efd - 1)
5769                         vector_idx++;
5770         }
5771 }
5772
5773 /**
5774  * Sets up the hardware to properly generate MSI-X interrupts
5775  * @hw
5776  *  board private structure
5777  */
5778 static void
5779 ixgbe_configure_msix(struct rte_eth_dev *dev)
5780 {
5781         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5782         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5783         struct ixgbe_hw *hw =
5784                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5785         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5786         uint32_t vec = IXGBE_MISC_VEC_ID;
5787         uint32_t mask;
5788         uint32_t gpie;
5789
5790         /* won't configure msix register if no mapping is done
5791          * between intr vector and event fd
5792          */
5793         if (!rte_intr_dp_is_en(intr_handle))
5794                 return;
5795
5796         if (rte_intr_allow_others(intr_handle))
5797                 vec = base = IXGBE_RX_VEC_START;
5798
5799         /* setup GPIE for MSI-x mode */
5800         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5801         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5802                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5803         /* auto clearing and auto setting corresponding bits in EIMS
5804          * when MSI-X interrupt is triggered
5805          */
5806         if (hw->mac.type == ixgbe_mac_82598EB) {
5807                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5808         } else {
5809                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5810                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5811         }
5812         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5813
5814         /* Populate the IVAR table and set the ITR values to the
5815          * corresponding register.
5816          */
5817         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5818              queue_id++) {
5819                 /* by default, 1:1 mapping */
5820                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5821                 intr_handle->intr_vec[queue_id] = vec;
5822                 if (vec < base + intr_handle->nb_efd - 1)
5823                         vec++;
5824         }
5825
5826         switch (hw->mac.type) {
5827         case ixgbe_mac_82598EB:
5828                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5829                                    IXGBE_MISC_VEC_ID);
5830                 break;
5831         case ixgbe_mac_82599EB:
5832         case ixgbe_mac_X540:
5833         case ixgbe_mac_X550:
5834                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5835                 break;
5836         default:
5837                 break;
5838         }
5839         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5840                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5841
5842         /* set up to autoclear timer, and the vectors */
5843         mask = IXGBE_EIMS_ENABLE_MASK;
5844         mask &= ~(IXGBE_EIMS_OTHER |
5845                   IXGBE_EIMS_MAILBOX |
5846                   IXGBE_EIMS_LSC);
5847
5848         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5849 }
5850
5851 int
5852 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5853                            uint16_t queue_idx, uint16_t tx_rate)
5854 {
5855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5856         uint32_t rf_dec, rf_int;
5857         uint32_t bcnrc_val;
5858         uint16_t link_speed = dev->data->dev_link.link_speed;
5859
5860         if (queue_idx >= hw->mac.max_tx_queues)
5861                 return -EINVAL;
5862
5863         if (tx_rate != 0) {
5864                 /* Calculate the rate factor values to set */
5865                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5866                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5867                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5868
5869                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5870                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5871                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5872                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5873         } else {
5874                 bcnrc_val = 0;
5875         }
5876
5877         /*
5878          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5879          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5880          * set as 0x4.
5881          */
5882         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5883                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5884                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5885                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5886                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5887         else
5888                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5889                         IXGBE_MMW_SIZE_DEFAULT);
5890
5891         /* Set RTTBCNRC of queue X */
5892         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5893         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5894         IXGBE_WRITE_FLUSH(hw);
5895
5896         return 0;
5897 }
5898
5899 static int
5900 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5901                      __attribute__((unused)) uint32_t index,
5902                      __attribute__((unused)) uint32_t pool)
5903 {
5904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5905         int diag;
5906
5907         /*
5908          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5909          * operation. Trap this case to avoid exhausting the [very limited]
5910          * set of PF resources used to store VF MAC addresses.
5911          */
5912         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5913                 return -1;
5914         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5915         if (diag != 0)
5916                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5917                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5918                             mac_addr->addr_bytes[0],
5919                             mac_addr->addr_bytes[1],
5920                             mac_addr->addr_bytes[2],
5921                             mac_addr->addr_bytes[3],
5922                             mac_addr->addr_bytes[4],
5923                             mac_addr->addr_bytes[5],
5924                             diag);
5925         return diag;
5926 }
5927
5928 static void
5929 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5930 {
5931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5932         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5933         struct ether_addr *mac_addr;
5934         uint32_t i;
5935         int diag;
5936
5937         /*
5938          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5939          * not support the deletion of a given MAC address.
5940          * Instead, it imposes to delete all MAC addresses, then to add again
5941          * all MAC addresses with the exception of the one to be deleted.
5942          */
5943         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5944
5945         /*
5946          * Add again all MAC addresses, with the exception of the deleted one
5947          * and of the permanent MAC address.
5948          */
5949         for (i = 0, mac_addr = dev->data->mac_addrs;
5950              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5951                 /* Skip the deleted MAC address */
5952                 if (i == index)
5953                         continue;
5954                 /* Skip NULL MAC addresses */
5955                 if (is_zero_ether_addr(mac_addr))
5956                         continue;
5957                 /* Skip the permanent MAC address */
5958                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5959                         continue;
5960                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5961                 if (diag != 0)
5962                         PMD_DRV_LOG(ERR,
5963                                     "Adding again MAC address "
5964                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5965                                     "diag=%d",
5966                                     mac_addr->addr_bytes[0],
5967                                     mac_addr->addr_bytes[1],
5968                                     mac_addr->addr_bytes[2],
5969                                     mac_addr->addr_bytes[3],
5970                                     mac_addr->addr_bytes[4],
5971                                     mac_addr->addr_bytes[5],
5972                                     diag);
5973         }
5974 }
5975
5976 static void
5977 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5978 {
5979         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5980
5981         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5982 }
5983
5984 int
5985 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5986                         struct rte_eth_syn_filter *filter,
5987                         bool add)
5988 {
5989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5990         struct ixgbe_filter_info *filter_info =
5991                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5992         uint32_t syn_info;
5993         uint32_t synqf;
5994
5995         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5996                 return -EINVAL;
5997
5998         syn_info = filter_info->syn_info;
5999
6000         if (add) {
6001                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6002                         return -EINVAL;
6003                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6004                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6005
6006                 if (filter->hig_pri)
6007                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6008                 else
6009                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6010         } else {
6011                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6012                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6013                         return -ENOENT;
6014                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6015         }
6016
6017         filter_info->syn_info = synqf;
6018         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6019         IXGBE_WRITE_FLUSH(hw);
6020         return 0;
6021 }
6022
6023 static int
6024 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6025                         struct rte_eth_syn_filter *filter)
6026 {
6027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6028         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6029
6030         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6031                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6032                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6033                 return 0;
6034         }
6035         return -ENOENT;
6036 }
6037
6038 static int
6039 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6040                         enum rte_filter_op filter_op,
6041                         void *arg)
6042 {
6043         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6044         int ret;
6045
6046         MAC_TYPE_FILTER_SUP(hw->mac.type);
6047
6048         if (filter_op == RTE_ETH_FILTER_NOP)
6049                 return 0;
6050
6051         if (arg == NULL) {
6052                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6053                             filter_op);
6054                 return -EINVAL;
6055         }
6056
6057         switch (filter_op) {
6058         case RTE_ETH_FILTER_ADD:
6059                 ret = ixgbe_syn_filter_set(dev,
6060                                 (struct rte_eth_syn_filter *)arg,
6061                                 TRUE);
6062                 break;
6063         case RTE_ETH_FILTER_DELETE:
6064                 ret = ixgbe_syn_filter_set(dev,
6065                                 (struct rte_eth_syn_filter *)arg,
6066                                 FALSE);
6067                 break;
6068         case RTE_ETH_FILTER_GET:
6069                 ret = ixgbe_syn_filter_get(dev,
6070                                 (struct rte_eth_syn_filter *)arg);
6071                 break;
6072         default:
6073                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6074                 ret = -EINVAL;
6075                 break;
6076         }
6077
6078         return ret;
6079 }
6080
6081
6082 static inline enum ixgbe_5tuple_protocol
6083 convert_protocol_type(uint8_t protocol_value)
6084 {
6085         if (protocol_value == IPPROTO_TCP)
6086                 return IXGBE_FILTER_PROTOCOL_TCP;
6087         else if (protocol_value == IPPROTO_UDP)
6088                 return IXGBE_FILTER_PROTOCOL_UDP;
6089         else if (protocol_value == IPPROTO_SCTP)
6090                 return IXGBE_FILTER_PROTOCOL_SCTP;
6091         else
6092                 return IXGBE_FILTER_PROTOCOL_NONE;
6093 }
6094
6095 /* inject a 5-tuple filter to HW */
6096 static inline void
6097 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6098                            struct ixgbe_5tuple_filter *filter)
6099 {
6100         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6101         int i;
6102         uint32_t ftqf, sdpqf;
6103         uint32_t l34timir = 0;
6104         uint8_t mask = 0xff;
6105
6106         i = filter->index;
6107
6108         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6109                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6110         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6111
6112         ftqf = (uint32_t)(filter->filter_info.proto &
6113                 IXGBE_FTQF_PROTOCOL_MASK);
6114         ftqf |= (uint32_t)((filter->filter_info.priority &
6115                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6116         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6117                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6118         if (filter->filter_info.dst_ip_mask == 0)
6119                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6120         if (filter->filter_info.src_port_mask == 0)
6121                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6122         if (filter->filter_info.dst_port_mask == 0)
6123                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6124         if (filter->filter_info.proto_mask == 0)
6125                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6126         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6127         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6128         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6129
6130         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6131         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6132         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6133         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6134
6135         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6136         l34timir |= (uint32_t)(filter->queue <<
6137                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6138         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6139 }
6140
6141 /*
6142  * add a 5tuple filter
6143  *
6144  * @param
6145  * dev: Pointer to struct rte_eth_dev.
6146  * index: the index the filter allocates.
6147  * filter: ponter to the filter that will be added.
6148  * rx_queue: the queue id the filter assigned to.
6149  *
6150  * @return
6151  *    - On success, zero.
6152  *    - On failure, a negative value.
6153  */
6154 static int
6155 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6156                         struct ixgbe_5tuple_filter *filter)
6157 {
6158         struct ixgbe_filter_info *filter_info =
6159                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6160         int i, idx, shift;
6161
6162         /*
6163          * look for an unused 5tuple filter index,
6164          * and insert the filter to list.
6165          */
6166         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6167                 idx = i / (sizeof(uint32_t) * NBBY);
6168                 shift = i % (sizeof(uint32_t) * NBBY);
6169                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6170                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6171                         filter->index = i;
6172                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6173                                           filter,
6174                                           entries);
6175                         break;
6176                 }
6177         }
6178         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6179                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6180                 return -ENOSYS;
6181         }
6182
6183         ixgbe_inject_5tuple_filter(dev, filter);
6184
6185         return 0;
6186 }
6187
6188 /*
6189  * remove a 5tuple filter
6190  *
6191  * @param
6192  * dev: Pointer to struct rte_eth_dev.
6193  * filter: the pointer of the filter will be removed.
6194  */
6195 static void
6196 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6197                         struct ixgbe_5tuple_filter *filter)
6198 {
6199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6200         struct ixgbe_filter_info *filter_info =
6201                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6202         uint16_t index = filter->index;
6203
6204         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6205                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6206         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6207         rte_free(filter);
6208
6209         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6210         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6211         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6212         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6213         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6214 }
6215
6216 static int
6217 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6218 {
6219         struct ixgbe_hw *hw;
6220         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6221         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6222
6223         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6224
6225         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6226                 return -EINVAL;
6227
6228         /* refuse mtu that requires the support of scattered packets when this
6229          * feature has not been enabled before.
6230          */
6231         if (!rx_conf->enable_scatter &&
6232             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6233              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6234                 return -EINVAL;
6235
6236         /*
6237          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6238          * request of the version 2.0 of the mailbox API.
6239          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6240          * of the mailbox API.
6241          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6242          * prior to 3.11.33 which contains the following change:
6243          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6244          */
6245         ixgbevf_rlpml_set_vf(hw, max_frame);
6246
6247         /* update max frame size */
6248         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6249         return 0;
6250 }
6251
6252 static inline struct ixgbe_5tuple_filter *
6253 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6254                         struct ixgbe_5tuple_filter_info *key)
6255 {
6256         struct ixgbe_5tuple_filter *it;
6257
6258         TAILQ_FOREACH(it, filter_list, entries) {
6259                 if (memcmp(key, &it->filter_info,
6260                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6261                         return it;
6262                 }
6263         }
6264         return NULL;
6265 }
6266
6267 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6268 static inline int
6269 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6270                         struct ixgbe_5tuple_filter_info *filter_info)
6271 {
6272         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6273                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6274                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6275                 return -EINVAL;
6276
6277         switch (filter->dst_ip_mask) {
6278         case UINT32_MAX:
6279                 filter_info->dst_ip_mask = 0;
6280                 filter_info->dst_ip = filter->dst_ip;
6281                 break;
6282         case 0:
6283                 filter_info->dst_ip_mask = 1;
6284                 break;
6285         default:
6286                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6287                 return -EINVAL;
6288         }
6289
6290         switch (filter->src_ip_mask) {
6291         case UINT32_MAX:
6292                 filter_info->src_ip_mask = 0;
6293                 filter_info->src_ip = filter->src_ip;
6294                 break;
6295         case 0:
6296                 filter_info->src_ip_mask = 1;
6297                 break;
6298         default:
6299                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6300                 return -EINVAL;
6301         }
6302
6303         switch (filter->dst_port_mask) {
6304         case UINT16_MAX:
6305                 filter_info->dst_port_mask = 0;
6306                 filter_info->dst_port = filter->dst_port;
6307                 break;
6308         case 0:
6309                 filter_info->dst_port_mask = 1;
6310                 break;
6311         default:
6312                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6313                 return -EINVAL;
6314         }
6315
6316         switch (filter->src_port_mask) {
6317         case UINT16_MAX:
6318                 filter_info->src_port_mask = 0;
6319                 filter_info->src_port = filter->src_port;
6320                 break;
6321         case 0:
6322                 filter_info->src_port_mask = 1;
6323                 break;
6324         default:
6325                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6326                 return -EINVAL;
6327         }
6328
6329         switch (filter->proto_mask) {
6330         case UINT8_MAX:
6331                 filter_info->proto_mask = 0;
6332                 filter_info->proto =
6333                         convert_protocol_type(filter->proto);
6334                 break;
6335         case 0:
6336                 filter_info->proto_mask = 1;
6337                 break;
6338         default:
6339                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6340                 return -EINVAL;
6341         }
6342
6343         filter_info->priority = (uint8_t)filter->priority;
6344         return 0;
6345 }
6346
6347 /*
6348  * add or delete a ntuple filter
6349  *
6350  * @param
6351  * dev: Pointer to struct rte_eth_dev.
6352  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6353  * add: if true, add filter, if false, remove filter
6354  *
6355  * @return
6356  *    - On success, zero.
6357  *    - On failure, a negative value.
6358  */
6359 int
6360 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6361                         struct rte_eth_ntuple_filter *ntuple_filter,
6362                         bool add)
6363 {
6364         struct ixgbe_filter_info *filter_info =
6365                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6366         struct ixgbe_5tuple_filter_info filter_5tuple;
6367         struct ixgbe_5tuple_filter *filter;
6368         int ret;
6369
6370         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6371                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6372                 return -EINVAL;
6373         }
6374
6375         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6376         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6377         if (ret < 0)
6378                 return ret;
6379
6380         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6381                                          &filter_5tuple);
6382         if (filter != NULL && add) {
6383                 PMD_DRV_LOG(ERR, "filter exists.");
6384                 return -EEXIST;
6385         }
6386         if (filter == NULL && !add) {
6387                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6388                 return -ENOENT;
6389         }
6390
6391         if (add) {
6392                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6393                                 sizeof(struct ixgbe_5tuple_filter), 0);
6394                 if (filter == NULL)
6395                         return -ENOMEM;
6396                 rte_memcpy(&filter->filter_info,
6397                                  &filter_5tuple,
6398                                  sizeof(struct ixgbe_5tuple_filter_info));
6399                 filter->queue = ntuple_filter->queue;
6400                 ret = ixgbe_add_5tuple_filter(dev, filter);
6401                 if (ret < 0) {
6402                         rte_free(filter);
6403                         return ret;
6404                 }
6405         } else
6406                 ixgbe_remove_5tuple_filter(dev, filter);
6407
6408         return 0;
6409 }
6410
6411 /*
6412  * get a ntuple filter
6413  *
6414  * @param
6415  * dev: Pointer to struct rte_eth_dev.
6416  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6417  *
6418  * @return
6419  *    - On success, zero.
6420  *    - On failure, a negative value.
6421  */
6422 static int
6423 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6424                         struct rte_eth_ntuple_filter *ntuple_filter)
6425 {
6426         struct ixgbe_filter_info *filter_info =
6427                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6428         struct ixgbe_5tuple_filter_info filter_5tuple;
6429         struct ixgbe_5tuple_filter *filter;
6430         int ret;
6431
6432         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6433                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6434                 return -EINVAL;
6435         }
6436
6437         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6438         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6439         if (ret < 0)
6440                 return ret;
6441
6442         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6443                                          &filter_5tuple);
6444         if (filter == NULL) {
6445                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6446                 return -ENOENT;
6447         }
6448         ntuple_filter->queue = filter->queue;
6449         return 0;
6450 }
6451
6452 /*
6453  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6454  * @dev: pointer to rte_eth_dev structure
6455  * @filter_op:operation will be taken.
6456  * @arg: a pointer to specific structure corresponding to the filter_op
6457  *
6458  * @return
6459  *    - On success, zero.
6460  *    - On failure, a negative value.
6461  */
6462 static int
6463 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6464                                 enum rte_filter_op filter_op,
6465                                 void *arg)
6466 {
6467         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6468         int ret;
6469
6470         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6471
6472         if (filter_op == RTE_ETH_FILTER_NOP)
6473                 return 0;
6474
6475         if (arg == NULL) {
6476                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6477                             filter_op);
6478                 return -EINVAL;
6479         }
6480
6481         switch (filter_op) {
6482         case RTE_ETH_FILTER_ADD:
6483                 ret = ixgbe_add_del_ntuple_filter(dev,
6484                         (struct rte_eth_ntuple_filter *)arg,
6485                         TRUE);
6486                 break;
6487         case RTE_ETH_FILTER_DELETE:
6488                 ret = ixgbe_add_del_ntuple_filter(dev,
6489                         (struct rte_eth_ntuple_filter *)arg,
6490                         FALSE);
6491                 break;
6492         case RTE_ETH_FILTER_GET:
6493                 ret = ixgbe_get_ntuple_filter(dev,
6494                         (struct rte_eth_ntuple_filter *)arg);
6495                 break;
6496         default:
6497                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6498                 ret = -EINVAL;
6499                 break;
6500         }
6501         return ret;
6502 }
6503
6504 int
6505 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6506                         struct rte_eth_ethertype_filter *filter,
6507                         bool add)
6508 {
6509         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6510         struct ixgbe_filter_info *filter_info =
6511                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6512         uint32_t etqf = 0;
6513         uint32_t etqs = 0;
6514         int ret;
6515         struct ixgbe_ethertype_filter ethertype_filter;
6516
6517         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6518                 return -EINVAL;
6519
6520         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6521                 filter->ether_type == ETHER_TYPE_IPv6) {
6522                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6523                         " ethertype filter.", filter->ether_type);
6524                 return -EINVAL;
6525         }
6526
6527         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6528                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6529                 return -EINVAL;
6530         }
6531         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6532                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6533                 return -EINVAL;
6534         }
6535
6536         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6537         if (ret >= 0 && add) {
6538                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6539                             filter->ether_type);
6540                 return -EEXIST;
6541         }
6542         if (ret < 0 && !add) {
6543                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6544                             filter->ether_type);
6545                 return -ENOENT;
6546         }
6547
6548         if (add) {
6549                 etqf = IXGBE_ETQF_FILTER_EN;
6550                 etqf |= (uint32_t)filter->ether_type;
6551                 etqs |= (uint32_t)((filter->queue <<
6552                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6553                                     IXGBE_ETQS_RX_QUEUE);
6554                 etqs |= IXGBE_ETQS_QUEUE_EN;
6555
6556                 ethertype_filter.ethertype = filter->ether_type;
6557                 ethertype_filter.etqf = etqf;
6558                 ethertype_filter.etqs = etqs;
6559                 ethertype_filter.conf = FALSE;
6560                 ret = ixgbe_ethertype_filter_insert(filter_info,
6561                                                     &ethertype_filter);
6562                 if (ret < 0) {
6563                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6564                         return -ENOSPC;
6565                 }
6566         } else {
6567                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6568                 if (ret < 0)
6569                         return -ENOSYS;
6570         }
6571         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6572         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6573         IXGBE_WRITE_FLUSH(hw);
6574
6575         return 0;
6576 }
6577
6578 static int
6579 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6580                         struct rte_eth_ethertype_filter *filter)
6581 {
6582         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6583         struct ixgbe_filter_info *filter_info =
6584                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6585         uint32_t etqf, etqs;
6586         int ret;
6587
6588         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6589         if (ret < 0) {
6590                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6591                             filter->ether_type);
6592                 return -ENOENT;
6593         }
6594
6595         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6596         if (etqf & IXGBE_ETQF_FILTER_EN) {
6597                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6598                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6599                 filter->flags = 0;
6600                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6601                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6602                 return 0;
6603         }
6604         return -ENOENT;
6605 }
6606
6607 /*
6608  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6609  * @dev: pointer to rte_eth_dev structure
6610  * @filter_op:operation will be taken.
6611  * @arg: a pointer to specific structure corresponding to the filter_op
6612  */
6613 static int
6614 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6615                                 enum rte_filter_op filter_op,
6616                                 void *arg)
6617 {
6618         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6619         int ret;
6620
6621         MAC_TYPE_FILTER_SUP(hw->mac.type);
6622
6623         if (filter_op == RTE_ETH_FILTER_NOP)
6624                 return 0;
6625
6626         if (arg == NULL) {
6627                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6628                             filter_op);
6629                 return -EINVAL;
6630         }
6631
6632         switch (filter_op) {
6633         case RTE_ETH_FILTER_ADD:
6634                 ret = ixgbe_add_del_ethertype_filter(dev,
6635                         (struct rte_eth_ethertype_filter *)arg,
6636                         TRUE);
6637                 break;
6638         case RTE_ETH_FILTER_DELETE:
6639                 ret = ixgbe_add_del_ethertype_filter(dev,
6640                         (struct rte_eth_ethertype_filter *)arg,
6641                         FALSE);
6642                 break;
6643         case RTE_ETH_FILTER_GET:
6644                 ret = ixgbe_get_ethertype_filter(dev,
6645                         (struct rte_eth_ethertype_filter *)arg);
6646                 break;
6647         default:
6648                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6649                 ret = -EINVAL;
6650                 break;
6651         }
6652         return ret;
6653 }
6654
6655 static int
6656 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6657                      enum rte_filter_type filter_type,
6658                      enum rte_filter_op filter_op,
6659                      void *arg)
6660 {
6661         int ret = 0;
6662
6663         switch (filter_type) {
6664         case RTE_ETH_FILTER_NTUPLE:
6665                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6666                 break;
6667         case RTE_ETH_FILTER_ETHERTYPE:
6668                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6669                 break;
6670         case RTE_ETH_FILTER_SYN:
6671                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6672                 break;
6673         case RTE_ETH_FILTER_FDIR:
6674                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6675                 break;
6676         case RTE_ETH_FILTER_L2_TUNNEL:
6677                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6678                 break;
6679         case RTE_ETH_FILTER_GENERIC:
6680                 if (filter_op != RTE_ETH_FILTER_GET)
6681                         return -EINVAL;
6682                 *(const void **)arg = &ixgbe_flow_ops;
6683                 break;
6684         default:
6685                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6686                                                         filter_type);
6687                 ret = -EINVAL;
6688                 break;
6689         }
6690
6691         return ret;
6692 }
6693
6694 static u8 *
6695 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6696                         u8 **mc_addr_ptr, u32 *vmdq)
6697 {
6698         u8 *mc_addr;
6699
6700         *vmdq = 0;
6701         mc_addr = *mc_addr_ptr;
6702         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6703         return mc_addr;
6704 }
6705
6706 static int
6707 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6708                           struct ether_addr *mc_addr_set,
6709                           uint32_t nb_mc_addr)
6710 {
6711         struct ixgbe_hw *hw;
6712         u8 *mc_addr_list;
6713
6714         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6715         mc_addr_list = (u8 *)mc_addr_set;
6716         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6717                                          ixgbe_dev_addr_list_itr, TRUE);
6718 }
6719
6720 static uint64_t
6721 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6722 {
6723         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6724         uint64_t systime_cycles;
6725
6726         switch (hw->mac.type) {
6727         case ixgbe_mac_X550:
6728         case ixgbe_mac_X550EM_x:
6729         case ixgbe_mac_X550EM_a:
6730                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6731                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6732                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6733                                 * NSEC_PER_SEC;
6734                 break;
6735         default:
6736                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6737                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6738                                 << 32;
6739         }
6740
6741         return systime_cycles;
6742 }
6743
6744 static uint64_t
6745 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6746 {
6747         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6748         uint64_t rx_tstamp_cycles;
6749
6750         switch (hw->mac.type) {
6751         case ixgbe_mac_X550:
6752         case ixgbe_mac_X550EM_x:
6753         case ixgbe_mac_X550EM_a:
6754                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6755                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6756                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6757                                 * NSEC_PER_SEC;
6758                 break;
6759         default:
6760                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6761                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6762                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6763                                 << 32;
6764         }
6765
6766         return rx_tstamp_cycles;
6767 }
6768
6769 static uint64_t
6770 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6771 {
6772         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6773         uint64_t tx_tstamp_cycles;
6774
6775         switch (hw->mac.type) {
6776         case ixgbe_mac_X550:
6777         case ixgbe_mac_X550EM_x:
6778         case ixgbe_mac_X550EM_a:
6779                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6780                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6781                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6782                                 * NSEC_PER_SEC;
6783                 break;
6784         default:
6785                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6786                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6787                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6788                                 << 32;
6789         }
6790
6791         return tx_tstamp_cycles;
6792 }
6793
6794 static void
6795 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6796 {
6797         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6798         struct ixgbe_adapter *adapter =
6799                 (struct ixgbe_adapter *)dev->data->dev_private;
6800         struct rte_eth_link link;
6801         uint32_t incval = 0;
6802         uint32_t shift = 0;
6803
6804         /* Get current link speed. */
6805         memset(&link, 0, sizeof(link));
6806         ixgbe_dev_link_update(dev, 1);
6807         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6808
6809         switch (link.link_speed) {
6810         case ETH_SPEED_NUM_100M:
6811                 incval = IXGBE_INCVAL_100;
6812                 shift = IXGBE_INCVAL_SHIFT_100;
6813                 break;
6814         case ETH_SPEED_NUM_1G:
6815                 incval = IXGBE_INCVAL_1GB;
6816                 shift = IXGBE_INCVAL_SHIFT_1GB;
6817                 break;
6818         case ETH_SPEED_NUM_10G:
6819         default:
6820                 incval = IXGBE_INCVAL_10GB;
6821                 shift = IXGBE_INCVAL_SHIFT_10GB;
6822                 break;
6823         }
6824
6825         switch (hw->mac.type) {
6826         case ixgbe_mac_X550:
6827         case ixgbe_mac_X550EM_x:
6828         case ixgbe_mac_X550EM_a:
6829                 /* Independent of link speed. */
6830                 incval = 1;
6831                 /* Cycles read will be interpreted as ns. */
6832                 shift = 0;
6833                 /* Fall-through */
6834         case ixgbe_mac_X540:
6835                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6836                 break;
6837         case ixgbe_mac_82599EB:
6838                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6839                 shift -= IXGBE_INCVAL_SHIFT_82599;
6840                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6841                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6842                 break;
6843         default:
6844                 /* Not supported. */
6845                 return;
6846         }
6847
6848         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6849         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6850         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6851
6852         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6853         adapter->systime_tc.cc_shift = shift;
6854         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6855
6856         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6857         adapter->rx_tstamp_tc.cc_shift = shift;
6858         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6859
6860         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6861         adapter->tx_tstamp_tc.cc_shift = shift;
6862         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6863 }
6864
6865 static int
6866 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6867 {
6868         struct ixgbe_adapter *adapter =
6869                         (struct ixgbe_adapter *)dev->data->dev_private;
6870
6871         adapter->systime_tc.nsec += delta;
6872         adapter->rx_tstamp_tc.nsec += delta;
6873         adapter->tx_tstamp_tc.nsec += delta;
6874
6875         return 0;
6876 }
6877
6878 static int
6879 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6880 {
6881         uint64_t ns;
6882         struct ixgbe_adapter *adapter =
6883                         (struct ixgbe_adapter *)dev->data->dev_private;
6884
6885         ns = rte_timespec_to_ns(ts);
6886         /* Set the timecounters to a new value. */
6887         adapter->systime_tc.nsec = ns;
6888         adapter->rx_tstamp_tc.nsec = ns;
6889         adapter->tx_tstamp_tc.nsec = ns;
6890
6891         return 0;
6892 }
6893
6894 static int
6895 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6896 {
6897         uint64_t ns, systime_cycles;
6898         struct ixgbe_adapter *adapter =
6899                         (struct ixgbe_adapter *)dev->data->dev_private;
6900
6901         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6902         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6903         *ts = rte_ns_to_timespec(ns);
6904
6905         return 0;
6906 }
6907
6908 static int
6909 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6910 {
6911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6912         uint32_t tsync_ctl;
6913         uint32_t tsauxc;
6914
6915         /* Stop the timesync system time. */
6916         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6917         /* Reset the timesync system time value. */
6918         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6919         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6920
6921         /* Enable system time for platforms where it isn't on by default. */
6922         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6923         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6924         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6925
6926         ixgbe_start_timecounters(dev);
6927
6928         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6929         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6930                         (ETHER_TYPE_1588 |
6931                          IXGBE_ETQF_FILTER_EN |
6932                          IXGBE_ETQF_1588));
6933
6934         /* Enable timestamping of received PTP packets. */
6935         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6936         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6937         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6938
6939         /* Enable timestamping of transmitted PTP packets. */
6940         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6941         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6942         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6943
6944         IXGBE_WRITE_FLUSH(hw);
6945
6946         return 0;
6947 }
6948
6949 static int
6950 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6951 {
6952         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6953         uint32_t tsync_ctl;
6954
6955         /* Disable timestamping of transmitted PTP packets. */
6956         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6957         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6958         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6959
6960         /* Disable timestamping of received PTP packets. */
6961         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6962         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6963         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6964
6965         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6966         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6967
6968         /* Stop incrementating the System Time registers. */
6969         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6970
6971         return 0;
6972 }
6973
6974 static int
6975 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6976                                  struct timespec *timestamp,
6977                                  uint32_t flags __rte_unused)
6978 {
6979         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6980         struct ixgbe_adapter *adapter =
6981                 (struct ixgbe_adapter *)dev->data->dev_private;
6982         uint32_t tsync_rxctl;
6983         uint64_t rx_tstamp_cycles;
6984         uint64_t ns;
6985
6986         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6987         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6988                 return -EINVAL;
6989
6990         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6991         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6992         *timestamp = rte_ns_to_timespec(ns);
6993
6994         return  0;
6995 }
6996
6997 static int
6998 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6999                                  struct timespec *timestamp)
7000 {
7001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7002         struct ixgbe_adapter *adapter =
7003                 (struct ixgbe_adapter *)dev->data->dev_private;
7004         uint32_t tsync_txctl;
7005         uint64_t tx_tstamp_cycles;
7006         uint64_t ns;
7007
7008         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7009         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7010                 return -EINVAL;
7011
7012         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7013         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7014         *timestamp = rte_ns_to_timespec(ns);
7015
7016         return 0;
7017 }
7018
7019 static int
7020 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7021 {
7022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7023         int count = 0;
7024         int g_ind = 0;
7025         const struct reg_info *reg_group;
7026         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7027                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7028
7029         while ((reg_group = reg_set[g_ind++]))
7030                 count += ixgbe_regs_group_count(reg_group);
7031
7032         return count;
7033 }
7034
7035 static int
7036 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7037 {
7038         int count = 0;
7039         int g_ind = 0;
7040         const struct reg_info *reg_group;
7041
7042         while ((reg_group = ixgbevf_regs[g_ind++]))
7043                 count += ixgbe_regs_group_count(reg_group);
7044
7045         return count;
7046 }
7047
7048 static int
7049 ixgbe_get_regs(struct rte_eth_dev *dev,
7050               struct rte_dev_reg_info *regs)
7051 {
7052         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7053         uint32_t *data = regs->data;
7054         int g_ind = 0;
7055         int count = 0;
7056         const struct reg_info *reg_group;
7057         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7058                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7059
7060         if (data == NULL) {
7061                 regs->length = ixgbe_get_reg_length(dev);
7062                 regs->width = sizeof(uint32_t);
7063                 return 0;
7064         }
7065
7066         /* Support only full register dump */
7067         if ((regs->length == 0) ||
7068             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7069                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7070                         hw->device_id;
7071                 while ((reg_group = reg_set[g_ind++]))
7072                         count += ixgbe_read_regs_group(dev, &data[count],
7073                                 reg_group);
7074                 return 0;
7075         }
7076
7077         return -ENOTSUP;
7078 }
7079
7080 static int
7081 ixgbevf_get_regs(struct rte_eth_dev *dev,
7082                 struct rte_dev_reg_info *regs)
7083 {
7084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7085         uint32_t *data = regs->data;
7086         int g_ind = 0;
7087         int count = 0;
7088         const struct reg_info *reg_group;
7089
7090         if (data == NULL) {
7091                 regs->length = ixgbevf_get_reg_length(dev);
7092                 regs->width = sizeof(uint32_t);
7093                 return 0;
7094         }
7095
7096         /* Support only full register dump */
7097         if ((regs->length == 0) ||
7098             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7099                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7100                         hw->device_id;
7101                 while ((reg_group = ixgbevf_regs[g_ind++]))
7102                         count += ixgbe_read_regs_group(dev, &data[count],
7103                                                       reg_group);
7104                 return 0;
7105         }
7106
7107         return -ENOTSUP;
7108 }
7109
7110 static int
7111 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7112 {
7113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7114
7115         /* Return unit is byte count */
7116         return hw->eeprom.word_size * 2;
7117 }
7118
7119 static int
7120 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7121                 struct rte_dev_eeprom_info *in_eeprom)
7122 {
7123         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7124         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7125         uint16_t *data = in_eeprom->data;
7126         int first, length;
7127
7128         first = in_eeprom->offset >> 1;
7129         length = in_eeprom->length >> 1;
7130         if ((first > hw->eeprom.word_size) ||
7131             ((first + length) > hw->eeprom.word_size))
7132                 return -EINVAL;
7133
7134         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7135
7136         return eeprom->ops.read_buffer(hw, first, length, data);
7137 }
7138
7139 static int
7140 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7141                 struct rte_dev_eeprom_info *in_eeprom)
7142 {
7143         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7144         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7145         uint16_t *data = in_eeprom->data;
7146         int first, length;
7147
7148         first = in_eeprom->offset >> 1;
7149         length = in_eeprom->length >> 1;
7150         if ((first > hw->eeprom.word_size) ||
7151             ((first + length) > hw->eeprom.word_size))
7152                 return -EINVAL;
7153
7154         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7155
7156         return eeprom->ops.write_buffer(hw,  first, length, data);
7157 }
7158
7159 uint16_t
7160 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7161         switch (mac_type) {
7162         case ixgbe_mac_X550:
7163         case ixgbe_mac_X550EM_x:
7164         case ixgbe_mac_X550EM_a:
7165                 return ETH_RSS_RETA_SIZE_512;
7166         case ixgbe_mac_X550_vf:
7167         case ixgbe_mac_X550EM_x_vf:
7168         case ixgbe_mac_X550EM_a_vf:
7169                 return ETH_RSS_RETA_SIZE_64;
7170         default:
7171                 return ETH_RSS_RETA_SIZE_128;
7172         }
7173 }
7174
7175 uint32_t
7176 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7177         switch (mac_type) {
7178         case ixgbe_mac_X550:
7179         case ixgbe_mac_X550EM_x:
7180         case ixgbe_mac_X550EM_a:
7181                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7182                         return IXGBE_RETA(reta_idx >> 2);
7183                 else
7184                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7185         case ixgbe_mac_X550_vf:
7186         case ixgbe_mac_X550EM_x_vf:
7187         case ixgbe_mac_X550EM_a_vf:
7188                 return IXGBE_VFRETA(reta_idx >> 2);
7189         default:
7190                 return IXGBE_RETA(reta_idx >> 2);
7191         }
7192 }
7193
7194 uint32_t
7195 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7196         switch (mac_type) {
7197         case ixgbe_mac_X550_vf:
7198         case ixgbe_mac_X550EM_x_vf:
7199         case ixgbe_mac_X550EM_a_vf:
7200                 return IXGBE_VFMRQC;
7201         default:
7202                 return IXGBE_MRQC;
7203         }
7204 }
7205
7206 uint32_t
7207 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7208         switch (mac_type) {
7209         case ixgbe_mac_X550_vf:
7210         case ixgbe_mac_X550EM_x_vf:
7211         case ixgbe_mac_X550EM_a_vf:
7212                 return IXGBE_VFRSSRK(i);
7213         default:
7214                 return IXGBE_RSSRK(i);
7215         }
7216 }
7217
7218 bool
7219 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7220         switch (mac_type) {
7221         case ixgbe_mac_82599_vf:
7222         case ixgbe_mac_X540_vf:
7223                 return 0;
7224         default:
7225                 return 1;
7226         }
7227 }
7228
7229 static int
7230 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7231                         struct rte_eth_dcb_info *dcb_info)
7232 {
7233         struct ixgbe_dcb_config *dcb_config =
7234                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7235         struct ixgbe_dcb_tc_config *tc;
7236         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7237         uint8_t nb_tcs;
7238         uint8_t i, j;
7239
7240         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7241                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7242         else
7243                 dcb_info->nb_tcs = 1;
7244
7245         tc_queue = &dcb_info->tc_queue;
7246         nb_tcs = dcb_info->nb_tcs;
7247
7248         if (dcb_config->vt_mode) { /* vt is enabled*/
7249                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7250                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7251                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7252                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7253                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7254                         for (j = 0; j < nb_tcs; j++) {
7255                                 tc_queue->tc_rxq[0][j].base = j;
7256                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7257                                 tc_queue->tc_txq[0][j].base = j;
7258                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7259                         }
7260                 } else {
7261                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7262                                 for (j = 0; j < nb_tcs; j++) {
7263                                         tc_queue->tc_rxq[i][j].base =
7264                                                 i * nb_tcs + j;
7265                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7266                                         tc_queue->tc_txq[i][j].base =
7267                                                 i * nb_tcs + j;
7268                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7269                                 }
7270                         }
7271                 }
7272         } else { /* vt is disabled*/
7273                 struct rte_eth_dcb_rx_conf *rx_conf =
7274                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7275                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7276                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7277                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7278                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7279                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7280                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7281                         }
7282                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7283                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7284                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7285                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7286                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7287                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7288                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7289                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7290                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7291                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7292                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7293                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7294                         }
7295                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7296                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7297                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7298                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7299                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7300                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7301                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7302                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7303                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7304                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7305                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7306                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7307                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7308                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7309                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7310                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7311                 }
7312         }
7313         for (i = 0; i < dcb_info->nb_tcs; i++) {
7314                 tc = &dcb_config->tc_config[i];
7315                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7316         }
7317         return 0;
7318 }
7319
7320 /* Update e-tag ether type */
7321 static int
7322 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7323                             uint16_t ether_type)
7324 {
7325         uint32_t etag_etype;
7326
7327         if (hw->mac.type != ixgbe_mac_X550 &&
7328             hw->mac.type != ixgbe_mac_X550EM_x &&
7329             hw->mac.type != ixgbe_mac_X550EM_a) {
7330                 return -ENOTSUP;
7331         }
7332
7333         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7334         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7335         etag_etype |= ether_type;
7336         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7337         IXGBE_WRITE_FLUSH(hw);
7338
7339         return 0;
7340 }
7341
7342 /* Config l2 tunnel ether type */
7343 static int
7344 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7345                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7346 {
7347         int ret = 0;
7348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7349         struct ixgbe_l2_tn_info *l2_tn_info =
7350                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7351
7352         if (l2_tunnel == NULL)
7353                 return -EINVAL;
7354
7355         switch (l2_tunnel->l2_tunnel_type) {
7356         case RTE_L2_TUNNEL_TYPE_E_TAG:
7357                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7358                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7359                 break;
7360         default:
7361                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7362                 ret = -EINVAL;
7363                 break;
7364         }
7365
7366         return ret;
7367 }
7368
7369 /* Enable e-tag tunnel */
7370 static int
7371 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7372 {
7373         uint32_t etag_etype;
7374
7375         if (hw->mac.type != ixgbe_mac_X550 &&
7376             hw->mac.type != ixgbe_mac_X550EM_x &&
7377             hw->mac.type != ixgbe_mac_X550EM_a) {
7378                 return -ENOTSUP;
7379         }
7380
7381         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7382         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7383         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7384         IXGBE_WRITE_FLUSH(hw);
7385
7386         return 0;
7387 }
7388
7389 /* Enable l2 tunnel */
7390 static int
7391 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7392                            enum rte_eth_tunnel_type l2_tunnel_type)
7393 {
7394         int ret = 0;
7395         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7396         struct ixgbe_l2_tn_info *l2_tn_info =
7397                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7398
7399         switch (l2_tunnel_type) {
7400         case RTE_L2_TUNNEL_TYPE_E_TAG:
7401                 l2_tn_info->e_tag_en = TRUE;
7402                 ret = ixgbe_e_tag_enable(hw);
7403                 break;
7404         default:
7405                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7406                 ret = -EINVAL;
7407                 break;
7408         }
7409
7410         return ret;
7411 }
7412
7413 /* Disable e-tag tunnel */
7414 static int
7415 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7416 {
7417         uint32_t etag_etype;
7418
7419         if (hw->mac.type != ixgbe_mac_X550 &&
7420             hw->mac.type != ixgbe_mac_X550EM_x &&
7421             hw->mac.type != ixgbe_mac_X550EM_a) {
7422                 return -ENOTSUP;
7423         }
7424
7425         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7426         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7427         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7428         IXGBE_WRITE_FLUSH(hw);
7429
7430         return 0;
7431 }
7432
7433 /* Disable l2 tunnel */
7434 static int
7435 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7436                             enum rte_eth_tunnel_type l2_tunnel_type)
7437 {
7438         int ret = 0;
7439         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7440         struct ixgbe_l2_tn_info *l2_tn_info =
7441                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7442
7443         switch (l2_tunnel_type) {
7444         case RTE_L2_TUNNEL_TYPE_E_TAG:
7445                 l2_tn_info->e_tag_en = FALSE;
7446                 ret = ixgbe_e_tag_disable(hw);
7447                 break;
7448         default:
7449                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7450                 ret = -EINVAL;
7451                 break;
7452         }
7453
7454         return ret;
7455 }
7456
7457 static int
7458 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7459                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7460 {
7461         int ret = 0;
7462         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7463         uint32_t i, rar_entries;
7464         uint32_t rar_low, rar_high;
7465
7466         if (hw->mac.type != ixgbe_mac_X550 &&
7467             hw->mac.type != ixgbe_mac_X550EM_x &&
7468             hw->mac.type != ixgbe_mac_X550EM_a) {
7469                 return -ENOTSUP;
7470         }
7471
7472         rar_entries = ixgbe_get_num_rx_addrs(hw);
7473
7474         for (i = 1; i < rar_entries; i++) {
7475                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7476                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7477                 if ((rar_high & IXGBE_RAH_AV) &&
7478                     (rar_high & IXGBE_RAH_ADTYPE) &&
7479                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7480                      l2_tunnel->tunnel_id)) {
7481                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7482                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7483
7484                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7485
7486                         return ret;
7487                 }
7488         }
7489
7490         return ret;
7491 }
7492
7493 static int
7494 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7495                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7496 {
7497         int ret = 0;
7498         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7499         uint32_t i, rar_entries;
7500         uint32_t rar_low, rar_high;
7501
7502         if (hw->mac.type != ixgbe_mac_X550 &&
7503             hw->mac.type != ixgbe_mac_X550EM_x &&
7504             hw->mac.type != ixgbe_mac_X550EM_a) {
7505                 return -ENOTSUP;
7506         }
7507
7508         /* One entry for one tunnel. Try to remove potential existing entry. */
7509         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7510
7511         rar_entries = ixgbe_get_num_rx_addrs(hw);
7512
7513         for (i = 1; i < rar_entries; i++) {
7514                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7515                 if (rar_high & IXGBE_RAH_AV) {
7516                         continue;
7517                 } else {
7518                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7519                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7520                         rar_low = l2_tunnel->tunnel_id;
7521
7522                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7523                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7524
7525                         return ret;
7526                 }
7527         }
7528
7529         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7530                      " Please remove a rule before adding a new one.");
7531         return -EINVAL;
7532 }
7533
7534 static inline struct ixgbe_l2_tn_filter *
7535 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7536                           struct ixgbe_l2_tn_key *key)
7537 {
7538         int ret;
7539
7540         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7541         if (ret < 0)
7542                 return NULL;
7543
7544         return l2_tn_info->hash_map[ret];
7545 }
7546
7547 static inline int
7548 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7549                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7550 {
7551         int ret;
7552
7553         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7554                                &l2_tn_filter->key);
7555
7556         if (ret < 0) {
7557                 PMD_DRV_LOG(ERR,
7558                             "Failed to insert L2 tunnel filter"
7559                             " to hash table %d!",
7560                             ret);
7561                 return ret;
7562         }
7563
7564         l2_tn_info->hash_map[ret] = l2_tn_filter;
7565
7566         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7567
7568         return 0;
7569 }
7570
7571 static inline int
7572 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7573                           struct ixgbe_l2_tn_key *key)
7574 {
7575         int ret;
7576         struct ixgbe_l2_tn_filter *l2_tn_filter;
7577
7578         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7579
7580         if (ret < 0) {
7581                 PMD_DRV_LOG(ERR,
7582                             "No such L2 tunnel filter to delete %d!",
7583                             ret);
7584                 return ret;
7585         }
7586
7587         l2_tn_filter = l2_tn_info->hash_map[ret];
7588         l2_tn_info->hash_map[ret] = NULL;
7589
7590         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7591         rte_free(l2_tn_filter);
7592
7593         return 0;
7594 }
7595
7596 /* Add l2 tunnel filter */
7597 int
7598 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7599                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7600                                bool restore)
7601 {
7602         int ret;
7603         struct ixgbe_l2_tn_info *l2_tn_info =
7604                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7605         struct ixgbe_l2_tn_key key;
7606         struct ixgbe_l2_tn_filter *node;
7607
7608         if (!restore) {
7609                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7610                 key.tn_id = l2_tunnel->tunnel_id;
7611
7612                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7613
7614                 if (node) {
7615                         PMD_DRV_LOG(ERR,
7616                                     "The L2 tunnel filter already exists!");
7617                         return -EINVAL;
7618                 }
7619
7620                 node = rte_zmalloc("ixgbe_l2_tn",
7621                                    sizeof(struct ixgbe_l2_tn_filter),
7622                                    0);
7623                 if (!node)
7624                         return -ENOMEM;
7625
7626                 rte_memcpy(&node->key,
7627                                  &key,
7628                                  sizeof(struct ixgbe_l2_tn_key));
7629                 node->pool = l2_tunnel->pool;
7630                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7631                 if (ret < 0) {
7632                         rte_free(node);
7633                         return ret;
7634                 }
7635         }
7636
7637         switch (l2_tunnel->l2_tunnel_type) {
7638         case RTE_L2_TUNNEL_TYPE_E_TAG:
7639                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7640                 break;
7641         default:
7642                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7643                 ret = -EINVAL;
7644                 break;
7645         }
7646
7647         if ((!restore) && (ret < 0))
7648                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7649
7650         return ret;
7651 }
7652
7653 /* Delete l2 tunnel filter */
7654 int
7655 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7656                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7657 {
7658         int ret;
7659         struct ixgbe_l2_tn_info *l2_tn_info =
7660                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7661         struct ixgbe_l2_tn_key key;
7662
7663         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7664         key.tn_id = l2_tunnel->tunnel_id;
7665         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7666         if (ret < 0)
7667                 return ret;
7668
7669         switch (l2_tunnel->l2_tunnel_type) {
7670         case RTE_L2_TUNNEL_TYPE_E_TAG:
7671                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7672                 break;
7673         default:
7674                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7675                 ret = -EINVAL;
7676                 break;
7677         }
7678
7679         return ret;
7680 }
7681
7682 /**
7683  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7684  * @dev: pointer to rte_eth_dev structure
7685  * @filter_op:operation will be taken.
7686  * @arg: a pointer to specific structure corresponding to the filter_op
7687  */
7688 static int
7689 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7690                                   enum rte_filter_op filter_op,
7691                                   void *arg)
7692 {
7693         int ret;
7694
7695         if (filter_op == RTE_ETH_FILTER_NOP)
7696                 return 0;
7697
7698         if (arg == NULL) {
7699                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7700                             filter_op);
7701                 return -EINVAL;
7702         }
7703
7704         switch (filter_op) {
7705         case RTE_ETH_FILTER_ADD:
7706                 ret = ixgbe_dev_l2_tunnel_filter_add
7707                         (dev,
7708                          (struct rte_eth_l2_tunnel_conf *)arg,
7709                          FALSE);
7710                 break;
7711         case RTE_ETH_FILTER_DELETE:
7712                 ret = ixgbe_dev_l2_tunnel_filter_del
7713                         (dev,
7714                          (struct rte_eth_l2_tunnel_conf *)arg);
7715                 break;
7716         default:
7717                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7718                 ret = -EINVAL;
7719                 break;
7720         }
7721         return ret;
7722 }
7723
7724 static int
7725 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7726 {
7727         int ret = 0;
7728         uint32_t ctrl;
7729         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7730
7731         if (hw->mac.type != ixgbe_mac_X550 &&
7732             hw->mac.type != ixgbe_mac_X550EM_x &&
7733             hw->mac.type != ixgbe_mac_X550EM_a) {
7734                 return -ENOTSUP;
7735         }
7736
7737         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7738         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7739         if (en)
7740                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7741         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7742
7743         return ret;
7744 }
7745
7746 /* Enable l2 tunnel forwarding */
7747 static int
7748 ixgbe_dev_l2_tunnel_forwarding_enable
7749         (struct rte_eth_dev *dev,
7750          enum rte_eth_tunnel_type l2_tunnel_type)
7751 {
7752         struct ixgbe_l2_tn_info *l2_tn_info =
7753                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7754         int ret = 0;
7755
7756         switch (l2_tunnel_type) {
7757         case RTE_L2_TUNNEL_TYPE_E_TAG:
7758                 l2_tn_info->e_tag_fwd_en = TRUE;
7759                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7760                 break;
7761         default:
7762                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7763                 ret = -EINVAL;
7764                 break;
7765         }
7766
7767         return ret;
7768 }
7769
7770 /* Disable l2 tunnel forwarding */
7771 static int
7772 ixgbe_dev_l2_tunnel_forwarding_disable
7773         (struct rte_eth_dev *dev,
7774          enum rte_eth_tunnel_type l2_tunnel_type)
7775 {
7776         struct ixgbe_l2_tn_info *l2_tn_info =
7777                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7778         int ret = 0;
7779
7780         switch (l2_tunnel_type) {
7781         case RTE_L2_TUNNEL_TYPE_E_TAG:
7782                 l2_tn_info->e_tag_fwd_en = FALSE;
7783                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7784                 break;
7785         default:
7786                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7787                 ret = -EINVAL;
7788                 break;
7789         }
7790
7791         return ret;
7792 }
7793
7794 static int
7795 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7796                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7797                              bool en)
7798 {
7799         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7800         int ret = 0;
7801         uint32_t vmtir, vmvir;
7802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7803
7804         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7805                 PMD_DRV_LOG(ERR,
7806                             "VF id %u should be less than %u",
7807                             l2_tunnel->vf_id,
7808                             pci_dev->max_vfs);
7809                 return -EINVAL;
7810         }
7811
7812         if (hw->mac.type != ixgbe_mac_X550 &&
7813             hw->mac.type != ixgbe_mac_X550EM_x &&
7814             hw->mac.type != ixgbe_mac_X550EM_a) {
7815                 return -ENOTSUP;
7816         }
7817
7818         if (en)
7819                 vmtir = l2_tunnel->tunnel_id;
7820         else
7821                 vmtir = 0;
7822
7823         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7824
7825         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7826         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7827         if (en)
7828                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7829         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7830
7831         return ret;
7832 }
7833
7834 /* Enable l2 tunnel tag insertion */
7835 static int
7836 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7837                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7838 {
7839         int ret = 0;
7840
7841         switch (l2_tunnel->l2_tunnel_type) {
7842         case RTE_L2_TUNNEL_TYPE_E_TAG:
7843                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7844                 break;
7845         default:
7846                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7847                 ret = -EINVAL;
7848                 break;
7849         }
7850
7851         return ret;
7852 }
7853
7854 /* Disable l2 tunnel tag insertion */
7855 static int
7856 ixgbe_dev_l2_tunnel_insertion_disable
7857         (struct rte_eth_dev *dev,
7858          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7859 {
7860         int ret = 0;
7861
7862         switch (l2_tunnel->l2_tunnel_type) {
7863         case RTE_L2_TUNNEL_TYPE_E_TAG:
7864                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7865                 break;
7866         default:
7867                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7868                 ret = -EINVAL;
7869                 break;
7870         }
7871
7872         return ret;
7873 }
7874
7875 static int
7876 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7877                              bool en)
7878 {
7879         int ret = 0;
7880         uint32_t qde;
7881         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7882
7883         if (hw->mac.type != ixgbe_mac_X550 &&
7884             hw->mac.type != ixgbe_mac_X550EM_x &&
7885             hw->mac.type != ixgbe_mac_X550EM_a) {
7886                 return -ENOTSUP;
7887         }
7888
7889         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7890         if (en)
7891                 qde |= IXGBE_QDE_STRIP_TAG;
7892         else
7893                 qde &= ~IXGBE_QDE_STRIP_TAG;
7894         qde &= ~IXGBE_QDE_READ;
7895         qde |= IXGBE_QDE_WRITE;
7896         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7897
7898         return ret;
7899 }
7900
7901 /* Enable l2 tunnel tag stripping */
7902 static int
7903 ixgbe_dev_l2_tunnel_stripping_enable
7904         (struct rte_eth_dev *dev,
7905          enum rte_eth_tunnel_type l2_tunnel_type)
7906 {
7907         int ret = 0;
7908
7909         switch (l2_tunnel_type) {
7910         case RTE_L2_TUNNEL_TYPE_E_TAG:
7911                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7912                 break;
7913         default:
7914                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7915                 ret = -EINVAL;
7916                 break;
7917         }
7918
7919         return ret;
7920 }
7921
7922 /* Disable l2 tunnel tag stripping */
7923 static int
7924 ixgbe_dev_l2_tunnel_stripping_disable
7925         (struct rte_eth_dev *dev,
7926          enum rte_eth_tunnel_type l2_tunnel_type)
7927 {
7928         int ret = 0;
7929
7930         switch (l2_tunnel_type) {
7931         case RTE_L2_TUNNEL_TYPE_E_TAG:
7932                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7933                 break;
7934         default:
7935                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7936                 ret = -EINVAL;
7937                 break;
7938         }
7939
7940         return ret;
7941 }
7942
7943 /* Enable/disable l2 tunnel offload functions */
7944 static int
7945 ixgbe_dev_l2_tunnel_offload_set
7946         (struct rte_eth_dev *dev,
7947          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7948          uint32_t mask,
7949          uint8_t en)
7950 {
7951         int ret = 0;
7952
7953         if (l2_tunnel == NULL)
7954                 return -EINVAL;
7955
7956         ret = -EINVAL;
7957         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7958                 if (en)
7959                         ret = ixgbe_dev_l2_tunnel_enable(
7960                                 dev,
7961                                 l2_tunnel->l2_tunnel_type);
7962                 else
7963                         ret = ixgbe_dev_l2_tunnel_disable(
7964                                 dev,
7965                                 l2_tunnel->l2_tunnel_type);
7966         }
7967
7968         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7969                 if (en)
7970                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7971                                 dev,
7972                                 l2_tunnel);
7973                 else
7974                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7975                                 dev,
7976                                 l2_tunnel);
7977         }
7978
7979         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7980                 if (en)
7981                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7982                                 dev,
7983                                 l2_tunnel->l2_tunnel_type);
7984                 else
7985                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7986                                 dev,
7987                                 l2_tunnel->l2_tunnel_type);
7988         }
7989
7990         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7991                 if (en)
7992                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7993                                 dev,
7994                                 l2_tunnel->l2_tunnel_type);
7995                 else
7996                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7997                                 dev,
7998                                 l2_tunnel->l2_tunnel_type);
7999         }
8000
8001         return ret;
8002 }
8003
8004 static int
8005 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8006                         uint16_t port)
8007 {
8008         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8009         IXGBE_WRITE_FLUSH(hw);
8010
8011         return 0;
8012 }
8013
8014 /* There's only one register for VxLAN UDP port.
8015  * So, we cannot add several ports. Will update it.
8016  */
8017 static int
8018 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8019                      uint16_t port)
8020 {
8021         if (port == 0) {
8022                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8023                 return -EINVAL;
8024         }
8025
8026         return ixgbe_update_vxlan_port(hw, port);
8027 }
8028
8029 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8030  * UDP port, it must have a value.
8031  * So, will reset it to the original value 0.
8032  */
8033 static int
8034 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8035                      uint16_t port)
8036 {
8037         uint16_t cur_port;
8038
8039         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8040
8041         if (cur_port != port) {
8042                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8043                 return -EINVAL;
8044         }
8045
8046         return ixgbe_update_vxlan_port(hw, 0);
8047 }
8048
8049 /* Add UDP tunneling port */
8050 static int
8051 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8052                               struct rte_eth_udp_tunnel *udp_tunnel)
8053 {
8054         int ret = 0;
8055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8056
8057         if (hw->mac.type != ixgbe_mac_X550 &&
8058             hw->mac.type != ixgbe_mac_X550EM_x &&
8059             hw->mac.type != ixgbe_mac_X550EM_a) {
8060                 return -ENOTSUP;
8061         }
8062
8063         if (udp_tunnel == NULL)
8064                 return -EINVAL;
8065
8066         switch (udp_tunnel->prot_type) {
8067         case RTE_TUNNEL_TYPE_VXLAN:
8068                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8069                 break;
8070
8071         case RTE_TUNNEL_TYPE_GENEVE:
8072         case RTE_TUNNEL_TYPE_TEREDO:
8073                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8074                 ret = -EINVAL;
8075                 break;
8076
8077         default:
8078                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8079                 ret = -EINVAL;
8080                 break;
8081         }
8082
8083         return ret;
8084 }
8085
8086 /* Remove UDP tunneling port */
8087 static int
8088 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8089                               struct rte_eth_udp_tunnel *udp_tunnel)
8090 {
8091         int ret = 0;
8092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8093
8094         if (hw->mac.type != ixgbe_mac_X550 &&
8095             hw->mac.type != ixgbe_mac_X550EM_x &&
8096             hw->mac.type != ixgbe_mac_X550EM_a) {
8097                 return -ENOTSUP;
8098         }
8099
8100         if (udp_tunnel == NULL)
8101                 return -EINVAL;
8102
8103         switch (udp_tunnel->prot_type) {
8104         case RTE_TUNNEL_TYPE_VXLAN:
8105                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8106                 break;
8107         case RTE_TUNNEL_TYPE_GENEVE:
8108         case RTE_TUNNEL_TYPE_TEREDO:
8109                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8110                 ret = -EINVAL;
8111                 break;
8112         default:
8113                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8114                 ret = -EINVAL;
8115                 break;
8116         }
8117
8118         return ret;
8119 }
8120
8121 static void
8122 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8123 {
8124         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8125
8126         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8127 }
8128
8129 static void
8130 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8131 {
8132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8133
8134         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8135 }
8136
8137 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8138 {
8139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8140         u32 in_msg = 0;
8141
8142         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8143                 return;
8144
8145         /* PF reset VF event */
8146         if (in_msg == IXGBE_PF_CONTROL_MSG)
8147                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8148                                               NULL, NULL);
8149 }
8150
8151 static int
8152 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8153 {
8154         uint32_t eicr;
8155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8156         struct ixgbe_interrupt *intr =
8157                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8158         ixgbevf_intr_disable(hw);
8159
8160         /* read-on-clear nic registers here */
8161         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8162         intr->flags = 0;
8163
8164         /* only one misc vector supported - mailbox */
8165         eicr &= IXGBE_VTEICR_MASK;
8166         if (eicr == IXGBE_MISC_VEC_ID)
8167                 intr->flags |= IXGBE_FLAG_MAILBOX;
8168
8169         return 0;
8170 }
8171
8172 static int
8173 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8174 {
8175         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8176         struct ixgbe_interrupt *intr =
8177                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8178
8179         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8180                 ixgbevf_mbx_process(dev);
8181                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8182         }
8183
8184         ixgbevf_intr_enable(hw);
8185
8186         return 0;
8187 }
8188
8189 static void
8190 ixgbevf_dev_interrupt_handler(void *param)
8191 {
8192         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8193
8194         ixgbevf_dev_interrupt_get_status(dev);
8195         ixgbevf_dev_interrupt_action(dev);
8196 }
8197
8198 /**
8199  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8200  *  @hw: pointer to hardware structure
8201  *
8202  *  Stops the transmit data path and waits for the HW to internally empty
8203  *  the Tx security block
8204  **/
8205 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8206 {
8207 #define IXGBE_MAX_SECTX_POLL 40
8208
8209         int i;
8210         int sectxreg;
8211
8212         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8213         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8214         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8215         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8216                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8217                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8218                         break;
8219                 /* Use interrupt-safe sleep just in case */
8220                 usec_delay(1000);
8221         }
8222
8223         /* For informational purposes only */
8224         if (i >= IXGBE_MAX_SECTX_POLL)
8225                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8226                          "path fully disabled.  Continuing with init.");
8227
8228         return IXGBE_SUCCESS;
8229 }
8230
8231 /**
8232  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8233  *  @hw: pointer to hardware structure
8234  *
8235  *  Enables the transmit data path.
8236  **/
8237 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8238 {
8239         uint32_t sectxreg;
8240
8241         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8242         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8243         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8244         IXGBE_WRITE_FLUSH(hw);
8245
8246         return IXGBE_SUCCESS;
8247 }
8248
8249 /* restore n-tuple filter */
8250 static inline void
8251 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8252 {
8253         struct ixgbe_filter_info *filter_info =
8254                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8255         struct ixgbe_5tuple_filter *node;
8256
8257         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8258                 ixgbe_inject_5tuple_filter(dev, node);
8259         }
8260 }
8261
8262 /* restore ethernet type filter */
8263 static inline void
8264 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8265 {
8266         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8267         struct ixgbe_filter_info *filter_info =
8268                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8269         int i;
8270
8271         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8272                 if (filter_info->ethertype_mask & (1 << i)) {
8273                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8274                                         filter_info->ethertype_filters[i].etqf);
8275                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8276                                         filter_info->ethertype_filters[i].etqs);
8277                         IXGBE_WRITE_FLUSH(hw);
8278                 }
8279         }
8280 }
8281
8282 /* restore SYN filter */
8283 static inline void
8284 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8285 {
8286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8287         struct ixgbe_filter_info *filter_info =
8288                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8289         uint32_t synqf;
8290
8291         synqf = filter_info->syn_info;
8292
8293         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8294                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8295                 IXGBE_WRITE_FLUSH(hw);
8296         }
8297 }
8298
8299 /* restore L2 tunnel filter */
8300 static inline void
8301 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8302 {
8303         struct ixgbe_l2_tn_info *l2_tn_info =
8304                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8305         struct ixgbe_l2_tn_filter *node;
8306         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8307
8308         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8309                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8310                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8311                 l2_tn_conf.pool           = node->pool;
8312                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8313         }
8314 }
8315
8316 /* restore rss filter */
8317 static inline void
8318 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8319 {
8320         struct ixgbe_filter_info *filter_info =
8321                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8322
8323         if (filter_info->rss_info.num)
8324                 ixgbe_config_rss_filter(dev,
8325                         &filter_info->rss_info, TRUE);
8326 }
8327
8328 static int
8329 ixgbe_filter_restore(struct rte_eth_dev *dev)
8330 {
8331         ixgbe_ntuple_filter_restore(dev);
8332         ixgbe_ethertype_filter_restore(dev);
8333         ixgbe_syn_filter_restore(dev);
8334         ixgbe_fdir_filter_restore(dev);
8335         ixgbe_l2_tn_filter_restore(dev);
8336         ixgbe_rss_filter_restore(dev);
8337
8338         return 0;
8339 }
8340
8341 static void
8342 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8343 {
8344         struct ixgbe_l2_tn_info *l2_tn_info =
8345                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8346         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8347
8348         if (l2_tn_info->e_tag_en)
8349                 (void)ixgbe_e_tag_enable(hw);
8350
8351         if (l2_tn_info->e_tag_fwd_en)
8352                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8353
8354         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8355 }
8356
8357 /* remove all the n-tuple filters */
8358 void
8359 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8360 {
8361         struct ixgbe_filter_info *filter_info =
8362                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8363         struct ixgbe_5tuple_filter *p_5tuple;
8364
8365         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8366                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8367 }
8368
8369 /* remove all the ether type filters */
8370 void
8371 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8372 {
8373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8374         struct ixgbe_filter_info *filter_info =
8375                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8376         int i;
8377
8378         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8379                 if (filter_info->ethertype_mask & (1 << i) &&
8380                     !filter_info->ethertype_filters[i].conf) {
8381                         (void)ixgbe_ethertype_filter_remove(filter_info,
8382                                                             (uint8_t)i);
8383                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8384                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8385                         IXGBE_WRITE_FLUSH(hw);
8386                 }
8387         }
8388 }
8389
8390 /* remove the SYN filter */
8391 void
8392 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8393 {
8394         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8395         struct ixgbe_filter_info *filter_info =
8396                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8397
8398         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8399                 filter_info->syn_info = 0;
8400
8401                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8402                 IXGBE_WRITE_FLUSH(hw);
8403         }
8404 }
8405
8406 /* remove all the L2 tunnel filters */
8407 int
8408 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8409 {
8410         struct ixgbe_l2_tn_info *l2_tn_info =
8411                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8412         struct ixgbe_l2_tn_filter *l2_tn_filter;
8413         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8414         int ret = 0;
8415
8416         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8417                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8418                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8419                 l2_tn_conf.pool           = l2_tn_filter->pool;
8420                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8421                 if (ret < 0)
8422                         return ret;
8423         }
8424
8425         return 0;
8426 }
8427
8428 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8429 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8430 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8431 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8432 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8433 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8434
8435 RTE_INIT(ixgbe_init_log);
8436 static void
8437 ixgbe_init_log(void)
8438 {
8439         ixgbe_logtype_init = rte_log_register("pmd.ixgbe.init");
8440         if (ixgbe_logtype_init >= 0)
8441                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8442         ixgbe_logtype_driver = rte_log_register("pmd.ixgbe.driver");
8443         if (ixgbe_logtype_driver >= 0)
8444                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8445 }