drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64 #include <rte_hash_crc.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 158 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 168 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static int
 186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 187                 uint64_t *values, unsigned int n);
 188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names,
 192         unsigned int size);
 193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 195 static int ixgbe_dev_xstats_get_names_by_id(
 196         struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names,
 198         const uint64_t *ids,
 199         unsigned int limit);
 200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 201                                              uint16_t queue_id,
 202                                              uint8_t stat_idx,
 203                                              uint8_t is_rx);
 204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 205                                  size_t fw_size);
 206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_dev_info *dev_info);
 208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 210                                  struct rte_eth_dev_info *dev_info);
 211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 212
 213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 216                                enum rte_vlan_type vlan_type,
 217                                uint16_t tpid_id);
 218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 219                 uint16_t queue, bool on);
 220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 221                 int on);
 222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 227
 228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 233                                struct rte_eth_fc_conf *fc_conf);
 234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 235                 struct rte_eth_pfc_conf *pfc_conf);
 236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 237                         struct rte_eth_rss_reta_entry64 *reta_conf,
 238                         uint16_t reta_size);
 239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_reta_entry64 *reta_conf,
 241                         uint16_t reta_size);
 242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 248                                       struct rte_intr_handle *handle);
 249 static void ixgbe_dev_interrupt_handler(void *param);
 250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 252                          uint32_t index, uint32_t pool);
 253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 255                                            struct ether_addr *mac_addr);
 256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 257 static bool is_device_supported(struct rte_eth_dev *dev,
 258                                 struct rte_pci_driver *drv);
 259
 260 /* For Virtual Function support */
 261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 263 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 264 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 265 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 266                                    int wait_to_complete);
 267 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 268 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 269 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 270 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 271 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 272                 struct rte_eth_stats *stats);
 273 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 274 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 275                 uint16_t vlan_id, int on);
 276 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 277                 uint16_t queue, int on);
 278 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 279 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 280 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 281                                             uint16_t queue_id);
 282 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 283                                              uint16_t queue_id);
 284 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 285                                  uint8_t queue, uint8_t msix_vector);
 286 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 287 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 288 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 289
 290 /* For Eth VMDQ APIs support */
 291 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 292                 ether_addr * mac_addr, uint8_t on);
 293 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 294 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 295                 struct rte_eth_mirror_conf *mirror_conf,
 296                 uint8_t rule_id, uint8_t on);
 297 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 298                 uint8_t rule_id);
 299 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 300                                           uint16_t queue_id);
 301 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 302                                            uint16_t queue_id);
 303 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 304                                uint8_t queue, uint8_t msix_vector);
 305 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 306
 307 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 308                                 struct ether_addr *mac_addr,
 309                                 uint32_t index, uint32_t pool);
 310 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 311 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 312                                              struct ether_addr *mac_addr);
 313 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 314                         struct rte_eth_syn_filter *filter);
 315 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 316                         enum rte_filter_op filter_op,
 317                         void *arg);
 318 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 319                         struct ixgbe_5tuple_filter *filter);
 320 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ntuple_filter *filter);
 327 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 328                                 enum rte_filter_op filter_op,
 329                                 void *arg);
 330 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 331                         struct rte_eth_ethertype_filter *filter);
 332 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 333                      enum rte_filter_type filter_type,
 334                      enum rte_filter_op filter_op,
 335                      void *arg);
 336 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 337
 338 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 339                                       struct ether_addr *mc_addr_set,
 340                                       uint32_t nb_mc_addr);
 341 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 342                                    struct rte_eth_dcb_info *dcb_info);
 343
 344 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 345 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 346                             struct rte_dev_reg_info *regs);
 347 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 348 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 349                                 struct rte_dev_eeprom_info *eeprom);
 350 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 351                                 struct rte_dev_eeprom_info *eeprom);
 352
 353 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 354 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 355                                 struct rte_dev_reg_info *regs);
 356
 357 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 358 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 359 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 360                                             struct timespec *timestamp,
 361                                             uint32_t flags);
 362 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 363                                             struct timespec *timestamp);
 364 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 365 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 366                                    struct timespec *timestamp);
 367 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 368                                    const struct timespec *timestamp);
 369 static void ixgbevf_dev_interrupt_handler(void *param);
 370
 371 static int ixgbe_dev_l2_tunnel_eth_type_conf
 372         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 373 static int ixgbe_dev_l2_tunnel_offload_set
 374         (struct rte_eth_dev *dev,
 375          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 376          uint32_t mask,
 377          uint8_t en);
 378 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 379                                              enum rte_filter_op filter_op,
 380                                              void *arg);
 381
 382 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 383                                          struct rte_eth_udp_tunnel *udp_tunnel);
 384 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 385                                          struct rte_eth_udp_tunnel *udp_tunnel);
 386 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 387 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 388
 389 /*
 390  * Define VF Stats MACRO for Non "cleared on read" register
 391  */
 392 #define UPDATE_VF_STAT(reg, last, cur)                          \
 393 {                                                               \
 394         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 395         cur += (latest - last) & UINT_MAX;                      \
 396         last = latest;                                          \
 397 }
 398
 399 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 400 {                                                                \
 401         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 402         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 403         u64 latest = ((new_msb << 32) | new_lsb);                \
 404         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 405         last = latest;                                           \
 406 }
 407
 408 #define IXGBE_SET_HWSTRIP(h, q) do {\
 409                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 410                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 411                 (h)->bitmap[idx] |= 1 << bit;\
 412         } while (0)
 413
 414 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 415                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 416                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 417                 (h)->bitmap[idx] &= ~(1 << bit);\
 418         } while (0)
 419
 420 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 421                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 422                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 423                 (r) = (h)->bitmap[idx] >> bit & 1;\
 424         } while (0)
 425
 426 /*
 427  * The set of PCI devices this driver supports
 428  */
 429 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 483 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 485 #endif
 486         { .vendor_id = 0, /* sentinel */ },
 487 };
 488
 489 /*
 490  * The set of PCI devices this driver supports (for 82599 VF)
 491  */
 492 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 503         { .vendor_id = 0, /* sentinel */ },
 504 };
 505
 506 static const struct rte_eth_desc_lim rx_desc_lim = {
 507         .nb_max = IXGBE_MAX_RING_DESC,
 508         .nb_min = IXGBE_MIN_RING_DESC,
 509         .nb_align = IXGBE_RXD_ALIGN,
 510 };
 511
 512 static const struct rte_eth_desc_lim tx_desc_lim = {
 513         .nb_max = IXGBE_MAX_RING_DESC,
 514         .nb_min = IXGBE_MIN_RING_DESC,
 515         .nb_align = IXGBE_TXD_ALIGN,
 516         .nb_seg_max = IXGBE_TX_MAX_SEG,
 517         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 518 };
 519
 520 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 521         .dev_configure        = ixgbe_dev_configure,
 522         .dev_start            = ixgbe_dev_start,
 523         .dev_stop             = ixgbe_dev_stop,
 524         .dev_set_link_up    = ixgbe_dev_set_link_up,
 525         .dev_set_link_down  = ixgbe_dev_set_link_down,
 526         .dev_close            = ixgbe_dev_close,
 527         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 528         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 529         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 530         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 531         .link_update          = ixgbe_dev_link_update,
 532         .stats_get            = ixgbe_dev_stats_get,
 533         .xstats_get           = ixgbe_dev_xstats_get,
 534         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 535         .stats_reset          = ixgbe_dev_stats_reset,
 536         .xstats_reset         = ixgbe_dev_xstats_reset,
 537         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 538         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 539         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 540         .fw_version_get       = ixgbe_fw_version_get,
 541         .dev_infos_get        = ixgbe_dev_info_get,
 542         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 543         .mtu_set              = ixgbe_dev_mtu_set,
 544         .vlan_filter_set      = ixgbe_vlan_filter_set,
 545         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 546         .vlan_offload_set     = ixgbe_vlan_offload_set,
 547         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 548         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 549         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 550         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 551         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 552         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 553         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 554         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 555         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 556         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 557         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 558         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 559         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 560         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 561         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 562         .dev_led_on           = ixgbe_dev_led_on,
 563         .dev_led_off          = ixgbe_dev_led_off,
 564         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 565         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 566         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 567         .mac_addr_add         = ixgbe_add_rar,
 568         .mac_addr_remove      = ixgbe_remove_rar,
 569         .mac_addr_set         = ixgbe_set_default_mac_addr,
 570         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 571         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 572         .mirror_rule_set      = ixgbe_mirror_rule_set,
 573         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 574         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 575         .reta_update          = ixgbe_dev_rss_reta_update,
 576         .reta_query           = ixgbe_dev_rss_reta_query,
 577         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 578         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 579         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 580         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 581         .rxq_info_get         = ixgbe_rxq_info_get,
 582         .txq_info_get         = ixgbe_txq_info_get,
 583         .timesync_enable      = ixgbe_timesync_enable,
 584         .timesync_disable     = ixgbe_timesync_disable,
 585         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 586         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 587         .get_reg              = ixgbe_get_regs,
 588         .get_eeprom_length    = ixgbe_get_eeprom_length,
 589         .get_eeprom           = ixgbe_get_eeprom,
 590         .set_eeprom           = ixgbe_set_eeprom,
 591         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 592         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 593         .timesync_read_time   = ixgbe_timesync_read_time,
 594         .timesync_write_time  = ixgbe_timesync_write_time,
 595         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 596         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 597         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 598         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 599         .tm_ops_get           = ixgbe_tm_ops_get,
 600 };
 601
 602 /*
 603  * dev_ops for virtual function, bare necessities for basic vf
 604  * operation have been implemented
 605  */
 606 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 607         .dev_configure        = ixgbevf_dev_configure,
 608         .dev_start            = ixgbevf_dev_start,
 609         .dev_stop             = ixgbevf_dev_stop,
 610         .link_update          = ixgbevf_dev_link_update,
 611         .stats_get            = ixgbevf_dev_stats_get,
 612         .xstats_get           = ixgbevf_dev_xstats_get,
 613         .stats_reset          = ixgbevf_dev_stats_reset,
 614         .xstats_reset         = ixgbevf_dev_stats_reset,
 615         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 616         .dev_close            = ixgbevf_dev_close,
 617         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 618         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 619         .dev_infos_get        = ixgbevf_dev_info_get,
 620         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 621         .mtu_set              = ixgbevf_dev_set_mtu,
 622         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 623         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 624         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 625         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 626         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 627         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 628         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 629         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 630         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 631         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 632         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 633         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 634         .mac_addr_add         = ixgbevf_add_mac_addr,
 635         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 636         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 637         .rxq_info_get         = ixgbe_rxq_info_get,
 638         .txq_info_get         = ixgbe_txq_info_get,
 639         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 640         .get_reg              = ixgbevf_get_regs,
 641         .reta_update          = ixgbe_dev_rss_reta_update,
 642         .reta_query           = ixgbe_dev_rss_reta_query,
 643         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 644         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 645 };
 646
 647 /* store statistics names and its offset in stats structure */
 648 struct rte_ixgbe_xstats_name_off {
 649         char name[RTE_ETH_XSTATS_NAME_SIZE];
 650         unsigned offset;
 651 };
 652
 653 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 654         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 655         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 656         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 657         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 658         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 659         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 660         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 661         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 662         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 663         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 664         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 665         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 666         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 667         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 668         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 669                 prc1023)},
 670         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 671                 prc1522)},
 672         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 673         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 674         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 675         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 676         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 677         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 678         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 679         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 680         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 681         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 682         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 683         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 684         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 685         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 686         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 687         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 688         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 689                 ptc1023)},
 690         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 691                 ptc1522)},
 692         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 693         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 694         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 695         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 696
 697         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirustat_add)},
 699         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirustat_remove)},
 701         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 702                 fdirfstat_fadd)},
 703         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 704                 fdirfstat_fremove)},
 705         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirmatch)},
 707         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirmiss)},
 709
 710         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 711         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 712         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 713                 fclast)},
 714         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 715         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 716         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 717         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 718         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 719                 fcoe_noddp)},
 720         {"rx_fcoe_no_direct_data_placement_ext_buff",
 721                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 722
 723         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 724                 lxontxc)},
 725         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 726                 lxonrxc)},
 727         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 728                 lxofftxc)},
 729         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 730                 lxoffrxc)},
 731         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 732 };
 733
 734 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 735                            sizeof(rte_ixgbe_stats_strings[0]))
 736
 737 /* MACsec statistics */
 738 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 739         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 740                 out_pkts_untagged)},
 741         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 742                 out_pkts_encrypted)},
 743         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 744                 out_pkts_protected)},
 745         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 746                 out_octets_encrypted)},
 747         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 748                 out_octets_protected)},
 749         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_untagged)},
 751         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_badtag)},
 753         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_nosci)},
 755         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unknownsci)},
 757         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 758                 in_octets_decrypted)},
 759         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 760                 in_octets_validated)},
 761         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_unchecked)},
 763         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_delayed)},
 765         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_late)},
 767         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_ok)},
 769         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_invalid)},
 771         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_notvalid)},
 773         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_unusedsa)},
 775         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_notusingsa)},
 777 };
 778
 779 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 780                            sizeof(rte_ixgbe_macsec_strings[0]))
 781
 782 /* Per-queue statistics */
 783 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 784         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 785         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 786         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 787         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 788 };
 789
 790 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 791                            sizeof(rte_ixgbe_rxq_strings[0]))
 792 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 793
 794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 795         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 796         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 797         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 798                 pxon2offc)},
 799 };
 800
 801 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 802                            sizeof(rte_ixgbe_txq_strings[0]))
 803 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 804
 805 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 806         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 807 };
 808
 809 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 810                 sizeof(rte_ixgbevf_stats_strings[0]))
 811
 812 /**
 813  * Atomically reads the link status information from global
 814  * structure rte_eth_dev.
 815  *
 816  * @param dev
 817  *   - Pointer to the structure rte_eth_dev to read from.
 818  *   - Pointer to the buffer to be saved with the link status.
 819  *
 820  * @return
 821  *   - On success, zero.
 822  *   - On failure, negative value.
 823  */
 824 static inline int
 825 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 826                                 struct rte_eth_link *link)
 827 {
 828         struct rte_eth_link *dst = link;
 829         struct rte_eth_link *src = &(dev->data->dev_link);
 830
 831         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 832                                         *(uint64_t *)src) == 0)
 833                 return -1;
 834
 835         return 0;
 836 }
 837
 838 /**
 839  * Atomically writes the link status information into global
 840  * structure rte_eth_dev.
 841  *
 842  * @param dev
 843  *   - Pointer to the structure rte_eth_dev to read from.
 844  *   - Pointer to the buffer to be saved with the link status.
 845  *
 846  * @return
 847  *   - On success, zero.
 848  *   - On failure, negative value.
 849  */
 850 static inline int
 851 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 852                                 struct rte_eth_link *link)
 853 {
 854         struct rte_eth_link *dst = &(dev->data->dev_link);
 855         struct rte_eth_link *src = link;
 856
 857         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 858                                         *(uint64_t *)src) == 0)
 859                 return -1;
 860
 861         return 0;
 862 }
 863
 864 /*
 865  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 866  */
 867 static inline int
 868 ixgbe_is_sfp(struct ixgbe_hw *hw)
 869 {
 870         switch (hw->phy.type) {
 871         case ixgbe_phy_sfp_avago:
 872         case ixgbe_phy_sfp_ftl:
 873         case ixgbe_phy_sfp_intel:
 874         case ixgbe_phy_sfp_unknown:
 875         case ixgbe_phy_sfp_passive_tyco:
 876         case ixgbe_phy_sfp_passive_unknown:
 877                 return 1;
 878         default:
 879                 return 0;
 880         }
 881 }
 882
 883 static inline int32_t
 884 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 885 {
 886         uint32_t ctrl_ext;
 887         int32_t status;
 888
 889         status = ixgbe_reset_hw(hw);
 890
 891         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 892         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 893         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 894         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 895         IXGBE_WRITE_FLUSH(hw);
 896
 897         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 898                 status = IXGBE_SUCCESS;
 899         return status;
 900 }
 901
 902 static inline void
 903 ixgbe_enable_intr(struct rte_eth_dev *dev)
 904 {
 905         struct ixgbe_interrupt *intr =
 906                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 907         struct ixgbe_hw *hw =
 908                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 909
 910         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 911         IXGBE_WRITE_FLUSH(hw);
 912 }
 913
 914 /*
 915  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 916  */
 917 static void
 918 ixgbe_disable_intr(struct ixgbe_hw *hw)
 919 {
 920         PMD_INIT_FUNC_TRACE();
 921
 922         if (hw->mac.type == ixgbe_mac_82598EB) {
 923                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 924         } else {
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 927                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 928         }
 929         IXGBE_WRITE_FLUSH(hw);
 930 }
 931
 932 /*
 933  * This function resets queue statistics mapping registers.
 934  * From Niantic datasheet, Initialization of Statistics section:
 935  * "...if software requires the queue counters, the RQSMR and TQSM registers
 936  * must be re-programmed following a device reset.
 937  */
 938 static void
 939 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 940 {
 941         uint32_t i;
 942
 943         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 944                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 946         }
 947 }
 948
 949
 950 static int
 951 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 952                                   uint16_t queue_id,
 953                                   uint8_t stat_idx,
 954                                   uint8_t is_rx)
 955 {
 956 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 957 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 958 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 959
 960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 961         struct ixgbe_stat_mapping_registers *stat_mappings =
 962                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 963         uint32_t qsmr_mask = 0;
 964         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 965         uint32_t q_map;
 966         uint8_t n, offset;
 967
 968         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 969                 (hw->mac.type != ixgbe_mac_X540) &&
 970                 (hw->mac.type != ixgbe_mac_X550) &&
 971                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 972                 (hw->mac.type != ixgbe_mac_X550EM_a))
 973                 return -ENOSYS;
 974
 975         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 976                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 977                      queue_id, stat_idx);
 978
 979         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 980         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 981                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 982                 return -EIO;
 983         }
 984         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 985
 986         /* Now clear any previous stat_idx set */
 987         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 988         if (!is_rx)
 989                 stat_mappings->tqsm[n] &= ~clearing_mask;
 990         else
 991                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 992
 993         q_map = (uint32_t)stat_idx;
 994         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 995         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 996         if (!is_rx)
 997                 stat_mappings->tqsm[n] |= qsmr_mask;
 998         else
 999                 stat_mappings->rqsmr[n] |= qsmr_mask;
1000
1001         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1002                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1003                      queue_id, stat_idx);
1004         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1005                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1006
1007         /* Now write the mapping in the appropriate register */
1008         if (is_rx) {
1009                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1010                              stat_mappings->rqsmr[n], n);
1011                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1012         } else {
1013                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1014                              stat_mappings->tqsm[n], n);
1015                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1016         }
1017         return 0;
1018 }
1019
1020 static void
1021 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1022 {
1023         struct ixgbe_stat_mapping_registers *stat_mappings =
1024                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026         int i;
1027
1028         /* write whatever was in stat mapping table to the NIC */
1029         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1030                 /* rx */
1031                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1032
1033                 /* tx */
1034                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1035         }
1036 }
1037
1038 static void
1039 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1040 {
1041         uint8_t i;
1042         struct ixgbe_dcb_tc_config *tc;
1043         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1044
1045         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1046         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1047         for (i = 0; i < dcb_max_tc; i++) {
1048                 tc = &dcb_config->tc_config[i];
1049                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1050                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1051                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1052                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1053                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1054                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1055                 tc->pfc = ixgbe_dcb_pfc_disabled;
1056         }
1057
1058         /* Initialize default user to priority mapping, UPx->TC0 */
1059         tc = &dcb_config->tc_config[0];
1060         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1061         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1062         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1063                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1064                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1065         }
1066         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1067         dcb_config->pfc_mode_enable = false;
1068         dcb_config->vt_mode = true;
1069         dcb_config->round_robin_enable = false;
1070         /* support all DCB capabilities in 82599 */
1071         dcb_config->support.capabilities = 0xFF;
1072
1073         /*we only support 4 Tcs for X540, X550 */
1074         if (hw->mac.type == ixgbe_mac_X540 ||
1075                 hw->mac.type == ixgbe_mac_X550 ||
1076                 hw->mac.type == ixgbe_mac_X550EM_x ||
1077                 hw->mac.type == ixgbe_mac_X550EM_a) {
1078                 dcb_config->num_tcs.pg_tcs = 4;
1079                 dcb_config->num_tcs.pfc_tcs = 4;
1080         }
1081 }
1082
1083 /*
1084  * Ensure that all locks are released before first NVM or PHY access
1085  */
1086 static void
1087 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1088 {
1089         uint16_t mask;
1090
1091         /*
1092          * Phy lock should not fail in this early stage. If this is the case,
1093          * it is due to an improper exit of the application.
1094          * So force the release of the faulty lock. Release of common lock
1095          * is done automatically by swfw_sync function.
1096          */
1097         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1098         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1099                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1100         }
1101         ixgbe_release_swfw_semaphore(hw, mask);
1102
1103         /*
1104          * These ones are more tricky since they are common to all ports; but
1105          * swfw_sync retries last long enough (1s) to be almost sure that if
1106          * lock can not be taken it is due to an improper lock of the
1107          * semaphore.
1108          */
1109         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1110         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1111                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1112         }
1113         ixgbe_release_swfw_semaphore(hw, mask);
1114 }
1115
1116 /*
1117  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1118  * It returns 0 on success.
1119  */
1120 static int
1121 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1122 {
1123         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1124         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1125         struct ixgbe_hw *hw =
1126                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1127         struct ixgbe_vfta *shadow_vfta =
1128                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1129         struct ixgbe_hwstrip *hwstrip =
1130                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1131         struct ixgbe_dcb_config *dcb_config =
1132                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1133         struct ixgbe_filter_info *filter_info =
1134                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1135         struct ixgbe_bw_conf *bw_conf =
1136                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1137         uint32_t ctrl_ext;
1138         uint16_t csum;
1139         int diag, i;
1140
1141         PMD_INIT_FUNC_TRACE();
1142
1143         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1144         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1145         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1146         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1147
1148         /*
1149          * For secondary processes, we don't initialise any further as primary
1150          * has already done this work. Only check we don't need a different
1151          * RX and TX function.
1152          */
1153         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1154                 struct ixgbe_tx_queue *txq;
1155                 /* TX queue function in primary, set by last queue initialized
1156                  * Tx queue may not initialized by primary process
1157                  */
1158                 if (eth_dev->data->tx_queues) {
1159                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1160                         ixgbe_set_tx_function(eth_dev, txq);
1161                 } else {
1162                         /* Use default TX function if we get here */
1163                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1164                                      "Using default TX function.");
1165                 }
1166
1167                 ixgbe_set_rx_function(eth_dev);
1168
1169                 return 0;
1170         }
1171
1172         rte_eth_copy_pci_info(eth_dev, pci_dev);
1173         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1174
1175         /* Vendor and Device ID need to be set before init of shared code */
1176         hw->device_id = pci_dev->id.device_id;
1177         hw->vendor_id = pci_dev->id.vendor_id;
1178         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1179         hw->allow_unsupported_sfp = 1;
1180
1181         /* Initialize the shared code (base driver) */
1182 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1183         diag = ixgbe_bypass_init_shared_code(hw);
1184 #else
1185         diag = ixgbe_init_shared_code(hw);
1186 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1187
1188         if (diag != IXGBE_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1190                 return -EIO;
1191         }
1192
1193         /* pick up the PCI bus settings for reporting later */
1194         ixgbe_get_bus_info(hw);
1195
1196         /* Unlock any pending hardware semaphore */
1197         ixgbe_swfw_lock_reset(hw);
1198
1199         /* Initialize DCB configuration*/
1200         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1201         ixgbe_dcb_init(hw, dcb_config);
1202         /* Get Hardware Flow Control setting */
1203         hw->fc.requested_mode = ixgbe_fc_full;
1204         hw->fc.current_mode = ixgbe_fc_full;
1205         hw->fc.pause_time = IXGBE_FC_PAUSE;
1206         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1207                 hw->fc.low_water[i] = IXGBE_FC_LO;
1208                 hw->fc.high_water[i] = IXGBE_FC_HI;
1209         }
1210         hw->fc.send_xon = 1;
1211
1212         /* Make sure we have a good EEPROM before we read from it */
1213         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1214         if (diag != IXGBE_SUCCESS) {
1215                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1216                 return -EIO;
1217         }
1218
1219 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1220         diag = ixgbe_bypass_init_hw(hw);
1221 #else
1222         diag = ixgbe_init_hw(hw);
1223 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1224
1225         /*
1226          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1227          * is called too soon after the kernel driver unbinding/binding occurs.
1228          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1229          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1230          * also called. See ixgbe_identify_phy_82599(). The reason for the
1231          * failure is not known, and only occuts when virtualisation features
1232          * are disabled in the bios. A delay of 100ms  was found to be enough by
1233          * trial-and-error, and is doubled to be safe.
1234          */
1235         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1236                 rte_delay_ms(200);
1237                 diag = ixgbe_init_hw(hw);
1238         }
1239
1240         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1241                 diag = IXGBE_SUCCESS;
1242
1243         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1244                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1245                              "LOM.  Please be aware there may be issues associated "
1246                              "with your hardware.");
1247                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1248                              "please contact your Intel or hardware representative "
1249                              "who provided you with this hardware.");
1250         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1251                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1252         if (diag) {
1253                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1254                 return -EIO;
1255         }
1256
1257         /* Reset the hw statistics */
1258         ixgbe_dev_stats_reset(eth_dev);
1259
1260         /* disable interrupt */
1261         ixgbe_disable_intr(hw);
1262
1263         /* reset mappings for queue statistics hw counters*/
1264         ixgbe_reset_qstat_mappings(hw);
1265
1266         /* Allocate memory for storing MAC addresses */
1267         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1268                                                hw->mac.num_rar_entries, 0);
1269         if (eth_dev->data->mac_addrs == NULL) {
1270                 PMD_INIT_LOG(ERR,
1271                              "Failed to allocate %u bytes needed to store "
1272                              "MAC addresses",
1273                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1274                 return -ENOMEM;
1275         }
1276         /* Copy the permanent MAC address */
1277         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1278                         &eth_dev->data->mac_addrs[0]);
1279
1280         /* Allocate memory for storing hash filter MAC addresses */
1281         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1282                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1283         if (eth_dev->data->hash_mac_addrs == NULL) {
1284                 PMD_INIT_LOG(ERR,
1285                              "Failed to allocate %d bytes needed to store MAC addresses",
1286                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1287                 return -ENOMEM;
1288         }
1289
1290         /* initialize the vfta */
1291         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1292
1293         /* initialize the hw strip bitmap*/
1294         memset(hwstrip, 0, sizeof(*hwstrip));
1295
1296         /* initialize PF if max_vfs not zero */
1297         ixgbe_pf_host_init(eth_dev);
1298
1299         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1300         /* let hardware know driver is loaded */
1301         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1302         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1303         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1304         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1305         IXGBE_WRITE_FLUSH(hw);
1306
1307         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1308                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1309                              (int) hw->mac.type, (int) hw->phy.type,
1310                              (int) hw->phy.sfp_type);
1311         else
1312                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1313                              (int) hw->mac.type, (int) hw->phy.type);
1314
1315         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1316                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1317                      pci_dev->id.device_id);
1318
1319         rte_intr_callback_register(intr_handle,
1320                                    ixgbe_dev_interrupt_handler, eth_dev);
1321
1322         /* enable uio/vfio intr/eventfd mapping */
1323         rte_intr_enable(intr_handle);
1324
1325         /* enable support intr */
1326         ixgbe_enable_intr(eth_dev);
1327
1328         /* initialize filter info */
1329         memset(filter_info, 0,
1330                sizeof(struct ixgbe_filter_info));
1331
1332         /* initialize 5tuple filter list */
1333         TAILQ_INIT(&filter_info->fivetuple_list);
1334
1335         /* initialize flow director filter list & hash */
1336         ixgbe_fdir_filter_init(eth_dev);
1337
1338         /* initialize l2 tunnel filter list & hash */
1339         ixgbe_l2_tn_filter_init(eth_dev);
1340
1341         TAILQ_INIT(&filter_ntuple_list);
1342         TAILQ_INIT(&filter_ethertype_list);
1343         TAILQ_INIT(&filter_syn_list);
1344         TAILQ_INIT(&filter_fdir_list);
1345         TAILQ_INIT(&filter_l2_tunnel_list);
1346         TAILQ_INIT(&ixgbe_flow_list);
1347
1348         /* initialize bandwidth configuration info */
1349         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1350
1351         /* initialize Traffic Manager configuration */
1352         ixgbe_tm_conf_init(eth_dev);
1353
1354         return 0;
1355 }
1356
1357 static int
1358 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1359 {
1360         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1361         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1362         struct ixgbe_hw *hw;
1363
1364         PMD_INIT_FUNC_TRACE();
1365
1366         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1367                 return -EPERM;
1368
1369         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1370
1371         if (hw->adapter_stopped == 0)
1372                 ixgbe_dev_close(eth_dev);
1373
1374         eth_dev->dev_ops = NULL;
1375         eth_dev->rx_pkt_burst = NULL;
1376         eth_dev->tx_pkt_burst = NULL;
1377
1378         /* Unlock any pending hardware semaphore */
1379         ixgbe_swfw_lock_reset(hw);
1380
1381         /* disable uio intr before callback unregister */
1382         rte_intr_disable(intr_handle);
1383         rte_intr_callback_unregister(intr_handle,
1384                                      ixgbe_dev_interrupt_handler, eth_dev);
1385
1386         /* uninitialize PF if max_vfs not zero */
1387         ixgbe_pf_host_uninit(eth_dev);
1388
1389         rte_free(eth_dev->data->mac_addrs);
1390         eth_dev->data->mac_addrs = NULL;
1391
1392         rte_free(eth_dev->data->hash_mac_addrs);
1393         eth_dev->data->hash_mac_addrs = NULL;
1394
1395         /* remove all the fdir filters & hash */
1396         ixgbe_fdir_filter_uninit(eth_dev);
1397
1398         /* remove all the L2 tunnel filters & hash */
1399         ixgbe_l2_tn_filter_uninit(eth_dev);
1400
1401         /* Remove all ntuple filters of the device */
1402         ixgbe_ntuple_filter_uninit(eth_dev);
1403
1404         /* clear all the filters list */
1405         ixgbe_filterlist_flush();
1406
1407         /* Remove all Traffic Manager configuration */
1408         ixgbe_tm_conf_uninit(eth_dev);
1409
1410         return 0;
1411 }
1412
1413 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1414 {
1415         struct ixgbe_filter_info *filter_info =
1416                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1417         struct ixgbe_5tuple_filter *p_5tuple;
1418
1419         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1420                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1421                              p_5tuple,
1422                              entries);
1423                 rte_free(p_5tuple);
1424         }
1425         memset(filter_info->fivetuple_mask, 0,
1426                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1427
1428         return 0;
1429 }
1430
1431 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1432 {
1433         struct ixgbe_hw_fdir_info *fdir_info =
1434                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1435         struct ixgbe_fdir_filter *fdir_filter;
1436
1437                 if (fdir_info->hash_map)
1438                 rte_free(fdir_info->hash_map);
1439         if (fdir_info->hash_handle)
1440                 rte_hash_free(fdir_info->hash_handle);
1441
1442         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1443                 TAILQ_REMOVE(&fdir_info->fdir_list,
1444                              fdir_filter,
1445                              entries);
1446                 rte_free(fdir_filter);
1447         }
1448
1449         return 0;
1450 }
1451
1452 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1453 {
1454         struct ixgbe_l2_tn_info *l2_tn_info =
1455                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1456         struct ixgbe_l2_tn_filter *l2_tn_filter;
1457
1458         if (l2_tn_info->hash_map)
1459                 rte_free(l2_tn_info->hash_map);
1460         if (l2_tn_info->hash_handle)
1461                 rte_hash_free(l2_tn_info->hash_handle);
1462
1463         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1464                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1465                              l2_tn_filter,
1466                              entries);
1467                 rte_free(l2_tn_filter);
1468         }
1469
1470         return 0;
1471 }
1472
1473 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1474 {
1475         struct ixgbe_hw_fdir_info *fdir_info =
1476                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1477         char fdir_hash_name[RTE_HASH_NAMESIZE];
1478         struct rte_hash_parameters fdir_hash_params = {
1479                 .name = fdir_hash_name,
1480                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1481                 .key_len = sizeof(union ixgbe_atr_input),
1482                 .hash_func = rte_hash_crc,
1483                 .hash_func_init_val = 0,
1484                 .socket_id = rte_socket_id(),
1485         };
1486
1487         TAILQ_INIT(&fdir_info->fdir_list);
1488         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1489                  "fdir_%s", eth_dev->device->name);
1490         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1491         if (!fdir_info->hash_handle) {
1492                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1493                 return -EINVAL;
1494         }
1495         fdir_info->hash_map = rte_zmalloc("ixgbe",
1496                                           sizeof(struct ixgbe_fdir_filter *) *
1497                                           IXGBE_MAX_FDIR_FILTER_NUM,
1498                                           0);
1499         if (!fdir_info->hash_map) {
1500                 PMD_INIT_LOG(ERR,
1501                              "Failed to allocate memory for fdir hash map!");
1502                 return -ENOMEM;
1503         }
1504         fdir_info->mask_added = FALSE;
1505
1506         return 0;
1507 }
1508
1509 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1510 {
1511         struct ixgbe_l2_tn_info *l2_tn_info =
1512                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1513         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1514         struct rte_hash_parameters l2_tn_hash_params = {
1515                 .name = l2_tn_hash_name,
1516                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1517                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1518                 .hash_func = rte_hash_crc,
1519                 .hash_func_init_val = 0,
1520                 .socket_id = rte_socket_id(),
1521         };
1522
1523         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1524         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1525                  "l2_tn_%s", eth_dev->device->name);
1526         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1527         if (!l2_tn_info->hash_handle) {
1528                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1529                 return -EINVAL;
1530         }
1531         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1532                                    sizeof(struct ixgbe_l2_tn_filter *) *
1533                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1534                                    0);
1535         if (!l2_tn_info->hash_map) {
1536                 PMD_INIT_LOG(ERR,
1537                         "Failed to allocate memory for L2 TN hash map!");
1538                 return -ENOMEM;
1539         }
1540         l2_tn_info->e_tag_en = FALSE;
1541         l2_tn_info->e_tag_fwd_en = FALSE;
1542         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1543
1544         return 0;
1545 }
1546 /*
1547  * Negotiate mailbox API version with the PF.
1548  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1549  * Then we try to negotiate starting with the most recent one.
1550  * If all negotiation attempts fail, then we will proceed with
1551  * the default one (ixgbe_mbox_api_10).
1552  */
1553 static void
1554 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1555 {
1556         int32_t i;
1557
1558         /* start with highest supported, proceed down */
1559         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1560                 ixgbe_mbox_api_12,
1561                 ixgbe_mbox_api_11,
1562                 ixgbe_mbox_api_10,
1563         };
1564
1565         for (i = 0;
1566                         i != RTE_DIM(sup_ver) &&
1567                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1568                         i++)
1569                 ;
1570 }
1571
1572 static void
1573 generate_random_mac_addr(struct ether_addr *mac_addr)
1574 {
1575         uint64_t random;
1576
1577         /* Set Organizationally Unique Identifier (OUI) prefix. */
1578         mac_addr->addr_bytes[0] = 0x00;
1579         mac_addr->addr_bytes[1] = 0x09;
1580         mac_addr->addr_bytes[2] = 0xC0;
1581         /* Force indication of locally assigned MAC address. */
1582         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1583         /* Generate the last 3 bytes of the MAC address with a random number. */
1584         random = rte_rand();
1585         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1586 }
1587
1588 /*
1589  * Virtual Function device init
1590  */
1591 static int
1592 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1593 {
1594         int diag;
1595         uint32_t tc, tcs;
1596         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1597         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1598         struct ixgbe_hw *hw =
1599                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1600         struct ixgbe_vfta *shadow_vfta =
1601                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1602         struct ixgbe_hwstrip *hwstrip =
1603                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1604         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1605
1606         PMD_INIT_FUNC_TRACE();
1607
1608         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1609         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1610         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1611
1612         /* for secondary processes, we don't initialise any further as primary
1613          * has already done this work. Only check we don't need a different
1614          * RX function
1615          */
1616         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1617                 struct ixgbe_tx_queue *txq;
1618                 /* TX queue function in primary, set by last queue initialized
1619                  * Tx queue may not initialized by primary process
1620                  */
1621                 if (eth_dev->data->tx_queues) {
1622                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1623                         ixgbe_set_tx_function(eth_dev, txq);
1624                 } else {
1625                         /* Use default TX function if we get here */
1626                         PMD_INIT_LOG(NOTICE,
1627                                      "No TX queues configured yet. Using default TX function.");
1628                 }
1629
1630                 ixgbe_set_rx_function(eth_dev);
1631
1632                 return 0;
1633         }
1634
1635         rte_eth_copy_pci_info(eth_dev, pci_dev);
1636         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1637
1638         hw->device_id = pci_dev->id.device_id;
1639         hw->vendor_id = pci_dev->id.vendor_id;
1640         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1641
1642         /* initialize the vfta */
1643         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1644
1645         /* initialize the hw strip bitmap*/
1646         memset(hwstrip, 0, sizeof(*hwstrip));
1647
1648         /* Initialize the shared code (base driver) */
1649         diag = ixgbe_init_shared_code(hw);
1650         if (diag != IXGBE_SUCCESS) {
1651                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1652                 return -EIO;
1653         }
1654
1655         /* init_mailbox_params */
1656         hw->mbx.ops.init_params(hw);
1657
1658         /* Reset the hw statistics */
1659         ixgbevf_dev_stats_reset(eth_dev);
1660
1661         /* Disable the interrupts for VF */
1662         ixgbevf_intr_disable(hw);
1663
1664         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1665         diag = hw->mac.ops.reset_hw(hw);
1666
1667         /*
1668          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1669          * the underlying PF driver has not assigned a MAC address to the VF.
1670          * In this case, assign a random MAC address.
1671          */
1672         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1673                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1674                 return diag;
1675         }
1676
1677         /* negotiate mailbox API version to use with the PF. */
1678         ixgbevf_negotiate_api(hw);
1679
1680         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1681         ixgbevf_get_queues(hw, &tcs, &tc);
1682
1683         /* Allocate memory for storing MAC addresses */
1684         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1685                                                hw->mac.num_rar_entries, 0);
1686         if (eth_dev->data->mac_addrs == NULL) {
1687                 PMD_INIT_LOG(ERR,
1688                              "Failed to allocate %u bytes needed to store "
1689                              "MAC addresses",
1690                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1691                 return -ENOMEM;
1692         }
1693
1694         /* Generate a random MAC address, if none was assigned by PF. */
1695         if (is_zero_ether_addr(perm_addr)) {
1696                 generate_random_mac_addr(perm_addr);
1697                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1698                 if (diag) {
1699                         rte_free(eth_dev->data->mac_addrs);
1700                         eth_dev->data->mac_addrs = NULL;
1701                         return diag;
1702                 }
1703                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1704                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1705                              "%02x:%02x:%02x:%02x:%02x:%02x",
1706                              perm_addr->addr_bytes[0],
1707                              perm_addr->addr_bytes[1],
1708                              perm_addr->addr_bytes[2],
1709                              perm_addr->addr_bytes[3],
1710                              perm_addr->addr_bytes[4],
1711                              perm_addr->addr_bytes[5]);
1712         }
1713
1714         /* Copy the permanent MAC address */
1715         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1716
1717         /* reset the hardware with the new settings */
1718         diag = hw->mac.ops.start_hw(hw);
1719         switch (diag) {
1720         case  0:
1721                 break;
1722
1723         default:
1724                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1725                 return -EIO;
1726         }
1727
1728         rte_intr_callback_register(intr_handle,
1729                                    ixgbevf_dev_interrupt_handler, eth_dev);
1730         rte_intr_enable(intr_handle);
1731         ixgbevf_intr_enable(hw);
1732
1733         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1734                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1735                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1736
1737         return 0;
1738 }
1739
1740 /* Virtual Function device uninit */
1741
1742 static int
1743 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1744 {
1745         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1746         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1747         struct ixgbe_hw *hw;
1748
1749         PMD_INIT_FUNC_TRACE();
1750
1751         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1752                 return -EPERM;
1753
1754         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1755
1756         if (hw->adapter_stopped == 0)
1757                 ixgbevf_dev_close(eth_dev);
1758
1759         eth_dev->dev_ops = NULL;
1760         eth_dev->rx_pkt_burst = NULL;
1761         eth_dev->tx_pkt_burst = NULL;
1762
1763         /* Disable the interrupts for VF */
1764         ixgbevf_intr_disable(hw);
1765
1766         rte_free(eth_dev->data->mac_addrs);
1767         eth_dev->data->mac_addrs = NULL;
1768
1769         rte_intr_disable(intr_handle);
1770         rte_intr_callback_unregister(intr_handle,
1771                                      ixgbevf_dev_interrupt_handler, eth_dev);
1772
1773         return 0;
1774 }
1775
1776 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1777         struct rte_pci_device *pci_dev)
1778 {
1779         return rte_eth_dev_pci_generic_probe(pci_dev,
1780                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1781 }
1782
1783 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1784 {
1785         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1786 }
1787
1788 static struct rte_pci_driver rte_ixgbe_pmd = {
1789         .id_table = pci_id_ixgbe_map,
1790         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1791         .probe = eth_ixgbe_pci_probe,
1792         .remove = eth_ixgbe_pci_remove,
1793 };
1794
1795 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1796         struct rte_pci_device *pci_dev)
1797 {
1798         return rte_eth_dev_pci_generic_probe(pci_dev,
1799                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1800 }
1801
1802 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1803 {
1804         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1805 }
1806
1807 /*
1808  * virtual function driver struct
1809  */
1810 static struct rte_pci_driver rte_ixgbevf_pmd = {
1811         .id_table = pci_id_ixgbevf_map,
1812         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1813         .probe = eth_ixgbevf_pci_probe,
1814         .remove = eth_ixgbevf_pci_remove,
1815 };
1816
1817 static int
1818 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1819 {
1820         struct ixgbe_hw *hw =
1821                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1822         struct ixgbe_vfta *shadow_vfta =
1823                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1824         uint32_t vfta;
1825         uint32_t vid_idx;
1826         uint32_t vid_bit;
1827
1828         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1829         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1830         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1831         if (on)
1832                 vfta |= vid_bit;
1833         else
1834                 vfta &= ~vid_bit;
1835         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1836
1837         /* update local VFTA copy */
1838         shadow_vfta->vfta[vid_idx] = vfta;
1839
1840         return 0;
1841 }
1842
1843 static void
1844 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1845 {
1846         if (on)
1847                 ixgbe_vlan_hw_strip_enable(dev, queue);
1848         else
1849                 ixgbe_vlan_hw_strip_disable(dev, queue);
1850 }
1851
1852 static int
1853 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1854                     enum rte_vlan_type vlan_type,
1855                     uint16_t tpid)
1856 {
1857         struct ixgbe_hw *hw =
1858                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859         int ret = 0;
1860         uint32_t reg;
1861         uint32_t qinq;
1862
1863         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1864         qinq &= IXGBE_DMATXCTL_GDV;
1865
1866         switch (vlan_type) {
1867         case ETH_VLAN_TYPE_INNER:
1868                 if (qinq) {
1869                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1870                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1871                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1872                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1873                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1874                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1875                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1876                 } else {
1877                         ret = -ENOTSUP;
1878                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1879                                     " by single VLAN");
1880                 }
1881                 break;
1882         case ETH_VLAN_TYPE_OUTER:
1883                 if (qinq) {
1884                         /* Only the high 16-bits is valid */
1885                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1886                                         IXGBE_EXVET_VET_EXT_SHIFT);
1887                 } else {
1888                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1889                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1890                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1891                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1892                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1893                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1894                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1895                 }
1896
1897                 break;
1898         default:
1899                 ret = -EINVAL;
1900                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1901                 break;
1902         }
1903
1904         return ret;
1905 }
1906
1907 void
1908 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1909 {
1910         struct ixgbe_hw *hw =
1911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912         uint32_t vlnctrl;
1913
1914         PMD_INIT_FUNC_TRACE();
1915
1916         /* Filter Table Disable */
1917         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1918         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1919
1920         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1921 }
1922
1923 void
1924 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1925 {
1926         struct ixgbe_hw *hw =
1927                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         struct ixgbe_vfta *shadow_vfta =
1929                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1930         uint32_t vlnctrl;
1931         uint16_t i;
1932
1933         PMD_INIT_FUNC_TRACE();
1934
1935         /* Filter Table Enable */
1936         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1937         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1938         vlnctrl |= IXGBE_VLNCTRL_VFE;
1939
1940         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1941
1942         /* write whatever is in local vfta copy */
1943         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1944                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1945 }
1946
1947 static void
1948 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1949 {
1950         struct ixgbe_hwstrip *hwstrip =
1951                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1952         struct ixgbe_rx_queue *rxq;
1953
1954         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1955                 return;
1956
1957         if (on)
1958                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1959         else
1960                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1961
1962         if (queue >= dev->data->nb_rx_queues)
1963                 return;
1964
1965         rxq = dev->data->rx_queues[queue];
1966
1967         if (on)
1968                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1969         else
1970                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1971 }
1972
1973 static void
1974 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1975 {
1976         struct ixgbe_hw *hw =
1977                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978         uint32_t ctrl;
1979
1980         PMD_INIT_FUNC_TRACE();
1981
1982         if (hw->mac.type == ixgbe_mac_82598EB) {
1983                 /* No queue level support */
1984                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1985                 return;
1986         }
1987
1988         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1989         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1990         ctrl &= ~IXGBE_RXDCTL_VME;
1991         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1992
1993         /* record those setting for HW strip per queue */
1994         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1995 }
1996
1997 static void
1998 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1999 {
2000         struct ixgbe_hw *hw =
2001                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2002         uint32_t ctrl;
2003
2004         PMD_INIT_FUNC_TRACE();
2005
2006         if (hw->mac.type == ixgbe_mac_82598EB) {
2007                 /* No queue level supported */
2008                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2009                 return;
2010         }
2011
2012         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2013         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2014         ctrl |= IXGBE_RXDCTL_VME;
2015         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2016
2017         /* record those setting for HW strip per queue */
2018         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2019 }
2020
2021 void
2022 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2023 {
2024         struct ixgbe_hw *hw =
2025                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2026         uint32_t ctrl;
2027         uint16_t i;
2028         struct ixgbe_rx_queue *rxq;
2029
2030         PMD_INIT_FUNC_TRACE();
2031
2032         if (hw->mac.type == ixgbe_mac_82598EB) {
2033                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2034                 ctrl &= ~IXGBE_VLNCTRL_VME;
2035                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2036         } else {
2037                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2038                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2039                         rxq = dev->data->rx_queues[i];
2040                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2041                         ctrl &= ~IXGBE_RXDCTL_VME;
2042                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2043
2044                         /* record those setting for HW strip per queue */
2045                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2046                 }
2047         }
2048 }
2049
2050 void
2051 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2052 {
2053         struct ixgbe_hw *hw =
2054                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         uint32_t ctrl;
2056         uint16_t i;
2057         struct ixgbe_rx_queue *rxq;
2058
2059         PMD_INIT_FUNC_TRACE();
2060
2061         if (hw->mac.type == ixgbe_mac_82598EB) {
2062                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2063                 ctrl |= IXGBE_VLNCTRL_VME;
2064                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2065         } else {
2066                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2067                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2068                         rxq = dev->data->rx_queues[i];
2069                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2070                         ctrl |= IXGBE_RXDCTL_VME;
2071                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2072
2073                         /* record those setting for HW strip per queue */
2074                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2075                 }
2076         }
2077 }
2078
2079 static void
2080 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2081 {
2082         struct ixgbe_hw *hw =
2083                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084         uint32_t ctrl;
2085
2086         PMD_INIT_FUNC_TRACE();
2087
2088         /* DMATXCTRL: Geric Double VLAN Disable */
2089         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2090         ctrl &= ~IXGBE_DMATXCTL_GDV;
2091         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2092
2093         /* CTRL_EXT: Global Double VLAN Disable */
2094         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2095         ctrl &= ~IXGBE_EXTENDED_VLAN;
2096         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2097
2098 }
2099
2100 static void
2101 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2102 {
2103         struct ixgbe_hw *hw =
2104                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         uint32_t ctrl;
2106
2107         PMD_INIT_FUNC_TRACE();
2108
2109         /* DMATXCTRL: Geric Double VLAN Enable */
2110         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2111         ctrl |= IXGBE_DMATXCTL_GDV;
2112         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2113
2114         /* CTRL_EXT: Global Double VLAN Enable */
2115         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2116         ctrl |= IXGBE_EXTENDED_VLAN;
2117         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2118
2119         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2120         if (hw->mac.type == ixgbe_mac_X550 ||
2121             hw->mac.type == ixgbe_mac_X550EM_x ||
2122             hw->mac.type == ixgbe_mac_X550EM_a) {
2123                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2124                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2125                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2126         }
2127
2128         /*
2129          * VET EXT field in the EXVET register = 0x8100 by default
2130          * So no need to change. Same to VT field of DMATXCTL register
2131          */
2132 }
2133
2134 static void
2135 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2136 {
2137         if (mask & ETH_VLAN_STRIP_MASK) {
2138                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2139                         ixgbe_vlan_hw_strip_enable_all(dev);
2140                 else
2141                         ixgbe_vlan_hw_strip_disable_all(dev);
2142         }
2143
2144         if (mask & ETH_VLAN_FILTER_MASK) {
2145                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2146                         ixgbe_vlan_hw_filter_enable(dev);
2147                 else
2148                         ixgbe_vlan_hw_filter_disable(dev);
2149         }
2150
2151         if (mask & ETH_VLAN_EXTEND_MASK) {
2152                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2153                         ixgbe_vlan_hw_extend_enable(dev);
2154                 else
2155                         ixgbe_vlan_hw_extend_disable(dev);
2156         }
2157 }
2158
2159 static void
2160 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2161 {
2162         struct ixgbe_hw *hw =
2163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2165         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2166
2167         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2168         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2169 }
2170
2171 static int
2172 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2173 {
2174         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2175
2176         switch (nb_rx_q) {
2177         case 1:
2178         case 2:
2179                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2180                 break;
2181         case 4:
2182                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2183                 break;
2184         default:
2185                 return -EINVAL;
2186         }
2187
2188         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2189         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2190
2191         return 0;
2192 }
2193
2194 static int
2195 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2196 {
2197         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2198         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2199         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2200         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2201
2202         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2203                 /* check multi-queue mode */
2204                 switch (dev_conf->rxmode.mq_mode) {
2205                 case ETH_MQ_RX_VMDQ_DCB:
2206                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2207                         break;
2208                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2209                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2210                         PMD_INIT_LOG(ERR, "SRIOV active,"
2211                                         " unsupported mq_mode rx %d.",
2212                                         dev_conf->rxmode.mq_mode);
2213                         return -EINVAL;
2214                 case ETH_MQ_RX_RSS:
2215                 case ETH_MQ_RX_VMDQ_RSS:
2216                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2217                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2218                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2219                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2220                                                 " invalid queue number"
2221                                                 " for VMDQ RSS, allowed"
2222                                                 " value are 1, 2 or 4.");
2223                                         return -EINVAL;
2224                                 }
2225                         break;
2226                 case ETH_MQ_RX_VMDQ_ONLY:
2227                 case ETH_MQ_RX_NONE:
2228                         /* if nothing mq mode configure, use default scheme */
2229                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2230                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2231                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2232                         break;
2233                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2234                         /* SRIOV only works in VMDq enable mode */
2235                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2236                                         " wrong mq_mode rx %d.",
2237                                         dev_conf->rxmode.mq_mode);
2238                         return -EINVAL;
2239                 }
2240
2241                 switch (dev_conf->txmode.mq_mode) {
2242                 case ETH_MQ_TX_VMDQ_DCB:
2243                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2244                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2245                         break;
2246                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2247                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2248                         break;
2249                 }
2250
2251                 /* check valid queue number */
2252                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2253                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2254                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2255                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2256                                         " must be less than or equal to %d.",
2257                                         nb_rx_q, nb_tx_q,
2258                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2259                         return -EINVAL;
2260                 }
2261         } else {
2262                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2263                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2264                                           " not supported.");
2265                         return -EINVAL;
2266                 }
2267                 /* check configuration for vmdb+dcb mode */
2268                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2269                         const struct rte_eth_vmdq_dcb_conf *conf;
2270
2271                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2272                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2273                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2274                                 return -EINVAL;
2275                         }
2276                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2277                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2278                                conf->nb_queue_pools == ETH_32_POOLS)) {
2279                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2280                                                 " nb_queue_pools must be %d or %d.",
2281                                                 ETH_16_POOLS, ETH_32_POOLS);
2282                                 return -EINVAL;
2283                         }
2284                 }
2285                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2286                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2287
2288                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2289                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2290                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2291                                 return -EINVAL;
2292                         }
2293                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2294                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2295                                conf->nb_queue_pools == ETH_32_POOLS)) {
2296                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2297                                                 " nb_queue_pools != %d and"
2298                                                 " nb_queue_pools != %d.",
2299                                                 ETH_16_POOLS, ETH_32_POOLS);
2300                                 return -EINVAL;
2301                         }
2302                 }
2303
2304                 /* For DCB mode check our configuration before we go further */
2305                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2306                         const struct rte_eth_dcb_rx_conf *conf;
2307
2308                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2309                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2310                                                  IXGBE_DCB_NB_QUEUES);
2311                                 return -EINVAL;
2312                         }
2313                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2314                         if (!(conf->nb_tcs == ETH_4_TCS ||
2315                                conf->nb_tcs == ETH_8_TCS)) {
2316                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2317                                                 " and nb_tcs != %d.",
2318                                                 ETH_4_TCS, ETH_8_TCS);
2319                                 return -EINVAL;
2320                         }
2321                 }
2322
2323                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2324                         const struct rte_eth_dcb_tx_conf *conf;
2325
2326                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2327                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2328                                                  IXGBE_DCB_NB_QUEUES);
2329                                 return -EINVAL;
2330                         }
2331                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2332                         if (!(conf->nb_tcs == ETH_4_TCS ||
2333                                conf->nb_tcs == ETH_8_TCS)) {
2334                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2335                                                 " and nb_tcs != %d.",
2336                                                 ETH_4_TCS, ETH_8_TCS);
2337                                 return -EINVAL;
2338                         }
2339                 }
2340
2341                 /*
2342                  * When DCB/VT is off, maximum number of queues changes,
2343                  * except for 82598EB, which remains constant.
2344                  */
2345                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2346                                 hw->mac.type != ixgbe_mac_82598EB) {
2347                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2348                                 PMD_INIT_LOG(ERR,
2349                                              "Neither VT nor DCB are enabled, "
2350                                              "nb_tx_q > %d.",
2351                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2352                                 return -EINVAL;
2353                         }
2354                 }
2355         }
2356         return 0;
2357 }
2358
2359 static int
2360 ixgbe_dev_configure(struct rte_eth_dev *dev)
2361 {
2362         struct ixgbe_interrupt *intr =
2363                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2364         struct ixgbe_adapter *adapter =
2365                 (struct ixgbe_adapter *)dev->data->dev_private;
2366         int ret;
2367
2368         PMD_INIT_FUNC_TRACE();
2369         /* multipe queue mode checking */
2370         ret  = ixgbe_check_mq_mode(dev);
2371         if (ret != 0) {
2372                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2373                             ret);
2374                 return ret;
2375         }
2376
2377         /* set flag to update link status after init */
2378         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2379
2380         /*
2381          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2382          * allocation or vector Rx preconditions we will reset it.
2383          */
2384         adapter->rx_bulk_alloc_allowed = true;
2385         adapter->rx_vec_allowed = true;
2386
2387         return 0;
2388 }
2389
2390 static void
2391 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2392 {
2393         struct ixgbe_hw *hw =
2394                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395         struct ixgbe_interrupt *intr =
2396                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2397         uint32_t gpie;
2398
2399         /* only set up it on X550EM_X */
2400         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2401                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2402                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2403                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2404                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2405                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2406         }
2407 }
2408
2409 int
2410 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2411                         uint16_t tx_rate, uint64_t q_msk)
2412 {
2413         struct ixgbe_hw *hw;
2414         struct ixgbe_vf_info *vfinfo;
2415         struct rte_eth_link link;
2416         uint8_t  nb_q_per_pool;
2417         uint32_t queue_stride;
2418         uint32_t queue_idx, idx = 0, vf_idx;
2419         uint32_t queue_end;
2420         uint16_t total_rate = 0;
2421         struct rte_pci_device *pci_dev;
2422
2423         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2424         rte_eth_link_get_nowait(dev->data->port_id, &link);
2425
2426         if (vf >= pci_dev->max_vfs)
2427                 return -EINVAL;
2428
2429         if (tx_rate > link.link_speed)
2430                 return -EINVAL;
2431
2432         if (q_msk == 0)
2433                 return 0;
2434
2435         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2436         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2437         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2438         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2439         queue_idx = vf * queue_stride;
2440         queue_end = queue_idx + nb_q_per_pool - 1;
2441         if (queue_end >= hw->mac.max_tx_queues)
2442                 return -EINVAL;
2443
2444         if (vfinfo) {
2445                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2446                         if (vf_idx == vf)
2447                                 continue;
2448                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2449                                 idx++)
2450                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2451                 }
2452         } else {
2453                 return -EINVAL;
2454         }
2455
2456         /* Store tx_rate for this vf. */
2457         for (idx = 0; idx < nb_q_per_pool; idx++) {
2458                 if (((uint64_t)0x1 << idx) & q_msk) {
2459                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2460                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2461                         total_rate += tx_rate;
2462                 }
2463         }
2464
2465         if (total_rate > dev->data->dev_link.link_speed) {
2466                 /* Reset stored TX rate of the VF if it causes exceed
2467                  * link speed.
2468                  */
2469                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2470                 return -EINVAL;
2471         }
2472
2473         /* Set RTTBCNRC of each queue/pool for vf X  */
2474         for (; queue_idx <= queue_end; queue_idx++) {
2475                 if (0x1 & q_msk)
2476                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2477                 q_msk = q_msk >> 1;
2478         }
2479
2480         return 0;
2481 }
2482
2483 /*
2484  * Configure device link speed and setup link.
2485  * It returns 0 on success.
2486  */
2487 static int
2488 ixgbe_dev_start(struct rte_eth_dev *dev)
2489 {
2490         struct ixgbe_hw *hw =
2491                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492         struct ixgbe_vf_info *vfinfo =
2493                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2494         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2495         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2496         uint32_t intr_vector = 0;
2497         int err, link_up = 0, negotiate = 0;
2498         uint32_t speed = 0;
2499         int mask = 0;
2500         int status;
2501         uint16_t vf, idx;
2502         uint32_t *link_speeds;
2503         struct ixgbe_tm_conf *tm_conf =
2504                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2505
2506         PMD_INIT_FUNC_TRACE();
2507
2508         /* IXGBE devices don't support:
2509         *    - half duplex (checked afterwards for valid speeds)
2510         *    - fixed speed: TODO implement
2511         */
2512         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2513                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2514                              dev->data->port_id);
2515                 return -EINVAL;
2516         }
2517
2518         /* disable uio/vfio intr/eventfd mapping */
2519         rte_intr_disable(intr_handle);
2520
2521         /* stop adapter */
2522         hw->adapter_stopped = 0;
2523         ixgbe_stop_adapter(hw);
2524
2525         /* reinitialize adapter
2526          * this calls reset and start
2527          */
2528         status = ixgbe_pf_reset_hw(hw);
2529         if (status != 0)
2530                 return -1;
2531         hw->mac.ops.start_hw(hw);
2532         hw->mac.get_link_status = true;
2533
2534         /* configure PF module if SRIOV enabled */
2535         ixgbe_pf_host_configure(dev);
2536
2537         ixgbe_dev_phy_intr_setup(dev);
2538
2539         /* check and configure queue intr-vector mapping */
2540         if ((rte_intr_cap_multiple(intr_handle) ||
2541              !RTE_ETH_DEV_SRIOV(dev).active) &&
2542             dev->data->dev_conf.intr_conf.rxq != 0) {
2543                 intr_vector = dev->data->nb_rx_queues;
2544                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2545                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2546                                         IXGBE_MAX_INTR_QUEUE_NUM);
2547                         return -ENOTSUP;
2548                 }
2549                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2550                         return -1;
2551         }
2552
2553         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2554                 intr_handle->intr_vec =
2555                         rte_zmalloc("intr_vec",
2556                                     dev->data->nb_rx_queues * sizeof(int), 0);
2557                 if (intr_handle->intr_vec == NULL) {
2558                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2559                                      " intr_vec", dev->data->nb_rx_queues);
2560                         return -ENOMEM;
2561                 }
2562         }
2563
2564         /* confiugre msix for sleep until rx interrupt */
2565         ixgbe_configure_msix(dev);
2566
2567         /* initialize transmission unit */
2568         ixgbe_dev_tx_init(dev);
2569
2570         /* This can fail when allocating mbufs for descriptor rings */
2571         err = ixgbe_dev_rx_init(dev);
2572         if (err) {
2573                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2574                 goto error;
2575         }
2576
2577     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2578                 ETH_VLAN_EXTEND_MASK;
2579         ixgbe_vlan_offload_set(dev, mask);
2580
2581         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2582                 /* Enable vlan filtering for VMDq */
2583                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2584         }
2585
2586         /* Configure DCB hw */
2587         ixgbe_configure_dcb(dev);
2588
2589         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2590                 err = ixgbe_fdir_configure(dev);
2591                 if (err)
2592                         goto error;
2593         }
2594
2595         /* Restore vf rate limit */
2596         if (vfinfo != NULL) {
2597                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2598                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2599                                 if (vfinfo[vf].tx_rate[idx] != 0)
2600                                         ixgbe_set_vf_rate_limit(
2601                                                 dev, vf,
2602                                                 vfinfo[vf].tx_rate[idx],
2603                                                 1 << idx);
2604         }
2605
2606         ixgbe_restore_statistics_mapping(dev);
2607
2608         err = ixgbe_dev_rxtx_start(dev);
2609         if (err < 0) {
2610                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2611                 goto error;
2612         }
2613
2614         /* Skip link setup if loopback mode is enabled for 82599. */
2615         if (hw->mac.type == ixgbe_mac_82599EB &&
2616                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2617                 goto skip_link_setup;
2618
2619         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2620                 err = hw->mac.ops.setup_sfp(hw);
2621                 if (err)
2622                         goto error;
2623         }
2624
2625         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2626                 /* Turn on the copper */
2627                 ixgbe_set_phy_power(hw, true);
2628         } else {
2629                 /* Turn on the laser */
2630                 ixgbe_enable_tx_laser(hw);
2631         }
2632
2633         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2634         if (err)
2635                 goto error;
2636         dev->data->dev_link.link_status = link_up;
2637
2638         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2639         if (err)
2640                 goto error;
2641
2642         link_speeds = &dev->data->dev_conf.link_speeds;
2643         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2644                         ETH_LINK_SPEED_10G)) {
2645                 PMD_INIT_LOG(ERR, "Invalid link setting");
2646                 goto error;
2647         }
2648
2649         speed = 0x0;
2650         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2651                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2652                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2653                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2654         } else {
2655                 if (*link_speeds & ETH_LINK_SPEED_10G)
2656                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2657                 if (*link_speeds & ETH_LINK_SPEED_1G)
2658                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2659                 if (*link_speeds & ETH_LINK_SPEED_100M)
2660                         speed |= IXGBE_LINK_SPEED_100_FULL;
2661         }
2662
2663         err = ixgbe_setup_link(hw, speed, link_up);
2664         if (err)
2665                 goto error;
2666
2667 skip_link_setup:
2668
2669         if (rte_intr_allow_others(intr_handle)) {
2670                 /* check if lsc interrupt is enabled */
2671                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2672                         ixgbe_dev_lsc_interrupt_setup(dev);
2673                 ixgbe_dev_macsec_interrupt_setup(dev);
2674         } else {
2675                 rte_intr_callback_unregister(intr_handle,
2676                                              ixgbe_dev_interrupt_handler, dev);
2677                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2678                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2679                                      " no intr multiplex");
2680         }
2681
2682         /* check if rxq interrupt is enabled */
2683         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2684             rte_intr_dp_is_en(intr_handle))
2685                 ixgbe_dev_rxq_interrupt_setup(dev);
2686
2687         /* enable uio/vfio intr/eventfd mapping */
2688         rte_intr_enable(intr_handle);
2689
2690         /* resume enabled intr since hw reset */
2691         ixgbe_enable_intr(dev);
2692         ixgbe_l2_tunnel_conf(dev);
2693         ixgbe_filter_restore(dev);
2694
2695         if (!tm_conf->committed)
2696                 PMD_DRV_LOG(WARNING,
2697                             "please call hierarchy_commit() "
2698                             "before starting the port");
2699
2700         return 0;
2701
2702 error:
2703         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2704         ixgbe_dev_clear_queues(dev);
2705         return -EIO;
2706 }
2707
2708 /*
2709  * Stop device: disable rx and tx functions to allow for reconfiguring.
2710  */
2711 static void
2712 ixgbe_dev_stop(struct rte_eth_dev *dev)
2713 {
2714         struct rte_eth_link link;
2715         struct ixgbe_hw *hw =
2716                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2717         struct ixgbe_vf_info *vfinfo =
2718                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2719         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2720         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2721         int vf;
2722         struct ixgbe_tm_conf *tm_conf =
2723                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2724
2725         PMD_INIT_FUNC_TRACE();
2726
2727         /* disable interrupts */
2728         ixgbe_disable_intr(hw);
2729
2730         /* reset the NIC */
2731         ixgbe_pf_reset_hw(hw);
2732         hw->adapter_stopped = 0;
2733
2734         /* stop adapter */
2735         ixgbe_stop_adapter(hw);
2736
2737         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2738                 vfinfo[vf].clear_to_send = false;
2739
2740         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2741                 /* Turn off the copper */
2742                 ixgbe_set_phy_power(hw, false);
2743         } else {
2744                 /* Turn off the laser */
2745                 ixgbe_disable_tx_laser(hw);
2746         }
2747
2748         ixgbe_dev_clear_queues(dev);
2749
2750         /* Clear stored conf */
2751         dev->data->scattered_rx = 0;
2752         dev->data->lro = 0;
2753
2754         /* Clear recorded link status */
2755         memset(&link, 0, sizeof(link));
2756         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2757
2758         if (!rte_intr_allow_others(intr_handle))
2759                 /* resume to the default handler */
2760                 rte_intr_callback_register(intr_handle,
2761                                            ixgbe_dev_interrupt_handler,
2762                                            (void *)dev);
2763
2764         /* Clean datapath event and queue/vec mapping */
2765         rte_intr_efd_disable(intr_handle);
2766         if (intr_handle->intr_vec != NULL) {
2767                 rte_free(intr_handle->intr_vec);
2768                 intr_handle->intr_vec = NULL;
2769         }
2770
2771         /* reset hierarchy commit */
2772         tm_conf->committed = false;
2773 }
2774
2775 /*
2776  * Set device link up: enable tx.
2777  */
2778 static int
2779 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2780 {
2781         struct ixgbe_hw *hw =
2782                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2783         if (hw->mac.type == ixgbe_mac_82599EB) {
2784 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2785                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2786                         /* Not suported in bypass mode */
2787                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2788                                      "by device id 0x%x", hw->device_id);
2789                         return -ENOTSUP;
2790                 }
2791 #endif
2792         }
2793
2794         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2795                 /* Turn on the copper */
2796                 ixgbe_set_phy_power(hw, true);
2797         } else {
2798                 /* Turn on the laser */
2799                 ixgbe_enable_tx_laser(hw);
2800         }
2801
2802         return 0;
2803 }
2804
2805 /*
2806  * Set device link down: disable tx.
2807  */
2808 static int
2809 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2810 {
2811         struct ixgbe_hw *hw =
2812                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813         if (hw->mac.type == ixgbe_mac_82599EB) {
2814 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2815                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2816                         /* Not suported in bypass mode */
2817                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2818                                      "by device id 0x%x", hw->device_id);
2819                         return -ENOTSUP;
2820                 }
2821 #endif
2822         }
2823
2824         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2825                 /* Turn off the copper */
2826                 ixgbe_set_phy_power(hw, false);
2827         } else {
2828                 /* Turn off the laser */
2829                 ixgbe_disable_tx_laser(hw);
2830         }
2831
2832         return 0;
2833 }
2834
2835 /*
2836  * Reest and stop device.
2837  */
2838 static void
2839 ixgbe_dev_close(struct rte_eth_dev *dev)
2840 {
2841         struct ixgbe_hw *hw =
2842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843
2844         PMD_INIT_FUNC_TRACE();
2845
2846         ixgbe_pf_reset_hw(hw);
2847
2848         ixgbe_dev_stop(dev);
2849         hw->adapter_stopped = 1;
2850
2851         ixgbe_dev_free_queues(dev);
2852
2853         ixgbe_disable_pcie_master(hw);
2854
2855         /* reprogram the RAR[0] in case user changed it. */
2856         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2857 }
2858
2859 static void
2860 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2861                            struct ixgbe_hw_stats *hw_stats,
2862                            struct ixgbe_macsec_stats *macsec_stats,
2863                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2864                            uint64_t *total_qprc, uint64_t *total_qprdc)
2865 {
2866         uint32_t bprc, lxon, lxoff, total;
2867         uint32_t delta_gprc = 0;
2868         unsigned i;
2869         /* Workaround for RX byte count not including CRC bytes when CRC
2870          * strip is enabled. CRC bytes are removed from counters when crc_strip
2871          * is disabled.
2872          */
2873         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2874                         IXGBE_HLREG0_RXCRCSTRP);
2875
2876         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2877         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2878         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2879         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2880
2881         for (i = 0; i < 8; i++) {
2882                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2883
2884                 /* global total per queue */
2885                 hw_stats->mpc[i] += mp;
2886                 /* Running comprehensive total for stats display */
2887                 *total_missed_rx += hw_stats->mpc[i];
2888                 if (hw->mac.type == ixgbe_mac_82598EB) {
2889                         hw_stats->rnbc[i] +=
2890                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2891                         hw_stats->pxonrxc[i] +=
2892                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2893                         hw_stats->pxoffrxc[i] +=
2894                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2895                 } else {
2896                         hw_stats->pxonrxc[i] +=
2897                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2898                         hw_stats->pxoffrxc[i] +=
2899                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2900                         hw_stats->pxon2offc[i] +=
2901                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2902                 }
2903                 hw_stats->pxontxc[i] +=
2904                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2905                 hw_stats->pxofftxc[i] +=
2906                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2907         }
2908         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2909                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2910                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2911                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2912
2913                 delta_gprc += delta_qprc;
2914
2915                 hw_stats->qprc[i] += delta_qprc;
2916                 hw_stats->qptc[i] += delta_qptc;
2917
2918                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2919                 hw_stats->qbrc[i] +=
2920                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2921                 if (crc_strip == 0)
2922                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2923
2924                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2925                 hw_stats->qbtc[i] +=
2926                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2927
2928                 hw_stats->qprdc[i] += delta_qprdc;
2929                 *total_qprdc += hw_stats->qprdc[i];
2930
2931                 *total_qprc += hw_stats->qprc[i];
2932                 *total_qbrc += hw_stats->qbrc[i];
2933         }
2934         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2935         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2936         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2937
2938         /*
2939          * An errata states that gprc actually counts good + missed packets:
2940          * Workaround to set gprc to summated queue packet receives
2941          */
2942         hw_stats->gprc = *total_qprc;
2943
2944         if (hw->mac.type != ixgbe_mac_82598EB) {
2945                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2946                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2947                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2948                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2949                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2950                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2951                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2952                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2953         } else {
2954                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2955                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2956                 /* 82598 only has a counter in the high register */
2957                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2958                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2959                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2960         }
2961         uint64_t old_tpr = hw_stats->tpr;
2962
2963         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2964         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2965
2966         if (crc_strip == 0)
2967                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2968
2969         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2970         hw_stats->gptc += delta_gptc;
2971         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2972         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2973
2974         /*
2975          * Workaround: mprc hardware is incorrectly counting
2976          * broadcasts, so for now we subtract those.
2977          */
2978         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2979         hw_stats->bprc += bprc;
2980         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2981         if (hw->mac.type == ixgbe_mac_82598EB)
2982                 hw_stats->mprc -= bprc;
2983
2984         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2985         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2986         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2987         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2988         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2989         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2990
2991         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2992         hw_stats->lxontxc += lxon;
2993         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2994         hw_stats->lxofftxc += lxoff;
2995         total = lxon + lxoff;
2996
2997         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2998         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2999         hw_stats->gptc -= total;
3000         hw_stats->mptc -= total;
3001         hw_stats->ptc64 -= total;
3002         hw_stats->gotc -= total * ETHER_MIN_LEN;
3003
3004         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3005         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3006         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3007         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3008         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3009         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3010         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3011         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3012         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3013         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3014         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3015         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3016         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3017         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3018         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3019         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3020         /* Only read FCOE on 82599 */
3021         if (hw->mac.type != ixgbe_mac_82598EB) {
3022                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3023                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3024                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3025                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3026                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3027         }
3028
3029         /* Flow Director Stats registers */
3030         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3031         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3032
3033         /* MACsec Stats registers */
3034         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3035         macsec_stats->out_pkts_encrypted +=
3036                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3037         macsec_stats->out_pkts_protected +=
3038                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3039         macsec_stats->out_octets_encrypted +=
3040                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3041         macsec_stats->out_octets_protected +=
3042                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3043         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3044         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3045         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3046         macsec_stats->in_pkts_unknownsci +=
3047                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3048         macsec_stats->in_octets_decrypted +=
3049                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3050         macsec_stats->in_octets_validated +=
3051                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3052         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3053         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3054         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3055         for (i = 0; i < 2; i++) {
3056                 macsec_stats->in_pkts_ok +=
3057                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3058                 macsec_stats->in_pkts_invalid +=
3059                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3060                 macsec_stats->in_pkts_notvalid +=
3061                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3062         }
3063         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3064         macsec_stats->in_pkts_notusingsa +=
3065                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3066 }
3067
3068 /*
3069  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3070  */
3071 static void
3072 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3073 {
3074         struct ixgbe_hw *hw =
3075                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076         struct ixgbe_hw_stats *hw_stats =
3077                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3078         struct ixgbe_macsec_stats *macsec_stats =
3079                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3080                                 dev->data->dev_private);
3081         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3082         unsigned i;
3083
3084         total_missed_rx = 0;
3085         total_qbrc = 0;
3086         total_qprc = 0;
3087         total_qprdc = 0;
3088
3089         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3090                         &total_qbrc, &total_qprc, &total_qprdc);
3091
3092         if (stats == NULL)
3093                 return;
3094
3095         /* Fill out the rte_eth_stats statistics structure */
3096         stats->ipackets = total_qprc;
3097         stats->ibytes = total_qbrc;
3098         stats->opackets = hw_stats->gptc;
3099         stats->obytes = hw_stats->gotc;
3100
3101         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3102                 stats->q_ipackets[i] = hw_stats->qprc[i];
3103                 stats->q_opackets[i] = hw_stats->qptc[i];
3104                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3105                 stats->q_obytes[i] = hw_stats->qbtc[i];
3106                 stats->q_errors[i] = hw_stats->qprdc[i];
3107         }
3108
3109         /* Rx Errors */
3110         stats->imissed  = total_missed_rx;
3111         stats->ierrors  = hw_stats->crcerrs +
3112                           hw_stats->mspdc +
3113                           hw_stats->rlec +
3114                           hw_stats->ruc +
3115                           hw_stats->roc +
3116                           hw_stats->illerrc +
3117                           hw_stats->errbc +
3118                           hw_stats->rfc +
3119                           hw_stats->fccrc +
3120                           hw_stats->fclast;
3121
3122         /* Tx Errors */
3123         stats->oerrors  = 0;
3124 }
3125
3126 static void
3127 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3128 {
3129         struct ixgbe_hw_stats *stats =
3130                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3131
3132         /* HW registers are cleared on read */
3133         ixgbe_dev_stats_get(dev, NULL);
3134
3135         /* Reset software totals */
3136         memset(stats, 0, sizeof(*stats));
3137 }
3138
3139 /* This function calculates the number of xstats based on the current config */
3140 static unsigned
3141 ixgbe_xstats_calc_num(void) {
3142         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3143                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3144                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3145 }
3146
3147 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3148         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3149 {
3150         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3151         unsigned stat, i, count;
3152
3153         if (xstats_names != NULL) {
3154                 count = 0;
3155
3156                 /* Note: limit >= cnt_stats checked upstream
3157                  * in rte_eth_xstats_names()
3158                  */
3159
3160                 /* Extended stats from ixgbe_hw_stats */
3161                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3162                         snprintf(xstats_names[count].name,
3163                                 sizeof(xstats_names[count].name),
3164                                 "%s",
3165                                 rte_ixgbe_stats_strings[i].name);
3166                         count++;
3167                 }
3168
3169                 /* MACsec Stats */
3170                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3171                         snprintf(xstats_names[count].name,
3172                                 sizeof(xstats_names[count].name),
3173                                 "%s",
3174                                 rte_ixgbe_macsec_strings[i].name);
3175                         count++;
3176                 }
3177
3178                 /* RX Priority Stats */
3179                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3180                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3181                                 snprintf(xstats_names[count].name,
3182                                         sizeof(xstats_names[count].name),
3183                                         "rx_priority%u_%s", i,
3184                                         rte_ixgbe_rxq_strings[stat].name);
3185                                 count++;
3186                         }
3187                 }
3188
3189                 /* TX Priority Stats */
3190                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3191                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3192                                 snprintf(xstats_names[count].name,
3193                                         sizeof(xstats_names[count].name),
3194                                         "tx_priority%u_%s", i,
3195                                         rte_ixgbe_txq_strings[stat].name);
3196                                 count++;
3197                         }
3198                 }
3199         }
3200         return cnt_stats;
3201 }
3202
3203 static int ixgbe_dev_xstats_get_names_by_id(
3204         struct rte_eth_dev *dev,
3205         struct rte_eth_xstat_name *xstats_names,
3206         const uint64_t *ids,
3207         unsigned int limit)
3208 {
3209         if (!ids) {
3210                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3211                 unsigned int stat, i, count;
3212
3213                 if (xstats_names != NULL) {
3214                         count = 0;
3215
3216                         /* Note: limit >= cnt_stats checked upstream
3217                          * in rte_eth_xstats_names()
3218                          */
3219
3220                         /* Extended stats from ixgbe_hw_stats */
3221                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3222                                 snprintf(xstats_names[count].name,
3223                                         sizeof(xstats_names[count].name),
3224                                         "%s",
3225                                         rte_ixgbe_stats_strings[i].name);
3226                                 count++;
3227                         }
3228
3229                         /* MACsec Stats */
3230                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3231                                 snprintf(xstats_names[count].name,
3232                                         sizeof(xstats_names[count].name),
3233                                         "%s",
3234                                         rte_ixgbe_macsec_strings[i].name);
3235                                 count++;
3236                         }
3237
3238                         /* RX Priority Stats */
3239                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3240                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3241                                         snprintf(xstats_names[count].name,
3242                                             sizeof(xstats_names[count].name),
3243                                             "rx_priority%u_%s", i,
3244                                             rte_ixgbe_rxq_strings[stat].name);
3245                                         count++;
3246                                 }
3247                         }
3248
3249                         /* TX Priority Stats */
3250                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3251                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3252                                         snprintf(xstats_names[count].name,
3253                                             sizeof(xstats_names[count].name),
3254                                             "tx_priority%u_%s", i,
3255                                             rte_ixgbe_txq_strings[stat].name);
3256                                         count++;
3257                                 }
3258                         }
3259                 }
3260                 return cnt_stats;
3261         }
3262
3263         uint16_t i;
3264         uint16_t size = ixgbe_xstats_calc_num();
3265         struct rte_eth_xstat_name xstats_names_copy[size];
3266
3267         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3268                         size);
3269
3270         for (i = 0; i < limit; i++) {
3271                 if (ids[i] >= size) {
3272                         PMD_INIT_LOG(ERR, "id value isn't valid");
3273                         return -1;
3274                 }
3275                 strcpy(xstats_names[i].name,
3276                                 xstats_names_copy[ids[i]].name);
3277         }
3278         return limit;
3279 }
3280
3281 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3282         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3283 {
3284         unsigned i;
3285
3286         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3287                 return -ENOMEM;
3288
3289         if (xstats_names != NULL)
3290                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3291                         snprintf(xstats_names[i].name,
3292                                 sizeof(xstats_names[i].name),
3293                                 "%s", rte_ixgbevf_stats_strings[i].name);
3294         return IXGBEVF_NB_XSTATS;
3295 }
3296
3297 static int
3298 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3299                                          unsigned n)
3300 {
3301         struct ixgbe_hw *hw =
3302                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3303         struct ixgbe_hw_stats *hw_stats =
3304                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3305         struct ixgbe_macsec_stats *macsec_stats =
3306                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3307                                 dev->data->dev_private);
3308         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3309         unsigned i, stat, count = 0;
3310
3311         count = ixgbe_xstats_calc_num();
3312
3313         if (n < count)
3314                 return count;
3315
3316         total_missed_rx = 0;
3317         total_qbrc = 0;
3318         total_qprc = 0;
3319         total_qprdc = 0;
3320
3321         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3322                         &total_qbrc, &total_qprc, &total_qprdc);
3323
3324         /* If this is a reset xstats is NULL, and we have cleared the
3325          * registers by reading them.
3326          */
3327         if (!xstats)
3328                 return 0;
3329
3330         /* Extended stats from ixgbe_hw_stats */
3331         count = 0;
3332         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3333                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3334                                 rte_ixgbe_stats_strings[i].offset);
3335                 xstats[count].id = count;
3336                 count++;
3337         }
3338
3339         /* MACsec Stats */
3340         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3341                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3342                                 rte_ixgbe_macsec_strings[i].offset);
3343                 xstats[count].id = count;
3344                 count++;
3345         }
3346
3347         /* RX Priority Stats */
3348         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3349                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3350                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3351                                         rte_ixgbe_rxq_strings[stat].offset +
3352                                         (sizeof(uint64_t) * i));
3353                         xstats[count].id = count;
3354                         count++;
3355                 }
3356         }
3357
3358         /* TX Priority Stats */
3359         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3360                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3361                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3362                                         rte_ixgbe_txq_strings[stat].offset +
3363                                         (sizeof(uint64_t) * i));
3364                         xstats[count].id = count;
3365                         count++;
3366                 }
3367         }
3368         return count;
3369 }
3370
3371 static int
3372 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3373                 uint64_t *values, unsigned int n)
3374 {
3375         if (!ids) {
3376                 struct ixgbe_hw *hw =
3377                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378                 struct ixgbe_hw_stats *hw_stats =
3379                                 IXGBE_DEV_PRIVATE_TO_STATS(
3380                                                 dev->data->dev_private);
3381                 struct ixgbe_macsec_stats *macsec_stats =
3382                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3383                                         dev->data->dev_private);
3384                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3385                 unsigned int i, stat, count = 0;
3386
3387                 count = ixgbe_xstats_calc_num();
3388
3389                 if (!ids && n < count)
3390                         return count;
3391
3392                 total_missed_rx = 0;
3393                 total_qbrc = 0;
3394                 total_qprc = 0;
3395                 total_qprdc = 0;
3396
3397                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3398                                 &total_missed_rx, &total_qbrc, &total_qprc,
3399                                 &total_qprdc);
3400
3401                 /* If this is a reset xstats is NULL, and we have cleared the
3402                  * registers by reading them.
3403                  */
3404                 if (!ids && !values)
3405                         return 0;
3406
3407                 /* Extended stats from ixgbe_hw_stats */
3408                 count = 0;
3409                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3410                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3411                                         rte_ixgbe_stats_strings[i].offset);
3412                         count++;
3413                 }
3414
3415                 /* MACsec Stats */
3416                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3417                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3418                                         rte_ixgbe_macsec_strings[i].offset);
3419                         count++;
3420                 }
3421
3422                 /* RX Priority Stats */
3423                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3424                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3425                                 values[count] =
3426                                         *(uint64_t *)(((char *)hw_stats) +
3427                                         rte_ixgbe_rxq_strings[stat].offset +
3428                                         (sizeof(uint64_t) * i));
3429                                 count++;
3430                         }
3431                 }
3432
3433                 /* TX Priority Stats */
3434                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3435                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3436                                 values[count] =
3437                                         *(uint64_t *)(((char *)hw_stats) +
3438                                         rte_ixgbe_txq_strings[stat].offset +
3439                                         (sizeof(uint64_t) * i));
3440                                 count++;
3441                         }
3442                 }
3443                 return count;
3444         }
3445
3446         uint16_t i;
3447         uint16_t size = ixgbe_xstats_calc_num();
3448         uint64_t values_copy[size];
3449
3450         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3451
3452         for (i = 0; i < n; i++) {
3453                 if (ids[i] >= size) {
3454                         PMD_INIT_LOG(ERR, "id value isn't valid");
3455                         return -1;
3456                 }
3457                 values[i] = values_copy[ids[i]];
3458         }
3459         return n;
3460 }
3461
3462 static void
3463 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3464 {
3465         struct ixgbe_hw_stats *stats =
3466                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3467         struct ixgbe_macsec_stats *macsec_stats =
3468                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3469                                 dev->data->dev_private);
3470
3471         unsigned count = ixgbe_xstats_calc_num();
3472
3473         /* HW registers are cleared on read */
3474         ixgbe_dev_xstats_get(dev, NULL, count);
3475
3476         /* Reset software totals */
3477         memset(stats, 0, sizeof(*stats));
3478         memset(macsec_stats, 0, sizeof(*macsec_stats));
3479 }
3480
3481 static void
3482 ixgbevf_update_stats(struct rte_eth_dev *dev)
3483 {
3484         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3485         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3486                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3487
3488         /* Good Rx packet, include VF loopback */
3489         UPDATE_VF_STAT(IXGBE_VFGPRC,
3490             hw_stats->last_vfgprc, hw_stats->vfgprc);
3491
3492         /* Good Rx octets, include VF loopback */
3493         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3494             hw_stats->last_vfgorc, hw_stats->vfgorc);
3495
3496         /* Good Tx packet, include VF loopback */
3497         UPDATE_VF_STAT(IXGBE_VFGPTC,
3498             hw_stats->last_vfgptc, hw_stats->vfgptc);
3499
3500         /* Good Tx octets, include VF loopback */
3501         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3502             hw_stats->last_vfgotc, hw_stats->vfgotc);
3503
3504         /* Rx Multicst Packet */
3505         UPDATE_VF_STAT(IXGBE_VFMPRC,
3506             hw_stats->last_vfmprc, hw_stats->vfmprc);
3507 }
3508
3509 static int
3510 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3511                        unsigned n)
3512 {
3513         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3514                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3515         unsigned i;
3516
3517         if (n < IXGBEVF_NB_XSTATS)
3518                 return IXGBEVF_NB_XSTATS;
3519
3520         ixgbevf_update_stats(dev);
3521
3522         if (!xstats)
3523                 return 0;
3524
3525         /* Extended stats */
3526         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3527                 xstats[i].id = i;
3528                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3529                         rte_ixgbevf_stats_strings[i].offset);
3530         }
3531
3532         return IXGBEVF_NB_XSTATS;
3533 }
3534
3535 static void
3536 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3537 {
3538         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3539                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3540
3541         ixgbevf_update_stats(dev);
3542
3543         if (stats == NULL)
3544                 return;
3545
3546         stats->ipackets = hw_stats->vfgprc;
3547         stats->ibytes = hw_stats->vfgorc;
3548         stats->opackets = hw_stats->vfgptc;
3549         stats->obytes = hw_stats->vfgotc;
3550 }
3551
3552 static void
3553 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3554 {
3555         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3556                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3557
3558         /* Sync HW register to the last stats */
3559         ixgbevf_dev_stats_get(dev, NULL);
3560
3561         /* reset HW current stats*/
3562         hw_stats->vfgprc = 0;
3563         hw_stats->vfgorc = 0;
3564         hw_stats->vfgptc = 0;
3565         hw_stats->vfgotc = 0;
3566 }
3567
3568 static int
3569 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3570 {
3571         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572         u16 eeprom_verh, eeprom_verl;
3573         u32 etrack_id;
3574         int ret;
3575
3576         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3577         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3578
3579         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3580         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3581
3582         ret += 1; /* add the size of '\0' */
3583         if (fw_size < (u32)ret)
3584                 return ret;
3585         else
3586                 return 0;
3587 }
3588
3589 static void
3590 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3591 {
3592         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3593         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3594         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3595
3596         dev_info->pci_dev = pci_dev;
3597         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3598         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3599         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3600                 /*
3601                  * When DCB/VT is off, maximum number of queues changes,
3602                  * except for 82598EB, which remains constant.
3603                  */
3604                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3605                                 hw->mac.type != ixgbe_mac_82598EB)
3606                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3607         }
3608         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3609         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3610         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3611         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3612         dev_info->max_vfs = pci_dev->max_vfs;
3613         if (hw->mac.type == ixgbe_mac_82598EB)
3614                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3615         else
3616                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3617         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3618         dev_info->rx_offload_capa =
3619                 DEV_RX_OFFLOAD_VLAN_STRIP |
3620                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3621                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3622                 DEV_RX_OFFLOAD_TCP_CKSUM;
3623
3624         /*
3625          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3626          * mode.
3627          */
3628         if ((hw->mac.type == ixgbe_mac_82599EB ||
3629              hw->mac.type == ixgbe_mac_X540) &&
3630             !RTE_ETH_DEV_SRIOV(dev).active)
3631                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3632
3633         if (hw->mac.type == ixgbe_mac_82599EB ||
3634             hw->mac.type == ixgbe_mac_X540)
3635                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3636
3637         if (hw->mac.type == ixgbe_mac_X550 ||
3638             hw->mac.type == ixgbe_mac_X550EM_x ||
3639             hw->mac.type == ixgbe_mac_X550EM_a)
3640                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3641
3642         dev_info->tx_offload_capa =
3643                 DEV_TX_OFFLOAD_VLAN_INSERT |
3644                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3645                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3646                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3647                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3648                 DEV_TX_OFFLOAD_TCP_TSO;
3649
3650         if (hw->mac.type == ixgbe_mac_82599EB ||
3651             hw->mac.type == ixgbe_mac_X540)
3652                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3653
3654         if (hw->mac.type == ixgbe_mac_X550 ||
3655             hw->mac.type == ixgbe_mac_X550EM_x ||
3656             hw->mac.type == ixgbe_mac_X550EM_a)
3657                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3658
3659         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3660                 .rx_thresh = {
3661                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3662                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3663                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3664                 },
3665                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3666                 .rx_drop_en = 0,
3667         };
3668
3669         dev_info->default_txconf = (struct rte_eth_txconf) {
3670                 .tx_thresh = {
3671                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3672                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3673                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3674                 },
3675                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3676                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3677                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3678                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3679         };
3680
3681         dev_info->rx_desc_lim = rx_desc_lim;
3682         dev_info->tx_desc_lim = tx_desc_lim;
3683
3684         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3685         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3686         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3687
3688         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3689         if (hw->mac.type == ixgbe_mac_X540 ||
3690             hw->mac.type == ixgbe_mac_X540_vf ||
3691             hw->mac.type == ixgbe_mac_X550 ||
3692             hw->mac.type == ixgbe_mac_X550_vf) {
3693                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3694         }
3695 }
3696
3697 static const uint32_t *
3698 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3699 {
3700         static const uint32_t ptypes[] = {
3701                 /* For non-vec functions,
3702                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3703                  * for vec functions,
3704                  * refers to _recv_raw_pkts_vec().
3705                  */
3706                 RTE_PTYPE_L2_ETHER,
3707                 RTE_PTYPE_L3_IPV4,
3708                 RTE_PTYPE_L3_IPV4_EXT,
3709                 RTE_PTYPE_L3_IPV6,
3710                 RTE_PTYPE_L3_IPV6_EXT,
3711                 RTE_PTYPE_L4_SCTP,
3712                 RTE_PTYPE_L4_TCP,
3713                 RTE_PTYPE_L4_UDP,
3714                 RTE_PTYPE_TUNNEL_IP,
3715                 RTE_PTYPE_INNER_L3_IPV6,
3716                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3717                 RTE_PTYPE_INNER_L4_TCP,
3718                 RTE_PTYPE_INNER_L4_UDP,
3719                 RTE_PTYPE_UNKNOWN
3720         };
3721
3722         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3723             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3724             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3725             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3726                 return ptypes;
3727
3728 #if defined(RTE_ARCH_X86)
3729         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3730             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3731                 return ptypes;
3732 #endif
3733         return NULL;
3734 }
3735
3736 static void
3737 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3738                      struct rte_eth_dev_info *dev_info)
3739 {
3740         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3742
3743         dev_info->pci_dev = pci_dev;
3744         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3745         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3746         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3747         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3748         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3749         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3750         dev_info->max_vfs = pci_dev->max_vfs;
3751         if (hw->mac.type == ixgbe_mac_82598EB)
3752                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3753         else
3754                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3755         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3756                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3757                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3758                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3759         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3760                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3761                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3762                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3763                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3764                                 DEV_TX_OFFLOAD_TCP_TSO;
3765
3766         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3767                 .rx_thresh = {
3768                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3769                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3770                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3771                 },
3772                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3773                 .rx_drop_en = 0,
3774         };
3775
3776         dev_info->default_txconf = (struct rte_eth_txconf) {
3777                 .tx_thresh = {
3778                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3779                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3780                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3781                 },
3782                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3783                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3784                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3785                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3786         };
3787
3788         dev_info->rx_desc_lim = rx_desc_lim;
3789         dev_info->tx_desc_lim = tx_desc_lim;
3790 }
3791
3792 static int
3793 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3794                    int *link_up, int wait_to_complete)
3795 {
3796         /**
3797          * for a quick link status checking, wait_to_compelet == 0,
3798          * skip PF link status checking
3799          */
3800         bool no_pflink_check = wait_to_complete == 0;
3801         struct ixgbe_mbx_info *mbx = &hw->mbx;
3802         struct ixgbe_mac_info *mac = &hw->mac;
3803         uint32_t links_reg, in_msg;
3804         int ret_val = 0;
3805
3806         /* If we were hit with a reset drop the link */
3807         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3808                 mac->get_link_status = true;
3809
3810         if (!mac->get_link_status)
3811                 goto out;
3812
3813         /* if link status is down no point in checking to see if pf is up */
3814         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3815         if (!(links_reg & IXGBE_LINKS_UP))
3816                 goto out;
3817
3818         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3819          * before the link status is correct
3820          */
3821         if (mac->type == ixgbe_mac_82599_vf) {
3822                 int i;
3823
3824                 for (i = 0; i < 5; i++) {
3825                         rte_delay_us(100);
3826                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3827
3828                         if (!(links_reg & IXGBE_LINKS_UP))
3829                                 goto out;
3830                 }
3831         }
3832
3833         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3834         case IXGBE_LINKS_SPEED_10G_82599:
3835                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3836                 if (hw->mac.type >= ixgbe_mac_X550) {
3837                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3838                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3839                 }
3840                 break;
3841         case IXGBE_LINKS_SPEED_1G_82599:
3842                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3843                 break;
3844         case IXGBE_LINKS_SPEED_100_82599:
3845                 *speed = IXGBE_LINK_SPEED_100_FULL;
3846                 if (hw->mac.type == ixgbe_mac_X550) {
3847                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3848                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3849                 }
3850                 break;
3851         case IXGBE_LINKS_SPEED_10_X550EM_A:
3852                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3853                 /* Since Reserved in older MAC's */
3854                 if (hw->mac.type >= ixgbe_mac_X550)
3855                         *speed = IXGBE_LINK_SPEED_10_FULL;
3856                 break;
3857         default:
3858                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3859         }
3860
3861         if (no_pflink_check) {
3862                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3863                         mac->get_link_status = true;
3864                 else
3865                         mac->get_link_status = false;
3866
3867                 goto out;
3868         }
3869         /* if the read failed it could just be a mailbox collision, best wait
3870          * until we are called again and don't report an error
3871          */
3872         if (mbx->ops.read(hw, &in_msg, 1, 0))
3873                 goto out;
3874
3875         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3876                 /* msg is not CTS and is NACK we must have lost CTS status */
3877                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3878                         ret_val = -1;
3879                 goto out;
3880         }
3881
3882         /* the pf is talking, if we timed out in the past we reinit */
3883         if (!mbx->timeout) {
3884                 ret_val = -1;
3885                 goto out;
3886         }
3887
3888         /* if we passed all the tests above then the link is up and we no
3889          * longer need to check for link
3890          */
3891         mac->get_link_status = false;
3892
3893 out:
3894         *link_up = !mac->get_link_status;
3895         return ret_val;
3896 }
3897
3898 /* return 0 means link status changed, -1 means not changed */
3899 static int
3900 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3901                             int wait_to_complete, int vf)
3902 {
3903         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3904         struct rte_eth_link link, old;
3905         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3906         struct ixgbe_interrupt *intr =
3907                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3908         int link_up;
3909         int diag;
3910         u32 speed = 0;
3911         int wait = 1;
3912         bool autoneg = false;
3913
3914         link.link_status = ETH_LINK_DOWN;
3915         link.link_speed = 0;
3916         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3917         memset(&old, 0, sizeof(old));
3918         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3919
3920         hw->mac.get_link_status = true;
3921
3922         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3923                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3924                 speed = hw->phy.autoneg_advertised;
3925                 if (!speed)
3926                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3927                 ixgbe_setup_link(hw, speed, true);
3928         }
3929
3930         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3931         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3932                 wait = 0;
3933
3934         if (vf)
3935                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3936         else
3937                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3938
3939         if (diag != 0) {
3940                 link.link_speed = ETH_SPEED_NUM_100M;
3941                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3942                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3943                 if (link.link_status == old.link_status)
3944                         return -1;
3945                 return 0;
3946         }
3947
3948         if (link_up == 0) {
3949                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3950                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3951                 if (link.link_status == old.link_status)
3952                         return -1;
3953                 return 0;
3954         }
3955         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3956         link.link_status = ETH_LINK_UP;
3957         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3958
3959         switch (link_speed) {
3960         default:
3961         case IXGBE_LINK_SPEED_UNKNOWN:
3962                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3963                 link.link_speed = ETH_SPEED_NUM_100M;
3964                 break;
3965
3966         case IXGBE_LINK_SPEED_100_FULL:
3967                 link.link_speed = ETH_SPEED_NUM_100M;
3968                 break;
3969
3970         case IXGBE_LINK_SPEED_1GB_FULL:
3971                 link.link_speed = ETH_SPEED_NUM_1G;
3972                 break;
3973
3974         case IXGBE_LINK_SPEED_10GB_FULL:
3975                 link.link_speed = ETH_SPEED_NUM_10G;
3976                 break;
3977         }
3978         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3979
3980         if (link.link_status == old.link_status)
3981                 return -1;
3982
3983         return 0;
3984 }
3985
3986 static int
3987 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3988 {
3989         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3990 }
3991
3992 static int
3993 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3994 {
3995         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3996 }
3997
3998 static void
3999 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4000 {
4001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4002         uint32_t fctrl;
4003
4004         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4005         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4006         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4007 }
4008
4009 static void
4010 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4011 {
4012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4013         uint32_t fctrl;
4014
4015         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4016         fctrl &= (~IXGBE_FCTRL_UPE);
4017         if (dev->data->all_multicast == 1)
4018                 fctrl |= IXGBE_FCTRL_MPE;
4019         else
4020                 fctrl &= (~IXGBE_FCTRL_MPE);
4021         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4022 }
4023
4024 static void
4025 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4026 {
4027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4028         uint32_t fctrl;
4029
4030         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4031         fctrl |= IXGBE_FCTRL_MPE;
4032         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4033 }
4034
4035 static void
4036 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4037 {
4038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4039         uint32_t fctrl;
4040
4041         if (dev->data->promiscuous == 1)
4042                 return; /* must remain in all_multicast mode */
4043
4044         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4045         fctrl &= (~IXGBE_FCTRL_MPE);
4046         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4047 }
4048
4049 /**
4050  * It clears the interrupt causes and enables the interrupt.
4051  * It will be called once only during nic initialized.
4052  *
4053  * @param dev
4054  *  Pointer to struct rte_eth_dev.
4055  *
4056  * @return
4057  *  - On success, zero.
4058  *  - On failure, a negative value.
4059  */
4060 static int
4061 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
4062 {
4063         struct ixgbe_interrupt *intr =
4064                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4065
4066         ixgbe_dev_link_status_print(dev);
4067         intr->mask |= IXGBE_EICR_LSC;
4068
4069         return 0;
4070 }
4071
4072 /**
4073  * It clears the interrupt causes and enables the interrupt.
4074  * It will be called once only during nic initialized.
4075  *
4076  * @param dev
4077  *  Pointer to struct rte_eth_dev.
4078  *
4079  * @return
4080  *  - On success, zero.
4081  *  - On failure, a negative value.
4082  */
4083 static int
4084 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4085 {
4086         struct ixgbe_interrupt *intr =
4087                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4088
4089         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4090
4091         return 0;
4092 }
4093
4094 /**
4095  * It clears the interrupt causes and enables the interrupt.
4096  * It will be called once only during nic initialized.
4097  *
4098  * @param dev
4099  *  Pointer to struct rte_eth_dev.
4100  *
4101  * @return
4102  *  - On success, zero.
4103  *  - On failure, a negative value.
4104  */
4105 static int
4106 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4107 {
4108         struct ixgbe_interrupt *intr =
4109                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4110
4111         intr->mask |= IXGBE_EICR_LINKSEC;
4112
4113         return 0;
4114 }
4115
4116 /*
4117  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4118  *
4119  * @param dev
4120  *  Pointer to struct rte_eth_dev.
4121  *
4122  * @return
4123  *  - On success, zero.
4124  *  - On failure, a negative value.
4125  */
4126 static int
4127 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4128 {
4129         uint32_t eicr;
4130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4131         struct ixgbe_interrupt *intr =
4132                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4133
4134         /* clear all cause mask */
4135         ixgbe_disable_intr(hw);
4136
4137         /* read-on-clear nic registers here */
4138         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4139         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4140
4141         intr->flags = 0;
4142
4143         /* set flag for async link update */
4144         if (eicr & IXGBE_EICR_LSC)
4145                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4146
4147         if (eicr & IXGBE_EICR_MAILBOX)
4148                 intr->flags |= IXGBE_FLAG_MAILBOX;
4149
4150         if (eicr & IXGBE_EICR_LINKSEC)
4151                 intr->flags |= IXGBE_FLAG_MACSEC;
4152
4153         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4154             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4155             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4156                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4157
4158         return 0;
4159 }
4160
4161 /**
4162  * It gets and then prints the link status.
4163  *
4164  * @param dev
4165  *  Pointer to struct rte_eth_dev.
4166  *
4167  * @return
4168  *  - On success, zero.
4169  *  - On failure, a negative value.
4170  */
4171 static void
4172 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4173 {
4174         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4175         struct rte_eth_link link;
4176
4177         memset(&link, 0, sizeof(link));
4178         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4179         if (link.link_status) {
4180                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4181                                         (int)(dev->data->port_id),
4182                                         (unsigned)link.link_speed,
4183                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4184                                         "full-duplex" : "half-duplex");
4185         } else {
4186                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4187                                 (int)(dev->data->port_id));
4188         }
4189         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4190                                 pci_dev->addr.domain,
4191                                 pci_dev->addr.bus,
4192                                 pci_dev->addr.devid,
4193                                 pci_dev->addr.function);
4194 }
4195
4196 /*
4197  * It executes link_update after knowing an interrupt occurred.
4198  *
4199  * @param dev
4200  *  Pointer to struct rte_eth_dev.
4201  *
4202  * @return
4203  *  - On success, zero.
4204  *  - On failure, a negative value.
4205  */
4206 static int
4207 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4208                            struct rte_intr_handle *intr_handle)
4209 {
4210         struct ixgbe_interrupt *intr =
4211                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4212         int64_t timeout;
4213         struct rte_eth_link link;
4214         struct ixgbe_hw *hw =
4215                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4216
4217         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4218
4219         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4220                 ixgbe_pf_mbx_process(dev);
4221                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4222         }
4223
4224         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4225                 ixgbe_handle_lasi(hw);
4226                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4227         }
4228
4229         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4230                 /* get the link status before link update, for predicting later */
4231                 memset(&link, 0, sizeof(link));
4232                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4233
4234                 ixgbe_dev_link_update(dev, 0);
4235
4236                 /* likely to up */
4237                 if (!link.link_status)
4238                         /* handle it 1 sec later, wait it being stable */
4239                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4240                 /* likely to down */
4241                 else
4242                         /* handle it 4 sec later, wait it being stable */
4243                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4244
4245                 ixgbe_dev_link_status_print(dev);
4246                 if (rte_eal_alarm_set(timeout * 1000,
4247                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4248                         PMD_DRV_LOG(ERR, "Error setting alarm");
4249                 else {
4250                         /* remember original mask */
4251                         intr->mask_original = intr->mask;
4252                         /* only disable lsc interrupt */
4253                         intr->mask &= ~IXGBE_EIMS_LSC;
4254                 }
4255         }
4256
4257         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4258         ixgbe_enable_intr(dev);
4259         rte_intr_enable(intr_handle);
4260
4261         return 0;
4262 }
4263
4264 /**
4265  * Interrupt handler which shall be registered for alarm callback for delayed
4266  * handling specific interrupt to wait for the stable nic state. As the
4267  * NIC interrupt state is not stable for ixgbe after link is just down,
4268  * it needs to wait 4 seconds to get the stable status.
4269  *
4270  * @param handle
4271  *  Pointer to interrupt handle.
4272  * @param param
4273  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4274  *
4275  * @return
4276  *  void
4277  */
4278 static void
4279 ixgbe_dev_interrupt_delayed_handler(void *param)
4280 {
4281         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4282         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4283         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4284         struct ixgbe_interrupt *intr =
4285                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4286         struct ixgbe_hw *hw =
4287                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4288         uint32_t eicr;
4289
4290         ixgbe_disable_intr(hw);
4291
4292         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4293         if (eicr & IXGBE_EICR_MAILBOX)
4294                 ixgbe_pf_mbx_process(dev);
4295
4296         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4297                 ixgbe_handle_lasi(hw);
4298                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4299         }
4300
4301         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4302                 ixgbe_dev_link_update(dev, 0);
4303                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4304                 ixgbe_dev_link_status_print(dev);
4305                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4306                                               NULL, NULL);
4307         }
4308
4309         if (intr->flags & IXGBE_FLAG_MACSEC) {
4310                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4311                                               NULL, NULL);
4312                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4313         }
4314
4315         /* restore original mask */
4316         intr->mask = intr->mask_original;
4317         intr->mask_original = 0;
4318
4319         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4320         ixgbe_enable_intr(dev);
4321         rte_intr_enable(intr_handle);
4322 }
4323
4324 /**
4325  * Interrupt handler triggered by NIC  for handling
4326  * specific interrupt.
4327  *
4328  * @param handle
4329  *  Pointer to interrupt handle.
4330  * @param param
4331  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4332  *
4333  * @return
4334  *  void
4335  */
4336 static void
4337 ixgbe_dev_interrupt_handler(void *param)
4338 {
4339         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4340
4341         ixgbe_dev_interrupt_get_status(dev);
4342         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4343 }
4344
4345 static int
4346 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4347 {
4348         struct ixgbe_hw *hw;
4349
4350         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4352 }
4353
4354 static int
4355 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4356 {
4357         struct ixgbe_hw *hw;
4358
4359         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4361 }
4362
4363 static int
4364 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4365 {
4366         struct ixgbe_hw *hw;
4367         uint32_t mflcn_reg;
4368         uint32_t fccfg_reg;
4369         int rx_pause;
4370         int tx_pause;
4371
4372         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4373
4374         fc_conf->pause_time = hw->fc.pause_time;
4375         fc_conf->high_water = hw->fc.high_water[0];
4376         fc_conf->low_water = hw->fc.low_water[0];
4377         fc_conf->send_xon = hw->fc.send_xon;
4378         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4379
4380         /*
4381          * Return rx_pause status according to actual setting of
4382          * MFLCN register.
4383          */
4384         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4385         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4386                 rx_pause = 1;
4387         else
4388                 rx_pause = 0;
4389
4390         /*
4391          * Return tx_pause status according to actual setting of
4392          * FCCFG register.
4393          */
4394         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4395         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4396                 tx_pause = 1;
4397         else
4398                 tx_pause = 0;
4399
4400         if (rx_pause && tx_pause)
4401                 fc_conf->mode = RTE_FC_FULL;
4402         else if (rx_pause)
4403                 fc_conf->mode = RTE_FC_RX_PAUSE;
4404         else if (tx_pause)
4405                 fc_conf->mode = RTE_FC_TX_PAUSE;
4406         else
4407                 fc_conf->mode = RTE_FC_NONE;
4408
4409         return 0;
4410 }
4411
4412 static int
4413 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4414 {
4415         struct ixgbe_hw *hw;
4416         int err;
4417         uint32_t rx_buf_size;
4418         uint32_t max_high_water;
4419         uint32_t mflcn;
4420         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4421                 ixgbe_fc_none,
4422                 ixgbe_fc_rx_pause,
4423                 ixgbe_fc_tx_pause,
4424                 ixgbe_fc_full
4425         };
4426
4427         PMD_INIT_FUNC_TRACE();
4428
4429         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4430         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4431         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4432
4433         /*
4434          * At least reserve one Ethernet frame for watermark
4435          * high_water/low_water in kilo bytes for ixgbe
4436          */
4437         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4438         if ((fc_conf->high_water > max_high_water) ||
4439                 (fc_conf->high_water < fc_conf->low_water)) {
4440                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4441                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4442                 return -EINVAL;
4443         }
4444
4445         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4446         hw->fc.pause_time     = fc_conf->pause_time;
4447         hw->fc.high_water[0]  = fc_conf->high_water;
4448         hw->fc.low_water[0]   = fc_conf->low_water;
4449         hw->fc.send_xon       = fc_conf->send_xon;
4450         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4451
4452         err = ixgbe_fc_enable(hw);
4453
4454         /* Not negotiated is not an error case */
4455         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4456
4457                 /* check if we want to forward MAC frames - driver doesn't have native
4458                  * capability to do that, so we'll write the registers ourselves */
4459
4460                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4461
4462                 /* set or clear MFLCN.PMCF bit depending on configuration */
4463                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4464                         mflcn |= IXGBE_MFLCN_PMCF;
4465                 else
4466                         mflcn &= ~IXGBE_MFLCN_PMCF;
4467
4468                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4469                 IXGBE_WRITE_FLUSH(hw);
4470
4471                 return 0;
4472         }
4473
4474         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4475         return -EIO;
4476 }
4477
4478 /**
4479  *  ixgbe_pfc_enable_generic - Enable flow control
4480  *  @hw: pointer to hardware structure
4481  *  @tc_num: traffic class number
4482  *  Enable flow control according to the current settings.
4483  */
4484 static int
4485 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4486 {
4487         int ret_val = 0;
4488         uint32_t mflcn_reg, fccfg_reg;
4489         uint32_t reg;
4490         uint32_t fcrtl, fcrth;
4491         uint8_t i;
4492         uint8_t nb_rx_en;
4493
4494         /* Validate the water mark configuration */
4495         if (!hw->fc.pause_time) {
4496                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4497                 goto out;
4498         }
4499
4500         /* Low water mark of zero causes XOFF floods */
4501         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4502                  /* High/Low water can not be 0 */
4503                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4504                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4505                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4506                         goto out;
4507                 }
4508
4509                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4510                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4511                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4512                         goto out;
4513                 }
4514         }
4515         /* Negotiate the fc mode to use */
4516         ixgbe_fc_autoneg(hw);
4517
4518         /* Disable any previous flow control settings */
4519         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4520         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4521
4522         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4523         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4524
4525         switch (hw->fc.current_mode) {
4526         case ixgbe_fc_none:
4527                 /*
4528                  * If the count of enabled RX Priority Flow control >1,
4529                  * and the TX pause can not be disabled
4530                  */
4531                 nb_rx_en = 0;
4532                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4533                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4534                         if (reg & IXGBE_FCRTH_FCEN)
4535                                 nb_rx_en++;
4536                 }
4537                 if (nb_rx_en > 1)
4538                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4539                 break;
4540         case ixgbe_fc_rx_pause:
4541                 /*
4542                  * Rx Flow control is enabled and Tx Flow control is
4543                  * disabled by software override. Since there really
4544                  * isn't a way to advertise that we are capable of RX
4545                  * Pause ONLY, we will advertise that we support both
4546                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4547                  * disable the adapter's ability to send PAUSE frames.
4548                  */
4549                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4550                 /*
4551                  * If the count of enabled RX Priority Flow control >1,
4552                  * and the TX pause can not be disabled
4553                  */
4554                 nb_rx_en = 0;
4555                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4556                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4557                         if (reg & IXGBE_FCRTH_FCEN)
4558                                 nb_rx_en++;
4559                 }
4560                 if (nb_rx_en > 1)
4561                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4562                 break;
4563         case ixgbe_fc_tx_pause:
4564                 /*
4565                  * Tx Flow control is enabled, and Rx Flow control is
4566                  * disabled by software override.
4567                  */
4568                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4569                 break;
4570         case ixgbe_fc_full:
4571                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4572                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4573                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4574                 break;
4575         default:
4576                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4577                 ret_val = IXGBE_ERR_CONFIG;
4578                 goto out;
4579         }
4580
4581         /* Set 802.3x based flow control settings. */
4582         mflcn_reg |= IXGBE_MFLCN_DPF;
4583         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4584         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4585
4586         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4587         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4588                 hw->fc.high_water[tc_num]) {
4589                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4590                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4591                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4592         } else {
4593                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4594                 /*
4595                  * In order to prevent Tx hangs when the internal Tx
4596                  * switch is enabled we must set the high water mark
4597                  * to the maximum FCRTH value.  This allows the Tx
4598                  * switch to function even under heavy Rx workloads.
4599                  */
4600                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4601         }
4602         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4603
4604         /* Configure pause time (2 TCs per register) */
4605         reg = hw->fc.pause_time * 0x00010001;
4606         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4607                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4608
4609         /* Configure flow control refresh threshold value */
4610         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4611
4612 out:
4613         return ret_val;
4614 }
4615
4616 static int
4617 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4618 {
4619         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4620         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4621
4622         if (hw->mac.type != ixgbe_mac_82598EB) {
4623                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4624         }
4625         return ret_val;
4626 }
4627
4628 static int
4629 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4630 {
4631         int err;
4632         uint32_t rx_buf_size;
4633         uint32_t max_high_water;
4634         uint8_t tc_num;
4635         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4636         struct ixgbe_hw *hw =
4637                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4638         struct ixgbe_dcb_config *dcb_config =
4639                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4640
4641         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4642                 ixgbe_fc_none,
4643                 ixgbe_fc_rx_pause,
4644                 ixgbe_fc_tx_pause,
4645                 ixgbe_fc_full
4646         };
4647
4648         PMD_INIT_FUNC_TRACE();
4649
4650         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4651         tc_num = map[pfc_conf->priority];
4652         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4653         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4654         /*
4655          * At least reserve one Ethernet frame for watermark
4656          * high_water/low_water in kilo bytes for ixgbe
4657          */
4658         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4659         if ((pfc_conf->fc.high_water > max_high_water) ||
4660             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4661                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4662                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4663                 return -EINVAL;
4664         }
4665
4666         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4667         hw->fc.pause_time = pfc_conf->fc.pause_time;
4668         hw->fc.send_xon = pfc_conf->fc.send_xon;
4669         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4670         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4671
4672         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4673
4674         /* Not negotiated is not an error case */
4675         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4676                 return 0;
4677
4678         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4679         return -EIO;
4680 }
4681
4682 static int
4683 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4684                           struct rte_eth_rss_reta_entry64 *reta_conf,
4685                           uint16_t reta_size)
4686 {
4687         uint16_t i, sp_reta_size;
4688         uint8_t j, mask;
4689         uint32_t reta, r;
4690         uint16_t idx, shift;
4691         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4692         uint32_t reta_reg;
4693
4694         PMD_INIT_FUNC_TRACE();
4695
4696         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4697                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4698                         "NIC.");
4699                 return -ENOTSUP;
4700         }
4701
4702         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4703         if (reta_size != sp_reta_size) {
4704                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4705                         "(%d) doesn't match the number hardware can supported "
4706                         "(%d)", reta_size, sp_reta_size);
4707                 return -EINVAL;
4708         }
4709
4710         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4711                 idx = i / RTE_RETA_GROUP_SIZE;
4712                 shift = i % RTE_RETA_GROUP_SIZE;
4713                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4714                                                 IXGBE_4_BIT_MASK);
4715                 if (!mask)
4716                         continue;
4717                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4718                 if (mask == IXGBE_4_BIT_MASK)
4719                         r = 0;
4720                 else
4721                         r = IXGBE_READ_REG(hw, reta_reg);
4722                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4723                         if (mask & (0x1 << j))
4724                                 reta |= reta_conf[idx].reta[shift + j] <<
4725                                                         (CHAR_BIT * j);
4726                         else
4727                                 reta |= r & (IXGBE_8_BIT_MASK <<
4728                                                 (CHAR_BIT * j));
4729                 }
4730                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4731         }
4732
4733         return 0;
4734 }
4735
4736 static int
4737 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4738                          struct rte_eth_rss_reta_entry64 *reta_conf,
4739                          uint16_t reta_size)
4740 {
4741         uint16_t i, sp_reta_size;
4742         uint8_t j, mask;
4743         uint32_t reta;
4744         uint16_t idx, shift;
4745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4746         uint32_t reta_reg;
4747
4748         PMD_INIT_FUNC_TRACE();
4749         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4750         if (reta_size != sp_reta_size) {
4751                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4752                         "(%d) doesn't match the number hardware can supported "
4753                         "(%d)", reta_size, sp_reta_size);
4754                 return -EINVAL;
4755         }
4756
4757         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4758                 idx = i / RTE_RETA_GROUP_SIZE;
4759                 shift = i % RTE_RETA_GROUP_SIZE;
4760                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4761                                                 IXGBE_4_BIT_MASK);
4762                 if (!mask)
4763                         continue;
4764
4765                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4766                 reta = IXGBE_READ_REG(hw, reta_reg);
4767                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4768                         if (mask & (0x1 << j))
4769                                 reta_conf[idx].reta[shift + j] =
4770                                         ((reta >> (CHAR_BIT * j)) &
4771                                                 IXGBE_8_BIT_MASK);
4772                 }
4773         }
4774
4775         return 0;
4776 }
4777
4778 static int
4779 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4780                                 uint32_t index, uint32_t pool)
4781 {
4782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4783         uint32_t enable_addr = 1;
4784
4785         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4786                              pool, enable_addr);
4787 }
4788
4789 static void
4790 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4791 {
4792         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4793
4794         ixgbe_clear_rar(hw, index);
4795 }
4796
4797 static void
4798 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4799 {
4800         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4801
4802         ixgbe_remove_rar(dev, 0);
4803
4804         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4805 }
4806
4807 static bool
4808 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4809 {
4810         if (strcmp(dev->device->driver->name, drv->driver.name))
4811                 return false;
4812
4813         return true;
4814 }
4815
4816 bool
4817 is_ixgbe_supported(struct rte_eth_dev *dev)
4818 {
4819         return is_device_supported(dev, &rte_ixgbe_pmd);
4820 }
4821
4822 static int
4823 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4824 {
4825         uint32_t hlreg0;
4826         uint32_t maxfrs;
4827         struct ixgbe_hw *hw;
4828         struct rte_eth_dev_info dev_info;
4829         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4830         struct rte_eth_dev_data *dev_data = dev->data;
4831
4832         ixgbe_dev_info_get(dev, &dev_info);
4833
4834         /* check that mtu is within the allowed range */
4835         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4836                 return -EINVAL;
4837
4838         /* If device is started, refuse mtu that requires the support of
4839          * scattered packets when this feature has not been enabled before.
4840          */
4841         if (dev_data->dev_started && !dev_data->scattered_rx &&
4842             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4843              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4844                 PMD_INIT_LOG(ERR, "Stop port first.");
4845                 return -EINVAL;
4846         }
4847
4848         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4849         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4850
4851         /* switch to jumbo mode if needed */
4852         if (frame_size > ETHER_MAX_LEN) {
4853                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4854                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4855         } else {
4856                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4857                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4858         }
4859         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4860
4861         /* update max frame size */
4862         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4863
4864         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4865         maxfrs &= 0x0000FFFF;
4866         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4867         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4868
4869         return 0;
4870 }
4871
4872 /*
4873  * Virtual Function operations
4874  */
4875 static void
4876 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4877 {
4878         PMD_INIT_FUNC_TRACE();
4879
4880         /* Clear interrupt mask to stop from interrupts being generated */
4881         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4882
4883         IXGBE_WRITE_FLUSH(hw);
4884 }
4885
4886 static void
4887 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4888 {
4889         PMD_INIT_FUNC_TRACE();
4890
4891         /* VF enable interrupt autoclean */
4892         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4893         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4894         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4895
4896         IXGBE_WRITE_FLUSH(hw);
4897 }
4898
4899 static int
4900 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4901 {
4902         struct rte_eth_conf *conf = &dev->data->dev_conf;
4903         struct ixgbe_adapter *adapter =
4904                         (struct ixgbe_adapter *)dev->data->dev_private;
4905
4906         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4907                      dev->data->port_id);
4908
4909         /*
4910          * VF has no ability to enable/disable HW CRC
4911          * Keep the persistent behavior the same as Host PF
4912          */
4913 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4914         if (!conf->rxmode.hw_strip_crc) {
4915                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4916                 conf->rxmode.hw_strip_crc = 1;
4917         }
4918 #else
4919         if (conf->rxmode.hw_strip_crc) {
4920                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4921                 conf->rxmode.hw_strip_crc = 0;
4922         }
4923 #endif
4924
4925         /*
4926          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4927          * allocation or vector Rx preconditions we will reset it.
4928          */
4929         adapter->rx_bulk_alloc_allowed = true;
4930         adapter->rx_vec_allowed = true;
4931
4932         return 0;
4933 }
4934
4935 static int
4936 ixgbevf_dev_start(struct rte_eth_dev *dev)
4937 {
4938         struct ixgbe_hw *hw =
4939                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4940         uint32_t intr_vector = 0;
4941         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4942         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4943
4944         int err, mask = 0;
4945
4946         PMD_INIT_FUNC_TRACE();
4947
4948         hw->mac.ops.reset_hw(hw);
4949         hw->mac.get_link_status = true;
4950
4951         /* negotiate mailbox API version to use with the PF. */
4952         ixgbevf_negotiate_api(hw);
4953
4954         ixgbevf_dev_tx_init(dev);
4955
4956         /* This can fail when allocating mbufs for descriptor rings */
4957         err = ixgbevf_dev_rx_init(dev);
4958         if (err) {
4959                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4960                 ixgbe_dev_clear_queues(dev);
4961                 return err;
4962         }
4963
4964         /* Set vfta */
4965         ixgbevf_set_vfta_all(dev, 1);
4966
4967         /* Set HW strip */
4968         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4969                 ETH_VLAN_EXTEND_MASK;
4970         ixgbevf_vlan_offload_set(dev, mask);
4971
4972         ixgbevf_dev_rxtx_start(dev);
4973
4974         /* check and configure queue intr-vector mapping */
4975         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4976                 intr_vector = dev->data->nb_rx_queues;
4977                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4978                         return -1;
4979         }
4980
4981         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4982                 intr_handle->intr_vec =
4983                         rte_zmalloc("intr_vec",
4984                                     dev->data->nb_rx_queues * sizeof(int), 0);
4985                 if (intr_handle->intr_vec == NULL) {
4986                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4987                                      " intr_vec", dev->data->nb_rx_queues);
4988                         return -ENOMEM;
4989                 }
4990         }
4991         ixgbevf_configure_msix(dev);
4992
4993         rte_intr_enable(intr_handle);
4994
4995         /* Re-enable interrupt for VF */
4996         ixgbevf_intr_enable(hw);
4997
4998         return 0;
4999 }
5000
5001 static void
5002 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5003 {
5004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5005         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5006         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5007
5008         PMD_INIT_FUNC_TRACE();
5009
5010         ixgbevf_intr_disable(hw);
5011
5012         hw->adapter_stopped = 1;
5013         ixgbe_stop_adapter(hw);
5014
5015         /*
5016           * Clear what we set, but we still keep shadow_vfta to
5017           * restore after device starts
5018           */
5019         ixgbevf_set_vfta_all(dev, 0);
5020
5021         /* Clear stored conf */
5022         dev->data->scattered_rx = 0;
5023
5024         ixgbe_dev_clear_queues(dev);
5025
5026         /* Clean datapath event and queue/vec mapping */
5027         rte_intr_efd_disable(intr_handle);
5028         if (intr_handle->intr_vec != NULL) {
5029                 rte_free(intr_handle->intr_vec);
5030                 intr_handle->intr_vec = NULL;
5031         }
5032 }
5033
5034 static void
5035 ixgbevf_dev_close(struct rte_eth_dev *dev)
5036 {
5037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5038
5039         PMD_INIT_FUNC_TRACE();
5040
5041         ixgbe_reset_hw(hw);
5042
5043         ixgbevf_dev_stop(dev);
5044
5045         ixgbe_dev_free_queues(dev);
5046
5047         /**
5048          * Remove the VF MAC address ro ensure
5049          * that the VF traffic goes to the PF
5050          * after stop, close and detach of the VF
5051          **/
5052         ixgbevf_remove_mac_addr(dev, 0);
5053 }
5054
5055 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5056 {
5057         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5058         struct ixgbe_vfta *shadow_vfta =
5059                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5060         int i = 0, j = 0, vfta = 0, mask = 1;
5061
5062         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5063                 vfta = shadow_vfta->vfta[i];
5064                 if (vfta) {
5065                         mask = 1;
5066                         for (j = 0; j < 32; j++) {
5067                                 if (vfta & mask)
5068                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5069                                                        on, false);
5070                                 mask <<= 1;
5071                         }
5072                 }
5073         }
5074
5075 }
5076
5077 static int
5078 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5079 {
5080         struct ixgbe_hw *hw =
5081                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5082         struct ixgbe_vfta *shadow_vfta =
5083                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5084         uint32_t vid_idx = 0;
5085         uint32_t vid_bit = 0;
5086         int ret = 0;
5087
5088         PMD_INIT_FUNC_TRACE();
5089
5090         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5091         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5092         if (ret) {
5093                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5094                 return ret;
5095         }
5096         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5097         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5098
5099         /* Save what we set and retore it after device reset */
5100         if (on)
5101                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5102         else
5103                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5104
5105         return 0;
5106 }
5107
5108 static void
5109 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5110 {
5111         struct ixgbe_hw *hw =
5112                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5113         uint32_t ctrl;
5114
5115         PMD_INIT_FUNC_TRACE();
5116
5117         if (queue >= hw->mac.max_rx_queues)
5118                 return;
5119
5120         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5121         if (on)
5122                 ctrl |= IXGBE_RXDCTL_VME;
5123         else
5124                 ctrl &= ~IXGBE_RXDCTL_VME;
5125         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5126
5127         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5128 }
5129
5130 static void
5131 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5132 {
5133         struct ixgbe_hw *hw =
5134                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5135         uint16_t i;
5136         int on = 0;
5137
5138         /* VF function only support hw strip feature, others are not support */
5139         if (mask & ETH_VLAN_STRIP_MASK) {
5140                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5141
5142                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5143                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5144         }
5145 }
5146
5147 int
5148 ixgbe_vt_check(struct ixgbe_hw *hw)
5149 {
5150         uint32_t reg_val;
5151
5152         /* if Virtualization Technology is enabled */
5153         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5154         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5155                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5156                 return -1;
5157         }
5158
5159         return 0;
5160 }
5161
5162 static uint32_t
5163 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5164 {
5165         uint32_t vector = 0;
5166
5167         switch (hw->mac.mc_filter_type) {
5168         case 0:   /* use bits [47:36] of the address */
5169                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5170                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5171                 break;
5172         case 1:   /* use bits [46:35] of the address */
5173                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5174                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5175                 break;
5176         case 2:   /* use bits [45:34] of the address */
5177                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5178                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5179                 break;
5180         case 3:   /* use bits [43:32] of the address */
5181                 vector = ((uc_addr->addr_bytes[4]) |
5182                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5183                 break;
5184         default:  /* Invalid mc_filter_type */
5185                 break;
5186         }
5187
5188         /* vector can only be 12-bits or boundary will be exceeded */
5189         vector &= 0xFFF;
5190         return vector;
5191 }
5192
5193 static int
5194 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5195                         uint8_t on)
5196 {
5197         uint32_t vector;
5198         uint32_t uta_idx;
5199         uint32_t reg_val;
5200         uint32_t uta_shift;
5201         uint32_t rc;
5202         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5203         const uint32_t ixgbe_uta_bit_shift = 5;
5204         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5205         const uint32_t bit1 = 0x1;
5206
5207         struct ixgbe_hw *hw =
5208                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5209         struct ixgbe_uta_info *uta_info =
5210                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5211
5212         /* The UTA table only exists on 82599 hardware and newer */
5213         if (hw->mac.type < ixgbe_mac_82599EB)
5214                 return -ENOTSUP;
5215
5216         vector = ixgbe_uta_vector(hw, mac_addr);
5217         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5218         uta_shift = vector & ixgbe_uta_bit_mask;
5219
5220         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5221         if (rc == on)
5222                 return 0;
5223
5224         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5225         if (on) {
5226                 uta_info->uta_in_use++;
5227                 reg_val |= (bit1 << uta_shift);
5228                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5229         } else {
5230                 uta_info->uta_in_use--;
5231                 reg_val &= ~(bit1 << uta_shift);
5232                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5233         }
5234
5235         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5236
5237         if (uta_info->uta_in_use > 0)
5238                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5239                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5240         else
5241                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5242
5243         return 0;
5244 }
5245
5246 static int
5247 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5248 {
5249         int i;
5250         struct ixgbe_hw *hw =
5251                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5252         struct ixgbe_uta_info *uta_info =
5253                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5254
5255         /* The UTA table only exists on 82599 hardware and newer */
5256         if (hw->mac.type < ixgbe_mac_82599EB)
5257                 return -ENOTSUP;
5258
5259         if (on) {
5260                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5261                         uta_info->uta_shadow[i] = ~0;
5262                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5263                 }
5264         } else {
5265                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5266                         uta_info->uta_shadow[i] = 0;
5267                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5268                 }
5269         }
5270         return 0;
5271
5272 }
5273
5274 uint32_t
5275 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5276 {
5277         uint32_t new_val = orig_val;
5278
5279         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5280                 new_val |= IXGBE_VMOLR_AUPE;
5281         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5282                 new_val |= IXGBE_VMOLR_ROMPE;
5283         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5284                 new_val |= IXGBE_VMOLR_ROPE;
5285         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5286                 new_val |= IXGBE_VMOLR_BAM;
5287         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5288                 new_val |= IXGBE_VMOLR_MPE;
5289
5290         return new_val;
5291 }
5292
5293 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5294 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5295 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5296 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5297 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5298         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5299         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5300
5301 static int
5302 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5303                       struct rte_eth_mirror_conf *mirror_conf,
5304                       uint8_t rule_id, uint8_t on)
5305 {
5306         uint32_t mr_ctl, vlvf;
5307         uint32_t mp_lsb = 0;
5308         uint32_t mv_msb = 0;
5309         uint32_t mv_lsb = 0;
5310         uint32_t mp_msb = 0;
5311         uint8_t i = 0;
5312         int reg_index = 0;
5313         uint64_t vlan_mask = 0;
5314
5315         const uint8_t pool_mask_offset = 32;
5316         const uint8_t vlan_mask_offset = 32;
5317         const uint8_t dst_pool_offset = 8;
5318         const uint8_t rule_mr_offset  = 4;
5319         const uint8_t mirror_rule_mask = 0x0F;
5320
5321         struct ixgbe_mirror_info *mr_info =
5322                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5323         struct ixgbe_hw *hw =
5324                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5325         uint8_t mirror_type = 0;
5326
5327         if (ixgbe_vt_check(hw) < 0)
5328                 return -ENOTSUP;
5329
5330         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5331                 return -EINVAL;
5332
5333         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5334                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5335                             mirror_conf->rule_type);
5336                 return -EINVAL;
5337         }
5338
5339         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5340                 mirror_type |= IXGBE_MRCTL_VLME;
5341                 /* Check if vlan id is valid and find conresponding VLAN ID
5342                  * index in VLVF
5343                  */
5344                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5345                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5346                                 /* search vlan id related pool vlan filter
5347                                  * index
5348                                  */
5349                                 reg_index = ixgbe_find_vlvf_slot(
5350                                                 hw,
5351                                                 mirror_conf->vlan.vlan_id[i],
5352                                                 false);
5353                                 if (reg_index < 0)
5354                                         return -EINVAL;
5355                                 vlvf = IXGBE_READ_REG(hw,
5356                                                       IXGBE_VLVF(reg_index));
5357                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5358                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5359                                       mirror_conf->vlan.vlan_id[i]))
5360                                         vlan_mask |= (1ULL << reg_index);
5361                                 else
5362                                         return -EINVAL;
5363                         }
5364                 }
5365
5366                 if (on) {
5367                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5368                         mv_msb = vlan_mask >> vlan_mask_offset;
5369
5370                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5371                                                 mirror_conf->vlan.vlan_mask;
5372                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5373                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5374                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5375                                                 mirror_conf->vlan.vlan_id[i];
5376                         }
5377                 } else {
5378                         mv_lsb = 0;
5379                         mv_msb = 0;
5380                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5381                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5382                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5383                 }
5384         }
5385
5386         /**
5387          * if enable pool mirror, write related pool mask register,if disable
5388          * pool mirror, clear PFMRVM register
5389          */
5390         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5391                 mirror_type |= IXGBE_MRCTL_VPME;
5392                 if (on) {
5393                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5394                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5395                         mr_info->mr_conf[rule_id].pool_mask =
5396                                         mirror_conf->pool_mask;
5397
5398                 } else {
5399                         mp_lsb = 0;
5400                         mp_msb = 0;
5401                         mr_info->mr_conf[rule_id].pool_mask = 0;
5402                 }
5403         }
5404         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5405                 mirror_type |= IXGBE_MRCTL_UPME;
5406         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5407                 mirror_type |= IXGBE_MRCTL_DPME;
5408
5409         /* read  mirror control register and recalculate it */
5410         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5411
5412         if (on) {
5413                 mr_ctl |= mirror_type;
5414                 mr_ctl &= mirror_rule_mask;
5415                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5416         } else {
5417                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5418         }
5419
5420         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5421         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5422
5423         /* write mirrror control  register */
5424         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5425
5426         /* write pool mirrror control  register */
5427         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5428                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5429                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5430                                 mp_msb);
5431         }
5432         /* write VLAN mirrror control  register */
5433         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5434                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5435                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5436                                 mv_msb);
5437         }
5438
5439         return 0;
5440 }
5441
5442 static int
5443 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5444 {
5445         int mr_ctl = 0;
5446         uint32_t lsb_val = 0;
5447         uint32_t msb_val = 0;
5448         const uint8_t rule_mr_offset = 4;
5449
5450         struct ixgbe_hw *hw =
5451                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5452         struct ixgbe_mirror_info *mr_info =
5453                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5454
5455         if (ixgbe_vt_check(hw) < 0)
5456                 return -ENOTSUP;
5457
5458         memset(&mr_info->mr_conf[rule_id], 0,
5459                sizeof(struct rte_eth_mirror_conf));
5460
5461         /* clear PFVMCTL register */
5462         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5463
5464         /* clear pool mask register */
5465         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5466         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5467
5468         /* clear vlan mask register */
5469         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5470         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5471
5472         return 0;
5473 }
5474
5475 static int
5476 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5477 {
5478         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5479         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5480         uint32_t mask;
5481         struct ixgbe_hw *hw =
5482                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5483
5484         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5485         mask |= (1 << IXGBE_MISC_VEC_ID);
5486         RTE_SET_USED(queue_id);
5487         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5488
5489         rte_intr_enable(intr_handle);
5490
5491         return 0;
5492 }
5493
5494 static int
5495 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5496 {
5497         uint32_t mask;
5498         struct ixgbe_hw *hw =
5499                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5500
5501         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5502         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5503         RTE_SET_USED(queue_id);
5504         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5505
5506         return 0;
5507 }
5508
5509 static int
5510 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5511 {
5512         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5513         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5514         uint32_t mask;
5515         struct ixgbe_hw *hw =
5516                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5517         struct ixgbe_interrupt *intr =
5518                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5519
5520         if (queue_id < 16) {
5521                 ixgbe_disable_intr(hw);
5522                 intr->mask |= (1 << queue_id);
5523                 ixgbe_enable_intr(dev);
5524         } else if (queue_id < 32) {
5525                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5526                 mask &= (1 << queue_id);
5527                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5528         } else if (queue_id < 64) {
5529                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5530                 mask &= (1 << (queue_id - 32));
5531                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5532         }
5533         rte_intr_enable(intr_handle);
5534
5535         return 0;
5536 }
5537
5538 static int
5539 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5540 {
5541         uint32_t mask;
5542         struct ixgbe_hw *hw =
5543                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5544         struct ixgbe_interrupt *intr =
5545                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5546
5547         if (queue_id < 16) {
5548                 ixgbe_disable_intr(hw);
5549                 intr->mask &= ~(1 << queue_id);
5550                 ixgbe_enable_intr(dev);
5551         } else if (queue_id < 32) {
5552                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5553                 mask &= ~(1 << queue_id);
5554                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5555         } else if (queue_id < 64) {
5556                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5557                 mask &= ~(1 << (queue_id - 32));
5558                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5559         }
5560
5561         return 0;
5562 }
5563
5564 static void
5565 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5566                      uint8_t queue, uint8_t msix_vector)
5567 {
5568         uint32_t tmp, idx;
5569
5570         if (direction == -1) {
5571                 /* other causes */
5572                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5573                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5574                 tmp &= ~0xFF;
5575                 tmp |= msix_vector;
5576                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5577         } else {
5578                 /* rx or tx cause */
5579                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5580                 idx = ((16 * (queue & 1)) + (8 * direction));
5581                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5582                 tmp &= ~(0xFF << idx);
5583                 tmp |= (msix_vector << idx);
5584                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5585         }
5586 }
5587
5588 /**
5589  * set the IVAR registers, mapping interrupt causes to vectors
5590  * @param hw
5591  *  pointer to ixgbe_hw struct
5592  * @direction
5593  *  0 for Rx, 1 for Tx, -1 for other causes
5594  * @queue
5595  *  queue to map the corresponding interrupt to
5596  * @msix_vector
5597  *  the vector to map to the corresponding queue
5598  */
5599 static void
5600 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5601                    uint8_t queue, uint8_t msix_vector)
5602 {
5603         uint32_t tmp, idx;
5604
5605         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5606         if (hw->mac.type == ixgbe_mac_82598EB) {
5607                 if (direction == -1)
5608                         direction = 0;
5609                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5610                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5611                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5612                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5613                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5614         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5615                         (hw->mac.type == ixgbe_mac_X540)) {
5616                 if (direction == -1) {
5617                         /* other causes */
5618                         idx = ((queue & 1) * 8);
5619                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5620                         tmp &= ~(0xFF << idx);
5621                         tmp |= (msix_vector << idx);
5622                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5623                 } else {
5624                         /* rx or tx causes */
5625                         idx = ((16 * (queue & 1)) + (8 * direction));
5626                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5627                         tmp &= ~(0xFF << idx);
5628                         tmp |= (msix_vector << idx);
5629                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5630                 }
5631         }
5632 }
5633
5634 static void
5635 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5636 {
5637         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5638         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5639         struct ixgbe_hw *hw =
5640                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5641         uint32_t q_idx;
5642         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5643
5644         /* Configure VF other cause ivar */
5645         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5646
5647         /* won't configure msix register if no mapping is done
5648          * between intr vector and event fd.
5649          */
5650         if (!rte_intr_dp_is_en(intr_handle))
5651                 return;
5652
5653         /* Configure all RX queues of VF */
5654         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5655                 /* Force all queue use vector 0,
5656                  * as IXGBE_VF_MAXMSIVECOTR = 1
5657                  */
5658                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5659                 intr_handle->intr_vec[q_idx] = vector_idx;
5660         }
5661 }
5662
5663 /**
5664  * Sets up the hardware to properly generate MSI-X interrupts
5665  * @hw
5666  *  board private structure
5667  */
5668 static void
5669 ixgbe_configure_msix(struct rte_eth_dev *dev)
5670 {
5671         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5672         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5673         struct ixgbe_hw *hw =
5674                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5675         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5676         uint32_t vec = IXGBE_MISC_VEC_ID;
5677         uint32_t mask;
5678         uint32_t gpie;
5679
5680         /* won't configure msix register if no mapping is done
5681          * between intr vector and event fd
5682          */
5683         if (!rte_intr_dp_is_en(intr_handle))
5684                 return;
5685
5686         if (rte_intr_allow_others(intr_handle))
5687                 vec = base = IXGBE_RX_VEC_START;
5688
5689         /* setup GPIE for MSI-x mode */
5690         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5691         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5692                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5693         /* auto clearing and auto setting corresponding bits in EIMS
5694          * when MSI-X interrupt is triggered
5695          */
5696         if (hw->mac.type == ixgbe_mac_82598EB) {
5697                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5698         } else {
5699                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5700                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5701         }
5702         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5703
5704         /* Populate the IVAR table and set the ITR values to the
5705          * corresponding register.
5706          */
5707         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5708              queue_id++) {
5709                 /* by default, 1:1 mapping */
5710                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5711                 intr_handle->intr_vec[queue_id] = vec;
5712                 if (vec < base + intr_handle->nb_efd - 1)
5713                         vec++;
5714         }
5715
5716         switch (hw->mac.type) {
5717         case ixgbe_mac_82598EB:
5718                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5719                                    IXGBE_MISC_VEC_ID);
5720                 break;
5721         case ixgbe_mac_82599EB:
5722         case ixgbe_mac_X540:
5723                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5724                 break;
5725         default:
5726                 break;
5727         }
5728         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5729                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5730
5731         /* set up to autoclear timer, and the vectors */
5732         mask = IXGBE_EIMS_ENABLE_MASK;
5733         mask &= ~(IXGBE_EIMS_OTHER |
5734                   IXGBE_EIMS_MAILBOX |
5735                   IXGBE_EIMS_LSC);
5736
5737         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5738 }
5739
5740 int
5741 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5742                            uint16_t queue_idx, uint16_t tx_rate)
5743 {
5744         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5745         uint32_t rf_dec, rf_int;
5746         uint32_t bcnrc_val;
5747         uint16_t link_speed = dev->data->dev_link.link_speed;
5748
5749         if (queue_idx >= hw->mac.max_tx_queues)
5750                 return -EINVAL;
5751
5752         if (tx_rate != 0) {
5753                 /* Calculate the rate factor values to set */
5754                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5755                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5756                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5757
5758                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5759                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5760                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5761                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5762         } else {
5763                 bcnrc_val = 0;
5764         }
5765
5766         /*
5767          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5768          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5769          * set as 0x4.
5770          */
5771         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5772                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5773                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5774                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5775                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5776         else
5777                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5778                         IXGBE_MMW_SIZE_DEFAULT);
5779
5780         /* Set RTTBCNRC of queue X */
5781         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5782         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5783         IXGBE_WRITE_FLUSH(hw);
5784
5785         return 0;
5786 }
5787
5788 static int
5789 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5790                      __attribute__((unused)) uint32_t index,
5791                      __attribute__((unused)) uint32_t pool)
5792 {
5793         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5794         int diag;
5795
5796         /*
5797          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5798          * operation. Trap this case to avoid exhausting the [very limited]
5799          * set of PF resources used to store VF MAC addresses.
5800          */
5801         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5802                 return -1;
5803         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5804         if (diag != 0)
5805                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5806                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5807                             mac_addr->addr_bytes[0],
5808                             mac_addr->addr_bytes[1],
5809                             mac_addr->addr_bytes[2],
5810                             mac_addr->addr_bytes[3],
5811                             mac_addr->addr_bytes[4],
5812                             mac_addr->addr_bytes[5],
5813                             diag);
5814         return diag;
5815 }
5816
5817 static void
5818 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5819 {
5820         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5821         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5822         struct ether_addr *mac_addr;
5823         uint32_t i;
5824         int diag;
5825
5826         /*
5827          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5828          * not support the deletion of a given MAC address.
5829          * Instead, it imposes to delete all MAC addresses, then to add again
5830          * all MAC addresses with the exception of the one to be deleted.
5831          */
5832         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5833
5834         /*
5835          * Add again all MAC addresses, with the exception of the deleted one
5836          * and of the permanent MAC address.
5837          */
5838         for (i = 0, mac_addr = dev->data->mac_addrs;
5839              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5840                 /* Skip the deleted MAC address */
5841                 if (i == index)
5842                         continue;
5843                 /* Skip NULL MAC addresses */
5844                 if (is_zero_ether_addr(mac_addr))
5845                         continue;
5846                 /* Skip the permanent MAC address */
5847                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5848                         continue;
5849                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5850                 if (diag != 0)
5851                         PMD_DRV_LOG(ERR,
5852                                     "Adding again MAC address "
5853                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5854                                     "diag=%d",
5855                                     mac_addr->addr_bytes[0],
5856                                     mac_addr->addr_bytes[1],
5857                                     mac_addr->addr_bytes[2],
5858                                     mac_addr->addr_bytes[3],
5859                                     mac_addr->addr_bytes[4],
5860                                     mac_addr->addr_bytes[5],
5861                                     diag);
5862         }
5863 }
5864
5865 static void
5866 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5867 {
5868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5869
5870         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5871 }
5872
5873 int
5874 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5875                         struct rte_eth_syn_filter *filter,
5876                         bool add)
5877 {
5878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5879         struct ixgbe_filter_info *filter_info =
5880                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5881         uint32_t syn_info;
5882         uint32_t synqf;
5883
5884         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5885                 return -EINVAL;
5886
5887         syn_info = filter_info->syn_info;
5888
5889         if (add) {
5890                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5891                         return -EINVAL;
5892                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5893                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5894
5895                 if (filter->hig_pri)
5896                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5897                 else
5898                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5899         } else {
5900                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5901                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5902                         return -ENOENT;
5903                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5904         }
5905
5906         filter_info->syn_info = synqf;
5907         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5908         IXGBE_WRITE_FLUSH(hw);
5909         return 0;
5910 }
5911
5912 static int
5913 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5914                         struct rte_eth_syn_filter *filter)
5915 {
5916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5917         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5918
5919         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5920                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5921                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5922                 return 0;
5923         }
5924         return -ENOENT;
5925 }
5926
5927 static int
5928 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5929                         enum rte_filter_op filter_op,
5930                         void *arg)
5931 {
5932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5933         int ret;
5934
5935         MAC_TYPE_FILTER_SUP(hw->mac.type);
5936
5937         if (filter_op == RTE_ETH_FILTER_NOP)
5938                 return 0;
5939
5940         if (arg == NULL) {
5941                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5942                             filter_op);
5943                 return -EINVAL;
5944         }
5945
5946         switch (filter_op) {
5947         case RTE_ETH_FILTER_ADD:
5948                 ret = ixgbe_syn_filter_set(dev,
5949                                 (struct rte_eth_syn_filter *)arg,
5950                                 TRUE);
5951                 break;
5952         case RTE_ETH_FILTER_DELETE:
5953                 ret = ixgbe_syn_filter_set(dev,
5954                                 (struct rte_eth_syn_filter *)arg,
5955                                 FALSE);
5956                 break;
5957         case RTE_ETH_FILTER_GET:
5958                 ret = ixgbe_syn_filter_get(dev,
5959                                 (struct rte_eth_syn_filter *)arg);
5960                 break;
5961         default:
5962                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5963                 ret = -EINVAL;
5964                 break;
5965         }
5966
5967         return ret;
5968 }
5969
5970
5971 static inline enum ixgbe_5tuple_protocol
5972 convert_protocol_type(uint8_t protocol_value)
5973 {
5974         if (protocol_value == IPPROTO_TCP)
5975                 return IXGBE_FILTER_PROTOCOL_TCP;
5976         else if (protocol_value == IPPROTO_UDP)
5977                 return IXGBE_FILTER_PROTOCOL_UDP;
5978         else if (protocol_value == IPPROTO_SCTP)
5979                 return IXGBE_FILTER_PROTOCOL_SCTP;
5980         else
5981                 return IXGBE_FILTER_PROTOCOL_NONE;
5982 }
5983
5984 /* inject a 5-tuple filter to HW */
5985 static inline void
5986 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5987                            struct ixgbe_5tuple_filter *filter)
5988 {
5989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5990         int i;
5991         uint32_t ftqf, sdpqf;
5992         uint32_t l34timir = 0;
5993         uint8_t mask = 0xff;
5994
5995         i = filter->index;
5996
5997         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5998                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5999         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6000
6001         ftqf = (uint32_t)(filter->filter_info.proto &
6002                 IXGBE_FTQF_PROTOCOL_MASK);
6003         ftqf |= (uint32_t)((filter->filter_info.priority &
6004                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6005         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6006                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6007         if (filter->filter_info.dst_ip_mask == 0)
6008                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6009         if (filter->filter_info.src_port_mask == 0)
6010                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6011         if (filter->filter_info.dst_port_mask == 0)
6012                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6013         if (filter->filter_info.proto_mask == 0)
6014                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6015         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6016         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6017         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6018
6019         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6020         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6021         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6022         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6023
6024         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6025         l34timir |= (uint32_t)(filter->queue <<
6026                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6027         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6028 }
6029
6030 /*
6031  * add a 5tuple filter
6032  *
6033  * @param
6034  * dev: Pointer to struct rte_eth_dev.
6035  * index: the index the filter allocates.
6036  * filter: ponter to the filter that will be added.
6037  * rx_queue: the queue id the filter assigned to.
6038  *
6039  * @return
6040  *    - On success, zero.
6041  *    - On failure, a negative value.
6042  */
6043 static int
6044 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6045                         struct ixgbe_5tuple_filter *filter)
6046 {
6047         struct ixgbe_filter_info *filter_info =
6048                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6049         int i, idx, shift;
6050
6051         /*
6052          * look for an unused 5tuple filter index,
6053          * and insert the filter to list.
6054          */
6055         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6056                 idx = i / (sizeof(uint32_t) * NBBY);
6057                 shift = i % (sizeof(uint32_t) * NBBY);
6058                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6059                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6060                         filter->index = i;
6061                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6062                                           filter,
6063                                           entries);
6064                         break;
6065                 }
6066         }
6067         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6068                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6069                 return -ENOSYS;
6070         }
6071
6072         ixgbe_inject_5tuple_filter(dev, filter);
6073
6074         return 0;
6075 }
6076
6077 /*
6078  * remove a 5tuple filter
6079  *
6080  * @param
6081  * dev: Pointer to struct rte_eth_dev.
6082  * filter: the pointer of the filter will be removed.
6083  */
6084 static void
6085 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6086                         struct ixgbe_5tuple_filter *filter)
6087 {
6088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6089         struct ixgbe_filter_info *filter_info =
6090                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6091         uint16_t index = filter->index;
6092
6093         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6094                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6095         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6096         rte_free(filter);
6097
6098         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6099         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6100         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6101         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6102         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6103 }
6104
6105 static int
6106 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6107 {
6108         struct ixgbe_hw *hw;
6109         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6110         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6111
6112         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6113
6114         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6115                 return -EINVAL;
6116
6117         /* refuse mtu that requires the support of scattered packets when this
6118          * feature has not been enabled before.
6119          */
6120         if (!rx_conf->enable_scatter &&
6121             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6122              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6123                 return -EINVAL;
6124
6125         /*
6126          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6127          * request of the version 2.0 of the mailbox API.
6128          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6129          * of the mailbox API.
6130          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6131          * prior to 3.11.33 which contains the following change:
6132          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6133          */
6134         ixgbevf_rlpml_set_vf(hw, max_frame);
6135
6136         /* update max frame size */
6137         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6138         return 0;
6139 }
6140
6141 static inline struct ixgbe_5tuple_filter *
6142 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6143                         struct ixgbe_5tuple_filter_info *key)
6144 {
6145         struct ixgbe_5tuple_filter *it;
6146
6147         TAILQ_FOREACH(it, filter_list, entries) {
6148                 if (memcmp(key, &it->filter_info,
6149                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6150                         return it;
6151                 }
6152         }
6153         return NULL;
6154 }
6155
6156 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6157 static inline int
6158 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6159                         struct ixgbe_5tuple_filter_info *filter_info)
6160 {
6161         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6162                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6163                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6164                 return -EINVAL;
6165
6166         switch (filter->dst_ip_mask) {
6167         case UINT32_MAX:
6168                 filter_info->dst_ip_mask = 0;
6169                 filter_info->dst_ip = filter->dst_ip;
6170                 break;
6171         case 0:
6172                 filter_info->dst_ip_mask = 1;
6173                 break;
6174         default:
6175                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6176                 return -EINVAL;
6177         }
6178
6179         switch (filter->src_ip_mask) {
6180         case UINT32_MAX:
6181                 filter_info->src_ip_mask = 0;
6182                 filter_info->src_ip = filter->src_ip;
6183                 break;
6184         case 0:
6185                 filter_info->src_ip_mask = 1;
6186                 break;
6187         default:
6188                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6189                 return -EINVAL;
6190         }
6191
6192         switch (filter->dst_port_mask) {
6193         case UINT16_MAX:
6194                 filter_info->dst_port_mask = 0;
6195                 filter_info->dst_port = filter->dst_port;
6196                 break;
6197         case 0:
6198                 filter_info->dst_port_mask = 1;
6199                 break;
6200         default:
6201                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6202                 return -EINVAL;
6203         }
6204
6205         switch (filter->src_port_mask) {
6206         case UINT16_MAX:
6207                 filter_info->src_port_mask = 0;
6208                 filter_info->src_port = filter->src_port;
6209                 break;
6210         case 0:
6211                 filter_info->src_port_mask = 1;
6212                 break;
6213         default:
6214                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6215                 return -EINVAL;
6216         }
6217
6218         switch (filter->proto_mask) {
6219         case UINT8_MAX:
6220                 filter_info->proto_mask = 0;
6221                 filter_info->proto =
6222                         convert_protocol_type(filter->proto);
6223                 break;
6224         case 0:
6225                 filter_info->proto_mask = 1;
6226                 break;
6227         default:
6228                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6229                 return -EINVAL;
6230         }
6231
6232         filter_info->priority = (uint8_t)filter->priority;
6233         return 0;
6234 }
6235
6236 /*
6237  * add or delete a ntuple filter
6238  *
6239  * @param
6240  * dev: Pointer to struct rte_eth_dev.
6241  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6242  * add: if true, add filter, if false, remove filter
6243  *
6244  * @return
6245  *    - On success, zero.
6246  *    - On failure, a negative value.
6247  */
6248 int
6249 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6250                         struct rte_eth_ntuple_filter *ntuple_filter,
6251                         bool add)
6252 {
6253         struct ixgbe_filter_info *filter_info =
6254                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6255         struct ixgbe_5tuple_filter_info filter_5tuple;
6256         struct ixgbe_5tuple_filter *filter;
6257         int ret;
6258
6259         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6260                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6261                 return -EINVAL;
6262         }
6263
6264         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6265         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6266         if (ret < 0)
6267                 return ret;
6268
6269         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6270                                          &filter_5tuple);
6271         if (filter != NULL && add) {
6272                 PMD_DRV_LOG(ERR, "filter exists.");
6273                 return -EEXIST;
6274         }
6275         if (filter == NULL && !add) {
6276                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6277                 return -ENOENT;
6278         }
6279
6280         if (add) {
6281                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6282                                 sizeof(struct ixgbe_5tuple_filter), 0);
6283                 if (filter == NULL)
6284                         return -ENOMEM;
6285                 (void)rte_memcpy(&filter->filter_info,
6286                                  &filter_5tuple,
6287                                  sizeof(struct ixgbe_5tuple_filter_info));
6288                 filter->queue = ntuple_filter->queue;
6289                 ret = ixgbe_add_5tuple_filter(dev, filter);
6290                 if (ret < 0) {
6291                         rte_free(filter);
6292                         return ret;
6293                 }
6294         } else
6295                 ixgbe_remove_5tuple_filter(dev, filter);
6296
6297         return 0;
6298 }
6299
6300 /*
6301  * get a ntuple filter
6302  *
6303  * @param
6304  * dev: Pointer to struct rte_eth_dev.
6305  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6306  *
6307  * @return
6308  *    - On success, zero.
6309  *    - On failure, a negative value.
6310  */
6311 static int
6312 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6313                         struct rte_eth_ntuple_filter *ntuple_filter)
6314 {
6315         struct ixgbe_filter_info *filter_info =
6316                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6317         struct ixgbe_5tuple_filter_info filter_5tuple;
6318         struct ixgbe_5tuple_filter *filter;
6319         int ret;
6320
6321         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6322                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6323                 return -EINVAL;
6324         }
6325
6326         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6327         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6328         if (ret < 0)
6329                 return ret;
6330
6331         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6332                                          &filter_5tuple);
6333         if (filter == NULL) {
6334                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6335                 return -ENOENT;
6336         }
6337         ntuple_filter->queue = filter->queue;
6338         return 0;
6339 }
6340
6341 /*
6342  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6343  * @dev: pointer to rte_eth_dev structure
6344  * @filter_op:operation will be taken.
6345  * @arg: a pointer to specific structure corresponding to the filter_op
6346  *
6347  * @return
6348  *    - On success, zero.
6349  *    - On failure, a negative value.
6350  */
6351 static int
6352 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6353                                 enum rte_filter_op filter_op,
6354                                 void *arg)
6355 {
6356         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6357         int ret;
6358
6359         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6360
6361         if (filter_op == RTE_ETH_FILTER_NOP)
6362                 return 0;
6363
6364         if (arg == NULL) {
6365                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6366                             filter_op);
6367                 return -EINVAL;
6368         }
6369
6370         switch (filter_op) {
6371         case RTE_ETH_FILTER_ADD:
6372                 ret = ixgbe_add_del_ntuple_filter(dev,
6373                         (struct rte_eth_ntuple_filter *)arg,
6374                         TRUE);
6375                 break;
6376         case RTE_ETH_FILTER_DELETE:
6377                 ret = ixgbe_add_del_ntuple_filter(dev,
6378                         (struct rte_eth_ntuple_filter *)arg,
6379                         FALSE);
6380                 break;
6381         case RTE_ETH_FILTER_GET:
6382                 ret = ixgbe_get_ntuple_filter(dev,
6383                         (struct rte_eth_ntuple_filter *)arg);
6384                 break;
6385         default:
6386                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6387                 ret = -EINVAL;
6388                 break;
6389         }
6390         return ret;
6391 }
6392
6393 int
6394 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6395                         struct rte_eth_ethertype_filter *filter,
6396                         bool add)
6397 {
6398         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6399         struct ixgbe_filter_info *filter_info =
6400                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6401         uint32_t etqf = 0;
6402         uint32_t etqs = 0;
6403         int ret;
6404         struct ixgbe_ethertype_filter ethertype_filter;
6405
6406         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6407                 return -EINVAL;
6408
6409         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6410                 filter->ether_type == ETHER_TYPE_IPv6) {
6411                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6412                         " ethertype filter.", filter->ether_type);
6413                 return -EINVAL;
6414         }
6415
6416         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6417                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6418                 return -EINVAL;
6419         }
6420         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6421                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6422                 return -EINVAL;
6423         }
6424
6425         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6426         if (ret >= 0 && add) {
6427                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6428                             filter->ether_type);
6429                 return -EEXIST;
6430         }
6431         if (ret < 0 && !add) {
6432                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6433                             filter->ether_type);
6434                 return -ENOENT;
6435         }
6436
6437         if (add) {
6438                 etqf = IXGBE_ETQF_FILTER_EN;
6439                 etqf |= (uint32_t)filter->ether_type;
6440                 etqs |= (uint32_t)((filter->queue <<
6441                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6442                                     IXGBE_ETQS_RX_QUEUE);
6443                 etqs |= IXGBE_ETQS_QUEUE_EN;
6444
6445                 ethertype_filter.ethertype = filter->ether_type;
6446                 ethertype_filter.etqf = etqf;
6447                 ethertype_filter.etqs = etqs;
6448                 ethertype_filter.conf = FALSE;
6449                 ret = ixgbe_ethertype_filter_insert(filter_info,
6450                                                     &ethertype_filter);
6451                 if (ret < 0) {
6452                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6453                         return -ENOSPC;
6454                 }
6455         } else {
6456                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6457                 if (ret < 0)
6458                         return -ENOSYS;
6459         }
6460         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6461         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6462         IXGBE_WRITE_FLUSH(hw);
6463
6464         return 0;
6465 }
6466
6467 static int
6468 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6469                         struct rte_eth_ethertype_filter *filter)
6470 {
6471         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6472         struct ixgbe_filter_info *filter_info =
6473                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6474         uint32_t etqf, etqs;
6475         int ret;
6476
6477         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6478         if (ret < 0) {
6479                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6480                             filter->ether_type);
6481                 return -ENOENT;
6482         }
6483
6484         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6485         if (etqf & IXGBE_ETQF_FILTER_EN) {
6486                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6487                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6488                 filter->flags = 0;
6489                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6490                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6491                 return 0;
6492         }
6493         return -ENOENT;
6494 }
6495
6496 /*
6497  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6498  * @dev: pointer to rte_eth_dev structure
6499  * @filter_op:operation will be taken.
6500  * @arg: a pointer to specific structure corresponding to the filter_op
6501  */
6502 static int
6503 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6504                                 enum rte_filter_op filter_op,
6505                                 void *arg)
6506 {
6507         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6508         int ret;
6509
6510         MAC_TYPE_FILTER_SUP(hw->mac.type);
6511
6512         if (filter_op == RTE_ETH_FILTER_NOP)
6513                 return 0;
6514
6515         if (arg == NULL) {
6516                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6517                             filter_op);
6518                 return -EINVAL;
6519         }
6520
6521         switch (filter_op) {
6522         case RTE_ETH_FILTER_ADD:
6523                 ret = ixgbe_add_del_ethertype_filter(dev,
6524                         (struct rte_eth_ethertype_filter *)arg,
6525                         TRUE);
6526                 break;
6527         case RTE_ETH_FILTER_DELETE:
6528                 ret = ixgbe_add_del_ethertype_filter(dev,
6529                         (struct rte_eth_ethertype_filter *)arg,
6530                         FALSE);
6531                 break;
6532         case RTE_ETH_FILTER_GET:
6533                 ret = ixgbe_get_ethertype_filter(dev,
6534                         (struct rte_eth_ethertype_filter *)arg);
6535                 break;
6536         default:
6537                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6538                 ret = -EINVAL;
6539                 break;
6540         }
6541         return ret;
6542 }
6543
6544 static int
6545 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6546                      enum rte_filter_type filter_type,
6547                      enum rte_filter_op filter_op,
6548                      void *arg)
6549 {
6550         int ret = 0;
6551
6552         switch (filter_type) {
6553         case RTE_ETH_FILTER_NTUPLE:
6554                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6555                 break;
6556         case RTE_ETH_FILTER_ETHERTYPE:
6557                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6558                 break;
6559         case RTE_ETH_FILTER_SYN:
6560                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6561                 break;
6562         case RTE_ETH_FILTER_FDIR:
6563                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6564                 break;
6565         case RTE_ETH_FILTER_L2_TUNNEL:
6566                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6567                 break;
6568         case RTE_ETH_FILTER_GENERIC:
6569                 if (filter_op != RTE_ETH_FILTER_GET)
6570                         return -EINVAL;
6571                 *(const void **)arg = &ixgbe_flow_ops;
6572                 break;
6573         default:
6574                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6575                                                         filter_type);
6576                 ret = -EINVAL;
6577                 break;
6578         }
6579
6580         return ret;
6581 }
6582
6583 static u8 *
6584 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6585                         u8 **mc_addr_ptr, u32 *vmdq)
6586 {
6587         u8 *mc_addr;
6588
6589         *vmdq = 0;
6590         mc_addr = *mc_addr_ptr;
6591         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6592         return mc_addr;
6593 }
6594
6595 static int
6596 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6597                           struct ether_addr *mc_addr_set,
6598                           uint32_t nb_mc_addr)
6599 {
6600         struct ixgbe_hw *hw;
6601         u8 *mc_addr_list;
6602
6603         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6604         mc_addr_list = (u8 *)mc_addr_set;
6605         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6606                                          ixgbe_dev_addr_list_itr, TRUE);
6607 }
6608
6609 static uint64_t
6610 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6611 {
6612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6613         uint64_t systime_cycles;
6614
6615         switch (hw->mac.type) {
6616         case ixgbe_mac_X550:
6617         case ixgbe_mac_X550EM_x:
6618         case ixgbe_mac_X550EM_a:
6619                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6620                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6621                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6622                                 * NSEC_PER_SEC;
6623                 break;
6624         default:
6625                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6626                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6627                                 << 32;
6628         }
6629
6630         return systime_cycles;
6631 }
6632
6633 static uint64_t
6634 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6635 {
6636         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6637         uint64_t rx_tstamp_cycles;
6638
6639         switch (hw->mac.type) {
6640         case ixgbe_mac_X550:
6641         case ixgbe_mac_X550EM_x:
6642         case ixgbe_mac_X550EM_a:
6643                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6644                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6645                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6646                                 * NSEC_PER_SEC;
6647                 break;
6648         default:
6649                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6650                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6651                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6652                                 << 32;
6653         }
6654
6655         return rx_tstamp_cycles;
6656 }
6657
6658 static uint64_t
6659 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6660 {
6661         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6662         uint64_t tx_tstamp_cycles;
6663
6664         switch (hw->mac.type) {
6665         case ixgbe_mac_X550:
6666         case ixgbe_mac_X550EM_x:
6667         case ixgbe_mac_X550EM_a:
6668                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6669                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6670                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6671                                 * NSEC_PER_SEC;
6672                 break;
6673         default:
6674                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6675                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6676                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6677                                 << 32;
6678         }
6679
6680         return tx_tstamp_cycles;
6681 }
6682
6683 static void
6684 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6685 {
6686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6687         struct ixgbe_adapter *adapter =
6688                 (struct ixgbe_adapter *)dev->data->dev_private;
6689         struct rte_eth_link link;
6690         uint32_t incval = 0;
6691         uint32_t shift = 0;
6692
6693         /* Get current link speed. */
6694         memset(&link, 0, sizeof(link));
6695         ixgbe_dev_link_update(dev, 1);
6696         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6697
6698         switch (link.link_speed) {
6699         case ETH_SPEED_NUM_100M:
6700                 incval = IXGBE_INCVAL_100;
6701                 shift = IXGBE_INCVAL_SHIFT_100;
6702                 break;
6703         case ETH_SPEED_NUM_1G:
6704                 incval = IXGBE_INCVAL_1GB;
6705                 shift = IXGBE_INCVAL_SHIFT_1GB;
6706                 break;
6707         case ETH_SPEED_NUM_10G:
6708         default:
6709                 incval = IXGBE_INCVAL_10GB;
6710                 shift = IXGBE_INCVAL_SHIFT_10GB;
6711                 break;
6712         }
6713
6714         switch (hw->mac.type) {
6715         case ixgbe_mac_X550:
6716         case ixgbe_mac_X550EM_x:
6717         case ixgbe_mac_X550EM_a:
6718                 /* Independent of link speed. */
6719                 incval = 1;
6720                 /* Cycles read will be interpreted as ns. */
6721                 shift = 0;
6722                 /* Fall-through */
6723         case ixgbe_mac_X540:
6724                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6725                 break;
6726         case ixgbe_mac_82599EB:
6727                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6728                 shift -= IXGBE_INCVAL_SHIFT_82599;
6729                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6730                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6731                 break;
6732         default:
6733                 /* Not supported. */
6734                 return;
6735         }
6736
6737         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6738         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6739         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6740
6741         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6742         adapter->systime_tc.cc_shift = shift;
6743         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6744
6745         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6746         adapter->rx_tstamp_tc.cc_shift = shift;
6747         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6748
6749         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6750         adapter->tx_tstamp_tc.cc_shift = shift;
6751         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6752 }
6753
6754 static int
6755 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6756 {
6757         struct ixgbe_adapter *adapter =
6758                         (struct ixgbe_adapter *)dev->data->dev_private;
6759
6760         adapter->systime_tc.nsec += delta;
6761         adapter->rx_tstamp_tc.nsec += delta;
6762         adapter->tx_tstamp_tc.nsec += delta;
6763
6764         return 0;
6765 }
6766
6767 static int
6768 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6769 {
6770         uint64_t ns;
6771         struct ixgbe_adapter *adapter =
6772                         (struct ixgbe_adapter *)dev->data->dev_private;
6773
6774         ns = rte_timespec_to_ns(ts);
6775         /* Set the timecounters to a new value. */
6776         adapter->systime_tc.nsec = ns;
6777         adapter->rx_tstamp_tc.nsec = ns;
6778         adapter->tx_tstamp_tc.nsec = ns;
6779
6780         return 0;
6781 }
6782
6783 static int
6784 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6785 {
6786         uint64_t ns, systime_cycles;
6787         struct ixgbe_adapter *adapter =
6788                         (struct ixgbe_adapter *)dev->data->dev_private;
6789
6790         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6791         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6792         *ts = rte_ns_to_timespec(ns);
6793
6794         return 0;
6795 }
6796
6797 static int
6798 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6799 {
6800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6801         uint32_t tsync_ctl;
6802         uint32_t tsauxc;
6803
6804         /* Stop the timesync system time. */
6805         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6806         /* Reset the timesync system time value. */
6807         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6808         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6809
6810         /* Enable system time for platforms where it isn't on by default. */
6811         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6812         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6813         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6814
6815         ixgbe_start_timecounters(dev);
6816
6817         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6818         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6819                         (ETHER_TYPE_1588 |
6820                          IXGBE_ETQF_FILTER_EN |
6821                          IXGBE_ETQF_1588));
6822
6823         /* Enable timestamping of received PTP packets. */
6824         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6825         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6826         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6827
6828         /* Enable timestamping of transmitted PTP packets. */
6829         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6830         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6831         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6832
6833         IXGBE_WRITE_FLUSH(hw);
6834
6835         return 0;
6836 }
6837
6838 static int
6839 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6840 {
6841         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6842         uint32_t tsync_ctl;
6843
6844         /* Disable timestamping of transmitted PTP packets. */
6845         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6846         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6847         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6848
6849         /* Disable timestamping of received PTP packets. */
6850         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6851         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6852         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6853
6854         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6855         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6856
6857         /* Stop incrementating the System Time registers. */
6858         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6859
6860         return 0;
6861 }
6862
6863 static int
6864 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6865                                  struct timespec *timestamp,
6866                                  uint32_t flags __rte_unused)
6867 {
6868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6869         struct ixgbe_adapter *adapter =
6870                 (struct ixgbe_adapter *)dev->data->dev_private;
6871         uint32_t tsync_rxctl;
6872         uint64_t rx_tstamp_cycles;
6873         uint64_t ns;
6874
6875         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6876         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6877                 return -EINVAL;
6878
6879         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6880         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6881         *timestamp = rte_ns_to_timespec(ns);
6882
6883         return  0;
6884 }
6885
6886 static int
6887 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6888                                  struct timespec *timestamp)
6889 {
6890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6891         struct ixgbe_adapter *adapter =
6892                 (struct ixgbe_adapter *)dev->data->dev_private;
6893         uint32_t tsync_txctl;
6894         uint64_t tx_tstamp_cycles;
6895         uint64_t ns;
6896
6897         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6898         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6899                 return -EINVAL;
6900
6901         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6902         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6903         *timestamp = rte_ns_to_timespec(ns);
6904
6905         return 0;
6906 }
6907
6908 static int
6909 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6910 {
6911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6912         int count = 0;
6913         int g_ind = 0;
6914         const struct reg_info *reg_group;
6915         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6916                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6917
6918         while ((reg_group = reg_set[g_ind++]))
6919                 count += ixgbe_regs_group_count(reg_group);
6920
6921         return count;
6922 }
6923
6924 static int
6925 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6926 {
6927         int count = 0;
6928         int g_ind = 0;
6929         const struct reg_info *reg_group;
6930
6931         while ((reg_group = ixgbevf_regs[g_ind++]))
6932                 count += ixgbe_regs_group_count(reg_group);
6933
6934         return count;
6935 }
6936
6937 static int
6938 ixgbe_get_regs(struct rte_eth_dev *dev,
6939               struct rte_dev_reg_info *regs)
6940 {
6941         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6942         uint32_t *data = regs->data;
6943         int g_ind = 0;
6944         int count = 0;
6945         const struct reg_info *reg_group;
6946         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6947                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6948
6949         if (data == NULL) {
6950                 regs->length = ixgbe_get_reg_length(dev);
6951                 regs->width = sizeof(uint32_t);
6952                 return 0;
6953         }
6954
6955         /* Support only full register dump */
6956         if ((regs->length == 0) ||
6957             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6958                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6959                         hw->device_id;
6960                 while ((reg_group = reg_set[g_ind++]))
6961                         count += ixgbe_read_regs_group(dev, &data[count],
6962                                 reg_group);
6963                 return 0;
6964         }
6965
6966         return -ENOTSUP;
6967 }
6968
6969 static int
6970 ixgbevf_get_regs(struct rte_eth_dev *dev,
6971                 struct rte_dev_reg_info *regs)
6972 {
6973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6974         uint32_t *data = regs->data;
6975         int g_ind = 0;
6976         int count = 0;
6977         const struct reg_info *reg_group;
6978
6979         if (data == NULL) {
6980                 regs->length = ixgbevf_get_reg_length(dev);
6981                 regs->width = sizeof(uint32_t);
6982                 return 0;
6983         }
6984
6985         /* Support only full register dump */
6986         if ((regs->length == 0) ||
6987             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6988                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6989                         hw->device_id;
6990                 while ((reg_group = ixgbevf_regs[g_ind++]))
6991                         count += ixgbe_read_regs_group(dev, &data[count],
6992                                                       reg_group);
6993                 return 0;
6994         }
6995
6996         return -ENOTSUP;
6997 }
6998
6999 static int
7000 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7001 {
7002         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7003
7004         /* Return unit is byte count */
7005         return hw->eeprom.word_size * 2;
7006 }
7007
7008 static int
7009 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7010                 struct rte_dev_eeprom_info *in_eeprom)
7011 {
7012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7013         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7014         uint16_t *data = in_eeprom->data;
7015         int first, length;
7016
7017         first = in_eeprom->offset >> 1;
7018         length = in_eeprom->length >> 1;
7019         if ((first > hw->eeprom.word_size) ||
7020             ((first + length) > hw->eeprom.word_size))
7021                 return -EINVAL;
7022
7023         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7024
7025         return eeprom->ops.read_buffer(hw, first, length, data);
7026 }
7027
7028 static int
7029 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7030                 struct rte_dev_eeprom_info *in_eeprom)
7031 {
7032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7033         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7034         uint16_t *data = in_eeprom->data;
7035         int first, length;
7036
7037         first = in_eeprom->offset >> 1;
7038         length = in_eeprom->length >> 1;
7039         if ((first > hw->eeprom.word_size) ||
7040             ((first + length) > hw->eeprom.word_size))
7041                 return -EINVAL;
7042
7043         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7044
7045         return eeprom->ops.write_buffer(hw,  first, length, data);
7046 }
7047
7048 uint16_t
7049 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7050         switch (mac_type) {
7051         case ixgbe_mac_X550:
7052         case ixgbe_mac_X550EM_x:
7053         case ixgbe_mac_X550EM_a:
7054                 return ETH_RSS_RETA_SIZE_512;
7055         case ixgbe_mac_X550_vf:
7056         case ixgbe_mac_X550EM_x_vf:
7057         case ixgbe_mac_X550EM_a_vf:
7058                 return ETH_RSS_RETA_SIZE_64;
7059         default:
7060                 return ETH_RSS_RETA_SIZE_128;
7061         }
7062 }
7063
7064 uint32_t
7065 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7066         switch (mac_type) {
7067         case ixgbe_mac_X550:
7068         case ixgbe_mac_X550EM_x:
7069         case ixgbe_mac_X550EM_a:
7070                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7071                         return IXGBE_RETA(reta_idx >> 2);
7072                 else
7073                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7074         case ixgbe_mac_X550_vf:
7075         case ixgbe_mac_X550EM_x_vf:
7076         case ixgbe_mac_X550EM_a_vf:
7077                 return IXGBE_VFRETA(reta_idx >> 2);
7078         default:
7079                 return IXGBE_RETA(reta_idx >> 2);
7080         }
7081 }
7082
7083 uint32_t
7084 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7085         switch (mac_type) {
7086         case ixgbe_mac_X550_vf:
7087         case ixgbe_mac_X550EM_x_vf:
7088         case ixgbe_mac_X550EM_a_vf:
7089                 return IXGBE_VFMRQC;
7090         default:
7091                 return IXGBE_MRQC;
7092         }
7093 }
7094
7095 uint32_t
7096 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7097         switch (mac_type) {
7098         case ixgbe_mac_X550_vf:
7099         case ixgbe_mac_X550EM_x_vf:
7100         case ixgbe_mac_X550EM_a_vf:
7101                 return IXGBE_VFRSSRK(i);
7102         default:
7103                 return IXGBE_RSSRK(i);
7104         }
7105 }
7106
7107 bool
7108 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7109         switch (mac_type) {
7110         case ixgbe_mac_82599_vf:
7111         case ixgbe_mac_X540_vf:
7112                 return 0;
7113         default:
7114                 return 1;
7115         }
7116 }
7117
7118 static int
7119 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7120                         struct rte_eth_dcb_info *dcb_info)
7121 {
7122         struct ixgbe_dcb_config *dcb_config =
7123                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7124         struct ixgbe_dcb_tc_config *tc;
7125         uint8_t i, j;
7126
7127         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7128                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7129         else
7130                 dcb_info->nb_tcs = 1;
7131
7132         if (dcb_config->vt_mode) { /* vt is enabled*/
7133                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7134                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7135                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7136                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7137                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7138                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7139                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7140                                                 i * dcb_info->nb_tcs + j;
7141                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7142                                 dcb_info->tc_queue.tc_txq[i][j].base =
7143                                                 i * dcb_info->nb_tcs + j;
7144                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7145                         }
7146                 }
7147         } else { /* vt is disabled*/
7148                 struct rte_eth_dcb_rx_conf *rx_conf =
7149                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7150                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7151                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7152                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7153                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7154                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7155                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7156                         }
7157                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7158                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7159                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7160                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7161                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7162                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7163                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7164                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7165                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7166                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7167                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7168                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7169                         }
7170                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7171                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7172                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7173                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7174                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7175                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7176                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7177                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7178                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7179                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7180                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7181                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7182                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7183                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7184                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7185                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7186                 }
7187         }
7188         for (i = 0; i < dcb_info->nb_tcs; i++) {
7189                 tc = &dcb_config->tc_config[i];
7190                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7191         }
7192         return 0;
7193 }
7194
7195 /* Update e-tag ether type */
7196 static int
7197 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7198                             uint16_t ether_type)
7199 {
7200         uint32_t etag_etype;
7201
7202         if (hw->mac.type != ixgbe_mac_X550 &&
7203             hw->mac.type != ixgbe_mac_X550EM_x &&
7204             hw->mac.type != ixgbe_mac_X550EM_a) {
7205                 return -ENOTSUP;
7206         }
7207
7208         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7209         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7210         etag_etype |= ether_type;
7211         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7212         IXGBE_WRITE_FLUSH(hw);
7213
7214         return 0;
7215 }
7216
7217 /* Config l2 tunnel ether type */
7218 static int
7219 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7220                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7221 {
7222         int ret = 0;
7223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7224         struct ixgbe_l2_tn_info *l2_tn_info =
7225                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7226
7227         if (l2_tunnel == NULL)
7228                 return -EINVAL;
7229
7230         switch (l2_tunnel->l2_tunnel_type) {
7231         case RTE_L2_TUNNEL_TYPE_E_TAG:
7232                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7233                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7234                 break;
7235         default:
7236                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7237                 ret = -EINVAL;
7238                 break;
7239         }
7240
7241         return ret;
7242 }
7243
7244 /* Enable e-tag tunnel */
7245 static int
7246 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7247 {
7248         uint32_t etag_etype;
7249
7250         if (hw->mac.type != ixgbe_mac_X550 &&
7251             hw->mac.type != ixgbe_mac_X550EM_x &&
7252             hw->mac.type != ixgbe_mac_X550EM_a) {
7253                 return -ENOTSUP;
7254         }
7255
7256         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7257         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7258         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7259         IXGBE_WRITE_FLUSH(hw);
7260
7261         return 0;
7262 }
7263
7264 /* Enable l2 tunnel */
7265 static int
7266 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7267                            enum rte_eth_tunnel_type l2_tunnel_type)
7268 {
7269         int ret = 0;
7270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7271         struct ixgbe_l2_tn_info *l2_tn_info =
7272                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7273
7274         switch (l2_tunnel_type) {
7275         case RTE_L2_TUNNEL_TYPE_E_TAG:
7276                 l2_tn_info->e_tag_en = TRUE;
7277                 ret = ixgbe_e_tag_enable(hw);
7278                 break;
7279         default:
7280                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7281                 ret = -EINVAL;
7282                 break;
7283         }
7284
7285         return ret;
7286 }
7287
7288 /* Disable e-tag tunnel */
7289 static int
7290 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7291 {
7292         uint32_t etag_etype;
7293
7294         if (hw->mac.type != ixgbe_mac_X550 &&
7295             hw->mac.type != ixgbe_mac_X550EM_x &&
7296             hw->mac.type != ixgbe_mac_X550EM_a) {
7297                 return -ENOTSUP;
7298         }
7299
7300         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7301         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7302         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7303         IXGBE_WRITE_FLUSH(hw);
7304
7305         return 0;
7306 }
7307
7308 /* Disable l2 tunnel */
7309 static int
7310 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7311                             enum rte_eth_tunnel_type l2_tunnel_type)
7312 {
7313         int ret = 0;
7314         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7315         struct ixgbe_l2_tn_info *l2_tn_info =
7316                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7317
7318         switch (l2_tunnel_type) {
7319         case RTE_L2_TUNNEL_TYPE_E_TAG:
7320                 l2_tn_info->e_tag_en = FALSE;
7321                 ret = ixgbe_e_tag_disable(hw);
7322                 break;
7323         default:
7324                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7325                 ret = -EINVAL;
7326                 break;
7327         }
7328
7329         return ret;
7330 }
7331
7332 static int
7333 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7334                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7335 {
7336         int ret = 0;
7337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7338         uint32_t i, rar_entries;
7339         uint32_t rar_low, rar_high;
7340
7341         if (hw->mac.type != ixgbe_mac_X550 &&
7342             hw->mac.type != ixgbe_mac_X550EM_x &&
7343             hw->mac.type != ixgbe_mac_X550EM_a) {
7344                 return -ENOTSUP;
7345         }
7346
7347         rar_entries = ixgbe_get_num_rx_addrs(hw);
7348
7349         for (i = 1; i < rar_entries; i++) {
7350                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7351                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7352                 if ((rar_high & IXGBE_RAH_AV) &&
7353                     (rar_high & IXGBE_RAH_ADTYPE) &&
7354                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7355                      l2_tunnel->tunnel_id)) {
7356                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7357                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7358
7359                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7360
7361                         return ret;
7362                 }
7363         }
7364
7365         return ret;
7366 }
7367
7368 static int
7369 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7370                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7371 {
7372         int ret = 0;
7373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7374         uint32_t i, rar_entries;
7375         uint32_t rar_low, rar_high;
7376
7377         if (hw->mac.type != ixgbe_mac_X550 &&
7378             hw->mac.type != ixgbe_mac_X550EM_x &&
7379             hw->mac.type != ixgbe_mac_X550EM_a) {
7380                 return -ENOTSUP;
7381         }
7382
7383         /* One entry for one tunnel. Try to remove potential existing entry. */
7384         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7385
7386         rar_entries = ixgbe_get_num_rx_addrs(hw);
7387
7388         for (i = 1; i < rar_entries; i++) {
7389                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7390                 if (rar_high & IXGBE_RAH_AV) {
7391                         continue;
7392                 } else {
7393                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7394                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7395                         rar_low = l2_tunnel->tunnel_id;
7396
7397                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7398                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7399
7400                         return ret;
7401                 }
7402         }
7403
7404         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7405                      " Please remove a rule before adding a new one.");
7406         return -EINVAL;
7407 }
7408
7409 static inline struct ixgbe_l2_tn_filter *
7410 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7411                           struct ixgbe_l2_tn_key *key)
7412 {
7413         int ret;
7414
7415         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7416         if (ret < 0)
7417                 return NULL;
7418
7419         return l2_tn_info->hash_map[ret];
7420 }
7421
7422 static inline int
7423 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7424                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7425 {
7426         int ret;
7427
7428         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7429                                &l2_tn_filter->key);
7430
7431         if (ret < 0) {
7432                 PMD_DRV_LOG(ERR,
7433                             "Failed to insert L2 tunnel filter"
7434                             " to hash table %d!",
7435                             ret);
7436                 return ret;
7437         }
7438
7439         l2_tn_info->hash_map[ret] = l2_tn_filter;
7440
7441         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7442
7443         return 0;
7444 }
7445
7446 static inline int
7447 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7448                           struct ixgbe_l2_tn_key *key)
7449 {
7450         int ret;
7451         struct ixgbe_l2_tn_filter *l2_tn_filter;
7452
7453         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7454
7455         if (ret < 0) {
7456                 PMD_DRV_LOG(ERR,
7457                             "No such L2 tunnel filter to delete %d!",
7458                             ret);
7459                 return ret;
7460         }
7461
7462         l2_tn_filter = l2_tn_info->hash_map[ret];
7463         l2_tn_info->hash_map[ret] = NULL;
7464
7465         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7466         rte_free(l2_tn_filter);
7467
7468         return 0;
7469 }
7470
7471 /* Add l2 tunnel filter */
7472 int
7473 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7474                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7475                                bool restore)
7476 {
7477         int ret;
7478         struct ixgbe_l2_tn_info *l2_tn_info =
7479                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7480         struct ixgbe_l2_tn_key key;
7481         struct ixgbe_l2_tn_filter *node;
7482
7483         if (!restore) {
7484                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7485                 key.tn_id = l2_tunnel->tunnel_id;
7486
7487                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7488
7489                 if (node) {
7490                         PMD_DRV_LOG(ERR,
7491                                     "The L2 tunnel filter already exists!");
7492                         return -EINVAL;
7493                 }
7494
7495                 node = rte_zmalloc("ixgbe_l2_tn",
7496                                    sizeof(struct ixgbe_l2_tn_filter),
7497                                    0);
7498                 if (!node)
7499                         return -ENOMEM;
7500
7501                 (void)rte_memcpy(&node->key,
7502                                  &key,
7503                                  sizeof(struct ixgbe_l2_tn_key));
7504                 node->pool = l2_tunnel->pool;
7505                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7506                 if (ret < 0) {
7507                         rte_free(node);
7508                         return ret;
7509                 }
7510         }
7511
7512         switch (l2_tunnel->l2_tunnel_type) {
7513         case RTE_L2_TUNNEL_TYPE_E_TAG:
7514                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7515                 break;
7516         default:
7517                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7518                 ret = -EINVAL;
7519                 break;
7520         }
7521
7522         if ((!restore) && (ret < 0))
7523                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7524
7525         return ret;
7526 }
7527
7528 /* Delete l2 tunnel filter */
7529 int
7530 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7531                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7532 {
7533         int ret;
7534         struct ixgbe_l2_tn_info *l2_tn_info =
7535                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7536         struct ixgbe_l2_tn_key key;
7537
7538         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7539         key.tn_id = l2_tunnel->tunnel_id;
7540         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7541         if (ret < 0)
7542                 return ret;
7543
7544         switch (l2_tunnel->l2_tunnel_type) {
7545         case RTE_L2_TUNNEL_TYPE_E_TAG:
7546                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7547                 break;
7548         default:
7549                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7550                 ret = -EINVAL;
7551                 break;
7552         }
7553
7554         return ret;
7555 }
7556
7557 /**
7558  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7559  * @dev: pointer to rte_eth_dev structure
7560  * @filter_op:operation will be taken.
7561  * @arg: a pointer to specific structure corresponding to the filter_op
7562  */
7563 static int
7564 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7565                                   enum rte_filter_op filter_op,
7566                                   void *arg)
7567 {
7568         int ret;
7569
7570         if (filter_op == RTE_ETH_FILTER_NOP)
7571                 return 0;
7572
7573         if (arg == NULL) {
7574                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7575                             filter_op);
7576                 return -EINVAL;
7577         }
7578
7579         switch (filter_op) {
7580         case RTE_ETH_FILTER_ADD:
7581                 ret = ixgbe_dev_l2_tunnel_filter_add
7582                         (dev,
7583                          (struct rte_eth_l2_tunnel_conf *)arg,
7584                          FALSE);
7585                 break;
7586         case RTE_ETH_FILTER_DELETE:
7587                 ret = ixgbe_dev_l2_tunnel_filter_del
7588                         (dev,
7589                          (struct rte_eth_l2_tunnel_conf *)arg);
7590                 break;
7591         default:
7592                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7593                 ret = -EINVAL;
7594                 break;
7595         }
7596         return ret;
7597 }
7598
7599 static int
7600 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7601 {
7602         int ret = 0;
7603         uint32_t ctrl;
7604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7605
7606         if (hw->mac.type != ixgbe_mac_X550 &&
7607             hw->mac.type != ixgbe_mac_X550EM_x &&
7608             hw->mac.type != ixgbe_mac_X550EM_a) {
7609                 return -ENOTSUP;
7610         }
7611
7612         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7613         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7614         if (en)
7615                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7616         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7617
7618         return ret;
7619 }
7620
7621 /* Enable l2 tunnel forwarding */
7622 static int
7623 ixgbe_dev_l2_tunnel_forwarding_enable
7624         (struct rte_eth_dev *dev,
7625          enum rte_eth_tunnel_type l2_tunnel_type)
7626 {
7627         struct ixgbe_l2_tn_info *l2_tn_info =
7628                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7629         int ret = 0;
7630
7631         switch (l2_tunnel_type) {
7632         case RTE_L2_TUNNEL_TYPE_E_TAG:
7633                 l2_tn_info->e_tag_fwd_en = TRUE;
7634                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7635                 break;
7636         default:
7637                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7638                 ret = -EINVAL;
7639                 break;
7640         }
7641
7642         return ret;
7643 }
7644
7645 /* Disable l2 tunnel forwarding */
7646 static int
7647 ixgbe_dev_l2_tunnel_forwarding_disable
7648         (struct rte_eth_dev *dev,
7649          enum rte_eth_tunnel_type l2_tunnel_type)
7650 {
7651         struct ixgbe_l2_tn_info *l2_tn_info =
7652                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7653         int ret = 0;
7654
7655         switch (l2_tunnel_type) {
7656         case RTE_L2_TUNNEL_TYPE_E_TAG:
7657                 l2_tn_info->e_tag_fwd_en = FALSE;
7658                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7659                 break;
7660         default:
7661                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7662                 ret = -EINVAL;
7663                 break;
7664         }
7665
7666         return ret;
7667 }
7668
7669 static int
7670 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7671                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7672                              bool en)
7673 {
7674         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7675         int ret = 0;
7676         uint32_t vmtir, vmvir;
7677         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7678
7679         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7680                 PMD_DRV_LOG(ERR,
7681                             "VF id %u should be less than %u",
7682                             l2_tunnel->vf_id,
7683                             pci_dev->max_vfs);
7684                 return -EINVAL;
7685         }
7686
7687         if (hw->mac.type != ixgbe_mac_X550 &&
7688             hw->mac.type != ixgbe_mac_X550EM_x &&
7689             hw->mac.type != ixgbe_mac_X550EM_a) {
7690                 return -ENOTSUP;
7691         }
7692
7693         if (en)
7694                 vmtir = l2_tunnel->tunnel_id;
7695         else
7696                 vmtir = 0;
7697
7698         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7699
7700         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7701         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7702         if (en)
7703                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7704         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7705
7706         return ret;
7707 }
7708
7709 /* Enable l2 tunnel tag insertion */
7710 static int
7711 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7712                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7713 {
7714         int ret = 0;
7715
7716         switch (l2_tunnel->l2_tunnel_type) {
7717         case RTE_L2_TUNNEL_TYPE_E_TAG:
7718                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7719                 break;
7720         default:
7721                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7722                 ret = -EINVAL;
7723                 break;
7724         }
7725
7726         return ret;
7727 }
7728
7729 /* Disable l2 tunnel tag insertion */
7730 static int
7731 ixgbe_dev_l2_tunnel_insertion_disable
7732         (struct rte_eth_dev *dev,
7733          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7734 {
7735         int ret = 0;
7736
7737         switch (l2_tunnel->l2_tunnel_type) {
7738         case RTE_L2_TUNNEL_TYPE_E_TAG:
7739                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7740                 break;
7741         default:
7742                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7743                 ret = -EINVAL;
7744                 break;
7745         }
7746
7747         return ret;
7748 }
7749
7750 static int
7751 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7752                              bool en)
7753 {
7754         int ret = 0;
7755         uint32_t qde;
7756         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7757
7758         if (hw->mac.type != ixgbe_mac_X550 &&
7759             hw->mac.type != ixgbe_mac_X550EM_x &&
7760             hw->mac.type != ixgbe_mac_X550EM_a) {
7761                 return -ENOTSUP;
7762         }
7763
7764         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7765         if (en)
7766                 qde |= IXGBE_QDE_STRIP_TAG;
7767         else
7768                 qde &= ~IXGBE_QDE_STRIP_TAG;
7769         qde &= ~IXGBE_QDE_READ;
7770         qde |= IXGBE_QDE_WRITE;
7771         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7772
7773         return ret;
7774 }
7775
7776 /* Enable l2 tunnel tag stripping */
7777 static int
7778 ixgbe_dev_l2_tunnel_stripping_enable
7779         (struct rte_eth_dev *dev,
7780          enum rte_eth_tunnel_type l2_tunnel_type)
7781 {
7782         int ret = 0;
7783
7784         switch (l2_tunnel_type) {
7785         case RTE_L2_TUNNEL_TYPE_E_TAG:
7786                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7787                 break;
7788         default:
7789                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7790                 ret = -EINVAL;
7791                 break;
7792         }
7793
7794         return ret;
7795 }
7796
7797 /* Disable l2 tunnel tag stripping */
7798 static int
7799 ixgbe_dev_l2_tunnel_stripping_disable
7800         (struct rte_eth_dev *dev,
7801          enum rte_eth_tunnel_type l2_tunnel_type)
7802 {
7803         int ret = 0;
7804
7805         switch (l2_tunnel_type) {
7806         case RTE_L2_TUNNEL_TYPE_E_TAG:
7807                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7808                 break;
7809         default:
7810                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7811                 ret = -EINVAL;
7812                 break;
7813         }
7814
7815         return ret;
7816 }
7817
7818 /* Enable/disable l2 tunnel offload functions */
7819 static int
7820 ixgbe_dev_l2_tunnel_offload_set
7821         (struct rte_eth_dev *dev,
7822          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7823          uint32_t mask,
7824          uint8_t en)
7825 {
7826         int ret = 0;
7827
7828         if (l2_tunnel == NULL)
7829                 return -EINVAL;
7830
7831         ret = -EINVAL;
7832         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7833                 if (en)
7834                         ret = ixgbe_dev_l2_tunnel_enable(
7835                                 dev,
7836                                 l2_tunnel->l2_tunnel_type);
7837                 else
7838                         ret = ixgbe_dev_l2_tunnel_disable(
7839                                 dev,
7840                                 l2_tunnel->l2_tunnel_type);
7841         }
7842
7843         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7844                 if (en)
7845                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7846                                 dev,
7847                                 l2_tunnel);
7848                 else
7849                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7850                                 dev,
7851                                 l2_tunnel);
7852         }
7853
7854         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7855                 if (en)
7856                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7857                                 dev,
7858                                 l2_tunnel->l2_tunnel_type);
7859                 else
7860                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7861                                 dev,
7862                                 l2_tunnel->l2_tunnel_type);
7863         }
7864
7865         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7866                 if (en)
7867                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7868                                 dev,
7869                                 l2_tunnel->l2_tunnel_type);
7870                 else
7871                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7872                                 dev,
7873                                 l2_tunnel->l2_tunnel_type);
7874         }
7875
7876         return ret;
7877 }
7878
7879 static int
7880 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7881                         uint16_t port)
7882 {
7883         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7884         IXGBE_WRITE_FLUSH(hw);
7885
7886         return 0;
7887 }
7888
7889 /* There's only one register for VxLAN UDP port.
7890  * So, we cannot add several ports. Will update it.
7891  */
7892 static int
7893 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7894                      uint16_t port)
7895 {
7896         if (port == 0) {
7897                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7898                 return -EINVAL;
7899         }
7900
7901         return ixgbe_update_vxlan_port(hw, port);
7902 }
7903
7904 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7905  * UDP port, it must have a value.
7906  * So, will reset it to the original value 0.
7907  */
7908 static int
7909 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7910                      uint16_t port)
7911 {
7912         uint16_t cur_port;
7913
7914         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7915
7916         if (cur_port != port) {
7917                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7918                 return -EINVAL;
7919         }
7920
7921         return ixgbe_update_vxlan_port(hw, 0);
7922 }
7923
7924 /* Add UDP tunneling port */
7925 static int
7926 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7927                               struct rte_eth_udp_tunnel *udp_tunnel)
7928 {
7929         int ret = 0;
7930         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7931
7932         if (hw->mac.type != ixgbe_mac_X550 &&
7933             hw->mac.type != ixgbe_mac_X550EM_x &&
7934             hw->mac.type != ixgbe_mac_X550EM_a) {
7935                 return -ENOTSUP;
7936         }
7937
7938         if (udp_tunnel == NULL)
7939                 return -EINVAL;
7940
7941         switch (udp_tunnel->prot_type) {
7942         case RTE_TUNNEL_TYPE_VXLAN:
7943                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7944                 break;
7945
7946         case RTE_TUNNEL_TYPE_GENEVE:
7947         case RTE_TUNNEL_TYPE_TEREDO:
7948                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7949                 ret = -EINVAL;
7950                 break;
7951
7952         default:
7953                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7954                 ret = -EINVAL;
7955                 break;
7956         }
7957
7958         return ret;
7959 }
7960
7961 /* Remove UDP tunneling port */
7962 static int
7963 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7964                               struct rte_eth_udp_tunnel *udp_tunnel)
7965 {
7966         int ret = 0;
7967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7968
7969         if (hw->mac.type != ixgbe_mac_X550 &&
7970             hw->mac.type != ixgbe_mac_X550EM_x &&
7971             hw->mac.type != ixgbe_mac_X550EM_a) {
7972                 return -ENOTSUP;
7973         }
7974
7975         if (udp_tunnel == NULL)
7976                 return -EINVAL;
7977
7978         switch (udp_tunnel->prot_type) {
7979         case RTE_TUNNEL_TYPE_VXLAN:
7980                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7981                 break;
7982         case RTE_TUNNEL_TYPE_GENEVE:
7983         case RTE_TUNNEL_TYPE_TEREDO:
7984                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7985                 ret = -EINVAL;
7986                 break;
7987         default:
7988                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7989                 ret = -EINVAL;
7990                 break;
7991         }
7992
7993         return ret;
7994 }
7995
7996 static void
7997 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7998 {
7999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8000
8001         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8002 }
8003
8004 static void
8005 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8006 {
8007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8008
8009         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8010 }
8011
8012 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8013 {
8014         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8015         u32 in_msg = 0;
8016
8017         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8018                 return;
8019
8020         /* PF reset VF event */
8021         if (in_msg == IXGBE_PF_CONTROL_MSG)
8022                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8023                                               NULL, NULL);
8024 }
8025
8026 static int
8027 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8028 {
8029         uint32_t eicr;
8030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8031         struct ixgbe_interrupt *intr =
8032                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8033         ixgbevf_intr_disable(hw);
8034
8035         /* read-on-clear nic registers here */
8036         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8037         intr->flags = 0;
8038
8039         /* only one misc vector supported - mailbox */
8040         eicr &= IXGBE_VTEICR_MASK;
8041         if (eicr == IXGBE_MISC_VEC_ID)
8042                 intr->flags |= IXGBE_FLAG_MAILBOX;
8043
8044         return 0;
8045 }
8046
8047 static int
8048 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8049 {
8050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8051         struct ixgbe_interrupt *intr =
8052                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8053
8054         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8055                 ixgbevf_mbx_process(dev);
8056                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8057         }
8058
8059         ixgbevf_intr_enable(hw);
8060
8061         return 0;
8062 }
8063
8064 static void
8065 ixgbevf_dev_interrupt_handler(void *param)
8066 {
8067         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8068
8069         ixgbevf_dev_interrupt_get_status(dev);
8070         ixgbevf_dev_interrupt_action(dev);
8071 }
8072
8073 /**
8074  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8075  *  @hw: pointer to hardware structure
8076  *
8077  *  Stops the transmit data path and waits for the HW to internally empty
8078  *  the Tx security block
8079  **/
8080 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8081 {
8082 #define IXGBE_MAX_SECTX_POLL 40
8083
8084         int i;
8085         int sectxreg;
8086
8087         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8088         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8089         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8090         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8091                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8092                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8093                         break;
8094                 /* Use interrupt-safe sleep just in case */
8095                 usec_delay(1000);
8096         }
8097
8098         /* For informational purposes only */
8099         if (i >= IXGBE_MAX_SECTX_POLL)
8100                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8101                          "path fully disabled.  Continuing with init.");
8102
8103         return IXGBE_SUCCESS;
8104 }
8105
8106 /**
8107  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8108  *  @hw: pointer to hardware structure
8109  *
8110  *  Enables the transmit data path.
8111  **/
8112 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8113 {
8114         uint32_t sectxreg;
8115
8116         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8117         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8118         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8119         IXGBE_WRITE_FLUSH(hw);
8120
8121         return IXGBE_SUCCESS;
8122 }
8123
8124 /* restore n-tuple filter */
8125 static inline void
8126 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8127 {
8128         struct ixgbe_filter_info *filter_info =
8129                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8130         struct ixgbe_5tuple_filter *node;
8131
8132         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8133                 ixgbe_inject_5tuple_filter(dev, node);
8134         }
8135 }
8136
8137 /* restore ethernet type filter */
8138 static inline void
8139 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8140 {
8141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8142         struct ixgbe_filter_info *filter_info =
8143                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8144         int i;
8145
8146         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8147                 if (filter_info->ethertype_mask & (1 << i)) {
8148                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8149                                         filter_info->ethertype_filters[i].etqf);
8150                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8151                                         filter_info->ethertype_filters[i].etqs);
8152                         IXGBE_WRITE_FLUSH(hw);
8153                 }
8154         }
8155 }
8156
8157 /* restore SYN filter */
8158 static inline void
8159 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8160 {
8161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8162         struct ixgbe_filter_info *filter_info =
8163                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8164         uint32_t synqf;
8165
8166         synqf = filter_info->syn_info;
8167
8168         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8169                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8170                 IXGBE_WRITE_FLUSH(hw);
8171         }
8172 }
8173
8174 /* restore L2 tunnel filter */
8175 static inline void
8176 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8177 {
8178         struct ixgbe_l2_tn_info *l2_tn_info =
8179                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8180         struct ixgbe_l2_tn_filter *node;
8181         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8182
8183         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8184                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8185                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8186                 l2_tn_conf.pool           = node->pool;
8187                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8188         }
8189 }
8190
8191 static int
8192 ixgbe_filter_restore(struct rte_eth_dev *dev)
8193 {
8194         ixgbe_ntuple_filter_restore(dev);
8195         ixgbe_ethertype_filter_restore(dev);
8196         ixgbe_syn_filter_restore(dev);
8197         ixgbe_fdir_filter_restore(dev);
8198         ixgbe_l2_tn_filter_restore(dev);
8199
8200         return 0;
8201 }
8202
8203 static void
8204 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8205 {
8206         struct ixgbe_l2_tn_info *l2_tn_info =
8207                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8208         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8209
8210         if (l2_tn_info->e_tag_en)
8211                 (void)ixgbe_e_tag_enable(hw);
8212
8213         if (l2_tn_info->e_tag_fwd_en)
8214                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8215
8216         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8217 }
8218
8219 /* remove all the n-tuple filters */
8220 void
8221 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8222 {
8223         struct ixgbe_filter_info *filter_info =
8224                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8225         struct ixgbe_5tuple_filter *p_5tuple;
8226
8227         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8228                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8229 }
8230
8231 /* remove all the ether type filters */
8232 void
8233 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8234 {
8235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8236         struct ixgbe_filter_info *filter_info =
8237                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8238         int i;
8239
8240         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8241                 if (filter_info->ethertype_mask & (1 << i) &&
8242                     !filter_info->ethertype_filters[i].conf) {
8243                         (void)ixgbe_ethertype_filter_remove(filter_info,
8244                                                             (uint8_t)i);
8245                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8246                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8247                         IXGBE_WRITE_FLUSH(hw);
8248                 }
8249         }
8250 }
8251
8252 /* remove the SYN filter */
8253 void
8254 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8255 {
8256         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8257         struct ixgbe_filter_info *filter_info =
8258                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8259
8260         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8261                 filter_info->syn_info = 0;
8262
8263                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8264                 IXGBE_WRITE_FLUSH(hw);
8265         }
8266 }
8267
8268 /* remove all the L2 tunnel filters */
8269 int
8270 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8271 {
8272         struct ixgbe_l2_tn_info *l2_tn_info =
8273                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8274         struct ixgbe_l2_tn_filter *l2_tn_filter;
8275         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8276         int ret = 0;
8277
8278         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8279                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8280                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8281                 l2_tn_conf.pool           = l2_tn_filter->pool;
8282                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8283                 if (ret < 0)
8284                         return ret;
8285         }
8286
8287         return 0;
8288 }
8289
8290 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8291 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8292 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8293 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8294 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8295 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");