drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <rte_ethdev.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIBRTE_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "ixgbe_regs.h"
  49
  50 /*
  51  * High threshold controlling when to start sending XOFF frames. Must be at
  52  * least 8 bytes less than receive packet buffer size. This value is in units
  53  * of 1024 bytes.
  54  */
  55 #define IXGBE_FC_HI    0x80
  56
  57 /*
  58  * Low threshold controlling when to start sending XON frames. This value is
  59  * in units of 1024 bytes.
  60  */
  61 #define IXGBE_FC_LO    0x40
  62
  63 /* Default minimum inter-interrupt interval for EITR configuration */
  64 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  65
  66 /* Timer value included in XOFF frames. */
  67 #define IXGBE_FC_PAUSE 0x680
  68
  69 /*Default value of Max Rx Queue*/
  70 #define IXGBE_MAX_RX_QUEUE_NUM 128
  71
  72 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  73 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  74 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  75
  76 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  77 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  78 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  79
  80 /*
  81  *  Default values for RX/TX configuration
  82  */
  83 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  84 #define IXGBE_DEFAULT_RX_PTHRESH      8
  85 #define IXGBE_DEFAULT_RX_HTHRESH      8
  86 #define IXGBE_DEFAULT_RX_WTHRESH      0
  87
  88 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  89 #define IXGBE_DEFAULT_TX_PTHRESH      32
  90 #define IXGBE_DEFAULT_TX_HTHRESH      0
  91 #define IXGBE_DEFAULT_TX_WTHRESH      0
  92 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  93
  94 /* Bit shift and mask */
  95 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  96 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  97 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  98 #define IXGBE_8_BIT_MASK   UINT8_MAX
  99
 100 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 101
 102 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 103
 104 #define IXGBE_HKEY_MAX_INDEX 10
 105
 106 /* Additional timesync values. */
 107 #define NSEC_PER_SEC             1000000000L
 108 #define IXGBE_INCVAL_10GB        0x66666666
 109 #define IXGBE_INCVAL_1GB         0x40000000
 110 #define IXGBE_INCVAL_100         0x50000000
 111 #define IXGBE_INCVAL_SHIFT_10GB  28
 112 #define IXGBE_INCVAL_SHIFT_1GB   24
 113 #define IXGBE_INCVAL_SHIFT_100   21
 114 #define IXGBE_INCVAL_SHIFT_82599 7
 115 #define IXGBE_INCPER_SHIFT_82599 24
 116
 117 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 118
 119 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 120 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 121 #define DEFAULT_ETAG_ETYPE                     0x893f
 122 #define IXGBE_ETAG_ETYPE                       0x00005084
 123 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 124 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 125 #define IXGBE_RAH_ADTYPE                       0x40000000
 126 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 127 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 128 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 129 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 130 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 131 #define IXGBE_VTEICR_MASK                      0x07
 132
 133 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 134 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 135
 136 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 137 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 143 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 144 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 147 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 153 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 155                                 int wait_to_complete);
 156 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 157                                 struct rte_eth_stats *stats);
 158 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_xstat *xstats, unsigned n);
 160 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 161                                   struct rte_eth_xstat *xstats, unsigned n);
 162 static int
 163 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 164                 uint64_t *values, unsigned int n);
 165 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 166 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 167 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 168         struct rte_eth_xstat_name *xstats_names,
 169         unsigned int size);
 170 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 171         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 172 static int ixgbe_dev_xstats_get_names_by_id(
 173         struct rte_eth_dev *dev,
 174         struct rte_eth_xstat_name *xstats_names,
 175         const uint64_t *ids,
 176         unsigned int limit);
 177 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 178                                              uint16_t queue_id,
 179                                              uint8_t stat_idx,
 180                                              uint8_t is_rx);
 181 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 182                                  size_t fw_size);
 183 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 184                                struct rte_eth_dev_info *dev_info);
 185 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 186 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 187                                  struct rte_eth_dev_info *dev_info);
 188 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 189
 190 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 191                 uint16_t vlan_id, int on);
 192 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 193                                enum rte_vlan_type vlan_type,
 194                                uint16_t tpid_id);
 195 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 196                 uint16_t queue, bool on);
 197 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 198                 int on);
 199 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 200 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 201 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 202 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 203 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 204
 205 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 206 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 207 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 208                                struct rte_eth_fc_conf *fc_conf);
 209 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 210                                struct rte_eth_fc_conf *fc_conf);
 211 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 212                 struct rte_eth_pfc_conf *pfc_conf);
 213 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 214                         struct rte_eth_rss_reta_entry64 *reta_conf,
 215                         uint16_t reta_size);
 216 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 217                         struct rte_eth_rss_reta_entry64 *reta_conf,
 218                         uint16_t reta_size);
 219 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 221 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 225                                       struct rte_intr_handle *handle);
 226 static void ixgbe_dev_interrupt_handler(void *param);
 227 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 228 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 229                          uint32_t index, uint32_t pool);
 230 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 231 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 232                                            struct ether_addr *mac_addr);
 233 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 234 static bool is_device_supported(struct rte_eth_dev *dev,
 235                                 struct rte_pci_driver *drv);
 236
 237 /* For Virtual Function support */
 238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 240 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 241 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 242 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 243                                    int wait_to_complete);
 244 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 245 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 246 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 247 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 248 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 249 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 250                 struct rte_eth_stats *stats);
 251 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 252 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 253                 uint16_t vlan_id, int on);
 254 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 255                 uint16_t queue, int on);
 256 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 257 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 258 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 259                                             uint16_t queue_id);
 260 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 261                                              uint16_t queue_id);
 262 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 263                                  uint8_t queue, uint8_t msix_vector);
 264 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 267
 268 /* For Eth VMDQ APIs support */
 269 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 270                 ether_addr * mac_addr, uint8_t on);
 271 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 272 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 273                 struct rte_eth_mirror_conf *mirror_conf,
 274                 uint8_t rule_id, uint8_t on);
 275 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 276                 uint8_t rule_id);
 277 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 278                                           uint16_t queue_id);
 279 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 280                                            uint16_t queue_id);
 281 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 282                                uint8_t queue, uint8_t msix_vector);
 283 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 284
 285 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 286                                 struct ether_addr *mac_addr,
 287                                 uint32_t index, uint32_t pool);
 288 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 289 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 290                                              struct ether_addr *mac_addr);
 291 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 292                         struct rte_eth_syn_filter *filter);
 293 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 294                         enum rte_filter_op filter_op,
 295                         void *arg);
 296 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 297                         struct ixgbe_5tuple_filter *filter);
 298 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 301                                 enum rte_filter_op filter_op,
 302                                 void *arg);
 303 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 304                         struct rte_eth_ntuple_filter *filter);
 305 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 306                                 enum rte_filter_op filter_op,
 307                                 void *arg);
 308 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 309                         struct rte_eth_ethertype_filter *filter);
 310 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 311                      enum rte_filter_type filter_type,
 312                      enum rte_filter_op filter_op,
 313                      void *arg);
 314 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 315
 316 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 317                                       struct ether_addr *mc_addr_set,
 318                                       uint32_t nb_mc_addr);
 319 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 320                                    struct rte_eth_dcb_info *dcb_info);
 321
 322 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 324                             struct rte_dev_reg_info *regs);
 325 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 326 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 327                                 struct rte_dev_eeprom_info *eeprom);
 328 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 329                                 struct rte_dev_eeprom_info *eeprom);
 330
 331 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 332 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 333                                 struct rte_dev_reg_info *regs);
 334
 335 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 338                                             struct timespec *timestamp,
 339                                             uint32_t flags);
 340 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 341                                             struct timespec *timestamp);
 342 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 343 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 344                                    struct timespec *timestamp);
 345 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 346                                    const struct timespec *timestamp);
 347 static void ixgbevf_dev_interrupt_handler(void *param);
 348
 349 static int ixgbe_dev_l2_tunnel_eth_type_conf
 350         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 351 static int ixgbe_dev_l2_tunnel_offload_set
 352         (struct rte_eth_dev *dev,
 353          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 354          uint32_t mask,
 355          uint8_t en);
 356 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 357                                              enum rte_filter_op filter_op,
 358                                              void *arg);
 359
 360 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 361                                          struct rte_eth_udp_tunnel *udp_tunnel);
 362 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 363                                          struct rte_eth_udp_tunnel *udp_tunnel);
 364 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 365 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 366
 367 /*
 368  * Define VF Stats MACRO for Non "cleared on read" register
 369  */
 370 #define UPDATE_VF_STAT(reg, last, cur)                          \
 371 {                                                               \
 372         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 373         cur += (latest - last) & UINT_MAX;                      \
 374         last = latest;                                          \
 375 }
 376
 377 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 378 {                                                                \
 379         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 380         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 381         u64 latest = ((new_msb << 32) | new_lsb);                \
 382         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 383         last = latest;                                           \
 384 }
 385
 386 #define IXGBE_SET_HWSTRIP(h, q) do {\
 387                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 388                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 389                 (h)->bitmap[idx] |= 1 << bit;\
 390         } while (0)
 391
 392 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 393                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 394                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 395                 (h)->bitmap[idx] &= ~(1 << bit);\
 396         } while (0)
 397
 398 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 399                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 400                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 401                 (r) = (h)->bitmap[idx] >> bit & 1;\
 402         } while (0)
 403
 404 int ixgbe_logtype_init;
 405 int ixgbe_logtype_driver;
 406
 407 /*
 408  * The set of PCI devices this driver supports
 409  */
 410 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 459 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 461 #endif
 462         { .vendor_id = 0, /* sentinel */ },
 463 };
 464
 465 /*
 466  * The set of PCI devices this driver supports (for 82599 VF)
 467  */
 468 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 479         { .vendor_id = 0, /* sentinel */ },
 480 };
 481
 482 static const struct rte_eth_desc_lim rx_desc_lim = {
 483         .nb_max = IXGBE_MAX_RING_DESC,
 484         .nb_min = IXGBE_MIN_RING_DESC,
 485         .nb_align = IXGBE_RXD_ALIGN,
 486 };
 487
 488 static const struct rte_eth_desc_lim tx_desc_lim = {
 489         .nb_max = IXGBE_MAX_RING_DESC,
 490         .nb_min = IXGBE_MIN_RING_DESC,
 491         .nb_align = IXGBE_TXD_ALIGN,
 492         .nb_seg_max = IXGBE_TX_MAX_SEG,
 493         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 494 };
 495
 496 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 497         .dev_configure        = ixgbe_dev_configure,
 498         .dev_start            = ixgbe_dev_start,
 499         .dev_stop             = ixgbe_dev_stop,
 500         .dev_set_link_up    = ixgbe_dev_set_link_up,
 501         .dev_set_link_down  = ixgbe_dev_set_link_down,
 502         .dev_close            = ixgbe_dev_close,
 503         .dev_reset            = ixgbe_dev_reset,
 504         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 505         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 506         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 507         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 508         .link_update          = ixgbe_dev_link_update,
 509         .stats_get            = ixgbe_dev_stats_get,
 510         .xstats_get           = ixgbe_dev_xstats_get,
 511         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 512         .stats_reset          = ixgbe_dev_stats_reset,
 513         .xstats_reset         = ixgbe_dev_xstats_reset,
 514         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 515         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 516         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 517         .fw_version_get       = ixgbe_fw_version_get,
 518         .dev_infos_get        = ixgbe_dev_info_get,
 519         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 520         .mtu_set              = ixgbe_dev_mtu_set,
 521         .vlan_filter_set      = ixgbe_vlan_filter_set,
 522         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 523         .vlan_offload_set     = ixgbe_vlan_offload_set,
 524         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 525         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 526         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 527         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 528         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 529         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 530         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 531         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 532         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 533         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 534         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 535         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 536         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 537         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 538         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 539         .dev_led_on           = ixgbe_dev_led_on,
 540         .dev_led_off          = ixgbe_dev_led_off,
 541         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 542         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 543         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 544         .mac_addr_add         = ixgbe_add_rar,
 545         .mac_addr_remove      = ixgbe_remove_rar,
 546         .mac_addr_set         = ixgbe_set_default_mac_addr,
 547         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 548         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 549         .mirror_rule_set      = ixgbe_mirror_rule_set,
 550         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 551         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 552         .reta_update          = ixgbe_dev_rss_reta_update,
 553         .reta_query           = ixgbe_dev_rss_reta_query,
 554         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 555         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 556         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 557         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 558         .rxq_info_get         = ixgbe_rxq_info_get,
 559         .txq_info_get         = ixgbe_txq_info_get,
 560         .timesync_enable      = ixgbe_timesync_enable,
 561         .timesync_disable     = ixgbe_timesync_disable,
 562         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 563         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 564         .get_reg              = ixgbe_get_regs,
 565         .get_eeprom_length    = ixgbe_get_eeprom_length,
 566         .get_eeprom           = ixgbe_get_eeprom,
 567         .set_eeprom           = ixgbe_set_eeprom,
 568         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 569         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 570         .timesync_read_time   = ixgbe_timesync_read_time,
 571         .timesync_write_time  = ixgbe_timesync_write_time,
 572         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 573         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 574         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 575         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 576         .tm_ops_get           = ixgbe_tm_ops_get,
 577 };
 578
 579 /*
 580  * dev_ops for virtual function, bare necessities for basic vf
 581  * operation have been implemented
 582  */
 583 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 584         .dev_configure        = ixgbevf_dev_configure,
 585         .dev_start            = ixgbevf_dev_start,
 586         .dev_stop             = ixgbevf_dev_stop,
 587         .link_update          = ixgbevf_dev_link_update,
 588         .stats_get            = ixgbevf_dev_stats_get,
 589         .xstats_get           = ixgbevf_dev_xstats_get,
 590         .stats_reset          = ixgbevf_dev_stats_reset,
 591         .xstats_reset         = ixgbevf_dev_stats_reset,
 592         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 593         .dev_close            = ixgbevf_dev_close,
 594         .dev_reset            = ixgbevf_dev_reset,
 595         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 596         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 597         .dev_infos_get        = ixgbevf_dev_info_get,
 598         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 599         .mtu_set              = ixgbevf_dev_set_mtu,
 600         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 601         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 602         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 603         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 604         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 605         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 606         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 607         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 608         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 609         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 610         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 611         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 612         .mac_addr_add         = ixgbevf_add_mac_addr,
 613         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 614         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 615         .rxq_info_get         = ixgbe_rxq_info_get,
 616         .txq_info_get         = ixgbe_txq_info_get,
 617         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 618         .get_reg              = ixgbevf_get_regs,
 619         .reta_update          = ixgbe_dev_rss_reta_update,
 620         .reta_query           = ixgbe_dev_rss_reta_query,
 621         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 622         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 623 };
 624
 625 /* store statistics names and its offset in stats structure */
 626 struct rte_ixgbe_xstats_name_off {
 627         char name[RTE_ETH_XSTATS_NAME_SIZE];
 628         unsigned offset;
 629 };
 630
 631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 632         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 633         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 634         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 635         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 636         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 637         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 638         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 639         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 640         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 641         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 642         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 643         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 644         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 645         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 646         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 647                 prc1023)},
 648         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 649                 prc1522)},
 650         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 651         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 652         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 653         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 654         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 655         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 656         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 657         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 658         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 659         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 660         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 661         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 662         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 663         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 664         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 665         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 666         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 667                 ptc1023)},
 668         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 669                 ptc1522)},
 670         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 671         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 672         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 673         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 674
 675         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 676                 fdirustat_add)},
 677         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 678                 fdirustat_remove)},
 679         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 680                 fdirfstat_fadd)},
 681         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 682                 fdirfstat_fremove)},
 683         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 684                 fdirmatch)},
 685         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 686                 fdirmiss)},
 687
 688         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 689         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 690         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 691                 fclast)},
 692         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 693         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 694         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 695         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 696         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 697                 fcoe_noddp)},
 698         {"rx_fcoe_no_direct_data_placement_ext_buff",
 699                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 700
 701         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 702                 lxontxc)},
 703         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 704                 lxonrxc)},
 705         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxofftxc)},
 707         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxoffrxc)},
 709         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 710 };
 711
 712 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 713                            sizeof(rte_ixgbe_stats_strings[0]))
 714
 715 /* MACsec statistics */
 716 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 717         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 718                 out_pkts_untagged)},
 719         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 720                 out_pkts_encrypted)},
 721         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_protected)},
 723         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_octets_encrypted)},
 725         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_octets_protected)},
 727         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 728                 in_pkts_untagged)},
 729         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 730                 in_pkts_badtag)},
 731         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_nosci)},
 733         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_unknownsci)},
 735         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 736                 in_octets_decrypted)},
 737         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 738                 in_octets_validated)},
 739         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_unchecked)},
 741         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_delayed)},
 743         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_late)},
 745         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_ok)},
 747         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_invalid)},
 749         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_notvalid)},
 751         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_unusedsa)},
 753         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notusingsa)},
 755 };
 756
 757 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 758                            sizeof(rte_ixgbe_macsec_strings[0]))
 759
 760 /* Per-queue statistics */
 761 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 762         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 763         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 764         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 765         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 766 };
 767
 768 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 769                            sizeof(rte_ixgbe_rxq_strings[0]))
 770 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 771
 772 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 773         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 774         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 775         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 776                 pxon2offc)},
 777 };
 778
 779 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 780                            sizeof(rte_ixgbe_txq_strings[0]))
 781 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 782
 783 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 784         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 785 };
 786
 787 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 788                 sizeof(rte_ixgbevf_stats_strings[0]))
 789
 790 /**
 791  * Atomically reads the link status information from global
 792  * structure rte_eth_dev.
 793  *
 794  * @param dev
 795  *   - Pointer to the structure rte_eth_dev to read from.
 796  *   - Pointer to the buffer to be saved with the link status.
 797  *
 798  * @return
 799  *   - On success, zero.
 800  *   - On failure, negative value.
 801  */
 802 static inline int
 803 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 804                                 struct rte_eth_link *link)
 805 {
 806         struct rte_eth_link *dst = link;
 807         struct rte_eth_link *src = &(dev->data->dev_link);
 808
 809         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 810                                         *(uint64_t *)src) == 0)
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 /**
 817  * Atomically writes the link status information into global
 818  * structure rte_eth_dev.
 819  *
 820  * @param dev
 821  *   - Pointer to the structure rte_eth_dev to read from.
 822  *   - Pointer to the buffer to be saved with the link status.
 823  *
 824  * @return
 825  *   - On success, zero.
 826  *   - On failure, negative value.
 827  */
 828 static inline int
 829 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 830                                 struct rte_eth_link *link)
 831 {
 832         struct rte_eth_link *dst = &(dev->data->dev_link);
 833         struct rte_eth_link *src = link;
 834
 835         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 836                                         *(uint64_t *)src) == 0)
 837                 return -1;
 838
 839         return 0;
 840 }
 841
 842 /*
 843  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 844  */
 845 static inline int
 846 ixgbe_is_sfp(struct ixgbe_hw *hw)
 847 {
 848         switch (hw->phy.type) {
 849         case ixgbe_phy_sfp_avago:
 850         case ixgbe_phy_sfp_ftl:
 851         case ixgbe_phy_sfp_intel:
 852         case ixgbe_phy_sfp_unknown:
 853         case ixgbe_phy_sfp_passive_tyco:
 854         case ixgbe_phy_sfp_passive_unknown:
 855                 return 1;
 856         default:
 857                 return 0;
 858         }
 859 }
 860
 861 static inline int32_t
 862 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 863 {
 864         uint32_t ctrl_ext;
 865         int32_t status;
 866
 867         status = ixgbe_reset_hw(hw);
 868
 869         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 870         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 871         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 872         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 873         IXGBE_WRITE_FLUSH(hw);
 874
 875         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 876                 status = IXGBE_SUCCESS;
 877         return status;
 878 }
 879
 880 static inline void
 881 ixgbe_enable_intr(struct rte_eth_dev *dev)
 882 {
 883         struct ixgbe_interrupt *intr =
 884                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 885         struct ixgbe_hw *hw =
 886                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 887
 888         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 889         IXGBE_WRITE_FLUSH(hw);
 890 }
 891
 892 /*
 893  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 894  */
 895 static void
 896 ixgbe_disable_intr(struct ixgbe_hw *hw)
 897 {
 898         PMD_INIT_FUNC_TRACE();
 899
 900         if (hw->mac.type == ixgbe_mac_82598EB) {
 901                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 902         } else {
 903                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 904                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 905                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 906         }
 907         IXGBE_WRITE_FLUSH(hw);
 908 }
 909
 910 /*
 911  * This function resets queue statistics mapping registers.
 912  * From Niantic datasheet, Initialization of Statistics section:
 913  * "...if software requires the queue counters, the RQSMR and TQSM registers
 914  * must be re-programmed following a device reset.
 915  */
 916 static void
 917 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 918 {
 919         uint32_t i;
 920
 921         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 922                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 923                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 924         }
 925 }
 926
 927
 928 static int
 929 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 930                                   uint16_t queue_id,
 931                                   uint8_t stat_idx,
 932                                   uint8_t is_rx)
 933 {
 934 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 935 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 936 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 937
 938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 939         struct ixgbe_stat_mapping_registers *stat_mappings =
 940                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 941         uint32_t qsmr_mask = 0;
 942         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 943         uint32_t q_map;
 944         uint8_t n, offset;
 945
 946         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 947                 (hw->mac.type != ixgbe_mac_X540) &&
 948                 (hw->mac.type != ixgbe_mac_X550) &&
 949                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 950                 (hw->mac.type != ixgbe_mac_X550EM_a))
 951                 return -ENOSYS;
 952
 953         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 954                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 955                      queue_id, stat_idx);
 956
 957         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 958         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 959                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 960                 return -EIO;
 961         }
 962         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 963
 964         /* Now clear any previous stat_idx set */
 965         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 966         if (!is_rx)
 967                 stat_mappings->tqsm[n] &= ~clearing_mask;
 968         else
 969                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 970
 971         q_map = (uint32_t)stat_idx;
 972         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 973         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 974         if (!is_rx)
 975                 stat_mappings->tqsm[n] |= qsmr_mask;
 976         else
 977                 stat_mappings->rqsmr[n] |= qsmr_mask;
 978
 979         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 980                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 981                      queue_id, stat_idx);
 982         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 983                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 984
 985         /* Now write the mapping in the appropriate register */
 986         if (is_rx) {
 987                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 988                              stat_mappings->rqsmr[n], n);
 989                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 990         } else {
 991                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 992                              stat_mappings->tqsm[n], n);
 993                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 994         }
 995         return 0;
 996 }
 997
 998 static void
 999 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1000 {
1001         struct ixgbe_stat_mapping_registers *stat_mappings =
1002                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1004         int i;
1005
1006         /* write whatever was in stat mapping table to the NIC */
1007         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1008                 /* rx */
1009                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1010
1011                 /* tx */
1012                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1013         }
1014 }
1015
1016 static void
1017 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1018 {
1019         uint8_t i;
1020         struct ixgbe_dcb_tc_config *tc;
1021         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1022
1023         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1024         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1025         for (i = 0; i < dcb_max_tc; i++) {
1026                 tc = &dcb_config->tc_config[i];
1027                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1028                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1029                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1030                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1031                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1032                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1033                 tc->pfc = ixgbe_dcb_pfc_disabled;
1034         }
1035
1036         /* Initialize default user to priority mapping, UPx->TC0 */
1037         tc = &dcb_config->tc_config[0];
1038         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1039         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1040         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1041                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1042                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1043         }
1044         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1045         dcb_config->pfc_mode_enable = false;
1046         dcb_config->vt_mode = true;
1047         dcb_config->round_robin_enable = false;
1048         /* support all DCB capabilities in 82599 */
1049         dcb_config->support.capabilities = 0xFF;
1050
1051         /*we only support 4 Tcs for X540, X550 */
1052         if (hw->mac.type == ixgbe_mac_X540 ||
1053                 hw->mac.type == ixgbe_mac_X550 ||
1054                 hw->mac.type == ixgbe_mac_X550EM_x ||
1055                 hw->mac.type == ixgbe_mac_X550EM_a) {
1056                 dcb_config->num_tcs.pg_tcs = 4;
1057                 dcb_config->num_tcs.pfc_tcs = 4;
1058         }
1059 }
1060
1061 /*
1062  * Ensure that all locks are released before first NVM or PHY access
1063  */
1064 static void
1065 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1066 {
1067         uint16_t mask;
1068
1069         /*
1070          * Phy lock should not fail in this early stage. If this is the case,
1071          * it is due to an improper exit of the application.
1072          * So force the release of the faulty lock. Release of common lock
1073          * is done automatically by swfw_sync function.
1074          */
1075         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1076         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1077                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1078         }
1079         ixgbe_release_swfw_semaphore(hw, mask);
1080
1081         /*
1082          * These ones are more tricky since they are common to all ports; but
1083          * swfw_sync retries last long enough (1s) to be almost sure that if
1084          * lock can not be taken it is due to an improper lock of the
1085          * semaphore.
1086          */
1087         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1088         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1089                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1090         }
1091         ixgbe_release_swfw_semaphore(hw, mask);
1092 }
1093
1094 /*
1095  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1096  * It returns 0 on success.
1097  */
1098 static int
1099 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1100 {
1101         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1102         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1103         struct ixgbe_hw *hw =
1104                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1105         struct ixgbe_vfta *shadow_vfta =
1106                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1107         struct ixgbe_hwstrip *hwstrip =
1108                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1109         struct ixgbe_dcb_config *dcb_config =
1110                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1111         struct ixgbe_filter_info *filter_info =
1112                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1113         struct ixgbe_bw_conf *bw_conf =
1114                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1115         uint32_t ctrl_ext;
1116         uint16_t csum;
1117         int diag, i;
1118
1119         PMD_INIT_FUNC_TRACE();
1120
1121         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1122         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1123         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1124         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1125
1126         /*
1127          * For secondary processes, we don't initialise any further as primary
1128          * has already done this work. Only check we don't need a different
1129          * RX and TX function.
1130          */
1131         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1132                 struct ixgbe_tx_queue *txq;
1133                 /* TX queue function in primary, set by last queue initialized
1134                  * Tx queue may not initialized by primary process
1135                  */
1136                 if (eth_dev->data->tx_queues) {
1137                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1138                         ixgbe_set_tx_function(eth_dev, txq);
1139                 } else {
1140                         /* Use default TX function if we get here */
1141                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1142                                      "Using default TX function.");
1143                 }
1144
1145                 ixgbe_set_rx_function(eth_dev);
1146
1147                 return 0;
1148         }
1149
1150 #ifdef RTE_LIBRTE_SECURITY
1151         /* Initialize security_ctx only for primary process*/
1152         eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1153         if (eth_dev->security_ctx == NULL)
1154                 return -ENOMEM;
1155 #endif
1156
1157         rte_eth_copy_pci_info(eth_dev, pci_dev);
1158
1159         /* Vendor and Device ID need to be set before init of shared code */
1160         hw->device_id = pci_dev->id.device_id;
1161         hw->vendor_id = pci_dev->id.vendor_id;
1162         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1163         hw->allow_unsupported_sfp = 1;
1164
1165         /* Initialize the shared code (base driver) */
1166 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1167         diag = ixgbe_bypass_init_shared_code(hw);
1168 #else
1169         diag = ixgbe_init_shared_code(hw);
1170 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1171
1172         if (diag != IXGBE_SUCCESS) {
1173                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1174                 return -EIO;
1175         }
1176
1177         /* pick up the PCI bus settings for reporting later */
1178         ixgbe_get_bus_info(hw);
1179
1180         /* Unlock any pending hardware semaphore */
1181         ixgbe_swfw_lock_reset(hw);
1182
1183         /* Initialize DCB configuration*/
1184         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1185         ixgbe_dcb_init(hw, dcb_config);
1186         /* Get Hardware Flow Control setting */
1187         hw->fc.requested_mode = ixgbe_fc_full;
1188         hw->fc.current_mode = ixgbe_fc_full;
1189         hw->fc.pause_time = IXGBE_FC_PAUSE;
1190         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1191                 hw->fc.low_water[i] = IXGBE_FC_LO;
1192                 hw->fc.high_water[i] = IXGBE_FC_HI;
1193         }
1194         hw->fc.send_xon = 1;
1195
1196         /* Make sure we have a good EEPROM before we read from it */
1197         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1198         if (diag != IXGBE_SUCCESS) {
1199                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1200                 return -EIO;
1201         }
1202
1203 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1204         diag = ixgbe_bypass_init_hw(hw);
1205 #else
1206         diag = ixgbe_init_hw(hw);
1207 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1208
1209         /*
1210          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1211          * is called too soon after the kernel driver unbinding/binding occurs.
1212          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1213          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1214          * also called. See ixgbe_identify_phy_82599(). The reason for the
1215          * failure is not known, and only occuts when virtualisation features
1216          * are disabled in the bios. A delay of 100ms  was found to be enough by
1217          * trial-and-error, and is doubled to be safe.
1218          */
1219         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1220                 rte_delay_ms(200);
1221                 diag = ixgbe_init_hw(hw);
1222         }
1223
1224         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1225                 diag = IXGBE_SUCCESS;
1226
1227         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1228                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1229                              "LOM.  Please be aware there may be issues associated "
1230                              "with your hardware.");
1231                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1232                              "please contact your Intel or hardware representative "
1233                              "who provided you with this hardware.");
1234         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1235                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1236         if (diag) {
1237                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1238                 return -EIO;
1239         }
1240
1241         /* Reset the hw statistics */
1242         ixgbe_dev_stats_reset(eth_dev);
1243
1244         /* disable interrupt */
1245         ixgbe_disable_intr(hw);
1246
1247         /* reset mappings for queue statistics hw counters*/
1248         ixgbe_reset_qstat_mappings(hw);
1249
1250         /* Allocate memory for storing MAC addresses */
1251         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1252                                                hw->mac.num_rar_entries, 0);
1253         if (eth_dev->data->mac_addrs == NULL) {
1254                 PMD_INIT_LOG(ERR,
1255                              "Failed to allocate %u bytes needed to store "
1256                              "MAC addresses",
1257                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1258                 return -ENOMEM;
1259         }
1260         /* Copy the permanent MAC address */
1261         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1262                         &eth_dev->data->mac_addrs[0]);
1263
1264         /* Allocate memory for storing hash filter MAC addresses */
1265         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1266                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1267         if (eth_dev->data->hash_mac_addrs == NULL) {
1268                 PMD_INIT_LOG(ERR,
1269                              "Failed to allocate %d bytes needed to store MAC addresses",
1270                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1271                 return -ENOMEM;
1272         }
1273
1274         /* initialize the vfta */
1275         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1276
1277         /* initialize the hw strip bitmap*/
1278         memset(hwstrip, 0, sizeof(*hwstrip));
1279
1280         /* initialize PF if max_vfs not zero */
1281         ixgbe_pf_host_init(eth_dev);
1282
1283         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1284         /* let hardware know driver is loaded */
1285         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1286         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1287         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1288         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1289         IXGBE_WRITE_FLUSH(hw);
1290
1291         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1292                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1293                              (int) hw->mac.type, (int) hw->phy.type,
1294                              (int) hw->phy.sfp_type);
1295         else
1296                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1297                              (int) hw->mac.type, (int) hw->phy.type);
1298
1299         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1300                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1301                      pci_dev->id.device_id);
1302
1303         rte_intr_callback_register(intr_handle,
1304                                    ixgbe_dev_interrupt_handler, eth_dev);
1305
1306         /* enable uio/vfio intr/eventfd mapping */
1307         rte_intr_enable(intr_handle);
1308
1309         /* enable support intr */
1310         ixgbe_enable_intr(eth_dev);
1311
1312         /* initialize filter info */
1313         memset(filter_info, 0,
1314                sizeof(struct ixgbe_filter_info));
1315
1316         /* initialize 5tuple filter list */
1317         TAILQ_INIT(&filter_info->fivetuple_list);
1318
1319         /* initialize flow director filter list & hash */
1320         ixgbe_fdir_filter_init(eth_dev);
1321
1322         /* initialize l2 tunnel filter list & hash */
1323         ixgbe_l2_tn_filter_init(eth_dev);
1324
1325         /* initialize flow filter lists */
1326         ixgbe_filterlist_init();
1327
1328         /* initialize bandwidth configuration info */
1329         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1330
1331         /* initialize Traffic Manager configuration */
1332         ixgbe_tm_conf_init(eth_dev);
1333
1334         return 0;
1335 }
1336
1337 static int
1338 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1339 {
1340         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1341         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1342         struct ixgbe_hw *hw;
1343
1344         PMD_INIT_FUNC_TRACE();
1345
1346         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1347                 return -EPERM;
1348
1349         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1350
1351         if (hw->adapter_stopped == 0)
1352                 ixgbe_dev_close(eth_dev);
1353
1354         eth_dev->dev_ops = NULL;
1355         eth_dev->rx_pkt_burst = NULL;
1356         eth_dev->tx_pkt_burst = NULL;
1357
1358         /* Unlock any pending hardware semaphore */
1359         ixgbe_swfw_lock_reset(hw);
1360
1361         /* disable uio intr before callback unregister */
1362         rte_intr_disable(intr_handle);
1363         rte_intr_callback_unregister(intr_handle,
1364                                      ixgbe_dev_interrupt_handler, eth_dev);
1365
1366         /* uninitialize PF if max_vfs not zero */
1367         ixgbe_pf_host_uninit(eth_dev);
1368
1369         rte_free(eth_dev->data->mac_addrs);
1370         eth_dev->data->mac_addrs = NULL;
1371
1372         rte_free(eth_dev->data->hash_mac_addrs);
1373         eth_dev->data->hash_mac_addrs = NULL;
1374
1375         /* remove all the fdir filters & hash */
1376         ixgbe_fdir_filter_uninit(eth_dev);
1377
1378         /* remove all the L2 tunnel filters & hash */
1379         ixgbe_l2_tn_filter_uninit(eth_dev);
1380
1381         /* Remove all ntuple filters of the device */
1382         ixgbe_ntuple_filter_uninit(eth_dev);
1383
1384         /* clear all the filters list */
1385         ixgbe_filterlist_flush();
1386
1387         /* Remove all Traffic Manager configuration */
1388         ixgbe_tm_conf_uninit(eth_dev);
1389
1390 #ifdef RTE_LIBRTE_SECURITY
1391         rte_free(eth_dev->security_ctx);
1392 #endif
1393
1394         return 0;
1395 }
1396
1397 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1398 {
1399         struct ixgbe_filter_info *filter_info =
1400                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1401         struct ixgbe_5tuple_filter *p_5tuple;
1402
1403         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1404                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1405                              p_5tuple,
1406                              entries);
1407                 rte_free(p_5tuple);
1408         }
1409         memset(filter_info->fivetuple_mask, 0,
1410                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1411
1412         return 0;
1413 }
1414
1415 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1416 {
1417         struct ixgbe_hw_fdir_info *fdir_info =
1418                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1419         struct ixgbe_fdir_filter *fdir_filter;
1420
1421                 if (fdir_info->hash_map)
1422                 rte_free(fdir_info->hash_map);
1423         if (fdir_info->hash_handle)
1424                 rte_hash_free(fdir_info->hash_handle);
1425
1426         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1427                 TAILQ_REMOVE(&fdir_info->fdir_list,
1428                              fdir_filter,
1429                              entries);
1430                 rte_free(fdir_filter);
1431         }
1432
1433         return 0;
1434 }
1435
1436 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1437 {
1438         struct ixgbe_l2_tn_info *l2_tn_info =
1439                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1440         struct ixgbe_l2_tn_filter *l2_tn_filter;
1441
1442         if (l2_tn_info->hash_map)
1443                 rte_free(l2_tn_info->hash_map);
1444         if (l2_tn_info->hash_handle)
1445                 rte_hash_free(l2_tn_info->hash_handle);
1446
1447         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1448                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1449                              l2_tn_filter,
1450                              entries);
1451                 rte_free(l2_tn_filter);
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1458 {
1459         struct ixgbe_hw_fdir_info *fdir_info =
1460                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1461         char fdir_hash_name[RTE_HASH_NAMESIZE];
1462         struct rte_hash_parameters fdir_hash_params = {
1463                 .name = fdir_hash_name,
1464                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1465                 .key_len = sizeof(union ixgbe_atr_input),
1466                 .hash_func = rte_hash_crc,
1467                 .hash_func_init_val = 0,
1468                 .socket_id = rte_socket_id(),
1469         };
1470
1471         TAILQ_INIT(&fdir_info->fdir_list);
1472         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1473                  "fdir_%s", eth_dev->device->name);
1474         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1475         if (!fdir_info->hash_handle) {
1476                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1477                 return -EINVAL;
1478         }
1479         fdir_info->hash_map = rte_zmalloc("ixgbe",
1480                                           sizeof(struct ixgbe_fdir_filter *) *
1481                                           IXGBE_MAX_FDIR_FILTER_NUM,
1482                                           0);
1483         if (!fdir_info->hash_map) {
1484                 PMD_INIT_LOG(ERR,
1485                              "Failed to allocate memory for fdir hash map!");
1486                 return -ENOMEM;
1487         }
1488         fdir_info->mask_added = FALSE;
1489
1490         return 0;
1491 }
1492
1493 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1494 {
1495         struct ixgbe_l2_tn_info *l2_tn_info =
1496                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1497         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1498         struct rte_hash_parameters l2_tn_hash_params = {
1499                 .name = l2_tn_hash_name,
1500                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1501                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1502                 .hash_func = rte_hash_crc,
1503                 .hash_func_init_val = 0,
1504                 .socket_id = rte_socket_id(),
1505         };
1506
1507         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1508         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1509                  "l2_tn_%s", eth_dev->device->name);
1510         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1511         if (!l2_tn_info->hash_handle) {
1512                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1513                 return -EINVAL;
1514         }
1515         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1516                                    sizeof(struct ixgbe_l2_tn_filter *) *
1517                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1518                                    0);
1519         if (!l2_tn_info->hash_map) {
1520                 PMD_INIT_LOG(ERR,
1521                         "Failed to allocate memory for L2 TN hash map!");
1522                 return -ENOMEM;
1523         }
1524         l2_tn_info->e_tag_en = FALSE;
1525         l2_tn_info->e_tag_fwd_en = FALSE;
1526         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1527
1528         return 0;
1529 }
1530 /*
1531  * Negotiate mailbox API version with the PF.
1532  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1533  * Then we try to negotiate starting with the most recent one.
1534  * If all negotiation attempts fail, then we will proceed with
1535  * the default one (ixgbe_mbox_api_10).
1536  */
1537 static void
1538 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1539 {
1540         int32_t i;
1541
1542         /* start with highest supported, proceed down */
1543         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1544                 ixgbe_mbox_api_12,
1545                 ixgbe_mbox_api_11,
1546                 ixgbe_mbox_api_10,
1547         };
1548
1549         for (i = 0;
1550                         i != RTE_DIM(sup_ver) &&
1551                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1552                         i++)
1553                 ;
1554 }
1555
1556 static void
1557 generate_random_mac_addr(struct ether_addr *mac_addr)
1558 {
1559         uint64_t random;
1560
1561         /* Set Organizationally Unique Identifier (OUI) prefix. */
1562         mac_addr->addr_bytes[0] = 0x00;
1563         mac_addr->addr_bytes[1] = 0x09;
1564         mac_addr->addr_bytes[2] = 0xC0;
1565         /* Force indication of locally assigned MAC address. */
1566         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1567         /* Generate the last 3 bytes of the MAC address with a random number. */
1568         random = rte_rand();
1569         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1570 }
1571
1572 /*
1573  * Virtual Function device init
1574  */
1575 static int
1576 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1577 {
1578         int diag;
1579         uint32_t tc, tcs;
1580         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1581         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1582         struct ixgbe_hw *hw =
1583                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1584         struct ixgbe_vfta *shadow_vfta =
1585                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1586         struct ixgbe_hwstrip *hwstrip =
1587                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1588         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1589
1590         PMD_INIT_FUNC_TRACE();
1591
1592         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1593         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1594         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1595
1596         /* for secondary processes, we don't initialise any further as primary
1597          * has already done this work. Only check we don't need a different
1598          * RX function
1599          */
1600         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1601                 struct ixgbe_tx_queue *txq;
1602                 /* TX queue function in primary, set by last queue initialized
1603                  * Tx queue may not initialized by primary process
1604                  */
1605                 if (eth_dev->data->tx_queues) {
1606                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1607                         ixgbe_set_tx_function(eth_dev, txq);
1608                 } else {
1609                         /* Use default TX function if we get here */
1610                         PMD_INIT_LOG(NOTICE,
1611                                      "No TX queues configured yet. Using default TX function.");
1612                 }
1613
1614                 ixgbe_set_rx_function(eth_dev);
1615
1616                 return 0;
1617         }
1618
1619         rte_eth_copy_pci_info(eth_dev, pci_dev);
1620
1621         hw->device_id = pci_dev->id.device_id;
1622         hw->vendor_id = pci_dev->id.vendor_id;
1623         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1624
1625         /* initialize the vfta */
1626         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1627
1628         /* initialize the hw strip bitmap*/
1629         memset(hwstrip, 0, sizeof(*hwstrip));
1630
1631         /* Initialize the shared code (base driver) */
1632         diag = ixgbe_init_shared_code(hw);
1633         if (diag != IXGBE_SUCCESS) {
1634                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1635                 return -EIO;
1636         }
1637
1638         /* init_mailbox_params */
1639         hw->mbx.ops.init_params(hw);
1640
1641         /* Reset the hw statistics */
1642         ixgbevf_dev_stats_reset(eth_dev);
1643
1644         /* Disable the interrupts for VF */
1645         ixgbevf_intr_disable(hw);
1646
1647         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1648         diag = hw->mac.ops.reset_hw(hw);
1649
1650         /*
1651          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1652          * the underlying PF driver has not assigned a MAC address to the VF.
1653          * In this case, assign a random MAC address.
1654          */
1655         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1656                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1657                 return diag;
1658         }
1659
1660         /* negotiate mailbox API version to use with the PF. */
1661         ixgbevf_negotiate_api(hw);
1662
1663         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1664         ixgbevf_get_queues(hw, &tcs, &tc);
1665
1666         /* Allocate memory for storing MAC addresses */
1667         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1668                                                hw->mac.num_rar_entries, 0);
1669         if (eth_dev->data->mac_addrs == NULL) {
1670                 PMD_INIT_LOG(ERR,
1671                              "Failed to allocate %u bytes needed to store "
1672                              "MAC addresses",
1673                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1674                 return -ENOMEM;
1675         }
1676
1677         /* Generate a random MAC address, if none was assigned by PF. */
1678         if (is_zero_ether_addr(perm_addr)) {
1679                 generate_random_mac_addr(perm_addr);
1680                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1681                 if (diag) {
1682                         rte_free(eth_dev->data->mac_addrs);
1683                         eth_dev->data->mac_addrs = NULL;
1684                         return diag;
1685                 }
1686                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1687                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1688                              "%02x:%02x:%02x:%02x:%02x:%02x",
1689                              perm_addr->addr_bytes[0],
1690                              perm_addr->addr_bytes[1],
1691                              perm_addr->addr_bytes[2],
1692                              perm_addr->addr_bytes[3],
1693                              perm_addr->addr_bytes[4],
1694                              perm_addr->addr_bytes[5]);
1695         }
1696
1697         /* Copy the permanent MAC address */
1698         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1699
1700         /* reset the hardware with the new settings */
1701         diag = hw->mac.ops.start_hw(hw);
1702         switch (diag) {
1703         case  0:
1704                 break;
1705
1706         default:
1707                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1708                 return -EIO;
1709         }
1710
1711         rte_intr_callback_register(intr_handle,
1712                                    ixgbevf_dev_interrupt_handler, eth_dev);
1713         rte_intr_enable(intr_handle);
1714         ixgbevf_intr_enable(hw);
1715
1716         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1717                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1718                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1719
1720         return 0;
1721 }
1722
1723 /* Virtual Function device uninit */
1724
1725 static int
1726 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1727 {
1728         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1729         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1730         struct ixgbe_hw *hw;
1731
1732         PMD_INIT_FUNC_TRACE();
1733
1734         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1735                 return -EPERM;
1736
1737         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1738
1739         if (hw->adapter_stopped == 0)
1740                 ixgbevf_dev_close(eth_dev);
1741
1742         eth_dev->dev_ops = NULL;
1743         eth_dev->rx_pkt_burst = NULL;
1744         eth_dev->tx_pkt_burst = NULL;
1745
1746         /* Disable the interrupts for VF */
1747         ixgbevf_intr_disable(hw);
1748
1749         rte_free(eth_dev->data->mac_addrs);
1750         eth_dev->data->mac_addrs = NULL;
1751
1752         rte_intr_disable(intr_handle);
1753         rte_intr_callback_unregister(intr_handle,
1754                                      ixgbevf_dev_interrupt_handler, eth_dev);
1755
1756         return 0;
1757 }
1758
1759 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1760         struct rte_pci_device *pci_dev)
1761 {
1762         return rte_eth_dev_pci_generic_probe(pci_dev,
1763                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1764 }
1765
1766 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1767 {
1768         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1769 }
1770
1771 static struct rte_pci_driver rte_ixgbe_pmd = {
1772         .id_table = pci_id_ixgbe_map,
1773         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1774                      RTE_PCI_DRV_IOVA_AS_VA,
1775         .probe = eth_ixgbe_pci_probe,
1776         .remove = eth_ixgbe_pci_remove,
1777 };
1778
1779 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1780         struct rte_pci_device *pci_dev)
1781 {
1782         return rte_eth_dev_pci_generic_probe(pci_dev,
1783                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1784 }
1785
1786 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1787 {
1788         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1789 }
1790
1791 /*
1792  * virtual function driver struct
1793  */
1794 static struct rte_pci_driver rte_ixgbevf_pmd = {
1795         .id_table = pci_id_ixgbevf_map,
1796         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1797         .probe = eth_ixgbevf_pci_probe,
1798         .remove = eth_ixgbevf_pci_remove,
1799 };
1800
1801 static int
1802 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1803 {
1804         struct ixgbe_hw *hw =
1805                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1806         struct ixgbe_vfta *shadow_vfta =
1807                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1808         uint32_t vfta;
1809         uint32_t vid_idx;
1810         uint32_t vid_bit;
1811
1812         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1813         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1814         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1815         if (on)
1816                 vfta |= vid_bit;
1817         else
1818                 vfta &= ~vid_bit;
1819         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1820
1821         /* update local VFTA copy */
1822         shadow_vfta->vfta[vid_idx] = vfta;
1823
1824         return 0;
1825 }
1826
1827 static void
1828 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1829 {
1830         if (on)
1831                 ixgbe_vlan_hw_strip_enable(dev, queue);
1832         else
1833                 ixgbe_vlan_hw_strip_disable(dev, queue);
1834 }
1835
1836 static int
1837 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1838                     enum rte_vlan_type vlan_type,
1839                     uint16_t tpid)
1840 {
1841         struct ixgbe_hw *hw =
1842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843         int ret = 0;
1844         uint32_t reg;
1845         uint32_t qinq;
1846
1847         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1848         qinq &= IXGBE_DMATXCTL_GDV;
1849
1850         switch (vlan_type) {
1851         case ETH_VLAN_TYPE_INNER:
1852                 if (qinq) {
1853                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1854                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1855                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1856                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1857                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1858                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1859                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1860                 } else {
1861                         ret = -ENOTSUP;
1862                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1863                                     " by single VLAN");
1864                 }
1865                 break;
1866         case ETH_VLAN_TYPE_OUTER:
1867                 if (qinq) {
1868                         /* Only the high 16-bits is valid */
1869                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1870                                         IXGBE_EXVET_VET_EXT_SHIFT);
1871                 } else {
1872                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1873                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1874                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1875                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1876                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1877                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1878                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1879                 }
1880
1881                 break;
1882         default:
1883                 ret = -EINVAL;
1884                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1885                 break;
1886         }
1887
1888         return ret;
1889 }
1890
1891 void
1892 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1893 {
1894         struct ixgbe_hw *hw =
1895                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1896         uint32_t vlnctrl;
1897
1898         PMD_INIT_FUNC_TRACE();
1899
1900         /* Filter Table Disable */
1901         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1902         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1903
1904         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1905 }
1906
1907 void
1908 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1909 {
1910         struct ixgbe_hw *hw =
1911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912         struct ixgbe_vfta *shadow_vfta =
1913                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1914         uint32_t vlnctrl;
1915         uint16_t i;
1916
1917         PMD_INIT_FUNC_TRACE();
1918
1919         /* Filter Table Enable */
1920         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1921         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1922         vlnctrl |= IXGBE_VLNCTRL_VFE;
1923
1924         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1925
1926         /* write whatever is in local vfta copy */
1927         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1928                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1929 }
1930
1931 static void
1932 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1933 {
1934         struct ixgbe_hwstrip *hwstrip =
1935                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1936         struct ixgbe_rx_queue *rxq;
1937
1938         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1939                 return;
1940
1941         if (on)
1942                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1943         else
1944                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1945
1946         if (queue >= dev->data->nb_rx_queues)
1947                 return;
1948
1949         rxq = dev->data->rx_queues[queue];
1950
1951         if (on)
1952                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1953         else
1954                 rxq->vlan_flags = PKT_RX_VLAN;
1955 }
1956
1957 static void
1958 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1959 {
1960         struct ixgbe_hw *hw =
1961                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962         uint32_t ctrl;
1963
1964         PMD_INIT_FUNC_TRACE();
1965
1966         if (hw->mac.type == ixgbe_mac_82598EB) {
1967                 /* No queue level support */
1968                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1969                 return;
1970         }
1971
1972         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1973         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1974         ctrl &= ~IXGBE_RXDCTL_VME;
1975         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1976
1977         /* record those setting for HW strip per queue */
1978         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1979 }
1980
1981 static void
1982 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1983 {
1984         struct ixgbe_hw *hw =
1985                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986         uint32_t ctrl;
1987
1988         PMD_INIT_FUNC_TRACE();
1989
1990         if (hw->mac.type == ixgbe_mac_82598EB) {
1991                 /* No queue level supported */
1992                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1993                 return;
1994         }
1995
1996         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1997         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1998         ctrl |= IXGBE_RXDCTL_VME;
1999         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2000
2001         /* record those setting for HW strip per queue */
2002         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2003 }
2004
2005 void
2006 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2007 {
2008         struct ixgbe_hw *hw =
2009                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010         uint32_t ctrl;
2011         uint16_t i;
2012         struct ixgbe_rx_queue *rxq;
2013
2014         PMD_INIT_FUNC_TRACE();
2015
2016         if (hw->mac.type == ixgbe_mac_82598EB) {
2017                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2018                 ctrl &= ~IXGBE_VLNCTRL_VME;
2019                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2020         } else {
2021                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2022                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2023                         rxq = dev->data->rx_queues[i];
2024                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2025                         ctrl &= ~IXGBE_RXDCTL_VME;
2026                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2027
2028                         /* record those setting for HW strip per queue */
2029                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2030                 }
2031         }
2032 }
2033
2034 void
2035 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2036 {
2037         struct ixgbe_hw *hw =
2038                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039         uint32_t ctrl;
2040         uint16_t i;
2041         struct ixgbe_rx_queue *rxq;
2042
2043         PMD_INIT_FUNC_TRACE();
2044
2045         if (hw->mac.type == ixgbe_mac_82598EB) {
2046                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2047                 ctrl |= IXGBE_VLNCTRL_VME;
2048                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2049         } else {
2050                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2051                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2052                         rxq = dev->data->rx_queues[i];
2053                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2054                         ctrl |= IXGBE_RXDCTL_VME;
2055                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2056
2057                         /* record those setting for HW strip per queue */
2058                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2059                 }
2060         }
2061 }
2062
2063 static void
2064 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2065 {
2066         struct ixgbe_hw *hw =
2067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2068         uint32_t ctrl;
2069
2070         PMD_INIT_FUNC_TRACE();
2071
2072         /* DMATXCTRL: Geric Double VLAN Disable */
2073         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2074         ctrl &= ~IXGBE_DMATXCTL_GDV;
2075         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2076
2077         /* CTRL_EXT: Global Double VLAN Disable */
2078         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2079         ctrl &= ~IXGBE_EXTENDED_VLAN;
2080         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2081
2082 }
2083
2084 static void
2085 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2086 {
2087         struct ixgbe_hw *hw =
2088                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089         uint32_t ctrl;
2090
2091         PMD_INIT_FUNC_TRACE();
2092
2093         /* DMATXCTRL: Geric Double VLAN Enable */
2094         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2095         ctrl |= IXGBE_DMATXCTL_GDV;
2096         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2097
2098         /* CTRL_EXT: Global Double VLAN Enable */
2099         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2100         ctrl |= IXGBE_EXTENDED_VLAN;
2101         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2102
2103         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2104         if (hw->mac.type == ixgbe_mac_X550 ||
2105             hw->mac.type == ixgbe_mac_X550EM_x ||
2106             hw->mac.type == ixgbe_mac_X550EM_a) {
2107                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2108                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2109                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2110         }
2111
2112         /*
2113          * VET EXT field in the EXVET register = 0x8100 by default
2114          * So no need to change. Same to VT field of DMATXCTL register
2115          */
2116 }
2117
2118 static int
2119 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2120 {
2121         if (mask & ETH_VLAN_STRIP_MASK) {
2122                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2123                         ixgbe_vlan_hw_strip_enable_all(dev);
2124                 else
2125                         ixgbe_vlan_hw_strip_disable_all(dev);
2126         }
2127
2128         if (mask & ETH_VLAN_FILTER_MASK) {
2129                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2130                         ixgbe_vlan_hw_filter_enable(dev);
2131                 else
2132                         ixgbe_vlan_hw_filter_disable(dev);
2133         }
2134
2135         if (mask & ETH_VLAN_EXTEND_MASK) {
2136                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2137                         ixgbe_vlan_hw_extend_enable(dev);
2138                 else
2139                         ixgbe_vlan_hw_extend_disable(dev);
2140         }
2141
2142         return 0;
2143 }
2144
2145 static void
2146 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2147 {
2148         struct ixgbe_hw *hw =
2149                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2151         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2152
2153         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2154         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2155 }
2156
2157 static int
2158 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2159 {
2160         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2161
2162         switch (nb_rx_q) {
2163         case 1:
2164         case 2:
2165                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2166                 break;
2167         case 4:
2168                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2169                 break;
2170         default:
2171                 return -EINVAL;
2172         }
2173
2174         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2175                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2176         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2177                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2178         return 0;
2179 }
2180
2181 static int
2182 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2183 {
2184         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2185         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2187         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2188
2189         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2190                 /* check multi-queue mode */
2191                 switch (dev_conf->rxmode.mq_mode) {
2192                 case ETH_MQ_RX_VMDQ_DCB:
2193                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2194                         break;
2195                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2196                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2197                         PMD_INIT_LOG(ERR, "SRIOV active,"
2198                                         " unsupported mq_mode rx %d.",
2199                                         dev_conf->rxmode.mq_mode);
2200                         return -EINVAL;
2201                 case ETH_MQ_RX_RSS:
2202                 case ETH_MQ_RX_VMDQ_RSS:
2203                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2204                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2205                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2206                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2207                                                 " invalid queue number"
2208                                                 " for VMDQ RSS, allowed"
2209                                                 " value are 1, 2 or 4.");
2210                                         return -EINVAL;
2211                                 }
2212                         break;
2213                 case ETH_MQ_RX_VMDQ_ONLY:
2214                 case ETH_MQ_RX_NONE:
2215                         /* if nothing mq mode configure, use default scheme */
2216                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2217                         break;
2218                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2219                         /* SRIOV only works in VMDq enable mode */
2220                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2221                                         " wrong mq_mode rx %d.",
2222                                         dev_conf->rxmode.mq_mode);
2223                         return -EINVAL;
2224                 }
2225
2226                 switch (dev_conf->txmode.mq_mode) {
2227                 case ETH_MQ_TX_VMDQ_DCB:
2228                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2229                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2230                         break;
2231                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2232                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2233                         break;
2234                 }
2235
2236                 /* check valid queue number */
2237                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2238                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2239                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2240                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2241                                         " must be less than or equal to %d.",
2242                                         nb_rx_q, nb_tx_q,
2243                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2244                         return -EINVAL;
2245                 }
2246         } else {
2247                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2248                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2249                                           " not supported.");
2250                         return -EINVAL;
2251                 }
2252                 /* check configuration for vmdb+dcb mode */
2253                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2254                         const struct rte_eth_vmdq_dcb_conf *conf;
2255
2256                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2257                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2258                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2259                                 return -EINVAL;
2260                         }
2261                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2262                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2263                                conf->nb_queue_pools == ETH_32_POOLS)) {
2264                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2265                                                 " nb_queue_pools must be %d or %d.",
2266                                                 ETH_16_POOLS, ETH_32_POOLS);
2267                                 return -EINVAL;
2268                         }
2269                 }
2270                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2271                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2272
2273                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2274                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2275                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2276                                 return -EINVAL;
2277                         }
2278                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2279                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2280                                conf->nb_queue_pools == ETH_32_POOLS)) {
2281                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2282                                                 " nb_queue_pools != %d and"
2283                                                 " nb_queue_pools != %d.",
2284                                                 ETH_16_POOLS, ETH_32_POOLS);
2285                                 return -EINVAL;
2286                         }
2287                 }
2288
2289                 /* For DCB mode check our configuration before we go further */
2290                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2291                         const struct rte_eth_dcb_rx_conf *conf;
2292
2293                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2294                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2295                                                  IXGBE_DCB_NB_QUEUES);
2296                                 return -EINVAL;
2297                         }
2298                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2299                         if (!(conf->nb_tcs == ETH_4_TCS ||
2300                                conf->nb_tcs == ETH_8_TCS)) {
2301                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2302                                                 " and nb_tcs != %d.",
2303                                                 ETH_4_TCS, ETH_8_TCS);
2304                                 return -EINVAL;
2305                         }
2306                 }
2307
2308                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2309                         const struct rte_eth_dcb_tx_conf *conf;
2310
2311                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2312                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2313                                                  IXGBE_DCB_NB_QUEUES);
2314                                 return -EINVAL;
2315                         }
2316                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2317                         if (!(conf->nb_tcs == ETH_4_TCS ||
2318                                conf->nb_tcs == ETH_8_TCS)) {
2319                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2320                                                 " and nb_tcs != %d.",
2321                                                 ETH_4_TCS, ETH_8_TCS);
2322                                 return -EINVAL;
2323                         }
2324                 }
2325
2326                 /*
2327                  * When DCB/VT is off, maximum number of queues changes,
2328                  * except for 82598EB, which remains constant.
2329                  */
2330                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2331                                 hw->mac.type != ixgbe_mac_82598EB) {
2332                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2333                                 PMD_INIT_LOG(ERR,
2334                                              "Neither VT nor DCB are enabled, "
2335                                              "nb_tx_q > %d.",
2336                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2337                                 return -EINVAL;
2338                         }
2339                 }
2340         }
2341         return 0;
2342 }
2343
2344 static int
2345 ixgbe_dev_configure(struct rte_eth_dev *dev)
2346 {
2347         struct ixgbe_interrupt *intr =
2348                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2349         struct ixgbe_adapter *adapter =
2350                 (struct ixgbe_adapter *)dev->data->dev_private;
2351         int ret;
2352
2353         PMD_INIT_FUNC_TRACE();
2354         /* multipe queue mode checking */
2355         ret  = ixgbe_check_mq_mode(dev);
2356         if (ret != 0) {
2357                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2358                             ret);
2359                 return ret;
2360         }
2361
2362         /* set flag to update link status after init */
2363         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2364
2365         /*
2366          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2367          * allocation or vector Rx preconditions we will reset it.
2368          */
2369         adapter->rx_bulk_alloc_allowed = true;
2370         adapter->rx_vec_allowed = true;
2371
2372         return 0;
2373 }
2374
2375 static void
2376 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2377 {
2378         struct ixgbe_hw *hw =
2379                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380         struct ixgbe_interrupt *intr =
2381                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2382         uint32_t gpie;
2383
2384         /* only set up it on X550EM_X */
2385         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2386                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2387                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2388                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2389                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2390                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2391         }
2392 }
2393
2394 int
2395 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2396                         uint16_t tx_rate, uint64_t q_msk)
2397 {
2398         struct ixgbe_hw *hw;
2399         struct ixgbe_vf_info *vfinfo;
2400         struct rte_eth_link link;
2401         uint8_t  nb_q_per_pool;
2402         uint32_t queue_stride;
2403         uint32_t queue_idx, idx = 0, vf_idx;
2404         uint32_t queue_end;
2405         uint16_t total_rate = 0;
2406         struct rte_pci_device *pci_dev;
2407
2408         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2409         rte_eth_link_get_nowait(dev->data->port_id, &link);
2410
2411         if (vf >= pci_dev->max_vfs)
2412                 return -EINVAL;
2413
2414         if (tx_rate > link.link_speed)
2415                 return -EINVAL;
2416
2417         if (q_msk == 0)
2418                 return 0;
2419
2420         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2421         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2422         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2423         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2424         queue_idx = vf * queue_stride;
2425         queue_end = queue_idx + nb_q_per_pool - 1;
2426         if (queue_end >= hw->mac.max_tx_queues)
2427                 return -EINVAL;
2428
2429         if (vfinfo) {
2430                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2431                         if (vf_idx == vf)
2432                                 continue;
2433                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2434                                 idx++)
2435                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2436                 }
2437         } else {
2438                 return -EINVAL;
2439         }
2440
2441         /* Store tx_rate for this vf. */
2442         for (idx = 0; idx < nb_q_per_pool; idx++) {
2443                 if (((uint64_t)0x1 << idx) & q_msk) {
2444                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2445                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2446                         total_rate += tx_rate;
2447                 }
2448         }
2449
2450         if (total_rate > dev->data->dev_link.link_speed) {
2451                 /* Reset stored TX rate of the VF if it causes exceed
2452                  * link speed.
2453                  */
2454                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2455                 return -EINVAL;
2456         }
2457
2458         /* Set RTTBCNRC of each queue/pool for vf X  */
2459         for (; queue_idx <= queue_end; queue_idx++) {
2460                 if (0x1 & q_msk)
2461                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2462                 q_msk = q_msk >> 1;
2463         }
2464
2465         return 0;
2466 }
2467
2468 /*
2469  * Configure device link speed and setup link.
2470  * It returns 0 on success.
2471  */
2472 static int
2473 ixgbe_dev_start(struct rte_eth_dev *dev)
2474 {
2475         struct ixgbe_hw *hw =
2476                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477         struct ixgbe_vf_info *vfinfo =
2478                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2479         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2480         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2481         uint32_t intr_vector = 0;
2482         int err, link_up = 0, negotiate = 0;
2483         uint32_t speed = 0;
2484         int mask = 0;
2485         int status;
2486         uint16_t vf, idx;
2487         uint32_t *link_speeds;
2488         struct ixgbe_tm_conf *tm_conf =
2489                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2490
2491         PMD_INIT_FUNC_TRACE();
2492
2493         /* IXGBE devices don't support:
2494         *    - half duplex (checked afterwards for valid speeds)
2495         *    - fixed speed: TODO implement
2496         */
2497         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2498                 PMD_INIT_LOG(ERR,
2499                 "Invalid link_speeds for port %u, fix speed not supported",
2500                                 dev->data->port_id);
2501                 return -EINVAL;
2502         }
2503
2504         /* disable uio/vfio intr/eventfd mapping */
2505         rte_intr_disable(intr_handle);
2506
2507         /* stop adapter */
2508         hw->adapter_stopped = 0;
2509         ixgbe_stop_adapter(hw);
2510
2511         /* reinitialize adapter
2512          * this calls reset and start
2513          */
2514         status = ixgbe_pf_reset_hw(hw);
2515         if (status != 0)
2516                 return -1;
2517         hw->mac.ops.start_hw(hw);
2518         hw->mac.get_link_status = true;
2519
2520         /* configure PF module if SRIOV enabled */
2521         ixgbe_pf_host_configure(dev);
2522
2523         ixgbe_dev_phy_intr_setup(dev);
2524
2525         /* check and configure queue intr-vector mapping */
2526         if ((rte_intr_cap_multiple(intr_handle) ||
2527              !RTE_ETH_DEV_SRIOV(dev).active) &&
2528             dev->data->dev_conf.intr_conf.rxq != 0) {
2529                 intr_vector = dev->data->nb_rx_queues;
2530                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2531                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2532                                         IXGBE_MAX_INTR_QUEUE_NUM);
2533                         return -ENOTSUP;
2534                 }
2535                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2536                         return -1;
2537         }
2538
2539         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2540                 intr_handle->intr_vec =
2541                         rte_zmalloc("intr_vec",
2542                                     dev->data->nb_rx_queues * sizeof(int), 0);
2543                 if (intr_handle->intr_vec == NULL) {
2544                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2545                                      " intr_vec", dev->data->nb_rx_queues);
2546                         return -ENOMEM;
2547                 }
2548         }
2549
2550         /* confiugre msix for sleep until rx interrupt */
2551         ixgbe_configure_msix(dev);
2552
2553         /* initialize transmission unit */
2554         ixgbe_dev_tx_init(dev);
2555
2556         /* This can fail when allocating mbufs for descriptor rings */
2557         err = ixgbe_dev_rx_init(dev);
2558         if (err) {
2559                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2560                 goto error;
2561         }
2562
2563         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2564                 ETH_VLAN_EXTEND_MASK;
2565         err = ixgbe_vlan_offload_set(dev, mask);
2566         if (err) {
2567                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2568                 goto error;
2569         }
2570
2571         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2572                 /* Enable vlan filtering for VMDq */
2573                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2574         }
2575
2576         /* Configure DCB hw */
2577         ixgbe_configure_dcb(dev);
2578
2579         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2580                 err = ixgbe_fdir_configure(dev);
2581                 if (err)
2582                         goto error;
2583         }
2584
2585         /* Restore vf rate limit */
2586         if (vfinfo != NULL) {
2587                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2588                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2589                                 if (vfinfo[vf].tx_rate[idx] != 0)
2590                                         ixgbe_set_vf_rate_limit(
2591                                                 dev, vf,
2592                                                 vfinfo[vf].tx_rate[idx],
2593                                                 1 << idx);
2594         }
2595
2596         ixgbe_restore_statistics_mapping(dev);
2597
2598         err = ixgbe_dev_rxtx_start(dev);
2599         if (err < 0) {
2600                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2601                 goto error;
2602         }
2603
2604         /* Skip link setup if loopback mode is enabled for 82599. */
2605         if (hw->mac.type == ixgbe_mac_82599EB &&
2606                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2607                 goto skip_link_setup;
2608
2609         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2610                 err = hw->mac.ops.setup_sfp(hw);
2611                 if (err)
2612                         goto error;
2613         }
2614
2615         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2616                 /* Turn on the copper */
2617                 ixgbe_set_phy_power(hw, true);
2618         } else {
2619                 /* Turn on the laser */
2620                 ixgbe_enable_tx_laser(hw);
2621         }
2622
2623         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2624         if (err)
2625                 goto error;
2626         dev->data->dev_link.link_status = link_up;
2627
2628         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2629         if (err)
2630                 goto error;
2631
2632         link_speeds = &dev->data->dev_conf.link_speeds;
2633         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2634                         ETH_LINK_SPEED_10G)) {
2635                 PMD_INIT_LOG(ERR, "Invalid link setting");
2636                 goto error;
2637         }
2638
2639         speed = 0x0;
2640         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2641                 switch (hw->mac.type) {
2642                 case ixgbe_mac_82598EB:
2643                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2644                         break;
2645                 case ixgbe_mac_82599EB:
2646                 case ixgbe_mac_X540:
2647                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2648                         break;
2649                 case ixgbe_mac_X550:
2650                 case ixgbe_mac_X550EM_x:
2651                 case ixgbe_mac_X550EM_a:
2652                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2653                         break;
2654                 default:
2655                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2656                 }
2657         } else {
2658                 if (*link_speeds & ETH_LINK_SPEED_10G)
2659                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2660                 if (*link_speeds & ETH_LINK_SPEED_1G)
2661                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2662                 if (*link_speeds & ETH_LINK_SPEED_100M)
2663                         speed |= IXGBE_LINK_SPEED_100_FULL;
2664         }
2665
2666         err = ixgbe_setup_link(hw, speed, link_up);
2667         if (err)
2668                 goto error;
2669
2670 skip_link_setup:
2671
2672         if (rte_intr_allow_others(intr_handle)) {
2673                 /* check if lsc interrupt is enabled */
2674                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2675                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2676                 else
2677                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2678                 ixgbe_dev_macsec_interrupt_setup(dev);
2679         } else {
2680                 rte_intr_callback_unregister(intr_handle,
2681                                              ixgbe_dev_interrupt_handler, dev);
2682                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2683                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2684                                      " no intr multiplex");
2685         }
2686
2687         /* check if rxq interrupt is enabled */
2688         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2689             rte_intr_dp_is_en(intr_handle))
2690                 ixgbe_dev_rxq_interrupt_setup(dev);
2691
2692         /* enable uio/vfio intr/eventfd mapping */
2693         rte_intr_enable(intr_handle);
2694
2695         /* resume enabled intr since hw reset */
2696         ixgbe_enable_intr(dev);
2697         ixgbe_l2_tunnel_conf(dev);
2698         ixgbe_filter_restore(dev);
2699
2700         if (tm_conf->root && !tm_conf->committed)
2701                 PMD_DRV_LOG(WARNING,
2702                             "please call hierarchy_commit() "
2703                             "before starting the port");
2704
2705         return 0;
2706
2707 error:
2708         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2709         ixgbe_dev_clear_queues(dev);
2710         return -EIO;
2711 }
2712
2713 /*
2714  * Stop device: disable rx and tx functions to allow for reconfiguring.
2715  */
2716 static void
2717 ixgbe_dev_stop(struct rte_eth_dev *dev)
2718 {
2719         struct rte_eth_link link;
2720         struct ixgbe_hw *hw =
2721                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2722         struct ixgbe_vf_info *vfinfo =
2723                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2724         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2725         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2726         int vf;
2727         struct ixgbe_tm_conf *tm_conf =
2728                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2729
2730         PMD_INIT_FUNC_TRACE();
2731
2732         /* disable interrupts */
2733         ixgbe_disable_intr(hw);
2734
2735         /* reset the NIC */
2736         ixgbe_pf_reset_hw(hw);
2737         hw->adapter_stopped = 0;
2738
2739         /* stop adapter */
2740         ixgbe_stop_adapter(hw);
2741
2742         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2743                 vfinfo[vf].clear_to_send = false;
2744
2745         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2746                 /* Turn off the copper */
2747                 ixgbe_set_phy_power(hw, false);
2748         } else {
2749                 /* Turn off the laser */
2750                 ixgbe_disable_tx_laser(hw);
2751         }
2752
2753         ixgbe_dev_clear_queues(dev);
2754
2755         /* Clear stored conf */
2756         dev->data->scattered_rx = 0;
2757         dev->data->lro = 0;
2758
2759         /* Clear recorded link status */
2760         memset(&link, 0, sizeof(link));
2761         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2762
2763         if (!rte_intr_allow_others(intr_handle))
2764                 /* resume to the default handler */
2765                 rte_intr_callback_register(intr_handle,
2766                                            ixgbe_dev_interrupt_handler,
2767                                            (void *)dev);
2768
2769         /* Clean datapath event and queue/vec mapping */
2770         rte_intr_efd_disable(intr_handle);
2771         if (intr_handle->intr_vec != NULL) {
2772                 rte_free(intr_handle->intr_vec);
2773                 intr_handle->intr_vec = NULL;
2774         }
2775
2776         /* reset hierarchy commit */
2777         tm_conf->committed = false;
2778 }
2779
2780 /*
2781  * Set device link up: enable tx.
2782  */
2783 static int
2784 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2785 {
2786         struct ixgbe_hw *hw =
2787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788         if (hw->mac.type == ixgbe_mac_82599EB) {
2789 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2790                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2791                         /* Not suported in bypass mode */
2792                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2793                                      "by device id 0x%x", hw->device_id);
2794                         return -ENOTSUP;
2795                 }
2796 #endif
2797         }
2798
2799         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2800                 /* Turn on the copper */
2801                 ixgbe_set_phy_power(hw, true);
2802         } else {
2803                 /* Turn on the laser */
2804                 ixgbe_enable_tx_laser(hw);
2805         }
2806
2807         return 0;
2808 }
2809
2810 /*
2811  * Set device link down: disable tx.
2812  */
2813 static int
2814 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2815 {
2816         struct ixgbe_hw *hw =
2817                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818         if (hw->mac.type == ixgbe_mac_82599EB) {
2819 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2820                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2821                         /* Not suported in bypass mode */
2822                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2823                                      "by device id 0x%x", hw->device_id);
2824                         return -ENOTSUP;
2825                 }
2826 #endif
2827         }
2828
2829         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2830                 /* Turn off the copper */
2831                 ixgbe_set_phy_power(hw, false);
2832         } else {
2833                 /* Turn off the laser */
2834                 ixgbe_disable_tx_laser(hw);
2835         }
2836
2837         return 0;
2838 }
2839
2840 /*
2841  * Reset and stop device.
2842  */
2843 static void
2844 ixgbe_dev_close(struct rte_eth_dev *dev)
2845 {
2846         struct ixgbe_hw *hw =
2847                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2848
2849         PMD_INIT_FUNC_TRACE();
2850
2851         ixgbe_pf_reset_hw(hw);
2852
2853         ixgbe_dev_stop(dev);
2854         hw->adapter_stopped = 1;
2855
2856         ixgbe_dev_free_queues(dev);
2857
2858         ixgbe_disable_pcie_master(hw);
2859
2860         /* reprogram the RAR[0] in case user changed it. */
2861         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2862 }
2863
2864 /*
2865  * Reset PF device.
2866  */
2867 static int
2868 ixgbe_dev_reset(struct rte_eth_dev *dev)
2869 {
2870         int ret;
2871
2872         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2873          * its VF to make them align with it. The detailed notification
2874          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2875          * To avoid unexpected behavior in VF, currently reset of PF with
2876          * SR-IOV activation is not supported. It might be supported later.
2877          */
2878         if (dev->data->sriov.active)
2879                 return -ENOTSUP;
2880
2881         ret = eth_ixgbe_dev_uninit(dev);
2882         if (ret)
2883                 return ret;
2884
2885         ret = eth_ixgbe_dev_init(dev);
2886
2887         return ret;
2888 }
2889
2890 static void
2891 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2892                            struct ixgbe_hw_stats *hw_stats,
2893                            struct ixgbe_macsec_stats *macsec_stats,
2894                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2895                            uint64_t *total_qprc, uint64_t *total_qprdc)
2896 {
2897         uint32_t bprc, lxon, lxoff, total;
2898         uint32_t delta_gprc = 0;
2899         unsigned i;
2900         /* Workaround for RX byte count not including CRC bytes when CRC
2901          * strip is enabled. CRC bytes are removed from counters when crc_strip
2902          * is disabled.
2903          */
2904         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2905                         IXGBE_HLREG0_RXCRCSTRP);
2906
2907         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2908         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2909         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2910         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2911
2912         for (i = 0; i < 8; i++) {
2913                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2914
2915                 /* global total per queue */
2916                 hw_stats->mpc[i] += mp;
2917                 /* Running comprehensive total for stats display */
2918                 *total_missed_rx += hw_stats->mpc[i];
2919                 if (hw->mac.type == ixgbe_mac_82598EB) {
2920                         hw_stats->rnbc[i] +=
2921                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2922                         hw_stats->pxonrxc[i] +=
2923                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2924                         hw_stats->pxoffrxc[i] +=
2925                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2926                 } else {
2927                         hw_stats->pxonrxc[i] +=
2928                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2929                         hw_stats->pxoffrxc[i] +=
2930                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2931                         hw_stats->pxon2offc[i] +=
2932                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2933                 }
2934                 hw_stats->pxontxc[i] +=
2935                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2936                 hw_stats->pxofftxc[i] +=
2937                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2938         }
2939         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2940                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2941                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2942                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2943
2944                 delta_gprc += delta_qprc;
2945
2946                 hw_stats->qprc[i] += delta_qprc;
2947                 hw_stats->qptc[i] += delta_qptc;
2948
2949                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2950                 hw_stats->qbrc[i] +=
2951                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2952                 if (crc_strip == 0)
2953                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2954
2955                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2956                 hw_stats->qbtc[i] +=
2957                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2958
2959                 hw_stats->qprdc[i] += delta_qprdc;
2960                 *total_qprdc += hw_stats->qprdc[i];
2961
2962                 *total_qprc += hw_stats->qprc[i];
2963                 *total_qbrc += hw_stats->qbrc[i];
2964         }
2965         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2966         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2967         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2968
2969         /*
2970          * An errata states that gprc actually counts good + missed packets:
2971          * Workaround to set gprc to summated queue packet receives
2972          */
2973         hw_stats->gprc = *total_qprc;
2974
2975         if (hw->mac.type != ixgbe_mac_82598EB) {
2976                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2977                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2978                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2979                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2980                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2981                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2982                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2983                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2984         } else {
2985                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2986                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2987                 /* 82598 only has a counter in the high register */
2988                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2989                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2990                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2991         }
2992         uint64_t old_tpr = hw_stats->tpr;
2993
2994         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2995         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2996
2997         if (crc_strip == 0)
2998                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2999
3000         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3001         hw_stats->gptc += delta_gptc;
3002         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3003         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3004
3005         /*
3006          * Workaround: mprc hardware is incorrectly counting
3007          * broadcasts, so for now we subtract those.
3008          */
3009         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3010         hw_stats->bprc += bprc;
3011         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3012         if (hw->mac.type == ixgbe_mac_82598EB)
3013                 hw_stats->mprc -= bprc;
3014
3015         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3016         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3017         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3018         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3019         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3020         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3021
3022         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3023         hw_stats->lxontxc += lxon;
3024         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3025         hw_stats->lxofftxc += lxoff;
3026         total = lxon + lxoff;
3027
3028         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3029         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3030         hw_stats->gptc -= total;
3031         hw_stats->mptc -= total;
3032         hw_stats->ptc64 -= total;
3033         hw_stats->gotc -= total * ETHER_MIN_LEN;
3034
3035         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3036         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3037         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3038         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3039         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3040         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3041         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3042         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3043         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3044         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3045         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3046         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3047         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3048         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3049         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3050         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3051         /* Only read FCOE on 82599 */
3052         if (hw->mac.type != ixgbe_mac_82598EB) {
3053                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3054                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3055                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3056                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3057                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3058         }
3059
3060         /* Flow Director Stats registers */
3061         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3062         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3063
3064         /* MACsec Stats registers */
3065         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3066         macsec_stats->out_pkts_encrypted +=
3067                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3068         macsec_stats->out_pkts_protected +=
3069                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3070         macsec_stats->out_octets_encrypted +=
3071                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3072         macsec_stats->out_octets_protected +=
3073                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3074         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3075         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3076         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3077         macsec_stats->in_pkts_unknownsci +=
3078                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3079         macsec_stats->in_octets_decrypted +=
3080                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3081         macsec_stats->in_octets_validated +=
3082                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3083         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3084         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3085         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3086         for (i = 0; i < 2; i++) {
3087                 macsec_stats->in_pkts_ok +=
3088                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3089                 macsec_stats->in_pkts_invalid +=
3090                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3091                 macsec_stats->in_pkts_notvalid +=
3092                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3093         }
3094         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3095         macsec_stats->in_pkts_notusingsa +=
3096                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3097 }
3098
3099 /*
3100  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3101  */
3102 static int
3103 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3104 {
3105         struct ixgbe_hw *hw =
3106                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3107         struct ixgbe_hw_stats *hw_stats =
3108                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3109         struct ixgbe_macsec_stats *macsec_stats =
3110                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3111                                 dev->data->dev_private);
3112         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3113         unsigned i;
3114
3115         total_missed_rx = 0;
3116         total_qbrc = 0;
3117         total_qprc = 0;
3118         total_qprdc = 0;
3119
3120         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3121                         &total_qbrc, &total_qprc, &total_qprdc);
3122
3123         if (stats == NULL)
3124                 return -EINVAL;
3125
3126         /* Fill out the rte_eth_stats statistics structure */
3127         stats->ipackets = total_qprc;
3128         stats->ibytes = total_qbrc;
3129         stats->opackets = hw_stats->gptc;
3130         stats->obytes = hw_stats->gotc;
3131
3132         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3133                 stats->q_ipackets[i] = hw_stats->qprc[i];
3134                 stats->q_opackets[i] = hw_stats->qptc[i];
3135                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3136                 stats->q_obytes[i] = hw_stats->qbtc[i];
3137                 stats->q_errors[i] = hw_stats->qprdc[i];
3138         }
3139
3140         /* Rx Errors */
3141         stats->imissed  = total_missed_rx;
3142         stats->ierrors  = hw_stats->crcerrs +
3143                           hw_stats->mspdc +
3144                           hw_stats->rlec +
3145                           hw_stats->ruc +
3146                           hw_stats->roc +
3147                           hw_stats->illerrc +
3148                           hw_stats->errbc +
3149                           hw_stats->rfc +
3150                           hw_stats->fccrc +
3151                           hw_stats->fclast;
3152
3153         /* Tx Errors */
3154         stats->oerrors  = 0;
3155         return 0;
3156 }
3157
3158 static void
3159 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3160 {
3161         struct ixgbe_hw_stats *stats =
3162                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3163
3164         /* HW registers are cleared on read */
3165         ixgbe_dev_stats_get(dev, NULL);
3166
3167         /* Reset software totals */
3168         memset(stats, 0, sizeof(*stats));
3169 }
3170
3171 /* This function calculates the number of xstats based on the current config */
3172 static unsigned
3173 ixgbe_xstats_calc_num(void) {
3174         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3175                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3176                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3177 }
3178
3179 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3180         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3181 {
3182         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3183         unsigned stat, i, count;
3184
3185         if (xstats_names != NULL) {
3186                 count = 0;
3187
3188                 /* Note: limit >= cnt_stats checked upstream
3189                  * in rte_eth_xstats_names()
3190                  */
3191
3192                 /* Extended stats from ixgbe_hw_stats */
3193                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3194                         snprintf(xstats_names[count].name,
3195                                 sizeof(xstats_names[count].name),
3196                                 "%s",
3197                                 rte_ixgbe_stats_strings[i].name);
3198                         count++;
3199                 }
3200
3201                 /* MACsec Stats */
3202                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3203                         snprintf(xstats_names[count].name,
3204                                 sizeof(xstats_names[count].name),
3205                                 "%s",
3206                                 rte_ixgbe_macsec_strings[i].name);
3207                         count++;
3208                 }
3209
3210                 /* RX Priority Stats */
3211                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3212                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3213                                 snprintf(xstats_names[count].name,
3214                                         sizeof(xstats_names[count].name),
3215                                         "rx_priority%u_%s", i,
3216                                         rte_ixgbe_rxq_strings[stat].name);
3217                                 count++;
3218                         }
3219                 }
3220
3221                 /* TX Priority Stats */
3222                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3223                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3224                                 snprintf(xstats_names[count].name,
3225                                         sizeof(xstats_names[count].name),
3226                                         "tx_priority%u_%s", i,
3227                                         rte_ixgbe_txq_strings[stat].name);
3228                                 count++;
3229                         }
3230                 }
3231         }
3232         return cnt_stats;
3233 }
3234
3235 static int ixgbe_dev_xstats_get_names_by_id(
3236         struct rte_eth_dev *dev,
3237         struct rte_eth_xstat_name *xstats_names,
3238         const uint64_t *ids,
3239         unsigned int limit)
3240 {
3241         if (!ids) {
3242                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3243                 unsigned int stat, i, count;
3244
3245                 if (xstats_names != NULL) {
3246                         count = 0;
3247
3248                         /* Note: limit >= cnt_stats checked upstream
3249                          * in rte_eth_xstats_names()
3250                          */
3251
3252                         /* Extended stats from ixgbe_hw_stats */
3253                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3254                                 snprintf(xstats_names[count].name,
3255                                         sizeof(xstats_names[count].name),
3256                                         "%s",
3257                                         rte_ixgbe_stats_strings[i].name);
3258                                 count++;
3259                         }
3260
3261                         /* MACsec Stats */
3262                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3263                                 snprintf(xstats_names[count].name,
3264                                         sizeof(xstats_names[count].name),
3265                                         "%s",
3266                                         rte_ixgbe_macsec_strings[i].name);
3267                                 count++;
3268                         }
3269
3270                         /* RX Priority Stats */
3271                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3272                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3273                                         snprintf(xstats_names[count].name,
3274                                             sizeof(xstats_names[count].name),
3275                                             "rx_priority%u_%s", i,
3276                                             rte_ixgbe_rxq_strings[stat].name);
3277                                         count++;
3278                                 }
3279                         }
3280
3281                         /* TX Priority Stats */
3282                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3283                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3284                                         snprintf(xstats_names[count].name,
3285                                             sizeof(xstats_names[count].name),
3286                                             "tx_priority%u_%s", i,
3287                                             rte_ixgbe_txq_strings[stat].name);
3288                                         count++;
3289                                 }
3290                         }
3291                 }
3292                 return cnt_stats;
3293         }
3294
3295         uint16_t i;
3296         uint16_t size = ixgbe_xstats_calc_num();
3297         struct rte_eth_xstat_name xstats_names_copy[size];
3298
3299         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3300                         size);
3301
3302         for (i = 0; i < limit; i++) {
3303                 if (ids[i] >= size) {
3304                         PMD_INIT_LOG(ERR, "id value isn't valid");
3305                         return -1;
3306                 }
3307                 strcpy(xstats_names[i].name,
3308                                 xstats_names_copy[ids[i]].name);
3309         }
3310         return limit;
3311 }
3312
3313 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3314         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3315 {
3316         unsigned i;
3317
3318         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3319                 return -ENOMEM;
3320
3321         if (xstats_names != NULL)
3322                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3323                         snprintf(xstats_names[i].name,
3324                                 sizeof(xstats_names[i].name),
3325                                 "%s", rte_ixgbevf_stats_strings[i].name);
3326         return IXGBEVF_NB_XSTATS;
3327 }
3328
3329 static int
3330 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3331                                          unsigned n)
3332 {
3333         struct ixgbe_hw *hw =
3334                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3335         struct ixgbe_hw_stats *hw_stats =
3336                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3337         struct ixgbe_macsec_stats *macsec_stats =
3338                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3339                                 dev->data->dev_private);
3340         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3341         unsigned i, stat, count = 0;
3342
3343         count = ixgbe_xstats_calc_num();
3344
3345         if (n < count)
3346                 return count;
3347
3348         total_missed_rx = 0;
3349         total_qbrc = 0;
3350         total_qprc = 0;
3351         total_qprdc = 0;
3352
3353         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3354                         &total_qbrc, &total_qprc, &total_qprdc);
3355
3356         /* If this is a reset xstats is NULL, and we have cleared the
3357          * registers by reading them.
3358          */
3359         if (!xstats)
3360                 return 0;
3361
3362         /* Extended stats from ixgbe_hw_stats */
3363         count = 0;
3364         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3365                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3366                                 rte_ixgbe_stats_strings[i].offset);
3367                 xstats[count].id = count;
3368                 count++;
3369         }
3370
3371         /* MACsec Stats */
3372         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3373                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3374                                 rte_ixgbe_macsec_strings[i].offset);
3375                 xstats[count].id = count;
3376                 count++;
3377         }
3378
3379         /* RX Priority Stats */
3380         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3381                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3382                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3383                                         rte_ixgbe_rxq_strings[stat].offset +
3384                                         (sizeof(uint64_t) * i));
3385                         xstats[count].id = count;
3386                         count++;
3387                 }
3388         }
3389
3390         /* TX Priority Stats */
3391         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3392                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3393                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3394                                         rte_ixgbe_txq_strings[stat].offset +
3395                                         (sizeof(uint64_t) * i));
3396                         xstats[count].id = count;
3397                         count++;
3398                 }
3399         }
3400         return count;
3401 }
3402
3403 static int
3404 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3405                 uint64_t *values, unsigned int n)
3406 {
3407         if (!ids) {
3408                 struct ixgbe_hw *hw =
3409                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3410                 struct ixgbe_hw_stats *hw_stats =
3411                                 IXGBE_DEV_PRIVATE_TO_STATS(
3412                                                 dev->data->dev_private);
3413                 struct ixgbe_macsec_stats *macsec_stats =
3414                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3415                                         dev->data->dev_private);
3416                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3417                 unsigned int i, stat, count = 0;
3418
3419                 count = ixgbe_xstats_calc_num();
3420
3421                 if (!ids && n < count)
3422                         return count;
3423
3424                 total_missed_rx = 0;
3425                 total_qbrc = 0;
3426                 total_qprc = 0;
3427                 total_qprdc = 0;
3428
3429                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3430                                 &total_missed_rx, &total_qbrc, &total_qprc,
3431                                 &total_qprdc);
3432
3433                 /* If this is a reset xstats is NULL, and we have cleared the
3434                  * registers by reading them.
3435                  */
3436                 if (!ids && !values)
3437                         return 0;
3438
3439                 /* Extended stats from ixgbe_hw_stats */
3440                 count = 0;
3441                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3442                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3443                                         rte_ixgbe_stats_strings[i].offset);
3444                         count++;
3445                 }
3446
3447                 /* MACsec Stats */
3448                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3449                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3450                                         rte_ixgbe_macsec_strings[i].offset);
3451                         count++;
3452                 }
3453
3454                 /* RX Priority Stats */
3455                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3456                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3457                                 values[count] =
3458                                         *(uint64_t *)(((char *)hw_stats) +
3459                                         rte_ixgbe_rxq_strings[stat].offset +
3460                                         (sizeof(uint64_t) * i));
3461                                 count++;
3462                         }
3463                 }
3464
3465                 /* TX Priority Stats */
3466                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3467                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3468                                 values[count] =
3469                                         *(uint64_t *)(((char *)hw_stats) +
3470                                         rte_ixgbe_txq_strings[stat].offset +
3471                                         (sizeof(uint64_t) * i));
3472                                 count++;
3473                         }
3474                 }
3475                 return count;
3476         }
3477
3478         uint16_t i;
3479         uint16_t size = ixgbe_xstats_calc_num();
3480         uint64_t values_copy[size];
3481
3482         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3483
3484         for (i = 0; i < n; i++) {
3485                 if (ids[i] >= size) {
3486                         PMD_INIT_LOG(ERR, "id value isn't valid");
3487                         return -1;
3488                 }
3489                 values[i] = values_copy[ids[i]];
3490         }
3491         return n;
3492 }
3493
3494 static void
3495 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3496 {
3497         struct ixgbe_hw_stats *stats =
3498                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3499         struct ixgbe_macsec_stats *macsec_stats =
3500                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3501                                 dev->data->dev_private);
3502
3503         unsigned count = ixgbe_xstats_calc_num();
3504
3505         /* HW registers are cleared on read */
3506         ixgbe_dev_xstats_get(dev, NULL, count);
3507
3508         /* Reset software totals */
3509         memset(stats, 0, sizeof(*stats));
3510         memset(macsec_stats, 0, sizeof(*macsec_stats));
3511 }
3512
3513 static void
3514 ixgbevf_update_stats(struct rte_eth_dev *dev)
3515 {
3516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3517         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3518                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3519
3520         /* Good Rx packet, include VF loopback */
3521         UPDATE_VF_STAT(IXGBE_VFGPRC,
3522             hw_stats->last_vfgprc, hw_stats->vfgprc);
3523
3524         /* Good Rx octets, include VF loopback */
3525         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3526             hw_stats->last_vfgorc, hw_stats->vfgorc);
3527
3528         /* Good Tx packet, include VF loopback */
3529         UPDATE_VF_STAT(IXGBE_VFGPTC,
3530             hw_stats->last_vfgptc, hw_stats->vfgptc);
3531
3532         /* Good Tx octets, include VF loopback */
3533         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3534             hw_stats->last_vfgotc, hw_stats->vfgotc);
3535
3536         /* Rx Multicst Packet */
3537         UPDATE_VF_STAT(IXGBE_VFMPRC,
3538             hw_stats->last_vfmprc, hw_stats->vfmprc);
3539 }
3540
3541 static int
3542 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3543                        unsigned n)
3544 {
3545         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3546                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3547         unsigned i;
3548
3549         if (n < IXGBEVF_NB_XSTATS)
3550                 return IXGBEVF_NB_XSTATS;
3551
3552         ixgbevf_update_stats(dev);
3553
3554         if (!xstats)
3555                 return 0;
3556
3557         /* Extended stats */
3558         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3559                 xstats[i].id = i;
3560                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3561                         rte_ixgbevf_stats_strings[i].offset);
3562         }
3563
3564         return IXGBEVF_NB_XSTATS;
3565 }
3566
3567 static int
3568 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3569 {
3570         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3571                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3572
3573         ixgbevf_update_stats(dev);
3574
3575         if (stats == NULL)
3576                 return -EINVAL;
3577
3578         stats->ipackets = hw_stats->vfgprc;
3579         stats->ibytes = hw_stats->vfgorc;
3580         stats->opackets = hw_stats->vfgptc;
3581         stats->obytes = hw_stats->vfgotc;
3582         return 0;
3583 }
3584
3585 static void
3586 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3587 {
3588         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3589                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3590
3591         /* Sync HW register to the last stats */
3592         ixgbevf_dev_stats_get(dev, NULL);
3593
3594         /* reset HW current stats*/
3595         hw_stats->vfgprc = 0;
3596         hw_stats->vfgorc = 0;
3597         hw_stats->vfgptc = 0;
3598         hw_stats->vfgotc = 0;
3599 }
3600
3601 static int
3602 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3603 {
3604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605         u16 eeprom_verh, eeprom_verl;
3606         u32 etrack_id;
3607         int ret;
3608
3609         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3610         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3611
3612         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3613         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3614
3615         ret += 1; /* add the size of '\0' */
3616         if (fw_size < (u32)ret)
3617                 return ret;
3618         else
3619                 return 0;
3620 }
3621
3622 static void
3623 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3624 {
3625         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3626         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3627         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3628
3629         dev_info->pci_dev = pci_dev;
3630         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3631         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3632         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3633                 /*
3634                  * When DCB/VT is off, maximum number of queues changes,
3635                  * except for 82598EB, which remains constant.
3636                  */
3637                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3638                                 hw->mac.type != ixgbe_mac_82598EB)
3639                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3640         }
3641         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3642         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3643         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3644         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3645         dev_info->max_vfs = pci_dev->max_vfs;
3646         if (hw->mac.type == ixgbe_mac_82598EB)
3647                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3648         else
3649                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3650         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3651         dev_info->rx_offload_capa =
3652                 DEV_RX_OFFLOAD_VLAN_STRIP |
3653                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3654                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3655                 DEV_RX_OFFLOAD_TCP_CKSUM;
3656
3657         /*
3658          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3659          * mode.
3660          */
3661         if ((hw->mac.type == ixgbe_mac_82599EB ||
3662              hw->mac.type == ixgbe_mac_X540) &&
3663             !RTE_ETH_DEV_SRIOV(dev).active)
3664                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3665
3666         if (hw->mac.type == ixgbe_mac_82599EB ||
3667             hw->mac.type == ixgbe_mac_X540)
3668                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3669
3670         if (hw->mac.type == ixgbe_mac_X550 ||
3671             hw->mac.type == ixgbe_mac_X550EM_x ||
3672             hw->mac.type == ixgbe_mac_X550EM_a)
3673                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3674
3675         dev_info->tx_offload_capa =
3676                 DEV_TX_OFFLOAD_VLAN_INSERT |
3677                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3678                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3679                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3680                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3681                 DEV_TX_OFFLOAD_TCP_TSO;
3682
3683         if (hw->mac.type == ixgbe_mac_82599EB ||
3684             hw->mac.type == ixgbe_mac_X540)
3685                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3686
3687         if (hw->mac.type == ixgbe_mac_X550 ||
3688             hw->mac.type == ixgbe_mac_X550EM_x ||
3689             hw->mac.type == ixgbe_mac_X550EM_a)
3690                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3691
3692 #ifdef RTE_LIBRTE_SECURITY
3693         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3694         dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3695 #endif
3696
3697         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3698                 .rx_thresh = {
3699                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3700                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3701                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3702                 },
3703                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3704                 .rx_drop_en = 0,
3705         };
3706
3707         dev_info->default_txconf = (struct rte_eth_txconf) {
3708                 .tx_thresh = {
3709                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3710                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3711                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3712                 },
3713                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3714                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3715                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3716                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3717         };
3718
3719         dev_info->rx_desc_lim = rx_desc_lim;
3720         dev_info->tx_desc_lim = tx_desc_lim;
3721
3722         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3723         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3724         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3725
3726         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3727         if (hw->mac.type == ixgbe_mac_X540 ||
3728             hw->mac.type == ixgbe_mac_X540_vf ||
3729             hw->mac.type == ixgbe_mac_X550 ||
3730             hw->mac.type == ixgbe_mac_X550_vf) {
3731                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3732         }
3733         if (hw->mac.type == ixgbe_mac_X550) {
3734                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3735                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3736         }
3737 }
3738
3739 static const uint32_t *
3740 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3741 {
3742         static const uint32_t ptypes[] = {
3743                 /* For non-vec functions,
3744                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3745                  * for vec functions,
3746                  * refers to _recv_raw_pkts_vec().
3747                  */
3748                 RTE_PTYPE_L2_ETHER,
3749                 RTE_PTYPE_L3_IPV4,
3750                 RTE_PTYPE_L3_IPV4_EXT,
3751                 RTE_PTYPE_L3_IPV6,
3752                 RTE_PTYPE_L3_IPV6_EXT,
3753                 RTE_PTYPE_L4_SCTP,
3754                 RTE_PTYPE_L4_TCP,
3755                 RTE_PTYPE_L4_UDP,
3756                 RTE_PTYPE_TUNNEL_IP,
3757                 RTE_PTYPE_INNER_L3_IPV6,
3758                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3759                 RTE_PTYPE_INNER_L4_TCP,
3760                 RTE_PTYPE_INNER_L4_UDP,
3761                 RTE_PTYPE_UNKNOWN
3762         };
3763
3764         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3765             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3766             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3767             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3768                 return ptypes;
3769
3770 #if defined(RTE_ARCH_X86)
3771         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3772             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3773                 return ptypes;
3774 #endif
3775         return NULL;
3776 }
3777
3778 static void
3779 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3780                      struct rte_eth_dev_info *dev_info)
3781 {
3782         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784
3785         dev_info->pci_dev = pci_dev;
3786         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3787         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3788         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3789         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3790         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3791         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3792         dev_info->max_vfs = pci_dev->max_vfs;
3793         if (hw->mac.type == ixgbe_mac_82598EB)
3794                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3795         else
3796                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3797         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3798                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3799                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3800                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3801         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3802                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3803                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3804                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3805                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3806                                 DEV_TX_OFFLOAD_TCP_TSO;
3807
3808         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3809                 .rx_thresh = {
3810                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3811                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3812                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3813                 },
3814                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3815                 .rx_drop_en = 0,
3816         };
3817
3818         dev_info->default_txconf = (struct rte_eth_txconf) {
3819                 .tx_thresh = {
3820                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3821                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3822                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3823                 },
3824                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3825                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3826                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3827                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3828         };
3829
3830         dev_info->rx_desc_lim = rx_desc_lim;
3831         dev_info->tx_desc_lim = tx_desc_lim;
3832 }
3833
3834 static int
3835 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3836                    int *link_up, int wait_to_complete)
3837 {
3838         /**
3839          * for a quick link status checking, wait_to_compelet == 0,
3840          * skip PF link status checking
3841          */
3842         bool no_pflink_check = wait_to_complete == 0;
3843         struct ixgbe_mbx_info *mbx = &hw->mbx;
3844         struct ixgbe_mac_info *mac = &hw->mac;
3845         uint32_t links_reg, in_msg;
3846         int ret_val = 0;
3847
3848         /* If we were hit with a reset drop the link */
3849         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3850                 mac->get_link_status = true;
3851
3852         if (!mac->get_link_status)
3853                 goto out;
3854
3855         /* if link status is down no point in checking to see if pf is up */
3856         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3857         if (!(links_reg & IXGBE_LINKS_UP))
3858                 goto out;
3859
3860         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3861          * before the link status is correct
3862          */
3863         if (mac->type == ixgbe_mac_82599_vf) {
3864                 int i;
3865
3866                 for (i = 0; i < 5; i++) {
3867                         rte_delay_us(100);
3868                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3869
3870                         if (!(links_reg & IXGBE_LINKS_UP))
3871                                 goto out;
3872                 }
3873         }
3874
3875         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3876         case IXGBE_LINKS_SPEED_10G_82599:
3877                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3878                 if (hw->mac.type >= ixgbe_mac_X550) {
3879                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3880                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3881                 }
3882                 break;
3883         case IXGBE_LINKS_SPEED_1G_82599:
3884                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3885                 break;
3886         case IXGBE_LINKS_SPEED_100_82599:
3887                 *speed = IXGBE_LINK_SPEED_100_FULL;
3888                 if (hw->mac.type == ixgbe_mac_X550) {
3889                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3890                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3891                 }
3892                 break;
3893         case IXGBE_LINKS_SPEED_10_X550EM_A:
3894                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3895                 /* Since Reserved in older MAC's */
3896                 if (hw->mac.type >= ixgbe_mac_X550)
3897                         *speed = IXGBE_LINK_SPEED_10_FULL;
3898                 break;
3899         default:
3900                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3901         }
3902
3903         if (no_pflink_check) {
3904                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3905                         mac->get_link_status = true;
3906                 else
3907                         mac->get_link_status = false;
3908
3909                 goto out;
3910         }
3911         /* if the read failed it could just be a mailbox collision, best wait
3912          * until we are called again and don't report an error
3913          */
3914         if (mbx->ops.read(hw, &in_msg, 1, 0))
3915                 goto out;
3916
3917         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3918                 /* msg is not CTS and is NACK we must have lost CTS status */
3919                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3920                         ret_val = -1;
3921                 goto out;
3922         }
3923
3924         /* the pf is talking, if we timed out in the past we reinit */
3925         if (!mbx->timeout) {
3926                 ret_val = -1;
3927                 goto out;
3928         }
3929
3930         /* if we passed all the tests above then the link is up and we no
3931          * longer need to check for link
3932          */
3933         mac->get_link_status = false;
3934
3935 out:
3936         *link_up = !mac->get_link_status;
3937         return ret_val;
3938 }
3939
3940 /* return 0 means link status changed, -1 means not changed */
3941 static int
3942 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3943                             int wait_to_complete, int vf)
3944 {
3945         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3946         struct rte_eth_link link, old;
3947         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3948         struct ixgbe_interrupt *intr =
3949                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3950         int link_up;
3951         int diag;
3952         u32 speed = 0;
3953         int wait = 1;
3954         bool autoneg = false;
3955
3956         link.link_status = ETH_LINK_DOWN;
3957         link.link_speed = 0;
3958         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3959         link.link_autoneg = ETH_LINK_AUTONEG;
3960         memset(&old, 0, sizeof(old));
3961         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3962
3963         hw->mac.get_link_status = true;
3964
3965         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3966                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3967                 speed = hw->phy.autoneg_advertised;
3968                 if (!speed)
3969                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3970                 ixgbe_setup_link(hw, speed, true);
3971         }
3972
3973         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3974         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3975                 wait = 0;
3976
3977         if (vf)
3978                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3979         else
3980                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3981
3982         if (diag != 0) {
3983                 link.link_speed = ETH_SPEED_NUM_100M;
3984                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3985                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3986                 if (link.link_status == old.link_status)
3987                         return -1;
3988                 return 0;
3989         }
3990
3991         if (link_up == 0) {
3992                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3993                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3994                 if (link.link_status == old.link_status)
3995                         return -1;
3996                 return 0;
3997         }
3998         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3999         link.link_status = ETH_LINK_UP;
4000         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4001
4002         switch (link_speed) {
4003         default:
4004         case IXGBE_LINK_SPEED_UNKNOWN:
4005                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4006                 link.link_speed = ETH_SPEED_NUM_100M;
4007                 break;
4008
4009         case IXGBE_LINK_SPEED_100_FULL:
4010                 link.link_speed = ETH_SPEED_NUM_100M;
4011                 break;
4012
4013         case IXGBE_LINK_SPEED_1GB_FULL:
4014                 link.link_speed = ETH_SPEED_NUM_1G;
4015                 break;
4016
4017         case IXGBE_LINK_SPEED_2_5GB_FULL:
4018                 link.link_speed = ETH_SPEED_NUM_2_5G;
4019                 break;
4020
4021         case IXGBE_LINK_SPEED_5GB_FULL:
4022                 link.link_speed = ETH_SPEED_NUM_5G;
4023                 break;
4024
4025         case IXGBE_LINK_SPEED_10GB_FULL:
4026                 link.link_speed = ETH_SPEED_NUM_10G;
4027                 break;
4028         }
4029         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4030
4031         if (link.link_status == old.link_status)
4032                 return -1;
4033
4034         return 0;
4035 }
4036
4037 static int
4038 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4039 {
4040         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4041 }
4042
4043 static int
4044 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4045 {
4046         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4047 }
4048
4049 static void
4050 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4051 {
4052         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4053         uint32_t fctrl;
4054
4055         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4056         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4057         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4058 }
4059
4060 static void
4061 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4062 {
4063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4064         uint32_t fctrl;
4065
4066         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4067         fctrl &= (~IXGBE_FCTRL_UPE);
4068         if (dev->data->all_multicast == 1)
4069                 fctrl |= IXGBE_FCTRL_MPE;
4070         else
4071                 fctrl &= (~IXGBE_FCTRL_MPE);
4072         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4073 }
4074
4075 static void
4076 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4077 {
4078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4079         uint32_t fctrl;
4080
4081         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4082         fctrl |= IXGBE_FCTRL_MPE;
4083         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4084 }
4085
4086 static void
4087 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4088 {
4089         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4090         uint32_t fctrl;
4091
4092         if (dev->data->promiscuous == 1)
4093                 return; /* must remain in all_multicast mode */
4094
4095         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4096         fctrl &= (~IXGBE_FCTRL_MPE);
4097         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4098 }
4099
4100 /**
4101  * It clears the interrupt causes and enables the interrupt.
4102  * It will be called once only during nic initialized.
4103  *
4104  * @param dev
4105  *  Pointer to struct rte_eth_dev.
4106  * @param on
4107  *  Enable or Disable.
4108  *
4109  * @return
4110  *  - On success, zero.
4111  *  - On failure, a negative value.
4112  */
4113 static int
4114 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4115 {
4116         struct ixgbe_interrupt *intr =
4117                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4118
4119         ixgbe_dev_link_status_print(dev);
4120         if (on)
4121                 intr->mask |= IXGBE_EICR_LSC;
4122         else
4123                 intr->mask &= ~IXGBE_EICR_LSC;
4124
4125         return 0;
4126 }
4127
4128 /**
4129  * It clears the interrupt causes and enables the interrupt.
4130  * It will be called once only during nic initialized.
4131  *
4132  * @param dev
4133  *  Pointer to struct rte_eth_dev.
4134  *
4135  * @return
4136  *  - On success, zero.
4137  *  - On failure, a negative value.
4138  */
4139 static int
4140 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4141 {
4142         struct ixgbe_interrupt *intr =
4143                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4144
4145         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4146
4147         return 0;
4148 }
4149
4150 /**
4151  * It clears the interrupt causes and enables the interrupt.
4152  * It will be called once only during nic initialized.
4153  *
4154  * @param dev
4155  *  Pointer to struct rte_eth_dev.
4156  *
4157  * @return
4158  *  - On success, zero.
4159  *  - On failure, a negative value.
4160  */
4161 static int
4162 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4163 {
4164         struct ixgbe_interrupt *intr =
4165                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4166
4167         intr->mask |= IXGBE_EICR_LINKSEC;
4168
4169         return 0;
4170 }
4171
4172 /*
4173  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4174  *
4175  * @param dev
4176  *  Pointer to struct rte_eth_dev.
4177  *
4178  * @return
4179  *  - On success, zero.
4180  *  - On failure, a negative value.
4181  */
4182 static int
4183 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4184 {
4185         uint32_t eicr;
4186         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4187         struct ixgbe_interrupt *intr =
4188                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4189
4190         /* clear all cause mask */
4191         ixgbe_disable_intr(hw);
4192
4193         /* read-on-clear nic registers here */
4194         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4195         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4196
4197         intr->flags = 0;
4198
4199         /* set flag for async link update */
4200         if (eicr & IXGBE_EICR_LSC)
4201                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4202
4203         if (eicr & IXGBE_EICR_MAILBOX)
4204                 intr->flags |= IXGBE_FLAG_MAILBOX;
4205
4206         if (eicr & IXGBE_EICR_LINKSEC)
4207                 intr->flags |= IXGBE_FLAG_MACSEC;
4208
4209         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4210             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4211             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4212                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4213
4214         return 0;
4215 }
4216
4217 /**
4218  * It gets and then prints the link status.
4219  *
4220  * @param dev
4221  *  Pointer to struct rte_eth_dev.
4222  *
4223  * @return
4224  *  - On success, zero.
4225  *  - On failure, a negative value.
4226  */
4227 static void
4228 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4229 {
4230         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4231         struct rte_eth_link link;
4232
4233         memset(&link, 0, sizeof(link));
4234         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4235         if (link.link_status) {
4236                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4237                                         (int)(dev->data->port_id),
4238                                         (unsigned)link.link_speed,
4239                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4240                                         "full-duplex" : "half-duplex");
4241         } else {
4242                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4243                                 (int)(dev->data->port_id));
4244         }
4245         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4246                                 pci_dev->addr.domain,
4247                                 pci_dev->addr.bus,
4248                                 pci_dev->addr.devid,
4249                                 pci_dev->addr.function);
4250 }
4251
4252 /*
4253  * It executes link_update after knowing an interrupt occurred.
4254  *
4255  * @param dev
4256  *  Pointer to struct rte_eth_dev.
4257  *
4258  * @return
4259  *  - On success, zero.
4260  *  - On failure, a negative value.
4261  */
4262 static int
4263 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4264                            struct rte_intr_handle *intr_handle)
4265 {
4266         struct ixgbe_interrupt *intr =
4267                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4268         int64_t timeout;
4269         struct rte_eth_link link;
4270         struct ixgbe_hw *hw =
4271                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4272
4273         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4274
4275         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4276                 ixgbe_pf_mbx_process(dev);
4277                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4278         }
4279
4280         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4281                 ixgbe_handle_lasi(hw);
4282                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4283         }
4284
4285         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4286                 /* get the link status before link update, for predicting later */
4287                 memset(&link, 0, sizeof(link));
4288                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4289
4290                 ixgbe_dev_link_update(dev, 0);
4291
4292                 /* likely to up */
4293                 if (!link.link_status)
4294                         /* handle it 1 sec later, wait it being stable */
4295                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4296                 /* likely to down */
4297                 else
4298                         /* handle it 4 sec later, wait it being stable */
4299                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4300
4301                 ixgbe_dev_link_status_print(dev);
4302                 if (rte_eal_alarm_set(timeout * 1000,
4303                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4304                         PMD_DRV_LOG(ERR, "Error setting alarm");
4305                 else {
4306                         /* remember original mask */
4307                         intr->mask_original = intr->mask;
4308                         /* only disable lsc interrupt */
4309                         intr->mask &= ~IXGBE_EIMS_LSC;
4310                 }
4311         }
4312
4313         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4314         ixgbe_enable_intr(dev);
4315         rte_intr_enable(intr_handle);
4316
4317         return 0;
4318 }
4319
4320 /**
4321  * Interrupt handler which shall be registered for alarm callback for delayed
4322  * handling specific interrupt to wait for the stable nic state. As the
4323  * NIC interrupt state is not stable for ixgbe after link is just down,
4324  * it needs to wait 4 seconds to get the stable status.
4325  *
4326  * @param handle
4327  *  Pointer to interrupt handle.
4328  * @param param
4329  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4330  *
4331  * @return
4332  *  void
4333  */
4334 static void
4335 ixgbe_dev_interrupt_delayed_handler(void *param)
4336 {
4337         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4338         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4339         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4340         struct ixgbe_interrupt *intr =
4341                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4342         struct ixgbe_hw *hw =
4343                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4344         uint32_t eicr;
4345
4346         ixgbe_disable_intr(hw);
4347
4348         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4349         if (eicr & IXGBE_EICR_MAILBOX)
4350                 ixgbe_pf_mbx_process(dev);
4351
4352         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4353                 ixgbe_handle_lasi(hw);
4354                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4355         }
4356
4357         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4358                 ixgbe_dev_link_update(dev, 0);
4359                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4360                 ixgbe_dev_link_status_print(dev);
4361                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4362                                               NULL);
4363         }
4364
4365         if (intr->flags & IXGBE_FLAG_MACSEC) {
4366                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4367                                               NULL);
4368                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4369         }
4370
4371         /* restore original mask */
4372         intr->mask = intr->mask_original;
4373         intr->mask_original = 0;
4374
4375         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4376         ixgbe_enable_intr(dev);
4377         rte_intr_enable(intr_handle);
4378 }
4379
4380 /**
4381  * Interrupt handler triggered by NIC  for handling
4382  * specific interrupt.
4383  *
4384  * @param handle
4385  *  Pointer to interrupt handle.
4386  * @param param
4387  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4388  *
4389  * @return
4390  *  void
4391  */
4392 static void
4393 ixgbe_dev_interrupt_handler(void *param)
4394 {
4395         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4396
4397         ixgbe_dev_interrupt_get_status(dev);
4398         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4399 }
4400
4401 static int
4402 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4403 {
4404         struct ixgbe_hw *hw;
4405
4406         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4408 }
4409
4410 static int
4411 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4412 {
4413         struct ixgbe_hw *hw;
4414
4415         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4416         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4417 }
4418
4419 static int
4420 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4421 {
4422         struct ixgbe_hw *hw;
4423         uint32_t mflcn_reg;
4424         uint32_t fccfg_reg;
4425         int rx_pause;
4426         int tx_pause;
4427
4428         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4429
4430         fc_conf->pause_time = hw->fc.pause_time;
4431         fc_conf->high_water = hw->fc.high_water[0];
4432         fc_conf->low_water = hw->fc.low_water[0];
4433         fc_conf->send_xon = hw->fc.send_xon;
4434         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4435
4436         /*
4437          * Return rx_pause status according to actual setting of
4438          * MFLCN register.
4439          */
4440         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4441         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4442                 rx_pause = 1;
4443         else
4444                 rx_pause = 0;
4445
4446         /*
4447          * Return tx_pause status according to actual setting of
4448          * FCCFG register.
4449          */
4450         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4451         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4452                 tx_pause = 1;
4453         else
4454                 tx_pause = 0;
4455
4456         if (rx_pause && tx_pause)
4457                 fc_conf->mode = RTE_FC_FULL;
4458         else if (rx_pause)
4459                 fc_conf->mode = RTE_FC_RX_PAUSE;
4460         else if (tx_pause)
4461                 fc_conf->mode = RTE_FC_TX_PAUSE;
4462         else
4463                 fc_conf->mode = RTE_FC_NONE;
4464
4465         return 0;
4466 }
4467
4468 static int
4469 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4470 {
4471         struct ixgbe_hw *hw;
4472         int err;
4473         uint32_t rx_buf_size;
4474         uint32_t max_high_water;
4475         uint32_t mflcn;
4476         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4477                 ixgbe_fc_none,
4478                 ixgbe_fc_rx_pause,
4479                 ixgbe_fc_tx_pause,
4480                 ixgbe_fc_full
4481         };
4482
4483         PMD_INIT_FUNC_TRACE();
4484
4485         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4486         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4487         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4488
4489         /*
4490          * At least reserve one Ethernet frame for watermark
4491          * high_water/low_water in kilo bytes for ixgbe
4492          */
4493         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4494         if ((fc_conf->high_water > max_high_water) ||
4495                 (fc_conf->high_water < fc_conf->low_water)) {
4496                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4497                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4498                 return -EINVAL;
4499         }
4500
4501         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4502         hw->fc.pause_time     = fc_conf->pause_time;
4503         hw->fc.high_water[0]  = fc_conf->high_water;
4504         hw->fc.low_water[0]   = fc_conf->low_water;
4505         hw->fc.send_xon       = fc_conf->send_xon;
4506         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4507
4508         err = ixgbe_fc_enable(hw);
4509
4510         /* Not negotiated is not an error case */
4511         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4512
4513                 /* check if we want to forward MAC frames - driver doesn't have native
4514                  * capability to do that, so we'll write the registers ourselves */
4515
4516                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4517
4518                 /* set or clear MFLCN.PMCF bit depending on configuration */
4519                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4520                         mflcn |= IXGBE_MFLCN_PMCF;
4521                 else
4522                         mflcn &= ~IXGBE_MFLCN_PMCF;
4523
4524                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4525                 IXGBE_WRITE_FLUSH(hw);
4526
4527                 return 0;
4528         }
4529
4530         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4531         return -EIO;
4532 }
4533
4534 /**
4535  *  ixgbe_pfc_enable_generic - Enable flow control
4536  *  @hw: pointer to hardware structure
4537  *  @tc_num: traffic class number
4538  *  Enable flow control according to the current settings.
4539  */
4540 static int
4541 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4542 {
4543         int ret_val = 0;
4544         uint32_t mflcn_reg, fccfg_reg;
4545         uint32_t reg;
4546         uint32_t fcrtl, fcrth;
4547         uint8_t i;
4548         uint8_t nb_rx_en;
4549
4550         /* Validate the water mark configuration */
4551         if (!hw->fc.pause_time) {
4552                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4553                 goto out;
4554         }
4555
4556         /* Low water mark of zero causes XOFF floods */
4557         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4558                  /* High/Low water can not be 0 */
4559                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4560                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4561                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4562                         goto out;
4563                 }
4564
4565                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4566                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4567                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4568                         goto out;
4569                 }
4570         }
4571         /* Negotiate the fc mode to use */
4572         ixgbe_fc_autoneg(hw);
4573
4574         /* Disable any previous flow control settings */
4575         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4576         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4577
4578         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4579         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4580
4581         switch (hw->fc.current_mode) {
4582         case ixgbe_fc_none:
4583                 /*
4584                  * If the count of enabled RX Priority Flow control >1,
4585                  * and the TX pause can not be disabled
4586                  */
4587                 nb_rx_en = 0;
4588                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4589                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4590                         if (reg & IXGBE_FCRTH_FCEN)
4591                                 nb_rx_en++;
4592                 }
4593                 if (nb_rx_en > 1)
4594                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4595                 break;
4596         case ixgbe_fc_rx_pause:
4597                 /*
4598                  * Rx Flow control is enabled and Tx Flow control is
4599                  * disabled by software override. Since there really
4600                  * isn't a way to advertise that we are capable of RX
4601                  * Pause ONLY, we will advertise that we support both
4602                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4603                  * disable the adapter's ability to send PAUSE frames.
4604                  */
4605                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4606                 /*
4607                  * If the count of enabled RX Priority Flow control >1,
4608                  * and the TX pause can not be disabled
4609                  */
4610                 nb_rx_en = 0;
4611                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4612                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4613                         if (reg & IXGBE_FCRTH_FCEN)
4614                                 nb_rx_en++;
4615                 }
4616                 if (nb_rx_en > 1)
4617                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4618                 break;
4619         case ixgbe_fc_tx_pause:
4620                 /*
4621                  * Tx Flow control is enabled, and Rx Flow control is
4622                  * disabled by software override.
4623                  */
4624                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4625                 break;
4626         case ixgbe_fc_full:
4627                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4628                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4629                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4630                 break;
4631         default:
4632                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4633                 ret_val = IXGBE_ERR_CONFIG;
4634                 goto out;
4635         }
4636
4637         /* Set 802.3x based flow control settings. */
4638         mflcn_reg |= IXGBE_MFLCN_DPF;
4639         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4640         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4641
4642         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4643         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4644                 hw->fc.high_water[tc_num]) {
4645                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4646                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4647                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4648         } else {
4649                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4650                 /*
4651                  * In order to prevent Tx hangs when the internal Tx
4652                  * switch is enabled we must set the high water mark
4653                  * to the maximum FCRTH value.  This allows the Tx
4654                  * switch to function even under heavy Rx workloads.
4655                  */
4656                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4657         }
4658         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4659
4660         /* Configure pause time (2 TCs per register) */
4661         reg = hw->fc.pause_time * 0x00010001;
4662         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4663                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4664
4665         /* Configure flow control refresh threshold value */
4666         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4667
4668 out:
4669         return ret_val;
4670 }
4671
4672 static int
4673 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4674 {
4675         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4676         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4677
4678         if (hw->mac.type != ixgbe_mac_82598EB) {
4679                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4680         }
4681         return ret_val;
4682 }
4683
4684 static int
4685 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4686 {
4687         int err;
4688         uint32_t rx_buf_size;
4689         uint32_t max_high_water;
4690         uint8_t tc_num;
4691         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4692         struct ixgbe_hw *hw =
4693                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4694         struct ixgbe_dcb_config *dcb_config =
4695                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4696
4697         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4698                 ixgbe_fc_none,
4699                 ixgbe_fc_rx_pause,
4700                 ixgbe_fc_tx_pause,
4701                 ixgbe_fc_full
4702         };
4703
4704         PMD_INIT_FUNC_TRACE();
4705
4706         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4707         tc_num = map[pfc_conf->priority];
4708         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4709         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4710         /*
4711          * At least reserve one Ethernet frame for watermark
4712          * high_water/low_water in kilo bytes for ixgbe
4713          */
4714         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4715         if ((pfc_conf->fc.high_water > max_high_water) ||
4716             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4717                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4718                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4719                 return -EINVAL;
4720         }
4721
4722         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4723         hw->fc.pause_time = pfc_conf->fc.pause_time;
4724         hw->fc.send_xon = pfc_conf->fc.send_xon;
4725         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4726         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4727
4728         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4729
4730         /* Not negotiated is not an error case */
4731         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4732                 return 0;
4733
4734         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4735         return -EIO;
4736 }
4737
4738 static int
4739 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4740                           struct rte_eth_rss_reta_entry64 *reta_conf,
4741                           uint16_t reta_size)
4742 {
4743         uint16_t i, sp_reta_size;
4744         uint8_t j, mask;
4745         uint32_t reta, r;
4746         uint16_t idx, shift;
4747         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4748         uint32_t reta_reg;
4749
4750         PMD_INIT_FUNC_TRACE();
4751
4752         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4753                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4754                         "NIC.");
4755                 return -ENOTSUP;
4756         }
4757
4758         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4759         if (reta_size != sp_reta_size) {
4760                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4761                         "(%d) doesn't match the number hardware can supported "
4762                         "(%d)", reta_size, sp_reta_size);
4763                 return -EINVAL;
4764         }
4765
4766         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4767                 idx = i / RTE_RETA_GROUP_SIZE;
4768                 shift = i % RTE_RETA_GROUP_SIZE;
4769                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4770                                                 IXGBE_4_BIT_MASK);
4771                 if (!mask)
4772                         continue;
4773                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4774                 if (mask == IXGBE_4_BIT_MASK)
4775                         r = 0;
4776                 else
4777                         r = IXGBE_READ_REG(hw, reta_reg);
4778                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4779                         if (mask & (0x1 << j))
4780                                 reta |= reta_conf[idx].reta[shift + j] <<
4781                                                         (CHAR_BIT * j);
4782                         else
4783                                 reta |= r & (IXGBE_8_BIT_MASK <<
4784                                                 (CHAR_BIT * j));
4785                 }
4786                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4787         }
4788
4789         return 0;
4790 }
4791
4792 static int
4793 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4794                          struct rte_eth_rss_reta_entry64 *reta_conf,
4795                          uint16_t reta_size)
4796 {
4797         uint16_t i, sp_reta_size;
4798         uint8_t j, mask;
4799         uint32_t reta;
4800         uint16_t idx, shift;
4801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4802         uint32_t reta_reg;
4803
4804         PMD_INIT_FUNC_TRACE();
4805         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4806         if (reta_size != sp_reta_size) {
4807                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4808                         "(%d) doesn't match the number hardware can supported "
4809                         "(%d)", reta_size, sp_reta_size);
4810                 return -EINVAL;
4811         }
4812
4813         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4814                 idx = i / RTE_RETA_GROUP_SIZE;
4815                 shift = i % RTE_RETA_GROUP_SIZE;
4816                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4817                                                 IXGBE_4_BIT_MASK);
4818                 if (!mask)
4819                         continue;
4820
4821                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4822                 reta = IXGBE_READ_REG(hw, reta_reg);
4823                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4824                         if (mask & (0x1 << j))
4825                                 reta_conf[idx].reta[shift + j] =
4826                                         ((reta >> (CHAR_BIT * j)) &
4827                                                 IXGBE_8_BIT_MASK);
4828                 }
4829         }
4830
4831         return 0;
4832 }
4833
4834 static int
4835 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4836                                 uint32_t index, uint32_t pool)
4837 {
4838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839         uint32_t enable_addr = 1;
4840
4841         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4842                              pool, enable_addr);
4843 }
4844
4845 static void
4846 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4847 {
4848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4849
4850         ixgbe_clear_rar(hw, index);
4851 }
4852
4853 static void
4854 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4855 {
4856         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4857
4858         ixgbe_remove_rar(dev, 0);
4859
4860         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4861 }
4862
4863 static bool
4864 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4865 {
4866         if (strcmp(dev->device->driver->name, drv->driver.name))
4867                 return false;
4868
4869         return true;
4870 }
4871
4872 bool
4873 is_ixgbe_supported(struct rte_eth_dev *dev)
4874 {
4875         return is_device_supported(dev, &rte_ixgbe_pmd);
4876 }
4877
4878 static int
4879 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4880 {
4881         uint32_t hlreg0;
4882         uint32_t maxfrs;
4883         struct ixgbe_hw *hw;
4884         struct rte_eth_dev_info dev_info;
4885         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4886         struct rte_eth_dev_data *dev_data = dev->data;
4887
4888         ixgbe_dev_info_get(dev, &dev_info);
4889
4890         /* check that mtu is within the allowed range */
4891         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4892                 return -EINVAL;
4893
4894         /* If device is started, refuse mtu that requires the support of
4895          * scattered packets when this feature has not been enabled before.
4896          */
4897         if (dev_data->dev_started && !dev_data->scattered_rx &&
4898             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4899              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4900                 PMD_INIT_LOG(ERR, "Stop port first.");
4901                 return -EINVAL;
4902         }
4903
4904         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4905         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4906
4907         /* switch to jumbo mode if needed */
4908         if (frame_size > ETHER_MAX_LEN) {
4909                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4910                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4911         } else {
4912                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4913                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4914         }
4915         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4916
4917         /* update max frame size */
4918         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4919
4920         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4921         maxfrs &= 0x0000FFFF;
4922         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4923         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4924
4925         return 0;
4926 }
4927
4928 /*
4929  * Virtual Function operations
4930  */
4931 static void
4932 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4933 {
4934         PMD_INIT_FUNC_TRACE();
4935
4936         /* Clear interrupt mask to stop from interrupts being generated */
4937         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4938
4939         IXGBE_WRITE_FLUSH(hw);
4940 }
4941
4942 static void
4943 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4944 {
4945         PMD_INIT_FUNC_TRACE();
4946
4947         /* VF enable interrupt autoclean */
4948         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4949         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4950         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4951
4952         IXGBE_WRITE_FLUSH(hw);
4953 }
4954
4955 static int
4956 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4957 {
4958         struct rte_eth_conf *conf = &dev->data->dev_conf;
4959         struct ixgbe_adapter *adapter =
4960                         (struct ixgbe_adapter *)dev->data->dev_private;
4961
4962         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4963                      dev->data->port_id);
4964
4965         /*
4966          * VF has no ability to enable/disable HW CRC
4967          * Keep the persistent behavior the same as Host PF
4968          */
4969 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4970         if (!conf->rxmode.hw_strip_crc) {
4971                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4972                 conf->rxmode.hw_strip_crc = 1;
4973         }
4974 #else
4975         if (conf->rxmode.hw_strip_crc) {
4976                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4977                 conf->rxmode.hw_strip_crc = 0;
4978         }
4979 #endif
4980
4981         /*
4982          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4983          * allocation or vector Rx preconditions we will reset it.
4984          */
4985         adapter->rx_bulk_alloc_allowed = true;
4986         adapter->rx_vec_allowed = true;
4987
4988         return 0;
4989 }
4990
4991 static int
4992 ixgbevf_dev_start(struct rte_eth_dev *dev)
4993 {
4994         struct ixgbe_hw *hw =
4995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4996         uint32_t intr_vector = 0;
4997         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4998         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4999
5000         int err, mask = 0;
5001
5002         PMD_INIT_FUNC_TRACE();
5003
5004         hw->mac.ops.reset_hw(hw);
5005         hw->mac.get_link_status = true;
5006
5007         /* negotiate mailbox API version to use with the PF. */
5008         ixgbevf_negotiate_api(hw);
5009
5010         ixgbevf_dev_tx_init(dev);
5011
5012         /* This can fail when allocating mbufs for descriptor rings */
5013         err = ixgbevf_dev_rx_init(dev);
5014         if (err) {
5015                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5016                 ixgbe_dev_clear_queues(dev);
5017                 return err;
5018         }
5019
5020         /* Set vfta */
5021         ixgbevf_set_vfta_all(dev, 1);
5022
5023         /* Set HW strip */
5024         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5025                 ETH_VLAN_EXTEND_MASK;
5026         err = ixgbevf_vlan_offload_set(dev, mask);
5027         if (err) {
5028                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5029                 ixgbe_dev_clear_queues(dev);
5030                 return err;
5031         }
5032
5033         ixgbevf_dev_rxtx_start(dev);
5034
5035         /* check and configure queue intr-vector mapping */
5036         if (dev->data->dev_conf.intr_conf.rxq != 0) {
5037                 /* According to datasheet, only vector 0/1/2 can be used,
5038                  * now only one vector is used for Rx queue
5039                  */
5040                 intr_vector = 1;
5041                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5042                         return -1;
5043         }
5044
5045         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5046                 intr_handle->intr_vec =
5047                         rte_zmalloc("intr_vec",
5048                                     dev->data->nb_rx_queues * sizeof(int), 0);
5049                 if (intr_handle->intr_vec == NULL) {
5050                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5051                                      " intr_vec", dev->data->nb_rx_queues);
5052                         return -ENOMEM;
5053                 }
5054         }
5055         ixgbevf_configure_msix(dev);
5056
5057         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5058          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5059          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5060          * is not cleared, it will fail when following rte_intr_enable( ) tries
5061          * to map Rx queue interrupt to other VFIO vectors.
5062          * So clear uio/vfio intr/evevnfd first to avoid failure.
5063          */
5064         rte_intr_disable(intr_handle);
5065
5066         rte_intr_enable(intr_handle);
5067
5068         /* Re-enable interrupt for VF */
5069         ixgbevf_intr_enable(hw);
5070
5071         return 0;
5072 }
5073
5074 static void
5075 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5076 {
5077         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5078         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5079         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5080
5081         PMD_INIT_FUNC_TRACE();
5082
5083         ixgbevf_intr_disable(hw);
5084
5085         hw->adapter_stopped = 1;
5086         ixgbe_stop_adapter(hw);
5087
5088         /*
5089           * Clear what we set, but we still keep shadow_vfta to
5090           * restore after device starts
5091           */
5092         ixgbevf_set_vfta_all(dev, 0);
5093
5094         /* Clear stored conf */
5095         dev->data->scattered_rx = 0;
5096
5097         ixgbe_dev_clear_queues(dev);
5098
5099         /* Clean datapath event and queue/vec mapping */
5100         rte_intr_efd_disable(intr_handle);
5101         if (intr_handle->intr_vec != NULL) {
5102                 rte_free(intr_handle->intr_vec);
5103                 intr_handle->intr_vec = NULL;
5104         }
5105 }
5106
5107 static void
5108 ixgbevf_dev_close(struct rte_eth_dev *dev)
5109 {
5110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5111
5112         PMD_INIT_FUNC_TRACE();
5113
5114         ixgbe_reset_hw(hw);
5115
5116         ixgbevf_dev_stop(dev);
5117
5118         ixgbe_dev_free_queues(dev);
5119
5120         /**
5121          * Remove the VF MAC address ro ensure
5122          * that the VF traffic goes to the PF
5123          * after stop, close and detach of the VF
5124          **/
5125         ixgbevf_remove_mac_addr(dev, 0);
5126 }
5127
5128 /*
5129  * Reset VF device
5130  */
5131 static int
5132 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5133 {
5134         int ret;
5135
5136         ret = eth_ixgbevf_dev_uninit(dev);
5137         if (ret)
5138                 return ret;
5139
5140         ret = eth_ixgbevf_dev_init(dev);
5141
5142         return ret;
5143 }
5144
5145 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5146 {
5147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5148         struct ixgbe_vfta *shadow_vfta =
5149                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5150         int i = 0, j = 0, vfta = 0, mask = 1;
5151
5152         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5153                 vfta = shadow_vfta->vfta[i];
5154                 if (vfta) {
5155                         mask = 1;
5156                         for (j = 0; j < 32; j++) {
5157                                 if (vfta & mask)
5158                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5159                                                        on, false);
5160                                 mask <<= 1;
5161                         }
5162                 }
5163         }
5164
5165 }
5166
5167 static int
5168 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5169 {
5170         struct ixgbe_hw *hw =
5171                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5172         struct ixgbe_vfta *shadow_vfta =
5173                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5174         uint32_t vid_idx = 0;
5175         uint32_t vid_bit = 0;
5176         int ret = 0;
5177
5178         PMD_INIT_FUNC_TRACE();
5179
5180         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5181         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5182         if (ret) {
5183                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5184                 return ret;
5185         }
5186         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5187         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5188
5189         /* Save what we set and retore it after device reset */
5190         if (on)
5191                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5192         else
5193                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5194
5195         return 0;
5196 }
5197
5198 static void
5199 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5200 {
5201         struct ixgbe_hw *hw =
5202                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5203         uint32_t ctrl;
5204
5205         PMD_INIT_FUNC_TRACE();
5206
5207         if (queue >= hw->mac.max_rx_queues)
5208                 return;
5209
5210         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5211         if (on)
5212                 ctrl |= IXGBE_RXDCTL_VME;
5213         else
5214                 ctrl &= ~IXGBE_RXDCTL_VME;
5215         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5216
5217         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5218 }
5219
5220 static int
5221 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5222 {
5223         struct ixgbe_hw *hw =
5224                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225         uint16_t i;
5226         int on = 0;
5227
5228         /* VF function only support hw strip feature, others are not support */
5229         if (mask & ETH_VLAN_STRIP_MASK) {
5230                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5231
5232                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5233                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5234         }
5235
5236         return 0;
5237 }
5238
5239 int
5240 ixgbe_vt_check(struct ixgbe_hw *hw)
5241 {
5242         uint32_t reg_val;
5243
5244         /* if Virtualization Technology is enabled */
5245         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5246         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5247                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5248                 return -1;
5249         }
5250
5251         return 0;
5252 }
5253
5254 static uint32_t
5255 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5256 {
5257         uint32_t vector = 0;
5258
5259         switch (hw->mac.mc_filter_type) {
5260         case 0:   /* use bits [47:36] of the address */
5261                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5262                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5263                 break;
5264         case 1:   /* use bits [46:35] of the address */
5265                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5266                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5267                 break;
5268         case 2:   /* use bits [45:34] of the address */
5269                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5270                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5271                 break;
5272         case 3:   /* use bits [43:32] of the address */
5273                 vector = ((uc_addr->addr_bytes[4]) |
5274                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5275                 break;
5276         default:  /* Invalid mc_filter_type */
5277                 break;
5278         }
5279
5280         /* vector can only be 12-bits or boundary will be exceeded */
5281         vector &= 0xFFF;
5282         return vector;
5283 }
5284
5285 static int
5286 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5287                         uint8_t on)
5288 {
5289         uint32_t vector;
5290         uint32_t uta_idx;
5291         uint32_t reg_val;
5292         uint32_t uta_shift;
5293         uint32_t rc;
5294         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5295         const uint32_t ixgbe_uta_bit_shift = 5;
5296         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5297         const uint32_t bit1 = 0x1;
5298
5299         struct ixgbe_hw *hw =
5300                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5301         struct ixgbe_uta_info *uta_info =
5302                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5303
5304         /* The UTA table only exists on 82599 hardware and newer */
5305         if (hw->mac.type < ixgbe_mac_82599EB)
5306                 return -ENOTSUP;
5307
5308         vector = ixgbe_uta_vector(hw, mac_addr);
5309         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5310         uta_shift = vector & ixgbe_uta_bit_mask;
5311
5312         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5313         if (rc == on)
5314                 return 0;
5315
5316         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5317         if (on) {
5318                 uta_info->uta_in_use++;
5319                 reg_val |= (bit1 << uta_shift);
5320                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5321         } else {
5322                 uta_info->uta_in_use--;
5323                 reg_val &= ~(bit1 << uta_shift);
5324                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5325         }
5326
5327         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5328
5329         if (uta_info->uta_in_use > 0)
5330                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5331                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5332         else
5333                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5334
5335         return 0;
5336 }
5337
5338 static int
5339 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5340 {
5341         int i;
5342         struct ixgbe_hw *hw =
5343                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5344         struct ixgbe_uta_info *uta_info =
5345                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5346
5347         /* The UTA table only exists on 82599 hardware and newer */
5348         if (hw->mac.type < ixgbe_mac_82599EB)
5349                 return -ENOTSUP;
5350
5351         if (on) {
5352                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5353                         uta_info->uta_shadow[i] = ~0;
5354                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5355                 }
5356         } else {
5357                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5358                         uta_info->uta_shadow[i] = 0;
5359                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5360                 }
5361         }
5362         return 0;
5363
5364 }
5365
5366 uint32_t
5367 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5368 {
5369         uint32_t new_val = orig_val;
5370
5371         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5372                 new_val |= IXGBE_VMOLR_AUPE;
5373         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5374                 new_val |= IXGBE_VMOLR_ROMPE;
5375         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5376                 new_val |= IXGBE_VMOLR_ROPE;
5377         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5378                 new_val |= IXGBE_VMOLR_BAM;
5379         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5380                 new_val |= IXGBE_VMOLR_MPE;
5381
5382         return new_val;
5383 }
5384
5385 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5386 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5387 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5388 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5389 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5390         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5391         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5392
5393 static int
5394 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5395                       struct rte_eth_mirror_conf *mirror_conf,
5396                       uint8_t rule_id, uint8_t on)
5397 {
5398         uint32_t mr_ctl, vlvf;
5399         uint32_t mp_lsb = 0;
5400         uint32_t mv_msb = 0;
5401         uint32_t mv_lsb = 0;
5402         uint32_t mp_msb = 0;
5403         uint8_t i = 0;
5404         int reg_index = 0;
5405         uint64_t vlan_mask = 0;
5406
5407         const uint8_t pool_mask_offset = 32;
5408         const uint8_t vlan_mask_offset = 32;
5409         const uint8_t dst_pool_offset = 8;
5410         const uint8_t rule_mr_offset  = 4;
5411         const uint8_t mirror_rule_mask = 0x0F;
5412
5413         struct ixgbe_mirror_info *mr_info =
5414                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5415         struct ixgbe_hw *hw =
5416                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5417         uint8_t mirror_type = 0;
5418
5419         if (ixgbe_vt_check(hw) < 0)
5420                 return -ENOTSUP;
5421
5422         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5423                 return -EINVAL;
5424
5425         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5426                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5427                             mirror_conf->rule_type);
5428                 return -EINVAL;
5429         }
5430
5431         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5432                 mirror_type |= IXGBE_MRCTL_VLME;
5433                 /* Check if vlan id is valid and find conresponding VLAN ID
5434                  * index in VLVF
5435                  */
5436                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5437                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5438                                 /* search vlan id related pool vlan filter
5439                                  * index
5440                                  */
5441                                 reg_index = ixgbe_find_vlvf_slot(
5442                                                 hw,
5443                                                 mirror_conf->vlan.vlan_id[i],
5444                                                 false);
5445                                 if (reg_index < 0)
5446                                         return -EINVAL;
5447                                 vlvf = IXGBE_READ_REG(hw,
5448                                                       IXGBE_VLVF(reg_index));
5449                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5450                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5451                                       mirror_conf->vlan.vlan_id[i]))
5452                                         vlan_mask |= (1ULL << reg_index);
5453                                 else
5454                                         return -EINVAL;
5455                         }
5456                 }
5457
5458                 if (on) {
5459                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5460                         mv_msb = vlan_mask >> vlan_mask_offset;
5461
5462                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5463                                                 mirror_conf->vlan.vlan_mask;
5464                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5465                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5466                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5467                                                 mirror_conf->vlan.vlan_id[i];
5468                         }
5469                 } else {
5470                         mv_lsb = 0;
5471                         mv_msb = 0;
5472                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5473                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5474                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5475                 }
5476         }
5477
5478         /**
5479          * if enable pool mirror, write related pool mask register,if disable
5480          * pool mirror, clear PFMRVM register
5481          */
5482         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5483                 mirror_type |= IXGBE_MRCTL_VPME;
5484                 if (on) {
5485                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5486                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5487                         mr_info->mr_conf[rule_id].pool_mask =
5488                                         mirror_conf->pool_mask;
5489
5490                 } else {
5491                         mp_lsb = 0;
5492                         mp_msb = 0;
5493                         mr_info->mr_conf[rule_id].pool_mask = 0;
5494                 }
5495         }
5496         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5497                 mirror_type |= IXGBE_MRCTL_UPME;
5498         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5499                 mirror_type |= IXGBE_MRCTL_DPME;
5500
5501         /* read  mirror control register and recalculate it */
5502         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5503
5504         if (on) {
5505                 mr_ctl |= mirror_type;
5506                 mr_ctl &= mirror_rule_mask;
5507                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5508         } else {
5509                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5510         }
5511
5512         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5513         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5514
5515         /* write mirrror control  register */
5516         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5517
5518         /* write pool mirrror control  register */
5519         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5520                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5521                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5522                                 mp_msb);
5523         }
5524         /* write VLAN mirrror control  register */
5525         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5526                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5527                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5528                                 mv_msb);
5529         }
5530
5531         return 0;
5532 }
5533
5534 static int
5535 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5536 {
5537         int mr_ctl = 0;
5538         uint32_t lsb_val = 0;
5539         uint32_t msb_val = 0;
5540         const uint8_t rule_mr_offset = 4;
5541
5542         struct ixgbe_hw *hw =
5543                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5544         struct ixgbe_mirror_info *mr_info =
5545                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5546
5547         if (ixgbe_vt_check(hw) < 0)
5548                 return -ENOTSUP;
5549
5550         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5551                 return -EINVAL;
5552
5553         memset(&mr_info->mr_conf[rule_id], 0,
5554                sizeof(struct rte_eth_mirror_conf));
5555
5556         /* clear PFVMCTL register */
5557         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5558
5559         /* clear pool mask register */
5560         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5561         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5562
5563         /* clear vlan mask register */
5564         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5565         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5566
5567         return 0;
5568 }
5569
5570 static int
5571 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5572 {
5573         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5574         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5575         uint32_t mask;
5576         struct ixgbe_hw *hw =
5577                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5578         uint32_t vec = IXGBE_MISC_VEC_ID;
5579
5580         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5581         if (rte_intr_allow_others(intr_handle))
5582                 vec = IXGBE_RX_VEC_START;
5583         mask |= (1 << vec);
5584         RTE_SET_USED(queue_id);
5585         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5586
5587         rte_intr_enable(intr_handle);
5588
5589         return 0;
5590 }
5591
5592 static int
5593 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5594 {
5595         uint32_t mask;
5596         struct ixgbe_hw *hw =
5597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5598         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5599         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5600         uint32_t vec = IXGBE_MISC_VEC_ID;
5601
5602         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5603         if (rte_intr_allow_others(intr_handle))
5604                 vec = IXGBE_RX_VEC_START;
5605         mask &= ~(1 << vec);
5606         RTE_SET_USED(queue_id);
5607         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5608
5609         return 0;
5610 }
5611
5612 static int
5613 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5614 {
5615         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5616         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5617         uint32_t mask;
5618         struct ixgbe_hw *hw =
5619                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5620         struct ixgbe_interrupt *intr =
5621                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5622
5623         if (queue_id < 16) {
5624                 ixgbe_disable_intr(hw);
5625                 intr->mask |= (1 << queue_id);
5626                 ixgbe_enable_intr(dev);
5627         } else if (queue_id < 32) {
5628                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5629                 mask &= (1 << queue_id);
5630                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5631         } else if (queue_id < 64) {
5632                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5633                 mask &= (1 << (queue_id - 32));
5634                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5635         }
5636         rte_intr_enable(intr_handle);
5637
5638         return 0;
5639 }
5640
5641 static int
5642 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5643 {
5644         uint32_t mask;
5645         struct ixgbe_hw *hw =
5646                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5647         struct ixgbe_interrupt *intr =
5648                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5649
5650         if (queue_id < 16) {
5651                 ixgbe_disable_intr(hw);
5652                 intr->mask &= ~(1 << queue_id);
5653                 ixgbe_enable_intr(dev);
5654         } else if (queue_id < 32) {
5655                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5656                 mask &= ~(1 << queue_id);
5657                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5658         } else if (queue_id < 64) {
5659                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5660                 mask &= ~(1 << (queue_id - 32));
5661                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5662         }
5663
5664         return 0;
5665 }
5666
5667 static void
5668 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5669                      uint8_t queue, uint8_t msix_vector)
5670 {
5671         uint32_t tmp, idx;
5672
5673         if (direction == -1) {
5674                 /* other causes */
5675                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5676                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5677                 tmp &= ~0xFF;
5678                 tmp |= msix_vector;
5679                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5680         } else {
5681                 /* rx or tx cause */
5682                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5683                 idx = ((16 * (queue & 1)) + (8 * direction));
5684                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5685                 tmp &= ~(0xFF << idx);
5686                 tmp |= (msix_vector << idx);
5687                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5688         }
5689 }
5690
5691 /**
5692  * set the IVAR registers, mapping interrupt causes to vectors
5693  * @param hw
5694  *  pointer to ixgbe_hw struct
5695  * @direction
5696  *  0 for Rx, 1 for Tx, -1 for other causes
5697  * @queue
5698  *  queue to map the corresponding interrupt to
5699  * @msix_vector
5700  *  the vector to map to the corresponding queue
5701  */
5702 static void
5703 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5704                    uint8_t queue, uint8_t msix_vector)
5705 {
5706         uint32_t tmp, idx;
5707
5708         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5709         if (hw->mac.type == ixgbe_mac_82598EB) {
5710                 if (direction == -1)
5711                         direction = 0;
5712                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5713                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5714                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5715                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5716                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5717         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5718                         (hw->mac.type == ixgbe_mac_X540) ||
5719                         (hw->mac.type == ixgbe_mac_X550)) {
5720                 if (direction == -1) {
5721                         /* other causes */
5722                         idx = ((queue & 1) * 8);
5723                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5724                         tmp &= ~(0xFF << idx);
5725                         tmp |= (msix_vector << idx);
5726                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5727                 } else {
5728                         /* rx or tx causes */
5729                         idx = ((16 * (queue & 1)) + (8 * direction));
5730                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5731                         tmp &= ~(0xFF << idx);
5732                         tmp |= (msix_vector << idx);
5733                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5734                 }
5735         }
5736 }
5737
5738 static void
5739 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5740 {
5741         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5742         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5743         struct ixgbe_hw *hw =
5744                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5745         uint32_t q_idx;
5746         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5747         uint32_t base = IXGBE_MISC_VEC_ID;
5748
5749         /* Configure VF other cause ivar */
5750         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5751
5752         /* won't configure msix register if no mapping is done
5753          * between intr vector and event fd.
5754          */
5755         if (!rte_intr_dp_is_en(intr_handle))
5756                 return;
5757
5758         if (rte_intr_allow_others(intr_handle)) {
5759                 base = IXGBE_RX_VEC_START;
5760                 vector_idx = IXGBE_RX_VEC_START;
5761         }
5762
5763         /* Configure all RX queues of VF */
5764         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5765                 /* Force all queue use vector 0,
5766                  * as IXGBE_VF_MAXMSIVECOTR = 1
5767                  */
5768                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5769                 intr_handle->intr_vec[q_idx] = vector_idx;
5770                 if (vector_idx < base + intr_handle->nb_efd - 1)
5771                         vector_idx++;
5772         }
5773 }
5774
5775 /**
5776  * Sets up the hardware to properly generate MSI-X interrupts
5777  * @hw
5778  *  board private structure
5779  */
5780 static void
5781 ixgbe_configure_msix(struct rte_eth_dev *dev)
5782 {
5783         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5784         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5785         struct ixgbe_hw *hw =
5786                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5787         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5788         uint32_t vec = IXGBE_MISC_VEC_ID;
5789         uint32_t mask;
5790         uint32_t gpie;
5791
5792         /* won't configure msix register if no mapping is done
5793          * between intr vector and event fd
5794          */
5795         if (!rte_intr_dp_is_en(intr_handle))
5796                 return;
5797
5798         if (rte_intr_allow_others(intr_handle))
5799                 vec = base = IXGBE_RX_VEC_START;
5800
5801         /* setup GPIE for MSI-x mode */
5802         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5803         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5804                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5805         /* auto clearing and auto setting corresponding bits in EIMS
5806          * when MSI-X interrupt is triggered
5807          */
5808         if (hw->mac.type == ixgbe_mac_82598EB) {
5809                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5810         } else {
5811                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5812                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5813         }
5814         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5815
5816         /* Populate the IVAR table and set the ITR values to the
5817          * corresponding register.
5818          */
5819         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5820              queue_id++) {
5821                 /* by default, 1:1 mapping */
5822                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5823                 intr_handle->intr_vec[queue_id] = vec;
5824                 if (vec < base + intr_handle->nb_efd - 1)
5825                         vec++;
5826         }
5827
5828         switch (hw->mac.type) {
5829         case ixgbe_mac_82598EB:
5830                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5831                                    IXGBE_MISC_VEC_ID);
5832                 break;
5833         case ixgbe_mac_82599EB:
5834         case ixgbe_mac_X540:
5835         case ixgbe_mac_X550:
5836                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5837                 break;
5838         default:
5839                 break;
5840         }
5841         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5842                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5843
5844         /* set up to autoclear timer, and the vectors */
5845         mask = IXGBE_EIMS_ENABLE_MASK;
5846         mask &= ~(IXGBE_EIMS_OTHER |
5847                   IXGBE_EIMS_MAILBOX |
5848                   IXGBE_EIMS_LSC);
5849
5850         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5851 }
5852
5853 int
5854 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5855                            uint16_t queue_idx, uint16_t tx_rate)
5856 {
5857         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5858         uint32_t rf_dec, rf_int;
5859         uint32_t bcnrc_val;
5860         uint16_t link_speed = dev->data->dev_link.link_speed;
5861
5862         if (queue_idx >= hw->mac.max_tx_queues)
5863                 return -EINVAL;
5864
5865         if (tx_rate != 0) {
5866                 /* Calculate the rate factor values to set */
5867                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5868                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5869                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5870
5871                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5872                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5873                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5874                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5875         } else {
5876                 bcnrc_val = 0;
5877         }
5878
5879         /*
5880          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5881          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5882          * set as 0x4.
5883          */
5884         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5885                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5886                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5887                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5888                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5889         else
5890                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5891                         IXGBE_MMW_SIZE_DEFAULT);
5892
5893         /* Set RTTBCNRC of queue X */
5894         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5895         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5896         IXGBE_WRITE_FLUSH(hw);
5897
5898         return 0;
5899 }
5900
5901 static int
5902 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5903                      __attribute__((unused)) uint32_t index,
5904                      __attribute__((unused)) uint32_t pool)
5905 {
5906         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5907         int diag;
5908
5909         /*
5910          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5911          * operation. Trap this case to avoid exhausting the [very limited]
5912          * set of PF resources used to store VF MAC addresses.
5913          */
5914         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5915                 return -1;
5916         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5917         if (diag != 0)
5918                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5919                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5920                             mac_addr->addr_bytes[0],
5921                             mac_addr->addr_bytes[1],
5922                             mac_addr->addr_bytes[2],
5923                             mac_addr->addr_bytes[3],
5924                             mac_addr->addr_bytes[4],
5925                             mac_addr->addr_bytes[5],
5926                             diag);
5927         return diag;
5928 }
5929
5930 static void
5931 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5932 {
5933         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5934         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5935         struct ether_addr *mac_addr;
5936         uint32_t i;
5937         int diag;
5938
5939         /*
5940          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5941          * not support the deletion of a given MAC address.
5942          * Instead, it imposes to delete all MAC addresses, then to add again
5943          * all MAC addresses with the exception of the one to be deleted.
5944          */
5945         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5946
5947         /*
5948          * Add again all MAC addresses, with the exception of the deleted one
5949          * and of the permanent MAC address.
5950          */
5951         for (i = 0, mac_addr = dev->data->mac_addrs;
5952              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5953                 /* Skip the deleted MAC address */
5954                 if (i == index)
5955                         continue;
5956                 /* Skip NULL MAC addresses */
5957                 if (is_zero_ether_addr(mac_addr))
5958                         continue;
5959                 /* Skip the permanent MAC address */
5960                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5961                         continue;
5962                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5963                 if (diag != 0)
5964                         PMD_DRV_LOG(ERR,
5965                                     "Adding again MAC address "
5966                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5967                                     "diag=%d",
5968                                     mac_addr->addr_bytes[0],
5969                                     mac_addr->addr_bytes[1],
5970                                     mac_addr->addr_bytes[2],
5971                                     mac_addr->addr_bytes[3],
5972                                     mac_addr->addr_bytes[4],
5973                                     mac_addr->addr_bytes[5],
5974                                     diag);
5975         }
5976 }
5977
5978 static void
5979 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5980 {
5981         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5982
5983         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5984 }
5985
5986 int
5987 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5988                         struct rte_eth_syn_filter *filter,
5989                         bool add)
5990 {
5991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5992         struct ixgbe_filter_info *filter_info =
5993                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5994         uint32_t syn_info;
5995         uint32_t synqf;
5996
5997         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5998                 return -EINVAL;
5999
6000         syn_info = filter_info->syn_info;
6001
6002         if (add) {
6003                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6004                         return -EINVAL;
6005                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6006                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6007
6008                 if (filter->hig_pri)
6009                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6010                 else
6011                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6012         } else {
6013                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6014                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6015                         return -ENOENT;
6016                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6017         }
6018
6019         filter_info->syn_info = synqf;
6020         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6021         IXGBE_WRITE_FLUSH(hw);
6022         return 0;
6023 }
6024
6025 static int
6026 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6027                         struct rte_eth_syn_filter *filter)
6028 {
6029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6030         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6031
6032         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6033                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6034                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6035                 return 0;
6036         }
6037         return -ENOENT;
6038 }
6039
6040 static int
6041 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6042                         enum rte_filter_op filter_op,
6043                         void *arg)
6044 {
6045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6046         int ret;
6047
6048         MAC_TYPE_FILTER_SUP(hw->mac.type);
6049
6050         if (filter_op == RTE_ETH_FILTER_NOP)
6051                 return 0;
6052
6053         if (arg == NULL) {
6054                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6055                             filter_op);
6056                 return -EINVAL;
6057         }
6058
6059         switch (filter_op) {
6060         case RTE_ETH_FILTER_ADD:
6061                 ret = ixgbe_syn_filter_set(dev,
6062                                 (struct rte_eth_syn_filter *)arg,
6063                                 TRUE);
6064                 break;
6065         case RTE_ETH_FILTER_DELETE:
6066                 ret = ixgbe_syn_filter_set(dev,
6067                                 (struct rte_eth_syn_filter *)arg,
6068                                 FALSE);
6069                 break;
6070         case RTE_ETH_FILTER_GET:
6071                 ret = ixgbe_syn_filter_get(dev,
6072                                 (struct rte_eth_syn_filter *)arg);
6073                 break;
6074         default:
6075                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6076                 ret = -EINVAL;
6077                 break;
6078         }
6079
6080         return ret;
6081 }
6082
6083
6084 static inline enum ixgbe_5tuple_protocol
6085 convert_protocol_type(uint8_t protocol_value)
6086 {
6087         if (protocol_value == IPPROTO_TCP)
6088                 return IXGBE_FILTER_PROTOCOL_TCP;
6089         else if (protocol_value == IPPROTO_UDP)
6090                 return IXGBE_FILTER_PROTOCOL_UDP;
6091         else if (protocol_value == IPPROTO_SCTP)
6092                 return IXGBE_FILTER_PROTOCOL_SCTP;
6093         else
6094                 return IXGBE_FILTER_PROTOCOL_NONE;
6095 }
6096
6097 /* inject a 5-tuple filter to HW */
6098 static inline void
6099 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6100                            struct ixgbe_5tuple_filter *filter)
6101 {
6102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6103         int i;
6104         uint32_t ftqf, sdpqf;
6105         uint32_t l34timir = 0;
6106         uint8_t mask = 0xff;
6107
6108         i = filter->index;
6109
6110         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6111                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6112         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6113
6114         ftqf = (uint32_t)(filter->filter_info.proto &
6115                 IXGBE_FTQF_PROTOCOL_MASK);
6116         ftqf |= (uint32_t)((filter->filter_info.priority &
6117                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6118         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6119                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6120         if (filter->filter_info.dst_ip_mask == 0)
6121                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6122         if (filter->filter_info.src_port_mask == 0)
6123                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6124         if (filter->filter_info.dst_port_mask == 0)
6125                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6126         if (filter->filter_info.proto_mask == 0)
6127                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6128         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6129         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6130         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6131
6132         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6133         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6134         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6135         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6136
6137         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6138         l34timir |= (uint32_t)(filter->queue <<
6139                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6140         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6141 }
6142
6143 /*
6144  * add a 5tuple filter
6145  *
6146  * @param
6147  * dev: Pointer to struct rte_eth_dev.
6148  * index: the index the filter allocates.
6149  * filter: ponter to the filter that will be added.
6150  * rx_queue: the queue id the filter assigned to.
6151  *
6152  * @return
6153  *    - On success, zero.
6154  *    - On failure, a negative value.
6155  */
6156 static int
6157 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6158                         struct ixgbe_5tuple_filter *filter)
6159 {
6160         struct ixgbe_filter_info *filter_info =
6161                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6162         int i, idx, shift;
6163
6164         /*
6165          * look for an unused 5tuple filter index,
6166          * and insert the filter to list.
6167          */
6168         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6169                 idx = i / (sizeof(uint32_t) * NBBY);
6170                 shift = i % (sizeof(uint32_t) * NBBY);
6171                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6172                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6173                         filter->index = i;
6174                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6175                                           filter,
6176                                           entries);
6177                         break;
6178                 }
6179         }
6180         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6181                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6182                 return -ENOSYS;
6183         }
6184
6185         ixgbe_inject_5tuple_filter(dev, filter);
6186
6187         return 0;
6188 }
6189
6190 /*
6191  * remove a 5tuple filter
6192  *
6193  * @param
6194  * dev: Pointer to struct rte_eth_dev.
6195  * filter: the pointer of the filter will be removed.
6196  */
6197 static void
6198 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6199                         struct ixgbe_5tuple_filter *filter)
6200 {
6201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6202         struct ixgbe_filter_info *filter_info =
6203                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6204         uint16_t index = filter->index;
6205
6206         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6207                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6208         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6209         rte_free(filter);
6210
6211         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6212         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6213         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6214         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6215         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6216 }
6217
6218 static int
6219 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6220 {
6221         struct ixgbe_hw *hw;
6222         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6223         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6224
6225         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6226
6227         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6228                 return -EINVAL;
6229
6230         /* refuse mtu that requires the support of scattered packets when this
6231          * feature has not been enabled before.
6232          */
6233         if (!rx_conf->enable_scatter &&
6234             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6235              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6236                 return -EINVAL;
6237
6238         /*
6239          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6240          * request of the version 2.0 of the mailbox API.
6241          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6242          * of the mailbox API.
6243          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6244          * prior to 3.11.33 which contains the following change:
6245          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6246          */
6247         ixgbevf_rlpml_set_vf(hw, max_frame);
6248
6249         /* update max frame size */
6250         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6251         return 0;
6252 }
6253
6254 static inline struct ixgbe_5tuple_filter *
6255 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6256                         struct ixgbe_5tuple_filter_info *key)
6257 {
6258         struct ixgbe_5tuple_filter *it;
6259
6260         TAILQ_FOREACH(it, filter_list, entries) {
6261                 if (memcmp(key, &it->filter_info,
6262                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6263                         return it;
6264                 }
6265         }
6266         return NULL;
6267 }
6268
6269 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6270 static inline int
6271 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6272                         struct ixgbe_5tuple_filter_info *filter_info)
6273 {
6274         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6275                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6276                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6277                 return -EINVAL;
6278
6279         switch (filter->dst_ip_mask) {
6280         case UINT32_MAX:
6281                 filter_info->dst_ip_mask = 0;
6282                 filter_info->dst_ip = filter->dst_ip;
6283                 break;
6284         case 0:
6285                 filter_info->dst_ip_mask = 1;
6286                 break;
6287         default:
6288                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6289                 return -EINVAL;
6290         }
6291
6292         switch (filter->src_ip_mask) {
6293         case UINT32_MAX:
6294                 filter_info->src_ip_mask = 0;
6295                 filter_info->src_ip = filter->src_ip;
6296                 break;
6297         case 0:
6298                 filter_info->src_ip_mask = 1;
6299                 break;
6300         default:
6301                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6302                 return -EINVAL;
6303         }
6304
6305         switch (filter->dst_port_mask) {
6306         case UINT16_MAX:
6307                 filter_info->dst_port_mask = 0;
6308                 filter_info->dst_port = filter->dst_port;
6309                 break;
6310         case 0:
6311                 filter_info->dst_port_mask = 1;
6312                 break;
6313         default:
6314                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6315                 return -EINVAL;
6316         }
6317
6318         switch (filter->src_port_mask) {
6319         case UINT16_MAX:
6320                 filter_info->src_port_mask = 0;
6321                 filter_info->src_port = filter->src_port;
6322                 break;
6323         case 0:
6324                 filter_info->src_port_mask = 1;
6325                 break;
6326         default:
6327                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6328                 return -EINVAL;
6329         }
6330
6331         switch (filter->proto_mask) {
6332         case UINT8_MAX:
6333                 filter_info->proto_mask = 0;
6334                 filter_info->proto =
6335                         convert_protocol_type(filter->proto);
6336                 break;
6337         case 0:
6338                 filter_info->proto_mask = 1;
6339                 break;
6340         default:
6341                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6342                 return -EINVAL;
6343         }
6344
6345         filter_info->priority = (uint8_t)filter->priority;
6346         return 0;
6347 }
6348
6349 /*
6350  * add or delete a ntuple filter
6351  *
6352  * @param
6353  * dev: Pointer to struct rte_eth_dev.
6354  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6355  * add: if true, add filter, if false, remove filter
6356  *
6357  * @return
6358  *    - On success, zero.
6359  *    - On failure, a negative value.
6360  */
6361 int
6362 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6363                         struct rte_eth_ntuple_filter *ntuple_filter,
6364                         bool add)
6365 {
6366         struct ixgbe_filter_info *filter_info =
6367                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6368         struct ixgbe_5tuple_filter_info filter_5tuple;
6369         struct ixgbe_5tuple_filter *filter;
6370         int ret;
6371
6372         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6373                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6374                 return -EINVAL;
6375         }
6376
6377         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6378         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6379         if (ret < 0)
6380                 return ret;
6381
6382         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6383                                          &filter_5tuple);
6384         if (filter != NULL && add) {
6385                 PMD_DRV_LOG(ERR, "filter exists.");
6386                 return -EEXIST;
6387         }
6388         if (filter == NULL && !add) {
6389                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6390                 return -ENOENT;
6391         }
6392
6393         if (add) {
6394                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6395                                 sizeof(struct ixgbe_5tuple_filter), 0);
6396                 if (filter == NULL)
6397                         return -ENOMEM;
6398                 rte_memcpy(&filter->filter_info,
6399                                  &filter_5tuple,
6400                                  sizeof(struct ixgbe_5tuple_filter_info));
6401                 filter->queue = ntuple_filter->queue;
6402                 ret = ixgbe_add_5tuple_filter(dev, filter);
6403                 if (ret < 0) {
6404                         rte_free(filter);
6405                         return ret;
6406                 }
6407         } else
6408                 ixgbe_remove_5tuple_filter(dev, filter);
6409
6410         return 0;
6411 }
6412
6413 /*
6414  * get a ntuple filter
6415  *
6416  * @param
6417  * dev: Pointer to struct rte_eth_dev.
6418  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6419  *
6420  * @return
6421  *    - On success, zero.
6422  *    - On failure, a negative value.
6423  */
6424 static int
6425 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6426                         struct rte_eth_ntuple_filter *ntuple_filter)
6427 {
6428         struct ixgbe_filter_info *filter_info =
6429                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6430         struct ixgbe_5tuple_filter_info filter_5tuple;
6431         struct ixgbe_5tuple_filter *filter;
6432         int ret;
6433
6434         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6435                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6436                 return -EINVAL;
6437         }
6438
6439         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6440         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6441         if (ret < 0)
6442                 return ret;
6443
6444         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6445                                          &filter_5tuple);
6446         if (filter == NULL) {
6447                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6448                 return -ENOENT;
6449         }
6450         ntuple_filter->queue = filter->queue;
6451         return 0;
6452 }
6453
6454 /*
6455  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6456  * @dev: pointer to rte_eth_dev structure
6457  * @filter_op:operation will be taken.
6458  * @arg: a pointer to specific structure corresponding to the filter_op
6459  *
6460  * @return
6461  *    - On success, zero.
6462  *    - On failure, a negative value.
6463  */
6464 static int
6465 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6466                                 enum rte_filter_op filter_op,
6467                                 void *arg)
6468 {
6469         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6470         int ret;
6471
6472         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6473
6474         if (filter_op == RTE_ETH_FILTER_NOP)
6475                 return 0;
6476
6477         if (arg == NULL) {
6478                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6479                             filter_op);
6480                 return -EINVAL;
6481         }
6482
6483         switch (filter_op) {
6484         case RTE_ETH_FILTER_ADD:
6485                 ret = ixgbe_add_del_ntuple_filter(dev,
6486                         (struct rte_eth_ntuple_filter *)arg,
6487                         TRUE);
6488                 break;
6489         case RTE_ETH_FILTER_DELETE:
6490                 ret = ixgbe_add_del_ntuple_filter(dev,
6491                         (struct rte_eth_ntuple_filter *)arg,
6492                         FALSE);
6493                 break;
6494         case RTE_ETH_FILTER_GET:
6495                 ret = ixgbe_get_ntuple_filter(dev,
6496                         (struct rte_eth_ntuple_filter *)arg);
6497                 break;
6498         default:
6499                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6500                 ret = -EINVAL;
6501                 break;
6502         }
6503         return ret;
6504 }
6505
6506 int
6507 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6508                         struct rte_eth_ethertype_filter *filter,
6509                         bool add)
6510 {
6511         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6512         struct ixgbe_filter_info *filter_info =
6513                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6514         uint32_t etqf = 0;
6515         uint32_t etqs = 0;
6516         int ret;
6517         struct ixgbe_ethertype_filter ethertype_filter;
6518
6519         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6520                 return -EINVAL;
6521
6522         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6523                 filter->ether_type == ETHER_TYPE_IPv6) {
6524                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6525                         " ethertype filter.", filter->ether_type);
6526                 return -EINVAL;
6527         }
6528
6529         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6530                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6531                 return -EINVAL;
6532         }
6533         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6534                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6535                 return -EINVAL;
6536         }
6537
6538         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6539         if (ret >= 0 && add) {
6540                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6541                             filter->ether_type);
6542                 return -EEXIST;
6543         }
6544         if (ret < 0 && !add) {
6545                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6546                             filter->ether_type);
6547                 return -ENOENT;
6548         }
6549
6550         if (add) {
6551                 etqf = IXGBE_ETQF_FILTER_EN;
6552                 etqf |= (uint32_t)filter->ether_type;
6553                 etqs |= (uint32_t)((filter->queue <<
6554                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6555                                     IXGBE_ETQS_RX_QUEUE);
6556                 etqs |= IXGBE_ETQS_QUEUE_EN;
6557
6558                 ethertype_filter.ethertype = filter->ether_type;
6559                 ethertype_filter.etqf = etqf;
6560                 ethertype_filter.etqs = etqs;
6561                 ethertype_filter.conf = FALSE;
6562                 ret = ixgbe_ethertype_filter_insert(filter_info,
6563                                                     &ethertype_filter);
6564                 if (ret < 0) {
6565                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6566                         return -ENOSPC;
6567                 }
6568         } else {
6569                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6570                 if (ret < 0)
6571                         return -ENOSYS;
6572         }
6573         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6574         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6575         IXGBE_WRITE_FLUSH(hw);
6576
6577         return 0;
6578 }
6579
6580 static int
6581 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6582                         struct rte_eth_ethertype_filter *filter)
6583 {
6584         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6585         struct ixgbe_filter_info *filter_info =
6586                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6587         uint32_t etqf, etqs;
6588         int ret;
6589
6590         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6591         if (ret < 0) {
6592                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6593                             filter->ether_type);
6594                 return -ENOENT;
6595         }
6596
6597         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6598         if (etqf & IXGBE_ETQF_FILTER_EN) {
6599                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6600                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6601                 filter->flags = 0;
6602                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6603                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6604                 return 0;
6605         }
6606         return -ENOENT;
6607 }
6608
6609 /*
6610  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6611  * @dev: pointer to rte_eth_dev structure
6612  * @filter_op:operation will be taken.
6613  * @arg: a pointer to specific structure corresponding to the filter_op
6614  */
6615 static int
6616 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6617                                 enum rte_filter_op filter_op,
6618                                 void *arg)
6619 {
6620         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6621         int ret;
6622
6623         MAC_TYPE_FILTER_SUP(hw->mac.type);
6624
6625         if (filter_op == RTE_ETH_FILTER_NOP)
6626                 return 0;
6627
6628         if (arg == NULL) {
6629                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6630                             filter_op);
6631                 return -EINVAL;
6632         }
6633
6634         switch (filter_op) {
6635         case RTE_ETH_FILTER_ADD:
6636                 ret = ixgbe_add_del_ethertype_filter(dev,
6637                         (struct rte_eth_ethertype_filter *)arg,
6638                         TRUE);
6639                 break;
6640         case RTE_ETH_FILTER_DELETE:
6641                 ret = ixgbe_add_del_ethertype_filter(dev,
6642                         (struct rte_eth_ethertype_filter *)arg,
6643                         FALSE);
6644                 break;
6645         case RTE_ETH_FILTER_GET:
6646                 ret = ixgbe_get_ethertype_filter(dev,
6647                         (struct rte_eth_ethertype_filter *)arg);
6648                 break;
6649         default:
6650                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6651                 ret = -EINVAL;
6652                 break;
6653         }
6654         return ret;
6655 }
6656
6657 static int
6658 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6659                      enum rte_filter_type filter_type,
6660                      enum rte_filter_op filter_op,
6661                      void *arg)
6662 {
6663         int ret = 0;
6664
6665         switch (filter_type) {
6666         case RTE_ETH_FILTER_NTUPLE:
6667                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6668                 break;
6669         case RTE_ETH_FILTER_ETHERTYPE:
6670                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6671                 break;
6672         case RTE_ETH_FILTER_SYN:
6673                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6674                 break;
6675         case RTE_ETH_FILTER_FDIR:
6676                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6677                 break;
6678         case RTE_ETH_FILTER_L2_TUNNEL:
6679                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6680                 break;
6681         case RTE_ETH_FILTER_GENERIC:
6682                 if (filter_op != RTE_ETH_FILTER_GET)
6683                         return -EINVAL;
6684                 *(const void **)arg = &ixgbe_flow_ops;
6685                 break;
6686         default:
6687                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6688                                                         filter_type);
6689                 ret = -EINVAL;
6690                 break;
6691         }
6692
6693         return ret;
6694 }
6695
6696 static u8 *
6697 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6698                         u8 **mc_addr_ptr, u32 *vmdq)
6699 {
6700         u8 *mc_addr;
6701
6702         *vmdq = 0;
6703         mc_addr = *mc_addr_ptr;
6704         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6705         return mc_addr;
6706 }
6707
6708 static int
6709 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6710                           struct ether_addr *mc_addr_set,
6711                           uint32_t nb_mc_addr)
6712 {
6713         struct ixgbe_hw *hw;
6714         u8 *mc_addr_list;
6715
6716         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6717         mc_addr_list = (u8 *)mc_addr_set;
6718         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6719                                          ixgbe_dev_addr_list_itr, TRUE);
6720 }
6721
6722 static uint64_t
6723 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6724 {
6725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6726         uint64_t systime_cycles;
6727
6728         switch (hw->mac.type) {
6729         case ixgbe_mac_X550:
6730         case ixgbe_mac_X550EM_x:
6731         case ixgbe_mac_X550EM_a:
6732                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6733                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6734                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6735                                 * NSEC_PER_SEC;
6736                 break;
6737         default:
6738                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6739                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6740                                 << 32;
6741         }
6742
6743         return systime_cycles;
6744 }
6745
6746 static uint64_t
6747 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6748 {
6749         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6750         uint64_t rx_tstamp_cycles;
6751
6752         switch (hw->mac.type) {
6753         case ixgbe_mac_X550:
6754         case ixgbe_mac_X550EM_x:
6755         case ixgbe_mac_X550EM_a:
6756                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6757                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6758                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6759                                 * NSEC_PER_SEC;
6760                 break;
6761         default:
6762                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6763                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6764                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6765                                 << 32;
6766         }
6767
6768         return rx_tstamp_cycles;
6769 }
6770
6771 static uint64_t
6772 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6773 {
6774         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6775         uint64_t tx_tstamp_cycles;
6776
6777         switch (hw->mac.type) {
6778         case ixgbe_mac_X550:
6779         case ixgbe_mac_X550EM_x:
6780         case ixgbe_mac_X550EM_a:
6781                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6782                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6783                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6784                                 * NSEC_PER_SEC;
6785                 break;
6786         default:
6787                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6788                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6789                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6790                                 << 32;
6791         }
6792
6793         return tx_tstamp_cycles;
6794 }
6795
6796 static void
6797 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6798 {
6799         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6800         struct ixgbe_adapter *adapter =
6801                 (struct ixgbe_adapter *)dev->data->dev_private;
6802         struct rte_eth_link link;
6803         uint32_t incval = 0;
6804         uint32_t shift = 0;
6805
6806         /* Get current link speed. */
6807         memset(&link, 0, sizeof(link));
6808         ixgbe_dev_link_update(dev, 1);
6809         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6810
6811         switch (link.link_speed) {
6812         case ETH_SPEED_NUM_100M:
6813                 incval = IXGBE_INCVAL_100;
6814                 shift = IXGBE_INCVAL_SHIFT_100;
6815                 break;
6816         case ETH_SPEED_NUM_1G:
6817                 incval = IXGBE_INCVAL_1GB;
6818                 shift = IXGBE_INCVAL_SHIFT_1GB;
6819                 break;
6820         case ETH_SPEED_NUM_10G:
6821         default:
6822                 incval = IXGBE_INCVAL_10GB;
6823                 shift = IXGBE_INCVAL_SHIFT_10GB;
6824                 break;
6825         }
6826
6827         switch (hw->mac.type) {
6828         case ixgbe_mac_X550:
6829         case ixgbe_mac_X550EM_x:
6830         case ixgbe_mac_X550EM_a:
6831                 /* Independent of link speed. */
6832                 incval = 1;
6833                 /* Cycles read will be interpreted as ns. */
6834                 shift = 0;
6835                 /* Fall-through */
6836         case ixgbe_mac_X540:
6837                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6838                 break;
6839         case ixgbe_mac_82599EB:
6840                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6841                 shift -= IXGBE_INCVAL_SHIFT_82599;
6842                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6843                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6844                 break;
6845         default:
6846                 /* Not supported. */
6847                 return;
6848         }
6849
6850         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6851         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6852         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6853
6854         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6855         adapter->systime_tc.cc_shift = shift;
6856         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6857
6858         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6859         adapter->rx_tstamp_tc.cc_shift = shift;
6860         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6861
6862         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6863         adapter->tx_tstamp_tc.cc_shift = shift;
6864         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6865 }
6866
6867 static int
6868 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6869 {
6870         struct ixgbe_adapter *adapter =
6871                         (struct ixgbe_adapter *)dev->data->dev_private;
6872
6873         adapter->systime_tc.nsec += delta;
6874         adapter->rx_tstamp_tc.nsec += delta;
6875         adapter->tx_tstamp_tc.nsec += delta;
6876
6877         return 0;
6878 }
6879
6880 static int
6881 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6882 {
6883         uint64_t ns;
6884         struct ixgbe_adapter *adapter =
6885                         (struct ixgbe_adapter *)dev->data->dev_private;
6886
6887         ns = rte_timespec_to_ns(ts);
6888         /* Set the timecounters to a new value. */
6889         adapter->systime_tc.nsec = ns;
6890         adapter->rx_tstamp_tc.nsec = ns;
6891         adapter->tx_tstamp_tc.nsec = ns;
6892
6893         return 0;
6894 }
6895
6896 static int
6897 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6898 {
6899         uint64_t ns, systime_cycles;
6900         struct ixgbe_adapter *adapter =
6901                         (struct ixgbe_adapter *)dev->data->dev_private;
6902
6903         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6904         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6905         *ts = rte_ns_to_timespec(ns);
6906
6907         return 0;
6908 }
6909
6910 static int
6911 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6912 {
6913         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6914         uint32_t tsync_ctl;
6915         uint32_t tsauxc;
6916
6917         /* Stop the timesync system time. */
6918         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6919         /* Reset the timesync system time value. */
6920         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6921         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6922
6923         /* Enable system time for platforms where it isn't on by default. */
6924         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6925         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6926         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6927
6928         ixgbe_start_timecounters(dev);
6929
6930         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6931         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6932                         (ETHER_TYPE_1588 |
6933                          IXGBE_ETQF_FILTER_EN |
6934                          IXGBE_ETQF_1588));
6935
6936         /* Enable timestamping of received PTP packets. */
6937         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6938         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6939         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6940
6941         /* Enable timestamping of transmitted PTP packets. */
6942         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6943         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6944         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6945
6946         IXGBE_WRITE_FLUSH(hw);
6947
6948         return 0;
6949 }
6950
6951 static int
6952 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6953 {
6954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6955         uint32_t tsync_ctl;
6956
6957         /* Disable timestamping of transmitted PTP packets. */
6958         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6959         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6960         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6961
6962         /* Disable timestamping of received PTP packets. */
6963         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6964         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6965         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6966
6967         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6968         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6969
6970         /* Stop incrementating the System Time registers. */
6971         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6972
6973         return 0;
6974 }
6975
6976 static int
6977 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6978                                  struct timespec *timestamp,
6979                                  uint32_t flags __rte_unused)
6980 {
6981         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6982         struct ixgbe_adapter *adapter =
6983                 (struct ixgbe_adapter *)dev->data->dev_private;
6984         uint32_t tsync_rxctl;
6985         uint64_t rx_tstamp_cycles;
6986         uint64_t ns;
6987
6988         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6989         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6990                 return -EINVAL;
6991
6992         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6993         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6994         *timestamp = rte_ns_to_timespec(ns);
6995
6996         return  0;
6997 }
6998
6999 static int
7000 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7001                                  struct timespec *timestamp)
7002 {
7003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7004         struct ixgbe_adapter *adapter =
7005                 (struct ixgbe_adapter *)dev->data->dev_private;
7006         uint32_t tsync_txctl;
7007         uint64_t tx_tstamp_cycles;
7008         uint64_t ns;
7009
7010         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7011         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7012                 return -EINVAL;
7013
7014         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7015         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7016         *timestamp = rte_ns_to_timespec(ns);
7017
7018         return 0;
7019 }
7020
7021 static int
7022 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7023 {
7024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7025         int count = 0;
7026         int g_ind = 0;
7027         const struct reg_info *reg_group;
7028         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7029                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7030
7031         while ((reg_group = reg_set[g_ind++]))
7032                 count += ixgbe_regs_group_count(reg_group);
7033
7034         return count;
7035 }
7036
7037 static int
7038 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7039 {
7040         int count = 0;
7041         int g_ind = 0;
7042         const struct reg_info *reg_group;
7043
7044         while ((reg_group = ixgbevf_regs[g_ind++]))
7045                 count += ixgbe_regs_group_count(reg_group);
7046
7047         return count;
7048 }
7049
7050 static int
7051 ixgbe_get_regs(struct rte_eth_dev *dev,
7052               struct rte_dev_reg_info *regs)
7053 {
7054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7055         uint32_t *data = regs->data;
7056         int g_ind = 0;
7057         int count = 0;
7058         const struct reg_info *reg_group;
7059         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7060                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7061
7062         if (data == NULL) {
7063                 regs->length = ixgbe_get_reg_length(dev);
7064                 regs->width = sizeof(uint32_t);
7065                 return 0;
7066         }
7067
7068         /* Support only full register dump */
7069         if ((regs->length == 0) ||
7070             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7071                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7072                         hw->device_id;
7073                 while ((reg_group = reg_set[g_ind++]))
7074                         count += ixgbe_read_regs_group(dev, &data[count],
7075                                 reg_group);
7076                 return 0;
7077         }
7078
7079         return -ENOTSUP;
7080 }
7081
7082 static int
7083 ixgbevf_get_regs(struct rte_eth_dev *dev,
7084                 struct rte_dev_reg_info *regs)
7085 {
7086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7087         uint32_t *data = regs->data;
7088         int g_ind = 0;
7089         int count = 0;
7090         const struct reg_info *reg_group;
7091
7092         if (data == NULL) {
7093                 regs->length = ixgbevf_get_reg_length(dev);
7094                 regs->width = sizeof(uint32_t);
7095                 return 0;
7096         }
7097
7098         /* Support only full register dump */
7099         if ((regs->length == 0) ||
7100             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7101                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7102                         hw->device_id;
7103                 while ((reg_group = ixgbevf_regs[g_ind++]))
7104                         count += ixgbe_read_regs_group(dev, &data[count],
7105                                                       reg_group);
7106                 return 0;
7107         }
7108
7109         return -ENOTSUP;
7110 }
7111
7112 static int
7113 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7114 {
7115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7116
7117         /* Return unit is byte count */
7118         return hw->eeprom.word_size * 2;
7119 }
7120
7121 static int
7122 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7123                 struct rte_dev_eeprom_info *in_eeprom)
7124 {
7125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7126         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7127         uint16_t *data = in_eeprom->data;
7128         int first, length;
7129
7130         first = in_eeprom->offset >> 1;
7131         length = in_eeprom->length >> 1;
7132         if ((first > hw->eeprom.word_size) ||
7133             ((first + length) > hw->eeprom.word_size))
7134                 return -EINVAL;
7135
7136         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7137
7138         return eeprom->ops.read_buffer(hw, first, length, data);
7139 }
7140
7141 static int
7142 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7143                 struct rte_dev_eeprom_info *in_eeprom)
7144 {
7145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7146         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7147         uint16_t *data = in_eeprom->data;
7148         int first, length;
7149
7150         first = in_eeprom->offset >> 1;
7151         length = in_eeprom->length >> 1;
7152         if ((first > hw->eeprom.word_size) ||
7153             ((first + length) > hw->eeprom.word_size))
7154                 return -EINVAL;
7155
7156         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7157
7158         return eeprom->ops.write_buffer(hw,  first, length, data);
7159 }
7160
7161 uint16_t
7162 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7163         switch (mac_type) {
7164         case ixgbe_mac_X550:
7165         case ixgbe_mac_X550EM_x:
7166         case ixgbe_mac_X550EM_a:
7167                 return ETH_RSS_RETA_SIZE_512;
7168         case ixgbe_mac_X550_vf:
7169         case ixgbe_mac_X550EM_x_vf:
7170         case ixgbe_mac_X550EM_a_vf:
7171                 return ETH_RSS_RETA_SIZE_64;
7172         default:
7173                 return ETH_RSS_RETA_SIZE_128;
7174         }
7175 }
7176
7177 uint32_t
7178 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7179         switch (mac_type) {
7180         case ixgbe_mac_X550:
7181         case ixgbe_mac_X550EM_x:
7182         case ixgbe_mac_X550EM_a:
7183                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7184                         return IXGBE_RETA(reta_idx >> 2);
7185                 else
7186                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7187         case ixgbe_mac_X550_vf:
7188         case ixgbe_mac_X550EM_x_vf:
7189         case ixgbe_mac_X550EM_a_vf:
7190                 return IXGBE_VFRETA(reta_idx >> 2);
7191         default:
7192                 return IXGBE_RETA(reta_idx >> 2);
7193         }
7194 }
7195
7196 uint32_t
7197 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7198         switch (mac_type) {
7199         case ixgbe_mac_X550_vf:
7200         case ixgbe_mac_X550EM_x_vf:
7201         case ixgbe_mac_X550EM_a_vf:
7202                 return IXGBE_VFMRQC;
7203         default:
7204                 return IXGBE_MRQC;
7205         }
7206 }
7207
7208 uint32_t
7209 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7210         switch (mac_type) {
7211         case ixgbe_mac_X550_vf:
7212         case ixgbe_mac_X550EM_x_vf:
7213         case ixgbe_mac_X550EM_a_vf:
7214                 return IXGBE_VFRSSRK(i);
7215         default:
7216                 return IXGBE_RSSRK(i);
7217         }
7218 }
7219
7220 bool
7221 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7222         switch (mac_type) {
7223         case ixgbe_mac_82599_vf:
7224         case ixgbe_mac_X540_vf:
7225                 return 0;
7226         default:
7227                 return 1;
7228         }
7229 }
7230
7231 static int
7232 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7233                         struct rte_eth_dcb_info *dcb_info)
7234 {
7235         struct ixgbe_dcb_config *dcb_config =
7236                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7237         struct ixgbe_dcb_tc_config *tc;
7238         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7239         uint8_t nb_tcs;
7240         uint8_t i, j;
7241
7242         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7243                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7244         else
7245                 dcb_info->nb_tcs = 1;
7246
7247         tc_queue = &dcb_info->tc_queue;
7248         nb_tcs = dcb_info->nb_tcs;
7249
7250         if (dcb_config->vt_mode) { /* vt is enabled*/
7251                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7252                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7253                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7254                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7255                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7256                         for (j = 0; j < nb_tcs; j++) {
7257                                 tc_queue->tc_rxq[0][j].base = j;
7258                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7259                                 tc_queue->tc_txq[0][j].base = j;
7260                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7261                         }
7262                 } else {
7263                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7264                                 for (j = 0; j < nb_tcs; j++) {
7265                                         tc_queue->tc_rxq[i][j].base =
7266                                                 i * nb_tcs + j;
7267                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7268                                         tc_queue->tc_txq[i][j].base =
7269                                                 i * nb_tcs + j;
7270                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7271                                 }
7272                         }
7273                 }
7274         } else { /* vt is disabled*/
7275                 struct rte_eth_dcb_rx_conf *rx_conf =
7276                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7277                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7278                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7279                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7280                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7281                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7282                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7283                         }
7284                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7285                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7286                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7287                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7288                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7289                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7290                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7291                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7292                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7293                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7294                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7295                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7296                         }
7297                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7298                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7299                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7300                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7301                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7302                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7303                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7304                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7305                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7306                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7307                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7308                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7309                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7310                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7311                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7312                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7313                 }
7314         }
7315         for (i = 0; i < dcb_info->nb_tcs; i++) {
7316                 tc = &dcb_config->tc_config[i];
7317                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7318         }
7319         return 0;
7320 }
7321
7322 /* Update e-tag ether type */
7323 static int
7324 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7325                             uint16_t ether_type)
7326 {
7327         uint32_t etag_etype;
7328
7329         if (hw->mac.type != ixgbe_mac_X550 &&
7330             hw->mac.type != ixgbe_mac_X550EM_x &&
7331             hw->mac.type != ixgbe_mac_X550EM_a) {
7332                 return -ENOTSUP;
7333         }
7334
7335         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7336         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7337         etag_etype |= ether_type;
7338         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7339         IXGBE_WRITE_FLUSH(hw);
7340
7341         return 0;
7342 }
7343
7344 /* Config l2 tunnel ether type */
7345 static int
7346 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7347                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7348 {
7349         int ret = 0;
7350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7351         struct ixgbe_l2_tn_info *l2_tn_info =
7352                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7353
7354         if (l2_tunnel == NULL)
7355                 return -EINVAL;
7356
7357         switch (l2_tunnel->l2_tunnel_type) {
7358         case RTE_L2_TUNNEL_TYPE_E_TAG:
7359                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7360                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7361                 break;
7362         default:
7363                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7364                 ret = -EINVAL;
7365                 break;
7366         }
7367
7368         return ret;
7369 }
7370
7371 /* Enable e-tag tunnel */
7372 static int
7373 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7374 {
7375         uint32_t etag_etype;
7376
7377         if (hw->mac.type != ixgbe_mac_X550 &&
7378             hw->mac.type != ixgbe_mac_X550EM_x &&
7379             hw->mac.type != ixgbe_mac_X550EM_a) {
7380                 return -ENOTSUP;
7381         }
7382
7383         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7384         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7385         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7386         IXGBE_WRITE_FLUSH(hw);
7387
7388         return 0;
7389 }
7390
7391 /* Enable l2 tunnel */
7392 static int
7393 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7394                            enum rte_eth_tunnel_type l2_tunnel_type)
7395 {
7396         int ret = 0;
7397         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7398         struct ixgbe_l2_tn_info *l2_tn_info =
7399                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7400
7401         switch (l2_tunnel_type) {
7402         case RTE_L2_TUNNEL_TYPE_E_TAG:
7403                 l2_tn_info->e_tag_en = TRUE;
7404                 ret = ixgbe_e_tag_enable(hw);
7405                 break;
7406         default:
7407                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7408                 ret = -EINVAL;
7409                 break;
7410         }
7411
7412         return ret;
7413 }
7414
7415 /* Disable e-tag tunnel */
7416 static int
7417 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7418 {
7419         uint32_t etag_etype;
7420
7421         if (hw->mac.type != ixgbe_mac_X550 &&
7422             hw->mac.type != ixgbe_mac_X550EM_x &&
7423             hw->mac.type != ixgbe_mac_X550EM_a) {
7424                 return -ENOTSUP;
7425         }
7426
7427         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7428         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7429         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7430         IXGBE_WRITE_FLUSH(hw);
7431
7432         return 0;
7433 }
7434
7435 /* Disable l2 tunnel */
7436 static int
7437 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7438                             enum rte_eth_tunnel_type l2_tunnel_type)
7439 {
7440         int ret = 0;
7441         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7442         struct ixgbe_l2_tn_info *l2_tn_info =
7443                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7444
7445         switch (l2_tunnel_type) {
7446         case RTE_L2_TUNNEL_TYPE_E_TAG:
7447                 l2_tn_info->e_tag_en = FALSE;
7448                 ret = ixgbe_e_tag_disable(hw);
7449                 break;
7450         default:
7451                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7452                 ret = -EINVAL;
7453                 break;
7454         }
7455
7456         return ret;
7457 }
7458
7459 static int
7460 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7461                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7462 {
7463         int ret = 0;
7464         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7465         uint32_t i, rar_entries;
7466         uint32_t rar_low, rar_high;
7467
7468         if (hw->mac.type != ixgbe_mac_X550 &&
7469             hw->mac.type != ixgbe_mac_X550EM_x &&
7470             hw->mac.type != ixgbe_mac_X550EM_a) {
7471                 return -ENOTSUP;
7472         }
7473
7474         rar_entries = ixgbe_get_num_rx_addrs(hw);
7475
7476         for (i = 1; i < rar_entries; i++) {
7477                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7478                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7479                 if ((rar_high & IXGBE_RAH_AV) &&
7480                     (rar_high & IXGBE_RAH_ADTYPE) &&
7481                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7482                      l2_tunnel->tunnel_id)) {
7483                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7484                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7485
7486                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7487
7488                         return ret;
7489                 }
7490         }
7491
7492         return ret;
7493 }
7494
7495 static int
7496 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7497                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7498 {
7499         int ret = 0;
7500         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7501         uint32_t i, rar_entries;
7502         uint32_t rar_low, rar_high;
7503
7504         if (hw->mac.type != ixgbe_mac_X550 &&
7505             hw->mac.type != ixgbe_mac_X550EM_x &&
7506             hw->mac.type != ixgbe_mac_X550EM_a) {
7507                 return -ENOTSUP;
7508         }
7509
7510         /* One entry for one tunnel. Try to remove potential existing entry. */
7511         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7512
7513         rar_entries = ixgbe_get_num_rx_addrs(hw);
7514
7515         for (i = 1; i < rar_entries; i++) {
7516                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7517                 if (rar_high & IXGBE_RAH_AV) {
7518                         continue;
7519                 } else {
7520                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7521                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7522                         rar_low = l2_tunnel->tunnel_id;
7523
7524                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7525                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7526
7527                         return ret;
7528                 }
7529         }
7530
7531         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7532                      " Please remove a rule before adding a new one.");
7533         return -EINVAL;
7534 }
7535
7536 static inline struct ixgbe_l2_tn_filter *
7537 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7538                           struct ixgbe_l2_tn_key *key)
7539 {
7540         int ret;
7541
7542         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7543         if (ret < 0)
7544                 return NULL;
7545
7546         return l2_tn_info->hash_map[ret];
7547 }
7548
7549 static inline int
7550 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7551                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7552 {
7553         int ret;
7554
7555         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7556                                &l2_tn_filter->key);
7557
7558         if (ret < 0) {
7559                 PMD_DRV_LOG(ERR,
7560                             "Failed to insert L2 tunnel filter"
7561                             " to hash table %d!",
7562                             ret);
7563                 return ret;
7564         }
7565
7566         l2_tn_info->hash_map[ret] = l2_tn_filter;
7567
7568         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7569
7570         return 0;
7571 }
7572
7573 static inline int
7574 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7575                           struct ixgbe_l2_tn_key *key)
7576 {
7577         int ret;
7578         struct ixgbe_l2_tn_filter *l2_tn_filter;
7579
7580         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7581
7582         if (ret < 0) {
7583                 PMD_DRV_LOG(ERR,
7584                             "No such L2 tunnel filter to delete %d!",
7585                             ret);
7586                 return ret;
7587         }
7588
7589         l2_tn_filter = l2_tn_info->hash_map[ret];
7590         l2_tn_info->hash_map[ret] = NULL;
7591
7592         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7593         rte_free(l2_tn_filter);
7594
7595         return 0;
7596 }
7597
7598 /* Add l2 tunnel filter */
7599 int
7600 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7601                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7602                                bool restore)
7603 {
7604         int ret;
7605         struct ixgbe_l2_tn_info *l2_tn_info =
7606                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7607         struct ixgbe_l2_tn_key key;
7608         struct ixgbe_l2_tn_filter *node;
7609
7610         if (!restore) {
7611                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7612                 key.tn_id = l2_tunnel->tunnel_id;
7613
7614                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7615
7616                 if (node) {
7617                         PMD_DRV_LOG(ERR,
7618                                     "The L2 tunnel filter already exists!");
7619                         return -EINVAL;
7620                 }
7621
7622                 node = rte_zmalloc("ixgbe_l2_tn",
7623                                    sizeof(struct ixgbe_l2_tn_filter),
7624                                    0);
7625                 if (!node)
7626                         return -ENOMEM;
7627
7628                 rte_memcpy(&node->key,
7629                                  &key,
7630                                  sizeof(struct ixgbe_l2_tn_key));
7631                 node->pool = l2_tunnel->pool;
7632                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7633                 if (ret < 0) {
7634                         rte_free(node);
7635                         return ret;
7636                 }
7637         }
7638
7639         switch (l2_tunnel->l2_tunnel_type) {
7640         case RTE_L2_TUNNEL_TYPE_E_TAG:
7641                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7642                 break;
7643         default:
7644                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7645                 ret = -EINVAL;
7646                 break;
7647         }
7648
7649         if ((!restore) && (ret < 0))
7650                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7651
7652         return ret;
7653 }
7654
7655 /* Delete l2 tunnel filter */
7656 int
7657 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7658                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7659 {
7660         int ret;
7661         struct ixgbe_l2_tn_info *l2_tn_info =
7662                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7663         struct ixgbe_l2_tn_key key;
7664
7665         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7666         key.tn_id = l2_tunnel->tunnel_id;
7667         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7668         if (ret < 0)
7669                 return ret;
7670
7671         switch (l2_tunnel->l2_tunnel_type) {
7672         case RTE_L2_TUNNEL_TYPE_E_TAG:
7673                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7674                 break;
7675         default:
7676                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7677                 ret = -EINVAL;
7678                 break;
7679         }
7680
7681         return ret;
7682 }
7683
7684 /**
7685  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7686  * @dev: pointer to rte_eth_dev structure
7687  * @filter_op:operation will be taken.
7688  * @arg: a pointer to specific structure corresponding to the filter_op
7689  */
7690 static int
7691 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7692                                   enum rte_filter_op filter_op,
7693                                   void *arg)
7694 {
7695         int ret;
7696
7697         if (filter_op == RTE_ETH_FILTER_NOP)
7698                 return 0;
7699
7700         if (arg == NULL) {
7701                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7702                             filter_op);
7703                 return -EINVAL;
7704         }
7705
7706         switch (filter_op) {
7707         case RTE_ETH_FILTER_ADD:
7708                 ret = ixgbe_dev_l2_tunnel_filter_add
7709                         (dev,
7710                          (struct rte_eth_l2_tunnel_conf *)arg,
7711                          FALSE);
7712                 break;
7713         case RTE_ETH_FILTER_DELETE:
7714                 ret = ixgbe_dev_l2_tunnel_filter_del
7715                         (dev,
7716                          (struct rte_eth_l2_tunnel_conf *)arg);
7717                 break;
7718         default:
7719                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7720                 ret = -EINVAL;
7721                 break;
7722         }
7723         return ret;
7724 }
7725
7726 static int
7727 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7728 {
7729         int ret = 0;
7730         uint32_t ctrl;
7731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7732
7733         if (hw->mac.type != ixgbe_mac_X550 &&
7734             hw->mac.type != ixgbe_mac_X550EM_x &&
7735             hw->mac.type != ixgbe_mac_X550EM_a) {
7736                 return -ENOTSUP;
7737         }
7738
7739         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7740         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7741         if (en)
7742                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7743         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7744
7745         return ret;
7746 }
7747
7748 /* Enable l2 tunnel forwarding */
7749 static int
7750 ixgbe_dev_l2_tunnel_forwarding_enable
7751         (struct rte_eth_dev *dev,
7752          enum rte_eth_tunnel_type l2_tunnel_type)
7753 {
7754         struct ixgbe_l2_tn_info *l2_tn_info =
7755                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7756         int ret = 0;
7757
7758         switch (l2_tunnel_type) {
7759         case RTE_L2_TUNNEL_TYPE_E_TAG:
7760                 l2_tn_info->e_tag_fwd_en = TRUE;
7761                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7762                 break;
7763         default:
7764                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7765                 ret = -EINVAL;
7766                 break;
7767         }
7768
7769         return ret;
7770 }
7771
7772 /* Disable l2 tunnel forwarding */
7773 static int
7774 ixgbe_dev_l2_tunnel_forwarding_disable
7775         (struct rte_eth_dev *dev,
7776          enum rte_eth_tunnel_type l2_tunnel_type)
7777 {
7778         struct ixgbe_l2_tn_info *l2_tn_info =
7779                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7780         int ret = 0;
7781
7782         switch (l2_tunnel_type) {
7783         case RTE_L2_TUNNEL_TYPE_E_TAG:
7784                 l2_tn_info->e_tag_fwd_en = FALSE;
7785                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7786                 break;
7787         default:
7788                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7789                 ret = -EINVAL;
7790                 break;
7791         }
7792
7793         return ret;
7794 }
7795
7796 static int
7797 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7798                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7799                              bool en)
7800 {
7801         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7802         int ret = 0;
7803         uint32_t vmtir, vmvir;
7804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7805
7806         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7807                 PMD_DRV_LOG(ERR,
7808                             "VF id %u should be less than %u",
7809                             l2_tunnel->vf_id,
7810                             pci_dev->max_vfs);
7811                 return -EINVAL;
7812         }
7813
7814         if (hw->mac.type != ixgbe_mac_X550 &&
7815             hw->mac.type != ixgbe_mac_X550EM_x &&
7816             hw->mac.type != ixgbe_mac_X550EM_a) {
7817                 return -ENOTSUP;
7818         }
7819
7820         if (en)
7821                 vmtir = l2_tunnel->tunnel_id;
7822         else
7823                 vmtir = 0;
7824
7825         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7826
7827         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7828         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7829         if (en)
7830                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7831         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7832
7833         return ret;
7834 }
7835
7836 /* Enable l2 tunnel tag insertion */
7837 static int
7838 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7839                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7840 {
7841         int ret = 0;
7842
7843         switch (l2_tunnel->l2_tunnel_type) {
7844         case RTE_L2_TUNNEL_TYPE_E_TAG:
7845                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7846                 break;
7847         default:
7848                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7849                 ret = -EINVAL;
7850                 break;
7851         }
7852
7853         return ret;
7854 }
7855
7856 /* Disable l2 tunnel tag insertion */
7857 static int
7858 ixgbe_dev_l2_tunnel_insertion_disable
7859         (struct rte_eth_dev *dev,
7860          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7861 {
7862         int ret = 0;
7863
7864         switch (l2_tunnel->l2_tunnel_type) {
7865         case RTE_L2_TUNNEL_TYPE_E_TAG:
7866                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7867                 break;
7868         default:
7869                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7870                 ret = -EINVAL;
7871                 break;
7872         }
7873
7874         return ret;
7875 }
7876
7877 static int
7878 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7879                              bool en)
7880 {
7881         int ret = 0;
7882         uint32_t qde;
7883         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7884
7885         if (hw->mac.type != ixgbe_mac_X550 &&
7886             hw->mac.type != ixgbe_mac_X550EM_x &&
7887             hw->mac.type != ixgbe_mac_X550EM_a) {
7888                 return -ENOTSUP;
7889         }
7890
7891         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7892         if (en)
7893                 qde |= IXGBE_QDE_STRIP_TAG;
7894         else
7895                 qde &= ~IXGBE_QDE_STRIP_TAG;
7896         qde &= ~IXGBE_QDE_READ;
7897         qde |= IXGBE_QDE_WRITE;
7898         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7899
7900         return ret;
7901 }
7902
7903 /* Enable l2 tunnel tag stripping */
7904 static int
7905 ixgbe_dev_l2_tunnel_stripping_enable
7906         (struct rte_eth_dev *dev,
7907          enum rte_eth_tunnel_type l2_tunnel_type)
7908 {
7909         int ret = 0;
7910
7911         switch (l2_tunnel_type) {
7912         case RTE_L2_TUNNEL_TYPE_E_TAG:
7913                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7914                 break;
7915         default:
7916                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7917                 ret = -EINVAL;
7918                 break;
7919         }
7920
7921         return ret;
7922 }
7923
7924 /* Disable l2 tunnel tag stripping */
7925 static int
7926 ixgbe_dev_l2_tunnel_stripping_disable
7927         (struct rte_eth_dev *dev,
7928          enum rte_eth_tunnel_type l2_tunnel_type)
7929 {
7930         int ret = 0;
7931
7932         switch (l2_tunnel_type) {
7933         case RTE_L2_TUNNEL_TYPE_E_TAG:
7934                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7935                 break;
7936         default:
7937                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7938                 ret = -EINVAL;
7939                 break;
7940         }
7941
7942         return ret;
7943 }
7944
7945 /* Enable/disable l2 tunnel offload functions */
7946 static int
7947 ixgbe_dev_l2_tunnel_offload_set
7948         (struct rte_eth_dev *dev,
7949          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7950          uint32_t mask,
7951          uint8_t en)
7952 {
7953         int ret = 0;
7954
7955         if (l2_tunnel == NULL)
7956                 return -EINVAL;
7957
7958         ret = -EINVAL;
7959         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7960                 if (en)
7961                         ret = ixgbe_dev_l2_tunnel_enable(
7962                                 dev,
7963                                 l2_tunnel->l2_tunnel_type);
7964                 else
7965                         ret = ixgbe_dev_l2_tunnel_disable(
7966                                 dev,
7967                                 l2_tunnel->l2_tunnel_type);
7968         }
7969
7970         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7971                 if (en)
7972                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7973                                 dev,
7974                                 l2_tunnel);
7975                 else
7976                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7977                                 dev,
7978                                 l2_tunnel);
7979         }
7980
7981         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7982                 if (en)
7983                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7984                                 dev,
7985                                 l2_tunnel->l2_tunnel_type);
7986                 else
7987                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7988                                 dev,
7989                                 l2_tunnel->l2_tunnel_type);
7990         }
7991
7992         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7993                 if (en)
7994                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7995                                 dev,
7996                                 l2_tunnel->l2_tunnel_type);
7997                 else
7998                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7999                                 dev,
8000                                 l2_tunnel->l2_tunnel_type);
8001         }
8002
8003         return ret;
8004 }
8005
8006 static int
8007 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8008                         uint16_t port)
8009 {
8010         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8011         IXGBE_WRITE_FLUSH(hw);
8012
8013         return 0;
8014 }
8015
8016 /* There's only one register for VxLAN UDP port.
8017  * So, we cannot add several ports. Will update it.
8018  */
8019 static int
8020 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8021                      uint16_t port)
8022 {
8023         if (port == 0) {
8024                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8025                 return -EINVAL;
8026         }
8027
8028         return ixgbe_update_vxlan_port(hw, port);
8029 }
8030
8031 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8032  * UDP port, it must have a value.
8033  * So, will reset it to the original value 0.
8034  */
8035 static int
8036 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8037                      uint16_t port)
8038 {
8039         uint16_t cur_port;
8040
8041         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8042
8043         if (cur_port != port) {
8044                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8045                 return -EINVAL;
8046         }
8047
8048         return ixgbe_update_vxlan_port(hw, 0);
8049 }
8050
8051 /* Add UDP tunneling port */
8052 static int
8053 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8054                               struct rte_eth_udp_tunnel *udp_tunnel)
8055 {
8056         int ret = 0;
8057         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8058
8059         if (hw->mac.type != ixgbe_mac_X550 &&
8060             hw->mac.type != ixgbe_mac_X550EM_x &&
8061             hw->mac.type != ixgbe_mac_X550EM_a) {
8062                 return -ENOTSUP;
8063         }
8064
8065         if (udp_tunnel == NULL)
8066                 return -EINVAL;
8067
8068         switch (udp_tunnel->prot_type) {
8069         case RTE_TUNNEL_TYPE_VXLAN:
8070                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8071                 break;
8072
8073         case RTE_TUNNEL_TYPE_GENEVE:
8074         case RTE_TUNNEL_TYPE_TEREDO:
8075                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8076                 ret = -EINVAL;
8077                 break;
8078
8079         default:
8080                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8081                 ret = -EINVAL;
8082                 break;
8083         }
8084
8085         return ret;
8086 }
8087
8088 /* Remove UDP tunneling port */
8089 static int
8090 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8091                               struct rte_eth_udp_tunnel *udp_tunnel)
8092 {
8093         int ret = 0;
8094         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8095
8096         if (hw->mac.type != ixgbe_mac_X550 &&
8097             hw->mac.type != ixgbe_mac_X550EM_x &&
8098             hw->mac.type != ixgbe_mac_X550EM_a) {
8099                 return -ENOTSUP;
8100         }
8101
8102         if (udp_tunnel == NULL)
8103                 return -EINVAL;
8104
8105         switch (udp_tunnel->prot_type) {
8106         case RTE_TUNNEL_TYPE_VXLAN:
8107                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8108                 break;
8109         case RTE_TUNNEL_TYPE_GENEVE:
8110         case RTE_TUNNEL_TYPE_TEREDO:
8111                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8112                 ret = -EINVAL;
8113                 break;
8114         default:
8115                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8116                 ret = -EINVAL;
8117                 break;
8118         }
8119
8120         return ret;
8121 }
8122
8123 static void
8124 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8125 {
8126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8127
8128         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8129 }
8130
8131 static void
8132 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8133 {
8134         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8135
8136         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8137 }
8138
8139 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8140 {
8141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8142         u32 in_msg = 0;
8143
8144         /* peek the message first */
8145         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8146
8147         /* PF reset VF event */
8148         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8149                 /* dummy mbx read to ack pf */
8150                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8151                         return;
8152                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8153                                               NULL);
8154         }
8155 }
8156
8157 static int
8158 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8159 {
8160         uint32_t eicr;
8161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8162         struct ixgbe_interrupt *intr =
8163                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8164         ixgbevf_intr_disable(hw);
8165
8166         /* read-on-clear nic registers here */
8167         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8168         intr->flags = 0;
8169
8170         /* only one misc vector supported - mailbox */
8171         eicr &= IXGBE_VTEICR_MASK;
8172         if (eicr == IXGBE_MISC_VEC_ID)
8173                 intr->flags |= IXGBE_FLAG_MAILBOX;
8174
8175         return 0;
8176 }
8177
8178 static int
8179 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8180 {
8181         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8182         struct ixgbe_interrupt *intr =
8183                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8184
8185         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8186                 ixgbevf_mbx_process(dev);
8187                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8188         }
8189
8190         ixgbevf_intr_enable(hw);
8191
8192         return 0;
8193 }
8194
8195 static void
8196 ixgbevf_dev_interrupt_handler(void *param)
8197 {
8198         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8199
8200         ixgbevf_dev_interrupt_get_status(dev);
8201         ixgbevf_dev_interrupt_action(dev);
8202 }
8203
8204 /**
8205  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8206  *  @hw: pointer to hardware structure
8207  *
8208  *  Stops the transmit data path and waits for the HW to internally empty
8209  *  the Tx security block
8210  **/
8211 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8212 {
8213 #define IXGBE_MAX_SECTX_POLL 40
8214
8215         int i;
8216         int sectxreg;
8217
8218         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8219         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8220         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8221         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8222                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8223                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8224                         break;
8225                 /* Use interrupt-safe sleep just in case */
8226                 usec_delay(1000);
8227         }
8228
8229         /* For informational purposes only */
8230         if (i >= IXGBE_MAX_SECTX_POLL)
8231                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8232                          "path fully disabled.  Continuing with init.");
8233
8234         return IXGBE_SUCCESS;
8235 }
8236
8237 /**
8238  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8239  *  @hw: pointer to hardware structure
8240  *
8241  *  Enables the transmit data path.
8242  **/
8243 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8244 {
8245         uint32_t sectxreg;
8246
8247         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8248         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8249         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8250         IXGBE_WRITE_FLUSH(hw);
8251
8252         return IXGBE_SUCCESS;
8253 }
8254
8255 /* restore n-tuple filter */
8256 static inline void
8257 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8258 {
8259         struct ixgbe_filter_info *filter_info =
8260                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8261         struct ixgbe_5tuple_filter *node;
8262
8263         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8264                 ixgbe_inject_5tuple_filter(dev, node);
8265         }
8266 }
8267
8268 /* restore ethernet type filter */
8269 static inline void
8270 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8271 {
8272         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8273         struct ixgbe_filter_info *filter_info =
8274                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8275         int i;
8276
8277         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8278                 if (filter_info->ethertype_mask & (1 << i)) {
8279                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8280                                         filter_info->ethertype_filters[i].etqf);
8281                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8282                                         filter_info->ethertype_filters[i].etqs);
8283                         IXGBE_WRITE_FLUSH(hw);
8284                 }
8285         }
8286 }
8287
8288 /* restore SYN filter */
8289 static inline void
8290 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8291 {
8292         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8293         struct ixgbe_filter_info *filter_info =
8294                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8295         uint32_t synqf;
8296
8297         synqf = filter_info->syn_info;
8298
8299         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8300                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8301                 IXGBE_WRITE_FLUSH(hw);
8302         }
8303 }
8304
8305 /* restore L2 tunnel filter */
8306 static inline void
8307 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8308 {
8309         struct ixgbe_l2_tn_info *l2_tn_info =
8310                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8311         struct ixgbe_l2_tn_filter *node;
8312         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8313
8314         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8315                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8316                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8317                 l2_tn_conf.pool           = node->pool;
8318                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8319         }
8320 }
8321
8322 /* restore rss filter */
8323 static inline void
8324 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8325 {
8326         struct ixgbe_filter_info *filter_info =
8327                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8328
8329         if (filter_info->rss_info.num)
8330                 ixgbe_config_rss_filter(dev,
8331                         &filter_info->rss_info, TRUE);
8332 }
8333
8334 static int
8335 ixgbe_filter_restore(struct rte_eth_dev *dev)
8336 {
8337         ixgbe_ntuple_filter_restore(dev);
8338         ixgbe_ethertype_filter_restore(dev);
8339         ixgbe_syn_filter_restore(dev);
8340         ixgbe_fdir_filter_restore(dev);
8341         ixgbe_l2_tn_filter_restore(dev);
8342         ixgbe_rss_filter_restore(dev);
8343
8344         return 0;
8345 }
8346
8347 static void
8348 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8349 {
8350         struct ixgbe_l2_tn_info *l2_tn_info =
8351                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8353
8354         if (l2_tn_info->e_tag_en)
8355                 (void)ixgbe_e_tag_enable(hw);
8356
8357         if (l2_tn_info->e_tag_fwd_en)
8358                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8359
8360         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8361 }
8362
8363 /* remove all the n-tuple filters */
8364 void
8365 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8366 {
8367         struct ixgbe_filter_info *filter_info =
8368                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8369         struct ixgbe_5tuple_filter *p_5tuple;
8370
8371         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8372                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8373 }
8374
8375 /* remove all the ether type filters */
8376 void
8377 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8378 {
8379         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8380         struct ixgbe_filter_info *filter_info =
8381                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8382         int i;
8383
8384         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8385                 if (filter_info->ethertype_mask & (1 << i) &&
8386                     !filter_info->ethertype_filters[i].conf) {
8387                         (void)ixgbe_ethertype_filter_remove(filter_info,
8388                                                             (uint8_t)i);
8389                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8390                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8391                         IXGBE_WRITE_FLUSH(hw);
8392                 }
8393         }
8394 }
8395
8396 /* remove the SYN filter */
8397 void
8398 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8399 {
8400         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8401         struct ixgbe_filter_info *filter_info =
8402                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8403
8404         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8405                 filter_info->syn_info = 0;
8406
8407                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8408                 IXGBE_WRITE_FLUSH(hw);
8409         }
8410 }
8411
8412 /* remove all the L2 tunnel filters */
8413 int
8414 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8415 {
8416         struct ixgbe_l2_tn_info *l2_tn_info =
8417                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8418         struct ixgbe_l2_tn_filter *l2_tn_filter;
8419         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8420         int ret = 0;
8421
8422         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8423                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8424                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8425                 l2_tn_conf.pool           = l2_tn_filter->pool;
8426                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8427                 if (ret < 0)
8428                         return ret;
8429         }
8430
8431         return 0;
8432 }
8433
8434 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8435 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8436 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8437 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8438 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8439 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8440
8441 RTE_INIT(ixgbe_init_log);
8442 static void
8443 ixgbe_init_log(void)
8444 {
8445         ixgbe_logtype_init = rte_log_register("pmd.ixgbe.init");
8446         if (ixgbe_logtype_init >= 0)
8447                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8448         ixgbe_logtype_driver = rte_log_register("pmd.ixgbe.driver");
8449         if (ixgbe_logtype_driver >= 0)
8450                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8451 }