drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 /* Bit shift and mask */
 110 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 111 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 112 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 113 #define IXGBE_8_BIT_MASK   UINT8_MAX
 114
 115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 116
 117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 118
 119 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 120 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 121 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 122 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 124 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 125 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 126 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 130 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 131                                 int wait_to_complete);
 132 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 133                                 struct rte_eth_stats *stats);
 134 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 135 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 136                                              uint16_t queue_id,
 137                                              uint8_t stat_idx,
 138                                              uint8_t is_rx);
 139 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 140                                struct rte_eth_dev_info *dev_info);
 141 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 142                                  struct rte_eth_dev_info *dev_info);
 143 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 144
 145 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 146                 uint16_t vlan_id, int on);
 147 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 148 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 149                 uint16_t queue, bool on);
 150 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 151                 int on);
 152 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 153 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 154 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 155 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 156 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 157
 158 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 159 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 160 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 161                                struct rte_eth_fc_conf *fc_conf);
 162 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 165                 struct rte_eth_pfc_conf *pfc_conf);
 166 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 167                         struct rte_eth_rss_reta_entry64 *reta_conf,
 168                         uint16_t reta_size);
 169 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 170                         struct rte_eth_rss_reta_entry64 *reta_conf,
 171                         uint16_t reta_size);
 172 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 173 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 174 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 177                 void *param);
 178 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 179 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 180                 uint32_t index, uint32_t pool);
 181 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 182 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 183
 184 /* For Virtual Function support */
 185 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 186 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 187 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 188 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 190 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 191 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 192                 struct rte_eth_stats *stats);
 193 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 194 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 195                 uint16_t vlan_id, int on);
 196 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 197                 uint16_t queue, int on);
 198 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 200
 201 /* For Eth VMDQ APIs support */
 202 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 203                 ether_addr* mac_addr,uint8_t on);
 204 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 205 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 206                 uint16_t rx_mask, uint8_t on);
 207 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 208 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 209 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 210                 uint64_t pool_mask,uint8_t vlan_on);
 211 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 212                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 213                 uint8_t rule_id, uint8_t on);
 214 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 215                 uint8_t rule_id);
 216
 217 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 218                 uint16_t queue_idx, uint16_t tx_rate);
 219 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 220                 uint16_t tx_rate, uint64_t q_msk);
 221
 222 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 223                                  struct ether_addr *mac_addr,
 224                                  uint32_t index, uint32_t pool);
 225 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 226 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 227                         struct rte_eth_syn_filter *filter,
 228                         bool add);
 229 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 230                         struct rte_eth_syn_filter *filter);
 231 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 232                         enum rte_filter_op filter_op,
 233                         void *arg);
 234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 235                         struct ixgbe_5tuple_filter *filter);
 236 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 237                         struct ixgbe_5tuple_filter *filter);
 238 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *filter,
 240                         bool add);
 241 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 242                                 enum rte_filter_op filter_op,
 243                                 void *arg);
 244 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 245                         struct rte_eth_ntuple_filter *filter);
 246 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ethertype_filter *filter,
 248                         bool add);
 249 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 250                                 enum rte_filter_op filter_op,
 251                                 void *arg);
 252 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 253                         struct rte_eth_ethertype_filter *filter);
 254 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 255                      enum rte_filter_type filter_type,
 256                      enum rte_filter_op filter_op,
 257                      void *arg);
 258 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 259
 260 /*
 261  * Define VF Stats MACRO for Non "cleared on read" register
 262  */
 263 #define UPDATE_VF_STAT(reg, last, cur)                          \
 264 {                                                               \
 265         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 266         cur += latest - last;                                   \
 267         last = latest;                                          \
 268 }
 269
 270 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 271 {                                                                \
 272         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 273         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 274         u64 latest = ((new_msb << 32) | new_lsb);                \
 275         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 276         last = latest;                                           \
 277 }
 278
 279 #define IXGBE_SET_HWSTRIP(h, q) do{\
 280                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 281                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 (h)->bitmap[idx] |= 1 << bit;\
 283         }while(0)
 284
 285 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 286                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 287                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 288                 (h)->bitmap[idx] &= ~(1 << bit);\
 289         }while(0)
 290
 291 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 292                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 293                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 294                 (r) = (h)->bitmap[idx] >> bit & 1;\
 295         }while(0)
 296
 297 /*
 298  * The set of PCI devices this driver supports
 299  */
 300 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 301
 302 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 303 #include "rte_pci_dev_ids.h"
 304
 305 { .vendor_id = 0, /* sentinel */ },
 306 };
 307
 308
 309 /*
 310  * The set of PCI devices this driver supports (for 82599 VF)
 311  */
 312 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 313
 314 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 315 #include "rte_pci_dev_ids.h"
 316 { .vendor_id = 0, /* sentinel */ },
 317
 318 };
 319
 320 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 321         .dev_configure        = ixgbe_dev_configure,
 322         .dev_start            = ixgbe_dev_start,
 323         .dev_stop             = ixgbe_dev_stop,
 324         .dev_set_link_up    = ixgbe_dev_set_link_up,
 325         .dev_set_link_down  = ixgbe_dev_set_link_down,
 326         .dev_close            = ixgbe_dev_close,
 327         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 328         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 329         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 330         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 331         .link_update          = ixgbe_dev_link_update,
 332         .stats_get            = ixgbe_dev_stats_get,
 333         .stats_reset          = ixgbe_dev_stats_reset,
 334         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 335         .dev_infos_get        = ixgbe_dev_info_get,
 336         .mtu_set              = ixgbe_dev_mtu_set,
 337         .vlan_filter_set      = ixgbe_vlan_filter_set,
 338         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 339         .vlan_offload_set     = ixgbe_vlan_offload_set,
 340         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 341         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 342         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 343         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 344         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 345         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 346         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 347         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 348         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 349         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 350         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 351         .dev_led_on           = ixgbe_dev_led_on,
 352         .dev_led_off          = ixgbe_dev_led_off,
 353         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 354         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 355         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 356         .mac_addr_add         = ixgbe_add_rar,
 357         .mac_addr_remove      = ixgbe_remove_rar,
 358         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 359         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 360         .mirror_rule_set      = ixgbe_mirror_rule_set,
 361         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 362         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 363         .set_vf_rx            = ixgbe_set_pool_rx,
 364         .set_vf_tx            = ixgbe_set_pool_tx,
 365         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 366         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 367         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 368         .reta_update          = ixgbe_dev_rss_reta_update,
 369         .reta_query           = ixgbe_dev_rss_reta_query,
 370 #ifdef RTE_NIC_BYPASS
 371         .bypass_init          = ixgbe_bypass_init,
 372         .bypass_state_set     = ixgbe_bypass_state_store,
 373         .bypass_state_show    = ixgbe_bypass_state_show,
 374         .bypass_event_set     = ixgbe_bypass_event_store,
 375         .bypass_event_show    = ixgbe_bypass_event_show,
 376         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 377         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 378         .bypass_ver_show      = ixgbe_bypass_ver_show,
 379         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 380 #endif /* RTE_NIC_BYPASS */
 381         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 382         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 383         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 384 };
 385
 386 /*
 387  * dev_ops for virtual function, bare necessities for basic vf
 388  * operation have been implemented
 389  */
 390 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 391         .dev_configure        = ixgbevf_dev_configure,
 392         .dev_start            = ixgbevf_dev_start,
 393         .dev_stop             = ixgbevf_dev_stop,
 394         .link_update          = ixgbe_dev_link_update,
 395         .stats_get            = ixgbevf_dev_stats_get,
 396         .stats_reset          = ixgbevf_dev_stats_reset,
 397         .dev_close            = ixgbevf_dev_close,
 398         .dev_infos_get        = ixgbevf_dev_info_get,
 399         .mtu_set              = ixgbevf_dev_set_mtu,
 400         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 401         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 402         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 403         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 404         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 405         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 406         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 407         .mac_addr_add         = ixgbevf_add_mac_addr,
 408         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 409 };
 410
 411 /**
 412  * Atomically reads the link status information from global
 413  * structure rte_eth_dev.
 414  *
 415  * @param dev
 416  *   - Pointer to the structure rte_eth_dev to read from.
 417  *   - Pointer to the buffer to be saved with the link status.
 418  *
 419  * @return
 420  *   - On success, zero.
 421  *   - On failure, negative value.
 422  */
 423 static inline int
 424 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 425                                 struct rte_eth_link *link)
 426 {
 427         struct rte_eth_link *dst = link;
 428         struct rte_eth_link *src = &(dev->data->dev_link);
 429
 430         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 431                                         *(uint64_t *)src) == 0)
 432                 return -1;
 433
 434         return 0;
 435 }
 436
 437 /**
 438  * Atomically writes the link status information into global
 439  * structure rte_eth_dev.
 440  *
 441  * @param dev
 442  *   - Pointer to the structure rte_eth_dev to read from.
 443  *   - Pointer to the buffer to be saved with the link status.
 444  *
 445  * @return
 446  *   - On success, zero.
 447  *   - On failure, negative value.
 448  */
 449 static inline int
 450 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 451                                 struct rte_eth_link *link)
 452 {
 453         struct rte_eth_link *dst = &(dev->data->dev_link);
 454         struct rte_eth_link *src = link;
 455
 456         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 457                                         *(uint64_t *)src) == 0)
 458                 return -1;
 459
 460         return 0;
 461 }
 462
 463 /*
 464  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 465  */
 466 static inline int
 467 ixgbe_is_sfp(struct ixgbe_hw *hw)
 468 {
 469         switch (hw->phy.type) {
 470         case ixgbe_phy_sfp_avago:
 471         case ixgbe_phy_sfp_ftl:
 472         case ixgbe_phy_sfp_intel:
 473         case ixgbe_phy_sfp_unknown:
 474         case ixgbe_phy_sfp_passive_tyco:
 475         case ixgbe_phy_sfp_passive_unknown:
 476                 return 1;
 477         default:
 478                 return 0;
 479         }
 480 }
 481
 482 static inline int32_t
 483 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 484 {
 485         uint32_t ctrl_ext;
 486         int32_t status;
 487
 488         status = ixgbe_reset_hw(hw);
 489
 490         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 491         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 492         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 493         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 494         IXGBE_WRITE_FLUSH(hw);
 495
 496         return status;
 497 }
 498
 499 static inline void
 500 ixgbe_enable_intr(struct rte_eth_dev *dev)
 501 {
 502         struct ixgbe_interrupt *intr =
 503                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 504         struct ixgbe_hw *hw =
 505                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 506
 507         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 508         IXGBE_WRITE_FLUSH(hw);
 509 }
 510
 511 /*
 512  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 513  */
 514 static void
 515 ixgbe_disable_intr(struct ixgbe_hw *hw)
 516 {
 517         PMD_INIT_FUNC_TRACE();
 518
 519         if (hw->mac.type == ixgbe_mac_82598EB) {
 520                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 521         } else {
 522                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 523                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 524                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 525         }
 526         IXGBE_WRITE_FLUSH(hw);
 527 }
 528
 529 /*
 530  * This function resets queue statistics mapping registers.
 531  * From Niantic datasheet, Initialization of Statistics section:
 532  * "...if software requires the queue counters, the RQSMR and TQSM registers
 533  * must be re-programmed following a device reset.
 534  */
 535 static void
 536 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 537 {
 538         uint32_t i;
 539
 540         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 541                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 542                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 543         }
 544 }
 545
 546
 547 static int
 548 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 549                                   uint16_t queue_id,
 550                                   uint8_t stat_idx,
 551                                   uint8_t is_rx)
 552 {
 553 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 554 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 555 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 556
 557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 558         struct ixgbe_stat_mapping_registers *stat_mappings =
 559                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 560         uint32_t qsmr_mask = 0;
 561         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 562         uint32_t q_map;
 563         uint8_t n, offset;
 564
 565         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 566                 (hw->mac.type != ixgbe_mac_X540) &&
 567                 (hw->mac.type != ixgbe_mac_X550) &&
 568                 (hw->mac.type != ixgbe_mac_X550EM_x))
 569                 return -ENOSYS;
 570
 571         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 572                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 573                      queue_id, stat_idx);
 574
 575         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 576         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 577                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 578                 return -EIO;
 579         }
 580         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 581
 582         /* Now clear any previous stat_idx set */
 583         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 584         if (!is_rx)
 585                 stat_mappings->tqsm[n] &= ~clearing_mask;
 586         else
 587                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 588
 589         q_map = (uint32_t)stat_idx;
 590         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 591         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 592         if (!is_rx)
 593                 stat_mappings->tqsm[n] |= qsmr_mask;
 594         else
 595                 stat_mappings->rqsmr[n] |= qsmr_mask;
 596
 597         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 598                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 599                      queue_id, stat_idx);
 600         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 601                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 602
 603         /* Now write the mapping in the appropriate register */
 604         if (is_rx) {
 605                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 606                              stat_mappings->rqsmr[n], n);
 607                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 608         }
 609         else {
 610                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 611                              stat_mappings->tqsm[n], n);
 612                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 613         }
 614         return 0;
 615 }
 616
 617 static void
 618 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 619 {
 620         struct ixgbe_stat_mapping_registers *stat_mappings =
 621                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623         int i;
 624
 625         /* write whatever was in stat mapping table to the NIC */
 626         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 627                 /* rx */
 628                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 629
 630                 /* tx */
 631                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 632         }
 633 }
 634
 635 static void
 636 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 637 {
 638         uint8_t i;
 639         struct ixgbe_dcb_tc_config *tc;
 640         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 641
 642         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 643         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 644         for (i = 0; i < dcb_max_tc; i++) {
 645                 tc = &dcb_config->tc_config[i];
 646                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 647                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 648                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 649                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 650                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 651                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 652                 tc->pfc = ixgbe_dcb_pfc_disabled;
 653         }
 654
 655         /* Initialize default user to priority mapping, UPx->TC0 */
 656         tc = &dcb_config->tc_config[0];
 657         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 658         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 659         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 660                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 661                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 662         }
 663         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 664         dcb_config->pfc_mode_enable = false;
 665         dcb_config->vt_mode = true;
 666         dcb_config->round_robin_enable = false;
 667         /* support all DCB capabilities in 82599 */
 668         dcb_config->support.capabilities = 0xFF;
 669
 670         /*we only support 4 Tcs for X540, X550 */
 671         if (hw->mac.type == ixgbe_mac_X540 ||
 672                 hw->mac.type == ixgbe_mac_X550 ||
 673                 hw->mac.type == ixgbe_mac_X550EM_x) {
 674                 dcb_config->num_tcs.pg_tcs = 4;
 675                 dcb_config->num_tcs.pfc_tcs = 4;
 676         }
 677 }
 678
 679 /*
 680  * Ensure that all locks are released before first NVM or PHY access
 681  */
 682 static void
 683 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 684 {
 685         uint16_t mask;
 686
 687         /*
 688          * Phy lock should not fail in this early stage. If this is the case,
 689          * it is due to an improper exit of the application.
 690          * So force the release of the faulty lock. Release of common lock
 691          * is done automatically by swfw_sync function.
 692          */
 693         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 694         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 695                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 696         }
 697         ixgbe_release_swfw_semaphore(hw, mask);
 698
 699         /*
 700          * These ones are more tricky since they are common to all ports; but
 701          * swfw_sync retries last long enough (1s) to be almost sure that if
 702          * lock can not be taken it is due to an improper lock of the
 703          * semaphore.
 704          */
 705         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 706         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 707                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 708         }
 709         ixgbe_release_swfw_semaphore(hw, mask);
 710 }
 711
 712 /*
 713  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 714  * It returns 0 on success.
 715  */
 716 static int
 717 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 718 {
 719         struct rte_pci_device *pci_dev;
 720         struct ixgbe_hw *hw =
 721                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 722         struct ixgbe_vfta * shadow_vfta =
 723                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 724         struct ixgbe_hwstrip *hwstrip =
 725                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 726         struct ixgbe_dcb_config *dcb_config =
 727                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 728         struct ixgbe_filter_info *filter_info =
 729                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 730         uint32_t ctrl_ext;
 731         uint16_t csum;
 732         int diag, i;
 733
 734         PMD_INIT_FUNC_TRACE();
 735
 736         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 737         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 738         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 739
 740         /*
 741          * For secondary processes, we don't initialise any further as primary
 742          * has already done this work. Only check we don't need a different
 743          * RX and TX function.
 744          */
 745         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 746                 struct ixgbe_tx_queue *txq;
 747                 /* TX queue function in primary, set by last queue initialized
 748                  * Tx queue may not initialized by primary process */
 749                 if (eth_dev->data->tx_queues) {
 750                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 751                         ixgbe_set_tx_function(eth_dev, txq);
 752                 } else {
 753                         /* Use default TX function if we get here */
 754                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 755                                            "Using default TX function.");
 756                 }
 757
 758                 ixgbe_set_rx_function(eth_dev);
 759
 760                 return 0;
 761         }
 762         pci_dev = eth_dev->pci_dev;
 763
 764         /* Vendor and Device ID need to be set before init of shared code */
 765         hw->device_id = pci_dev->id.device_id;
 766         hw->vendor_id = pci_dev->id.vendor_id;
 767         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 768         hw->allow_unsupported_sfp = 1;
 769
 770         /* Initialize the shared code (base driver) */
 771 #ifdef RTE_NIC_BYPASS
 772         diag = ixgbe_bypass_init_shared_code(hw);
 773 #else
 774         diag = ixgbe_init_shared_code(hw);
 775 #endif /* RTE_NIC_BYPASS */
 776
 777         if (diag != IXGBE_SUCCESS) {
 778                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 779                 return -EIO;
 780         }
 781
 782         /* pick up the PCI bus settings for reporting later */
 783         ixgbe_get_bus_info(hw);
 784
 785         /* Unlock any pending hardware semaphore */
 786         ixgbe_swfw_lock_reset(hw);
 787
 788         /* Initialize DCB configuration*/
 789         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 790         ixgbe_dcb_init(hw,dcb_config);
 791         /* Get Hardware Flow Control setting */
 792         hw->fc.requested_mode = ixgbe_fc_full;
 793         hw->fc.current_mode = ixgbe_fc_full;
 794         hw->fc.pause_time = IXGBE_FC_PAUSE;
 795         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 796                 hw->fc.low_water[i] = IXGBE_FC_LO;
 797                 hw->fc.high_water[i] = IXGBE_FC_HI;
 798         }
 799         hw->fc.send_xon = 1;
 800
 801         /* Make sure we have a good EEPROM before we read from it */
 802         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 803         if (diag != IXGBE_SUCCESS) {
 804                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 805                 return -EIO;
 806         }
 807
 808 #ifdef RTE_NIC_BYPASS
 809         diag = ixgbe_bypass_init_hw(hw);
 810 #else
 811         diag = ixgbe_init_hw(hw);
 812 #endif /* RTE_NIC_BYPASS */
 813
 814         /*
 815          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 816          * is called too soon after the kernel driver unbinding/binding occurs.
 817          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 818          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 819          * also called. See ixgbe_identify_phy_82599(). The reason for the
 820          * failure is not known, and only occuts when virtualisation features
 821          * are disabled in the bios. A delay of 100ms  was found to be enough by
 822          * trial-and-error, and is doubled to be safe.
 823          */
 824         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 825                 rte_delay_ms(200);
 826                 diag = ixgbe_init_hw(hw);
 827         }
 828
 829         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 830                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 831                     "LOM.  Please be aware there may be issues associated "
 832                     "with your hardware.");
 833                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 834                     "please contact your Intel or hardware representative "
 835                     "who provided you with this hardware.");
 836         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 837                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 838         if (diag) {
 839                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 840                 return -EIO;
 841         }
 842
 843         /* disable interrupt */
 844         ixgbe_disable_intr(hw);
 845
 846         /* reset mappings for queue statistics hw counters*/
 847         ixgbe_reset_qstat_mappings(hw);
 848
 849         /* Allocate memory for storing MAC addresses */
 850         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 851                         hw->mac.num_rar_entries, 0);
 852         if (eth_dev->data->mac_addrs == NULL) {
 853                 PMD_INIT_LOG(ERR,
 854                         "Failed to allocate %u bytes needed to store "
 855                         "MAC addresses",
 856                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 857                 return -ENOMEM;
 858         }
 859         /* Copy the permanent MAC address */
 860         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 861                         &eth_dev->data->mac_addrs[0]);
 862
 863         /* Allocate memory for storing hash filter MAC addresses */
 864         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 865                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 866         if (eth_dev->data->hash_mac_addrs == NULL) {
 867                 PMD_INIT_LOG(ERR,
 868                         "Failed to allocate %d bytes needed to store MAC addresses",
 869                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 870                 return -ENOMEM;
 871         }
 872
 873         /* initialize the vfta */
 874         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 875
 876         /* initialize the hw strip bitmap*/
 877         memset(hwstrip, 0, sizeof(*hwstrip));
 878
 879         /* initialize PF if max_vfs not zero */
 880         ixgbe_pf_host_init(eth_dev);
 881
 882         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 883         /* let hardware know driver is loaded */
 884         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 885         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 886         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 887         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 888         IXGBE_WRITE_FLUSH(hw);
 889
 890         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 891                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 892                              (int) hw->mac.type, (int) hw->phy.type,
 893                              (int) hw->phy.sfp_type);
 894         else
 895                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 896                              (int) hw->mac.type, (int) hw->phy.type);
 897
 898         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 899                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 900                         pci_dev->id.device_id);
 901
 902         rte_intr_callback_register(&(pci_dev->intr_handle),
 903                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 904
 905         /* enable uio intr after callback register */
 906         rte_intr_enable(&(pci_dev->intr_handle));
 907
 908         /* enable support intr */
 909         ixgbe_enable_intr(eth_dev);
 910
 911         /* initialize 5tuple filter list */
 912         TAILQ_INIT(&filter_info->fivetuple_list);
 913         memset(filter_info->fivetuple_mask, 0,
 914                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
 915
 916         return 0;
 917 }
 918
 919
 920 /*
 921  * Negotiate mailbox API version with the PF.
 922  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 923  * Then we try to negotiate starting with the most recent one.
 924  * If all negotiation attempts fail, then we will proceed with
 925  * the default one (ixgbe_mbox_api_10).
 926  */
 927 static void
 928 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 929 {
 930         int32_t i;
 931
 932         /* start with highest supported, proceed down */
 933         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 934                 ixgbe_mbox_api_11,
 935                 ixgbe_mbox_api_10,
 936         };
 937
 938         for (i = 0;
 939                         i != RTE_DIM(sup_ver) &&
 940                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 941                         i++)
 942                 ;
 943 }
 944
 945 static void
 946 generate_random_mac_addr(struct ether_addr *mac_addr)
 947 {
 948         uint64_t random;
 949
 950         /* Set Organizationally Unique Identifier (OUI) prefix. */
 951         mac_addr->addr_bytes[0] = 0x00;
 952         mac_addr->addr_bytes[1] = 0x09;
 953         mac_addr->addr_bytes[2] = 0xC0;
 954         /* Force indication of locally assigned MAC address. */
 955         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 956         /* Generate the last 3 bytes of the MAC address with a random number. */
 957         random = rte_rand();
 958         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 959 }
 960
 961 /*
 962  * Virtual Function device init
 963  */
 964 static int
 965 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
 966 {
 967         int diag;
 968         uint32_t tc, tcs;
 969         struct rte_pci_device *pci_dev;
 970         struct ixgbe_hw *hw =
 971                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 972         struct ixgbe_vfta * shadow_vfta =
 973                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 974         struct ixgbe_hwstrip *hwstrip =
 975                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 976         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 977
 978         PMD_INIT_FUNC_TRACE();
 979
 980         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 981         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 982         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 983
 984         /* for secondary processes, we don't initialise any further as primary
 985          * has already done this work. Only check we don't need a different
 986          * RX function */
 987         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 988                 if (eth_dev->data->scattered_rx)
 989                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
 990                 return 0;
 991         }
 992
 993         pci_dev = eth_dev->pci_dev;
 994
 995         hw->device_id = pci_dev->id.device_id;
 996         hw->vendor_id = pci_dev->id.vendor_id;
 997         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 998
 999         /* initialize the vfta */
1000         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1001
1002         /* initialize the hw strip bitmap*/
1003         memset(hwstrip, 0, sizeof(*hwstrip));
1004
1005         /* Initialize the shared code (base driver) */
1006         diag = ixgbe_init_shared_code(hw);
1007         if (diag != IXGBE_SUCCESS) {
1008                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1009                 return -EIO;
1010         }
1011
1012         /* init_mailbox_params */
1013         hw->mbx.ops.init_params(hw);
1014
1015         /* Disable the interrupts for VF */
1016         ixgbevf_intr_disable(hw);
1017
1018         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1019         diag = hw->mac.ops.reset_hw(hw);
1020
1021         /*
1022          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1023          * the underlying PF driver has not assigned a MAC address to the VF.
1024          * In this case, assign a random MAC address.
1025          */
1026         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1027                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1028                 return (diag);
1029         }
1030
1031         /* negotiate mailbox API version to use with the PF. */
1032         ixgbevf_negotiate_api(hw);
1033
1034         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1035         ixgbevf_get_queues(hw, &tcs, &tc);
1036
1037         /* Allocate memory for storing MAC addresses */
1038         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1039                         hw->mac.num_rar_entries, 0);
1040         if (eth_dev->data->mac_addrs == NULL) {
1041                 PMD_INIT_LOG(ERR,
1042                         "Failed to allocate %u bytes needed to store "
1043                         "MAC addresses",
1044                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1045                 return -ENOMEM;
1046         }
1047
1048         /* Generate a random MAC address, if none was assigned by PF. */
1049         if (is_zero_ether_addr(perm_addr)) {
1050                 generate_random_mac_addr(perm_addr);
1051                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1052                 if (diag) {
1053                         rte_free(eth_dev->data->mac_addrs);
1054                         eth_dev->data->mac_addrs = NULL;
1055                         return diag;
1056                 }
1057                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1058                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1059                              "%02x:%02x:%02x:%02x:%02x:%02x",
1060                              perm_addr->addr_bytes[0],
1061                              perm_addr->addr_bytes[1],
1062                              perm_addr->addr_bytes[2],
1063                              perm_addr->addr_bytes[3],
1064                              perm_addr->addr_bytes[4],
1065                              perm_addr->addr_bytes[5]);
1066         }
1067
1068         /* Copy the permanent MAC address */
1069         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1070
1071         /* reset the hardware with the new settings */
1072         diag = hw->mac.ops.start_hw(hw);
1073         switch (diag) {
1074                 case  0:
1075                         break;
1076
1077                 default:
1078                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1079                         return (-EIO);
1080         }
1081
1082         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1083                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1084                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1085
1086         return 0;
1087 }
1088
1089 static struct eth_driver rte_ixgbe_pmd = {
1090         .pci_drv = {
1091                 .name = "rte_ixgbe_pmd",
1092                 .id_table = pci_id_ixgbe_map,
1093                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1094         },
1095         .eth_dev_init = eth_ixgbe_dev_init,
1096         .dev_private_size = sizeof(struct ixgbe_adapter),
1097 };
1098
1099 /*
1100  * virtual function driver struct
1101  */
1102 static struct eth_driver rte_ixgbevf_pmd = {
1103         .pci_drv = {
1104                 .name = "rte_ixgbevf_pmd",
1105                 .id_table = pci_id_ixgbevf_map,
1106                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1107         },
1108         .eth_dev_init = eth_ixgbevf_dev_init,
1109         .dev_private_size = sizeof(struct ixgbe_adapter),
1110 };
1111
1112 /*
1113  * Driver initialization routine.
1114  * Invoked once at EAL init time.
1115  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1116  */
1117 static int
1118 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1119 {
1120         PMD_INIT_FUNC_TRACE();
1121
1122         rte_eth_driver_register(&rte_ixgbe_pmd);
1123         return 0;
1124 }
1125
1126 /*
1127  * VF Driver initialization routine.
1128  * Invoked one at EAL init time.
1129  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1130  */
1131 static int
1132 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1133 {
1134         PMD_INIT_FUNC_TRACE();
1135
1136         rte_eth_driver_register(&rte_ixgbevf_pmd);
1137         return (0);
1138 }
1139
1140 static int
1141 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1142 {
1143         struct ixgbe_hw *hw =
1144                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1145         struct ixgbe_vfta * shadow_vfta =
1146                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1147         uint32_t vfta;
1148         uint32_t vid_idx;
1149         uint32_t vid_bit;
1150
1151         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1152         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1153         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1154         if (on)
1155                 vfta |= vid_bit;
1156         else
1157                 vfta &= ~vid_bit;
1158         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1159
1160         /* update local VFTA copy */
1161         shadow_vfta->vfta[vid_idx] = vfta;
1162
1163         return 0;
1164 }
1165
1166 static void
1167 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1168 {
1169         if (on)
1170                 ixgbe_vlan_hw_strip_enable(dev, queue);
1171         else
1172                 ixgbe_vlan_hw_strip_disable(dev, queue);
1173 }
1174
1175 static void
1176 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1177 {
1178         struct ixgbe_hw *hw =
1179                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1180
1181         /* Only the high 16-bits is valid */
1182         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1183 }
1184
1185 void
1186 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1187 {
1188         struct ixgbe_hw *hw =
1189                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1190         uint32_t vlnctrl;
1191
1192         PMD_INIT_FUNC_TRACE();
1193
1194         /* Filter Table Disable */
1195         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1196         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1197
1198         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1199 }
1200
1201 void
1202 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1203 {
1204         struct ixgbe_hw *hw =
1205                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1206         struct ixgbe_vfta * shadow_vfta =
1207                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1208         uint32_t vlnctrl;
1209         uint16_t i;
1210
1211         PMD_INIT_FUNC_TRACE();
1212
1213         /* Filter Table Enable */
1214         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1215         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1216         vlnctrl |= IXGBE_VLNCTRL_VFE;
1217
1218         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1219
1220         /* write whatever is in local vfta copy */
1221         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1222                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1223 }
1224
1225 static void
1226 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1227 {
1228         struct ixgbe_hwstrip *hwstrip =
1229                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1230
1231         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1232                 return;
1233
1234         if (on)
1235                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1236         else
1237                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1238 }
1239
1240 static void
1241 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1242 {
1243         struct ixgbe_hw *hw =
1244                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245         uint32_t ctrl;
1246
1247         PMD_INIT_FUNC_TRACE();
1248
1249         if (hw->mac.type == ixgbe_mac_82598EB) {
1250                 /* No queue level support */
1251                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1252                 return;
1253         }
1254         else {
1255                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1256                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1257                 ctrl &= ~IXGBE_RXDCTL_VME;
1258                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1259         }
1260         /* record those setting for HW strip per queue */
1261         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1262 }
1263
1264 static void
1265 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1266 {
1267         struct ixgbe_hw *hw =
1268                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1269         uint32_t ctrl;
1270
1271         PMD_INIT_FUNC_TRACE();
1272
1273         if (hw->mac.type == ixgbe_mac_82598EB) {
1274                 /* No queue level supported */
1275                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1276                 return;
1277         }
1278         else {
1279                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1280                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1281                 ctrl |= IXGBE_RXDCTL_VME;
1282                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1283         }
1284         /* record those setting for HW strip per queue */
1285         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1286 }
1287
1288 void
1289 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1290 {
1291         struct ixgbe_hw *hw =
1292                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1293         uint32_t ctrl;
1294         uint16_t i;
1295
1296         PMD_INIT_FUNC_TRACE();
1297
1298         if (hw->mac.type == ixgbe_mac_82598EB) {
1299                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1300                 ctrl &= ~IXGBE_VLNCTRL_VME;
1301                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1302         }
1303         else {
1304                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1305                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1306                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1307                         ctrl &= ~IXGBE_RXDCTL_VME;
1308                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1309
1310                         /* record those setting for HW strip per queue */
1311                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1312                 }
1313         }
1314 }
1315
1316 void
1317 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1318 {
1319         struct ixgbe_hw *hw =
1320                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1321         uint32_t ctrl;
1322         uint16_t i;
1323
1324         PMD_INIT_FUNC_TRACE();
1325
1326         if (hw->mac.type == ixgbe_mac_82598EB) {
1327                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1328                 ctrl |= IXGBE_VLNCTRL_VME;
1329                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1330         }
1331         else {
1332                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1333                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1334                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1335                         ctrl |= IXGBE_RXDCTL_VME;
1336                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1337
1338                         /* record those setting for HW strip per queue */
1339                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1340                 }
1341         }
1342 }
1343
1344 static void
1345 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1346 {
1347         struct ixgbe_hw *hw =
1348                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349         uint32_t ctrl;
1350
1351         PMD_INIT_FUNC_TRACE();
1352
1353         /* DMATXCTRL: Geric Double VLAN Disable */
1354         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1355         ctrl &= ~IXGBE_DMATXCTL_GDV;
1356         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1357
1358         /* CTRL_EXT: Global Double VLAN Disable */
1359         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1360         ctrl &= ~IXGBE_EXTENDED_VLAN;
1361         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1362
1363 }
1364
1365 static void
1366 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1367 {
1368         struct ixgbe_hw *hw =
1369                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370         uint32_t ctrl;
1371
1372         PMD_INIT_FUNC_TRACE();
1373
1374         /* DMATXCTRL: Geric Double VLAN Enable */
1375         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1376         ctrl |= IXGBE_DMATXCTL_GDV;
1377         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1378
1379         /* CTRL_EXT: Global Double VLAN Enable */
1380         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1381         ctrl |= IXGBE_EXTENDED_VLAN;
1382         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1383
1384         /*
1385          * VET EXT field in the EXVET register = 0x8100 by default
1386          * So no need to change. Same to VT field of DMATXCTL register
1387          */
1388 }
1389
1390 static void
1391 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1392 {
1393         if(mask & ETH_VLAN_STRIP_MASK){
1394                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1395                         ixgbe_vlan_hw_strip_enable_all(dev);
1396                 else
1397                         ixgbe_vlan_hw_strip_disable_all(dev);
1398         }
1399
1400         if(mask & ETH_VLAN_FILTER_MASK){
1401                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1402                         ixgbe_vlan_hw_filter_enable(dev);
1403                 else
1404                         ixgbe_vlan_hw_filter_disable(dev);
1405         }
1406
1407         if(mask & ETH_VLAN_EXTEND_MASK){
1408                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1409                         ixgbe_vlan_hw_extend_enable(dev);
1410                 else
1411                         ixgbe_vlan_hw_extend_disable(dev);
1412         }
1413 }
1414
1415 static void
1416 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1417 {
1418         struct ixgbe_hw *hw =
1419                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1420         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1421         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1422         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1423         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1424 }
1425
1426 static int
1427 ixgbe_dev_configure(struct rte_eth_dev *dev)
1428 {
1429         struct ixgbe_interrupt *intr =
1430                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1431         struct ixgbe_adapter *adapter =
1432                 (struct ixgbe_adapter *)dev->data->dev_private;
1433
1434         PMD_INIT_FUNC_TRACE();
1435
1436         /* set flag to update link status after init */
1437         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1438
1439         /*
1440          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1441          * allocation or vector Rx preconditions we will reset it.
1442          */
1443         adapter->rx_bulk_alloc_allowed = true;
1444         adapter->rx_vec_allowed = true;
1445
1446         return 0;
1447 }
1448
1449 /*
1450  * Configure device link speed and setup link.
1451  * It returns 0 on success.
1452  */
1453 static int
1454 ixgbe_dev_start(struct rte_eth_dev *dev)
1455 {
1456         struct ixgbe_hw *hw =
1457                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458         struct ixgbe_vf_info *vfinfo =
1459                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1460         int err, link_up = 0, negotiate = 0;
1461         uint32_t speed = 0;
1462         int mask = 0;
1463         int status;
1464         uint16_t vf, idx;
1465
1466         PMD_INIT_FUNC_TRACE();
1467
1468         /* IXGBE devices don't support half duplex */
1469         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1470                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1471                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1472                              dev->data->dev_conf.link_duplex,
1473                              dev->data->port_id);
1474                 return -EINVAL;
1475         }
1476
1477         /* stop adapter */
1478         hw->adapter_stopped = FALSE;
1479         ixgbe_stop_adapter(hw);
1480
1481         /* reinitialize adapter
1482          * this calls reset and start */
1483         status = ixgbe_pf_reset_hw(hw);
1484         if (status != 0)
1485                 return -1;
1486         hw->mac.ops.start_hw(hw);
1487         hw->mac.get_link_status = true;
1488
1489         /* configure PF module if SRIOV enabled */
1490         ixgbe_pf_host_configure(dev);
1491
1492         /* initialize transmission unit */
1493         ixgbe_dev_tx_init(dev);
1494
1495         /* This can fail when allocating mbufs for descriptor rings */
1496         err = ixgbe_dev_rx_init(dev);
1497         if (err) {
1498                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1499                 goto error;
1500         }
1501
1502         err = ixgbe_dev_rxtx_start(dev);
1503         if (err < 0) {
1504                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1505                 goto error;
1506         }
1507
1508         /* Skip link setup if loopback mode is enabled for 82599. */
1509         if (hw->mac.type == ixgbe_mac_82599EB &&
1510                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1511                 goto skip_link_setup;
1512
1513         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1514                 err = hw->mac.ops.setup_sfp(hw);
1515                 if (err)
1516                         goto error;
1517         }
1518
1519         /* Turn on the laser */
1520         ixgbe_enable_tx_laser(hw);
1521
1522         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1523         if (err)
1524                 goto error;
1525         dev->data->dev_link.link_status = link_up;
1526
1527         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1528         if (err)
1529                 goto error;
1530
1531         switch(dev->data->dev_conf.link_speed) {
1532         case ETH_LINK_SPEED_AUTONEG:
1533                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1534                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1535                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1536                 break;
1537         case ETH_LINK_SPEED_100:
1538                 /*
1539                  * Invalid for 82598 but error will be detected by
1540                  * ixgbe_setup_link()
1541                  */
1542                 speed = IXGBE_LINK_SPEED_100_FULL;
1543                 break;
1544         case ETH_LINK_SPEED_1000:
1545                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1546                 break;
1547         case ETH_LINK_SPEED_10000:
1548                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1549                 break;
1550         default:
1551                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1552                              dev->data->dev_conf.link_speed,
1553                              dev->data->port_id);
1554                 goto error;
1555         }
1556
1557         err = ixgbe_setup_link(hw, speed, link_up);
1558         if (err)
1559                 goto error;
1560
1561 skip_link_setup:
1562
1563         /* check if lsc interrupt is enabled */
1564         if (dev->data->dev_conf.intr_conf.lsc != 0)
1565                 ixgbe_dev_lsc_interrupt_setup(dev);
1566
1567         /* resume enabled intr since hw reset */
1568         ixgbe_enable_intr(dev);
1569
1570         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1571                 ETH_VLAN_EXTEND_MASK;
1572         ixgbe_vlan_offload_set(dev, mask);
1573
1574         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1575                 /* Enable vlan filtering for VMDq */
1576                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1577         }
1578
1579         /* Configure DCB hw */
1580         ixgbe_configure_dcb(dev);
1581
1582         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1583                 err = ixgbe_fdir_configure(dev);
1584                 if (err)
1585                         goto error;
1586         }
1587
1588         /* Restore vf rate limit */
1589         if (vfinfo != NULL) {
1590                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1591                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1592                                 if (vfinfo[vf].tx_rate[idx] != 0)
1593                                         ixgbe_set_vf_rate_limit(dev, vf,
1594                                                 vfinfo[vf].tx_rate[idx],
1595                                                 1 << idx);
1596         }
1597
1598         ixgbe_restore_statistics_mapping(dev);
1599
1600         return (0);
1601
1602 error:
1603         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1604         ixgbe_dev_clear_queues(dev);
1605         return -EIO;
1606 }
1607
1608 /*
1609  * Stop device: disable rx and tx functions to allow for reconfiguring.
1610  */
1611 static void
1612 ixgbe_dev_stop(struct rte_eth_dev *dev)
1613 {
1614         struct rte_eth_link link;
1615         struct ixgbe_hw *hw =
1616                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617         struct ixgbe_vf_info *vfinfo =
1618                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1619         struct ixgbe_filter_info *filter_info =
1620                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1621         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1622         int vf;
1623
1624         PMD_INIT_FUNC_TRACE();
1625
1626         /* disable interrupts */
1627         ixgbe_disable_intr(hw);
1628
1629         /* reset the NIC */
1630         ixgbe_pf_reset_hw(hw);
1631         hw->adapter_stopped = FALSE;
1632
1633         /* stop adapter */
1634         ixgbe_stop_adapter(hw);
1635
1636         for (vf = 0; vfinfo != NULL &&
1637                      vf < dev->pci_dev->max_vfs; vf++)
1638                 vfinfo[vf].clear_to_send = false;
1639
1640         /* Turn off the laser */
1641         ixgbe_disable_tx_laser(hw);
1642
1643         ixgbe_dev_clear_queues(dev);
1644
1645         /* Clear stored conf */
1646         dev->data->scattered_rx = 0;
1647         dev->data->lro = 0;
1648
1649         /* Clear recorded link status */
1650         memset(&link, 0, sizeof(link));
1651         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1652
1653         /* Remove all ntuple filters of the device */
1654         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1655              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1656                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1657                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1658                              p_5tuple, entries);
1659                 rte_free(p_5tuple);
1660         }
1661         memset(filter_info->fivetuple_mask, 0,
1662                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1663
1664 }
1665
1666 /*
1667  * Set device link up: enable tx laser.
1668  */
1669 static int
1670 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1671 {
1672         struct ixgbe_hw *hw =
1673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         if (hw->mac.type == ixgbe_mac_82599EB) {
1675 #ifdef RTE_NIC_BYPASS
1676                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1677                         /* Not suported in bypass mode */
1678                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1679                                      "by device id 0x%x", hw->device_id);
1680                         return -ENOTSUP;
1681                 }
1682 #endif
1683                 /* Turn on the laser */
1684                 ixgbe_enable_tx_laser(hw);
1685                 return 0;
1686         }
1687
1688         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1689                      hw->device_id);
1690         return -ENOTSUP;
1691 }
1692
1693 /*
1694  * Set device link down: disable tx laser.
1695  */
1696 static int
1697 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1698 {
1699         struct ixgbe_hw *hw =
1700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701         if (hw->mac.type == ixgbe_mac_82599EB) {
1702 #ifdef RTE_NIC_BYPASS
1703                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1704                         /* Not suported in bypass mode */
1705                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1706                                      "by device id 0x%x", hw->device_id);
1707                         return -ENOTSUP;
1708                 }
1709 #endif
1710                 /* Turn off the laser */
1711                 ixgbe_disable_tx_laser(hw);
1712                 return 0;
1713         }
1714
1715         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1716                      hw->device_id);
1717         return -ENOTSUP;
1718 }
1719
1720 /*
1721  * Reest and stop device.
1722  */
1723 static void
1724 ixgbe_dev_close(struct rte_eth_dev *dev)
1725 {
1726         struct ixgbe_hw *hw =
1727                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1728
1729         PMD_INIT_FUNC_TRACE();
1730
1731         ixgbe_pf_reset_hw(hw);
1732
1733         ixgbe_dev_stop(dev);
1734         hw->adapter_stopped = 1;
1735
1736         ixgbe_disable_pcie_master(hw);
1737
1738         /* reprogram the RAR[0] in case user changed it. */
1739         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1740 }
1741
1742 /*
1743  * This function is based on ixgbe_update_stats_counters() in base/ixgbe.c
1744  */
1745 static void
1746 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1747 {
1748         struct ixgbe_hw *hw =
1749                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750         struct ixgbe_hw_stats *hw_stats =
1751                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1752         uint32_t bprc, lxon, lxoff, total;
1753         uint64_t total_missed_rx, total_qbrc, total_qprc;
1754         unsigned i;
1755
1756         total_missed_rx = 0;
1757         total_qbrc = 0;
1758         total_qprc = 0;
1759
1760         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1761         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1762         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1763         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1764
1765         for (i = 0; i < 8; i++) {
1766                 uint32_t mp;
1767                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1768                 /* global total per queue */
1769                 hw_stats->mpc[i] += mp;
1770                 /* Running comprehensive total for stats display */
1771                 total_missed_rx += hw_stats->mpc[i];
1772                 if (hw->mac.type == ixgbe_mac_82598EB)
1773                         hw_stats->rnbc[i] +=
1774                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1775                 hw_stats->pxontxc[i] +=
1776                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1777                 hw_stats->pxonrxc[i] +=
1778                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1779                 hw_stats->pxofftxc[i] +=
1780                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1781                 hw_stats->pxoffrxc[i] +=
1782                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1783                 hw_stats->pxon2offc[i] +=
1784                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1785         }
1786         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1787                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1788                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1789                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1790                 hw_stats->qbrc[i] +=
1791                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1792                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1793                 hw_stats->qbtc[i] +=
1794                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1795                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1796
1797                 total_qprc += hw_stats->qprc[i];
1798                 total_qbrc += hw_stats->qbrc[i];
1799         }
1800         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1801         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1802         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1803
1804         /* Note that gprc counts missed packets */
1805         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1806
1807         if (hw->mac.type != ixgbe_mac_82598EB) {
1808                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1809                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1810                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1811                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1812                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1813                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1814                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1815                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1816         } else {
1817                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1818                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1819                 /* 82598 only has a counter in the high register */
1820                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1821                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1822                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1823         }
1824
1825         /*
1826          * Workaround: mprc hardware is incorrectly counting
1827          * broadcasts, so for now we subtract those.
1828          */
1829         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1830         hw_stats->bprc += bprc;
1831         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1832         if (hw->mac.type == ixgbe_mac_82598EB)
1833                 hw_stats->mprc -= bprc;
1834
1835         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1836         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1837         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1838         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1839         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1840         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1841
1842         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1843         hw_stats->lxontxc += lxon;
1844         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1845         hw_stats->lxofftxc += lxoff;
1846         total = lxon + lxoff;
1847
1848         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1849         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1850         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1851         hw_stats->gptc -= total;
1852         hw_stats->mptc -= total;
1853         hw_stats->ptc64 -= total;
1854         hw_stats->gotc -= total * ETHER_MIN_LEN;
1855
1856         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1857         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1858         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1859         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1860         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1861         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1862         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1863         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1864         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1865         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1866         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1867         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1868         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1869         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1870         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1871         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1872         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1873         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1874         /* Only read FCOE on 82599 */
1875         if (hw->mac.type != ixgbe_mac_82598EB) {
1876                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1877                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1878                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1879                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1880                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1881         }
1882
1883         if (stats == NULL)
1884                 return;
1885
1886         /* Fill out the rte_eth_stats statistics structure */
1887         stats->ipackets = total_qprc;
1888         stats->ibytes = total_qbrc;
1889         stats->opackets = hw_stats->gptc;
1890         stats->obytes = hw_stats->gotc;
1891         stats->imcasts = hw_stats->mprc;
1892
1893         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1894                 stats->q_ipackets[i] = hw_stats->qprc[i];
1895                 stats->q_opackets[i] = hw_stats->qptc[i];
1896                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1897                 stats->q_obytes[i] = hw_stats->qbtc[i];
1898                 stats->q_errors[i] = hw_stats->qprdc[i];
1899         }
1900
1901         /* Rx Errors */
1902         stats->ibadcrc  = hw_stats->crcerrs;
1903         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1904         stats->imissed  = total_missed_rx;
1905         stats->ierrors  = stats->ibadcrc +
1906                           stats->ibadlen +
1907                           stats->imissed +
1908                           hw_stats->illerrc + hw_stats->errbc;
1909
1910         /* Tx Errors */
1911         stats->oerrors  = 0;
1912
1913         /* XON/XOFF pause frames */
1914         stats->tx_pause_xon  = hw_stats->lxontxc;
1915         stats->rx_pause_xon  = hw_stats->lxonrxc;
1916         stats->tx_pause_xoff = hw_stats->lxofftxc;
1917         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1918
1919         /* Flow Director Stats registers */
1920         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1921         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1922         stats->fdirmatch = hw_stats->fdirmatch;
1923         stats->fdirmiss = hw_stats->fdirmiss;
1924 }
1925
1926 static void
1927 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1928 {
1929         struct ixgbe_hw_stats *stats =
1930                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1931
1932         /* HW registers are cleared on read */
1933         ixgbe_dev_stats_get(dev, NULL);
1934
1935         /* Reset software totals */
1936         memset(stats, 0, sizeof(*stats));
1937 }
1938
1939 static void
1940 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1941 {
1942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1944                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1945
1946         /* Good Rx packet, include VF loopback */
1947         UPDATE_VF_STAT(IXGBE_VFGPRC,
1948             hw_stats->last_vfgprc, hw_stats->vfgprc);
1949
1950         /* Good Rx octets, include VF loopback */
1951         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1952             hw_stats->last_vfgorc, hw_stats->vfgorc);
1953
1954         /* Good Tx packet, include VF loopback */
1955         UPDATE_VF_STAT(IXGBE_VFGPTC,
1956             hw_stats->last_vfgptc, hw_stats->vfgptc);
1957
1958         /* Good Tx octets, include VF loopback */
1959         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1960             hw_stats->last_vfgotc, hw_stats->vfgotc);
1961
1962         /* Rx Multicst Packet */
1963         UPDATE_VF_STAT(IXGBE_VFMPRC,
1964             hw_stats->last_vfmprc, hw_stats->vfmprc);
1965
1966         if (stats == NULL)
1967                 return;
1968
1969         stats->ipackets = hw_stats->vfgprc;
1970         stats->ibytes = hw_stats->vfgorc;
1971         stats->opackets = hw_stats->vfgptc;
1972         stats->obytes = hw_stats->vfgotc;
1973         stats->imcasts = hw_stats->vfmprc;
1974 }
1975
1976 static void
1977 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1978 {
1979         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1980                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1981
1982         /* Sync HW register to the last stats */
1983         ixgbevf_dev_stats_get(dev, NULL);
1984
1985         /* reset HW current stats*/
1986         hw_stats->vfgprc = 0;
1987         hw_stats->vfgorc = 0;
1988         hw_stats->vfgptc = 0;
1989         hw_stats->vfgotc = 0;
1990         hw_stats->vfmprc = 0;
1991
1992 }
1993
1994 static void
1995 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1996 {
1997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998
1999         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2000         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2001         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2002         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2003         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2004         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2005         dev_info->max_vfs = dev->pci_dev->max_vfs;
2006         if (hw->mac.type == ixgbe_mac_82598EB)
2007                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2008         else
2009                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2010         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2011         dev_info->rx_offload_capa =
2012                 DEV_RX_OFFLOAD_VLAN_STRIP |
2013                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2014                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2015                 DEV_RX_OFFLOAD_TCP_CKSUM;
2016
2017         /*
2018          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2019          * mode.
2020          */
2021         if ((hw->mac.type == ixgbe_mac_82599EB ||
2022              hw->mac.type == ixgbe_mac_X540) &&
2023             !RTE_ETH_DEV_SRIOV(dev).active)
2024                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2025
2026         dev_info->tx_offload_capa =
2027                 DEV_TX_OFFLOAD_VLAN_INSERT |
2028                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2029                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2030                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2031                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2032                 DEV_TX_OFFLOAD_TCP_TSO;
2033
2034         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2035                 .rx_thresh = {
2036                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2037                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2038                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2039                 },
2040                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2041                 .rx_drop_en = 0,
2042         };
2043
2044         dev_info->default_txconf = (struct rte_eth_txconf) {
2045                 .tx_thresh = {
2046                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2047                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2048                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2049                 },
2050                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2051                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2052                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2053                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2054         };
2055         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2056         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2057 }
2058
2059 static void
2060 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2061                      struct rte_eth_dev_info *dev_info)
2062 {
2063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2064
2065         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2066         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2067         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2068         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2069         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2070         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2071         dev_info->max_vfs = dev->pci_dev->max_vfs;
2072         if (hw->mac.type == ixgbe_mac_82598EB)
2073                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2074         else
2075                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2076         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2077                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2078                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2079                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2080         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2081                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2082                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2083                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2084                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2085
2086         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2087                 .rx_thresh = {
2088                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2089                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2090                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2091                 },
2092                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2093                 .rx_drop_en = 0,
2094         };
2095
2096         dev_info->default_txconf = (struct rte_eth_txconf) {
2097                 .tx_thresh = {
2098                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2099                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2100                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2101                 },
2102                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2103                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2104                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2105                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2106         };
2107 }
2108
2109 /* return 0 means link status changed, -1 means not changed */
2110 static int
2111 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2112 {
2113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2114         struct rte_eth_link link, old;
2115         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2116         int link_up;
2117         int diag;
2118
2119         link.link_status = 0;
2120         link.link_speed = 0;
2121         link.link_duplex = 0;
2122         memset(&old, 0, sizeof(old));
2123         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2124
2125         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2126         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2127                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2128         else
2129                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2130         if (diag != 0) {
2131                 link.link_speed = ETH_LINK_SPEED_100;
2132                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2133                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2134                 if (link.link_status == old.link_status)
2135                         return -1;
2136                 return 0;
2137         }
2138
2139         if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2140             !hw->mac.get_link_status) {
2141                 memcpy(&link, &old, sizeof(link));
2142                 return -1;
2143         }
2144
2145         if (link_up == 0) {
2146                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2147                 if (link.link_status == old.link_status)
2148                         return -1;
2149                 return 0;
2150         }
2151         link.link_status = 1;
2152         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2153
2154         switch (link_speed) {
2155         default:
2156         case IXGBE_LINK_SPEED_UNKNOWN:
2157                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2158                 link.link_speed = ETH_LINK_SPEED_100;
2159                 break;
2160
2161         case IXGBE_LINK_SPEED_100_FULL:
2162                 link.link_speed = ETH_LINK_SPEED_100;
2163                 break;
2164
2165         case IXGBE_LINK_SPEED_1GB_FULL:
2166                 link.link_speed = ETH_LINK_SPEED_1000;
2167                 break;
2168
2169         case IXGBE_LINK_SPEED_10GB_FULL:
2170                 link.link_speed = ETH_LINK_SPEED_10000;
2171                 break;
2172         }
2173         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2174
2175         if (link.link_status == old.link_status)
2176                 return -1;
2177
2178         return 0;
2179 }
2180
2181 static void
2182 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2183 {
2184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185         uint32_t fctrl;
2186
2187         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2188         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2189         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2190 }
2191
2192 static void
2193 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2194 {
2195         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196         uint32_t fctrl;
2197
2198         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2199         fctrl &= (~IXGBE_FCTRL_UPE);
2200         if (dev->data->all_multicast == 1)
2201                 fctrl |= IXGBE_FCTRL_MPE;
2202         else
2203                 fctrl &= (~IXGBE_FCTRL_MPE);
2204         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2205 }
2206
2207 static void
2208 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2209 {
2210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211         uint32_t fctrl;
2212
2213         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2214         fctrl |= IXGBE_FCTRL_MPE;
2215         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2216 }
2217
2218 static void
2219 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2220 {
2221         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2222         uint32_t fctrl;
2223
2224         if (dev->data->promiscuous == 1)
2225                 return; /* must remain in all_multicast mode */
2226
2227         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2228         fctrl &= (~IXGBE_FCTRL_MPE);
2229         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2230 }
2231
2232 /**
2233  * It clears the interrupt causes and enables the interrupt.
2234  * It will be called once only during nic initialized.
2235  *
2236  * @param dev
2237  *  Pointer to struct rte_eth_dev.
2238  *
2239  * @return
2240  *  - On success, zero.
2241  *  - On failure, a negative value.
2242  */
2243 static int
2244 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2245 {
2246         struct ixgbe_interrupt *intr =
2247                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2248
2249         ixgbe_dev_link_status_print(dev);
2250         intr->mask |= IXGBE_EICR_LSC;
2251
2252         return 0;
2253 }
2254
2255 /*
2256  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2257  *
2258  * @param dev
2259  *  Pointer to struct rte_eth_dev.
2260  *
2261  * @return
2262  *  - On success, zero.
2263  *  - On failure, a negative value.
2264  */
2265 static int
2266 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2267 {
2268         uint32_t eicr;
2269         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2270         struct ixgbe_interrupt *intr =
2271                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2272
2273         /* clear all cause mask */
2274         ixgbe_disable_intr(hw);
2275
2276         /* read-on-clear nic registers here */
2277         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2278         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2279
2280         intr->flags = 0;
2281         if (eicr & IXGBE_EICR_LSC) {
2282                 /* set flag for async link update */
2283                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2284         }
2285
2286         if (eicr & IXGBE_EICR_MAILBOX)
2287                 intr->flags |= IXGBE_FLAG_MAILBOX;
2288
2289         return 0;
2290 }
2291
2292 /**
2293  * It gets and then prints the link status.
2294  *
2295  * @param dev
2296  *  Pointer to struct rte_eth_dev.
2297  *
2298  * @return
2299  *  - On success, zero.
2300  *  - On failure, a negative value.
2301  */
2302 static void
2303 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2304 {
2305         struct rte_eth_link link;
2306
2307         memset(&link, 0, sizeof(link));
2308         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2309         if (link.link_status) {
2310                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2311                                         (int)(dev->data->port_id),
2312                                         (unsigned)link.link_speed,
2313                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2314                                         "full-duplex" : "half-duplex");
2315         } else {
2316                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2317                                 (int)(dev->data->port_id));
2318         }
2319         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2320                                 dev->pci_dev->addr.domain,
2321                                 dev->pci_dev->addr.bus,
2322                                 dev->pci_dev->addr.devid,
2323                                 dev->pci_dev->addr.function);
2324 }
2325
2326 /*
2327  * It executes link_update after knowing an interrupt occurred.
2328  *
2329  * @param dev
2330  *  Pointer to struct rte_eth_dev.
2331  *
2332  * @return
2333  *  - On success, zero.
2334  *  - On failure, a negative value.
2335  */
2336 static int
2337 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2338 {
2339         struct ixgbe_interrupt *intr =
2340                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2341         int64_t timeout;
2342         struct rte_eth_link link;
2343         int intr_enable_delay = false;
2344
2345         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2346
2347         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2348                 ixgbe_pf_mbx_process(dev);
2349                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2350         }
2351
2352         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2353                 /* get the link status before link update, for predicting later */
2354                 memset(&link, 0, sizeof(link));
2355                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2356
2357                 ixgbe_dev_link_update(dev, 0);
2358
2359                 /* likely to up */
2360                 if (!link.link_status)
2361                         /* handle it 1 sec later, wait it being stable */
2362                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2363                 /* likely to down */
2364                 else
2365                         /* handle it 4 sec later, wait it being stable */
2366                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2367
2368                 ixgbe_dev_link_status_print(dev);
2369
2370                 intr_enable_delay = true;
2371         }
2372
2373         if (intr_enable_delay) {
2374                 if (rte_eal_alarm_set(timeout * 1000,
2375                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2376                         PMD_DRV_LOG(ERR, "Error setting alarm");
2377         } else {
2378                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2379                 ixgbe_enable_intr(dev);
2380                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2381         }
2382
2383
2384         return 0;
2385 }
2386
2387 /**
2388  * Interrupt handler which shall be registered for alarm callback for delayed
2389  * handling specific interrupt to wait for the stable nic state. As the
2390  * NIC interrupt state is not stable for ixgbe after link is just down,
2391  * it needs to wait 4 seconds to get the stable status.
2392  *
2393  * @param handle
2394  *  Pointer to interrupt handle.
2395  * @param param
2396  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2397  *
2398  * @return
2399  *  void
2400  */
2401 static void
2402 ixgbe_dev_interrupt_delayed_handler(void *param)
2403 {
2404         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2405         struct ixgbe_interrupt *intr =
2406                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2407         struct ixgbe_hw *hw =
2408                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409         uint32_t eicr;
2410
2411         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2412         if (eicr & IXGBE_EICR_MAILBOX)
2413                 ixgbe_pf_mbx_process(dev);
2414
2415         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2416                 ixgbe_dev_link_update(dev, 0);
2417                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2418                 ixgbe_dev_link_status_print(dev);
2419                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2420         }
2421
2422         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2423         ixgbe_enable_intr(dev);
2424         rte_intr_enable(&(dev->pci_dev->intr_handle));
2425 }
2426
2427 /**
2428  * Interrupt handler triggered by NIC  for handling
2429  * specific interrupt.
2430  *
2431  * @param handle
2432  *  Pointer to interrupt handle.
2433  * @param param
2434  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2435  *
2436  * @return
2437  *  void
2438  */
2439 static void
2440 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2441                                                         void *param)
2442 {
2443         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2444         ixgbe_dev_interrupt_get_status(dev);
2445         ixgbe_dev_interrupt_action(dev);
2446 }
2447
2448 static int
2449 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2450 {
2451         struct ixgbe_hw *hw;
2452
2453         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2454         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2455 }
2456
2457 static int
2458 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2459 {
2460         struct ixgbe_hw *hw;
2461
2462         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2463         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2464 }
2465
2466 static int
2467 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2468 {
2469         struct ixgbe_hw *hw;
2470         uint32_t mflcn_reg;
2471         uint32_t fccfg_reg;
2472         int rx_pause;
2473         int tx_pause;
2474
2475         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476
2477         fc_conf->pause_time = hw->fc.pause_time;
2478         fc_conf->high_water = hw->fc.high_water[0];
2479         fc_conf->low_water = hw->fc.low_water[0];
2480         fc_conf->send_xon = hw->fc.send_xon;
2481         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2482
2483         /*
2484          * Return rx_pause status according to actual setting of
2485          * MFLCN register.
2486          */
2487         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2488         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2489                 rx_pause = 1;
2490         else
2491                 rx_pause = 0;
2492
2493         /*
2494          * Return tx_pause status according to actual setting of
2495          * FCCFG register.
2496          */
2497         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2498         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2499                 tx_pause = 1;
2500         else
2501                 tx_pause = 0;
2502
2503         if (rx_pause && tx_pause)
2504                 fc_conf->mode = RTE_FC_FULL;
2505         else if (rx_pause)
2506                 fc_conf->mode = RTE_FC_RX_PAUSE;
2507         else if (tx_pause)
2508                 fc_conf->mode = RTE_FC_TX_PAUSE;
2509         else
2510                 fc_conf->mode = RTE_FC_NONE;
2511
2512         return 0;
2513 }
2514
2515 static int
2516 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2517 {
2518         struct ixgbe_hw *hw;
2519         int err;
2520         uint32_t rx_buf_size;
2521         uint32_t max_high_water;
2522         uint32_t mflcn;
2523         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2524                 ixgbe_fc_none,
2525                 ixgbe_fc_rx_pause,
2526                 ixgbe_fc_tx_pause,
2527                 ixgbe_fc_full
2528         };
2529
2530         PMD_INIT_FUNC_TRACE();
2531
2532         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2533         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2534                 return -ENOTSUP;
2535         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2536         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2537
2538         /*
2539          * At least reserve one Ethernet frame for watermark
2540          * high_water/low_water in kilo bytes for ixgbe
2541          */
2542         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2543         if ((fc_conf->high_water > max_high_water) ||
2544                 (fc_conf->high_water < fc_conf->low_water)) {
2545                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2546                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2547                 return (-EINVAL);
2548         }
2549
2550         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2551         hw->fc.pause_time     = fc_conf->pause_time;
2552         hw->fc.high_water[0]  = fc_conf->high_water;
2553         hw->fc.low_water[0]   = fc_conf->low_water;
2554         hw->fc.send_xon       = fc_conf->send_xon;
2555
2556         err = ixgbe_fc_enable(hw);
2557
2558         /* Not negotiated is not an error case */
2559         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2560
2561                 /* check if we want to forward MAC frames - driver doesn't have native
2562                  * capability to do that, so we'll write the registers ourselves */
2563
2564                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2565
2566                 /* set or clear MFLCN.PMCF bit depending on configuration */
2567                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2568                         mflcn |= IXGBE_MFLCN_PMCF;
2569                 else
2570                         mflcn &= ~IXGBE_MFLCN_PMCF;
2571
2572                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2573                 IXGBE_WRITE_FLUSH(hw);
2574
2575                 return 0;
2576         }
2577
2578         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2579         return -EIO;
2580 }
2581
2582 /**
2583  *  ixgbe_pfc_enable_generic - Enable flow control
2584  *  @hw: pointer to hardware structure
2585  *  @tc_num: traffic class number
2586  *  Enable flow control according to the current settings.
2587  */
2588 static int
2589 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2590 {
2591         int ret_val = 0;
2592         uint32_t mflcn_reg, fccfg_reg;
2593         uint32_t reg;
2594         uint32_t fcrtl, fcrth;
2595         uint8_t i;
2596         uint8_t nb_rx_en;
2597
2598         /* Validate the water mark configuration */
2599         if (!hw->fc.pause_time) {
2600                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2601                 goto out;
2602         }
2603
2604         /* Low water mark of zero causes XOFF floods */
2605         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2606                  /* High/Low water can not be 0 */
2607                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2608                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2609                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2610                         goto out;
2611                 }
2612
2613                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2614                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2615                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2616                         goto out;
2617                 }
2618         }
2619         /* Negotiate the fc mode to use */
2620         ixgbe_fc_autoneg(hw);
2621
2622         /* Disable any previous flow control settings */
2623         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2624         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2625
2626         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2627         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2628
2629         switch (hw->fc.current_mode) {
2630         case ixgbe_fc_none:
2631                 /*
2632                  * If the count of enabled RX Priority Flow control >1,
2633                  * and the TX pause can not be disabled
2634                  */
2635                 nb_rx_en = 0;
2636                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2637                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2638                         if (reg & IXGBE_FCRTH_FCEN)
2639                                 nb_rx_en++;
2640                 }
2641                 if (nb_rx_en > 1)
2642                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2643                 break;
2644         case ixgbe_fc_rx_pause:
2645                 /*
2646                  * Rx Flow control is enabled and Tx Flow control is
2647                  * disabled by software override. Since there really
2648                  * isn't a way to advertise that we are capable of RX
2649                  * Pause ONLY, we will advertise that we support both
2650                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2651                  * disable the adapter's ability to send PAUSE frames.
2652                  */
2653                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2654                 /*
2655                  * If the count of enabled RX Priority Flow control >1,
2656                  * and the TX pause can not be disabled
2657                  */
2658                 nb_rx_en = 0;
2659                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2660                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2661                         if (reg & IXGBE_FCRTH_FCEN)
2662                                 nb_rx_en++;
2663                 }
2664                 if (nb_rx_en > 1)
2665                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2666                 break;
2667         case ixgbe_fc_tx_pause:
2668                 /*
2669                  * Tx Flow control is enabled, and Rx Flow control is
2670                  * disabled by software override.
2671                  */
2672                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2673                 break;
2674         case ixgbe_fc_full:
2675                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2676                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2677                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2678                 break;
2679         default:
2680                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2681                 ret_val = IXGBE_ERR_CONFIG;
2682                 goto out;
2683                 break;
2684         }
2685
2686         /* Set 802.3x based flow control settings. */
2687         mflcn_reg |= IXGBE_MFLCN_DPF;
2688         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2689         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2690
2691         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2692         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2693                 hw->fc.high_water[tc_num]) {
2694                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2695                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2696                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2697         } else {
2698                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2699                 /*
2700                  * In order to prevent Tx hangs when the internal Tx
2701                  * switch is enabled we must set the high water mark
2702                  * to the maximum FCRTH value.  This allows the Tx
2703                  * switch to function even under heavy Rx workloads.
2704                  */
2705                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2706         }
2707         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2708
2709         /* Configure pause time (2 TCs per register) */
2710         reg = hw->fc.pause_time * 0x00010001;
2711         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2712                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2713
2714         /* Configure flow control refresh threshold value */
2715         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2716
2717 out:
2718         return ret_val;
2719 }
2720
2721 static int
2722 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2723 {
2724         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2725         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2726
2727         if(hw->mac.type != ixgbe_mac_82598EB) {
2728                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2729         }
2730         return ret_val;
2731 }
2732
2733 static int
2734 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2735 {
2736         int err;
2737         uint32_t rx_buf_size;
2738         uint32_t max_high_water;
2739         uint8_t tc_num;
2740         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2741         struct ixgbe_hw *hw =
2742                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743         struct ixgbe_dcb_config *dcb_config =
2744                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2745
2746         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2747                 ixgbe_fc_none,
2748                 ixgbe_fc_rx_pause,
2749                 ixgbe_fc_tx_pause,
2750                 ixgbe_fc_full
2751         };
2752
2753         PMD_INIT_FUNC_TRACE();
2754
2755         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2756         tc_num = map[pfc_conf->priority];
2757         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2758         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2759         /*
2760          * At least reserve one Ethernet frame for watermark
2761          * high_water/low_water in kilo bytes for ixgbe
2762          */
2763         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2764         if ((pfc_conf->fc.high_water > max_high_water) ||
2765             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2766                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2767                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2768                 return (-EINVAL);
2769         }
2770
2771         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2772         hw->fc.pause_time = pfc_conf->fc.pause_time;
2773         hw->fc.send_xon = pfc_conf->fc.send_xon;
2774         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2775         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2776
2777         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2778
2779         /* Not negotiated is not an error case */
2780         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2781                 return 0;
2782
2783         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2784         return -EIO;
2785 }
2786
2787 static int
2788 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2789                           struct rte_eth_rss_reta_entry64 *reta_conf,
2790                           uint16_t reta_size)
2791 {
2792         uint8_t i, j, mask;
2793         uint32_t reta, r;
2794         uint16_t idx, shift;
2795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2796
2797         PMD_INIT_FUNC_TRACE();
2798         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2799                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2800                         "(%d) doesn't match the number hardware can supported "
2801                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2802                 return -EINVAL;
2803         }
2804
2805         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2806                 idx = i / RTE_RETA_GROUP_SIZE;
2807                 shift = i % RTE_RETA_GROUP_SIZE;
2808                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2809                                                 IXGBE_4_BIT_MASK);
2810                 if (!mask)
2811                         continue;
2812                 if (mask == IXGBE_4_BIT_MASK)
2813                         r = 0;
2814                 else
2815                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2816                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2817                         if (mask & (0x1 << j))
2818                                 reta |= reta_conf[idx].reta[shift + j] <<
2819                                                         (CHAR_BIT * j);
2820                         else
2821                                 reta |= r & (IXGBE_8_BIT_MASK <<
2822                                                 (CHAR_BIT * j));
2823                 }
2824                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2825         }
2826
2827         return 0;
2828 }
2829
2830 static int
2831 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2832                          struct rte_eth_rss_reta_entry64 *reta_conf,
2833                          uint16_t reta_size)
2834 {
2835         uint8_t i, j, mask;
2836         uint32_t reta;
2837         uint16_t idx, shift;
2838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839
2840         PMD_INIT_FUNC_TRACE();
2841         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2842                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2843                         "(%d) doesn't match the number hardware can supported "
2844                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2845                 return -EINVAL;
2846         }
2847
2848         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2849                 idx = i / RTE_RETA_GROUP_SIZE;
2850                 shift = i % RTE_RETA_GROUP_SIZE;
2851                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2852                                                 IXGBE_4_BIT_MASK);
2853                 if (!mask)
2854                         continue;
2855
2856                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2857                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2858                         if (mask & (0x1 << j))
2859                                 reta_conf[idx].reta[shift + j] =
2860                                         ((reta >> (CHAR_BIT * j)) &
2861                                                 IXGBE_8_BIT_MASK);
2862                 }
2863         }
2864
2865         return 0;
2866 }
2867
2868 static void
2869 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2870                                 uint32_t index, uint32_t pool)
2871 {
2872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873         uint32_t enable_addr = 1;
2874
2875         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2876 }
2877
2878 static void
2879 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2880 {
2881         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2882
2883         ixgbe_clear_rar(hw, index);
2884 }
2885
2886 static int
2887 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2888 {
2889         uint32_t hlreg0;
2890         uint32_t maxfrs;
2891         struct ixgbe_hw *hw;
2892         struct rte_eth_dev_info dev_info;
2893         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2894
2895         ixgbe_dev_info_get(dev, &dev_info);
2896
2897         /* check that mtu is within the allowed range */
2898         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2899                 return -EINVAL;
2900
2901         /* refuse mtu that requires the support of scattered packets when this
2902          * feature has not been enabled before. */
2903         if (!dev->data->scattered_rx &&
2904             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2905              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2906                 return -EINVAL;
2907
2908         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2909         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2910
2911         /* switch to jumbo mode if needed */
2912         if (frame_size > ETHER_MAX_LEN) {
2913                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2914                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2915         } else {
2916                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2917                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2918         }
2919         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2920
2921         /* update max frame size */
2922         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2923
2924         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2925         maxfrs &= 0x0000FFFF;
2926         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2927         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2928
2929         return 0;
2930 }
2931
2932 /*
2933  * Virtual Function operations
2934  */
2935 static void
2936 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2937 {
2938         PMD_INIT_FUNC_TRACE();
2939
2940         /* Clear interrupt mask to stop from interrupts being generated */
2941         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2942
2943         IXGBE_WRITE_FLUSH(hw);
2944 }
2945
2946 static int
2947 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2948 {
2949         struct rte_eth_conf* conf = &dev->data->dev_conf;
2950
2951         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2952                      dev->data->port_id);
2953
2954         /*
2955          * VF has no ability to enable/disable HW CRC
2956          * Keep the persistent behavior the same as Host PF
2957          */
2958 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2959         if (!conf->rxmode.hw_strip_crc) {
2960                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2961                 conf->rxmode.hw_strip_crc = 1;
2962         }
2963 #else
2964         if (conf->rxmode.hw_strip_crc) {
2965                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2966                 conf->rxmode.hw_strip_crc = 0;
2967         }
2968 #endif
2969
2970         return 0;
2971 }
2972
2973 static int
2974 ixgbevf_dev_start(struct rte_eth_dev *dev)
2975 {
2976         struct ixgbe_hw *hw =
2977                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2978         int err, mask = 0;
2979
2980         PMD_INIT_FUNC_TRACE();
2981
2982         hw->mac.ops.reset_hw(hw);
2983         hw->mac.get_link_status = true;
2984
2985         /* negotiate mailbox API version to use with the PF. */
2986         ixgbevf_negotiate_api(hw);
2987
2988         ixgbevf_dev_tx_init(dev);
2989
2990         /* This can fail when allocating mbufs for descriptor rings */
2991         err = ixgbevf_dev_rx_init(dev);
2992         if (err) {
2993                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2994                 ixgbe_dev_clear_queues(dev);
2995                 return err;
2996         }
2997
2998         /* Set vfta */
2999         ixgbevf_set_vfta_all(dev,1);
3000
3001         /* Set HW strip */
3002         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3003                 ETH_VLAN_EXTEND_MASK;
3004         ixgbevf_vlan_offload_set(dev, mask);
3005
3006         ixgbevf_dev_rxtx_start(dev);
3007
3008         return 0;
3009 }
3010
3011 static void
3012 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3013 {
3014         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015
3016         PMD_INIT_FUNC_TRACE();
3017
3018         hw->adapter_stopped = TRUE;
3019         ixgbe_stop_adapter(hw);
3020
3021         /*
3022           * Clear what we set, but we still keep shadow_vfta to
3023           * restore after device starts
3024           */
3025         ixgbevf_set_vfta_all(dev,0);
3026
3027         /* Clear stored conf */
3028         dev->data->scattered_rx = 0;
3029
3030         ixgbe_dev_clear_queues(dev);
3031 }
3032
3033 static void
3034 ixgbevf_dev_close(struct rte_eth_dev *dev)
3035 {
3036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3037
3038         PMD_INIT_FUNC_TRACE();
3039
3040         ixgbe_reset_hw(hw);
3041
3042         ixgbevf_dev_stop(dev);
3043
3044         /* reprogram the RAR[0] in case user changed it. */
3045         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3046 }
3047
3048 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3049 {
3050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3051         struct ixgbe_vfta * shadow_vfta =
3052                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3053         int i = 0, j = 0, vfta = 0, mask = 1;
3054
3055         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3056                 vfta = shadow_vfta->vfta[i];
3057                 if(vfta){
3058                         mask = 1;
3059                         for (j = 0; j < 32; j++){
3060                                 if(vfta & mask)
3061                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3062                                 mask<<=1;
3063                         }
3064                 }
3065         }
3066
3067 }
3068
3069 static int
3070 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3071 {
3072         struct ixgbe_hw *hw =
3073                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074         struct ixgbe_vfta * shadow_vfta =
3075                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3076         uint32_t vid_idx = 0;
3077         uint32_t vid_bit = 0;
3078         int ret = 0;
3079
3080         PMD_INIT_FUNC_TRACE();
3081
3082         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3083         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3084         if(ret){
3085                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3086                 return ret;
3087         }
3088         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3089         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3090
3091         /* Save what we set and retore it after device reset */
3092         if (on)
3093                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3094         else
3095                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3096
3097         return 0;
3098 }
3099
3100 static void
3101 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3102 {
3103         struct ixgbe_hw *hw =
3104                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3105         uint32_t ctrl;
3106
3107         PMD_INIT_FUNC_TRACE();
3108
3109         if(queue >= hw->mac.max_rx_queues)
3110                 return;
3111
3112         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3113         if(on)
3114                 ctrl |= IXGBE_RXDCTL_VME;
3115         else
3116                 ctrl &= ~IXGBE_RXDCTL_VME;
3117         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3118
3119         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3120 }
3121
3122 static void
3123 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3124 {
3125         struct ixgbe_hw *hw =
3126                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3127         uint16_t i;
3128         int on = 0;
3129
3130         /* VF function only support hw strip feature, others are not support */
3131         if(mask & ETH_VLAN_STRIP_MASK){
3132                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3133
3134                 for(i=0; i < hw->mac.max_rx_queues; i++)
3135                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3136         }
3137 }
3138
3139 static int
3140 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3141 {
3142         uint32_t reg_val;
3143
3144         /* we only need to do this if VMDq is enabled */
3145         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3146         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3147                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3148                 return (-1);
3149         }
3150
3151         return 0;
3152 }
3153
3154 static uint32_t
3155 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3156 {
3157         uint32_t vector = 0;
3158         switch (hw->mac.mc_filter_type) {
3159         case 0:   /* use bits [47:36] of the address */
3160                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3161                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3162                 break;
3163         case 1:   /* use bits [46:35] of the address */
3164                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3165                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3166                 break;
3167         case 2:   /* use bits [45:34] of the address */
3168                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3169                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3170                 break;
3171         case 3:   /* use bits [43:32] of the address */
3172                 vector = ((uc_addr->addr_bytes[4]) |
3173                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3174                 break;
3175         default:  /* Invalid mc_filter_type */
3176                 break;
3177         }
3178
3179         /* vector can only be 12-bits or boundary will be exceeded */
3180         vector &= 0xFFF;
3181         return vector;
3182 }
3183
3184 static int
3185 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3186                                uint8_t on)
3187 {
3188         uint32_t vector;
3189         uint32_t uta_idx;
3190         uint32_t reg_val;
3191         uint32_t uta_shift;
3192         uint32_t rc;
3193         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3194         const uint32_t ixgbe_uta_bit_shift = 5;
3195         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3196         const uint32_t bit1 = 0x1;
3197
3198         struct ixgbe_hw *hw =
3199                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3200         struct ixgbe_uta_info *uta_info =
3201                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3202
3203         /* The UTA table only exists on 82599 hardware and newer */
3204         if (hw->mac.type < ixgbe_mac_82599EB)
3205                 return (-ENOTSUP);
3206
3207         vector = ixgbe_uta_vector(hw,mac_addr);
3208         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3209         uta_shift = vector & ixgbe_uta_bit_mask;
3210
3211         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3212         if(rc == on)
3213                 return 0;
3214
3215         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3216         if (on) {
3217                 uta_info->uta_in_use++;
3218                 reg_val |= (bit1 << uta_shift);
3219                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3220         } else {
3221                 uta_info->uta_in_use--;
3222                 reg_val &= ~(bit1 << uta_shift);
3223                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3224         }
3225
3226         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3227
3228         if (uta_info->uta_in_use > 0)
3229                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3230                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3231         else
3232                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3233
3234         return 0;
3235 }
3236
3237 static int
3238 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3239 {
3240         int i;
3241         struct ixgbe_hw *hw =
3242                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3243         struct ixgbe_uta_info *uta_info =
3244                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3245
3246         /* The UTA table only exists on 82599 hardware and newer */
3247         if (hw->mac.type < ixgbe_mac_82599EB)
3248                 return (-ENOTSUP);
3249
3250         if(on) {
3251                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3252                         uta_info->uta_shadow[i] = ~0;
3253                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3254                 }
3255         } else {
3256                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3257                         uta_info->uta_shadow[i] = 0;
3258                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3259                 }
3260         }
3261         return 0;
3262
3263 }
3264
3265 uint32_t
3266 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3267 {
3268         uint32_t new_val = orig_val;
3269
3270         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3271                 new_val |= IXGBE_VMOLR_AUPE;
3272         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3273                 new_val |= IXGBE_VMOLR_ROMPE;
3274         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3275                 new_val |= IXGBE_VMOLR_ROPE;
3276         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3277                 new_val |= IXGBE_VMOLR_BAM;
3278         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3279                 new_val |= IXGBE_VMOLR_MPE;
3280
3281         return new_val;
3282 }
3283
3284 static int
3285 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3286                                uint16_t rx_mask, uint8_t on)
3287 {
3288         int val = 0;
3289
3290         struct ixgbe_hw *hw =
3291                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3292         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3293
3294         if (hw->mac.type == ixgbe_mac_82598EB) {
3295                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3296                              " on 82599 hardware and newer");
3297                 return (-ENOTSUP);
3298         }
3299         if (ixgbe_vmdq_mode_check(hw) < 0)
3300                 return (-ENOTSUP);
3301
3302         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3303
3304         if (on)
3305                 vmolr |= val;
3306         else
3307                 vmolr &= ~val;
3308
3309         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3310
3311         return 0;
3312 }
3313
3314 static int
3315 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3316 {
3317         uint32_t reg,addr;
3318         uint32_t val;
3319         const uint8_t bit1 = 0x1;
3320
3321         struct ixgbe_hw *hw =
3322                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3323
3324         if (ixgbe_vmdq_mode_check(hw) < 0)
3325                 return (-ENOTSUP);
3326
3327         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3328         reg = IXGBE_READ_REG(hw, addr);
3329         val = bit1 << pool;
3330
3331         if (on)
3332                 reg |= val;
3333         else
3334                 reg &= ~val;
3335
3336         IXGBE_WRITE_REG(hw, addr,reg);
3337
3338         return 0;
3339 }
3340
3341 static int
3342 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3343 {
3344         uint32_t reg,addr;
3345         uint32_t val;
3346         const uint8_t bit1 = 0x1;
3347
3348         struct ixgbe_hw *hw =
3349                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3350
3351         if (ixgbe_vmdq_mode_check(hw) < 0)
3352                 return (-ENOTSUP);
3353
3354         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3355         reg = IXGBE_READ_REG(hw, addr);
3356         val = bit1 << pool;
3357
3358         if (on)
3359                 reg |= val;
3360         else
3361                 reg &= ~val;
3362
3363         IXGBE_WRITE_REG(hw, addr,reg);
3364
3365         return 0;
3366 }
3367
3368 static int
3369 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3370                         uint64_t pool_mask, uint8_t vlan_on)
3371 {
3372         int ret = 0;
3373         uint16_t pool_idx;
3374         struct ixgbe_hw *hw =
3375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3376
3377         if (ixgbe_vmdq_mode_check(hw) < 0)
3378                 return (-ENOTSUP);
3379         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3380                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3381                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3382                         if (ret < 0)
3383                                 return ret;
3384         }
3385
3386         return ret;
3387 }
3388
3389 static int
3390 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3391                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3392                         uint8_t rule_id, uint8_t on)
3393 {
3394         uint32_t mr_ctl,vlvf;
3395         uint32_t mp_lsb = 0;
3396         uint32_t mv_msb = 0;
3397         uint32_t mv_lsb = 0;
3398         uint32_t mp_msb = 0;
3399         uint8_t i = 0;
3400         int reg_index = 0;
3401         uint64_t vlan_mask = 0;
3402
3403         const uint8_t pool_mask_offset = 32;
3404         const uint8_t vlan_mask_offset = 32;
3405         const uint8_t dst_pool_offset = 8;
3406         const uint8_t rule_mr_offset  = 4;
3407         const uint8_t mirror_rule_mask= 0x0F;
3408
3409         struct ixgbe_mirror_info *mr_info =
3410                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3411         struct ixgbe_hw *hw =
3412                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3413
3414         if (ixgbe_vmdq_mode_check(hw) < 0)
3415                 return (-ENOTSUP);
3416
3417         /* Check if vlan mask is valid */
3418         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3419                 if (mirror_conf->vlan.vlan_mask == 0)
3420                         return (-EINVAL);
3421         }
3422
3423         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3424         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3425                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3426                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3427                                 /* search vlan id related pool vlan filter index */
3428                                 reg_index = ixgbe_find_vlvf_slot(hw,
3429                                                 mirror_conf->vlan.vlan_id[i]);
3430                                 if(reg_index < 0)
3431                                         return (-EINVAL);
3432                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3433                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3434                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3435                                                 == mirror_conf->vlan.vlan_id[i]))
3436                                         vlan_mask |= (1ULL << reg_index);
3437                                 else
3438                                         return (-EINVAL);
3439                         }
3440                 }
3441
3442                 if (on) {
3443                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3444                         mv_msb = vlan_mask >> vlan_mask_offset;
3445
3446                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3447                                                 mirror_conf->vlan.vlan_mask;
3448                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3449                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3450                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3451                                                 mirror_conf->vlan.vlan_id[i];
3452                         }
3453                 } else {
3454                         mv_lsb = 0;
3455                         mv_msb = 0;
3456                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3457                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3458                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3459                 }
3460         }
3461
3462         /*
3463          * if enable pool mirror, write related pool mask register,if disable
3464          * pool mirror, clear PFMRVM register
3465          */
3466         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3467                 if (on) {
3468                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3469                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3470                         mr_info->mr_conf[rule_id].pool_mask =
3471                                         mirror_conf->pool_mask;
3472
3473                 } else {
3474                         mp_lsb = 0;
3475                         mp_msb = 0;
3476                         mr_info->mr_conf[rule_id].pool_mask = 0;
3477                 }
3478         }
3479
3480         /* read  mirror control register and recalculate it */
3481         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3482
3483         if (on) {
3484                 mr_ctl |= mirror_conf->rule_type_mask;
3485                 mr_ctl &= mirror_rule_mask;
3486                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3487         } else
3488                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3489
3490         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3491         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3492
3493         /* write mirrror control  register */
3494         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3495
3496         /* write pool mirrror control  register */
3497         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3498                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3499                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3500                                 mp_msb);
3501         }
3502         /* write VLAN mirrror control  register */
3503         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3504                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3505                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3506                                 mv_msb);
3507         }
3508
3509         return 0;
3510 }
3511
3512 static int
3513 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3514 {
3515         int mr_ctl = 0;
3516         uint32_t lsb_val = 0;
3517         uint32_t msb_val = 0;
3518         const uint8_t rule_mr_offset = 4;
3519
3520         struct ixgbe_hw *hw =
3521                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3522         struct ixgbe_mirror_info *mr_info =
3523                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3524
3525         if (ixgbe_vmdq_mode_check(hw) < 0)
3526                 return (-ENOTSUP);
3527
3528         memset(&mr_info->mr_conf[rule_id], 0,
3529                 sizeof(struct rte_eth_vmdq_mirror_conf));
3530
3531         /* clear PFVMCTL register */
3532         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3533
3534         /* clear pool mask register */
3535         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3536         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3537
3538         /* clear vlan mask register */
3539         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3540         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3541
3542         return 0;
3543 }
3544
3545 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3546         uint16_t queue_idx, uint16_t tx_rate)
3547 {
3548         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549         uint32_t rf_dec, rf_int;
3550         uint32_t bcnrc_val;
3551         uint16_t link_speed = dev->data->dev_link.link_speed;
3552
3553         if (queue_idx >= hw->mac.max_tx_queues)
3554                 return -EINVAL;
3555
3556         if (tx_rate != 0) {
3557                 /* Calculate the rate factor values to set */
3558                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3559                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3560                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3561
3562                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3563                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3564                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3565                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3566         } else {
3567                 bcnrc_val = 0;
3568         }
3569
3570         /*
3571          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3572          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3573          * set as 0x4.
3574          */
3575         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3576                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3577                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3578                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3579                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3580         else
3581                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3582                         IXGBE_MMW_SIZE_DEFAULT);
3583
3584         /* Set RTTBCNRC of queue X */
3585         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3586         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3587         IXGBE_WRITE_FLUSH(hw);
3588
3589         return 0;
3590 }
3591
3592 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3593         uint16_t tx_rate, uint64_t q_msk)
3594 {
3595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3596         struct ixgbe_vf_info *vfinfo =
3597                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3598         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3599         uint32_t queue_stride =
3600                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3601         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3602         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3603         uint16_t total_rate = 0;
3604
3605         if (queue_end >= hw->mac.max_tx_queues)
3606                 return -EINVAL;
3607
3608         if (vfinfo != NULL) {
3609                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3610                         if (vf_idx == vf)
3611                                 continue;
3612                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3613                                 idx++)
3614                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3615                 }
3616         } else
3617                 return -EINVAL;
3618
3619         /* Store tx_rate for this vf. */
3620         for (idx = 0; idx < nb_q_per_pool; idx++) {
3621                 if (((uint64_t)0x1 << idx) & q_msk) {
3622                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3623                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3624                         total_rate += tx_rate;
3625                 }
3626         }
3627
3628         if (total_rate > dev->data->dev_link.link_speed) {
3629                 /*
3630                  * Reset stored TX rate of the VF if it causes exceed
3631                  * link speed.
3632                  */
3633                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3634                 return -EINVAL;
3635         }
3636
3637         /* Set RTTBCNRC of each queue/pool for vf X  */
3638         for (; queue_idx <= queue_end; queue_idx++) {
3639                 if (0x1 & q_msk)
3640                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3641                 q_msk = q_msk >> 1;
3642         }
3643
3644         return 0;
3645 }
3646
3647 static void
3648 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3649                      __attribute__((unused)) uint32_t index,
3650                      __attribute__((unused)) uint32_t pool)
3651 {
3652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3653         int diag;
3654
3655         /*
3656          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3657          * operation. Trap this case to avoid exhausting the [very limited]
3658          * set of PF resources used to store VF MAC addresses.
3659          */
3660         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3661                 return;
3662         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3663         if (diag == 0)
3664                 return;
3665         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3666 }
3667
3668 static void
3669 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3670 {
3671         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3672         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3673         struct ether_addr *mac_addr;
3674         uint32_t i;
3675         int diag;
3676
3677         /*
3678          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3679          * not support the deletion of a given MAC address.
3680          * Instead, it imposes to delete all MAC addresses, then to add again
3681          * all MAC addresses with the exception of the one to be deleted.
3682          */
3683         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3684
3685         /*
3686          * Add again all MAC addresses, with the exception of the deleted one
3687          * and of the permanent MAC address.
3688          */
3689         for (i = 0, mac_addr = dev->data->mac_addrs;
3690              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3691                 /* Skip the deleted MAC address */
3692                 if (i == index)
3693                         continue;
3694                 /* Skip NULL MAC addresses */
3695                 if (is_zero_ether_addr(mac_addr))
3696                         continue;
3697                 /* Skip the permanent MAC address */
3698                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3699                         continue;
3700                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3701                 if (diag != 0)
3702                         PMD_DRV_LOG(ERR,
3703                                     "Adding again MAC address "
3704                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3705                                     "diag=%d",
3706                                     mac_addr->addr_bytes[0],
3707                                     mac_addr->addr_bytes[1],
3708                                     mac_addr->addr_bytes[2],
3709                                     mac_addr->addr_bytes[3],
3710                                     mac_addr->addr_bytes[4],
3711                                     mac_addr->addr_bytes[5],
3712                                     diag);
3713         }
3714 }
3715
3716 #define MAC_TYPE_FILTER_SUP(type)    do {\
3717         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3718                 (type) != ixgbe_mac_X550)\
3719                 return -ENOTSUP;\
3720 } while (0)
3721
3722 static int
3723 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3724                         struct rte_eth_syn_filter *filter,
3725                         bool add)
3726 {
3727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3728         uint32_t synqf;
3729
3730         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3731                 return -EINVAL;
3732
3733         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3734
3735         if (add) {
3736                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3737                         return -EINVAL;
3738                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3739                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3740
3741                 if (filter->hig_pri)
3742                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
3743                 else
3744                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3745         } else {
3746                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3747                         return -ENOENT;
3748                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3749         }
3750         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3751         IXGBE_WRITE_FLUSH(hw);
3752         return 0;
3753 }
3754
3755 static int
3756 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3757                         struct rte_eth_syn_filter *filter)
3758 {
3759         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3760         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3761
3762         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3763                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3764                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3765                 return 0;
3766         }
3767         return -ENOENT;
3768 }
3769
3770 static int
3771 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3772                         enum rte_filter_op filter_op,
3773                         void *arg)
3774 {
3775         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3776         int ret;
3777
3778         MAC_TYPE_FILTER_SUP(hw->mac.type);
3779
3780         if (filter_op == RTE_ETH_FILTER_NOP)
3781                 return 0;
3782
3783         if (arg == NULL) {
3784                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3785                             filter_op);
3786                 return -EINVAL;
3787         }
3788
3789         switch (filter_op) {
3790         case RTE_ETH_FILTER_ADD:
3791                 ret = ixgbe_syn_filter_set(dev,
3792                                 (struct rte_eth_syn_filter *)arg,
3793                                 TRUE);
3794                 break;
3795         case RTE_ETH_FILTER_DELETE:
3796                 ret = ixgbe_syn_filter_set(dev,
3797                                 (struct rte_eth_syn_filter *)arg,
3798                                 FALSE);
3799                 break;
3800         case RTE_ETH_FILTER_GET:
3801                 ret = ixgbe_syn_filter_get(dev,
3802                                 (struct rte_eth_syn_filter *)arg);
3803                 break;
3804         default:
3805                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3806                 ret = -EINVAL;
3807                 break;
3808         }
3809
3810         return ret;
3811 }
3812
3813
3814 static inline enum ixgbe_5tuple_protocol
3815 convert_protocol_type(uint8_t protocol_value)
3816 {
3817         if (protocol_value == IPPROTO_TCP)
3818                 return IXGBE_FILTER_PROTOCOL_TCP;
3819         else if (protocol_value == IPPROTO_UDP)
3820                 return IXGBE_FILTER_PROTOCOL_UDP;
3821         else if (protocol_value == IPPROTO_SCTP)
3822                 return IXGBE_FILTER_PROTOCOL_SCTP;
3823         else
3824                 return IXGBE_FILTER_PROTOCOL_NONE;
3825 }
3826
3827 /*
3828  * add a 5tuple filter
3829  *
3830  * @param
3831  * dev: Pointer to struct rte_eth_dev.
3832  * index: the index the filter allocates.
3833  * filter: ponter to the filter that will be added.
3834  * rx_queue: the queue id the filter assigned to.
3835  *
3836  * @return
3837  *    - On success, zero.
3838  *    - On failure, a negative value.
3839  */
3840 static int
3841 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3842                         struct ixgbe_5tuple_filter *filter)
3843 {
3844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3845         struct ixgbe_filter_info *filter_info =
3846                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3847         int i, idx, shift;
3848         uint32_t ftqf, sdpqf;
3849         uint32_t l34timir = 0;
3850         uint8_t mask = 0xff;
3851
3852         /*
3853          * look for an unused 5tuple filter index,
3854          * and insert the filter to list.
3855          */
3856         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3857                 idx = i / (sizeof(uint32_t) * NBBY);
3858                 shift = i % (sizeof(uint32_t) * NBBY);
3859                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3860                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3861                         filter->index = i;
3862                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3863                                           filter,
3864                                           entries);
3865                         break;
3866                 }
3867         }
3868         if (i >= IXGBE_MAX_FTQF_FILTERS) {
3869                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3870                 return -ENOSYS;
3871         }
3872
3873         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3874                                 IXGBE_SDPQF_DSTPORT_SHIFT);
3875         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3876
3877         ftqf = (uint32_t)(filter->filter_info.proto &
3878                 IXGBE_FTQF_PROTOCOL_MASK);
3879         ftqf |= (uint32_t)((filter->filter_info.priority &
3880                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3881         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3882                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3883         if (filter->filter_info.dst_ip_mask == 0)
3884                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3885         if (filter->filter_info.src_port_mask == 0)
3886                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3887         if (filter->filter_info.dst_port_mask == 0)
3888                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3889         if (filter->filter_info.proto_mask == 0)
3890                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3891         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3892         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3893         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3894
3895         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
3896         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
3897         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
3898         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
3899
3900         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3901         l34timir |= (uint32_t)(filter->queue <<
3902                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3903         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3904         return 0;
3905 }
3906
3907 /*
3908  * remove a 5tuple filter
3909  *
3910  * @param
3911  * dev: Pointer to struct rte_eth_dev.
3912  * filter: the pointer of the filter will be removed.
3913  */
3914 static void
3915 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3916                         struct ixgbe_5tuple_filter *filter)
3917 {
3918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3919         struct ixgbe_filter_info *filter_info =
3920                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3921         uint16_t index = filter->index;
3922
3923         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3924                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3925         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3926         rte_free(filter);
3927
3928         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3929         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3930         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3931         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3932         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3933 }
3934
3935 static int
3936 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3937 {
3938         struct ixgbe_hw *hw;
3939         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3940
3941         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3942
3943         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3944                 return -EINVAL;
3945
3946         /* refuse mtu that requires the support of scattered packets when this
3947          * feature has not been enabled before. */
3948         if (!dev->data->scattered_rx &&
3949             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3950              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3951                 return -EINVAL;
3952
3953         /*
3954          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3955          * request of the version 2.0 of the mailbox API.
3956          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3957          * of the mailbox API.
3958          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3959          * prior to 3.11.33 which contains the following change:
3960          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3961          */
3962         ixgbevf_rlpml_set_vf(hw, max_frame);
3963
3964         /* update max frame size */
3965         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3966         return 0;
3967 }
3968
3969 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3970         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
3971                 return -ENOTSUP;\
3972 } while (0)
3973
3974 static inline struct ixgbe_5tuple_filter *
3975 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
3976                         struct ixgbe_5tuple_filter_info *key)
3977 {
3978         struct ixgbe_5tuple_filter *it;
3979
3980         TAILQ_FOREACH(it, filter_list, entries) {
3981                 if (memcmp(key, &it->filter_info,
3982                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
3983                         return it;
3984                 }
3985         }
3986         return NULL;
3987 }
3988
3989 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
3990 static inline int
3991 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3992                         struct ixgbe_5tuple_filter_info *filter_info)
3993 {
3994         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3995                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3996                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3997                 return -EINVAL;
3998
3999         switch (filter->dst_ip_mask) {
4000         case UINT32_MAX:
4001                 filter_info->dst_ip_mask = 0;
4002                 filter_info->dst_ip = filter->dst_ip;
4003                 break;
4004         case 0:
4005                 filter_info->dst_ip_mask = 1;
4006                 break;
4007         default:
4008                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4009                 return -EINVAL;
4010         }
4011
4012         switch (filter->src_ip_mask) {
4013         case UINT32_MAX:
4014                 filter_info->src_ip_mask = 0;
4015                 filter_info->src_ip = filter->src_ip;
4016                 break;
4017         case 0:
4018                 filter_info->src_ip_mask = 1;
4019                 break;
4020         default:
4021                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4022                 return -EINVAL;
4023         }
4024
4025         switch (filter->dst_port_mask) {
4026         case UINT16_MAX:
4027                 filter_info->dst_port_mask = 0;
4028                 filter_info->dst_port = filter->dst_port;
4029                 break;
4030         case 0:
4031                 filter_info->dst_port_mask = 1;
4032                 break;
4033         default:
4034                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4035                 return -EINVAL;
4036         }
4037
4038         switch (filter->src_port_mask) {
4039         case UINT16_MAX:
4040                 filter_info->src_port_mask = 0;
4041                 filter_info->src_port = filter->src_port;
4042                 break;
4043         case 0:
4044                 filter_info->src_port_mask = 1;
4045                 break;
4046         default:
4047                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4048                 return -EINVAL;
4049         }
4050
4051         switch (filter->proto_mask) {
4052         case UINT8_MAX:
4053                 filter_info->proto_mask = 0;
4054                 filter_info->proto =
4055                         convert_protocol_type(filter->proto);
4056                 break;
4057         case 0:
4058                 filter_info->proto_mask = 1;
4059                 break;
4060         default:
4061                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4062                 return -EINVAL;
4063         }
4064
4065         filter_info->priority = (uint8_t)filter->priority;
4066         return 0;
4067 }
4068
4069 /*
4070  * add or delete a ntuple filter
4071  *
4072  * @param
4073  * dev: Pointer to struct rte_eth_dev.
4074  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4075  * add: if true, add filter, if false, remove filter
4076  *
4077  * @return
4078  *    - On success, zero.
4079  *    - On failure, a negative value.
4080  */
4081 static int
4082 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4083                         struct rte_eth_ntuple_filter *ntuple_filter,
4084                         bool add)
4085 {
4086         struct ixgbe_filter_info *filter_info =
4087                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4088         struct ixgbe_5tuple_filter_info filter_5tuple;
4089         struct ixgbe_5tuple_filter *filter;
4090         int ret;
4091
4092         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4093                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4094                 return -EINVAL;
4095         }
4096
4097         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4098         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4099         if (ret < 0)
4100                 return ret;
4101
4102         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4103                                          &filter_5tuple);
4104         if (filter != NULL && add) {
4105                 PMD_DRV_LOG(ERR, "filter exists.");
4106                 return -EEXIST;
4107         }
4108         if (filter == NULL && !add) {
4109                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4110                 return -ENOENT;
4111         }
4112
4113         if (add) {
4114                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4115                                 sizeof(struct ixgbe_5tuple_filter), 0);
4116                 if (filter == NULL)
4117                         return -ENOMEM;
4118                 (void)rte_memcpy(&filter->filter_info,
4119                                  &filter_5tuple,
4120                                  sizeof(struct ixgbe_5tuple_filter_info));
4121                 filter->queue = ntuple_filter->queue;
4122                 ret = ixgbe_add_5tuple_filter(dev, filter);
4123                 if (ret < 0) {
4124                         rte_free(filter);
4125                         return ret;
4126                 }
4127         } else
4128                 ixgbe_remove_5tuple_filter(dev, filter);
4129
4130         return 0;
4131 }
4132
4133 /*
4134  * get a ntuple filter
4135  *
4136  * @param
4137  * dev: Pointer to struct rte_eth_dev.
4138  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4139  *
4140  * @return
4141  *    - On success, zero.
4142  *    - On failure, a negative value.
4143  */
4144 static int
4145 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4146                         struct rte_eth_ntuple_filter *ntuple_filter)
4147 {
4148         struct ixgbe_filter_info *filter_info =
4149                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4150         struct ixgbe_5tuple_filter_info filter_5tuple;
4151         struct ixgbe_5tuple_filter *filter;
4152         int ret;
4153
4154         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4155                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4156                 return -EINVAL;
4157         }
4158
4159         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4160         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4161         if (ret < 0)
4162                 return ret;
4163
4164         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4165                                          &filter_5tuple);
4166         if (filter == NULL) {
4167                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4168                 return -ENOENT;
4169         }
4170         ntuple_filter->queue = filter->queue;
4171         return 0;
4172 }
4173
4174 /*
4175  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4176  * @dev: pointer to rte_eth_dev structure
4177  * @filter_op:operation will be taken.
4178  * @arg: a pointer to specific structure corresponding to the filter_op
4179  *
4180  * @return
4181  *    - On success, zero.
4182  *    - On failure, a negative value.
4183  */
4184 static int
4185 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4186                                 enum rte_filter_op filter_op,
4187                                 void *arg)
4188 {
4189         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4190         int ret;
4191
4192         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4193
4194         if (filter_op == RTE_ETH_FILTER_NOP)
4195                 return 0;
4196
4197         if (arg == NULL) {
4198                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4199                             filter_op);
4200                 return -EINVAL;
4201         }
4202
4203         switch (filter_op) {
4204         case RTE_ETH_FILTER_ADD:
4205                 ret = ixgbe_add_del_ntuple_filter(dev,
4206                         (struct rte_eth_ntuple_filter *)arg,
4207                         TRUE);
4208                 break;
4209         case RTE_ETH_FILTER_DELETE:
4210                 ret = ixgbe_add_del_ntuple_filter(dev,
4211                         (struct rte_eth_ntuple_filter *)arg,
4212                         FALSE);
4213                 break;
4214         case RTE_ETH_FILTER_GET:
4215                 ret = ixgbe_get_ntuple_filter(dev,
4216                         (struct rte_eth_ntuple_filter *)arg);
4217                 break;
4218         default:
4219                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4220                 ret = -EINVAL;
4221                 break;
4222         }
4223         return ret;
4224 }
4225
4226 static inline int
4227 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4228                         uint16_t ethertype)
4229 {
4230         int i;
4231
4232         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4233                 if (filter_info->ethertype_filters[i] == ethertype &&
4234                     (filter_info->ethertype_mask & (1 << i)))
4235                         return i;
4236         }
4237         return -1;
4238 }
4239
4240 static inline int
4241 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4242                         uint16_t ethertype)
4243 {
4244         int i;
4245
4246         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4247                 if (!(filter_info->ethertype_mask & (1 << i))) {
4248                         filter_info->ethertype_mask |= 1 << i;
4249                         filter_info->ethertype_filters[i] = ethertype;
4250                         return i;
4251                 }
4252         }
4253         return -1;
4254 }
4255
4256 static inline int
4257 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4258                         uint8_t idx)
4259 {
4260         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4261                 return -1;
4262         filter_info->ethertype_mask &= ~(1 << idx);
4263         filter_info->ethertype_filters[idx] = 0;
4264         return idx;
4265 }
4266
4267 static int
4268 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4269                         struct rte_eth_ethertype_filter *filter,
4270                         bool add)
4271 {
4272         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4273         struct ixgbe_filter_info *filter_info =
4274                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4275         uint32_t etqf = 0;
4276         uint32_t etqs = 0;
4277         int ret;
4278
4279         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4280                 return -EINVAL;
4281
4282         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4283                 filter->ether_type == ETHER_TYPE_IPv6) {
4284                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4285                         " ethertype filter.", filter->ether_type);
4286                 return -EINVAL;
4287         }
4288
4289         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4290                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4291                 return -EINVAL;
4292         }
4293         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4294                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4295                 return -EINVAL;
4296         }
4297
4298         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4299         if (ret >= 0 && add) {
4300                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4301                             filter->ether_type);
4302                 return -EEXIST;
4303         }
4304         if (ret < 0 && !add) {
4305                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4306                             filter->ether_type);
4307                 return -ENOENT;
4308         }
4309
4310         if (add) {
4311                 ret = ixgbe_ethertype_filter_insert(filter_info,
4312                         filter->ether_type);
4313                 if (ret < 0) {
4314                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4315                         return -ENOSYS;
4316                 }
4317                 etqf = IXGBE_ETQF_FILTER_EN;
4318                 etqf |= (uint32_t)filter->ether_type;
4319                 etqs |= (uint32_t)((filter->queue <<
4320                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4321                                     IXGBE_ETQS_RX_QUEUE);
4322                 etqs |= IXGBE_ETQS_QUEUE_EN;
4323         } else {
4324                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4325                 if (ret < 0)
4326                         return -ENOSYS;
4327         }
4328         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4329         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4330         IXGBE_WRITE_FLUSH(hw);
4331
4332         return 0;
4333 }
4334
4335 static int
4336 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4337                         struct rte_eth_ethertype_filter *filter)
4338 {
4339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4340         struct ixgbe_filter_info *filter_info =
4341                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4342         uint32_t etqf, etqs;
4343         int ret;
4344
4345         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4346         if (ret < 0) {
4347                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4348                             filter->ether_type);
4349                 return -ENOENT;
4350         }
4351
4352         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4353         if (etqf & IXGBE_ETQF_FILTER_EN) {
4354                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4355                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4356                 filter->flags = 0;
4357                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4358                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4359                 return 0;
4360         }
4361         return -ENOENT;
4362 }
4363
4364 /*
4365  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4366  * @dev: pointer to rte_eth_dev structure
4367  * @filter_op:operation will be taken.
4368  * @arg: a pointer to specific structure corresponding to the filter_op
4369  */
4370 static int
4371 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4372                                 enum rte_filter_op filter_op,
4373                                 void *arg)
4374 {
4375         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4376         int ret;
4377
4378         MAC_TYPE_FILTER_SUP(hw->mac.type);
4379
4380         if (filter_op == RTE_ETH_FILTER_NOP)
4381                 return 0;
4382
4383         if (arg == NULL) {
4384                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4385                             filter_op);
4386                 return -EINVAL;
4387         }
4388
4389         switch (filter_op) {
4390         case RTE_ETH_FILTER_ADD:
4391                 ret = ixgbe_add_del_ethertype_filter(dev,
4392                         (struct rte_eth_ethertype_filter *)arg,
4393                         TRUE);
4394                 break;
4395         case RTE_ETH_FILTER_DELETE:
4396                 ret = ixgbe_add_del_ethertype_filter(dev,
4397                         (struct rte_eth_ethertype_filter *)arg,
4398                         FALSE);
4399                 break;
4400         case RTE_ETH_FILTER_GET:
4401                 ret = ixgbe_get_ethertype_filter(dev,
4402                         (struct rte_eth_ethertype_filter *)arg);
4403                 break;
4404         default:
4405                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4406                 ret = -EINVAL;
4407                 break;
4408         }
4409         return ret;
4410 }
4411
4412 static int
4413 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4414                      enum rte_filter_type filter_type,
4415                      enum rte_filter_op filter_op,
4416                      void *arg)
4417 {
4418         int ret = -EINVAL;
4419
4420         switch (filter_type) {
4421         case RTE_ETH_FILTER_NTUPLE:
4422                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4423                 break;
4424         case RTE_ETH_FILTER_ETHERTYPE:
4425                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4426                 break;
4427         case RTE_ETH_FILTER_SYN:
4428                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4429                 break;
4430         case RTE_ETH_FILTER_FDIR:
4431                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4432                 break;
4433         default:
4434                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4435                                                         filter_type);
4436                 break;
4437         }
4438
4439         return ret;
4440 }
4441
4442 static struct rte_driver rte_ixgbe_driver = {
4443         .type = PMD_PDEV,
4444         .init = rte_ixgbe_pmd_init,
4445 };
4446
4447 static struct rte_driver rte_ixgbevf_driver = {
4448         .type = PMD_PDEV,
4449         .init = rte_ixgbevf_pmd_init,
4450 };
4451
4452 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4453 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);