drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 enum ixgbevf_xcast_modes {
 158         IXGBEVF_XCAST_MODE_NONE = 0,
 159         IXGBEVF_XCAST_MODE_MULTI,
 160         IXGBEVF_XCAST_MODE_ALLMULTI,
 161 };
 162
 163 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 164 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 165
 166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 197                                  size_t fw_size);
 198 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 199                                struct rte_eth_dev_info *dev_info);
 200 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 201 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 202                                  struct rte_eth_dev_info *dev_info);
 203 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 204
 205 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 206                 uint16_t vlan_id, int on);
 207 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 208                                enum rte_vlan_type vlan_type,
 209                                uint16_t tpid_id);
 210 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 211                 uint16_t queue, bool on);
 212 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 213                 int on);
 214 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 215 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 216 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 218 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 219
 220 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 222 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 225                                struct rte_eth_fc_conf *fc_conf);
 226 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 227                 struct rte_eth_pfc_conf *pfc_conf);
 228 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 229                         struct rte_eth_rss_reta_entry64 *reta_conf,
 230                         uint16_t reta_size);
 231 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 232                         struct rte_eth_rss_reta_entry64 *reta_conf,
 233                         uint16_t reta_size);
 234 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 240                                       struct rte_intr_handle *handle);
 241 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 242                 void *param);
 243 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 244 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 245                 uint32_t index, uint32_t pool);
 246 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 247 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 248                                            struct ether_addr *mac_addr);
 249 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 250
 251 /* For Virtual Function support */
 252 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 253 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 254 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 256 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 257 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 258 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 259 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 260 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 261                 struct rte_eth_stats *stats);
 262 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 263 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 264                 uint16_t vlan_id, int on);
 265 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 266                 uint16_t queue, int on);
 267 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 268 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 269 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 270                                             uint16_t queue_id);
 271 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 272                                              uint16_t queue_id);
 273 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 274                                  uint8_t queue, uint8_t msix_vector);
 275 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 276 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 277 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 278
 279 /* For Eth VMDQ APIs support */
 280 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 281                 ether_addr * mac_addr, uint8_t on);
 282 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 284                 struct rte_eth_mirror_conf *mirror_conf,
 285                 uint8_t rule_id, uint8_t on);
 286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 287                 uint8_t rule_id);
 288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 289                                           uint16_t queue_id);
 290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 291                                            uint16_t queue_id);
 292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 293                                uint8_t queue, uint8_t msix_vector);
 294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 295
 296 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 297                 uint16_t queue_idx, uint16_t tx_rate);
 298
 299 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 300                                  struct ether_addr *mac_addr,
 301                                  uint32_t index, uint32_t pool);
 302 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 303 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 304                                              struct ether_addr *mac_addr);
 305 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 306                         struct rte_eth_syn_filter *filter,
 307                         bool add);
 308 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 309                         struct rte_eth_syn_filter *filter);
 310 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 311                         enum rte_filter_op filter_op,
 312                         void *arg);
 313 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 314                         struct ixgbe_5tuple_filter *filter);
 315 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 316                         struct ixgbe_5tuple_filter *filter);
 317 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 318                         struct rte_eth_ntuple_filter *filter,
 319                         bool add);
 320 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 324                         struct rte_eth_ntuple_filter *filter);
 325 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ethertype_filter *filter,
 327                         bool add);
 328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 332                         struct rte_eth_ethertype_filter *filter);
 333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 334                      enum rte_filter_type filter_type,
 335                      enum rte_filter_op filter_op,
 336                      void *arg);
 337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 338
 339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 340                                       struct ether_addr *mc_addr_set,
 341                                       uint32_t nb_mc_addr);
 342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 343                                    struct rte_eth_dcb_info *dcb_info);
 344
 345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 347                             struct rte_dev_reg_info *regs);
 348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353
 354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 356                                 struct rte_dev_reg_info *regs);
 357
 358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 361                                             struct timespec *timestamp,
 362                                             uint32_t flags);
 363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 364                                             struct timespec *timestamp);
 365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 367                                    struct timespec *timestamp);
 368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 369                                    const struct timespec *timestamp);
 370 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 371                                           void *param);
 372
 373 static int ixgbe_dev_l2_tunnel_eth_type_conf
 374         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 375 static int ixgbe_dev_l2_tunnel_offload_set
 376         (struct rte_eth_dev *dev,
 377          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 378          uint32_t mask,
 379          uint8_t en);
 380 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 381                                              enum rte_filter_op filter_op,
 382                                              void *arg);
 383
 384 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 385                                          struct rte_eth_udp_tunnel *udp_tunnel);
 386 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 387                                          struct rte_eth_udp_tunnel *udp_tunnel);
 388
 389 /*
 390  * Define VF Stats MACRO for Non "cleared on read" register
 391  */
 392 #define UPDATE_VF_STAT(reg, last, cur)                          \
 393 {                                                               \
 394         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 395         cur += (latest - last) & UINT_MAX;                      \
 396         last = latest;                                          \
 397 }
 398
 399 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 400 {                                                                \
 401         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 402         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 403         u64 latest = ((new_msb << 32) | new_lsb);                \
 404         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 405         last = latest;                                           \
 406 }
 407
 408 #define IXGBE_SET_HWSTRIP(h, q) do {\
 409                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 410                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 411                 (h)->bitmap[idx] |= 1 << bit;\
 412         } while (0)
 413
 414 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 415                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 416                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 417                 (h)->bitmap[idx] &= ~(1 << bit);\
 418         } while (0)
 419
 420 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 421                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 422                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 423                 (r) = (h)->bitmap[idx] >> bit & 1;\
 424         } while (0)
 425
 426 /*
 427  * The set of PCI devices this driver supports
 428  */
 429 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 483 #ifdef RTE_NIC_BYPASS
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 485 #endif
 486         { .vendor_id = 0, /* sentinel */ },
 487 };
 488
 489 /*
 490  * The set of PCI devices this driver supports (for 82599 VF)
 491  */
 492 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 503         { .vendor_id = 0, /* sentinel */ },
 504 };
 505
 506 static const struct rte_eth_desc_lim rx_desc_lim = {
 507         .nb_max = IXGBE_MAX_RING_DESC,
 508         .nb_min = IXGBE_MIN_RING_DESC,
 509         .nb_align = IXGBE_RXD_ALIGN,
 510 };
 511
 512 static const struct rte_eth_desc_lim tx_desc_lim = {
 513         .nb_max = IXGBE_MAX_RING_DESC,
 514         .nb_min = IXGBE_MIN_RING_DESC,
 515         .nb_align = IXGBE_TXD_ALIGN,
 516         .nb_seg_max = IXGBE_TX_MAX_SEG,
 517         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 518 };
 519
 520 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 521         .dev_configure        = ixgbe_dev_configure,
 522         .dev_start            = ixgbe_dev_start,
 523         .dev_stop             = ixgbe_dev_stop,
 524         .dev_set_link_up    = ixgbe_dev_set_link_up,
 525         .dev_set_link_down  = ixgbe_dev_set_link_down,
 526         .dev_close            = ixgbe_dev_close,
 527         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 528         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 529         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 530         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 531         .link_update          = ixgbe_dev_link_update,
 532         .stats_get            = ixgbe_dev_stats_get,
 533         .xstats_get           = ixgbe_dev_xstats_get,
 534         .stats_reset          = ixgbe_dev_stats_reset,
 535         .xstats_reset         = ixgbe_dev_xstats_reset,
 536         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 537         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 538         .fw_version_get       = ixgbe_fw_version_get,
 539         .dev_infos_get        = ixgbe_dev_info_get,
 540         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 541         .mtu_set              = ixgbe_dev_mtu_set,
 542         .vlan_filter_set      = ixgbe_vlan_filter_set,
 543         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 544         .vlan_offload_set     = ixgbe_vlan_offload_set,
 545         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 546         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 547         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 548         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 549         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 550         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 551         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 552         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 553         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 554         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 555         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 556         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 557         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 558         .dev_led_on           = ixgbe_dev_led_on,
 559         .dev_led_off          = ixgbe_dev_led_off,
 560         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 561         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 562         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 563         .mac_addr_add         = ixgbe_add_rar,
 564         .mac_addr_remove      = ixgbe_remove_rar,
 565         .mac_addr_set         = ixgbe_set_default_mac_addr,
 566         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 567         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 568         .mirror_rule_set      = ixgbe_mirror_rule_set,
 569         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 570         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 571         .reta_update          = ixgbe_dev_rss_reta_update,
 572         .reta_query           = ixgbe_dev_rss_reta_query,
 573 #ifdef RTE_NIC_BYPASS
 574         .bypass_init          = ixgbe_bypass_init,
 575         .bypass_state_set     = ixgbe_bypass_state_store,
 576         .bypass_state_show    = ixgbe_bypass_state_show,
 577         .bypass_event_set     = ixgbe_bypass_event_store,
 578         .bypass_event_show    = ixgbe_bypass_event_show,
 579         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 580         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 581         .bypass_ver_show      = ixgbe_bypass_ver_show,
 582         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 583 #endif /* RTE_NIC_BYPASS */
 584         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 585         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 586         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 587         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 588         .rxq_info_get         = ixgbe_rxq_info_get,
 589         .txq_info_get         = ixgbe_txq_info_get,
 590         .timesync_enable      = ixgbe_timesync_enable,
 591         .timesync_disable     = ixgbe_timesync_disable,
 592         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 593         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 594         .get_reg              = ixgbe_get_regs,
 595         .get_eeprom_length    = ixgbe_get_eeprom_length,
 596         .get_eeprom           = ixgbe_get_eeprom,
 597         .set_eeprom           = ixgbe_set_eeprom,
 598         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 599         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 600         .timesync_read_time   = ixgbe_timesync_read_time,
 601         .timesync_write_time  = ixgbe_timesync_write_time,
 602         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 603         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 604         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 605         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 606 };
 607
 608 /*
 609  * dev_ops for virtual function, bare necessities for basic vf
 610  * operation have been implemented
 611  */
 612 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 613         .dev_configure        = ixgbevf_dev_configure,
 614         .dev_start            = ixgbevf_dev_start,
 615         .dev_stop             = ixgbevf_dev_stop,
 616         .link_update          = ixgbe_dev_link_update,
 617         .stats_get            = ixgbevf_dev_stats_get,
 618         .xstats_get           = ixgbevf_dev_xstats_get,
 619         .stats_reset          = ixgbevf_dev_stats_reset,
 620         .xstats_reset         = ixgbevf_dev_stats_reset,
 621         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 622         .dev_close            = ixgbevf_dev_close,
 623         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 624         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 625         .dev_infos_get        = ixgbevf_dev_info_get,
 626         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 627         .mtu_set              = ixgbevf_dev_set_mtu,
 628         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 629         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 630         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 631         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 632         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 633         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 634         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 635         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 636         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 637         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 638         .mac_addr_add         = ixgbevf_add_mac_addr,
 639         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 640         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 641         .rxq_info_get         = ixgbe_rxq_info_get,
 642         .txq_info_get         = ixgbe_txq_info_get,
 643         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 644         .get_reg              = ixgbevf_get_regs,
 645         .reta_update          = ixgbe_dev_rss_reta_update,
 646         .reta_query           = ixgbe_dev_rss_reta_query,
 647         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 648         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 649 };
 650
 651 /* store statistics names and its offset in stats structure */
 652 struct rte_ixgbe_xstats_name_off {
 653         char name[RTE_ETH_XSTATS_NAME_SIZE];
 654         unsigned offset;
 655 };
 656
 657 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 658         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 659         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 660         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 661         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 662         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 663         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 664         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 665         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 666         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 667         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 668         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 669         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 670         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 671         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 672         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 673                 prc1023)},
 674         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 675                 prc1522)},
 676         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 677         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 678         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 679         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 680         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 681         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 682         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 683         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 684         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 685         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 686         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 687         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 688         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 689         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 690         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 691         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 692         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 693                 ptc1023)},
 694         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 695                 ptc1522)},
 696         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 697         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 698         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 699         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 700
 701         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 702                 fdirustat_add)},
 703         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 704                 fdirustat_remove)},
 705         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 706                 fdirfstat_fadd)},
 707         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 708                 fdirfstat_fremove)},
 709         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 710                 fdirmatch)},
 711         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 712                 fdirmiss)},
 713
 714         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 715         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 716         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 717                 fclast)},
 718         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 719         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 720         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 721         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 722         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 723                 fcoe_noddp)},
 724         {"rx_fcoe_no_direct_data_placement_ext_buff",
 725                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 726
 727         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 728                 lxontxc)},
 729         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 730                 lxonrxc)},
 731         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 732                 lxofftxc)},
 733         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 734                 lxoffrxc)},
 735         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 736 };
 737
 738 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 739                            sizeof(rte_ixgbe_stats_strings[0]))
 740
 741 /* MACsec statistics */
 742 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 743         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 744                 out_pkts_untagged)},
 745         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 746                 out_pkts_encrypted)},
 747         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 748                 out_pkts_protected)},
 749         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 750                 out_octets_encrypted)},
 751         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 752                 out_octets_protected)},
 753         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_untagged)},
 755         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_badtag)},
 757         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_nosci)},
 759         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_unknownsci)},
 761         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 762                 in_octets_decrypted)},
 763         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 764                 in_octets_validated)},
 765         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_unchecked)},
 767         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_delayed)},
 769         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_late)},
 771         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_ok)},
 773         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_invalid)},
 775         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_notvalid)},
 777         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_unusedsa)},
 779         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_notusingsa)},
 781 };
 782
 783 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 784                            sizeof(rte_ixgbe_macsec_strings[0]))
 785
 786 /* Per-queue statistics */
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 788         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 789         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 790         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 791         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 792 };
 793
 794 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 795                            sizeof(rte_ixgbe_rxq_strings[0]))
 796 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 797
 798 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 799         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 800         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 801         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 802                 pxon2offc)},
 803 };
 804
 805 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 806                            sizeof(rte_ixgbe_txq_strings[0]))
 807 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 808
 809 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 810         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 811 };
 812
 813 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 814                 sizeof(rte_ixgbevf_stats_strings[0]))
 815
 816 /**
 817  * Atomically reads the link status information from global
 818  * structure rte_eth_dev.
 819  *
 820  * @param dev
 821  *   - Pointer to the structure rte_eth_dev to read from.
 822  *   - Pointer to the buffer to be saved with the link status.
 823  *
 824  * @return
 825  *   - On success, zero.
 826  *   - On failure, negative value.
 827  */
 828 static inline int
 829 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 830                                 struct rte_eth_link *link)
 831 {
 832         struct rte_eth_link *dst = link;
 833         struct rte_eth_link *src = &(dev->data->dev_link);
 834
 835         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 836                                         *(uint64_t *)src) == 0)
 837                 return -1;
 838
 839         return 0;
 840 }
 841
 842 /**
 843  * Atomically writes the link status information into global
 844  * structure rte_eth_dev.
 845  *
 846  * @param dev
 847  *   - Pointer to the structure rte_eth_dev to read from.
 848  *   - Pointer to the buffer to be saved with the link status.
 849  *
 850  * @return
 851  *   - On success, zero.
 852  *   - On failure, negative value.
 853  */
 854 static inline int
 855 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 856                                 struct rte_eth_link *link)
 857 {
 858         struct rte_eth_link *dst = &(dev->data->dev_link);
 859         struct rte_eth_link *src = link;
 860
 861         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 862                                         *(uint64_t *)src) == 0)
 863                 return -1;
 864
 865         return 0;
 866 }
 867
 868 /*
 869  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 870  */
 871 static inline int
 872 ixgbe_is_sfp(struct ixgbe_hw *hw)
 873 {
 874         switch (hw->phy.type) {
 875         case ixgbe_phy_sfp_avago:
 876         case ixgbe_phy_sfp_ftl:
 877         case ixgbe_phy_sfp_intel:
 878         case ixgbe_phy_sfp_unknown:
 879         case ixgbe_phy_sfp_passive_tyco:
 880         case ixgbe_phy_sfp_passive_unknown:
 881                 return 1;
 882         default:
 883                 return 0;
 884         }
 885 }
 886
 887 static inline int32_t
 888 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 889 {
 890         uint32_t ctrl_ext;
 891         int32_t status;
 892
 893         status = ixgbe_reset_hw(hw);
 894
 895         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 896         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 897         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 898         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 899         IXGBE_WRITE_FLUSH(hw);
 900
 901         return status;
 902 }
 903
 904 static inline void
 905 ixgbe_enable_intr(struct rte_eth_dev *dev)
 906 {
 907         struct ixgbe_interrupt *intr =
 908                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 909         struct ixgbe_hw *hw =
 910                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 911
 912         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 913         IXGBE_WRITE_FLUSH(hw);
 914 }
 915
 916 /*
 917  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 918  */
 919 static void
 920 ixgbe_disable_intr(struct ixgbe_hw *hw)
 921 {
 922         PMD_INIT_FUNC_TRACE();
 923
 924         if (hw->mac.type == ixgbe_mac_82598EB) {
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 926         } else {
 927                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 928                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 930         }
 931         IXGBE_WRITE_FLUSH(hw);
 932 }
 933
 934 /*
 935  * This function resets queue statistics mapping registers.
 936  * From Niantic datasheet, Initialization of Statistics section:
 937  * "...if software requires the queue counters, the RQSMR and TQSM registers
 938  * must be re-programmed following a device reset.
 939  */
 940 static void
 941 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 942 {
 943         uint32_t i;
 944
 945         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 946                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 947                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 948         }
 949 }
 950
 951
 952 static int
 953 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 954                                   uint16_t queue_id,
 955                                   uint8_t stat_idx,
 956                                   uint8_t is_rx)
 957 {
 958 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 959 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 960 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 961
 962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 963         struct ixgbe_stat_mapping_registers *stat_mappings =
 964                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 965         uint32_t qsmr_mask = 0;
 966         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 967         uint32_t q_map;
 968         uint8_t n, offset;
 969
 970         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 971                 (hw->mac.type != ixgbe_mac_X540) &&
 972                 (hw->mac.type != ixgbe_mac_X550) &&
 973                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 974                 (hw->mac.type != ixgbe_mac_X550EM_a))
 975                 return -ENOSYS;
 976
 977         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 978                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 979                      queue_id, stat_idx);
 980
 981         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 982         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 983                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 984                 return -EIO;
 985         }
 986         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 987
 988         /* Now clear any previous stat_idx set */
 989         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 990         if (!is_rx)
 991                 stat_mappings->tqsm[n] &= ~clearing_mask;
 992         else
 993                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 994
 995         q_map = (uint32_t)stat_idx;
 996         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 997         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 998         if (!is_rx)
 999                 stat_mappings->tqsm[n] |= qsmr_mask;
1000         else
1001                 stat_mappings->rqsmr[n] |= qsmr_mask;
1002
1003         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1004                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1005                      queue_id, stat_idx);
1006         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1007                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1008
1009         /* Now write the mapping in the appropriate register */
1010         if (is_rx) {
1011                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1012                              stat_mappings->rqsmr[n], n);
1013                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1014         } else {
1015                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1016                              stat_mappings->tqsm[n], n);
1017                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1018         }
1019         return 0;
1020 }
1021
1022 static void
1023 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1024 {
1025         struct ixgbe_stat_mapping_registers *stat_mappings =
1026                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1028         int i;
1029
1030         /* write whatever was in stat mapping table to the NIC */
1031         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1032                 /* rx */
1033                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1034
1035                 /* tx */
1036                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1037         }
1038 }
1039
1040 static void
1041 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1042 {
1043         uint8_t i;
1044         struct ixgbe_dcb_tc_config *tc;
1045         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1046
1047         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1048         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1049         for (i = 0; i < dcb_max_tc; i++) {
1050                 tc = &dcb_config->tc_config[i];
1051                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1052                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1053                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1054                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1055                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1056                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1057                 tc->pfc = ixgbe_dcb_pfc_disabled;
1058         }
1059
1060         /* Initialize default user to priority mapping, UPx->TC0 */
1061         tc = &dcb_config->tc_config[0];
1062         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1063         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1064         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1065                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1066                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1067         }
1068         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1069         dcb_config->pfc_mode_enable = false;
1070         dcb_config->vt_mode = true;
1071         dcb_config->round_robin_enable = false;
1072         /* support all DCB capabilities in 82599 */
1073         dcb_config->support.capabilities = 0xFF;
1074
1075         /*we only support 4 Tcs for X540, X550 */
1076         if (hw->mac.type == ixgbe_mac_X540 ||
1077                 hw->mac.type == ixgbe_mac_X550 ||
1078                 hw->mac.type == ixgbe_mac_X550EM_x ||
1079                 hw->mac.type == ixgbe_mac_X550EM_a) {
1080                 dcb_config->num_tcs.pg_tcs = 4;
1081                 dcb_config->num_tcs.pfc_tcs = 4;
1082         }
1083 }
1084
1085 /*
1086  * Ensure that all locks are released before first NVM or PHY access
1087  */
1088 static void
1089 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1090 {
1091         uint16_t mask;
1092
1093         /*
1094          * Phy lock should not fail in this early stage. If this is the case,
1095          * it is due to an improper exit of the application.
1096          * So force the release of the faulty lock. Release of common lock
1097          * is done automatically by swfw_sync function.
1098          */
1099         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1100         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1101                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1102         }
1103         ixgbe_release_swfw_semaphore(hw, mask);
1104
1105         /*
1106          * These ones are more tricky since they are common to all ports; but
1107          * swfw_sync retries last long enough (1s) to be almost sure that if
1108          * lock can not be taken it is due to an improper lock of the
1109          * semaphore.
1110          */
1111         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1112         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1113                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1114         }
1115         ixgbe_release_swfw_semaphore(hw, mask);
1116 }
1117
1118 /*
1119  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1120  * It returns 0 on success.
1121  */
1122 static int
1123 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1124 {
1125         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1126         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1127         struct ixgbe_hw *hw =
1128                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1129         struct ixgbe_vfta *shadow_vfta =
1130                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1131         struct ixgbe_hwstrip *hwstrip =
1132                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1133         struct ixgbe_dcb_config *dcb_config =
1134                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1135         struct ixgbe_filter_info *filter_info =
1136                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1137         uint32_t ctrl_ext;
1138         uint16_t csum;
1139         int diag, i;
1140
1141         PMD_INIT_FUNC_TRACE();
1142
1143         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1144         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1145         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1146         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1147
1148         /*
1149          * For secondary processes, we don't initialise any further as primary
1150          * has already done this work. Only check we don't need a different
1151          * RX and TX function.
1152          */
1153         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1154                 struct ixgbe_tx_queue *txq;
1155                 /* TX queue function in primary, set by last queue initialized
1156                  * Tx queue may not initialized by primary process
1157                  */
1158                 if (eth_dev->data->tx_queues) {
1159                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1160                         ixgbe_set_tx_function(eth_dev, txq);
1161                 } else {
1162                         /* Use default TX function if we get here */
1163                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1164                                      "Using default TX function.");
1165                 }
1166
1167                 ixgbe_set_rx_function(eth_dev);
1168
1169                 return 0;
1170         }
1171
1172         rte_eth_copy_pci_info(eth_dev, pci_dev);
1173         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1174
1175         /* Vendor and Device ID need to be set before init of shared code */
1176         hw->device_id = pci_dev->id.device_id;
1177         hw->vendor_id = pci_dev->id.vendor_id;
1178         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1179         hw->allow_unsupported_sfp = 1;
1180
1181         /* Initialize the shared code (base driver) */
1182 #ifdef RTE_NIC_BYPASS
1183         diag = ixgbe_bypass_init_shared_code(hw);
1184 #else
1185         diag = ixgbe_init_shared_code(hw);
1186 #endif /* RTE_NIC_BYPASS */
1187
1188         if (diag != IXGBE_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1190                 return -EIO;
1191         }
1192
1193         /* pick up the PCI bus settings for reporting later */
1194         ixgbe_get_bus_info(hw);
1195
1196         /* Unlock any pending hardware semaphore */
1197         ixgbe_swfw_lock_reset(hw);
1198
1199         /* Initialize DCB configuration*/
1200         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1201         ixgbe_dcb_init(hw, dcb_config);
1202         /* Get Hardware Flow Control setting */
1203         hw->fc.requested_mode = ixgbe_fc_full;
1204         hw->fc.current_mode = ixgbe_fc_full;
1205         hw->fc.pause_time = IXGBE_FC_PAUSE;
1206         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1207                 hw->fc.low_water[i] = IXGBE_FC_LO;
1208                 hw->fc.high_water[i] = IXGBE_FC_HI;
1209         }
1210         hw->fc.send_xon = 1;
1211
1212         /* Make sure we have a good EEPROM before we read from it */
1213         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1214         if (diag != IXGBE_SUCCESS) {
1215                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1216                 return -EIO;
1217         }
1218
1219 #ifdef RTE_NIC_BYPASS
1220         diag = ixgbe_bypass_init_hw(hw);
1221 #else
1222         diag = ixgbe_init_hw(hw);
1223 #endif /* RTE_NIC_BYPASS */
1224
1225         /*
1226          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1227          * is called too soon after the kernel driver unbinding/binding occurs.
1228          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1229          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1230          * also called. See ixgbe_identify_phy_82599(). The reason for the
1231          * failure is not known, and only occuts when virtualisation features
1232          * are disabled in the bios. A delay of 100ms  was found to be enough by
1233          * trial-and-error, and is doubled to be safe.
1234          */
1235         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1236                 rte_delay_ms(200);
1237                 diag = ixgbe_init_hw(hw);
1238         }
1239
1240         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1241                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1242                              "LOM.  Please be aware there may be issues associated "
1243                              "with your hardware.");
1244                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1245                              "please contact your Intel or hardware representative "
1246                              "who provided you with this hardware.");
1247         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1248                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1249         if (diag) {
1250                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1251                 return -EIO;
1252         }
1253
1254         /* Reset the hw statistics */
1255         ixgbe_dev_stats_reset(eth_dev);
1256
1257         /* disable interrupt */
1258         ixgbe_disable_intr(hw);
1259
1260         /* reset mappings for queue statistics hw counters*/
1261         ixgbe_reset_qstat_mappings(hw);
1262
1263         /* Allocate memory for storing MAC addresses */
1264         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1265                                                hw->mac.num_rar_entries, 0);
1266         if (eth_dev->data->mac_addrs == NULL) {
1267                 PMD_INIT_LOG(ERR,
1268                              "Failed to allocate %u bytes needed to store "
1269                              "MAC addresses",
1270                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1271                 return -ENOMEM;
1272         }
1273         /* Copy the permanent MAC address */
1274         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1275                         &eth_dev->data->mac_addrs[0]);
1276
1277         /* Allocate memory for storing hash filter MAC addresses */
1278         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1279                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1280         if (eth_dev->data->hash_mac_addrs == NULL) {
1281                 PMD_INIT_LOG(ERR,
1282                              "Failed to allocate %d bytes needed to store MAC addresses",
1283                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1284                 return -ENOMEM;
1285         }
1286
1287         /* initialize the vfta */
1288         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1289
1290         /* initialize the hw strip bitmap*/
1291         memset(hwstrip, 0, sizeof(*hwstrip));
1292
1293         /* initialize PF if max_vfs not zero */
1294         ixgbe_pf_host_init(eth_dev);
1295
1296         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1297         /* let hardware know driver is loaded */
1298         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1299         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1300         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1301         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1302         IXGBE_WRITE_FLUSH(hw);
1303
1304         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1305                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1306                              (int) hw->mac.type, (int) hw->phy.type,
1307                              (int) hw->phy.sfp_type);
1308         else
1309                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1310                              (int) hw->mac.type, (int) hw->phy.type);
1311
1312         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1313                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1314                      pci_dev->id.device_id);
1315
1316         rte_intr_callback_register(intr_handle,
1317                                    ixgbe_dev_interrupt_handler, eth_dev);
1318
1319         /* enable uio/vfio intr/eventfd mapping */
1320         rte_intr_enable(intr_handle);
1321
1322         /* enable support intr */
1323         ixgbe_enable_intr(eth_dev);
1324
1325         /* initialize 5tuple filter list */
1326         TAILQ_INIT(&filter_info->fivetuple_list);
1327         memset(filter_info->fivetuple_mask, 0,
1328                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1329
1330         return 0;
1331 }
1332
1333 static int
1334 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1335 {
1336         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1337         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1338         struct ixgbe_hw *hw;
1339
1340         PMD_INIT_FUNC_TRACE();
1341
1342         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1343                 return -EPERM;
1344
1345         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1346
1347         if (hw->adapter_stopped == 0)
1348                 ixgbe_dev_close(eth_dev);
1349
1350         eth_dev->dev_ops = NULL;
1351         eth_dev->rx_pkt_burst = NULL;
1352         eth_dev->tx_pkt_burst = NULL;
1353
1354         /* Unlock any pending hardware semaphore */
1355         ixgbe_swfw_lock_reset(hw);
1356
1357         /* disable uio intr before callback unregister */
1358         rte_intr_disable(intr_handle);
1359         rte_intr_callback_unregister(intr_handle,
1360                                      ixgbe_dev_interrupt_handler, eth_dev);
1361
1362         /* uninitialize PF if max_vfs not zero */
1363         ixgbe_pf_host_uninit(eth_dev);
1364
1365         rte_free(eth_dev->data->mac_addrs);
1366         eth_dev->data->mac_addrs = NULL;
1367
1368         rte_free(eth_dev->data->hash_mac_addrs);
1369         eth_dev->data->hash_mac_addrs = NULL;
1370
1371         return 0;
1372 }
1373
1374 /*
1375  * Negotiate mailbox API version with the PF.
1376  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1377  * Then we try to negotiate starting with the most recent one.
1378  * If all negotiation attempts fail, then we will proceed with
1379  * the default one (ixgbe_mbox_api_10).
1380  */
1381 static void
1382 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1383 {
1384         int32_t i;
1385
1386         /* start with highest supported, proceed down */
1387         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1388                 ixgbe_mbox_api_12,
1389                 ixgbe_mbox_api_11,
1390                 ixgbe_mbox_api_10,
1391         };
1392
1393         for (i = 0;
1394                         i != RTE_DIM(sup_ver) &&
1395                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1396                         i++)
1397                 ;
1398 }
1399
1400 static void
1401 generate_random_mac_addr(struct ether_addr *mac_addr)
1402 {
1403         uint64_t random;
1404
1405         /* Set Organizationally Unique Identifier (OUI) prefix. */
1406         mac_addr->addr_bytes[0] = 0x00;
1407         mac_addr->addr_bytes[1] = 0x09;
1408         mac_addr->addr_bytes[2] = 0xC0;
1409         /* Force indication of locally assigned MAC address. */
1410         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1411         /* Generate the last 3 bytes of the MAC address with a random number. */
1412         random = rte_rand();
1413         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1414 }
1415
1416 /*
1417  * Virtual Function device init
1418  */
1419 static int
1420 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1421 {
1422         int diag;
1423         uint32_t tc, tcs;
1424         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1425         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1426         struct ixgbe_hw *hw =
1427                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1428         struct ixgbe_vfta *shadow_vfta =
1429                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1430         struct ixgbe_hwstrip *hwstrip =
1431                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1432         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1433
1434         PMD_INIT_FUNC_TRACE();
1435
1436         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1437         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1438         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1439
1440         /* for secondary processes, we don't initialise any further as primary
1441          * has already done this work. Only check we don't need a different
1442          * RX function
1443          */
1444         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1445                 struct ixgbe_tx_queue *txq;
1446                 /* TX queue function in primary, set by last queue initialized
1447                  * Tx queue may not initialized by primary process
1448                  */
1449                 if (eth_dev->data->tx_queues) {
1450                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1451                         ixgbe_set_tx_function(eth_dev, txq);
1452                 } else {
1453                         /* Use default TX function if we get here */
1454                         PMD_INIT_LOG(NOTICE,
1455                                      "No TX queues configured yet. Using default TX function.");
1456                 }
1457
1458                 ixgbe_set_rx_function(eth_dev);
1459
1460                 return 0;
1461         }
1462
1463         rte_eth_copy_pci_info(eth_dev, pci_dev);
1464         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1465
1466         hw->device_id = pci_dev->id.device_id;
1467         hw->vendor_id = pci_dev->id.vendor_id;
1468         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1469
1470         /* initialize the vfta */
1471         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1472
1473         /* initialize the hw strip bitmap*/
1474         memset(hwstrip, 0, sizeof(*hwstrip));
1475
1476         /* Initialize the shared code (base driver) */
1477         diag = ixgbe_init_shared_code(hw);
1478         if (diag != IXGBE_SUCCESS) {
1479                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1480                 return -EIO;
1481         }
1482
1483         /* init_mailbox_params */
1484         hw->mbx.ops.init_params(hw);
1485
1486         /* Reset the hw statistics */
1487         ixgbevf_dev_stats_reset(eth_dev);
1488
1489         /* Disable the interrupts for VF */
1490         ixgbevf_intr_disable(hw);
1491
1492         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1493         diag = hw->mac.ops.reset_hw(hw);
1494
1495         /*
1496          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1497          * the underlying PF driver has not assigned a MAC address to the VF.
1498          * In this case, assign a random MAC address.
1499          */
1500         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1501                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1502                 return diag;
1503         }
1504
1505         /* negotiate mailbox API version to use with the PF. */
1506         ixgbevf_negotiate_api(hw);
1507
1508         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1509         ixgbevf_get_queues(hw, &tcs, &tc);
1510
1511         /* Allocate memory for storing MAC addresses */
1512         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1513                                                hw->mac.num_rar_entries, 0);
1514         if (eth_dev->data->mac_addrs == NULL) {
1515                 PMD_INIT_LOG(ERR,
1516                              "Failed to allocate %u bytes needed to store "
1517                              "MAC addresses",
1518                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1519                 return -ENOMEM;
1520         }
1521
1522         /* Generate a random MAC address, if none was assigned by PF. */
1523         if (is_zero_ether_addr(perm_addr)) {
1524                 generate_random_mac_addr(perm_addr);
1525                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1526                 if (diag) {
1527                         rte_free(eth_dev->data->mac_addrs);
1528                         eth_dev->data->mac_addrs = NULL;
1529                         return diag;
1530                 }
1531                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1532                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1533                              "%02x:%02x:%02x:%02x:%02x:%02x",
1534                              perm_addr->addr_bytes[0],
1535                              perm_addr->addr_bytes[1],
1536                              perm_addr->addr_bytes[2],
1537                              perm_addr->addr_bytes[3],
1538                              perm_addr->addr_bytes[4],
1539                              perm_addr->addr_bytes[5]);
1540         }
1541
1542         /* Copy the permanent MAC address */
1543         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1544
1545         /* reset the hardware with the new settings */
1546         diag = hw->mac.ops.start_hw(hw);
1547         switch (diag) {
1548         case  0:
1549                 break;
1550
1551         default:
1552                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1553                 return -EIO;
1554         }
1555
1556         rte_intr_callback_register(intr_handle,
1557                                    ixgbevf_dev_interrupt_handler, eth_dev);
1558         rte_intr_enable(intr_handle);
1559         ixgbevf_intr_enable(hw);
1560
1561         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1562                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1563                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1564
1565         return 0;
1566 }
1567
1568 /* Virtual Function device uninit */
1569
1570 static int
1571 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1572 {
1573         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1574         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1575         struct ixgbe_hw *hw;
1576
1577         PMD_INIT_FUNC_TRACE();
1578
1579         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1580                 return -EPERM;
1581
1582         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1583
1584         if (hw->adapter_stopped == 0)
1585                 ixgbevf_dev_close(eth_dev);
1586
1587         eth_dev->dev_ops = NULL;
1588         eth_dev->rx_pkt_burst = NULL;
1589         eth_dev->tx_pkt_burst = NULL;
1590
1591         /* Disable the interrupts for VF */
1592         ixgbevf_intr_disable(hw);
1593
1594         rte_free(eth_dev->data->mac_addrs);
1595         eth_dev->data->mac_addrs = NULL;
1596
1597         rte_intr_disable(intr_handle);
1598         rte_intr_callback_unregister(intr_handle,
1599                                      ixgbevf_dev_interrupt_handler, eth_dev);
1600
1601         return 0;
1602 }
1603
1604 static struct eth_driver rte_ixgbe_pmd = {
1605         .pci_drv = {
1606                 .id_table = pci_id_ixgbe_map,
1607                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1608                 .probe = rte_eth_dev_pci_probe,
1609                 .remove = rte_eth_dev_pci_remove,
1610         },
1611         .eth_dev_init = eth_ixgbe_dev_init,
1612         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1613         .dev_private_size = sizeof(struct ixgbe_adapter),
1614 };
1615
1616 /*
1617  * virtual function driver struct
1618  */
1619 static struct eth_driver rte_ixgbevf_pmd = {
1620         .pci_drv = {
1621                 .id_table = pci_id_ixgbevf_map,
1622                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1623                 .probe = rte_eth_dev_pci_probe,
1624                 .remove = rte_eth_dev_pci_remove,
1625         },
1626         .eth_dev_init = eth_ixgbevf_dev_init,
1627         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1628         .dev_private_size = sizeof(struct ixgbe_adapter),
1629 };
1630
1631 static int
1632 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1633 {
1634         struct ixgbe_hw *hw =
1635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636         struct ixgbe_vfta *shadow_vfta =
1637                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1638         uint32_t vfta;
1639         uint32_t vid_idx;
1640         uint32_t vid_bit;
1641
1642         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1643         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1644         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1645         if (on)
1646                 vfta |= vid_bit;
1647         else
1648                 vfta &= ~vid_bit;
1649         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1650
1651         /* update local VFTA copy */
1652         shadow_vfta->vfta[vid_idx] = vfta;
1653
1654         return 0;
1655 }
1656
1657 static void
1658 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1659 {
1660         if (on)
1661                 ixgbe_vlan_hw_strip_enable(dev, queue);
1662         else
1663                 ixgbe_vlan_hw_strip_disable(dev, queue);
1664 }
1665
1666 static int
1667 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1668                     enum rte_vlan_type vlan_type,
1669                     uint16_t tpid)
1670 {
1671         struct ixgbe_hw *hw =
1672                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673         int ret = 0;
1674         uint32_t reg;
1675         uint32_t qinq;
1676
1677         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1678         qinq &= IXGBE_DMATXCTL_GDV;
1679
1680         switch (vlan_type) {
1681         case ETH_VLAN_TYPE_INNER:
1682                 if (qinq) {
1683                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1684                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1685                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1686                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1687                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1688                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1689                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1690                 } else {
1691                         ret = -ENOTSUP;
1692                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1693                                     " by single VLAN");
1694                 }
1695                 break;
1696         case ETH_VLAN_TYPE_OUTER:
1697                 if (qinq) {
1698                         /* Only the high 16-bits is valid */
1699                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1700                                         IXGBE_EXVET_VET_EXT_SHIFT);
1701                 } else {
1702                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1703                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1704                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1705                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1706                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1707                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1708                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1709                 }
1710
1711                 break;
1712         default:
1713                 ret = -EINVAL;
1714                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1715                 break;
1716         }
1717
1718         return ret;
1719 }
1720
1721 void
1722 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1723 {
1724         struct ixgbe_hw *hw =
1725                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         uint32_t vlnctrl;
1727
1728         PMD_INIT_FUNC_TRACE();
1729
1730         /* Filter Table Disable */
1731         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1732         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1733
1734         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1735 }
1736
1737 void
1738 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1739 {
1740         struct ixgbe_hw *hw =
1741                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1742         struct ixgbe_vfta *shadow_vfta =
1743                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1744         uint32_t vlnctrl;
1745         uint16_t i;
1746
1747         PMD_INIT_FUNC_TRACE();
1748
1749         /* Filter Table Enable */
1750         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1751         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1752         vlnctrl |= IXGBE_VLNCTRL_VFE;
1753
1754         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1755
1756         /* write whatever is in local vfta copy */
1757         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1758                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1759 }
1760
1761 static void
1762 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1763 {
1764         struct ixgbe_hwstrip *hwstrip =
1765                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1766         struct ixgbe_rx_queue *rxq;
1767
1768         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1769                 return;
1770
1771         if (on)
1772                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1773         else
1774                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1775
1776         if (queue >= dev->data->nb_rx_queues)
1777                 return;
1778
1779         rxq = dev->data->rx_queues[queue];
1780
1781         if (on)
1782                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1783         else
1784                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1785 }
1786
1787 static void
1788 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1789 {
1790         struct ixgbe_hw *hw =
1791                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1792         uint32_t ctrl;
1793
1794         PMD_INIT_FUNC_TRACE();
1795
1796         if (hw->mac.type == ixgbe_mac_82598EB) {
1797                 /* No queue level support */
1798                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1799                 return;
1800         }
1801
1802         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1803         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1804         ctrl &= ~IXGBE_RXDCTL_VME;
1805         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1806
1807         /* record those setting for HW strip per queue */
1808         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1809 }
1810
1811 static void
1812 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1813 {
1814         struct ixgbe_hw *hw =
1815                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816         uint32_t ctrl;
1817
1818         PMD_INIT_FUNC_TRACE();
1819
1820         if (hw->mac.type == ixgbe_mac_82598EB) {
1821                 /* No queue level supported */
1822                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1823                 return;
1824         }
1825
1826         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1827         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1828         ctrl |= IXGBE_RXDCTL_VME;
1829         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1830
1831         /* record those setting for HW strip per queue */
1832         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1833 }
1834
1835 void
1836 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1837 {
1838         struct ixgbe_hw *hw =
1839                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         uint32_t ctrl;
1841         uint16_t i;
1842         struct ixgbe_rx_queue *rxq;
1843
1844         PMD_INIT_FUNC_TRACE();
1845
1846         if (hw->mac.type == ixgbe_mac_82598EB) {
1847                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1848                 ctrl &= ~IXGBE_VLNCTRL_VME;
1849                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1850         } else {
1851                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1852                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1853                         rxq = dev->data->rx_queues[i];
1854                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1855                         ctrl &= ~IXGBE_RXDCTL_VME;
1856                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1857
1858                         /* record those setting for HW strip per queue */
1859                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1860                 }
1861         }
1862 }
1863
1864 void
1865 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1866 {
1867         struct ixgbe_hw *hw =
1868                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         uint32_t ctrl;
1870         uint16_t i;
1871         struct ixgbe_rx_queue *rxq;
1872
1873         PMD_INIT_FUNC_TRACE();
1874
1875         if (hw->mac.type == ixgbe_mac_82598EB) {
1876                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1877                 ctrl |= IXGBE_VLNCTRL_VME;
1878                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1879         } else {
1880                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1881                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1882                         rxq = dev->data->rx_queues[i];
1883                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1884                         ctrl |= IXGBE_RXDCTL_VME;
1885                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1886
1887                         /* record those setting for HW strip per queue */
1888                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1889                 }
1890         }
1891 }
1892
1893 static void
1894 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1895 {
1896         struct ixgbe_hw *hw =
1897                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898         uint32_t ctrl;
1899
1900         PMD_INIT_FUNC_TRACE();
1901
1902         /* DMATXCTRL: Geric Double VLAN Disable */
1903         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1904         ctrl &= ~IXGBE_DMATXCTL_GDV;
1905         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1906
1907         /* CTRL_EXT: Global Double VLAN Disable */
1908         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1909         ctrl &= ~IXGBE_EXTENDED_VLAN;
1910         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1911
1912 }
1913
1914 static void
1915 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1916 {
1917         struct ixgbe_hw *hw =
1918                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1919         uint32_t ctrl;
1920
1921         PMD_INIT_FUNC_TRACE();
1922
1923         /* DMATXCTRL: Geric Double VLAN Enable */
1924         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1925         ctrl |= IXGBE_DMATXCTL_GDV;
1926         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1927
1928         /* CTRL_EXT: Global Double VLAN Enable */
1929         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1930         ctrl |= IXGBE_EXTENDED_VLAN;
1931         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1932
1933         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1934         if (hw->mac.type == ixgbe_mac_X550 ||
1935             hw->mac.type == ixgbe_mac_X550EM_x ||
1936             hw->mac.type == ixgbe_mac_X550EM_a) {
1937                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1938                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1939                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1940         }
1941
1942         /*
1943          * VET EXT field in the EXVET register = 0x8100 by default
1944          * So no need to change. Same to VT field of DMATXCTL register
1945          */
1946 }
1947
1948 static void
1949 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1950 {
1951         if (mask & ETH_VLAN_STRIP_MASK) {
1952                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1953                         ixgbe_vlan_hw_strip_enable_all(dev);
1954                 else
1955                         ixgbe_vlan_hw_strip_disable_all(dev);
1956         }
1957
1958         if (mask & ETH_VLAN_FILTER_MASK) {
1959                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1960                         ixgbe_vlan_hw_filter_enable(dev);
1961                 else
1962                         ixgbe_vlan_hw_filter_disable(dev);
1963         }
1964
1965         if (mask & ETH_VLAN_EXTEND_MASK) {
1966                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1967                         ixgbe_vlan_hw_extend_enable(dev);
1968                 else
1969                         ixgbe_vlan_hw_extend_disable(dev);
1970         }
1971 }
1972
1973 static void
1974 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1975 {
1976         struct ixgbe_hw *hw =
1977                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1979         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1980
1981         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1982         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1983 }
1984
1985 static int
1986 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1987 {
1988         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
1989
1990         switch (nb_rx_q) {
1991         case 1:
1992         case 2:
1993                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1994                 break;
1995         case 4:
1996                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1997                 break;
1998         default:
1999                 return -EINVAL;
2000         }
2001
2002         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2003         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2004
2005         return 0;
2006 }
2007
2008 static int
2009 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2010 {
2011         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2014         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2015
2016         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2017                 /* check multi-queue mode */
2018                 switch (dev_conf->rxmode.mq_mode) {
2019                 case ETH_MQ_RX_VMDQ_DCB:
2020                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2021                         break;
2022                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2023                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2024                         PMD_INIT_LOG(ERR, "SRIOV active,"
2025                                         " unsupported mq_mode rx %d.",
2026                                         dev_conf->rxmode.mq_mode);
2027                         return -EINVAL;
2028                 case ETH_MQ_RX_RSS:
2029                 case ETH_MQ_RX_VMDQ_RSS:
2030                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2031                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2032                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2033                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2034                                                 " invalid queue number"
2035                                                 " for VMDQ RSS, allowed"
2036                                                 " value are 1, 2 or 4.");
2037                                         return -EINVAL;
2038                                 }
2039                         break;
2040                 case ETH_MQ_RX_VMDQ_ONLY:
2041                 case ETH_MQ_RX_NONE:
2042                         /* if nothing mq mode configure, use default scheme */
2043                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2044                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2045                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2046                         break;
2047                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2048                         /* SRIOV only works in VMDq enable mode */
2049                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2050                                         " wrong mq_mode rx %d.",
2051                                         dev_conf->rxmode.mq_mode);
2052                         return -EINVAL;
2053                 }
2054
2055                 switch (dev_conf->txmode.mq_mode) {
2056                 case ETH_MQ_TX_VMDQ_DCB:
2057                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2058                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2059                         break;
2060                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2061                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2062                         break;
2063                 }
2064
2065                 /* check valid queue number */
2066                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2067                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2068                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2069                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2070                                         " must be less than or equal to %d.",
2071                                         nb_rx_q, nb_tx_q,
2072                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2073                         return -EINVAL;
2074                 }
2075         } else {
2076                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2077                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2078                                           " not supported.");
2079                         return -EINVAL;
2080                 }
2081                 /* check configuration for vmdb+dcb mode */
2082                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2083                         const struct rte_eth_vmdq_dcb_conf *conf;
2084
2085                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2086                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2087                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2088                                 return -EINVAL;
2089                         }
2090                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2091                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2092                                conf->nb_queue_pools == ETH_32_POOLS)) {
2093                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2094                                                 " nb_queue_pools must be %d or %d.",
2095                                                 ETH_16_POOLS, ETH_32_POOLS);
2096                                 return -EINVAL;
2097                         }
2098                 }
2099                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2100                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2101
2102                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2103                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2104                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2105                                 return -EINVAL;
2106                         }
2107                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2108                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2109                                conf->nb_queue_pools == ETH_32_POOLS)) {
2110                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2111                                                 " nb_queue_pools != %d and"
2112                                                 " nb_queue_pools != %d.",
2113                                                 ETH_16_POOLS, ETH_32_POOLS);
2114                                 return -EINVAL;
2115                         }
2116                 }
2117
2118                 /* For DCB mode check our configuration before we go further */
2119                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2120                         const struct rte_eth_dcb_rx_conf *conf;
2121
2122                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2123                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2124                                                  IXGBE_DCB_NB_QUEUES);
2125                                 return -EINVAL;
2126                         }
2127                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2128                         if (!(conf->nb_tcs == ETH_4_TCS ||
2129                                conf->nb_tcs == ETH_8_TCS)) {
2130                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2131                                                 " and nb_tcs != %d.",
2132                                                 ETH_4_TCS, ETH_8_TCS);
2133                                 return -EINVAL;
2134                         }
2135                 }
2136
2137                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2138                         const struct rte_eth_dcb_tx_conf *conf;
2139
2140                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2141                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2142                                                  IXGBE_DCB_NB_QUEUES);
2143                                 return -EINVAL;
2144                         }
2145                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2146                         if (!(conf->nb_tcs == ETH_4_TCS ||
2147                                conf->nb_tcs == ETH_8_TCS)) {
2148                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2149                                                 " and nb_tcs != %d.",
2150                                                 ETH_4_TCS, ETH_8_TCS);
2151                                 return -EINVAL;
2152                         }
2153                 }
2154
2155                 /*
2156                  * When DCB/VT is off, maximum number of queues changes,
2157                  * except for 82598EB, which remains constant.
2158                  */
2159                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2160                                 hw->mac.type != ixgbe_mac_82598EB) {
2161                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2162                                 PMD_INIT_LOG(ERR,
2163                                              "Neither VT nor DCB are enabled, "
2164                                              "nb_tx_q > %d.",
2165                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2166                                 return -EINVAL;
2167                         }
2168                 }
2169         }
2170         return 0;
2171 }
2172
2173 static int
2174 ixgbe_dev_configure(struct rte_eth_dev *dev)
2175 {
2176         struct ixgbe_interrupt *intr =
2177                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2178         struct ixgbe_adapter *adapter =
2179                 (struct ixgbe_adapter *)dev->data->dev_private;
2180         int ret;
2181
2182         PMD_INIT_FUNC_TRACE();
2183         /* multipe queue mode checking */
2184         ret  = ixgbe_check_mq_mode(dev);
2185         if (ret != 0) {
2186                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2187                             ret);
2188                 return ret;
2189         }
2190
2191         /* set flag to update link status after init */
2192         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2193
2194         /*
2195          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2196          * allocation or vector Rx preconditions we will reset it.
2197          */
2198         adapter->rx_bulk_alloc_allowed = true;
2199         adapter->rx_vec_allowed = true;
2200
2201         return 0;
2202 }
2203
2204 static void
2205 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2206 {
2207         struct ixgbe_hw *hw =
2208                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2209         struct ixgbe_interrupt *intr =
2210                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2211         uint32_t gpie;
2212
2213         /* only set up it on X550EM_X */
2214         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2215                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2216                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2217                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2218                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2219                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2220         }
2221 }
2222
2223 /*
2224  * Configure device link speed and setup link.
2225  * It returns 0 on success.
2226  */
2227 static int
2228 ixgbe_dev_start(struct rte_eth_dev *dev)
2229 {
2230         struct ixgbe_hw *hw =
2231                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232         struct ixgbe_vf_info *vfinfo =
2233                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2234         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2235         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2236         uint32_t intr_vector = 0;
2237         int err, link_up = 0, negotiate = 0;
2238         uint32_t speed = 0;
2239         int mask = 0;
2240         int status;
2241         uint16_t vf, idx;
2242         uint32_t *link_speeds;
2243
2244         PMD_INIT_FUNC_TRACE();
2245
2246         /* IXGBE devices don't support:
2247         *    - half duplex (checked afterwards for valid speeds)
2248         *    - fixed speed: TODO implement
2249         */
2250         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2251                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2252                              dev->data->port_id);
2253                 return -EINVAL;
2254         }
2255
2256         /* disable uio/vfio intr/eventfd mapping */
2257         rte_intr_disable(intr_handle);
2258
2259         /* stop adapter */
2260         hw->adapter_stopped = 0;
2261         ixgbe_stop_adapter(hw);
2262
2263         /* reinitialize adapter
2264          * this calls reset and start
2265          */
2266         status = ixgbe_pf_reset_hw(hw);
2267         if (status != 0)
2268                 return -1;
2269         hw->mac.ops.start_hw(hw);
2270         hw->mac.get_link_status = true;
2271
2272         /* configure PF module if SRIOV enabled */
2273         ixgbe_pf_host_configure(dev);
2274
2275         ixgbe_dev_phy_intr_setup(dev);
2276
2277         /* check and configure queue intr-vector mapping */
2278         if ((rte_intr_cap_multiple(intr_handle) ||
2279              !RTE_ETH_DEV_SRIOV(dev).active) &&
2280             dev->data->dev_conf.intr_conf.rxq != 0) {
2281                 intr_vector = dev->data->nb_rx_queues;
2282                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2283                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2284                                         IXGBE_MAX_INTR_QUEUE_NUM);
2285                         return -ENOTSUP;
2286                 }
2287                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2288                         return -1;
2289         }
2290
2291         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2292                 intr_handle->intr_vec =
2293                         rte_zmalloc("intr_vec",
2294                                     dev->data->nb_rx_queues * sizeof(int), 0);
2295                 if (intr_handle->intr_vec == NULL) {
2296                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2297                                      " intr_vec\n", dev->data->nb_rx_queues);
2298                         return -ENOMEM;
2299                 }
2300         }
2301
2302         /* confiugre msix for sleep until rx interrupt */
2303         ixgbe_configure_msix(dev);
2304
2305         /* initialize transmission unit */
2306         ixgbe_dev_tx_init(dev);
2307
2308         /* This can fail when allocating mbufs for descriptor rings */
2309         err = ixgbe_dev_rx_init(dev);
2310         if (err) {
2311                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2312                 goto error;
2313         }
2314
2315     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2316                 ETH_VLAN_EXTEND_MASK;
2317         ixgbe_vlan_offload_set(dev, mask);
2318
2319         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2320                 /* Enable vlan filtering for VMDq */
2321                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2322         }
2323
2324         /* Configure DCB hw */
2325         ixgbe_configure_dcb(dev);
2326
2327         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2328                 err = ixgbe_fdir_configure(dev);
2329                 if (err)
2330                         goto error;
2331         }
2332
2333         /* Restore vf rate limit */
2334         if (vfinfo != NULL) {
2335                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2336                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2337                                 if (vfinfo[vf].tx_rate[idx] != 0)
2338                                         rte_pmd_ixgbe_set_vf_rate_limit(
2339                                                 dev->data->port_id, vf,
2340                                                 vfinfo[vf].tx_rate[idx],
2341                                                 1 << idx);
2342         }
2343
2344         ixgbe_restore_statistics_mapping(dev);
2345
2346         err = ixgbe_dev_rxtx_start(dev);
2347         if (err < 0) {
2348                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2349                 goto error;
2350         }
2351
2352         /* Skip link setup if loopback mode is enabled for 82599. */
2353         if (hw->mac.type == ixgbe_mac_82599EB &&
2354                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2355                 goto skip_link_setup;
2356
2357         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2358                 err = hw->mac.ops.setup_sfp(hw);
2359                 if (err)
2360                         goto error;
2361         }
2362
2363         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2364                 /* Turn on the copper */
2365                 ixgbe_set_phy_power(hw, true);
2366         } else {
2367                 /* Turn on the laser */
2368                 ixgbe_enable_tx_laser(hw);
2369         }
2370
2371         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2372         if (err)
2373                 goto error;
2374         dev->data->dev_link.link_status = link_up;
2375
2376         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2377         if (err)
2378                 goto error;
2379
2380         link_speeds = &dev->data->dev_conf.link_speeds;
2381         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2382                         ETH_LINK_SPEED_10G)) {
2383                 PMD_INIT_LOG(ERR, "Invalid link setting");
2384                 goto error;
2385         }
2386
2387         speed = 0x0;
2388         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2389                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2390                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2391                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2392         } else {
2393                 if (*link_speeds & ETH_LINK_SPEED_10G)
2394                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2395                 if (*link_speeds & ETH_LINK_SPEED_1G)
2396                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2397                 if (*link_speeds & ETH_LINK_SPEED_100M)
2398                         speed |= IXGBE_LINK_SPEED_100_FULL;
2399         }
2400
2401         err = ixgbe_setup_link(hw, speed, link_up);
2402         if (err)
2403                 goto error;
2404
2405 skip_link_setup:
2406
2407         if (rte_intr_allow_others(intr_handle)) {
2408                 /* check if lsc interrupt is enabled */
2409                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2410                         ixgbe_dev_lsc_interrupt_setup(dev);
2411                 ixgbe_dev_macsec_interrupt_setup(dev);
2412         } else {
2413                 rte_intr_callback_unregister(intr_handle,
2414                                              ixgbe_dev_interrupt_handler, dev);
2415                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2416                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2417                                      " no intr multiplex\n");
2418         }
2419
2420         /* check if rxq interrupt is enabled */
2421         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2422             rte_intr_dp_is_en(intr_handle))
2423                 ixgbe_dev_rxq_interrupt_setup(dev);
2424
2425         /* enable uio/vfio intr/eventfd mapping */
2426         rte_intr_enable(intr_handle);
2427
2428         /* resume enabled intr since hw reset */
2429         ixgbe_enable_intr(dev);
2430
2431         return 0;
2432
2433 error:
2434         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2435         ixgbe_dev_clear_queues(dev);
2436         return -EIO;
2437 }
2438
2439 /*
2440  * Stop device: disable rx and tx functions to allow for reconfiguring.
2441  */
2442 static void
2443 ixgbe_dev_stop(struct rte_eth_dev *dev)
2444 {
2445         struct rte_eth_link link;
2446         struct ixgbe_hw *hw =
2447                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448         struct ixgbe_vf_info *vfinfo =
2449                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2450         struct ixgbe_filter_info *filter_info =
2451                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2452         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2453         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2454         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2455         int vf;
2456
2457         PMD_INIT_FUNC_TRACE();
2458
2459         /* disable interrupts */
2460         ixgbe_disable_intr(hw);
2461
2462         /* reset the NIC */
2463         ixgbe_pf_reset_hw(hw);
2464         hw->adapter_stopped = 0;
2465
2466         /* stop adapter */
2467         ixgbe_stop_adapter(hw);
2468
2469         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2470                 vfinfo[vf].clear_to_send = false;
2471
2472         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2473                 /* Turn off the copper */
2474                 ixgbe_set_phy_power(hw, false);
2475         } else {
2476                 /* Turn off the laser */
2477                 ixgbe_disable_tx_laser(hw);
2478         }
2479
2480         ixgbe_dev_clear_queues(dev);
2481
2482         /* Clear stored conf */
2483         dev->data->scattered_rx = 0;
2484         dev->data->lro = 0;
2485
2486         /* Clear recorded link status */
2487         memset(&link, 0, sizeof(link));
2488         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2489
2490         /* Remove all ntuple filters of the device */
2491         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2492              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2493                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2494                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2495                              p_5tuple, entries);
2496                 rte_free(p_5tuple);
2497         }
2498         memset(filter_info->fivetuple_mask, 0,
2499                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2500
2501         if (!rte_intr_allow_others(intr_handle))
2502                 /* resume to the default handler */
2503                 rte_intr_callback_register(intr_handle,
2504                                            ixgbe_dev_interrupt_handler,
2505                                            (void *)dev);
2506
2507         /* Clean datapath event and queue/vec mapping */
2508         rte_intr_efd_disable(intr_handle);
2509         if (intr_handle->intr_vec != NULL) {
2510                 rte_free(intr_handle->intr_vec);
2511                 intr_handle->intr_vec = NULL;
2512         }
2513 }
2514
2515 /*
2516  * Set device link up: enable tx.
2517  */
2518 static int
2519 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2520 {
2521         struct ixgbe_hw *hw =
2522                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         if (hw->mac.type == ixgbe_mac_82599EB) {
2524 #ifdef RTE_NIC_BYPASS
2525                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2526                         /* Not suported in bypass mode */
2527                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2528                                      "by device id 0x%x", hw->device_id);
2529                         return -ENOTSUP;
2530                 }
2531 #endif
2532         }
2533
2534         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2535                 /* Turn on the copper */
2536                 ixgbe_set_phy_power(hw, true);
2537         } else {
2538                 /* Turn on the laser */
2539                 ixgbe_enable_tx_laser(hw);
2540         }
2541
2542         return 0;
2543 }
2544
2545 /*
2546  * Set device link down: disable tx.
2547  */
2548 static int
2549 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2550 {
2551         struct ixgbe_hw *hw =
2552                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553         if (hw->mac.type == ixgbe_mac_82599EB) {
2554 #ifdef RTE_NIC_BYPASS
2555                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2556                         /* Not suported in bypass mode */
2557                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2558                                      "by device id 0x%x", hw->device_id);
2559                         return -ENOTSUP;
2560                 }
2561 #endif
2562         }
2563
2564         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2565                 /* Turn off the copper */
2566                 ixgbe_set_phy_power(hw, false);
2567         } else {
2568                 /* Turn off the laser */
2569                 ixgbe_disable_tx_laser(hw);
2570         }
2571
2572         return 0;
2573 }
2574
2575 /*
2576  * Reest and stop device.
2577  */
2578 static void
2579 ixgbe_dev_close(struct rte_eth_dev *dev)
2580 {
2581         struct ixgbe_hw *hw =
2582                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2583
2584         PMD_INIT_FUNC_TRACE();
2585
2586         ixgbe_pf_reset_hw(hw);
2587
2588         ixgbe_dev_stop(dev);
2589         hw->adapter_stopped = 1;
2590
2591         ixgbe_dev_free_queues(dev);
2592
2593         ixgbe_disable_pcie_master(hw);
2594
2595         /* reprogram the RAR[0] in case user changed it. */
2596         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2597 }
2598
2599 static void
2600 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2601                            struct ixgbe_hw_stats *hw_stats,
2602                            struct ixgbe_macsec_stats *macsec_stats,
2603                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2604                            uint64_t *total_qprc, uint64_t *total_qprdc)
2605 {
2606         uint32_t bprc, lxon, lxoff, total;
2607         uint32_t delta_gprc = 0;
2608         unsigned i;
2609         /* Workaround for RX byte count not including CRC bytes when CRC
2610          * strip is enabled. CRC bytes are removed from counters when crc_strip
2611          * is disabled.
2612          */
2613         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2614                         IXGBE_HLREG0_RXCRCSTRP);
2615
2616         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2617         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2618         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2619         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2620
2621         for (i = 0; i < 8; i++) {
2622                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2623
2624                 /* global total per queue */
2625                 hw_stats->mpc[i] += mp;
2626                 /* Running comprehensive total for stats display */
2627                 *total_missed_rx += hw_stats->mpc[i];
2628                 if (hw->mac.type == ixgbe_mac_82598EB) {
2629                         hw_stats->rnbc[i] +=
2630                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2631                         hw_stats->pxonrxc[i] +=
2632                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2633                         hw_stats->pxoffrxc[i] +=
2634                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2635                 } else {
2636                         hw_stats->pxonrxc[i] +=
2637                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2638                         hw_stats->pxoffrxc[i] +=
2639                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2640                         hw_stats->pxon2offc[i] +=
2641                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2642                 }
2643                 hw_stats->pxontxc[i] +=
2644                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2645                 hw_stats->pxofftxc[i] +=
2646                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2647         }
2648         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2649                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2650                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2651                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2652
2653                 delta_gprc += delta_qprc;
2654
2655                 hw_stats->qprc[i] += delta_qprc;
2656                 hw_stats->qptc[i] += delta_qptc;
2657
2658                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2659                 hw_stats->qbrc[i] +=
2660                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2661                 if (crc_strip == 0)
2662                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2663
2664                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2665                 hw_stats->qbtc[i] +=
2666                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2667
2668                 hw_stats->qprdc[i] += delta_qprdc;
2669                 *total_qprdc += hw_stats->qprdc[i];
2670
2671                 *total_qprc += hw_stats->qprc[i];
2672                 *total_qbrc += hw_stats->qbrc[i];
2673         }
2674         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2675         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2676         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2677
2678         /*
2679          * An errata states that gprc actually counts good + missed packets:
2680          * Workaround to set gprc to summated queue packet receives
2681          */
2682         hw_stats->gprc = *total_qprc;
2683
2684         if (hw->mac.type != ixgbe_mac_82598EB) {
2685                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2686                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2687                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2688                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2689                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2690                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2691                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2692                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2693         } else {
2694                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2695                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2696                 /* 82598 only has a counter in the high register */
2697                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2698                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2699                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2700         }
2701         uint64_t old_tpr = hw_stats->tpr;
2702
2703         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2704         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2705
2706         if (crc_strip == 0)
2707                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2708
2709         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2710         hw_stats->gptc += delta_gptc;
2711         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2712         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2713
2714         /*
2715          * Workaround: mprc hardware is incorrectly counting
2716          * broadcasts, so for now we subtract those.
2717          */
2718         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2719         hw_stats->bprc += bprc;
2720         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2721         if (hw->mac.type == ixgbe_mac_82598EB)
2722                 hw_stats->mprc -= bprc;
2723
2724         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2725         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2726         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2727         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2728         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2729         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2730
2731         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2732         hw_stats->lxontxc += lxon;
2733         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2734         hw_stats->lxofftxc += lxoff;
2735         total = lxon + lxoff;
2736
2737         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2738         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2739         hw_stats->gptc -= total;
2740         hw_stats->mptc -= total;
2741         hw_stats->ptc64 -= total;
2742         hw_stats->gotc -= total * ETHER_MIN_LEN;
2743
2744         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2745         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2746         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2747         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2748         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2749         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2750         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2751         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2752         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2753         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2754         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2755         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2756         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2757         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2758         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2759         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2760         /* Only read FCOE on 82599 */
2761         if (hw->mac.type != ixgbe_mac_82598EB) {
2762                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2763                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2764                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2765                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2766                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2767         }
2768
2769         /* Flow Director Stats registers */
2770         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2771         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2772
2773         /* MACsec Stats registers */
2774         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2775         macsec_stats->out_pkts_encrypted +=
2776                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2777         macsec_stats->out_pkts_protected +=
2778                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2779         macsec_stats->out_octets_encrypted +=
2780                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2781         macsec_stats->out_octets_protected +=
2782                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2783         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2784         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2785         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2786         macsec_stats->in_pkts_unknownsci +=
2787                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2788         macsec_stats->in_octets_decrypted +=
2789                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2790         macsec_stats->in_octets_validated +=
2791                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2792         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2793         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2794         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2795         for (i = 0; i < 2; i++) {
2796                 macsec_stats->in_pkts_ok +=
2797                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2798                 macsec_stats->in_pkts_invalid +=
2799                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2800                 macsec_stats->in_pkts_notvalid +=
2801                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2802         }
2803         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2804         macsec_stats->in_pkts_notusingsa +=
2805                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2806 }
2807
2808 /*
2809  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2810  */
2811 static void
2812 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2813 {
2814         struct ixgbe_hw *hw =
2815                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2816         struct ixgbe_hw_stats *hw_stats =
2817                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2818         struct ixgbe_macsec_stats *macsec_stats =
2819                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2820                                 dev->data->dev_private);
2821         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2822         unsigned i;
2823
2824         total_missed_rx = 0;
2825         total_qbrc = 0;
2826         total_qprc = 0;
2827         total_qprdc = 0;
2828
2829         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2830                         &total_qbrc, &total_qprc, &total_qprdc);
2831
2832         if (stats == NULL)
2833                 return;
2834
2835         /* Fill out the rte_eth_stats statistics structure */
2836         stats->ipackets = total_qprc;
2837         stats->ibytes = total_qbrc;
2838         stats->opackets = hw_stats->gptc;
2839         stats->obytes = hw_stats->gotc;
2840
2841         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2842                 stats->q_ipackets[i] = hw_stats->qprc[i];
2843                 stats->q_opackets[i] = hw_stats->qptc[i];
2844                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2845                 stats->q_obytes[i] = hw_stats->qbtc[i];
2846                 stats->q_errors[i] = hw_stats->qprdc[i];
2847         }
2848
2849         /* Rx Errors */
2850         stats->imissed  = total_missed_rx;
2851         stats->ierrors  = hw_stats->crcerrs +
2852                           hw_stats->mspdc +
2853                           hw_stats->rlec +
2854                           hw_stats->ruc +
2855                           hw_stats->roc +
2856                           hw_stats->illerrc +
2857                           hw_stats->errbc +
2858                           hw_stats->rfc +
2859                           hw_stats->fccrc +
2860                           hw_stats->fclast;
2861
2862         /* Tx Errors */
2863         stats->oerrors  = 0;
2864 }
2865
2866 static void
2867 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2868 {
2869         struct ixgbe_hw_stats *stats =
2870                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2871
2872         /* HW registers are cleared on read */
2873         ixgbe_dev_stats_get(dev, NULL);
2874
2875         /* Reset software totals */
2876         memset(stats, 0, sizeof(*stats));
2877 }
2878
2879 /* This function calculates the number of xstats based on the current config */
2880 static unsigned
2881 ixgbe_xstats_calc_num(void) {
2882         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
2883                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2884                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2885 }
2886
2887 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2888         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2889 {
2890         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2891         unsigned stat, i, count;
2892
2893         if (xstats_names != NULL) {
2894                 count = 0;
2895
2896                 /* Note: limit >= cnt_stats checked upstream
2897                  * in rte_eth_xstats_names()
2898                  */
2899
2900                 /* Extended stats from ixgbe_hw_stats */
2901                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2902                         snprintf(xstats_names[count].name,
2903                                 sizeof(xstats_names[count].name),
2904                                 "%s",
2905                                 rte_ixgbe_stats_strings[i].name);
2906                         count++;
2907                 }
2908
2909                 /* MACsec Stats */
2910                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
2911                         snprintf(xstats_names[count].name,
2912                                 sizeof(xstats_names[count].name),
2913                                 "%s",
2914                                 rte_ixgbe_macsec_strings[i].name);
2915                         count++;
2916                 }
2917
2918                 /* RX Priority Stats */
2919                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2920                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2921                                 snprintf(xstats_names[count].name,
2922                                         sizeof(xstats_names[count].name),
2923                                         "rx_priority%u_%s", i,
2924                                         rte_ixgbe_rxq_strings[stat].name);
2925                                 count++;
2926                         }
2927                 }
2928
2929                 /* TX Priority Stats */
2930                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2931                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2932                                 snprintf(xstats_names[count].name,
2933                                         sizeof(xstats_names[count].name),
2934                                         "tx_priority%u_%s", i,
2935                                         rte_ixgbe_txq_strings[stat].name);
2936                                 count++;
2937                         }
2938                 }
2939         }
2940         return cnt_stats;
2941 }
2942
2943 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2944         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2945 {
2946         unsigned i;
2947
2948         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2949                 return -ENOMEM;
2950
2951         if (xstats_names != NULL)
2952                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2953                         snprintf(xstats_names[i].name,
2954                                 sizeof(xstats_names[i].name),
2955                                 "%s", rte_ixgbevf_stats_strings[i].name);
2956         return IXGBEVF_NB_XSTATS;
2957 }
2958
2959 static int
2960 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2961                                          unsigned n)
2962 {
2963         struct ixgbe_hw *hw =
2964                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2965         struct ixgbe_hw_stats *hw_stats =
2966                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2967         struct ixgbe_macsec_stats *macsec_stats =
2968                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2969                                 dev->data->dev_private);
2970         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2971         unsigned i, stat, count = 0;
2972
2973         count = ixgbe_xstats_calc_num();
2974
2975         if (n < count)
2976                 return count;
2977
2978         total_missed_rx = 0;
2979         total_qbrc = 0;
2980         total_qprc = 0;
2981         total_qprdc = 0;
2982
2983         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2984                         &total_qbrc, &total_qprc, &total_qprdc);
2985
2986         /* If this is a reset xstats is NULL, and we have cleared the
2987          * registers by reading them.
2988          */
2989         if (!xstats)
2990                 return 0;
2991
2992         /* Extended stats from ixgbe_hw_stats */
2993         count = 0;
2994         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2995                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2996                                 rte_ixgbe_stats_strings[i].offset);
2997                 xstats[count].id = count;
2998                 count++;
2999         }
3000
3001         /* MACsec Stats */
3002         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3003                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3004                                 rte_ixgbe_macsec_strings[i].offset);
3005                 xstats[count].id = count;
3006                 count++;
3007         }
3008
3009         /* RX Priority Stats */
3010         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3011                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3012                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3013                                         rte_ixgbe_rxq_strings[stat].offset +
3014                                         (sizeof(uint64_t) * i));
3015                         xstats[count].id = count;
3016                         count++;
3017                 }
3018         }
3019
3020         /* TX Priority Stats */
3021         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3022                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3023                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3024                                         rte_ixgbe_txq_strings[stat].offset +
3025                                         (sizeof(uint64_t) * i));
3026                         xstats[count].id = count;
3027                         count++;
3028                 }
3029         }
3030         return count;
3031 }
3032
3033 static void
3034 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3035 {
3036         struct ixgbe_hw_stats *stats =
3037                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3038         struct ixgbe_macsec_stats *macsec_stats =
3039                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3040                                 dev->data->dev_private);
3041
3042         unsigned count = ixgbe_xstats_calc_num();
3043
3044         /* HW registers are cleared on read */
3045         ixgbe_dev_xstats_get(dev, NULL, count);
3046
3047         /* Reset software totals */
3048         memset(stats, 0, sizeof(*stats));
3049         memset(macsec_stats, 0, sizeof(*macsec_stats));
3050 }
3051
3052 static void
3053 ixgbevf_update_stats(struct rte_eth_dev *dev)
3054 {
3055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3056         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3057                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3058
3059         /* Good Rx packet, include VF loopback */
3060         UPDATE_VF_STAT(IXGBE_VFGPRC,
3061             hw_stats->last_vfgprc, hw_stats->vfgprc);
3062
3063         /* Good Rx octets, include VF loopback */
3064         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3065             hw_stats->last_vfgorc, hw_stats->vfgorc);
3066
3067         /* Good Tx packet, include VF loopback */
3068         UPDATE_VF_STAT(IXGBE_VFGPTC,
3069             hw_stats->last_vfgptc, hw_stats->vfgptc);
3070
3071         /* Good Tx octets, include VF loopback */
3072         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3073             hw_stats->last_vfgotc, hw_stats->vfgotc);
3074
3075         /* Rx Multicst Packet */
3076         UPDATE_VF_STAT(IXGBE_VFMPRC,
3077             hw_stats->last_vfmprc, hw_stats->vfmprc);
3078 }
3079
3080 static int
3081 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3082                        unsigned n)
3083 {
3084         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3085                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3086         unsigned i;
3087
3088         if (n < IXGBEVF_NB_XSTATS)
3089                 return IXGBEVF_NB_XSTATS;
3090
3091         ixgbevf_update_stats(dev);
3092
3093         if (!xstats)
3094                 return 0;
3095
3096         /* Extended stats */
3097         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3098                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3099                         rte_ixgbevf_stats_strings[i].offset);
3100         }
3101
3102         return IXGBEVF_NB_XSTATS;
3103 }
3104
3105 static void
3106 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3107 {
3108         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3109                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3110
3111         ixgbevf_update_stats(dev);
3112
3113         if (stats == NULL)
3114                 return;
3115
3116         stats->ipackets = hw_stats->vfgprc;
3117         stats->ibytes = hw_stats->vfgorc;
3118         stats->opackets = hw_stats->vfgptc;
3119         stats->obytes = hw_stats->vfgotc;
3120 }
3121
3122 static void
3123 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3124 {
3125         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3126                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3127
3128         /* Sync HW register to the last stats */
3129         ixgbevf_dev_stats_get(dev, NULL);
3130
3131         /* reset HW current stats*/
3132         hw_stats->vfgprc = 0;
3133         hw_stats->vfgorc = 0;
3134         hw_stats->vfgptc = 0;
3135         hw_stats->vfgotc = 0;
3136 }
3137
3138 static int
3139 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3140 {
3141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142         u16 eeprom_verh, eeprom_verl;
3143         u32 etrack_id;
3144         int ret;
3145
3146         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3147         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3148
3149         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3150         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3151
3152         ret += 1; /* add the size of '\0' */
3153         if (fw_size < (u32)ret)
3154                 return ret;
3155         else
3156                 return 0;
3157 }
3158
3159 static void
3160 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3161 {
3162         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3164         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3165
3166         dev_info->pci_dev = pci_dev;
3167         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3168         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3169         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3170                 /*
3171                  * When DCB/VT is off, maximum number of queues changes,
3172                  * except for 82598EB, which remains constant.
3173                  */
3174                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3175                                 hw->mac.type != ixgbe_mac_82598EB)
3176                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3177         }
3178         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3179         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3180         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3181         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3182         dev_info->max_vfs = pci_dev->max_vfs;
3183         if (hw->mac.type == ixgbe_mac_82598EB)
3184                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3185         else
3186                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3187         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3188         dev_info->rx_offload_capa =
3189                 DEV_RX_OFFLOAD_VLAN_STRIP |
3190                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3191                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3192                 DEV_RX_OFFLOAD_TCP_CKSUM;
3193
3194         /*
3195          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3196          * mode.
3197          */
3198         if ((hw->mac.type == ixgbe_mac_82599EB ||
3199              hw->mac.type == ixgbe_mac_X540) &&
3200             !RTE_ETH_DEV_SRIOV(dev).active)
3201                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3202
3203         if (hw->mac.type == ixgbe_mac_82599EB ||
3204             hw->mac.type == ixgbe_mac_X540)
3205                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3206
3207         if (hw->mac.type == ixgbe_mac_X550 ||
3208             hw->mac.type == ixgbe_mac_X550EM_x ||
3209             hw->mac.type == ixgbe_mac_X550EM_a)
3210                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3211
3212         dev_info->tx_offload_capa =
3213                 DEV_TX_OFFLOAD_VLAN_INSERT |
3214                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3215                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3216                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3217                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3218                 DEV_TX_OFFLOAD_TCP_TSO;
3219
3220         if (hw->mac.type == ixgbe_mac_82599EB ||
3221             hw->mac.type == ixgbe_mac_X540)
3222                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3223
3224         if (hw->mac.type == ixgbe_mac_X550 ||
3225             hw->mac.type == ixgbe_mac_X550EM_x ||
3226             hw->mac.type == ixgbe_mac_X550EM_a)
3227                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3228
3229         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3230                 .rx_thresh = {
3231                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3232                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3233                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3234                 },
3235                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3236                 .rx_drop_en = 0,
3237         };
3238
3239         dev_info->default_txconf = (struct rte_eth_txconf) {
3240                 .tx_thresh = {
3241                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3242                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3243                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3244                 },
3245                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3246                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3247                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3248                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3249         };
3250
3251         dev_info->rx_desc_lim = rx_desc_lim;
3252         dev_info->tx_desc_lim = tx_desc_lim;
3253
3254         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3255         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3256         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3257
3258         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3259         if (hw->mac.type == ixgbe_mac_X540 ||
3260             hw->mac.type == ixgbe_mac_X540_vf ||
3261             hw->mac.type == ixgbe_mac_X550 ||
3262             hw->mac.type == ixgbe_mac_X550_vf) {
3263                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3264         }
3265 }
3266
3267 static const uint32_t *
3268 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3269 {
3270         static const uint32_t ptypes[] = {
3271                 /* For non-vec functions,
3272                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3273                  * for vec functions,
3274                  * refers to _recv_raw_pkts_vec().
3275                  */
3276                 RTE_PTYPE_L2_ETHER,
3277                 RTE_PTYPE_L3_IPV4,
3278                 RTE_PTYPE_L3_IPV4_EXT,
3279                 RTE_PTYPE_L3_IPV6,
3280                 RTE_PTYPE_L3_IPV6_EXT,
3281                 RTE_PTYPE_L4_SCTP,
3282                 RTE_PTYPE_L4_TCP,
3283                 RTE_PTYPE_L4_UDP,
3284                 RTE_PTYPE_TUNNEL_IP,
3285                 RTE_PTYPE_INNER_L3_IPV6,
3286                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3287                 RTE_PTYPE_INNER_L4_TCP,
3288                 RTE_PTYPE_INNER_L4_UDP,
3289                 RTE_PTYPE_UNKNOWN
3290         };
3291
3292         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3293             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3294             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3295             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3296                 return ptypes;
3297         return NULL;
3298 }
3299
3300 static void
3301 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3302                      struct rte_eth_dev_info *dev_info)
3303 {
3304         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3305         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3306
3307         dev_info->pci_dev = pci_dev;
3308         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3309         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3310         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3311         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3312         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3313         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3314         dev_info->max_vfs = pci_dev->max_vfs;
3315         if (hw->mac.type == ixgbe_mac_82598EB)
3316                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3317         else
3318                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3319         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3320                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3321                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3322                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3323         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3324                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3325                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3326                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3327                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3328                                 DEV_TX_OFFLOAD_TCP_TSO;
3329
3330         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3331                 .rx_thresh = {
3332                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3333                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3334                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3335                 },
3336                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3337                 .rx_drop_en = 0,
3338         };
3339
3340         dev_info->default_txconf = (struct rte_eth_txconf) {
3341                 .tx_thresh = {
3342                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3343                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3344                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3345                 },
3346                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3347                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3348                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3349                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3350         };
3351
3352         dev_info->rx_desc_lim = rx_desc_lim;
3353         dev_info->tx_desc_lim = tx_desc_lim;
3354 }
3355
3356 /* return 0 means link status changed, -1 means not changed */
3357 static int
3358 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3359 {
3360         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361         struct rte_eth_link link, old;
3362         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3363         int link_up;
3364         int diag;
3365
3366         link.link_status = ETH_LINK_DOWN;
3367         link.link_speed = 0;
3368         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3369         memset(&old, 0, sizeof(old));
3370         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3371
3372         hw->mac.get_link_status = true;
3373
3374         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3375         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3376                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3377         else
3378                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3379
3380         if (diag != 0) {
3381                 link.link_speed = ETH_SPEED_NUM_100M;
3382                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3383                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3384                 if (link.link_status == old.link_status)
3385                         return -1;
3386                 return 0;
3387         }
3388
3389         if (link_up == 0) {
3390                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3391                 if (link.link_status == old.link_status)
3392                         return -1;
3393                 return 0;
3394         }
3395         link.link_status = ETH_LINK_UP;
3396         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3397
3398         switch (link_speed) {
3399         default:
3400         case IXGBE_LINK_SPEED_UNKNOWN:
3401                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3402                 link.link_speed = ETH_SPEED_NUM_100M;
3403                 break;
3404
3405         case IXGBE_LINK_SPEED_100_FULL:
3406                 link.link_speed = ETH_SPEED_NUM_100M;
3407                 break;
3408
3409         case IXGBE_LINK_SPEED_1GB_FULL:
3410                 link.link_speed = ETH_SPEED_NUM_1G;
3411                 break;
3412
3413         case IXGBE_LINK_SPEED_10GB_FULL:
3414                 link.link_speed = ETH_SPEED_NUM_10G;
3415                 break;
3416         }
3417         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3418
3419         if (link.link_status == old.link_status)
3420                 return -1;
3421
3422         return 0;
3423 }
3424
3425 static void
3426 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3427 {
3428         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3429         uint32_t fctrl;
3430
3431         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3432         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3433         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3434 }
3435
3436 static void
3437 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3438 {
3439         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3440         uint32_t fctrl;
3441
3442         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3443         fctrl &= (~IXGBE_FCTRL_UPE);
3444         if (dev->data->all_multicast == 1)
3445                 fctrl |= IXGBE_FCTRL_MPE;
3446         else
3447                 fctrl &= (~IXGBE_FCTRL_MPE);
3448         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3449 }
3450
3451 static void
3452 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3453 {
3454         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3455         uint32_t fctrl;
3456
3457         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3458         fctrl |= IXGBE_FCTRL_MPE;
3459         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3460 }
3461
3462 static void
3463 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3464 {
3465         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3466         uint32_t fctrl;
3467
3468         if (dev->data->promiscuous == 1)
3469                 return; /* must remain in all_multicast mode */
3470
3471         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3472         fctrl &= (~IXGBE_FCTRL_MPE);
3473         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3474 }
3475
3476 /**
3477  * It clears the interrupt causes and enables the interrupt.
3478  * It will be called once only during nic initialized.
3479  *
3480  * @param dev
3481  *  Pointer to struct rte_eth_dev.
3482  *
3483  * @return
3484  *  - On success, zero.
3485  *  - On failure, a negative value.
3486  */
3487 static int
3488 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3489 {
3490         struct ixgbe_interrupt *intr =
3491                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3492
3493         ixgbe_dev_link_status_print(dev);
3494         intr->mask |= IXGBE_EICR_LSC;
3495
3496         return 0;
3497 }
3498
3499 /**
3500  * It clears the interrupt causes and enables the interrupt.
3501  * It will be called once only during nic initialized.
3502  *
3503  * @param dev
3504  *  Pointer to struct rte_eth_dev.
3505  *
3506  * @return
3507  *  - On success, zero.
3508  *  - On failure, a negative value.
3509  */
3510 static int
3511 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3512 {
3513         struct ixgbe_interrupt *intr =
3514                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3515
3516         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3517
3518         return 0;
3519 }
3520
3521 /**
3522  * It clears the interrupt causes and enables the interrupt.
3523  * It will be called once only during nic initialized.
3524  *
3525  * @param dev
3526  *  Pointer to struct rte_eth_dev.
3527  *
3528  * @return
3529  *  - On success, zero.
3530  *  - On failure, a negative value.
3531  */
3532 static int
3533 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3534 {
3535         struct ixgbe_interrupt *intr =
3536                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3537
3538         intr->mask |= IXGBE_EICR_LINKSEC;
3539
3540         return 0;
3541 }
3542
3543 /*
3544  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3545  *
3546  * @param dev
3547  *  Pointer to struct rte_eth_dev.
3548  *
3549  * @return
3550  *  - On success, zero.
3551  *  - On failure, a negative value.
3552  */
3553 static int
3554 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3555 {
3556         uint32_t eicr;
3557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3558         struct ixgbe_interrupt *intr =
3559                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3560
3561         /* clear all cause mask */
3562         ixgbe_disable_intr(hw);
3563
3564         /* read-on-clear nic registers here */
3565         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3566         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3567
3568         intr->flags = 0;
3569
3570         /* set flag for async link update */
3571         if (eicr & IXGBE_EICR_LSC)
3572                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3573
3574         if (eicr & IXGBE_EICR_MAILBOX)
3575                 intr->flags |= IXGBE_FLAG_MAILBOX;
3576
3577         if (eicr & IXGBE_EICR_LINKSEC)
3578                 intr->flags |= IXGBE_FLAG_MACSEC;
3579
3580         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3581             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3582             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3583                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3584
3585         return 0;
3586 }
3587
3588 /**
3589  * It gets and then prints the link status.
3590  *
3591  * @param dev
3592  *  Pointer to struct rte_eth_dev.
3593  *
3594  * @return
3595  *  - On success, zero.
3596  *  - On failure, a negative value.
3597  */
3598 static void
3599 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3600 {
3601         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3602         struct rte_eth_link link;
3603
3604         memset(&link, 0, sizeof(link));
3605         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3606         if (link.link_status) {
3607                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3608                                         (int)(dev->data->port_id),
3609                                         (unsigned)link.link_speed,
3610                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3611                                         "full-duplex" : "half-duplex");
3612         } else {
3613                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3614                                 (int)(dev->data->port_id));
3615         }
3616         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3617                                 pci_dev->addr.domain,
3618                                 pci_dev->addr.bus,
3619                                 pci_dev->addr.devid,
3620                                 pci_dev->addr.function);
3621 }
3622
3623 /*
3624  * It executes link_update after knowing an interrupt occurred.
3625  *
3626  * @param dev
3627  *  Pointer to struct rte_eth_dev.
3628  *
3629  * @return
3630  *  - On success, zero.
3631  *  - On failure, a negative value.
3632  */
3633 static int
3634 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3635                            struct rte_intr_handle *intr_handle)
3636 {
3637         struct ixgbe_interrupt *intr =
3638                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3639         int64_t timeout;
3640         struct rte_eth_link link;
3641         int intr_enable_delay = false;
3642         struct ixgbe_hw *hw =
3643                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3644
3645         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3646
3647         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3648                 ixgbe_pf_mbx_process(dev);
3649                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3650         }
3651
3652         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3653                 ixgbe_handle_lasi(hw);
3654                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3655         }
3656
3657         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3658                 /* get the link status before link update, for predicting later */
3659                 memset(&link, 0, sizeof(link));
3660                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3661
3662                 ixgbe_dev_link_update(dev, 0);
3663
3664                 /* likely to up */
3665                 if (!link.link_status)
3666                         /* handle it 1 sec later, wait it being stable */
3667                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3668                 /* likely to down */
3669                 else
3670                         /* handle it 4 sec later, wait it being stable */
3671                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3672
3673                 ixgbe_dev_link_status_print(dev);
3674
3675                 intr_enable_delay = true;
3676         }
3677
3678         if (intr_enable_delay) {
3679                 if (rte_eal_alarm_set(timeout * 1000,
3680                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3681                         PMD_DRV_LOG(ERR, "Error setting alarm");
3682         } else {
3683                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3684                 ixgbe_enable_intr(dev);
3685                 rte_intr_enable(intr_handle);
3686         }
3687
3688
3689         return 0;
3690 }
3691
3692 /**
3693  * Interrupt handler which shall be registered for alarm callback for delayed
3694  * handling specific interrupt to wait for the stable nic state. As the
3695  * NIC interrupt state is not stable for ixgbe after link is just down,
3696  * it needs to wait 4 seconds to get the stable status.
3697  *
3698  * @param handle
3699  *  Pointer to interrupt handle.
3700  * @param param
3701  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3702  *
3703  * @return
3704  *  void
3705  */
3706 static void
3707 ixgbe_dev_interrupt_delayed_handler(void *param)
3708 {
3709         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3710         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3711         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3712         struct ixgbe_interrupt *intr =
3713                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3714         struct ixgbe_hw *hw =
3715                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716         uint32_t eicr;
3717
3718         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3719         if (eicr & IXGBE_EICR_MAILBOX)
3720                 ixgbe_pf_mbx_process(dev);
3721
3722         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3723                 ixgbe_handle_lasi(hw);
3724                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3725         }
3726
3727         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3728                 ixgbe_dev_link_update(dev, 0);
3729                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3730                 ixgbe_dev_link_status_print(dev);
3731                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3732         }
3733
3734         if (intr->flags & IXGBE_FLAG_MACSEC) {
3735                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3736                                               NULL);
3737                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3738         }
3739
3740         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3741         ixgbe_enable_intr(dev);
3742         rte_intr_enable(intr_handle);
3743 }
3744
3745 /**
3746  * Interrupt handler triggered by NIC  for handling
3747  * specific interrupt.
3748  *
3749  * @param handle
3750  *  Pointer to interrupt handle.
3751  * @param param
3752  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3753  *
3754  * @return
3755  *  void
3756  */
3757 static void
3758 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3759                             void *param)
3760 {
3761         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3762
3763         ixgbe_dev_interrupt_get_status(dev);
3764         ixgbe_dev_interrupt_action(dev, handle);
3765 }
3766
3767 static int
3768 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3769 {
3770         struct ixgbe_hw *hw;
3771
3772         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3773         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3774 }
3775
3776 static int
3777 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3778 {
3779         struct ixgbe_hw *hw;
3780
3781         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3783 }
3784
3785 static int
3786 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3787 {
3788         struct ixgbe_hw *hw;
3789         uint32_t mflcn_reg;
3790         uint32_t fccfg_reg;
3791         int rx_pause;
3792         int tx_pause;
3793
3794         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3795
3796         fc_conf->pause_time = hw->fc.pause_time;
3797         fc_conf->high_water = hw->fc.high_water[0];
3798         fc_conf->low_water = hw->fc.low_water[0];
3799         fc_conf->send_xon = hw->fc.send_xon;
3800         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3801
3802         /*
3803          * Return rx_pause status according to actual setting of
3804          * MFLCN register.
3805          */
3806         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3807         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3808                 rx_pause = 1;
3809         else
3810                 rx_pause = 0;
3811
3812         /*
3813          * Return tx_pause status according to actual setting of
3814          * FCCFG register.
3815          */
3816         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3817         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3818                 tx_pause = 1;
3819         else
3820                 tx_pause = 0;
3821
3822         if (rx_pause && tx_pause)
3823                 fc_conf->mode = RTE_FC_FULL;
3824         else if (rx_pause)
3825                 fc_conf->mode = RTE_FC_RX_PAUSE;
3826         else if (tx_pause)
3827                 fc_conf->mode = RTE_FC_TX_PAUSE;
3828         else
3829                 fc_conf->mode = RTE_FC_NONE;
3830
3831         return 0;
3832 }
3833
3834 static int
3835 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3836 {
3837         struct ixgbe_hw *hw;
3838         int err;
3839         uint32_t rx_buf_size;
3840         uint32_t max_high_water;
3841         uint32_t mflcn;
3842         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3843                 ixgbe_fc_none,
3844                 ixgbe_fc_rx_pause,
3845                 ixgbe_fc_tx_pause,
3846                 ixgbe_fc_full
3847         };
3848
3849         PMD_INIT_FUNC_TRACE();
3850
3851         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3852         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3853         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3854
3855         /*
3856          * At least reserve one Ethernet frame for watermark
3857          * high_water/low_water in kilo bytes for ixgbe
3858          */
3859         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3860         if ((fc_conf->high_water > max_high_water) ||
3861                 (fc_conf->high_water < fc_conf->low_water)) {
3862                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3863                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3864                 return -EINVAL;
3865         }
3866
3867         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3868         hw->fc.pause_time     = fc_conf->pause_time;
3869         hw->fc.high_water[0]  = fc_conf->high_water;
3870         hw->fc.low_water[0]   = fc_conf->low_water;
3871         hw->fc.send_xon       = fc_conf->send_xon;
3872         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3873
3874         err = ixgbe_fc_enable(hw);
3875
3876         /* Not negotiated is not an error case */
3877         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3878
3879                 /* check if we want to forward MAC frames - driver doesn't have native
3880                  * capability to do that, so we'll write the registers ourselves */
3881
3882                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3883
3884                 /* set or clear MFLCN.PMCF bit depending on configuration */
3885                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3886                         mflcn |= IXGBE_MFLCN_PMCF;
3887                 else
3888                         mflcn &= ~IXGBE_MFLCN_PMCF;
3889
3890                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3891                 IXGBE_WRITE_FLUSH(hw);
3892
3893                 return 0;
3894         }
3895
3896         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3897         return -EIO;
3898 }
3899
3900 /**
3901  *  ixgbe_pfc_enable_generic - Enable flow control
3902  *  @hw: pointer to hardware structure
3903  *  @tc_num: traffic class number
3904  *  Enable flow control according to the current settings.
3905  */
3906 static int
3907 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3908 {
3909         int ret_val = 0;
3910         uint32_t mflcn_reg, fccfg_reg;
3911         uint32_t reg;
3912         uint32_t fcrtl, fcrth;
3913         uint8_t i;
3914         uint8_t nb_rx_en;
3915
3916         /* Validate the water mark configuration */
3917         if (!hw->fc.pause_time) {
3918                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3919                 goto out;
3920         }
3921
3922         /* Low water mark of zero causes XOFF floods */
3923         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3924                  /* High/Low water can not be 0 */
3925                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3926                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3927                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3928                         goto out;
3929                 }
3930
3931                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3932                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3933                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3934                         goto out;
3935                 }
3936         }
3937         /* Negotiate the fc mode to use */
3938         ixgbe_fc_autoneg(hw);
3939
3940         /* Disable any previous flow control settings */
3941         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3942         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3943
3944         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3945         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3946
3947         switch (hw->fc.current_mode) {
3948         case ixgbe_fc_none:
3949                 /*
3950                  * If the count of enabled RX Priority Flow control >1,
3951                  * and the TX pause can not be disabled
3952                  */
3953                 nb_rx_en = 0;
3954                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3955                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3956                         if (reg & IXGBE_FCRTH_FCEN)
3957                                 nb_rx_en++;
3958                 }
3959                 if (nb_rx_en > 1)
3960                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3961                 break;
3962         case ixgbe_fc_rx_pause:
3963                 /*
3964                  * Rx Flow control is enabled and Tx Flow control is
3965                  * disabled by software override. Since there really
3966                  * isn't a way to advertise that we are capable of RX
3967                  * Pause ONLY, we will advertise that we support both
3968                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3969                  * disable the adapter's ability to send PAUSE frames.
3970                  */
3971                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3972                 /*
3973                  * If the count of enabled RX Priority Flow control >1,
3974                  * and the TX pause can not be disabled
3975                  */
3976                 nb_rx_en = 0;
3977                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3978                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3979                         if (reg & IXGBE_FCRTH_FCEN)
3980                                 nb_rx_en++;
3981                 }
3982                 if (nb_rx_en > 1)
3983                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3984                 break;
3985         case ixgbe_fc_tx_pause:
3986                 /*
3987                  * Tx Flow control is enabled, and Rx Flow control is
3988                  * disabled by software override.
3989                  */
3990                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3991                 break;
3992         case ixgbe_fc_full:
3993                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3994                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3995                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3996                 break;
3997         default:
3998                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3999                 ret_val = IXGBE_ERR_CONFIG;
4000                 goto out;
4001         }
4002
4003         /* Set 802.3x based flow control settings. */
4004         mflcn_reg |= IXGBE_MFLCN_DPF;
4005         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4006         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4007
4008         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4009         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4010                 hw->fc.high_water[tc_num]) {
4011                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4012                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4013                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4014         } else {
4015                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4016                 /*
4017                  * In order to prevent Tx hangs when the internal Tx
4018                  * switch is enabled we must set the high water mark
4019                  * to the maximum FCRTH value.  This allows the Tx
4020                  * switch to function even under heavy Rx workloads.
4021                  */
4022                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4023         }
4024         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4025
4026         /* Configure pause time (2 TCs per register) */
4027         reg = hw->fc.pause_time * 0x00010001;
4028         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4029                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4030
4031         /* Configure flow control refresh threshold value */
4032         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4033
4034 out:
4035         return ret_val;
4036 }
4037
4038 static int
4039 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4040 {
4041         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4042         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4043
4044         if (hw->mac.type != ixgbe_mac_82598EB) {
4045                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4046         }
4047         return ret_val;
4048 }
4049
4050 static int
4051 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4052 {
4053         int err;
4054         uint32_t rx_buf_size;
4055         uint32_t max_high_water;
4056         uint8_t tc_num;
4057         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4058         struct ixgbe_hw *hw =
4059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4060         struct ixgbe_dcb_config *dcb_config =
4061                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4062
4063         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4064                 ixgbe_fc_none,
4065                 ixgbe_fc_rx_pause,
4066                 ixgbe_fc_tx_pause,
4067                 ixgbe_fc_full
4068         };
4069
4070         PMD_INIT_FUNC_TRACE();
4071
4072         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4073         tc_num = map[pfc_conf->priority];
4074         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4075         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4076         /*
4077          * At least reserve one Ethernet frame for watermark
4078          * high_water/low_water in kilo bytes for ixgbe
4079          */
4080         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4081         if ((pfc_conf->fc.high_water > max_high_water) ||
4082             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4083                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4084                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4085                 return -EINVAL;
4086         }
4087
4088         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4089         hw->fc.pause_time = pfc_conf->fc.pause_time;
4090         hw->fc.send_xon = pfc_conf->fc.send_xon;
4091         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4092         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4093
4094         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4095
4096         /* Not negotiated is not an error case */
4097         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4098                 return 0;
4099
4100         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4101         return -EIO;
4102 }
4103
4104 static int
4105 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4106                           struct rte_eth_rss_reta_entry64 *reta_conf,
4107                           uint16_t reta_size)
4108 {
4109         uint16_t i, sp_reta_size;
4110         uint8_t j, mask;
4111         uint32_t reta, r;
4112         uint16_t idx, shift;
4113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114         uint32_t reta_reg;
4115
4116         PMD_INIT_FUNC_TRACE();
4117
4118         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4119                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4120                         "NIC.");
4121                 return -ENOTSUP;
4122         }
4123
4124         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4125         if (reta_size != sp_reta_size) {
4126                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4127                         "(%d) doesn't match the number hardware can supported "
4128                         "(%d)\n", reta_size, sp_reta_size);
4129                 return -EINVAL;
4130         }
4131
4132         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4133                 idx = i / RTE_RETA_GROUP_SIZE;
4134                 shift = i % RTE_RETA_GROUP_SIZE;
4135                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4136                                                 IXGBE_4_BIT_MASK);
4137                 if (!mask)
4138                         continue;
4139                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4140                 if (mask == IXGBE_4_BIT_MASK)
4141                         r = 0;
4142                 else
4143                         r = IXGBE_READ_REG(hw, reta_reg);
4144                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4145                         if (mask & (0x1 << j))
4146                                 reta |= reta_conf[idx].reta[shift + j] <<
4147                                                         (CHAR_BIT * j);
4148                         else
4149                                 reta |= r & (IXGBE_8_BIT_MASK <<
4150                                                 (CHAR_BIT * j));
4151                 }
4152                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4153         }
4154
4155         return 0;
4156 }
4157
4158 static int
4159 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4160                          struct rte_eth_rss_reta_entry64 *reta_conf,
4161                          uint16_t reta_size)
4162 {
4163         uint16_t i, sp_reta_size;
4164         uint8_t j, mask;
4165         uint32_t reta;
4166         uint16_t idx, shift;
4167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4168         uint32_t reta_reg;
4169
4170         PMD_INIT_FUNC_TRACE();
4171         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4172         if (reta_size != sp_reta_size) {
4173                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4174                         "(%d) doesn't match the number hardware can supported "
4175                         "(%d)\n", reta_size, sp_reta_size);
4176                 return -EINVAL;
4177         }
4178
4179         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4180                 idx = i / RTE_RETA_GROUP_SIZE;
4181                 shift = i % RTE_RETA_GROUP_SIZE;
4182                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4183                                                 IXGBE_4_BIT_MASK);
4184                 if (!mask)
4185                         continue;
4186
4187                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4188                 reta = IXGBE_READ_REG(hw, reta_reg);
4189                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4190                         if (mask & (0x1 << j))
4191                                 reta_conf[idx].reta[shift + j] =
4192                                         ((reta >> (CHAR_BIT * j)) &
4193                                                 IXGBE_8_BIT_MASK);
4194                 }
4195         }
4196
4197         return 0;
4198 }
4199
4200 static void
4201 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4202                                 uint32_t index, uint32_t pool)
4203 {
4204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4205         uint32_t enable_addr = 1;
4206
4207         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4208 }
4209
4210 static void
4211 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4212 {
4213         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4214
4215         ixgbe_clear_rar(hw, index);
4216 }
4217
4218 static void
4219 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4220 {
4221         ixgbe_remove_rar(dev, 0);
4222
4223         ixgbe_add_rar(dev, addr, 0, 0);
4224 }
4225
4226 int
4227 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4228                 struct ether_addr *mac_addr)
4229 {
4230         struct ixgbe_hw *hw;
4231         struct ixgbe_vf_info *vfinfo;
4232         int rar_entry;
4233         uint8_t *new_mac = (uint8_t *)(mac_addr);
4234         struct rte_eth_dev *dev;
4235         struct rte_eth_dev_info dev_info;
4236
4237         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4238
4239         dev = &rte_eth_devices[port];
4240         rte_eth_dev_info_get(port, &dev_info);
4241
4242         if (vf >= dev_info.max_vfs)
4243                 return -EINVAL;
4244
4245         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4246         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4247         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4248
4249         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4250                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4251                                 ETHER_ADDR_LEN);
4252                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4253                                 IXGBE_RAH_AV);
4254         }
4255         return -EINVAL;
4256 }
4257
4258 static int
4259 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4260 {
4261         uint32_t hlreg0;
4262         uint32_t maxfrs;
4263         struct ixgbe_hw *hw;
4264         struct rte_eth_dev_info dev_info;
4265         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4266
4267         ixgbe_dev_info_get(dev, &dev_info);
4268
4269         /* check that mtu is within the allowed range */
4270         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4271                 return -EINVAL;
4272
4273         /* refuse mtu that requires the support of scattered packets when this
4274          * feature has not been enabled before.
4275          */
4276         if (!dev->data->scattered_rx &&
4277             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4278              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4279                 return -EINVAL;
4280
4281         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4283
4284         /* switch to jumbo mode if needed */
4285         if (frame_size > ETHER_MAX_LEN) {
4286                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4287                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4288         } else {
4289                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4290                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4291         }
4292         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4293
4294         /* update max frame size */
4295         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4296
4297         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4298         maxfrs &= 0x0000FFFF;
4299         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4300         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4301
4302         return 0;
4303 }
4304
4305 /*
4306  * Virtual Function operations
4307  */
4308 static void
4309 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4310 {
4311         PMD_INIT_FUNC_TRACE();
4312
4313         /* Clear interrupt mask to stop from interrupts being generated */
4314         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4315
4316         IXGBE_WRITE_FLUSH(hw);
4317 }
4318
4319 static void
4320 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4321 {
4322         PMD_INIT_FUNC_TRACE();
4323
4324         /* VF enable interrupt autoclean */
4325         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4326         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4327         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4328
4329         IXGBE_WRITE_FLUSH(hw);
4330 }
4331
4332 static int
4333 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4334 {
4335         struct rte_eth_conf *conf = &dev->data->dev_conf;
4336         struct ixgbe_adapter *adapter =
4337                         (struct ixgbe_adapter *)dev->data->dev_private;
4338
4339         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4340                      dev->data->port_id);
4341
4342         /*
4343          * VF has no ability to enable/disable HW CRC
4344          * Keep the persistent behavior the same as Host PF
4345          */
4346 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4347         if (!conf->rxmode.hw_strip_crc) {
4348                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4349                 conf->rxmode.hw_strip_crc = 1;
4350         }
4351 #else
4352         if (conf->rxmode.hw_strip_crc) {
4353                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4354                 conf->rxmode.hw_strip_crc = 0;
4355         }
4356 #endif
4357
4358         /*
4359          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4360          * allocation or vector Rx preconditions we will reset it.
4361          */
4362         adapter->rx_bulk_alloc_allowed = true;
4363         adapter->rx_vec_allowed = true;
4364
4365         return 0;
4366 }
4367
4368 static int
4369 ixgbevf_dev_start(struct rte_eth_dev *dev)
4370 {
4371         struct ixgbe_hw *hw =
4372                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4373         uint32_t intr_vector = 0;
4374         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4375         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4376
4377         int err, mask = 0;
4378
4379         PMD_INIT_FUNC_TRACE();
4380
4381         hw->mac.ops.reset_hw(hw);
4382         hw->mac.get_link_status = true;
4383
4384         /* negotiate mailbox API version to use with the PF. */
4385         ixgbevf_negotiate_api(hw);
4386
4387         ixgbevf_dev_tx_init(dev);
4388
4389         /* This can fail when allocating mbufs for descriptor rings */
4390         err = ixgbevf_dev_rx_init(dev);
4391         if (err) {
4392                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4393                 ixgbe_dev_clear_queues(dev);
4394                 return err;
4395         }
4396
4397         /* Set vfta */
4398         ixgbevf_set_vfta_all(dev, 1);
4399
4400         /* Set HW strip */
4401         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4402                 ETH_VLAN_EXTEND_MASK;
4403         ixgbevf_vlan_offload_set(dev, mask);
4404
4405         ixgbevf_dev_rxtx_start(dev);
4406
4407         /* check and configure queue intr-vector mapping */
4408         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4409                 intr_vector = dev->data->nb_rx_queues;
4410                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4411                         return -1;
4412         }
4413
4414         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4415                 intr_handle->intr_vec =
4416                         rte_zmalloc("intr_vec",
4417                                     dev->data->nb_rx_queues * sizeof(int), 0);
4418                 if (intr_handle->intr_vec == NULL) {
4419                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4420                                      " intr_vec\n", dev->data->nb_rx_queues);
4421                         return -ENOMEM;
4422                 }
4423         }
4424         ixgbevf_configure_msix(dev);
4425
4426         rte_intr_enable(intr_handle);
4427
4428         /* Re-enable interrupt for VF */
4429         ixgbevf_intr_enable(hw);
4430
4431         return 0;
4432 }
4433
4434 static void
4435 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4436 {
4437         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4438         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4439         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4440
4441         PMD_INIT_FUNC_TRACE();
4442
4443         ixgbevf_intr_disable(hw);
4444
4445         hw->adapter_stopped = 1;
4446         ixgbe_stop_adapter(hw);
4447
4448         /*
4449           * Clear what we set, but we still keep shadow_vfta to
4450           * restore after device starts
4451           */
4452         ixgbevf_set_vfta_all(dev, 0);
4453
4454         /* Clear stored conf */
4455         dev->data->scattered_rx = 0;
4456
4457         ixgbe_dev_clear_queues(dev);
4458
4459         /* Clean datapath event and queue/vec mapping */
4460         rte_intr_efd_disable(intr_handle);
4461         if (intr_handle->intr_vec != NULL) {
4462                 rte_free(intr_handle->intr_vec);
4463                 intr_handle->intr_vec = NULL;
4464         }
4465 }
4466
4467 static void
4468 ixgbevf_dev_close(struct rte_eth_dev *dev)
4469 {
4470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4471
4472         PMD_INIT_FUNC_TRACE();
4473
4474         ixgbe_reset_hw(hw);
4475
4476         ixgbevf_dev_stop(dev);
4477
4478         ixgbe_dev_free_queues(dev);
4479
4480         /**
4481          * Remove the VF MAC address ro ensure
4482          * that the VF traffic goes to the PF
4483          * after stop, close and detach of the VF
4484          **/
4485         ixgbevf_remove_mac_addr(dev, 0);
4486 }
4487
4488 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4489 {
4490         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4491         struct ixgbe_vfta *shadow_vfta =
4492                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4493         int i = 0, j = 0, vfta = 0, mask = 1;
4494
4495         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4496                 vfta = shadow_vfta->vfta[i];
4497                 if (vfta) {
4498                         mask = 1;
4499                         for (j = 0; j < 32; j++) {
4500                                 if (vfta & mask)
4501                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4502                                                        on, false);
4503                                 mask <<= 1;
4504                         }
4505                 }
4506         }
4507
4508 }
4509
4510 static int
4511 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4512 {
4513         struct ixgbe_hw *hw =
4514                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4515         struct ixgbe_vfta *shadow_vfta =
4516                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4517         uint32_t vid_idx = 0;
4518         uint32_t vid_bit = 0;
4519         int ret = 0;
4520
4521         PMD_INIT_FUNC_TRACE();
4522
4523         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4524         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4525         if (ret) {
4526                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4527                 return ret;
4528         }
4529         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4530         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4531
4532         /* Save what we set and retore it after device reset */
4533         if (on)
4534                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4535         else
4536                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4537
4538         return 0;
4539 }
4540
4541 static void
4542 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4543 {
4544         struct ixgbe_hw *hw =
4545                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4546         uint32_t ctrl;
4547
4548         PMD_INIT_FUNC_TRACE();
4549
4550         if (queue >= hw->mac.max_rx_queues)
4551                 return;
4552
4553         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4554         if (on)
4555                 ctrl |= IXGBE_RXDCTL_VME;
4556         else
4557                 ctrl &= ~IXGBE_RXDCTL_VME;
4558         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4559
4560         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4561 }
4562
4563 static void
4564 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4565 {
4566         struct ixgbe_hw *hw =
4567                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4568         uint16_t i;
4569         int on = 0;
4570
4571         /* VF function only support hw strip feature, others are not support */
4572         if (mask & ETH_VLAN_STRIP_MASK) {
4573                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4574
4575                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4576                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4577         }
4578 }
4579
4580 static int
4581 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4582 {
4583         uint32_t reg_val;
4584
4585         /* we only need to do this if VMDq is enabled */
4586         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4587         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4588                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4589                 return -1;
4590         }
4591
4592         return 0;
4593 }
4594
4595 static uint32_t
4596 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4597 {
4598         uint32_t vector = 0;
4599
4600         switch (hw->mac.mc_filter_type) {
4601         case 0:   /* use bits [47:36] of the address */
4602                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4603                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4604                 break;
4605         case 1:   /* use bits [46:35] of the address */
4606                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4607                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4608                 break;
4609         case 2:   /* use bits [45:34] of the address */
4610                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4611                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4612                 break;
4613         case 3:   /* use bits [43:32] of the address */
4614                 vector = ((uc_addr->addr_bytes[4]) |
4615                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4616                 break;
4617         default:  /* Invalid mc_filter_type */
4618                 break;
4619         }
4620
4621         /* vector can only be 12-bits or boundary will be exceeded */
4622         vector &= 0xFFF;
4623         return vector;
4624 }
4625
4626 static int
4627 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4628                         uint8_t on)
4629 {
4630         uint32_t vector;
4631         uint32_t uta_idx;
4632         uint32_t reg_val;
4633         uint32_t uta_shift;
4634         uint32_t rc;
4635         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4636         const uint32_t ixgbe_uta_bit_shift = 5;
4637         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4638         const uint32_t bit1 = 0x1;
4639
4640         struct ixgbe_hw *hw =
4641                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4642         struct ixgbe_uta_info *uta_info =
4643                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4644
4645         /* The UTA table only exists on 82599 hardware and newer */
4646         if (hw->mac.type < ixgbe_mac_82599EB)
4647                 return -ENOTSUP;
4648
4649         vector = ixgbe_uta_vector(hw, mac_addr);
4650         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4651         uta_shift = vector & ixgbe_uta_bit_mask;
4652
4653         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4654         if (rc == on)
4655                 return 0;
4656
4657         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4658         if (on) {
4659                 uta_info->uta_in_use++;
4660                 reg_val |= (bit1 << uta_shift);
4661                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4662         } else {
4663                 uta_info->uta_in_use--;
4664                 reg_val &= ~(bit1 << uta_shift);
4665                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4666         }
4667
4668         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4669
4670         if (uta_info->uta_in_use > 0)
4671                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4672                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4673         else
4674                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4675
4676         return 0;
4677 }
4678
4679 static int
4680 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4681 {
4682         int i;
4683         struct ixgbe_hw *hw =
4684                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685         struct ixgbe_uta_info *uta_info =
4686                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4687
4688         /* The UTA table only exists on 82599 hardware and newer */
4689         if (hw->mac.type < ixgbe_mac_82599EB)
4690                 return -ENOTSUP;
4691
4692         if (on) {
4693                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4694                         uta_info->uta_shadow[i] = ~0;
4695                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4696                 }
4697         } else {
4698                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4699                         uta_info->uta_shadow[i] = 0;
4700                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4701                 }
4702         }
4703         return 0;
4704
4705 }
4706
4707 uint32_t
4708 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4709 {
4710         uint32_t new_val = orig_val;
4711
4712         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4713                 new_val |= IXGBE_VMOLR_AUPE;
4714         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4715                 new_val |= IXGBE_VMOLR_ROMPE;
4716         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4717                 new_val |= IXGBE_VMOLR_ROPE;
4718         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4719                 new_val |= IXGBE_VMOLR_BAM;
4720         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4721                 new_val |= IXGBE_VMOLR_MPE;
4722
4723         return new_val;
4724 }
4725
4726
4727 int
4728 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4729 {
4730         struct ixgbe_hw *hw;
4731         struct ixgbe_mac_info *mac;
4732         struct rte_eth_dev *dev;
4733         struct rte_eth_dev_info dev_info;
4734
4735         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4736
4737         dev = &rte_eth_devices[port];
4738         rte_eth_dev_info_get(port, &dev_info);
4739
4740         if (vf >= dev_info.max_vfs)
4741                 return -EINVAL;
4742
4743         if (on > 1)
4744                 return -EINVAL;
4745
4746         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4747         mac = &hw->mac;
4748
4749         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4750
4751         return 0;
4752 }
4753
4754 int
4755 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4756 {
4757         struct ixgbe_hw *hw;
4758         struct ixgbe_mac_info *mac;
4759         struct rte_eth_dev *dev;
4760         struct rte_eth_dev_info dev_info;
4761
4762         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4763
4764         dev = &rte_eth_devices[port];
4765         rte_eth_dev_info_get(port, &dev_info);
4766
4767         if (vf >= dev_info.max_vfs)
4768                 return -EINVAL;
4769
4770         if (on > 1)
4771                 return -EINVAL;
4772
4773         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4774         mac = &hw->mac;
4775         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4776
4777         return 0;
4778 }
4779
4780 int
4781 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4782 {
4783         struct ixgbe_hw *hw;
4784         uint32_t ctrl;
4785         struct rte_eth_dev *dev;
4786         struct rte_eth_dev_info dev_info;
4787
4788         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4789
4790         dev = &rte_eth_devices[port];
4791         rte_eth_dev_info_get(port, &dev_info);
4792
4793         if (vf >= dev_info.max_vfs)
4794                 return -EINVAL;
4795
4796         if (vlan_id > 4095)
4797                 return -EINVAL;
4798
4799         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4801         if (vlan_id) {
4802                 ctrl = vlan_id;
4803                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4804         } else {
4805                 ctrl = 0;
4806         }
4807
4808         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4809
4810         return 0;
4811 }
4812
4813 int
4814 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4815 {
4816         struct ixgbe_hw *hw;
4817         uint32_t ctrl;
4818         struct rte_eth_dev *dev;
4819
4820         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4821
4822         dev = &rte_eth_devices[port];
4823
4824         if (on > 1)
4825                 return -EINVAL;
4826
4827         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4829         /* enable or disable VMDQ loopback */
4830         if (on)
4831                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4832         else
4833                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4834
4835         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4836
4837         return 0;
4838 }
4839
4840 int
4841 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4842 {
4843         struct ixgbe_hw *hw;
4844         uint32_t reg_value;
4845         int i;
4846         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4847         struct rte_eth_dev *dev;
4848
4849         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4850
4851         dev = &rte_eth_devices[port];
4852
4853         if (on > 1)
4854                 return -EINVAL;
4855
4856         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4857         for (i = 0; i <= num_queues; i++) {
4858                 reg_value = IXGBE_QDE_WRITE |
4859                                 (i << IXGBE_QDE_IDX_SHIFT) |
4860                                 (on & IXGBE_QDE_ENABLE);
4861                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4862         }
4863
4864         return 0;
4865 }
4866
4867 int
4868 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4869 {
4870         struct ixgbe_hw *hw;
4871         uint32_t reg_value;
4872         struct rte_eth_dev *dev;
4873         struct rte_eth_dev_info dev_info;
4874
4875         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4876
4877         dev = &rte_eth_devices[port];
4878         rte_eth_dev_info_get(port, &dev_info);
4879
4880         /* only support VF's 0 to 63 */
4881         if ((vf >= dev_info.max_vfs) || (vf > 63))
4882                 return -EINVAL;
4883
4884         if (on > 1)
4885                 return -EINVAL;
4886
4887         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4888         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4889         if (on)
4890                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4891         else
4892                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4893
4894         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4895
4896         return 0;
4897 }
4898
4899 int
4900 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4901 {
4902         struct rte_eth_dev *dev;
4903         struct rte_eth_dev_info dev_info;
4904         uint16_t queues_per_pool;
4905         uint32_t q;
4906
4907         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4908
4909         dev = &rte_eth_devices[port];
4910         rte_eth_dev_info_get(port, &dev_info);
4911
4912         if (vf >= dev_info.max_vfs)
4913                 return -EINVAL;
4914
4915         if (on > 1)
4916                 return -EINVAL;
4917
4918         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4919
4920         /* The PF has 128 queue pairs and in SRIOV configuration
4921          * those queues will be assigned to VF's, so RXDCTL
4922          * registers will be dealing with queues which will be
4923          * assigned to VF's.
4924          * Let's say we have SRIOV configured with 31 VF's then the
4925          * first 124 queues 0-123 will be allocated to VF's and only
4926          * the last 4 queues 123-127 will be assigned to the PF.
4927          */
4928
4929         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4930
4931         for (q = 0; q < queues_per_pool; q++)
4932                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4933                                 q + vf * queues_per_pool, on);
4934         return 0;
4935 }
4936
4937 int
4938 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
4939 {
4940         int val = 0;
4941         struct rte_eth_dev *dev;
4942         struct rte_eth_dev_info dev_info;
4943         struct ixgbe_hw *hw;
4944         uint32_t vmolr;
4945
4946         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4947
4948         dev = &rte_eth_devices[port];
4949         rte_eth_dev_info_get(port, &dev_info);
4950
4951         if (strstr(dev_info.driver_name, "ixgbe_vf"))
4952                 return -ENOTSUP;
4953
4954         if (vf >= dev_info.max_vfs)
4955                 return -EINVAL;
4956
4957         if (on > 1)
4958                 return -EINVAL;
4959
4960         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4961         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
4962
4963         if (hw->mac.type == ixgbe_mac_82598EB) {
4964                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4965                              " on 82599 hardware and newer");
4966                 return -ENOTSUP;
4967         }
4968         if (ixgbe_vmdq_mode_check(hw) < 0)
4969                 return -ENOTSUP;
4970
4971         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4972
4973         if (on)
4974                 vmolr |= val;
4975         else
4976                 vmolr &= ~val;
4977
4978         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
4979
4980         return 0;
4981 }
4982
4983 int
4984 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
4985 {
4986         struct rte_eth_dev *dev;
4987         struct rte_eth_dev_info dev_info;
4988         uint32_t reg, addr;
4989         uint32_t val;
4990         const uint8_t bit1 = 0x1;
4991         struct ixgbe_hw *hw;
4992
4993         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4994
4995         dev = &rte_eth_devices[port];
4996         rte_eth_dev_info_get(port, &dev_info);
4997
4998         if (strstr(dev_info.driver_name, "ixgbe_vf"))
4999                 return -ENOTSUP;
5000
5001         if (vf >= dev_info.max_vfs)
5002                 return -EINVAL;
5003
5004         if (on > 1)
5005                 return -EINVAL;
5006
5007         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5008
5009         if (ixgbe_vmdq_mode_check(hw) < 0)
5010                 return -ENOTSUP;
5011
5012         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5013         if (vf >= 32) {
5014                 addr = IXGBE_VFRE(1);
5015                 val = bit1 << (vf - 32);
5016         } else {
5017                 addr = IXGBE_VFRE(0);
5018                 val = bit1 << vf;
5019         }
5020
5021         reg = IXGBE_READ_REG(hw, addr);
5022
5023         if (on)
5024                 reg |= val;
5025         else
5026                 reg &= ~val;
5027
5028         IXGBE_WRITE_REG(hw, addr, reg);
5029
5030         return 0;
5031 }
5032
5033 int
5034 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5035 {
5036         struct rte_eth_dev *dev;
5037         struct rte_eth_dev_info dev_info;
5038         uint32_t reg, addr;
5039         uint32_t val;
5040         const uint8_t bit1 = 0x1;
5041
5042         struct ixgbe_hw *hw;
5043
5044         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5045
5046         dev = &rte_eth_devices[port];
5047         rte_eth_dev_info_get(port, &dev_info);
5048
5049         if (strstr(dev_info.driver_name, "ixgbe_vf"))
5050                 return -ENOTSUP;
5051
5052         if (vf >= dev_info.max_vfs)
5053                 return -EINVAL;
5054
5055         if (on > 1)
5056                 return -EINVAL;
5057
5058         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5059         if (ixgbe_vmdq_mode_check(hw) < 0)
5060                 return -ENOTSUP;
5061
5062         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5063         if (vf >= 32) {
5064                 addr = IXGBE_VFTE(1);
5065                 val = bit1 << (vf - 32);
5066         } else {
5067                 addr = IXGBE_VFTE(0);
5068                 val = bit1 << vf;
5069         }
5070
5071         reg = IXGBE_READ_REG(hw, addr);
5072
5073         if (on)
5074                 reg |= val;
5075         else
5076                 reg &= ~val;
5077
5078         IXGBE_WRITE_REG(hw, addr, reg);
5079
5080         return 0;
5081 }
5082
5083 int
5084 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5085                         uint64_t vf_mask, uint8_t vlan_on)
5086 {
5087         struct rte_eth_dev *dev;
5088         struct rte_eth_dev_info dev_info;
5089         int ret = 0;
5090         uint16_t vf_idx;
5091         struct ixgbe_hw *hw;
5092
5093         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5094
5095         dev = &rte_eth_devices[port];
5096         rte_eth_dev_info_get(port, &dev_info);
5097
5098         if (strstr(dev_info.driver_name, "ixgbe_vf"))
5099                 return -ENOTSUP;
5100
5101         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5102                 return -EINVAL;
5103
5104         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5105         if (ixgbe_vmdq_mode_check(hw) < 0)
5106                 return -ENOTSUP;
5107
5108         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5109                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5110                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5111                                                    vlan_on, false);
5112                         if (ret < 0)
5113                                 return ret;
5114                 }
5115         }
5116
5117         return ret;
5118 }
5119
5120 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5121         uint16_t tx_rate, uint64_t q_msk)
5122 {
5123         struct rte_eth_dev *dev;
5124         struct rte_eth_dev_info dev_info;
5125         struct ixgbe_hw *hw;
5126         struct ixgbe_vf_info *vfinfo;
5127         struct rte_eth_link link;
5128         uint8_t  nb_q_per_pool;
5129         uint32_t queue_stride;
5130         uint32_t queue_idx, idx = 0, vf_idx;
5131         uint32_t queue_end;
5132         uint16_t total_rate = 0;
5133         struct rte_pci_device *pci_dev;
5134
5135         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5136
5137         dev = &rte_eth_devices[port];
5138         rte_eth_dev_info_get(port, &dev_info);
5139         rte_eth_link_get_nowait(port, &link);
5140
5141         if (strstr(dev_info.driver_name, "ixgbe_vf"))
5142                 return -ENOTSUP;
5143
5144         if (vf >= dev_info.max_vfs)
5145                 return -EINVAL;
5146
5147         if (tx_rate > link.link_speed)
5148                 return -EINVAL;
5149
5150         if (q_msk == 0)
5151                 return 0;
5152
5153         pci_dev = IXGBE_DEV_TO_PCI(dev);
5154         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5156         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5157         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5158         queue_idx = vf * queue_stride;
5159         queue_end = queue_idx + nb_q_per_pool - 1;
5160         if (queue_end >= hw->mac.max_tx_queues)
5161                 return -EINVAL;
5162
5163         if (vfinfo) {
5164                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5165                         if (vf_idx == vf)
5166                                 continue;
5167                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5168                                 idx++)
5169                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5170                 }
5171         } else {
5172                 return -EINVAL;
5173         }
5174
5175         /* Store tx_rate for this vf. */
5176         for (idx = 0; idx < nb_q_per_pool; idx++) {
5177                 if (((uint64_t)0x1 << idx) & q_msk) {
5178                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5179                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5180                         total_rate += tx_rate;
5181                 }
5182         }
5183
5184         if (total_rate > dev->data->dev_link.link_speed) {
5185                 /* Reset stored TX rate of the VF if it causes exceed
5186                  * link speed.
5187                  */
5188                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5189                 return -EINVAL;
5190         }
5191
5192         /* Set RTTBCNRC of each queue/pool for vf X  */
5193         for (; queue_idx <= queue_end; queue_idx++) {
5194                 if (0x1 & q_msk)
5195                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5196                 q_msk = q_msk >> 1;
5197         }
5198
5199         return 0;
5200 }
5201
5202 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5203 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5204 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5205 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5206 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5207         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5208         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5209
5210 static int
5211 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5212                         struct rte_eth_mirror_conf *mirror_conf,
5213                         uint8_t rule_id, uint8_t on)
5214 {
5215         uint32_t mr_ctl, vlvf;
5216         uint32_t mp_lsb = 0;
5217         uint32_t mv_msb = 0;
5218         uint32_t mv_lsb = 0;
5219         uint32_t mp_msb = 0;
5220         uint8_t i = 0;
5221         int reg_index = 0;
5222         uint64_t vlan_mask = 0;
5223
5224         const uint8_t pool_mask_offset = 32;
5225         const uint8_t vlan_mask_offset = 32;
5226         const uint8_t dst_pool_offset = 8;
5227         const uint8_t rule_mr_offset  = 4;
5228         const uint8_t mirror_rule_mask = 0x0F;
5229
5230         struct ixgbe_mirror_info *mr_info =
5231                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5232         struct ixgbe_hw *hw =
5233                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5234         uint8_t mirror_type = 0;
5235
5236         if (ixgbe_vmdq_mode_check(hw) < 0)
5237                 return -ENOTSUP;
5238
5239         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5240                 return -EINVAL;
5241
5242         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5243                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5244                         mirror_conf->rule_type);
5245                 return -EINVAL;
5246         }
5247
5248         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5249                 mirror_type |= IXGBE_MRCTL_VLME;
5250                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5251                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5252                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5253                                 /* search vlan id related pool vlan filter index */
5254                                 reg_index = ixgbe_find_vlvf_slot(hw,
5255                                                  mirror_conf->vlan.vlan_id[i],
5256                                                  false);
5257                                 if (reg_index < 0)
5258                                         return -EINVAL;
5259                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5260                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5261                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5262                                       mirror_conf->vlan.vlan_id[i]))
5263                                         vlan_mask |= (1ULL << reg_index);
5264                                 else
5265                                         return -EINVAL;
5266                         }
5267                 }
5268
5269                 if (on) {
5270                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5271                         mv_msb = vlan_mask >> vlan_mask_offset;
5272
5273                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5274                                                 mirror_conf->vlan.vlan_mask;
5275                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5276                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5277                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5278                                                 mirror_conf->vlan.vlan_id[i];
5279                         }
5280                 } else {
5281                         mv_lsb = 0;
5282                         mv_msb = 0;
5283                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5284                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5285                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5286                 }
5287         }
5288
5289         /*
5290          * if enable pool mirror, write related pool mask register,if disable
5291          * pool mirror, clear PFMRVM register
5292          */
5293         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5294                 mirror_type |= IXGBE_MRCTL_VPME;
5295                 if (on) {
5296                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5297                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5298                         mr_info->mr_conf[rule_id].pool_mask =
5299                                         mirror_conf->pool_mask;
5300
5301                 } else {
5302                         mp_lsb = 0;
5303                         mp_msb = 0;
5304                         mr_info->mr_conf[rule_id].pool_mask = 0;
5305                 }
5306         }
5307         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5308                 mirror_type |= IXGBE_MRCTL_UPME;
5309         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5310                 mirror_type |= IXGBE_MRCTL_DPME;
5311
5312         /* read  mirror control register and recalculate it */
5313         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5314
5315         if (on) {
5316                 mr_ctl |= mirror_type;
5317                 mr_ctl &= mirror_rule_mask;
5318                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5319         } else
5320                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5321
5322         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5323         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5324
5325         /* write mirrror control  register */
5326         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5327
5328         /* write pool mirrror control  register */
5329         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5330                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5331                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5332                                 mp_msb);
5333         }
5334         /* write VLAN mirrror control  register */
5335         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5336                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5337                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5338                                 mv_msb);
5339         }
5340
5341         return 0;
5342 }
5343
5344 static int
5345 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5346 {
5347         int mr_ctl = 0;
5348         uint32_t lsb_val = 0;
5349         uint32_t msb_val = 0;
5350         const uint8_t rule_mr_offset = 4;
5351
5352         struct ixgbe_hw *hw =
5353                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5354         struct ixgbe_mirror_info *mr_info =
5355                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5356
5357         if (ixgbe_vmdq_mode_check(hw) < 0)
5358                 return -ENOTSUP;
5359
5360         memset(&mr_info->mr_conf[rule_id], 0,
5361                 sizeof(struct rte_eth_mirror_conf));
5362
5363         /* clear PFVMCTL register */
5364         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5365
5366         /* clear pool mask register */
5367         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5368         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5369
5370         /* clear vlan mask register */
5371         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5372         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5373
5374         return 0;
5375 }
5376
5377 static int
5378 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5379 {
5380         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5381         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5382         uint32_t mask;
5383         struct ixgbe_hw *hw =
5384                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5385
5386         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5387         mask |= (1 << IXGBE_MISC_VEC_ID);
5388         RTE_SET_USED(queue_id);
5389         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5390
5391         rte_intr_enable(intr_handle);
5392
5393         return 0;
5394 }
5395
5396 static int
5397 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5398 {
5399         uint32_t mask;
5400         struct ixgbe_hw *hw =
5401                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5402
5403         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5404         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5405         RTE_SET_USED(queue_id);
5406         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5407
5408         return 0;
5409 }
5410
5411 static int
5412 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5413 {
5414         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5415         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5416         uint32_t mask;
5417         struct ixgbe_hw *hw =
5418                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5419         struct ixgbe_interrupt *intr =
5420                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5421
5422         if (queue_id < 16) {
5423                 ixgbe_disable_intr(hw);
5424                 intr->mask |= (1 << queue_id);
5425                 ixgbe_enable_intr(dev);
5426         } else if (queue_id < 32) {
5427                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5428                 mask &= (1 << queue_id);
5429                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5430         } else if (queue_id < 64) {
5431                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5432                 mask &= (1 << (queue_id - 32));
5433                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5434         }
5435         rte_intr_enable(intr_handle);
5436
5437         return 0;
5438 }
5439
5440 static int
5441 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5442 {
5443         uint32_t mask;
5444         struct ixgbe_hw *hw =
5445                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5446         struct ixgbe_interrupt *intr =
5447                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5448
5449         if (queue_id < 16) {
5450                 ixgbe_disable_intr(hw);
5451                 intr->mask &= ~(1 << queue_id);
5452                 ixgbe_enable_intr(dev);
5453         } else if (queue_id < 32) {
5454                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5455                 mask &= ~(1 << queue_id);
5456                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5457         } else if (queue_id < 64) {
5458                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5459                 mask &= ~(1 << (queue_id - 32));
5460                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5461         }
5462
5463         return 0;
5464 }
5465
5466 static void
5467 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5468                      uint8_t queue, uint8_t msix_vector)
5469 {
5470         uint32_t tmp, idx;
5471
5472         if (direction == -1) {
5473                 /* other causes */
5474                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5475                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5476                 tmp &= ~0xFF;
5477                 tmp |= msix_vector;
5478                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5479         } else {
5480                 /* rx or tx cause */
5481                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5482                 idx = ((16 * (queue & 1)) + (8 * direction));
5483                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5484                 tmp &= ~(0xFF << idx);
5485                 tmp |= (msix_vector << idx);
5486                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5487         }
5488 }
5489
5490 /**
5491  * set the IVAR registers, mapping interrupt causes to vectors
5492  * @param hw
5493  *  pointer to ixgbe_hw struct
5494  * @direction
5495  *  0 for Rx, 1 for Tx, -1 for other causes
5496  * @queue
5497  *  queue to map the corresponding interrupt to
5498  * @msix_vector
5499  *  the vector to map to the corresponding queue
5500  */
5501 static void
5502 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5503                    uint8_t queue, uint8_t msix_vector)
5504 {
5505         uint32_t tmp, idx;
5506
5507         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5508         if (hw->mac.type == ixgbe_mac_82598EB) {
5509                 if (direction == -1)
5510                         direction = 0;
5511                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5512                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5513                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5514                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5515                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5516         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5517                         (hw->mac.type == ixgbe_mac_X540)) {
5518                 if (direction == -1) {
5519                         /* other causes */
5520                         idx = ((queue & 1) * 8);
5521                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5522                         tmp &= ~(0xFF << idx);
5523                         tmp |= (msix_vector << idx);
5524                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5525                 } else {
5526                         /* rx or tx causes */
5527                         idx = ((16 * (queue & 1)) + (8 * direction));
5528                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5529                         tmp &= ~(0xFF << idx);
5530                         tmp |= (msix_vector << idx);
5531                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5532                 }
5533         }
5534 }
5535
5536 static void
5537 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5538 {
5539         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5540         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5541         struct ixgbe_hw *hw =
5542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5543         uint32_t q_idx;
5544         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5545
5546         /* Configure VF other cause ivar */
5547         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5548
5549         /* won't configure msix register if no mapping is done
5550          * between intr vector and event fd.
5551          */
5552         if (!rte_intr_dp_is_en(intr_handle))
5553                 return;
5554
5555         /* Configure all RX queues of VF */
5556         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5557                 /* Force all queue use vector 0,
5558                  * as IXGBE_VF_MAXMSIVECOTR = 1
5559                  */
5560                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5561                 intr_handle->intr_vec[q_idx] = vector_idx;
5562         }
5563 }
5564
5565 /**
5566  * Sets up the hardware to properly generate MSI-X interrupts
5567  * @hw
5568  *  board private structure
5569  */
5570 static void
5571 ixgbe_configure_msix(struct rte_eth_dev *dev)
5572 {
5573         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5574         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5575         struct ixgbe_hw *hw =
5576                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5577         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5578         uint32_t vec = IXGBE_MISC_VEC_ID;
5579         uint32_t mask;
5580         uint32_t gpie;
5581
5582         /* won't configure msix register if no mapping is done
5583          * between intr vector and event fd
5584          */
5585         if (!rte_intr_dp_is_en(intr_handle))
5586                 return;
5587
5588         if (rte_intr_allow_others(intr_handle))
5589                 vec = base = IXGBE_RX_VEC_START;
5590
5591         /* setup GPIE for MSI-x mode */
5592         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5593         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5594                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5595         /* auto clearing and auto setting corresponding bits in EIMS
5596          * when MSI-X interrupt is triggered
5597          */
5598         if (hw->mac.type == ixgbe_mac_82598EB) {
5599                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5600         } else {
5601                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5602                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5603         }
5604         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5605
5606         /* Populate the IVAR table and set the ITR values to the
5607          * corresponding register.
5608          */
5609         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5610              queue_id++) {
5611                 /* by default, 1:1 mapping */
5612                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5613                 intr_handle->intr_vec[queue_id] = vec;
5614                 if (vec < base + intr_handle->nb_efd - 1)
5615                         vec++;
5616         }
5617
5618         switch (hw->mac.type) {
5619         case ixgbe_mac_82598EB:
5620                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5621                                    IXGBE_MISC_VEC_ID);
5622                 break;
5623         case ixgbe_mac_82599EB:
5624         case ixgbe_mac_X540:
5625                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5626                 break;
5627         default:
5628                 break;
5629         }
5630         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5631                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5632
5633         /* set up to autoclear timer, and the vectors */
5634         mask = IXGBE_EIMS_ENABLE_MASK;
5635         mask &= ~(IXGBE_EIMS_OTHER |
5636                   IXGBE_EIMS_MAILBOX |
5637                   IXGBE_EIMS_LSC);
5638
5639         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5640 }
5641
5642 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5643         uint16_t queue_idx, uint16_t tx_rate)
5644 {
5645         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5646         uint32_t rf_dec, rf_int;
5647         uint32_t bcnrc_val;
5648         uint16_t link_speed = dev->data->dev_link.link_speed;
5649
5650         if (queue_idx >= hw->mac.max_tx_queues)
5651                 return -EINVAL;
5652
5653         if (tx_rate != 0) {
5654                 /* Calculate the rate factor values to set */
5655                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5656                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5657                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5658
5659                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5660                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5661                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5662                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5663         } else {
5664                 bcnrc_val = 0;
5665         }
5666
5667         /*
5668          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5669          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5670          * set as 0x4.
5671          */
5672         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5673                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5674                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5675                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5676                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5677         else
5678                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5679                         IXGBE_MMW_SIZE_DEFAULT);
5680
5681         /* Set RTTBCNRC of queue X */
5682         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5683         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5684         IXGBE_WRITE_FLUSH(hw);
5685
5686         return 0;
5687 }
5688
5689 static void
5690 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5691                      __attribute__((unused)) uint32_t index,
5692                      __attribute__((unused)) uint32_t pool)
5693 {
5694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5695         int diag;
5696
5697         /*
5698          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5699          * operation. Trap this case to avoid exhausting the [very limited]
5700          * set of PF resources used to store VF MAC addresses.
5701          */
5702         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5703                 return;
5704         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5705         if (diag == 0)
5706                 return;
5707         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5708 }
5709
5710 static void
5711 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5712 {
5713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5714         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5715         struct ether_addr *mac_addr;
5716         uint32_t i;
5717         int diag;
5718
5719         /*
5720          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5721          * not support the deletion of a given MAC address.
5722          * Instead, it imposes to delete all MAC addresses, then to add again
5723          * all MAC addresses with the exception of the one to be deleted.
5724          */
5725         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5726
5727         /*
5728          * Add again all MAC addresses, with the exception of the deleted one
5729          * and of the permanent MAC address.
5730          */
5731         for (i = 0, mac_addr = dev->data->mac_addrs;
5732              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5733                 /* Skip the deleted MAC address */
5734                 if (i == index)
5735                         continue;
5736                 /* Skip NULL MAC addresses */
5737                 if (is_zero_ether_addr(mac_addr))
5738                         continue;
5739                 /* Skip the permanent MAC address */
5740                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5741                         continue;
5742                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5743                 if (diag != 0)
5744                         PMD_DRV_LOG(ERR,
5745                                     "Adding again MAC address "
5746                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5747                                     "diag=%d",
5748                                     mac_addr->addr_bytes[0],
5749                                     mac_addr->addr_bytes[1],
5750                                     mac_addr->addr_bytes[2],
5751                                     mac_addr->addr_bytes[3],
5752                                     mac_addr->addr_bytes[4],
5753                                     mac_addr->addr_bytes[5],
5754                                     diag);
5755         }
5756 }
5757
5758 static void
5759 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5760 {
5761         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5762
5763         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5764 }
5765
5766 #define MAC_TYPE_FILTER_SUP(type)    do {\
5767         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5768                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5769                 (type) != ixgbe_mac_X550EM_a)\
5770                 return -ENOTSUP;\
5771 } while (0)
5772
5773 static int
5774 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5775                         struct rte_eth_syn_filter *filter,
5776                         bool add)
5777 {
5778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5779         uint32_t synqf;
5780
5781         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5782                 return -EINVAL;
5783
5784         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5785
5786         if (add) {
5787                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5788                         return -EINVAL;
5789                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5790                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5791
5792                 if (filter->hig_pri)
5793                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5794                 else
5795                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5796         } else {
5797                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5798                         return -ENOENT;
5799                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5800         }
5801         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5802         IXGBE_WRITE_FLUSH(hw);
5803         return 0;
5804 }
5805
5806 static int
5807 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5808                         struct rte_eth_syn_filter *filter)
5809 {
5810         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5811         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5812
5813         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5814                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5815                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5816                 return 0;
5817         }
5818         return -ENOENT;
5819 }
5820
5821 static int
5822 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5823                         enum rte_filter_op filter_op,
5824                         void *arg)
5825 {
5826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5827         int ret;
5828
5829         MAC_TYPE_FILTER_SUP(hw->mac.type);
5830
5831         if (filter_op == RTE_ETH_FILTER_NOP)
5832                 return 0;
5833
5834         if (arg == NULL) {
5835                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5836                             filter_op);
5837                 return -EINVAL;
5838         }
5839
5840         switch (filter_op) {
5841         case RTE_ETH_FILTER_ADD:
5842                 ret = ixgbe_syn_filter_set(dev,
5843                                 (struct rte_eth_syn_filter *)arg,
5844                                 TRUE);
5845                 break;
5846         case RTE_ETH_FILTER_DELETE:
5847                 ret = ixgbe_syn_filter_set(dev,
5848                                 (struct rte_eth_syn_filter *)arg,
5849                                 FALSE);
5850                 break;
5851         case RTE_ETH_FILTER_GET:
5852                 ret = ixgbe_syn_filter_get(dev,
5853                                 (struct rte_eth_syn_filter *)arg);
5854                 break;
5855         default:
5856                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5857                 ret = -EINVAL;
5858                 break;
5859         }
5860
5861         return ret;
5862 }
5863
5864
5865 static inline enum ixgbe_5tuple_protocol
5866 convert_protocol_type(uint8_t protocol_value)
5867 {
5868         if (protocol_value == IPPROTO_TCP)
5869                 return IXGBE_FILTER_PROTOCOL_TCP;
5870         else if (protocol_value == IPPROTO_UDP)
5871                 return IXGBE_FILTER_PROTOCOL_UDP;
5872         else if (protocol_value == IPPROTO_SCTP)
5873                 return IXGBE_FILTER_PROTOCOL_SCTP;
5874         else
5875                 return IXGBE_FILTER_PROTOCOL_NONE;
5876 }
5877
5878 /*
5879  * add a 5tuple filter
5880  *
5881  * @param
5882  * dev: Pointer to struct rte_eth_dev.
5883  * index: the index the filter allocates.
5884  * filter: ponter to the filter that will be added.
5885  * rx_queue: the queue id the filter assigned to.
5886  *
5887  * @return
5888  *    - On success, zero.
5889  *    - On failure, a negative value.
5890  */
5891 static int
5892 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5893                         struct ixgbe_5tuple_filter *filter)
5894 {
5895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5896         struct ixgbe_filter_info *filter_info =
5897                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5898         int i, idx, shift;
5899         uint32_t ftqf, sdpqf;
5900         uint32_t l34timir = 0;
5901         uint8_t mask = 0xff;
5902
5903         /*
5904          * look for an unused 5tuple filter index,
5905          * and insert the filter to list.
5906          */
5907         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5908                 idx = i / (sizeof(uint32_t) * NBBY);
5909                 shift = i % (sizeof(uint32_t) * NBBY);
5910                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5911                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5912                         filter->index = i;
5913                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5914                                           filter,
5915                                           entries);
5916                         break;
5917                 }
5918         }
5919         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5920                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5921                 return -ENOSYS;
5922         }
5923
5924         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5925                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5926         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5927
5928         ftqf = (uint32_t)(filter->filter_info.proto &
5929                 IXGBE_FTQF_PROTOCOL_MASK);
5930         ftqf |= (uint32_t)((filter->filter_info.priority &
5931                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5932         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5933                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5934         if (filter->filter_info.dst_ip_mask == 0)
5935                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5936         if (filter->filter_info.src_port_mask == 0)
5937                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5938         if (filter->filter_info.dst_port_mask == 0)
5939                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5940         if (filter->filter_info.proto_mask == 0)
5941                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5942         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5943         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5944         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5945
5946         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5947         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5948         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5949         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5950
5951         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5952         l34timir |= (uint32_t)(filter->queue <<
5953                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5954         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5955         return 0;
5956 }
5957
5958 /*
5959  * remove a 5tuple filter
5960  *
5961  * @param
5962  * dev: Pointer to struct rte_eth_dev.
5963  * filter: the pointer of the filter will be removed.
5964  */
5965 static void
5966 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5967                         struct ixgbe_5tuple_filter *filter)
5968 {
5969         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5970         struct ixgbe_filter_info *filter_info =
5971                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5972         uint16_t index = filter->index;
5973
5974         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5975                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5976         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5977         rte_free(filter);
5978
5979         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5980         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5981         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5982         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5983         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5984 }
5985
5986 static int
5987 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5988 {
5989         struct ixgbe_hw *hw;
5990         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5991
5992         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5993
5994         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5995                 return -EINVAL;
5996
5997         /* refuse mtu that requires the support of scattered packets when this
5998          * feature has not been enabled before.
5999          */
6000         if (!dev->data->scattered_rx &&
6001             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6002              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6003                 return -EINVAL;
6004
6005         /*
6006          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6007          * request of the version 2.0 of the mailbox API.
6008          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6009          * of the mailbox API.
6010          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6011          * prior to 3.11.33 which contains the following change:
6012          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6013          */
6014         ixgbevf_rlpml_set_vf(hw, max_frame);
6015
6016         /* update max frame size */
6017         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6018         return 0;
6019 }
6020
6021 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
6022         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6023                 return -ENOTSUP;\
6024 } while (0)
6025
6026 static inline struct ixgbe_5tuple_filter *
6027 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6028                         struct ixgbe_5tuple_filter_info *key)
6029 {
6030         struct ixgbe_5tuple_filter *it;
6031
6032         TAILQ_FOREACH(it, filter_list, entries) {
6033                 if (memcmp(key, &it->filter_info,
6034                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6035                         return it;
6036                 }
6037         }
6038         return NULL;
6039 }
6040
6041 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6042 static inline int
6043 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6044                         struct ixgbe_5tuple_filter_info *filter_info)
6045 {
6046         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6047                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6048                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6049                 return -EINVAL;
6050
6051         switch (filter->dst_ip_mask) {
6052         case UINT32_MAX:
6053                 filter_info->dst_ip_mask = 0;
6054                 filter_info->dst_ip = filter->dst_ip;
6055                 break;
6056         case 0:
6057                 filter_info->dst_ip_mask = 1;
6058                 break;
6059         default:
6060                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6061                 return -EINVAL;
6062         }
6063
6064         switch (filter->src_ip_mask) {
6065         case UINT32_MAX:
6066                 filter_info->src_ip_mask = 0;
6067                 filter_info->src_ip = filter->src_ip;
6068                 break;
6069         case 0:
6070                 filter_info->src_ip_mask = 1;
6071                 break;
6072         default:
6073                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6074                 return -EINVAL;
6075         }
6076
6077         switch (filter->dst_port_mask) {
6078         case UINT16_MAX:
6079                 filter_info->dst_port_mask = 0;
6080                 filter_info->dst_port = filter->dst_port;
6081                 break;
6082         case 0:
6083                 filter_info->dst_port_mask = 1;
6084                 break;
6085         default:
6086                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6087                 return -EINVAL;
6088         }
6089
6090         switch (filter->src_port_mask) {
6091         case UINT16_MAX:
6092                 filter_info->src_port_mask = 0;
6093                 filter_info->src_port = filter->src_port;
6094                 break;
6095         case 0:
6096                 filter_info->src_port_mask = 1;
6097                 break;
6098         default:
6099                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6100                 return -EINVAL;
6101         }
6102
6103         switch (filter->proto_mask) {
6104         case UINT8_MAX:
6105                 filter_info->proto_mask = 0;
6106                 filter_info->proto =
6107                         convert_protocol_type(filter->proto);
6108                 break;
6109         case 0:
6110                 filter_info->proto_mask = 1;
6111                 break;
6112         default:
6113                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6114                 return -EINVAL;
6115         }
6116
6117         filter_info->priority = (uint8_t)filter->priority;
6118         return 0;
6119 }
6120
6121 /*
6122  * add or delete a ntuple filter
6123  *
6124  * @param
6125  * dev: Pointer to struct rte_eth_dev.
6126  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6127  * add: if true, add filter, if false, remove filter
6128  *
6129  * @return
6130  *    - On success, zero.
6131  *    - On failure, a negative value.
6132  */
6133 static int
6134 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6135                         struct rte_eth_ntuple_filter *ntuple_filter,
6136                         bool add)
6137 {
6138         struct ixgbe_filter_info *filter_info =
6139                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6140         struct ixgbe_5tuple_filter_info filter_5tuple;
6141         struct ixgbe_5tuple_filter *filter;
6142         int ret;
6143
6144         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6145                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6146                 return -EINVAL;
6147         }
6148
6149         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6150         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6151         if (ret < 0)
6152                 return ret;
6153
6154         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6155                                          &filter_5tuple);
6156         if (filter != NULL && add) {
6157                 PMD_DRV_LOG(ERR, "filter exists.");
6158                 return -EEXIST;
6159         }
6160         if (filter == NULL && !add) {
6161                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6162                 return -ENOENT;
6163         }
6164
6165         if (add) {
6166                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6167                                 sizeof(struct ixgbe_5tuple_filter), 0);
6168                 if (filter == NULL)
6169                         return -ENOMEM;
6170                 (void)rte_memcpy(&filter->filter_info,
6171                                  &filter_5tuple,
6172                                  sizeof(struct ixgbe_5tuple_filter_info));
6173                 filter->queue = ntuple_filter->queue;
6174                 ret = ixgbe_add_5tuple_filter(dev, filter);
6175                 if (ret < 0) {
6176                         rte_free(filter);
6177                         return ret;
6178                 }
6179         } else
6180                 ixgbe_remove_5tuple_filter(dev, filter);
6181
6182         return 0;
6183 }
6184
6185 /*
6186  * get a ntuple filter
6187  *
6188  * @param
6189  * dev: Pointer to struct rte_eth_dev.
6190  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6191  *
6192  * @return
6193  *    - On success, zero.
6194  *    - On failure, a negative value.
6195  */
6196 static int
6197 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6198                         struct rte_eth_ntuple_filter *ntuple_filter)
6199 {
6200         struct ixgbe_filter_info *filter_info =
6201                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6202         struct ixgbe_5tuple_filter_info filter_5tuple;
6203         struct ixgbe_5tuple_filter *filter;
6204         int ret;
6205
6206         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6207                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6208                 return -EINVAL;
6209         }
6210
6211         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6212         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6213         if (ret < 0)
6214                 return ret;
6215
6216         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6217                                          &filter_5tuple);
6218         if (filter == NULL) {
6219                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6220                 return -ENOENT;
6221         }
6222         ntuple_filter->queue = filter->queue;
6223         return 0;
6224 }
6225
6226 /*
6227  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6228  * @dev: pointer to rte_eth_dev structure
6229  * @filter_op:operation will be taken.
6230  * @arg: a pointer to specific structure corresponding to the filter_op
6231  *
6232  * @return
6233  *    - On success, zero.
6234  *    - On failure, a negative value.
6235  */
6236 static int
6237 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6238                                 enum rte_filter_op filter_op,
6239                                 void *arg)
6240 {
6241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6242         int ret;
6243
6244         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6245
6246         if (filter_op == RTE_ETH_FILTER_NOP)
6247                 return 0;
6248
6249         if (arg == NULL) {
6250                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6251                             filter_op);
6252                 return -EINVAL;
6253         }
6254
6255         switch (filter_op) {
6256         case RTE_ETH_FILTER_ADD:
6257                 ret = ixgbe_add_del_ntuple_filter(dev,
6258                         (struct rte_eth_ntuple_filter *)arg,
6259                         TRUE);
6260                 break;
6261         case RTE_ETH_FILTER_DELETE:
6262                 ret = ixgbe_add_del_ntuple_filter(dev,
6263                         (struct rte_eth_ntuple_filter *)arg,
6264                         FALSE);
6265                 break;
6266         case RTE_ETH_FILTER_GET:
6267                 ret = ixgbe_get_ntuple_filter(dev,
6268                         (struct rte_eth_ntuple_filter *)arg);
6269                 break;
6270         default:
6271                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6272                 ret = -EINVAL;
6273                 break;
6274         }
6275         return ret;
6276 }
6277
6278 static inline int
6279 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6280                         uint16_t ethertype)
6281 {
6282         int i;
6283
6284         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6285                 if (filter_info->ethertype_filters[i] == ethertype &&
6286                     (filter_info->ethertype_mask & (1 << i)))
6287                         return i;
6288         }
6289         return -1;
6290 }
6291
6292 static inline int
6293 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6294                         uint16_t ethertype)
6295 {
6296         int i;
6297
6298         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6299                 if (!(filter_info->ethertype_mask & (1 << i))) {
6300                         filter_info->ethertype_mask |= 1 << i;
6301                         filter_info->ethertype_filters[i] = ethertype;
6302                         return i;
6303                 }
6304         }
6305         return -1;
6306 }
6307
6308 static inline int
6309 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6310                         uint8_t idx)
6311 {
6312         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6313                 return -1;
6314         filter_info->ethertype_mask &= ~(1 << idx);
6315         filter_info->ethertype_filters[idx] = 0;
6316         return idx;
6317 }
6318
6319 static int
6320 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6321                         struct rte_eth_ethertype_filter *filter,
6322                         bool add)
6323 {
6324         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6325         struct ixgbe_filter_info *filter_info =
6326                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6327         uint32_t etqf = 0;
6328         uint32_t etqs = 0;
6329         int ret;
6330
6331         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6332                 return -EINVAL;
6333
6334         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6335                 filter->ether_type == ETHER_TYPE_IPv6) {
6336                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6337                         " ethertype filter.", filter->ether_type);
6338                 return -EINVAL;
6339         }
6340
6341         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6342                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6343                 return -EINVAL;
6344         }
6345         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6346                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6347                 return -EINVAL;
6348         }
6349
6350         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6351         if (ret >= 0 && add) {
6352                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6353                             filter->ether_type);
6354                 return -EEXIST;
6355         }
6356         if (ret < 0 && !add) {
6357                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6358                             filter->ether_type);
6359                 return -ENOENT;
6360         }
6361
6362         if (add) {
6363                 ret = ixgbe_ethertype_filter_insert(filter_info,
6364                         filter->ether_type);
6365                 if (ret < 0) {
6366                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6367                         return -ENOSYS;
6368                 }
6369                 etqf = IXGBE_ETQF_FILTER_EN;
6370                 etqf |= (uint32_t)filter->ether_type;
6371                 etqs |= (uint32_t)((filter->queue <<
6372                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6373                                     IXGBE_ETQS_RX_QUEUE);
6374                 etqs |= IXGBE_ETQS_QUEUE_EN;
6375         } else {
6376                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6377                 if (ret < 0)
6378                         return -ENOSYS;
6379         }
6380         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6381         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6382         IXGBE_WRITE_FLUSH(hw);
6383
6384         return 0;
6385 }
6386
6387 static int
6388 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6389                         struct rte_eth_ethertype_filter *filter)
6390 {
6391         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6392         struct ixgbe_filter_info *filter_info =
6393                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6394         uint32_t etqf, etqs;
6395         int ret;
6396
6397         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6398         if (ret < 0) {
6399                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6400                             filter->ether_type);
6401                 return -ENOENT;
6402         }
6403
6404         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6405         if (etqf & IXGBE_ETQF_FILTER_EN) {
6406                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6407                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6408                 filter->flags = 0;
6409                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6410                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6411                 return 0;
6412         }
6413         return -ENOENT;
6414 }
6415
6416 /*
6417  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6418  * @dev: pointer to rte_eth_dev structure
6419  * @filter_op:operation will be taken.
6420  * @arg: a pointer to specific structure corresponding to the filter_op
6421  */
6422 static int
6423 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6424                                 enum rte_filter_op filter_op,
6425                                 void *arg)
6426 {
6427         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6428         int ret;
6429
6430         MAC_TYPE_FILTER_SUP(hw->mac.type);
6431
6432         if (filter_op == RTE_ETH_FILTER_NOP)
6433                 return 0;
6434
6435         if (arg == NULL) {
6436                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6437                             filter_op);
6438                 return -EINVAL;
6439         }
6440
6441         switch (filter_op) {
6442         case RTE_ETH_FILTER_ADD:
6443                 ret = ixgbe_add_del_ethertype_filter(dev,
6444                         (struct rte_eth_ethertype_filter *)arg,
6445                         TRUE);
6446                 break;
6447         case RTE_ETH_FILTER_DELETE:
6448                 ret = ixgbe_add_del_ethertype_filter(dev,
6449                         (struct rte_eth_ethertype_filter *)arg,
6450                         FALSE);
6451                 break;
6452         case RTE_ETH_FILTER_GET:
6453                 ret = ixgbe_get_ethertype_filter(dev,
6454                         (struct rte_eth_ethertype_filter *)arg);
6455                 break;
6456         default:
6457                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6458                 ret = -EINVAL;
6459                 break;
6460         }
6461         return ret;
6462 }
6463
6464 static int
6465 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6466                      enum rte_filter_type filter_type,
6467                      enum rte_filter_op filter_op,
6468                      void *arg)
6469 {
6470         int ret = -EINVAL;
6471
6472         switch (filter_type) {
6473         case RTE_ETH_FILTER_NTUPLE:
6474                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6475                 break;
6476         case RTE_ETH_FILTER_ETHERTYPE:
6477                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6478                 break;
6479         case RTE_ETH_FILTER_SYN:
6480                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6481                 break;
6482         case RTE_ETH_FILTER_FDIR:
6483                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6484                 break;
6485         case RTE_ETH_FILTER_L2_TUNNEL:
6486                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6487                 break;
6488         default:
6489                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6490                                                         filter_type);
6491                 break;
6492         }
6493
6494         return ret;
6495 }
6496
6497 static u8 *
6498 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6499                         u8 **mc_addr_ptr, u32 *vmdq)
6500 {
6501         u8 *mc_addr;
6502
6503         *vmdq = 0;
6504         mc_addr = *mc_addr_ptr;
6505         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6506         return mc_addr;
6507 }
6508
6509 static int
6510 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6511                           struct ether_addr *mc_addr_set,
6512                           uint32_t nb_mc_addr)
6513 {
6514         struct ixgbe_hw *hw;
6515         u8 *mc_addr_list;
6516
6517         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6518         mc_addr_list = (u8 *)mc_addr_set;
6519         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6520                                          ixgbe_dev_addr_list_itr, TRUE);
6521 }
6522
6523 static uint64_t
6524 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6525 {
6526         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6527         uint64_t systime_cycles;
6528
6529         switch (hw->mac.type) {
6530         case ixgbe_mac_X550:
6531         case ixgbe_mac_X550EM_x:
6532         case ixgbe_mac_X550EM_a:
6533                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6534                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6535                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6536                                 * NSEC_PER_SEC;
6537                 break;
6538         default:
6539                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6540                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6541                                 << 32;
6542         }
6543
6544         return systime_cycles;
6545 }
6546
6547 static uint64_t
6548 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6549 {
6550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6551         uint64_t rx_tstamp_cycles;
6552
6553         switch (hw->mac.type) {
6554         case ixgbe_mac_X550:
6555         case ixgbe_mac_X550EM_x:
6556         case ixgbe_mac_X550EM_a:
6557                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6558                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6559                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6560                                 * NSEC_PER_SEC;
6561                 break;
6562         default:
6563                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6564                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6565                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6566                                 << 32;
6567         }
6568
6569         return rx_tstamp_cycles;
6570 }
6571
6572 static uint64_t
6573 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6574 {
6575         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6576         uint64_t tx_tstamp_cycles;
6577
6578         switch (hw->mac.type) {
6579         case ixgbe_mac_X550:
6580         case ixgbe_mac_X550EM_x:
6581         case ixgbe_mac_X550EM_a:
6582                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6583                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6584                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6585                                 * NSEC_PER_SEC;
6586                 break;
6587         default:
6588                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6589                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6590                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6591                                 << 32;
6592         }
6593
6594         return tx_tstamp_cycles;
6595 }
6596
6597 static void
6598 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6599 {
6600         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6601         struct ixgbe_adapter *adapter =
6602                 (struct ixgbe_adapter *)dev->data->dev_private;
6603         struct rte_eth_link link;
6604         uint32_t incval = 0;
6605         uint32_t shift = 0;
6606
6607         /* Get current link speed. */
6608         memset(&link, 0, sizeof(link));
6609         ixgbe_dev_link_update(dev, 1);
6610         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6611
6612         switch (link.link_speed) {
6613         case ETH_SPEED_NUM_100M:
6614                 incval = IXGBE_INCVAL_100;
6615                 shift = IXGBE_INCVAL_SHIFT_100;
6616                 break;
6617         case ETH_SPEED_NUM_1G:
6618                 incval = IXGBE_INCVAL_1GB;
6619                 shift = IXGBE_INCVAL_SHIFT_1GB;
6620                 break;
6621         case ETH_SPEED_NUM_10G:
6622         default:
6623                 incval = IXGBE_INCVAL_10GB;
6624                 shift = IXGBE_INCVAL_SHIFT_10GB;
6625                 break;
6626         }
6627
6628         switch (hw->mac.type) {
6629         case ixgbe_mac_X550:
6630         case ixgbe_mac_X550EM_x:
6631         case ixgbe_mac_X550EM_a:
6632                 /* Independent of link speed. */
6633                 incval = 1;
6634                 /* Cycles read will be interpreted as ns. */
6635                 shift = 0;
6636                 /* Fall-through */
6637         case ixgbe_mac_X540:
6638                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6639                 break;
6640         case ixgbe_mac_82599EB:
6641                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6642                 shift -= IXGBE_INCVAL_SHIFT_82599;
6643                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6644                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6645                 break;
6646         default:
6647                 /* Not supported. */
6648                 return;
6649         }
6650
6651         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6652         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6653         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6654
6655         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6656         adapter->systime_tc.cc_shift = shift;
6657         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6658
6659         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6660         adapter->rx_tstamp_tc.cc_shift = shift;
6661         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6662
6663         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6664         adapter->tx_tstamp_tc.cc_shift = shift;
6665         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6666 }
6667
6668 static int
6669 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6670 {
6671         struct ixgbe_adapter *adapter =
6672                         (struct ixgbe_adapter *)dev->data->dev_private;
6673
6674         adapter->systime_tc.nsec += delta;
6675         adapter->rx_tstamp_tc.nsec += delta;
6676         adapter->tx_tstamp_tc.nsec += delta;
6677
6678         return 0;
6679 }
6680
6681 static int
6682 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6683 {
6684         uint64_t ns;
6685         struct ixgbe_adapter *adapter =
6686                         (struct ixgbe_adapter *)dev->data->dev_private;
6687
6688         ns = rte_timespec_to_ns(ts);
6689         /* Set the timecounters to a new value. */
6690         adapter->systime_tc.nsec = ns;
6691         adapter->rx_tstamp_tc.nsec = ns;
6692         adapter->tx_tstamp_tc.nsec = ns;
6693
6694         return 0;
6695 }
6696
6697 static int
6698 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6699 {
6700         uint64_t ns, systime_cycles;
6701         struct ixgbe_adapter *adapter =
6702                         (struct ixgbe_adapter *)dev->data->dev_private;
6703
6704         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6705         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6706         *ts = rte_ns_to_timespec(ns);
6707
6708         return 0;
6709 }
6710
6711 static int
6712 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6713 {
6714         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6715         uint32_t tsync_ctl;
6716         uint32_t tsauxc;
6717
6718         /* Stop the timesync system time. */
6719         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6720         /* Reset the timesync system time value. */
6721         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6722         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6723
6724         /* Enable system time for platforms where it isn't on by default. */
6725         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6726         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6727         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6728
6729         ixgbe_start_timecounters(dev);
6730
6731         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6732         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6733                         (ETHER_TYPE_1588 |
6734                          IXGBE_ETQF_FILTER_EN |
6735                          IXGBE_ETQF_1588));
6736
6737         /* Enable timestamping of received PTP packets. */
6738         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6739         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6740         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6741
6742         /* Enable timestamping of transmitted PTP packets. */
6743         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6744         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6745         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6746
6747         IXGBE_WRITE_FLUSH(hw);
6748
6749         return 0;
6750 }
6751
6752 static int
6753 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6754 {
6755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6756         uint32_t tsync_ctl;
6757
6758         /* Disable timestamping of transmitted PTP packets. */
6759         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6760         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6761         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6762
6763         /* Disable timestamping of received PTP packets. */
6764         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6765         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6766         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6767
6768         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6769         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6770
6771         /* Stop incrementating the System Time registers. */
6772         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6773
6774         return 0;
6775 }
6776
6777 static int
6778 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6779                                  struct timespec *timestamp,
6780                                  uint32_t flags __rte_unused)
6781 {
6782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783         struct ixgbe_adapter *adapter =
6784                 (struct ixgbe_adapter *)dev->data->dev_private;
6785         uint32_t tsync_rxctl;
6786         uint64_t rx_tstamp_cycles;
6787         uint64_t ns;
6788
6789         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6790         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6791                 return -EINVAL;
6792
6793         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6794         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6795         *timestamp = rte_ns_to_timespec(ns);
6796
6797         return  0;
6798 }
6799
6800 static int
6801 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6802                                  struct timespec *timestamp)
6803 {
6804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6805         struct ixgbe_adapter *adapter =
6806                 (struct ixgbe_adapter *)dev->data->dev_private;
6807         uint32_t tsync_txctl;
6808         uint64_t tx_tstamp_cycles;
6809         uint64_t ns;
6810
6811         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6812         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6813                 return -EINVAL;
6814
6815         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6816         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6817         *timestamp = rte_ns_to_timespec(ns);
6818
6819         return 0;
6820 }
6821
6822 static int
6823 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6824 {
6825         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6826         int count = 0;
6827         int g_ind = 0;
6828         const struct reg_info *reg_group;
6829         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6830                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6831
6832         while ((reg_group = reg_set[g_ind++]))
6833                 count += ixgbe_regs_group_count(reg_group);
6834
6835         return count;
6836 }
6837
6838 static int
6839 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6840 {
6841         int count = 0;
6842         int g_ind = 0;
6843         const struct reg_info *reg_group;
6844
6845         while ((reg_group = ixgbevf_regs[g_ind++]))
6846                 count += ixgbe_regs_group_count(reg_group);
6847
6848         return count;
6849 }
6850
6851 static int
6852 ixgbe_get_regs(struct rte_eth_dev *dev,
6853               struct rte_dev_reg_info *regs)
6854 {
6855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6856         uint32_t *data = regs->data;
6857         int g_ind = 0;
6858         int count = 0;
6859         const struct reg_info *reg_group;
6860         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6861                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6862
6863         if (data == NULL) {
6864                 regs->length = ixgbe_get_reg_length(dev);
6865                 regs->width = sizeof(uint32_t);
6866                 return 0;
6867         }
6868
6869         /* Support only full register dump */
6870         if ((regs->length == 0) ||
6871             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6872                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6873                         hw->device_id;
6874                 while ((reg_group = reg_set[g_ind++]))
6875                         count += ixgbe_read_regs_group(dev, &data[count],
6876                                 reg_group);
6877                 return 0;
6878         }
6879
6880         return -ENOTSUP;
6881 }
6882
6883 static int
6884 ixgbevf_get_regs(struct rte_eth_dev *dev,
6885                 struct rte_dev_reg_info *regs)
6886 {
6887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6888         uint32_t *data = regs->data;
6889         int g_ind = 0;
6890         int count = 0;
6891         const struct reg_info *reg_group;
6892
6893         if (data == NULL) {
6894                 regs->length = ixgbevf_get_reg_length(dev);
6895                 regs->width = sizeof(uint32_t);
6896                 return 0;
6897         }
6898
6899         /* Support only full register dump */
6900         if ((regs->length == 0) ||
6901             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6902                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6903                         hw->device_id;
6904                 while ((reg_group = ixgbevf_regs[g_ind++]))
6905                         count += ixgbe_read_regs_group(dev, &data[count],
6906                                                       reg_group);
6907                 return 0;
6908         }
6909
6910         return -ENOTSUP;
6911 }
6912
6913 static int
6914 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6915 {
6916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6917
6918         /* Return unit is byte count */
6919         return hw->eeprom.word_size * 2;
6920 }
6921
6922 static int
6923 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6924                 struct rte_dev_eeprom_info *in_eeprom)
6925 {
6926         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6927         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6928         uint16_t *data = in_eeprom->data;
6929         int first, length;
6930
6931         first = in_eeprom->offset >> 1;
6932         length = in_eeprom->length >> 1;
6933         if ((first > hw->eeprom.word_size) ||
6934             ((first + length) > hw->eeprom.word_size))
6935                 return -EINVAL;
6936
6937         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6938
6939         return eeprom->ops.read_buffer(hw, first, length, data);
6940 }
6941
6942 static int
6943 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6944                 struct rte_dev_eeprom_info *in_eeprom)
6945 {
6946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6947         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6948         uint16_t *data = in_eeprom->data;
6949         int first, length;
6950
6951         first = in_eeprom->offset >> 1;
6952         length = in_eeprom->length >> 1;
6953         if ((first > hw->eeprom.word_size) ||
6954             ((first + length) > hw->eeprom.word_size))
6955                 return -EINVAL;
6956
6957         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6958
6959         return eeprom->ops.write_buffer(hw,  first, length, data);
6960 }
6961
6962 uint16_t
6963 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6964         switch (mac_type) {
6965         case ixgbe_mac_X550:
6966         case ixgbe_mac_X550EM_x:
6967         case ixgbe_mac_X550EM_a:
6968                 return ETH_RSS_RETA_SIZE_512;
6969         case ixgbe_mac_X550_vf:
6970         case ixgbe_mac_X550EM_x_vf:
6971         case ixgbe_mac_X550EM_a_vf:
6972                 return ETH_RSS_RETA_SIZE_64;
6973         default:
6974                 return ETH_RSS_RETA_SIZE_128;
6975         }
6976 }
6977
6978 uint32_t
6979 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6980         switch (mac_type) {
6981         case ixgbe_mac_X550:
6982         case ixgbe_mac_X550EM_x:
6983         case ixgbe_mac_X550EM_a:
6984                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6985                         return IXGBE_RETA(reta_idx >> 2);
6986                 else
6987                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6988         case ixgbe_mac_X550_vf:
6989         case ixgbe_mac_X550EM_x_vf:
6990         case ixgbe_mac_X550EM_a_vf:
6991                 return IXGBE_VFRETA(reta_idx >> 2);
6992         default:
6993                 return IXGBE_RETA(reta_idx >> 2);
6994         }
6995 }
6996
6997 uint32_t
6998 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6999         switch (mac_type) {
7000         case ixgbe_mac_X550_vf:
7001         case ixgbe_mac_X550EM_x_vf:
7002         case ixgbe_mac_X550EM_a_vf:
7003                 return IXGBE_VFMRQC;
7004         default:
7005                 return IXGBE_MRQC;
7006         }
7007 }
7008
7009 uint32_t
7010 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7011         switch (mac_type) {
7012         case ixgbe_mac_X550_vf:
7013         case ixgbe_mac_X550EM_x_vf:
7014         case ixgbe_mac_X550EM_a_vf:
7015                 return IXGBE_VFRSSRK(i);
7016         default:
7017                 return IXGBE_RSSRK(i);
7018         }
7019 }
7020
7021 bool
7022 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7023         switch (mac_type) {
7024         case ixgbe_mac_82599_vf:
7025         case ixgbe_mac_X540_vf:
7026                 return 0;
7027         default:
7028                 return 1;
7029         }
7030 }
7031
7032 static int
7033 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7034                         struct rte_eth_dcb_info *dcb_info)
7035 {
7036         struct ixgbe_dcb_config *dcb_config =
7037                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7038         struct ixgbe_dcb_tc_config *tc;
7039         uint8_t i, j;
7040
7041         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7042                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7043         else
7044                 dcb_info->nb_tcs = 1;
7045
7046         if (dcb_config->vt_mode) { /* vt is enabled*/
7047                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7048                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7049                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7050                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7051                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7052                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7053                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7054                                                 i * dcb_info->nb_tcs + j;
7055                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7056                                 dcb_info->tc_queue.tc_txq[i][j].base =
7057                                                 i * dcb_info->nb_tcs + j;
7058                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7059                         }
7060                 }
7061         } else { /* vt is disabled*/
7062                 struct rte_eth_dcb_rx_conf *rx_conf =
7063                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7064                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7065                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7066                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7067                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7068                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7069                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7070                         }
7071                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7072                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7073                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7074                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7075                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7076                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7077                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7078                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7079                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7080                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7081                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7082                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7083                         }
7084                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7085                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7086                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7087                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7088                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7089                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7090                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7091                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7092                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7093                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7094                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7095                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7096                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7097                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7098                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7099                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7100                 }
7101         }
7102         for (i = 0; i < dcb_info->nb_tcs; i++) {
7103                 tc = &dcb_config->tc_config[i];
7104                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7105         }
7106         return 0;
7107 }
7108
7109 /* Update e-tag ether type */
7110 static int
7111 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7112                             uint16_t ether_type)
7113 {
7114         uint32_t etag_etype;
7115
7116         if (hw->mac.type != ixgbe_mac_X550 &&
7117             hw->mac.type != ixgbe_mac_X550EM_x &&
7118             hw->mac.type != ixgbe_mac_X550EM_a) {
7119                 return -ENOTSUP;
7120         }
7121
7122         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7123         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7124         etag_etype |= ether_type;
7125         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7126         IXGBE_WRITE_FLUSH(hw);
7127
7128         return 0;
7129 }
7130
7131 /* Config l2 tunnel ether type */
7132 static int
7133 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7134                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7135 {
7136         int ret = 0;
7137         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7138
7139         if (l2_tunnel == NULL)
7140                 return -EINVAL;
7141
7142         switch (l2_tunnel->l2_tunnel_type) {
7143         case RTE_L2_TUNNEL_TYPE_E_TAG:
7144                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7145                 break;
7146         default:
7147                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7148                 ret = -EINVAL;
7149                 break;
7150         }
7151
7152         return ret;
7153 }
7154
7155 /* Enable e-tag tunnel */
7156 static int
7157 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7158 {
7159         uint32_t etag_etype;
7160
7161         if (hw->mac.type != ixgbe_mac_X550 &&
7162             hw->mac.type != ixgbe_mac_X550EM_x &&
7163             hw->mac.type != ixgbe_mac_X550EM_a) {
7164                 return -ENOTSUP;
7165         }
7166
7167         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7168         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7169         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7170         IXGBE_WRITE_FLUSH(hw);
7171
7172         return 0;
7173 }
7174
7175 /* Enable l2 tunnel */
7176 static int
7177 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7178                            enum rte_eth_tunnel_type l2_tunnel_type)
7179 {
7180         int ret = 0;
7181         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7182
7183         switch (l2_tunnel_type) {
7184         case RTE_L2_TUNNEL_TYPE_E_TAG:
7185                 ret = ixgbe_e_tag_enable(hw);
7186                 break;
7187         default:
7188                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7189                 ret = -EINVAL;
7190                 break;
7191         }
7192
7193         return ret;
7194 }
7195
7196 /* Disable e-tag tunnel */
7197 static int
7198 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7199 {
7200         uint32_t etag_etype;
7201
7202         if (hw->mac.type != ixgbe_mac_X550 &&
7203             hw->mac.type != ixgbe_mac_X550EM_x &&
7204             hw->mac.type != ixgbe_mac_X550EM_a) {
7205                 return -ENOTSUP;
7206         }
7207
7208         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7209         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7210         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7211         IXGBE_WRITE_FLUSH(hw);
7212
7213         return 0;
7214 }
7215
7216 /* Disable l2 tunnel */
7217 static int
7218 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7219                             enum rte_eth_tunnel_type l2_tunnel_type)
7220 {
7221         int ret = 0;
7222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7223
7224         switch (l2_tunnel_type) {
7225         case RTE_L2_TUNNEL_TYPE_E_TAG:
7226                 ret = ixgbe_e_tag_disable(hw);
7227                 break;
7228         default:
7229                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7230                 ret = -EINVAL;
7231                 break;
7232         }
7233
7234         return ret;
7235 }
7236
7237 static int
7238 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7239                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7240 {
7241         int ret = 0;
7242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7243         uint32_t i, rar_entries;
7244         uint32_t rar_low, rar_high;
7245
7246         if (hw->mac.type != ixgbe_mac_X550 &&
7247             hw->mac.type != ixgbe_mac_X550EM_x &&
7248             hw->mac.type != ixgbe_mac_X550EM_a) {
7249                 return -ENOTSUP;
7250         }
7251
7252         rar_entries = ixgbe_get_num_rx_addrs(hw);
7253
7254         for (i = 1; i < rar_entries; i++) {
7255                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7256                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7257                 if ((rar_high & IXGBE_RAH_AV) &&
7258                     (rar_high & IXGBE_RAH_ADTYPE) &&
7259                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7260                      l2_tunnel->tunnel_id)) {
7261                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7262                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7263
7264                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7265
7266                         return ret;
7267                 }
7268         }
7269
7270         return ret;
7271 }
7272
7273 static int
7274 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7275                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7276 {
7277         int ret = 0;
7278         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7279         uint32_t i, rar_entries;
7280         uint32_t rar_low, rar_high;
7281
7282         if (hw->mac.type != ixgbe_mac_X550 &&
7283             hw->mac.type != ixgbe_mac_X550EM_x &&
7284             hw->mac.type != ixgbe_mac_X550EM_a) {
7285                 return -ENOTSUP;
7286         }
7287
7288         /* One entry for one tunnel. Try to remove potential existing entry. */
7289         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7290
7291         rar_entries = ixgbe_get_num_rx_addrs(hw);
7292
7293         for (i = 1; i < rar_entries; i++) {
7294                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7295                 if (rar_high & IXGBE_RAH_AV) {
7296                         continue;
7297                 } else {
7298                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7299                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7300                         rar_low = l2_tunnel->tunnel_id;
7301
7302                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7303                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7304
7305                         return ret;
7306                 }
7307         }
7308
7309         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7310                      " Please remove a rule before adding a new one.");
7311         return -EINVAL;
7312 }
7313
7314 /* Add l2 tunnel filter */
7315 static int
7316 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7317                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7318 {
7319         int ret = 0;
7320
7321         switch (l2_tunnel->l2_tunnel_type) {
7322         case RTE_L2_TUNNEL_TYPE_E_TAG:
7323                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7324                 break;
7325         default:
7326                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7327                 ret = -EINVAL;
7328                 break;
7329         }
7330
7331         return ret;
7332 }
7333
7334 /* Delete l2 tunnel filter */
7335 static int
7336 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7337                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7338 {
7339         int ret = 0;
7340
7341         switch (l2_tunnel->l2_tunnel_type) {
7342         case RTE_L2_TUNNEL_TYPE_E_TAG:
7343                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7344                 break;
7345         default:
7346                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7347                 ret = -EINVAL;
7348                 break;
7349         }
7350
7351         return ret;
7352 }
7353
7354 /**
7355  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7356  * @dev: pointer to rte_eth_dev structure
7357  * @filter_op:operation will be taken.
7358  * @arg: a pointer to specific structure corresponding to the filter_op
7359  */
7360 static int
7361 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7362                                   enum rte_filter_op filter_op,
7363                                   void *arg)
7364 {
7365         int ret = 0;
7366
7367         if (filter_op == RTE_ETH_FILTER_NOP)
7368                 return 0;
7369
7370         if (arg == NULL) {
7371                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7372                             filter_op);
7373                 return -EINVAL;
7374         }
7375
7376         switch (filter_op) {
7377         case RTE_ETH_FILTER_ADD:
7378                 ret = ixgbe_dev_l2_tunnel_filter_add
7379                         (dev,
7380                          (struct rte_eth_l2_tunnel_conf *)arg);
7381                 break;
7382         case RTE_ETH_FILTER_DELETE:
7383                 ret = ixgbe_dev_l2_tunnel_filter_del
7384                         (dev,
7385                          (struct rte_eth_l2_tunnel_conf *)arg);
7386                 break;
7387         default:
7388                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7389                 ret = -EINVAL;
7390                 break;
7391         }
7392         return ret;
7393 }
7394
7395 static int
7396 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7397 {
7398         int ret = 0;
7399         uint32_t ctrl;
7400         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7401
7402         if (hw->mac.type != ixgbe_mac_X550 &&
7403             hw->mac.type != ixgbe_mac_X550EM_x &&
7404             hw->mac.type != ixgbe_mac_X550EM_a) {
7405                 return -ENOTSUP;
7406         }
7407
7408         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7409         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7410         if (en)
7411                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7412         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7413
7414         return ret;
7415 }
7416
7417 /* Enable l2 tunnel forwarding */
7418 static int
7419 ixgbe_dev_l2_tunnel_forwarding_enable
7420         (struct rte_eth_dev *dev,
7421          enum rte_eth_tunnel_type l2_tunnel_type)
7422 {
7423         int ret = 0;
7424
7425         switch (l2_tunnel_type) {
7426         case RTE_L2_TUNNEL_TYPE_E_TAG:
7427                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7428                 break;
7429         default:
7430                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7431                 ret = -EINVAL;
7432                 break;
7433         }
7434
7435         return ret;
7436 }
7437
7438 /* Disable l2 tunnel forwarding */
7439 static int
7440 ixgbe_dev_l2_tunnel_forwarding_disable
7441         (struct rte_eth_dev *dev,
7442          enum rte_eth_tunnel_type l2_tunnel_type)
7443 {
7444         int ret = 0;
7445
7446         switch (l2_tunnel_type) {
7447         case RTE_L2_TUNNEL_TYPE_E_TAG:
7448                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7449                 break;
7450         default:
7451                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7452                 ret = -EINVAL;
7453                 break;
7454         }
7455
7456         return ret;
7457 }
7458
7459 static int
7460 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7461                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7462                              bool en)
7463 {
7464         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7465         int ret = 0;
7466         uint32_t vmtir, vmvir;
7467         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7468
7469         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7470                 PMD_DRV_LOG(ERR,
7471                             "VF id %u should be less than %u",
7472                             l2_tunnel->vf_id,
7473                             pci_dev->max_vfs);
7474                 return -EINVAL;
7475         }
7476
7477         if (hw->mac.type != ixgbe_mac_X550 &&
7478             hw->mac.type != ixgbe_mac_X550EM_x &&
7479             hw->mac.type != ixgbe_mac_X550EM_a) {
7480                 return -ENOTSUP;
7481         }
7482
7483         if (en)
7484                 vmtir = l2_tunnel->tunnel_id;
7485         else
7486                 vmtir = 0;
7487
7488         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7489
7490         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7491         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7492         if (en)
7493                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7494         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7495
7496         return ret;
7497 }
7498
7499 /* Enable l2 tunnel tag insertion */
7500 static int
7501 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7502                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7503 {
7504         int ret = 0;
7505
7506         switch (l2_tunnel->l2_tunnel_type) {
7507         case RTE_L2_TUNNEL_TYPE_E_TAG:
7508                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7509                 break;
7510         default:
7511                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7512                 ret = -EINVAL;
7513                 break;
7514         }
7515
7516         return ret;
7517 }
7518
7519 /* Disable l2 tunnel tag insertion */
7520 static int
7521 ixgbe_dev_l2_tunnel_insertion_disable
7522         (struct rte_eth_dev *dev,
7523          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7524 {
7525         int ret = 0;
7526
7527         switch (l2_tunnel->l2_tunnel_type) {
7528         case RTE_L2_TUNNEL_TYPE_E_TAG:
7529                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7530                 break;
7531         default:
7532                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7533                 ret = -EINVAL;
7534                 break;
7535         }
7536
7537         return ret;
7538 }
7539
7540 static int
7541 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7542                              bool en)
7543 {
7544         int ret = 0;
7545         uint32_t qde;
7546         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7547
7548         if (hw->mac.type != ixgbe_mac_X550 &&
7549             hw->mac.type != ixgbe_mac_X550EM_x &&
7550             hw->mac.type != ixgbe_mac_X550EM_a) {
7551                 return -ENOTSUP;
7552         }
7553
7554         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7555         if (en)
7556                 qde |= IXGBE_QDE_STRIP_TAG;
7557         else
7558                 qde &= ~IXGBE_QDE_STRIP_TAG;
7559         qde &= ~IXGBE_QDE_READ;
7560         qde |= IXGBE_QDE_WRITE;
7561         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7562
7563         return ret;
7564 }
7565
7566 /* Enable l2 tunnel tag stripping */
7567 static int
7568 ixgbe_dev_l2_tunnel_stripping_enable
7569         (struct rte_eth_dev *dev,
7570          enum rte_eth_tunnel_type l2_tunnel_type)
7571 {
7572         int ret = 0;
7573
7574         switch (l2_tunnel_type) {
7575         case RTE_L2_TUNNEL_TYPE_E_TAG:
7576                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7577                 break;
7578         default:
7579                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7580                 ret = -EINVAL;
7581                 break;
7582         }
7583
7584         return ret;
7585 }
7586
7587 /* Disable l2 tunnel tag stripping */
7588 static int
7589 ixgbe_dev_l2_tunnel_stripping_disable
7590         (struct rte_eth_dev *dev,
7591          enum rte_eth_tunnel_type l2_tunnel_type)
7592 {
7593         int ret = 0;
7594
7595         switch (l2_tunnel_type) {
7596         case RTE_L2_TUNNEL_TYPE_E_TAG:
7597                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7598                 break;
7599         default:
7600                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7601                 ret = -EINVAL;
7602                 break;
7603         }
7604
7605         return ret;
7606 }
7607
7608 /* Enable/disable l2 tunnel offload functions */
7609 static int
7610 ixgbe_dev_l2_tunnel_offload_set
7611         (struct rte_eth_dev *dev,
7612          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7613          uint32_t mask,
7614          uint8_t en)
7615 {
7616         int ret = 0;
7617
7618         if (l2_tunnel == NULL)
7619                 return -EINVAL;
7620
7621         ret = -EINVAL;
7622         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7623                 if (en)
7624                         ret = ixgbe_dev_l2_tunnel_enable(
7625                                 dev,
7626                                 l2_tunnel->l2_tunnel_type);
7627                 else
7628                         ret = ixgbe_dev_l2_tunnel_disable(
7629                                 dev,
7630                                 l2_tunnel->l2_tunnel_type);
7631         }
7632
7633         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7634                 if (en)
7635                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7636                                 dev,
7637                                 l2_tunnel);
7638                 else
7639                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7640                                 dev,
7641                                 l2_tunnel);
7642         }
7643
7644         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7645                 if (en)
7646                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7647                                 dev,
7648                                 l2_tunnel->l2_tunnel_type);
7649                 else
7650                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7651                                 dev,
7652                                 l2_tunnel->l2_tunnel_type);
7653         }
7654
7655         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7656                 if (en)
7657                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7658                                 dev,
7659                                 l2_tunnel->l2_tunnel_type);
7660                 else
7661                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7662                                 dev,
7663                                 l2_tunnel->l2_tunnel_type);
7664         }
7665
7666         return ret;
7667 }
7668
7669 static int
7670 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7671                         uint16_t port)
7672 {
7673         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7674         IXGBE_WRITE_FLUSH(hw);
7675
7676         return 0;
7677 }
7678
7679 /* There's only one register for VxLAN UDP port.
7680  * So, we cannot add several ports. Will update it.
7681  */
7682 static int
7683 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7684                      uint16_t port)
7685 {
7686         if (port == 0) {
7687                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7688                 return -EINVAL;
7689         }
7690
7691         return ixgbe_update_vxlan_port(hw, port);
7692 }
7693
7694 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7695  * UDP port, it must have a value.
7696  * So, will reset it to the original value 0.
7697  */
7698 static int
7699 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7700                      uint16_t port)
7701 {
7702         uint16_t cur_port;
7703
7704         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7705
7706         if (cur_port != port) {
7707                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7708                 return -EINVAL;
7709         }
7710
7711         return ixgbe_update_vxlan_port(hw, 0);
7712 }
7713
7714 /* Add UDP tunneling port */
7715 static int
7716 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7717                               struct rte_eth_udp_tunnel *udp_tunnel)
7718 {
7719         int ret = 0;
7720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7721
7722         if (hw->mac.type != ixgbe_mac_X550 &&
7723             hw->mac.type != ixgbe_mac_X550EM_x &&
7724             hw->mac.type != ixgbe_mac_X550EM_a) {
7725                 return -ENOTSUP;
7726         }
7727
7728         if (udp_tunnel == NULL)
7729                 return -EINVAL;
7730
7731         switch (udp_tunnel->prot_type) {
7732         case RTE_TUNNEL_TYPE_VXLAN:
7733                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7734                 break;
7735
7736         case RTE_TUNNEL_TYPE_GENEVE:
7737         case RTE_TUNNEL_TYPE_TEREDO:
7738                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7739                 ret = -EINVAL;
7740                 break;
7741
7742         default:
7743                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7744                 ret = -EINVAL;
7745                 break;
7746         }
7747
7748         return ret;
7749 }
7750
7751 /* Remove UDP tunneling port */
7752 static int
7753 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7754                               struct rte_eth_udp_tunnel *udp_tunnel)
7755 {
7756         int ret = 0;
7757         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7758
7759         if (hw->mac.type != ixgbe_mac_X550 &&
7760             hw->mac.type != ixgbe_mac_X550EM_x &&
7761             hw->mac.type != ixgbe_mac_X550EM_a) {
7762                 return -ENOTSUP;
7763         }
7764
7765         if (udp_tunnel == NULL)
7766                 return -EINVAL;
7767
7768         switch (udp_tunnel->prot_type) {
7769         case RTE_TUNNEL_TYPE_VXLAN:
7770                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7771                 break;
7772         case RTE_TUNNEL_TYPE_GENEVE:
7773         case RTE_TUNNEL_TYPE_TEREDO:
7774                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7775                 ret = -EINVAL;
7776                 break;
7777         default:
7778                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7779                 ret = -EINVAL;
7780                 break;
7781         }
7782
7783         return ret;
7784 }
7785
7786 static void
7787 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7788 {
7789         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7790
7791         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7792 }
7793
7794 static void
7795 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7796 {
7797         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7798
7799         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7800 }
7801
7802 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7803 {
7804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7805         u32 in_msg = 0;
7806
7807         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7808                 return;
7809
7810         /* PF reset VF event */
7811         if (in_msg == IXGBE_PF_CONTROL_MSG)
7812                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7813 }
7814
7815 static int
7816 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7817 {
7818         uint32_t eicr;
7819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7820         struct ixgbe_interrupt *intr =
7821                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7822         ixgbevf_intr_disable(hw);
7823
7824         /* read-on-clear nic registers here */
7825         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7826         intr->flags = 0;
7827
7828         /* only one misc vector supported - mailbox */
7829         eicr &= IXGBE_VTEICR_MASK;
7830         if (eicr == IXGBE_MISC_VEC_ID)
7831                 intr->flags |= IXGBE_FLAG_MAILBOX;
7832
7833         return 0;
7834 }
7835
7836 static int
7837 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7838 {
7839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7840         struct ixgbe_interrupt *intr =
7841                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7842
7843         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7844                 ixgbevf_mbx_process(dev);
7845                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7846         }
7847
7848         ixgbevf_intr_enable(hw);
7849
7850         return 0;
7851 }
7852
7853 static void
7854 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7855                               void *param)
7856 {
7857         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7858
7859         ixgbevf_dev_interrupt_get_status(dev);
7860         ixgbevf_dev_interrupt_action(dev);
7861 }
7862
7863 /**
7864  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7865  *  @hw: pointer to hardware structure
7866  *
7867  *  Stops the transmit data path and waits for the HW to internally empty
7868  *  the Tx security block
7869  **/
7870 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7871 {
7872 #define IXGBE_MAX_SECTX_POLL 40
7873
7874         int i;
7875         int sectxreg;
7876
7877         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7878         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7879         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7880         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7881                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7882                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7883                         break;
7884                 /* Use interrupt-safe sleep just in case */
7885                 usec_delay(1000);
7886         }
7887
7888         /* For informational purposes only */
7889         if (i >= IXGBE_MAX_SECTX_POLL)
7890                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7891                          "path fully disabled.  Continuing with init.\n");
7892
7893         return IXGBE_SUCCESS;
7894 }
7895
7896 /**
7897  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7898  *  @hw: pointer to hardware structure
7899  *
7900  *  Enables the transmit data path.
7901  **/
7902 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7903 {
7904         uint32_t sectxreg;
7905
7906         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7907         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7908         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7909         IXGBE_WRITE_FLUSH(hw);
7910
7911         return IXGBE_SUCCESS;
7912 }
7913
7914 int
7915 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
7916 {
7917         struct ixgbe_hw *hw;
7918         struct rte_eth_dev *dev;
7919         uint32_t ctrl;
7920
7921         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
7922
7923         dev = &rte_eth_devices[port];
7924         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7925
7926         /* Stop the data paths */
7927         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
7928                 return -ENOTSUP;
7929         /*
7930          * Workaround:
7931          * As no ixgbe_disable_sec_rx_path equivalent is
7932          * implemented for tx in the base code, and we are
7933          * not allowed to modify the base code in DPDK, so
7934          * just call the hand-written one directly for now.
7935          * The hardware support has been checked by
7936          * ixgbe_disable_sec_rx_path().
7937          */
7938         ixgbe_disable_sec_tx_path_generic(hw);
7939
7940         /* Enable Ethernet CRC (required by MACsec offload) */
7941         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
7942         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
7943         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
7944
7945         /* Enable the TX and RX crypto engines */
7946         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7947         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
7948         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
7949
7950         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
7951         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
7952         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
7953
7954         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
7955         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
7956         ctrl |= 0x3;
7957         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
7958
7959         /* Enable SA lookup */
7960         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
7961         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
7962         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
7963                      IXGBE_LSECTXCTRL_AUTH;
7964         ctrl |= IXGBE_LSECTXCTRL_AISCI;
7965         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
7966         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
7967         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
7968
7969         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
7970         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
7971         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
7972         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
7973         if (rp)
7974                 ctrl |= IXGBE_LSECRXCTRL_RP;
7975         else
7976                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
7977         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
7978
7979         /* Start the data paths */
7980         ixgbe_enable_sec_rx_path(hw);
7981         /*
7982          * Workaround:
7983          * As no ixgbe_enable_sec_rx_path equivalent is
7984          * implemented for tx in the base code, and we are
7985          * not allowed to modify the base code in DPDK, so
7986          * just call the hand-written one directly for now.
7987          */
7988         ixgbe_enable_sec_tx_path_generic(hw);
7989
7990         return 0;
7991 }
7992
7993 int
7994 rte_pmd_ixgbe_macsec_disable(uint8_t port)
7995 {
7996         struct ixgbe_hw *hw;
7997         struct rte_eth_dev *dev;
7998         uint32_t ctrl;
7999
8000         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8001
8002         dev = &rte_eth_devices[port];
8003         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8004
8005         /* Stop the data paths */
8006         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8007                 return -ENOTSUP;
8008         /*
8009          * Workaround:
8010          * As no ixgbe_disable_sec_rx_path equivalent is
8011          * implemented for tx in the base code, and we are
8012          * not allowed to modify the base code in DPDK, so
8013          * just call the hand-written one directly for now.
8014          * The hardware support has been checked by
8015          * ixgbe_disable_sec_rx_path().
8016          */
8017         ixgbe_disable_sec_tx_path_generic(hw);
8018
8019         /* Disable the TX and RX crypto engines */
8020         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8021         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8022         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8023
8024         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8025         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8026         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8027
8028         /* Disable SA lookup */
8029         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8030         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8031         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8032         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8033
8034         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8035         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8036         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8037         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8038
8039         /* Start the data paths */
8040         ixgbe_enable_sec_rx_path(hw);
8041         /*
8042          * Workaround:
8043          * As no ixgbe_enable_sec_rx_path equivalent is
8044          * implemented for tx in the base code, and we are
8045          * not allowed to modify the base code in DPDK, so
8046          * just call the hand-written one directly for now.
8047          */
8048         ixgbe_enable_sec_tx_path_generic(hw);
8049
8050         return 0;
8051 }
8052
8053 int
8054 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8055 {
8056         struct ixgbe_hw *hw;
8057         struct rte_eth_dev *dev;
8058         uint32_t ctrl;
8059
8060         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8061
8062         dev = &rte_eth_devices[port];
8063         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8064
8065         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8066         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8067
8068         ctrl = mac[4] | (mac[5] << 8);
8069         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8070
8071         return 0;
8072 }
8073
8074 int
8075 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8076 {
8077         struct ixgbe_hw *hw;
8078         struct rte_eth_dev *dev;
8079         uint32_t ctrl;
8080
8081         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8082
8083         dev = &rte_eth_devices[port];
8084         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8085
8086         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8087         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8088
8089         pi = rte_cpu_to_be_16(pi);
8090         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8091         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8092
8093         return 0;
8094 }
8095
8096 int
8097 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8098                                  uint32_t pn, uint8_t *key)
8099 {
8100         struct ixgbe_hw *hw;
8101         struct rte_eth_dev *dev;
8102         uint32_t ctrl, i;
8103
8104         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8105
8106         dev = &rte_eth_devices[port];
8107         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8108
8109         if (idx != 0 && idx != 1)
8110                 return -EINVAL;
8111
8112         if (an >= 4)
8113                 return -EINVAL;
8114
8115         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8116
8117         /* Set the PN and key */
8118         pn = rte_cpu_to_be_32(pn);
8119         if (idx == 0) {
8120                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8121
8122                 for (i = 0; i < 4; i++) {
8123                         ctrl = (key[i * 4 + 0] <<  0) |
8124                                (key[i * 4 + 1] <<  8) |
8125                                (key[i * 4 + 2] << 16) |
8126                                (key[i * 4 + 3] << 24);
8127                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8128                 }
8129         } else {
8130                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8131
8132                 for (i = 0; i < 4; i++) {
8133                         ctrl = (key[i * 4 + 0] <<  0) |
8134                                (key[i * 4 + 1] <<  8) |
8135                                (key[i * 4 + 2] << 16) |
8136                                (key[i * 4 + 3] << 24);
8137                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8138                 }
8139         }
8140
8141         /* Set AN and select the SA */
8142         ctrl = (an << idx * 2) | (idx << 4);
8143         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8144
8145         return 0;
8146 }
8147
8148 int
8149 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8150                                  uint32_t pn, uint8_t *key)
8151 {
8152         struct ixgbe_hw *hw;
8153         struct rte_eth_dev *dev;
8154         uint32_t ctrl, i;
8155
8156         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8157
8158         dev = &rte_eth_devices[port];
8159         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8160
8161         if (idx != 0 && idx != 1)
8162                 return -EINVAL;
8163
8164         if (an >= 4)
8165                 return -EINVAL;
8166
8167         /* Set the PN */
8168         pn = rte_cpu_to_be_32(pn);
8169         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8170
8171         /* Set the key */
8172         for (i = 0; i < 4; i++) {
8173                 ctrl = (key[i * 4 + 0] <<  0) |
8174                        (key[i * 4 + 1] <<  8) |
8175                        (key[i * 4 + 2] << 16) |
8176                        (key[i * 4 + 3] << 24);
8177                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8178         }
8179
8180         /* Set the AN and validate the SA */
8181         ctrl = an | (1 << 2);
8182         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8183
8184         return 0;
8185 }
8186
8187 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8188 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8189 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8190 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8191 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8192 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");