drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Timer value included in XOFF frames. */
  63 #define IXGBE_FC_PAUSE 0x680
  64
  65 /*Default value of Max Rx Queue*/
  66 #define IXGBE_MAX_RX_QUEUE_NUM 128
  67
  68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  71
  72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  75
  76 /*
  77  *  Default values for RX/TX configuration
  78  */
  79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  80 #define IXGBE_DEFAULT_RX_PTHRESH      8
  81 #define IXGBE_DEFAULT_RX_HTHRESH      8
  82 #define IXGBE_DEFAULT_RX_WTHRESH      0
  83
  84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  85 #define IXGBE_DEFAULT_TX_PTHRESH      32
  86 #define IXGBE_DEFAULT_TX_HTHRESH      0
  87 #define IXGBE_DEFAULT_TX_WTHRESH      0
  88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  89
  90 /* Bit shift and mask */
  91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  94 #define IXGBE_8_BIT_MASK   UINT8_MAX
  95
  96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  97
  98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  99
 100 /* Additional timesync values. */
 101 #define NSEC_PER_SEC             1000000000L
 102 #define IXGBE_INCVAL_10GB        0x66666666
 103 #define IXGBE_INCVAL_1GB         0x40000000
 104 #define IXGBE_INCVAL_100         0x50000000
 105 #define IXGBE_INCVAL_SHIFT_10GB  28
 106 #define IXGBE_INCVAL_SHIFT_1GB   24
 107 #define IXGBE_INCVAL_SHIFT_100   21
 108 #define IXGBE_INCVAL_SHIFT_82599 7
 109 #define IXGBE_INCPER_SHIFT_82599 24
 110
 111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 115 #define IXGBE_ETAG_ETYPE                       0x00005084
 116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 118 #define IXGBE_RAH_ADTYPE                       0x40000000
 119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 124 #define IXGBE_VTEICR_MASK                      0x07
 125
 126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 128
 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 148                                 int wait_to_complete);
 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 150                                 struct rte_eth_stats *stats);
 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 152                                 struct rte_eth_xstat *xstats, unsigned n);
 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 154                                   struct rte_eth_xstat *xstats, unsigned n);
 155 static int
 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 157                 uint64_t *values, unsigned int n);
 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 161         struct rte_eth_xstat_name *xstats_names,
 162         unsigned int size);
 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 165 static int ixgbe_dev_xstats_get_names_by_id(
 166         struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         const uint64_t *ids,
 169         unsigned int limit);
 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 171                                              uint16_t queue_id,
 172                                              uint8_t stat_idx,
 173                                              uint8_t is_rx);
 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 175                                  size_t fw_size);
 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_dev_info *dev_info);
 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 180                                  struct rte_eth_dev_info *dev_info);
 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 182
 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 184                 uint16_t vlan_id, int on);
 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 186                                enum rte_vlan_type vlan_type,
 187                                uint16_t tpid_id);
 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 189                 uint16_t queue, bool on);
 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 191                 int on);
 192 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 193 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 194 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 195 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 196 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 197
 198 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 199 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 200 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 201                                struct rte_eth_fc_conf *fc_conf);
 202 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 203                                struct rte_eth_fc_conf *fc_conf);
 204 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 205                 struct rte_eth_pfc_conf *pfc_conf);
 206 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 207                         struct rte_eth_rss_reta_entry64 *reta_conf,
 208                         uint16_t reta_size);
 209 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 213 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 214 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 215 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 218                                       struct rte_intr_handle *handle);
 219 static void ixgbe_dev_interrupt_handler(void *param);
 220 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 221 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 222                          uint32_t index, uint32_t pool);
 223 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 224 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 225                                            struct ether_addr *mac_addr);
 226 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 227 static bool is_device_supported(struct rte_eth_dev *dev,
 228                                 struct rte_pci_driver *drv);
 229
 230 /* For Virtual Function support */
 231 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 232 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 233 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 234 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 235 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 236                                    int wait_to_complete);
 237 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 238 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 239 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 240 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 241 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 242 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 243                 struct rte_eth_stats *stats);
 244 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 245 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 246                 uint16_t vlan_id, int on);
 247 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 248                 uint16_t queue, int on);
 249 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 250 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 251 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 252                                             uint16_t queue_id);
 253 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 254                                              uint16_t queue_id);
 255 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 256                                  uint8_t queue, uint8_t msix_vector);
 257 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 259 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 260
 261 /* For Eth VMDQ APIs support */
 262 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 263                 ether_addr * mac_addr, uint8_t on);
 264 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 265 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 266                 struct rte_eth_mirror_conf *mirror_conf,
 267                 uint8_t rule_id, uint8_t on);
 268 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 269                 uint8_t rule_id);
 270 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 271                                           uint16_t queue_id);
 272 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 273                                            uint16_t queue_id);
 274 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 275                                uint8_t queue, uint8_t msix_vector);
 276 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 277
 278 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 279                                 struct ether_addr *mac_addr,
 280                                 uint32_t index, uint32_t pool);
 281 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 282 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 283                                              struct ether_addr *mac_addr);
 284 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 285                         struct rte_eth_syn_filter *filter);
 286 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 287                         enum rte_filter_op filter_op,
 288                         void *arg);
 289 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 290                         struct ixgbe_5tuple_filter *filter);
 291 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 292                         struct ixgbe_5tuple_filter *filter);
 293 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 294                                 enum rte_filter_op filter_op,
 295                                 void *arg);
 296 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 297                         struct rte_eth_ntuple_filter *filter);
 298 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 299                                 enum rte_filter_op filter_op,
 300                                 void *arg);
 301 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 302                         struct rte_eth_ethertype_filter *filter);
 303 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 304                      enum rte_filter_type filter_type,
 305                      enum rte_filter_op filter_op,
 306                      void *arg);
 307 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 308
 309 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 310                                       struct ether_addr *mc_addr_set,
 311                                       uint32_t nb_mc_addr);
 312 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 313                                    struct rte_eth_dcb_info *dcb_info);
 314
 315 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 316 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 317                             struct rte_dev_reg_info *regs);
 318 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 319 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 320                                 struct rte_dev_eeprom_info *eeprom);
 321 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 322                                 struct rte_dev_eeprom_info *eeprom);
 323
 324 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 325                                  struct rte_eth_dev_module_info *modinfo);
 326 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 327                                    struct rte_dev_eeprom_info *info);
 328
 329 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 330 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 331                                 struct rte_dev_reg_info *regs);
 332
 333 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 334 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 335 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 336                                             struct timespec *timestamp,
 337                                             uint32_t flags);
 338 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 339                                             struct timespec *timestamp);
 340 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 341 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 342                                    struct timespec *timestamp);
 343 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 344                                    const struct timespec *timestamp);
 345 static void ixgbevf_dev_interrupt_handler(void *param);
 346
 347 static int ixgbe_dev_l2_tunnel_eth_type_conf
 348         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 349 static int ixgbe_dev_l2_tunnel_offload_set
 350         (struct rte_eth_dev *dev,
 351          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 352          uint32_t mask,
 353          uint8_t en);
 354 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 355                                              enum rte_filter_op filter_op,
 356                                              void *arg);
 357
 358 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 359                                          struct rte_eth_udp_tunnel *udp_tunnel);
 360 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 361                                          struct rte_eth_udp_tunnel *udp_tunnel);
 362 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 363 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 364
 365 /*
 366  * Define VF Stats MACRO for Non "cleared on read" register
 367  */
 368 #define UPDATE_VF_STAT(reg, last, cur)                          \
 369 {                                                               \
 370         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 371         cur += (latest - last) & UINT_MAX;                      \
 372         last = latest;                                          \
 373 }
 374
 375 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 376 {                                                                \
 377         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 378         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 379         u64 latest = ((new_msb << 32) | new_lsb);                \
 380         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 381         last = latest;                                           \
 382 }
 383
 384 #define IXGBE_SET_HWSTRIP(h, q) do {\
 385                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 386                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 387                 (h)->bitmap[idx] |= 1 << bit;\
 388         } while (0)
 389
 390 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 391                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 392                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 393                 (h)->bitmap[idx] &= ~(1 << bit);\
 394         } while (0)
 395
 396 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 397                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 398                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 399                 (r) = (h)->bitmap[idx] >> bit & 1;\
 400         } while (0)
 401
 402 int ixgbe_logtype_init;
 403 int ixgbe_logtype_driver;
 404
 405 /*
 406  * The set of PCI devices this driver supports
 407  */
 408 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 457 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 459 #endif
 460         { .vendor_id = 0, /* sentinel */ },
 461 };
 462
 463 /*
 464  * The set of PCI devices this driver supports (for 82599 VF)
 465  */
 466 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 static const struct rte_eth_desc_lim rx_desc_lim = {
 481         .nb_max = IXGBE_MAX_RING_DESC,
 482         .nb_min = IXGBE_MIN_RING_DESC,
 483         .nb_align = IXGBE_RXD_ALIGN,
 484 };
 485
 486 static const struct rte_eth_desc_lim tx_desc_lim = {
 487         .nb_max = IXGBE_MAX_RING_DESC,
 488         .nb_min = IXGBE_MIN_RING_DESC,
 489         .nb_align = IXGBE_TXD_ALIGN,
 490         .nb_seg_max = IXGBE_TX_MAX_SEG,
 491         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 492 };
 493
 494 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 495         .dev_configure        = ixgbe_dev_configure,
 496         .dev_start            = ixgbe_dev_start,
 497         .dev_stop             = ixgbe_dev_stop,
 498         .dev_set_link_up    = ixgbe_dev_set_link_up,
 499         .dev_set_link_down  = ixgbe_dev_set_link_down,
 500         .dev_close            = ixgbe_dev_close,
 501         .dev_reset            = ixgbe_dev_reset,
 502         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 503         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 504         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 505         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 506         .link_update          = ixgbe_dev_link_update,
 507         .stats_get            = ixgbe_dev_stats_get,
 508         .xstats_get           = ixgbe_dev_xstats_get,
 509         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 510         .stats_reset          = ixgbe_dev_stats_reset,
 511         .xstats_reset         = ixgbe_dev_xstats_reset,
 512         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 513         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 514         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 515         .fw_version_get       = ixgbe_fw_version_get,
 516         .dev_infos_get        = ixgbe_dev_info_get,
 517         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 518         .mtu_set              = ixgbe_dev_mtu_set,
 519         .vlan_filter_set      = ixgbe_vlan_filter_set,
 520         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 521         .vlan_offload_set     = ixgbe_vlan_offload_set,
 522         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 523         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 524         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 525         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 526         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 527         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 528         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 529         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 530         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 531         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 532         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 533         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 534         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 535         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 536         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 537         .dev_led_on           = ixgbe_dev_led_on,
 538         .dev_led_off          = ixgbe_dev_led_off,
 539         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 540         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 541         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 542         .mac_addr_add         = ixgbe_add_rar,
 543         .mac_addr_remove      = ixgbe_remove_rar,
 544         .mac_addr_set         = ixgbe_set_default_mac_addr,
 545         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 546         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 547         .mirror_rule_set      = ixgbe_mirror_rule_set,
 548         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 549         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 550         .reta_update          = ixgbe_dev_rss_reta_update,
 551         .reta_query           = ixgbe_dev_rss_reta_query,
 552         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 553         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 554         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 555         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 556         .rxq_info_get         = ixgbe_rxq_info_get,
 557         .txq_info_get         = ixgbe_txq_info_get,
 558         .timesync_enable      = ixgbe_timesync_enable,
 559         .timesync_disable     = ixgbe_timesync_disable,
 560         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 561         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 562         .get_reg              = ixgbe_get_regs,
 563         .get_eeprom_length    = ixgbe_get_eeprom_length,
 564         .get_eeprom           = ixgbe_get_eeprom,
 565         .set_eeprom           = ixgbe_set_eeprom,
 566         .get_module_info      = ixgbe_get_module_info,
 567         .get_module_eeprom    = ixgbe_get_module_eeprom,
 568         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 569         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 570         .timesync_read_time   = ixgbe_timesync_read_time,
 571         .timesync_write_time  = ixgbe_timesync_write_time,
 572         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 573         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 574         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 575         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 576         .tm_ops_get           = ixgbe_tm_ops_get,
 577 };
 578
 579 /*
 580  * dev_ops for virtual function, bare necessities for basic vf
 581  * operation have been implemented
 582  */
 583 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 584         .dev_configure        = ixgbevf_dev_configure,
 585         .dev_start            = ixgbevf_dev_start,
 586         .dev_stop             = ixgbevf_dev_stop,
 587         .link_update          = ixgbevf_dev_link_update,
 588         .stats_get            = ixgbevf_dev_stats_get,
 589         .xstats_get           = ixgbevf_dev_xstats_get,
 590         .stats_reset          = ixgbevf_dev_stats_reset,
 591         .xstats_reset         = ixgbevf_dev_stats_reset,
 592         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 593         .dev_close            = ixgbevf_dev_close,
 594         .dev_reset            = ixgbevf_dev_reset,
 595         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 596         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 597         .dev_infos_get        = ixgbevf_dev_info_get,
 598         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 599         .mtu_set              = ixgbevf_dev_set_mtu,
 600         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 601         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 602         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 603         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 604         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 605         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 606         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 607         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 608         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 609         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 610         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 611         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 612         .mac_addr_add         = ixgbevf_add_mac_addr,
 613         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 614         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 615         .rxq_info_get         = ixgbe_rxq_info_get,
 616         .txq_info_get         = ixgbe_txq_info_get,
 617         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 618         .get_reg              = ixgbevf_get_regs,
 619         .reta_update          = ixgbe_dev_rss_reta_update,
 620         .reta_query           = ixgbe_dev_rss_reta_query,
 621         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 622         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 623 };
 624
 625 /* store statistics names and its offset in stats structure */
 626 struct rte_ixgbe_xstats_name_off {
 627         char name[RTE_ETH_XSTATS_NAME_SIZE];
 628         unsigned offset;
 629 };
 630
 631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 632         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 633         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 634         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 635         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 636         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 637         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 638         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 639         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 640         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 641         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 642         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 643         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 644         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 645         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 646         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 647                 prc1023)},
 648         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 649                 prc1522)},
 650         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 651         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 652         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 653         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 654         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 655         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 656         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 657         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 658         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 659         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 660         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 661         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 662         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 663         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 664         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 665         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 666         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 667                 ptc1023)},
 668         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 669                 ptc1522)},
 670         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 671         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 672         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 673         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 674
 675         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 676                 fdirustat_add)},
 677         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 678                 fdirustat_remove)},
 679         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 680                 fdirfstat_fadd)},
 681         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 682                 fdirfstat_fremove)},
 683         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 684                 fdirmatch)},
 685         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 686                 fdirmiss)},
 687
 688         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 689         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 690         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 691                 fclast)},
 692         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 693         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 694         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 695         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 696         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 697                 fcoe_noddp)},
 698         {"rx_fcoe_no_direct_data_placement_ext_buff",
 699                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 700
 701         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 702                 lxontxc)},
 703         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 704                 lxonrxc)},
 705         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxofftxc)},
 707         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxoffrxc)},
 709         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 710 };
 711
 712 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 713                            sizeof(rte_ixgbe_stats_strings[0]))
 714
 715 /* MACsec statistics */
 716 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 717         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 718                 out_pkts_untagged)},
 719         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 720                 out_pkts_encrypted)},
 721         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_protected)},
 723         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_octets_encrypted)},
 725         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_octets_protected)},
 727         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 728                 in_pkts_untagged)},
 729         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 730                 in_pkts_badtag)},
 731         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_nosci)},
 733         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_unknownsci)},
 735         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 736                 in_octets_decrypted)},
 737         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 738                 in_octets_validated)},
 739         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_unchecked)},
 741         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_delayed)},
 743         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_late)},
 745         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_ok)},
 747         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_invalid)},
 749         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_notvalid)},
 751         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_unusedsa)},
 753         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notusingsa)},
 755 };
 756
 757 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 758                            sizeof(rte_ixgbe_macsec_strings[0]))
 759
 760 /* Per-queue statistics */
 761 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 762         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 763         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 764         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 765         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 766 };
 767
 768 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 769                            sizeof(rte_ixgbe_rxq_strings[0]))
 770 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 771
 772 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 773         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 774         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 775         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 776                 pxon2offc)},
 777 };
 778
 779 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 780                            sizeof(rte_ixgbe_txq_strings[0]))
 781 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 782
 783 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 784         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 785 };
 786
 787 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 788                 sizeof(rte_ixgbevf_stats_strings[0]))
 789
 790 /*
 791  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 792  */
 793 static inline int
 794 ixgbe_is_sfp(struct ixgbe_hw *hw)
 795 {
 796         switch (hw->phy.type) {
 797         case ixgbe_phy_sfp_avago:
 798         case ixgbe_phy_sfp_ftl:
 799         case ixgbe_phy_sfp_intel:
 800         case ixgbe_phy_sfp_unknown:
 801         case ixgbe_phy_sfp_passive_tyco:
 802         case ixgbe_phy_sfp_passive_unknown:
 803                 return 1;
 804         default:
 805                 return 0;
 806         }
 807 }
 808
 809 static inline int32_t
 810 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 811 {
 812         uint32_t ctrl_ext;
 813         int32_t status;
 814
 815         status = ixgbe_reset_hw(hw);
 816
 817         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 818         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 819         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 820         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 821         IXGBE_WRITE_FLUSH(hw);
 822
 823         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 824                 status = IXGBE_SUCCESS;
 825         return status;
 826 }
 827
 828 static inline void
 829 ixgbe_enable_intr(struct rte_eth_dev *dev)
 830 {
 831         struct ixgbe_interrupt *intr =
 832                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 833         struct ixgbe_hw *hw =
 834                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 835
 836         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 837         IXGBE_WRITE_FLUSH(hw);
 838 }
 839
 840 /*
 841  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 842  */
 843 static void
 844 ixgbe_disable_intr(struct ixgbe_hw *hw)
 845 {
 846         PMD_INIT_FUNC_TRACE();
 847
 848         if (hw->mac.type == ixgbe_mac_82598EB) {
 849                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 850         } else {
 851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 854         }
 855         IXGBE_WRITE_FLUSH(hw);
 856 }
 857
 858 /*
 859  * This function resets queue statistics mapping registers.
 860  * From Niantic datasheet, Initialization of Statistics section:
 861  * "...if software requires the queue counters, the RQSMR and TQSM registers
 862  * must be re-programmed following a device reset.
 863  */
 864 static void
 865 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 866 {
 867         uint32_t i;
 868
 869         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 870                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 871                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 872         }
 873 }
 874
 875
 876 static int
 877 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 878                                   uint16_t queue_id,
 879                                   uint8_t stat_idx,
 880                                   uint8_t is_rx)
 881 {
 882 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 883 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 884 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 885
 886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 887         struct ixgbe_stat_mapping_registers *stat_mappings =
 888                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 889         uint32_t qsmr_mask = 0;
 890         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 891         uint32_t q_map;
 892         uint8_t n, offset;
 893
 894         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 895                 (hw->mac.type != ixgbe_mac_X540) &&
 896                 (hw->mac.type != ixgbe_mac_X550) &&
 897                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 898                 (hw->mac.type != ixgbe_mac_X550EM_a))
 899                 return -ENOSYS;
 900
 901         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 902                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 903                      queue_id, stat_idx);
 904
 905         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 906         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 907                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 908                 return -EIO;
 909         }
 910         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 911
 912         /* Now clear any previous stat_idx set */
 913         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 914         if (!is_rx)
 915                 stat_mappings->tqsm[n] &= ~clearing_mask;
 916         else
 917                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 918
 919         q_map = (uint32_t)stat_idx;
 920         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 921         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 922         if (!is_rx)
 923                 stat_mappings->tqsm[n] |= qsmr_mask;
 924         else
 925                 stat_mappings->rqsmr[n] |= qsmr_mask;
 926
 927         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 928                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 929                      queue_id, stat_idx);
 930         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 931                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 932
 933         /* Now write the mapping in the appropriate register */
 934         if (is_rx) {
 935                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 936                              stat_mappings->rqsmr[n], n);
 937                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 938         } else {
 939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 940                              stat_mappings->tqsm[n], n);
 941                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 942         }
 943         return 0;
 944 }
 945
 946 static void
 947 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 948 {
 949         struct ixgbe_stat_mapping_registers *stat_mappings =
 950                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 952         int i;
 953
 954         /* write whatever was in stat mapping table to the NIC */
 955         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 956                 /* rx */
 957                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 958
 959                 /* tx */
 960                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 961         }
 962 }
 963
 964 static void
 965 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 966 {
 967         uint8_t i;
 968         struct ixgbe_dcb_tc_config *tc;
 969         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 970
 971         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 972         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 973         for (i = 0; i < dcb_max_tc; i++) {
 974                 tc = &dcb_config->tc_config[i];
 975                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 976                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 977                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 978                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 979                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 980                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 981                 tc->pfc = ixgbe_dcb_pfc_disabled;
 982         }
 983
 984         /* Initialize default user to priority mapping, UPx->TC0 */
 985         tc = &dcb_config->tc_config[0];
 986         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 987         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 988         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 989                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 990                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 991         }
 992         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 993         dcb_config->pfc_mode_enable = false;
 994         dcb_config->vt_mode = true;
 995         dcb_config->round_robin_enable = false;
 996         /* support all DCB capabilities in 82599 */
 997         dcb_config->support.capabilities = 0xFF;
 998
 999         /*we only support 4 Tcs for X540, X550 */
1000         if (hw->mac.type == ixgbe_mac_X540 ||
1001                 hw->mac.type == ixgbe_mac_X550 ||
1002                 hw->mac.type == ixgbe_mac_X550EM_x ||
1003                 hw->mac.type == ixgbe_mac_X550EM_a) {
1004                 dcb_config->num_tcs.pg_tcs = 4;
1005                 dcb_config->num_tcs.pfc_tcs = 4;
1006         }
1007 }
1008
1009 /*
1010  * Ensure that all locks are released before first NVM or PHY access
1011  */
1012 static void
1013 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1014 {
1015         uint16_t mask;
1016
1017         /*
1018          * Phy lock should not fail in this early stage. If this is the case,
1019          * it is due to an improper exit of the application.
1020          * So force the release of the faulty lock. Release of common lock
1021          * is done automatically by swfw_sync function.
1022          */
1023         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1024         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1025                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1026         }
1027         ixgbe_release_swfw_semaphore(hw, mask);
1028
1029         /*
1030          * These ones are more tricky since they are common to all ports; but
1031          * swfw_sync retries last long enough (1s) to be almost sure that if
1032          * lock can not be taken it is due to an improper lock of the
1033          * semaphore.
1034          */
1035         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1036         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1037                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1038         }
1039         ixgbe_release_swfw_semaphore(hw, mask);
1040 }
1041
1042 /*
1043  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1044  * It returns 0 on success.
1045  */
1046 static int
1047 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1048 {
1049         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1050         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1051         struct ixgbe_hw *hw =
1052                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1053         struct ixgbe_vfta *shadow_vfta =
1054                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1055         struct ixgbe_hwstrip *hwstrip =
1056                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1057         struct ixgbe_dcb_config *dcb_config =
1058                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1059         struct ixgbe_filter_info *filter_info =
1060                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1061         struct ixgbe_bw_conf *bw_conf =
1062                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1063         uint32_t ctrl_ext;
1064         uint16_t csum;
1065         int diag, i;
1066
1067         PMD_INIT_FUNC_TRACE();
1068
1069         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1070         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1071         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1072         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1073
1074         /*
1075          * For secondary processes, we don't initialise any further as primary
1076          * has already done this work. Only check we don't need a different
1077          * RX and TX function.
1078          */
1079         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1080                 struct ixgbe_tx_queue *txq;
1081                 /* TX queue function in primary, set by last queue initialized
1082                  * Tx queue may not initialized by primary process
1083                  */
1084                 if (eth_dev->data->tx_queues) {
1085                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1086                         ixgbe_set_tx_function(eth_dev, txq);
1087                 } else {
1088                         /* Use default TX function if we get here */
1089                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1090                                      "Using default TX function.");
1091                 }
1092
1093                 ixgbe_set_rx_function(eth_dev);
1094
1095                 return 0;
1096         }
1097
1098         rte_eth_copy_pci_info(eth_dev, pci_dev);
1099
1100         /* Vendor and Device ID need to be set before init of shared code */
1101         hw->device_id = pci_dev->id.device_id;
1102         hw->vendor_id = pci_dev->id.vendor_id;
1103         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1104         hw->allow_unsupported_sfp = 1;
1105
1106         /* Initialize the shared code (base driver) */
1107 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1108         diag = ixgbe_bypass_init_shared_code(hw);
1109 #else
1110         diag = ixgbe_init_shared_code(hw);
1111 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1112
1113         if (diag != IXGBE_SUCCESS) {
1114                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1115                 return -EIO;
1116         }
1117
1118         /* pick up the PCI bus settings for reporting later */
1119         ixgbe_get_bus_info(hw);
1120
1121         /* Unlock any pending hardware semaphore */
1122         ixgbe_swfw_lock_reset(hw);
1123
1124 #ifdef RTE_LIBRTE_SECURITY
1125         /* Initialize security_ctx only for primary process*/
1126         if (ixgbe_ipsec_ctx_create(eth_dev))
1127                 return -ENOMEM;
1128 #endif
1129
1130         /* Initialize DCB configuration*/
1131         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1132         ixgbe_dcb_init(hw, dcb_config);
1133         /* Get Hardware Flow Control setting */
1134         hw->fc.requested_mode = ixgbe_fc_full;
1135         hw->fc.current_mode = ixgbe_fc_full;
1136         hw->fc.pause_time = IXGBE_FC_PAUSE;
1137         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1138                 hw->fc.low_water[i] = IXGBE_FC_LO;
1139                 hw->fc.high_water[i] = IXGBE_FC_HI;
1140         }
1141         hw->fc.send_xon = 1;
1142
1143         /* Make sure we have a good EEPROM before we read from it */
1144         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1145         if (diag != IXGBE_SUCCESS) {
1146                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1147                 return -EIO;
1148         }
1149
1150 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1151         diag = ixgbe_bypass_init_hw(hw);
1152 #else
1153         diag = ixgbe_init_hw(hw);
1154 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1155
1156         /*
1157          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1158          * is called too soon after the kernel driver unbinding/binding occurs.
1159          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1160          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1161          * also called. See ixgbe_identify_phy_82599(). The reason for the
1162          * failure is not known, and only occuts when virtualisation features
1163          * are disabled in the bios. A delay of 100ms  was found to be enough by
1164          * trial-and-error, and is doubled to be safe.
1165          */
1166         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1167                 rte_delay_ms(200);
1168                 diag = ixgbe_init_hw(hw);
1169         }
1170
1171         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1172                 diag = IXGBE_SUCCESS;
1173
1174         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1175                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1176                              "LOM.  Please be aware there may be issues associated "
1177                              "with your hardware.");
1178                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1179                              "please contact your Intel or hardware representative "
1180                              "who provided you with this hardware.");
1181         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1182                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1183         if (diag) {
1184                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1185                 return -EIO;
1186         }
1187
1188         /* Reset the hw statistics */
1189         ixgbe_dev_stats_reset(eth_dev);
1190
1191         /* disable interrupt */
1192         ixgbe_disable_intr(hw);
1193
1194         /* reset mappings for queue statistics hw counters*/
1195         ixgbe_reset_qstat_mappings(hw);
1196
1197         /* Allocate memory for storing MAC addresses */
1198         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1199                                                hw->mac.num_rar_entries, 0);
1200         if (eth_dev->data->mac_addrs == NULL) {
1201                 PMD_INIT_LOG(ERR,
1202                              "Failed to allocate %u bytes needed to store "
1203                              "MAC addresses",
1204                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1205                 return -ENOMEM;
1206         }
1207         /* Copy the permanent MAC address */
1208         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1209                         &eth_dev->data->mac_addrs[0]);
1210
1211         /* Allocate memory for storing hash filter MAC addresses */
1212         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1213                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1214         if (eth_dev->data->hash_mac_addrs == NULL) {
1215                 PMD_INIT_LOG(ERR,
1216                              "Failed to allocate %d bytes needed to store MAC addresses",
1217                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1218                 return -ENOMEM;
1219         }
1220
1221         /* initialize the vfta */
1222         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1223
1224         /* initialize the hw strip bitmap*/
1225         memset(hwstrip, 0, sizeof(*hwstrip));
1226
1227         /* initialize PF if max_vfs not zero */
1228         ixgbe_pf_host_init(eth_dev);
1229
1230         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1231         /* let hardware know driver is loaded */
1232         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1233         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1234         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1235         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1236         IXGBE_WRITE_FLUSH(hw);
1237
1238         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1239                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1240                              (int) hw->mac.type, (int) hw->phy.type,
1241                              (int) hw->phy.sfp_type);
1242         else
1243                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1244                              (int) hw->mac.type, (int) hw->phy.type);
1245
1246         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1247                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1248                      pci_dev->id.device_id);
1249
1250         rte_intr_callback_register(intr_handle,
1251                                    ixgbe_dev_interrupt_handler, eth_dev);
1252
1253         /* enable uio/vfio intr/eventfd mapping */
1254         rte_intr_enable(intr_handle);
1255
1256         /* enable support intr */
1257         ixgbe_enable_intr(eth_dev);
1258
1259         /* initialize filter info */
1260         memset(filter_info, 0,
1261                sizeof(struct ixgbe_filter_info));
1262
1263         /* initialize 5tuple filter list */
1264         TAILQ_INIT(&filter_info->fivetuple_list);
1265
1266         /* initialize flow director filter list & hash */
1267         ixgbe_fdir_filter_init(eth_dev);
1268
1269         /* initialize l2 tunnel filter list & hash */
1270         ixgbe_l2_tn_filter_init(eth_dev);
1271
1272         /* initialize flow filter lists */
1273         ixgbe_filterlist_init();
1274
1275         /* initialize bandwidth configuration info */
1276         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1277
1278         /* initialize Traffic Manager configuration */
1279         ixgbe_tm_conf_init(eth_dev);
1280
1281         return 0;
1282 }
1283
1284 static int
1285 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1286 {
1287         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1288         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1289         struct ixgbe_hw *hw;
1290         int retries = 0;
1291         int ret;
1292
1293         PMD_INIT_FUNC_TRACE();
1294
1295         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1296                 return -EPERM;
1297
1298         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1299
1300         if (hw->adapter_stopped == 0)
1301                 ixgbe_dev_close(eth_dev);
1302
1303         eth_dev->dev_ops = NULL;
1304         eth_dev->rx_pkt_burst = NULL;
1305         eth_dev->tx_pkt_burst = NULL;
1306
1307         /* Unlock any pending hardware semaphore */
1308         ixgbe_swfw_lock_reset(hw);
1309
1310         /* disable uio intr before callback unregister */
1311         rte_intr_disable(intr_handle);
1312
1313         do {
1314                 ret = rte_intr_callback_unregister(intr_handle,
1315                                 ixgbe_dev_interrupt_handler, eth_dev);
1316                 if (ret >= 0) {
1317                         break;
1318                 } else if (ret != -EAGAIN) {
1319                         PMD_INIT_LOG(ERR,
1320                                 "intr callback unregister failed: %d",
1321                                 ret);
1322                         return ret;
1323                 }
1324                 rte_delay_ms(100);
1325         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1326
1327         /* uninitialize PF if max_vfs not zero */
1328         ixgbe_pf_host_uninit(eth_dev);
1329
1330         rte_free(eth_dev->data->mac_addrs);
1331         eth_dev->data->mac_addrs = NULL;
1332
1333         rte_free(eth_dev->data->hash_mac_addrs);
1334         eth_dev->data->hash_mac_addrs = NULL;
1335
1336         /* remove all the fdir filters & hash */
1337         ixgbe_fdir_filter_uninit(eth_dev);
1338
1339         /* remove all the L2 tunnel filters & hash */
1340         ixgbe_l2_tn_filter_uninit(eth_dev);
1341
1342         /* Remove all ntuple filters of the device */
1343         ixgbe_ntuple_filter_uninit(eth_dev);
1344
1345         /* clear all the filters list */
1346         ixgbe_filterlist_flush();
1347
1348         /* Remove all Traffic Manager configuration */
1349         ixgbe_tm_conf_uninit(eth_dev);
1350
1351 #ifdef RTE_LIBRTE_SECURITY
1352         rte_free(eth_dev->security_ctx);
1353 #endif
1354
1355         return 0;
1356 }
1357
1358 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1359 {
1360         struct ixgbe_filter_info *filter_info =
1361                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1362         struct ixgbe_5tuple_filter *p_5tuple;
1363
1364         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1365                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1366                              p_5tuple,
1367                              entries);
1368                 rte_free(p_5tuple);
1369         }
1370         memset(filter_info->fivetuple_mask, 0,
1371                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1372
1373         return 0;
1374 }
1375
1376 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1377 {
1378         struct ixgbe_hw_fdir_info *fdir_info =
1379                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1380         struct ixgbe_fdir_filter *fdir_filter;
1381
1382                 if (fdir_info->hash_map)
1383                 rte_free(fdir_info->hash_map);
1384         if (fdir_info->hash_handle)
1385                 rte_hash_free(fdir_info->hash_handle);
1386
1387         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1388                 TAILQ_REMOVE(&fdir_info->fdir_list,
1389                              fdir_filter,
1390                              entries);
1391                 rte_free(fdir_filter);
1392         }
1393
1394         return 0;
1395 }
1396
1397 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1398 {
1399         struct ixgbe_l2_tn_info *l2_tn_info =
1400                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1401         struct ixgbe_l2_tn_filter *l2_tn_filter;
1402
1403         if (l2_tn_info->hash_map)
1404                 rte_free(l2_tn_info->hash_map);
1405         if (l2_tn_info->hash_handle)
1406                 rte_hash_free(l2_tn_info->hash_handle);
1407
1408         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1409                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1410                              l2_tn_filter,
1411                              entries);
1412                 rte_free(l2_tn_filter);
1413         }
1414
1415         return 0;
1416 }
1417
1418 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1419 {
1420         struct ixgbe_hw_fdir_info *fdir_info =
1421                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1422         char fdir_hash_name[RTE_HASH_NAMESIZE];
1423         struct rte_hash_parameters fdir_hash_params = {
1424                 .name = fdir_hash_name,
1425                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1426                 .key_len = sizeof(union ixgbe_atr_input),
1427                 .hash_func = rte_hash_crc,
1428                 .hash_func_init_val = 0,
1429                 .socket_id = rte_socket_id(),
1430         };
1431
1432         TAILQ_INIT(&fdir_info->fdir_list);
1433         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1434                  "fdir_%s", eth_dev->device->name);
1435         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1436         if (!fdir_info->hash_handle) {
1437                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1438                 return -EINVAL;
1439         }
1440         fdir_info->hash_map = rte_zmalloc("ixgbe",
1441                                           sizeof(struct ixgbe_fdir_filter *) *
1442                                           IXGBE_MAX_FDIR_FILTER_NUM,
1443                                           0);
1444         if (!fdir_info->hash_map) {
1445                 PMD_INIT_LOG(ERR,
1446                              "Failed to allocate memory for fdir hash map!");
1447                 return -ENOMEM;
1448         }
1449         fdir_info->mask_added = FALSE;
1450
1451         return 0;
1452 }
1453
1454 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1455 {
1456         struct ixgbe_l2_tn_info *l2_tn_info =
1457                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1458         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1459         struct rte_hash_parameters l2_tn_hash_params = {
1460                 .name = l2_tn_hash_name,
1461                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1462                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1463                 .hash_func = rte_hash_crc,
1464                 .hash_func_init_val = 0,
1465                 .socket_id = rte_socket_id(),
1466         };
1467
1468         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1469         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1470                  "l2_tn_%s", eth_dev->device->name);
1471         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1472         if (!l2_tn_info->hash_handle) {
1473                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1474                 return -EINVAL;
1475         }
1476         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1477                                    sizeof(struct ixgbe_l2_tn_filter *) *
1478                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1479                                    0);
1480         if (!l2_tn_info->hash_map) {
1481                 PMD_INIT_LOG(ERR,
1482                         "Failed to allocate memory for L2 TN hash map!");
1483                 return -ENOMEM;
1484         }
1485         l2_tn_info->e_tag_en = FALSE;
1486         l2_tn_info->e_tag_fwd_en = FALSE;
1487         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1488
1489         return 0;
1490 }
1491 /*
1492  * Negotiate mailbox API version with the PF.
1493  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1494  * Then we try to negotiate starting with the most recent one.
1495  * If all negotiation attempts fail, then we will proceed with
1496  * the default one (ixgbe_mbox_api_10).
1497  */
1498 static void
1499 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1500 {
1501         int32_t i;
1502
1503         /* start with highest supported, proceed down */
1504         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1505                 ixgbe_mbox_api_12,
1506                 ixgbe_mbox_api_11,
1507                 ixgbe_mbox_api_10,
1508         };
1509
1510         for (i = 0;
1511                         i != RTE_DIM(sup_ver) &&
1512                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1513                         i++)
1514                 ;
1515 }
1516
1517 static void
1518 generate_random_mac_addr(struct ether_addr *mac_addr)
1519 {
1520         uint64_t random;
1521
1522         /* Set Organizationally Unique Identifier (OUI) prefix. */
1523         mac_addr->addr_bytes[0] = 0x00;
1524         mac_addr->addr_bytes[1] = 0x09;
1525         mac_addr->addr_bytes[2] = 0xC0;
1526         /* Force indication of locally assigned MAC address. */
1527         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1528         /* Generate the last 3 bytes of the MAC address with a random number. */
1529         random = rte_rand();
1530         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1531 }
1532
1533 /*
1534  * Virtual Function device init
1535  */
1536 static int
1537 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1538 {
1539         int diag;
1540         uint32_t tc, tcs;
1541         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1543         struct ixgbe_hw *hw =
1544                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1545         struct ixgbe_vfta *shadow_vfta =
1546                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1547         struct ixgbe_hwstrip *hwstrip =
1548                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1549         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1550
1551         PMD_INIT_FUNC_TRACE();
1552
1553         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1554         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1555         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1556
1557         /* for secondary processes, we don't initialise any further as primary
1558          * has already done this work. Only check we don't need a different
1559          * RX function
1560          */
1561         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1562                 struct ixgbe_tx_queue *txq;
1563                 /* TX queue function in primary, set by last queue initialized
1564                  * Tx queue may not initialized by primary process
1565                  */
1566                 if (eth_dev->data->tx_queues) {
1567                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1568                         ixgbe_set_tx_function(eth_dev, txq);
1569                 } else {
1570                         /* Use default TX function if we get here */
1571                         PMD_INIT_LOG(NOTICE,
1572                                      "No TX queues configured yet. Using default TX function.");
1573                 }
1574
1575                 ixgbe_set_rx_function(eth_dev);
1576
1577                 return 0;
1578         }
1579
1580         rte_eth_copy_pci_info(eth_dev, pci_dev);
1581
1582         hw->device_id = pci_dev->id.device_id;
1583         hw->vendor_id = pci_dev->id.vendor_id;
1584         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1585
1586         /* initialize the vfta */
1587         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1588
1589         /* initialize the hw strip bitmap*/
1590         memset(hwstrip, 0, sizeof(*hwstrip));
1591
1592         /* Initialize the shared code (base driver) */
1593         diag = ixgbe_init_shared_code(hw);
1594         if (diag != IXGBE_SUCCESS) {
1595                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1596                 return -EIO;
1597         }
1598
1599         /* init_mailbox_params */
1600         hw->mbx.ops.init_params(hw);
1601
1602         /* Reset the hw statistics */
1603         ixgbevf_dev_stats_reset(eth_dev);
1604
1605         /* Disable the interrupts for VF */
1606         ixgbevf_intr_disable(eth_dev);
1607
1608         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1609         diag = hw->mac.ops.reset_hw(hw);
1610
1611         /*
1612          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1613          * the underlying PF driver has not assigned a MAC address to the VF.
1614          * In this case, assign a random MAC address.
1615          */
1616         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1617                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1618                 return diag;
1619         }
1620
1621         /* negotiate mailbox API version to use with the PF. */
1622         ixgbevf_negotiate_api(hw);
1623
1624         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1625         ixgbevf_get_queues(hw, &tcs, &tc);
1626
1627         /* Allocate memory for storing MAC addresses */
1628         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1629                                                hw->mac.num_rar_entries, 0);
1630         if (eth_dev->data->mac_addrs == NULL) {
1631                 PMD_INIT_LOG(ERR,
1632                              "Failed to allocate %u bytes needed to store "
1633                              "MAC addresses",
1634                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1635                 return -ENOMEM;
1636         }
1637
1638         /* Generate a random MAC address, if none was assigned by PF. */
1639         if (is_zero_ether_addr(perm_addr)) {
1640                 generate_random_mac_addr(perm_addr);
1641                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1642                 if (diag) {
1643                         rte_free(eth_dev->data->mac_addrs);
1644                         eth_dev->data->mac_addrs = NULL;
1645                         return diag;
1646                 }
1647                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1648                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1649                              "%02x:%02x:%02x:%02x:%02x:%02x",
1650                              perm_addr->addr_bytes[0],
1651                              perm_addr->addr_bytes[1],
1652                              perm_addr->addr_bytes[2],
1653                              perm_addr->addr_bytes[3],
1654                              perm_addr->addr_bytes[4],
1655                              perm_addr->addr_bytes[5]);
1656         }
1657
1658         /* Copy the permanent MAC address */
1659         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1660
1661         /* reset the hardware with the new settings */
1662         diag = hw->mac.ops.start_hw(hw);
1663         switch (diag) {
1664         case  0:
1665                 break;
1666
1667         default:
1668                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1669                 return -EIO;
1670         }
1671
1672         rte_intr_callback_register(intr_handle,
1673                                    ixgbevf_dev_interrupt_handler, eth_dev);
1674         rte_intr_enable(intr_handle);
1675         ixgbevf_intr_enable(eth_dev);
1676
1677         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1678                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1679                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1680
1681         return 0;
1682 }
1683
1684 /* Virtual Function device uninit */
1685
1686 static int
1687 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1688 {
1689         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1690         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1691         struct ixgbe_hw *hw;
1692
1693         PMD_INIT_FUNC_TRACE();
1694
1695         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1696                 return -EPERM;
1697
1698         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1699
1700         if (hw->adapter_stopped == 0)
1701                 ixgbevf_dev_close(eth_dev);
1702
1703         eth_dev->dev_ops = NULL;
1704         eth_dev->rx_pkt_burst = NULL;
1705         eth_dev->tx_pkt_burst = NULL;
1706
1707         /* Disable the interrupts for VF */
1708         ixgbevf_intr_disable(eth_dev);
1709
1710         rte_free(eth_dev->data->mac_addrs);
1711         eth_dev->data->mac_addrs = NULL;
1712
1713         rte_intr_disable(intr_handle);
1714         rte_intr_callback_unregister(intr_handle,
1715                                      ixgbevf_dev_interrupt_handler, eth_dev);
1716
1717         return 0;
1718 }
1719
1720 static int
1721 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1722                 struct rte_pci_device *pci_dev)
1723 {
1724         char name[RTE_ETH_NAME_MAX_LEN];
1725         struct rte_eth_dev *pf_ethdev;
1726         struct rte_eth_devargs eth_da;
1727         int i, retval;
1728
1729         if (pci_dev->device.devargs) {
1730                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1731                                 &eth_da);
1732                 if (retval)
1733                         return retval;
1734         } else
1735                 memset(&eth_da, 0, sizeof(eth_da));
1736
1737         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1738                 sizeof(struct ixgbe_adapter),
1739                 eth_dev_pci_specific_init, pci_dev,
1740                 eth_ixgbe_dev_init, NULL);
1741
1742         if (retval || eth_da.nb_representor_ports < 1)
1743                 return retval;
1744
1745         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1746         if (pf_ethdev == NULL)
1747                 return -ENODEV;
1748
1749         /* probe VF representor ports */
1750         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1751                 struct ixgbe_vf_info *vfinfo;
1752                 struct ixgbe_vf_representor representor;
1753
1754                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1755                         pf_ethdev->data->dev_private);
1756                 if (vfinfo == NULL) {
1757                         PMD_DRV_LOG(ERR,
1758                                 "no virtual functions supported by PF");
1759                         break;
1760                 }
1761
1762                 representor.vf_id = eth_da.representor_ports[i];
1763                 representor.switch_domain_id = vfinfo->switch_domain_id;
1764                 representor.pf_ethdev = pf_ethdev;
1765
1766                 /* representor port net_bdf_port */
1767                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1768                         pci_dev->device.name,
1769                         eth_da.representor_ports[i]);
1770
1771                 retval = rte_eth_dev_create(&pci_dev->device, name,
1772                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1773                         ixgbe_vf_representor_init, &representor);
1774
1775                 if (retval)
1776                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1777                                 "representor %s.", name);
1778         }
1779
1780         return 0;
1781 }
1782
1783 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1784 {
1785         struct rte_eth_dev *ethdev;
1786
1787         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1788         if (!ethdev)
1789                 return -ENODEV;
1790
1791         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1792                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1793         else
1794                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1795 }
1796
1797 static struct rte_pci_driver rte_ixgbe_pmd = {
1798         .id_table = pci_id_ixgbe_map,
1799         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1800                      RTE_PCI_DRV_IOVA_AS_VA,
1801         .probe = eth_ixgbe_pci_probe,
1802         .remove = eth_ixgbe_pci_remove,
1803 };
1804
1805 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1806         struct rte_pci_device *pci_dev)
1807 {
1808         return rte_eth_dev_pci_generic_probe(pci_dev,
1809                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1810 }
1811
1812 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1813 {
1814         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1815 }
1816
1817 /*
1818  * virtual function driver struct
1819  */
1820 static struct rte_pci_driver rte_ixgbevf_pmd = {
1821         .id_table = pci_id_ixgbevf_map,
1822         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1823         .probe = eth_ixgbevf_pci_probe,
1824         .remove = eth_ixgbevf_pci_remove,
1825 };
1826
1827 static int
1828 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1829 {
1830         struct ixgbe_hw *hw =
1831                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832         struct ixgbe_vfta *shadow_vfta =
1833                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1834         uint32_t vfta;
1835         uint32_t vid_idx;
1836         uint32_t vid_bit;
1837
1838         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1839         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1840         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1841         if (on)
1842                 vfta |= vid_bit;
1843         else
1844                 vfta &= ~vid_bit;
1845         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1846
1847         /* update local VFTA copy */
1848         shadow_vfta->vfta[vid_idx] = vfta;
1849
1850         return 0;
1851 }
1852
1853 static void
1854 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1855 {
1856         if (on)
1857                 ixgbe_vlan_hw_strip_enable(dev, queue);
1858         else
1859                 ixgbe_vlan_hw_strip_disable(dev, queue);
1860 }
1861
1862 static int
1863 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1864                     enum rte_vlan_type vlan_type,
1865                     uint16_t tpid)
1866 {
1867         struct ixgbe_hw *hw =
1868                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         int ret = 0;
1870         uint32_t reg;
1871         uint32_t qinq;
1872
1873         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1874         qinq &= IXGBE_DMATXCTL_GDV;
1875
1876         switch (vlan_type) {
1877         case ETH_VLAN_TYPE_INNER:
1878                 if (qinq) {
1879                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1880                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1881                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1882                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1883                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1884                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1885                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1886                 } else {
1887                         ret = -ENOTSUP;
1888                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1889                                     " by single VLAN");
1890                 }
1891                 break;
1892         case ETH_VLAN_TYPE_OUTER:
1893                 if (qinq) {
1894                         /* Only the high 16-bits is valid */
1895                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1896                                         IXGBE_EXVET_VET_EXT_SHIFT);
1897                 } else {
1898                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1899                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1900                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1901                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1902                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1903                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1904                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1905                 }
1906
1907                 break;
1908         default:
1909                 ret = -EINVAL;
1910                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1911                 break;
1912         }
1913
1914         return ret;
1915 }
1916
1917 void
1918 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint32_t vlnctrl;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         /* Filter Table Disable */
1927         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1928         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1929
1930         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1931 }
1932
1933 void
1934 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_hw *hw =
1937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         struct ixgbe_vfta *shadow_vfta =
1939                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1940         uint32_t vlnctrl;
1941         uint16_t i;
1942
1943         PMD_INIT_FUNC_TRACE();
1944
1945         /* Filter Table Enable */
1946         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1947         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1948         vlnctrl |= IXGBE_VLNCTRL_VFE;
1949
1950         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1951
1952         /* write whatever is in local vfta copy */
1953         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1954                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1955 }
1956
1957 static void
1958 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1959 {
1960         struct ixgbe_hwstrip *hwstrip =
1961                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1962         struct ixgbe_rx_queue *rxq;
1963
1964         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1965                 return;
1966
1967         if (on)
1968                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1969         else
1970                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1971
1972         if (queue >= dev->data->nb_rx_queues)
1973                 return;
1974
1975         rxq = dev->data->rx_queues[queue];
1976
1977         if (on)
1978                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1979         else
1980                 rxq->vlan_flags = PKT_RX_VLAN;
1981 }
1982
1983 static void
1984 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1985 {
1986         struct ixgbe_hw *hw =
1987                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1988         uint32_t ctrl;
1989
1990         PMD_INIT_FUNC_TRACE();
1991
1992         if (hw->mac.type == ixgbe_mac_82598EB) {
1993                 /* No queue level support */
1994                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1995                 return;
1996         }
1997
1998         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1999         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2000         ctrl &= ~IXGBE_RXDCTL_VME;
2001         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2002
2003         /* record those setting for HW strip per queue */
2004         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2005 }
2006
2007 static void
2008 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2009 {
2010         struct ixgbe_hw *hw =
2011                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012         uint32_t ctrl;
2013
2014         PMD_INIT_FUNC_TRACE();
2015
2016         if (hw->mac.type == ixgbe_mac_82598EB) {
2017                 /* No queue level supported */
2018                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2019                 return;
2020         }
2021
2022         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2023         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2024         ctrl |= IXGBE_RXDCTL_VME;
2025         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2026
2027         /* record those setting for HW strip per queue */
2028         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2029 }
2030
2031 static void
2032 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2033 {
2034         struct ixgbe_hw *hw =
2035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         uint32_t ctrl;
2037
2038         PMD_INIT_FUNC_TRACE();
2039
2040         /* DMATXCTRL: Geric Double VLAN Disable */
2041         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2042         ctrl &= ~IXGBE_DMATXCTL_GDV;
2043         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2044
2045         /* CTRL_EXT: Global Double VLAN Disable */
2046         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2047         ctrl &= ~IXGBE_EXTENDED_VLAN;
2048         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2049
2050 }
2051
2052 static void
2053 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2054 {
2055         struct ixgbe_hw *hw =
2056                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057         uint32_t ctrl;
2058
2059         PMD_INIT_FUNC_TRACE();
2060
2061         /* DMATXCTRL: Geric Double VLAN Enable */
2062         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2063         ctrl |= IXGBE_DMATXCTL_GDV;
2064         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2065
2066         /* CTRL_EXT: Global Double VLAN Enable */
2067         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2068         ctrl |= IXGBE_EXTENDED_VLAN;
2069         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2070
2071         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2072         if (hw->mac.type == ixgbe_mac_X550 ||
2073             hw->mac.type == ixgbe_mac_X550EM_x ||
2074             hw->mac.type == ixgbe_mac_X550EM_a) {
2075                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2076                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2077                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2078         }
2079
2080         /*
2081          * VET EXT field in the EXVET register = 0x8100 by default
2082          * So no need to change. Same to VT field of DMATXCTL register
2083          */
2084 }
2085
2086 void
2087 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2088 {
2089         struct ixgbe_hw *hw =
2090                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2092         uint32_t ctrl;
2093         uint16_t i;
2094         struct ixgbe_rx_queue *rxq;
2095         bool on;
2096
2097         PMD_INIT_FUNC_TRACE();
2098
2099         if (hw->mac.type == ixgbe_mac_82598EB) {
2100                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2101                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2102                         ctrl |= IXGBE_VLNCTRL_VME;
2103                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2104                 } else {
2105                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2106                         ctrl &= ~IXGBE_VLNCTRL_VME;
2107                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2108                 }
2109         } else {
2110                 /*
2111                  * Other 10G NIC, the VLAN strip can be setup
2112                  * per queue in RXDCTL
2113                  */
2114                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2115                         rxq = dev->data->rx_queues[i];
2116                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2117                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2118                                 ctrl |= IXGBE_RXDCTL_VME;
2119                                 on = TRUE;
2120                         } else {
2121                                 ctrl &= ~IXGBE_RXDCTL_VME;
2122                                 on = FALSE;
2123                         }
2124                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2125
2126                         /* record those setting for HW strip per queue */
2127                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2128                 }
2129         }
2130 }
2131
2132 static int
2133 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2134 {
2135         struct rte_eth_rxmode *rxmode;
2136         rxmode = &dev->data->dev_conf.rxmode;
2137
2138         if (mask & ETH_VLAN_STRIP_MASK) {
2139                 ixgbe_vlan_hw_strip_config(dev);
2140         }
2141
2142         if (mask & ETH_VLAN_FILTER_MASK) {
2143                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2144                         ixgbe_vlan_hw_filter_enable(dev);
2145                 else
2146                         ixgbe_vlan_hw_filter_disable(dev);
2147         }
2148
2149         if (mask & ETH_VLAN_EXTEND_MASK) {
2150                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2151                         ixgbe_vlan_hw_extend_enable(dev);
2152                 else
2153                         ixgbe_vlan_hw_extend_disable(dev);
2154         }
2155
2156         return 0;
2157 }
2158
2159 static void
2160 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2161 {
2162         struct ixgbe_hw *hw =
2163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2165         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2166
2167         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2168         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2169 }
2170
2171 static int
2172 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2173 {
2174         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2175
2176         switch (nb_rx_q) {
2177         case 1:
2178         case 2:
2179                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2180                 break;
2181         case 4:
2182                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2183                 break;
2184         default:
2185                 return -EINVAL;
2186         }
2187
2188         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2189                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2190         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2191                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2192         return 0;
2193 }
2194
2195 static int
2196 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2197 {
2198         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2201         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2202
2203         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2204                 /* check multi-queue mode */
2205                 switch (dev_conf->rxmode.mq_mode) {
2206                 case ETH_MQ_RX_VMDQ_DCB:
2207                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2208                         break;
2209                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2210                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2211                         PMD_INIT_LOG(ERR, "SRIOV active,"
2212                                         " unsupported mq_mode rx %d.",
2213                                         dev_conf->rxmode.mq_mode);
2214                         return -EINVAL;
2215                 case ETH_MQ_RX_RSS:
2216                 case ETH_MQ_RX_VMDQ_RSS:
2217                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2218                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2219                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2220                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2221                                                 " invalid queue number"
2222                                                 " for VMDQ RSS, allowed"
2223                                                 " value are 1, 2 or 4.");
2224                                         return -EINVAL;
2225                                 }
2226                         break;
2227                 case ETH_MQ_RX_VMDQ_ONLY:
2228                 case ETH_MQ_RX_NONE:
2229                         /* if nothing mq mode configure, use default scheme */
2230                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2231                         break;
2232                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2233                         /* SRIOV only works in VMDq enable mode */
2234                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2235                                         " wrong mq_mode rx %d.",
2236                                         dev_conf->rxmode.mq_mode);
2237                         return -EINVAL;
2238                 }
2239
2240                 switch (dev_conf->txmode.mq_mode) {
2241                 case ETH_MQ_TX_VMDQ_DCB:
2242                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2243                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2244                         break;
2245                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2246                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2247                         break;
2248                 }
2249
2250                 /* check valid queue number */
2251                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2252                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2253                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2254                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2255                                         " must be less than or equal to %d.",
2256                                         nb_rx_q, nb_tx_q,
2257                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2258                         return -EINVAL;
2259                 }
2260         } else {
2261                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2262                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2263                                           " not supported.");
2264                         return -EINVAL;
2265                 }
2266                 /* check configuration for vmdb+dcb mode */
2267                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2268                         const struct rte_eth_vmdq_dcb_conf *conf;
2269
2270                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2271                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2272                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2273                                 return -EINVAL;
2274                         }
2275                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2276                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2277                                conf->nb_queue_pools == ETH_32_POOLS)) {
2278                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2279                                                 " nb_queue_pools must be %d or %d.",
2280                                                 ETH_16_POOLS, ETH_32_POOLS);
2281                                 return -EINVAL;
2282                         }
2283                 }
2284                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2285                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2286
2287                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2288                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2289                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2290                                 return -EINVAL;
2291                         }
2292                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2293                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2294                                conf->nb_queue_pools == ETH_32_POOLS)) {
2295                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2296                                                 " nb_queue_pools != %d and"
2297                                                 " nb_queue_pools != %d.",
2298                                                 ETH_16_POOLS, ETH_32_POOLS);
2299                                 return -EINVAL;
2300                         }
2301                 }
2302
2303                 /* For DCB mode check our configuration before we go further */
2304                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2305                         const struct rte_eth_dcb_rx_conf *conf;
2306
2307                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2308                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2309                                                  IXGBE_DCB_NB_QUEUES);
2310                                 return -EINVAL;
2311                         }
2312                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2313                         if (!(conf->nb_tcs == ETH_4_TCS ||
2314                                conf->nb_tcs == ETH_8_TCS)) {
2315                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2316                                                 " and nb_tcs != %d.",
2317                                                 ETH_4_TCS, ETH_8_TCS);
2318                                 return -EINVAL;
2319                         }
2320                 }
2321
2322                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2323                         const struct rte_eth_dcb_tx_conf *conf;
2324
2325                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2326                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2327                                                  IXGBE_DCB_NB_QUEUES);
2328                                 return -EINVAL;
2329                         }
2330                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2331                         if (!(conf->nb_tcs == ETH_4_TCS ||
2332                                conf->nb_tcs == ETH_8_TCS)) {
2333                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2334                                                 " and nb_tcs != %d.",
2335                                                 ETH_4_TCS, ETH_8_TCS);
2336                                 return -EINVAL;
2337                         }
2338                 }
2339
2340                 /*
2341                  * When DCB/VT is off, maximum number of queues changes,
2342                  * except for 82598EB, which remains constant.
2343                  */
2344                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2345                                 hw->mac.type != ixgbe_mac_82598EB) {
2346                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2347                                 PMD_INIT_LOG(ERR,
2348                                              "Neither VT nor DCB are enabled, "
2349                                              "nb_tx_q > %d.",
2350                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2351                                 return -EINVAL;
2352                         }
2353                 }
2354         }
2355         return 0;
2356 }
2357
2358 static int
2359 ixgbe_dev_configure(struct rte_eth_dev *dev)
2360 {
2361         struct ixgbe_interrupt *intr =
2362                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2363         struct ixgbe_adapter *adapter =
2364                 (struct ixgbe_adapter *)dev->data->dev_private;
2365         struct rte_eth_dev_info dev_info;
2366         uint64_t rx_offloads;
2367         uint64_t tx_offloads;
2368         int ret;
2369
2370         PMD_INIT_FUNC_TRACE();
2371         /* multipe queue mode checking */
2372         ret  = ixgbe_check_mq_mode(dev);
2373         if (ret != 0) {
2374                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2375                             ret);
2376                 return ret;
2377         }
2378
2379         ixgbe_dev_info_get(dev, &dev_info);
2380         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2381         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2382                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2383                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2384                             rx_offloads, dev_info.rx_offload_capa);
2385                 return -ENOTSUP;
2386         }
2387         tx_offloads = dev->data->dev_conf.txmode.offloads;
2388         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2389                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2390                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2391                             tx_offloads, dev_info.tx_offload_capa);
2392                 return -ENOTSUP;
2393         }
2394
2395         /* set flag to update link status after init */
2396         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2397
2398         /*
2399          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2400          * allocation or vector Rx preconditions we will reset it.
2401          */
2402         adapter->rx_bulk_alloc_allowed = true;
2403         adapter->rx_vec_allowed = true;
2404
2405         return 0;
2406 }
2407
2408 static void
2409 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2410 {
2411         struct ixgbe_hw *hw =
2412                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413         struct ixgbe_interrupt *intr =
2414                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2415         uint32_t gpie;
2416
2417         /* only set up it on X550EM_X */
2418         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2419                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2420                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2421                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2422                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2423                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2424         }
2425 }
2426
2427 int
2428 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2429                         uint16_t tx_rate, uint64_t q_msk)
2430 {
2431         struct ixgbe_hw *hw;
2432         struct ixgbe_vf_info *vfinfo;
2433         struct rte_eth_link link;
2434         uint8_t  nb_q_per_pool;
2435         uint32_t queue_stride;
2436         uint32_t queue_idx, idx = 0, vf_idx;
2437         uint32_t queue_end;
2438         uint16_t total_rate = 0;
2439         struct rte_pci_device *pci_dev;
2440
2441         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2442         rte_eth_link_get_nowait(dev->data->port_id, &link);
2443
2444         if (vf >= pci_dev->max_vfs)
2445                 return -EINVAL;
2446
2447         if (tx_rate > link.link_speed)
2448                 return -EINVAL;
2449
2450         if (q_msk == 0)
2451                 return 0;
2452
2453         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2454         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2455         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2456         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2457         queue_idx = vf * queue_stride;
2458         queue_end = queue_idx + nb_q_per_pool - 1;
2459         if (queue_end >= hw->mac.max_tx_queues)
2460                 return -EINVAL;
2461
2462         if (vfinfo) {
2463                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2464                         if (vf_idx == vf)
2465                                 continue;
2466                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2467                                 idx++)
2468                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2469                 }
2470         } else {
2471                 return -EINVAL;
2472         }
2473
2474         /* Store tx_rate for this vf. */
2475         for (idx = 0; idx < nb_q_per_pool; idx++) {
2476                 if (((uint64_t)0x1 << idx) & q_msk) {
2477                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2478                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2479                         total_rate += tx_rate;
2480                 }
2481         }
2482
2483         if (total_rate > dev->data->dev_link.link_speed) {
2484                 /* Reset stored TX rate of the VF if it causes exceed
2485                  * link speed.
2486                  */
2487                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2488                 return -EINVAL;
2489         }
2490
2491         /* Set RTTBCNRC of each queue/pool for vf X  */
2492         for (; queue_idx <= queue_end; queue_idx++) {
2493                 if (0x1 & q_msk)
2494                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2495                 q_msk = q_msk >> 1;
2496         }
2497
2498         return 0;
2499 }
2500
2501 /*
2502  * Configure device link speed and setup link.
2503  * It returns 0 on success.
2504  */
2505 static int
2506 ixgbe_dev_start(struct rte_eth_dev *dev)
2507 {
2508         struct ixgbe_hw *hw =
2509                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2510         struct ixgbe_vf_info *vfinfo =
2511                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2512         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2513         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2514         uint32_t intr_vector = 0;
2515         int err, link_up = 0, negotiate = 0;
2516         uint32_t speed = 0;
2517         uint32_t allowed_speeds = 0;
2518         int mask = 0;
2519         int status;
2520         uint16_t vf, idx;
2521         uint32_t *link_speeds;
2522         struct ixgbe_tm_conf *tm_conf =
2523                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2524
2525         PMD_INIT_FUNC_TRACE();
2526
2527         /* IXGBE devices don't support:
2528         *    - half duplex (checked afterwards for valid speeds)
2529         *    - fixed speed: TODO implement
2530         */
2531         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2532                 PMD_INIT_LOG(ERR,
2533                 "Invalid link_speeds for port %u, fix speed not supported",
2534                                 dev->data->port_id);
2535                 return -EINVAL;
2536         }
2537
2538         /* disable uio/vfio intr/eventfd mapping */
2539         rte_intr_disable(intr_handle);
2540
2541         /* stop adapter */
2542         hw->adapter_stopped = 0;
2543         ixgbe_stop_adapter(hw);
2544
2545         /* reinitialize adapter
2546          * this calls reset and start
2547          */
2548         status = ixgbe_pf_reset_hw(hw);
2549         if (status != 0)
2550                 return -1;
2551         hw->mac.ops.start_hw(hw);
2552         hw->mac.get_link_status = true;
2553
2554         /* configure PF module if SRIOV enabled */
2555         ixgbe_pf_host_configure(dev);
2556
2557         ixgbe_dev_phy_intr_setup(dev);
2558
2559         /* check and configure queue intr-vector mapping */
2560         if ((rte_intr_cap_multiple(intr_handle) ||
2561              !RTE_ETH_DEV_SRIOV(dev).active) &&
2562             dev->data->dev_conf.intr_conf.rxq != 0) {
2563                 intr_vector = dev->data->nb_rx_queues;
2564                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2565                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2566                                         IXGBE_MAX_INTR_QUEUE_NUM);
2567                         return -ENOTSUP;
2568                 }
2569                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2570                         return -1;
2571         }
2572
2573         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2574                 intr_handle->intr_vec =
2575                         rte_zmalloc("intr_vec",
2576                                     dev->data->nb_rx_queues * sizeof(int), 0);
2577                 if (intr_handle->intr_vec == NULL) {
2578                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2579                                      " intr_vec", dev->data->nb_rx_queues);
2580                         return -ENOMEM;
2581                 }
2582         }
2583
2584         /* confiugre msix for sleep until rx interrupt */
2585         ixgbe_configure_msix(dev);
2586
2587         /* initialize transmission unit */
2588         ixgbe_dev_tx_init(dev);
2589
2590         /* This can fail when allocating mbufs for descriptor rings */
2591         err = ixgbe_dev_rx_init(dev);
2592         if (err) {
2593                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2594                 goto error;
2595         }
2596
2597         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2598                 ETH_VLAN_EXTEND_MASK;
2599         err = ixgbe_vlan_offload_set(dev, mask);
2600         if (err) {
2601                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2602                 goto error;
2603         }
2604
2605         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2606                 /* Enable vlan filtering for VMDq */
2607                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2608         }
2609
2610         /* Configure DCB hw */
2611         ixgbe_configure_dcb(dev);
2612
2613         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2614                 err = ixgbe_fdir_configure(dev);
2615                 if (err)
2616                         goto error;
2617         }
2618
2619         /* Restore vf rate limit */
2620         if (vfinfo != NULL) {
2621                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2622                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2623                                 if (vfinfo[vf].tx_rate[idx] != 0)
2624                                         ixgbe_set_vf_rate_limit(
2625                                                 dev, vf,
2626                                                 vfinfo[vf].tx_rate[idx],
2627                                                 1 << idx);
2628         }
2629
2630         ixgbe_restore_statistics_mapping(dev);
2631
2632         err = ixgbe_dev_rxtx_start(dev);
2633         if (err < 0) {
2634                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2635                 goto error;
2636         }
2637
2638         /* Skip link setup if loopback mode is enabled for 82599. */
2639         if (hw->mac.type == ixgbe_mac_82599EB &&
2640                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2641                 goto skip_link_setup;
2642
2643         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2644                 err = hw->mac.ops.setup_sfp(hw);
2645                 if (err)
2646                         goto error;
2647         }
2648
2649         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2650                 /* Turn on the copper */
2651                 ixgbe_set_phy_power(hw, true);
2652         } else {
2653                 /* Turn on the laser */
2654                 ixgbe_enable_tx_laser(hw);
2655         }
2656
2657         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2658         if (err)
2659                 goto error;
2660         dev->data->dev_link.link_status = link_up;
2661
2662         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2663         if (err)
2664                 goto error;
2665
2666         switch (hw->mac.type) {
2667         case ixgbe_mac_X550:
2668         case ixgbe_mac_X550EM_x:
2669         case ixgbe_mac_X550EM_a:
2670                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2671                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2672                         ETH_LINK_SPEED_10G;
2673                 break;
2674         default:
2675                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2676                         ETH_LINK_SPEED_10G;
2677         }
2678
2679         link_speeds = &dev->data->dev_conf.link_speeds;
2680         if (*link_speeds & ~allowed_speeds) {
2681                 PMD_INIT_LOG(ERR, "Invalid link setting");
2682                 goto error;
2683         }
2684
2685         speed = 0x0;
2686         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2687                 switch (hw->mac.type) {
2688                 case ixgbe_mac_82598EB:
2689                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2690                         break;
2691                 case ixgbe_mac_82599EB:
2692                 case ixgbe_mac_X540:
2693                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2694                         break;
2695                 case ixgbe_mac_X550:
2696                 case ixgbe_mac_X550EM_x:
2697                 case ixgbe_mac_X550EM_a:
2698                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2699                         break;
2700                 default:
2701                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2702                 }
2703         } else {
2704                 if (*link_speeds & ETH_LINK_SPEED_10G)
2705                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2706                 if (*link_speeds & ETH_LINK_SPEED_5G)
2707                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2708                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2709                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2710                 if (*link_speeds & ETH_LINK_SPEED_1G)
2711                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2712                 if (*link_speeds & ETH_LINK_SPEED_100M)
2713                         speed |= IXGBE_LINK_SPEED_100_FULL;
2714         }
2715
2716         err = ixgbe_setup_link(hw, speed, link_up);
2717         if (err)
2718                 goto error;
2719
2720         ixgbe_dev_link_update(dev, 0);
2721
2722 skip_link_setup:
2723
2724         if (rte_intr_allow_others(intr_handle)) {
2725                 /* check if lsc interrupt is enabled */
2726                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2727                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2728                 else
2729                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2730                 ixgbe_dev_macsec_interrupt_setup(dev);
2731         } else {
2732                 rte_intr_callback_unregister(intr_handle,
2733                                              ixgbe_dev_interrupt_handler, dev);
2734                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2735                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2736                                      " no intr multiplex");
2737         }
2738
2739         /* check if rxq interrupt is enabled */
2740         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2741             rte_intr_dp_is_en(intr_handle))
2742                 ixgbe_dev_rxq_interrupt_setup(dev);
2743
2744         /* enable uio/vfio intr/eventfd mapping */
2745         rte_intr_enable(intr_handle);
2746
2747         /* resume enabled intr since hw reset */
2748         ixgbe_enable_intr(dev);
2749         ixgbe_l2_tunnel_conf(dev);
2750         ixgbe_filter_restore(dev);
2751
2752         if (tm_conf->root && !tm_conf->committed)
2753                 PMD_DRV_LOG(WARNING,
2754                             "please call hierarchy_commit() "
2755                             "before starting the port");
2756
2757         return 0;
2758
2759 error:
2760         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2761         ixgbe_dev_clear_queues(dev);
2762         return -EIO;
2763 }
2764
2765 /*
2766  * Stop device: disable rx and tx functions to allow for reconfiguring.
2767  */
2768 static void
2769 ixgbe_dev_stop(struct rte_eth_dev *dev)
2770 {
2771         struct rte_eth_link link;
2772         struct ixgbe_hw *hw =
2773                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774         struct ixgbe_vf_info *vfinfo =
2775                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2777         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2778         int vf;
2779         struct ixgbe_tm_conf *tm_conf =
2780                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2781
2782         PMD_INIT_FUNC_TRACE();
2783
2784         /* disable interrupts */
2785         ixgbe_disable_intr(hw);
2786
2787         /* reset the NIC */
2788         ixgbe_pf_reset_hw(hw);
2789         hw->adapter_stopped = 0;
2790
2791         /* stop adapter */
2792         ixgbe_stop_adapter(hw);
2793
2794         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2795                 vfinfo[vf].clear_to_send = false;
2796
2797         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2798                 /* Turn off the copper */
2799                 ixgbe_set_phy_power(hw, false);
2800         } else {
2801                 /* Turn off the laser */
2802                 ixgbe_disable_tx_laser(hw);
2803         }
2804
2805         ixgbe_dev_clear_queues(dev);
2806
2807         /* Clear stored conf */
2808         dev->data->scattered_rx = 0;
2809         dev->data->lro = 0;
2810
2811         /* Clear recorded link status */
2812         memset(&link, 0, sizeof(link));
2813         rte_eth_linkstatus_set(dev, &link);
2814
2815         if (!rte_intr_allow_others(intr_handle))
2816                 /* resume to the default handler */
2817                 rte_intr_callback_register(intr_handle,
2818                                            ixgbe_dev_interrupt_handler,
2819                                            (void *)dev);
2820
2821         /* Clean datapath event and queue/vec mapping */
2822         rte_intr_efd_disable(intr_handle);
2823         if (intr_handle->intr_vec != NULL) {
2824                 rte_free(intr_handle->intr_vec);
2825                 intr_handle->intr_vec = NULL;
2826         }
2827
2828         /* reset hierarchy commit */
2829         tm_conf->committed = false;
2830 }
2831
2832 /*
2833  * Set device link up: enable tx.
2834  */
2835 static int
2836 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2837 {
2838         struct ixgbe_hw *hw =
2839                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840         if (hw->mac.type == ixgbe_mac_82599EB) {
2841 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2842                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2843                         /* Not suported in bypass mode */
2844                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2845                                      "by device id 0x%x", hw->device_id);
2846                         return -ENOTSUP;
2847                 }
2848 #endif
2849         }
2850
2851         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2852                 /* Turn on the copper */
2853                 ixgbe_set_phy_power(hw, true);
2854         } else {
2855                 /* Turn on the laser */
2856                 ixgbe_enable_tx_laser(hw);
2857         }
2858
2859         return 0;
2860 }
2861
2862 /*
2863  * Set device link down: disable tx.
2864  */
2865 static int
2866 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2867 {
2868         struct ixgbe_hw *hw =
2869                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870         if (hw->mac.type == ixgbe_mac_82599EB) {
2871 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2872                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2873                         /* Not suported in bypass mode */
2874                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2875                                      "by device id 0x%x", hw->device_id);
2876                         return -ENOTSUP;
2877                 }
2878 #endif
2879         }
2880
2881         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2882                 /* Turn off the copper */
2883                 ixgbe_set_phy_power(hw, false);
2884         } else {
2885                 /* Turn off the laser */
2886                 ixgbe_disable_tx_laser(hw);
2887         }
2888
2889         return 0;
2890 }
2891
2892 /*
2893  * Reset and stop device.
2894  */
2895 static void
2896 ixgbe_dev_close(struct rte_eth_dev *dev)
2897 {
2898         struct ixgbe_hw *hw =
2899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900
2901         PMD_INIT_FUNC_TRACE();
2902
2903         ixgbe_pf_reset_hw(hw);
2904
2905         ixgbe_dev_stop(dev);
2906         hw->adapter_stopped = 1;
2907
2908         ixgbe_dev_free_queues(dev);
2909
2910         ixgbe_disable_pcie_master(hw);
2911
2912         /* reprogram the RAR[0] in case user changed it. */
2913         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2914 }
2915
2916 /*
2917  * Reset PF device.
2918  */
2919 static int
2920 ixgbe_dev_reset(struct rte_eth_dev *dev)
2921 {
2922         int ret;
2923
2924         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2925          * its VF to make them align with it. The detailed notification
2926          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2927          * To avoid unexpected behavior in VF, currently reset of PF with
2928          * SR-IOV activation is not supported. It might be supported later.
2929          */
2930         if (dev->data->sriov.active)
2931                 return -ENOTSUP;
2932
2933         ret = eth_ixgbe_dev_uninit(dev);
2934         if (ret)
2935                 return ret;
2936
2937         ret = eth_ixgbe_dev_init(dev, NULL);
2938
2939         return ret;
2940 }
2941
2942 static void
2943 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2944                            struct ixgbe_hw_stats *hw_stats,
2945                            struct ixgbe_macsec_stats *macsec_stats,
2946                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2947                            uint64_t *total_qprc, uint64_t *total_qprdc)
2948 {
2949         uint32_t bprc, lxon, lxoff, total;
2950         uint32_t delta_gprc = 0;
2951         unsigned i;
2952         /* Workaround for RX byte count not including CRC bytes when CRC
2953          * strip is enabled. CRC bytes are removed from counters when crc_strip
2954          * is disabled.
2955          */
2956         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2957                         IXGBE_HLREG0_RXCRCSTRP);
2958
2959         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2960         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2961         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2962         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2963
2964         for (i = 0; i < 8; i++) {
2965                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2966
2967                 /* global total per queue */
2968                 hw_stats->mpc[i] += mp;
2969                 /* Running comprehensive total for stats display */
2970                 *total_missed_rx += hw_stats->mpc[i];
2971                 if (hw->mac.type == ixgbe_mac_82598EB) {
2972                         hw_stats->rnbc[i] +=
2973                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2974                         hw_stats->pxonrxc[i] +=
2975                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2976                         hw_stats->pxoffrxc[i] +=
2977                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2978                 } else {
2979                         hw_stats->pxonrxc[i] +=
2980                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2981                         hw_stats->pxoffrxc[i] +=
2982                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2983                         hw_stats->pxon2offc[i] +=
2984                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2985                 }
2986                 hw_stats->pxontxc[i] +=
2987                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2988                 hw_stats->pxofftxc[i] +=
2989                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2990         }
2991         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2992                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2993                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2994                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2995
2996                 delta_gprc += delta_qprc;
2997
2998                 hw_stats->qprc[i] += delta_qprc;
2999                 hw_stats->qptc[i] += delta_qptc;
3000
3001                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3002                 hw_stats->qbrc[i] +=
3003                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3004                 if (crc_strip == 0)
3005                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3006
3007                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3008                 hw_stats->qbtc[i] +=
3009                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3010
3011                 hw_stats->qprdc[i] += delta_qprdc;
3012                 *total_qprdc += hw_stats->qprdc[i];
3013
3014                 *total_qprc += hw_stats->qprc[i];
3015                 *total_qbrc += hw_stats->qbrc[i];
3016         }
3017         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3018         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3019         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3020
3021         /*
3022          * An errata states that gprc actually counts good + missed packets:
3023          * Workaround to set gprc to summated queue packet receives
3024          */
3025         hw_stats->gprc = *total_qprc;
3026
3027         if (hw->mac.type != ixgbe_mac_82598EB) {
3028                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3029                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3030                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3031                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3032                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3033                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3034                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3035                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3036         } else {
3037                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3038                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3039                 /* 82598 only has a counter in the high register */
3040                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3041                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3042                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3043         }
3044         uint64_t old_tpr = hw_stats->tpr;
3045
3046         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3047         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3048
3049         if (crc_strip == 0)
3050                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3051
3052         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3053         hw_stats->gptc += delta_gptc;
3054         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3055         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3056
3057         /*
3058          * Workaround: mprc hardware is incorrectly counting
3059          * broadcasts, so for now we subtract those.
3060          */
3061         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3062         hw_stats->bprc += bprc;
3063         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3064         if (hw->mac.type == ixgbe_mac_82598EB)
3065                 hw_stats->mprc -= bprc;
3066
3067         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3068         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3069         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3070         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3071         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3072         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3073
3074         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3075         hw_stats->lxontxc += lxon;
3076         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3077         hw_stats->lxofftxc += lxoff;
3078         total = lxon + lxoff;
3079
3080         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3081         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3082         hw_stats->gptc -= total;
3083         hw_stats->mptc -= total;
3084         hw_stats->ptc64 -= total;
3085         hw_stats->gotc -= total * ETHER_MIN_LEN;
3086
3087         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3088         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3089         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3090         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3091         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3092         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3093         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3094         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3095         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3096         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3097         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3098         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3099         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3100         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3101         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3102         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3103         /* Only read FCOE on 82599 */
3104         if (hw->mac.type != ixgbe_mac_82598EB) {
3105                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3106                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3107                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3108                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3109                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3110         }
3111
3112         /* Flow Director Stats registers */
3113         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3114         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3115
3116         /* MACsec Stats registers */
3117         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3118         macsec_stats->out_pkts_encrypted +=
3119                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3120         macsec_stats->out_pkts_protected +=
3121                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3122         macsec_stats->out_octets_encrypted +=
3123                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3124         macsec_stats->out_octets_protected +=
3125                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3126         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3127         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3128         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3129         macsec_stats->in_pkts_unknownsci +=
3130                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3131         macsec_stats->in_octets_decrypted +=
3132                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3133         macsec_stats->in_octets_validated +=
3134                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3135         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3136         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3137         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3138         for (i = 0; i < 2; i++) {
3139                 macsec_stats->in_pkts_ok +=
3140                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3141                 macsec_stats->in_pkts_invalid +=
3142                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3143                 macsec_stats->in_pkts_notvalid +=
3144                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3145         }
3146         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3147         macsec_stats->in_pkts_notusingsa +=
3148                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3149 }
3150
3151 /*
3152  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3153  */
3154 static int
3155 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3156 {
3157         struct ixgbe_hw *hw =
3158                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3159         struct ixgbe_hw_stats *hw_stats =
3160                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3161         struct ixgbe_macsec_stats *macsec_stats =
3162                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3163                                 dev->data->dev_private);
3164         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3165         unsigned i;
3166
3167         total_missed_rx = 0;
3168         total_qbrc = 0;
3169         total_qprc = 0;
3170         total_qprdc = 0;
3171
3172         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3173                         &total_qbrc, &total_qprc, &total_qprdc);
3174
3175         if (stats == NULL)
3176                 return -EINVAL;
3177
3178         /* Fill out the rte_eth_stats statistics structure */
3179         stats->ipackets = total_qprc;
3180         stats->ibytes = total_qbrc;
3181         stats->opackets = hw_stats->gptc;
3182         stats->obytes = hw_stats->gotc;
3183
3184         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3185                 stats->q_ipackets[i] = hw_stats->qprc[i];
3186                 stats->q_opackets[i] = hw_stats->qptc[i];
3187                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3188                 stats->q_obytes[i] = hw_stats->qbtc[i];
3189                 stats->q_errors[i] = hw_stats->qprdc[i];
3190         }
3191
3192         /* Rx Errors */
3193         stats->imissed  = total_missed_rx;
3194         stats->ierrors  = hw_stats->crcerrs +
3195                           hw_stats->mspdc +
3196                           hw_stats->rlec +
3197                           hw_stats->ruc +
3198                           hw_stats->roc +
3199                           hw_stats->illerrc +
3200                           hw_stats->errbc +
3201                           hw_stats->rfc +
3202                           hw_stats->fccrc +
3203                           hw_stats->fclast;
3204
3205         /* Tx Errors */
3206         stats->oerrors  = 0;
3207         return 0;
3208 }
3209
3210 static void
3211 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3212 {
3213         struct ixgbe_hw_stats *stats =
3214                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3215
3216         /* HW registers are cleared on read */
3217         ixgbe_dev_stats_get(dev, NULL);
3218
3219         /* Reset software totals */
3220         memset(stats, 0, sizeof(*stats));
3221 }
3222
3223 /* This function calculates the number of xstats based on the current config */
3224 static unsigned
3225 ixgbe_xstats_calc_num(void) {
3226         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3227                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3228                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3229 }
3230
3231 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3232         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3233 {
3234         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3235         unsigned stat, i, count;
3236
3237         if (xstats_names != NULL) {
3238                 count = 0;
3239
3240                 /* Note: limit >= cnt_stats checked upstream
3241                  * in rte_eth_xstats_names()
3242                  */
3243
3244                 /* Extended stats from ixgbe_hw_stats */
3245                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3246                         snprintf(xstats_names[count].name,
3247                                 sizeof(xstats_names[count].name),
3248                                 "%s",
3249                                 rte_ixgbe_stats_strings[i].name);
3250                         count++;
3251                 }
3252
3253                 /* MACsec Stats */
3254                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3255                         snprintf(xstats_names[count].name,
3256                                 sizeof(xstats_names[count].name),
3257                                 "%s",
3258                                 rte_ixgbe_macsec_strings[i].name);
3259                         count++;
3260                 }
3261
3262                 /* RX Priority Stats */
3263                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3264                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3265                                 snprintf(xstats_names[count].name,
3266                                         sizeof(xstats_names[count].name),
3267                                         "rx_priority%u_%s", i,
3268                                         rte_ixgbe_rxq_strings[stat].name);
3269                                 count++;
3270                         }
3271                 }
3272
3273                 /* TX Priority Stats */
3274                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3275                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3276                                 snprintf(xstats_names[count].name,
3277                                         sizeof(xstats_names[count].name),
3278                                         "tx_priority%u_%s", i,
3279                                         rte_ixgbe_txq_strings[stat].name);
3280                                 count++;
3281                         }
3282                 }
3283         }
3284         return cnt_stats;
3285 }
3286
3287 static int ixgbe_dev_xstats_get_names_by_id(
3288         struct rte_eth_dev *dev,
3289         struct rte_eth_xstat_name *xstats_names,
3290         const uint64_t *ids,
3291         unsigned int limit)
3292 {
3293         if (!ids) {
3294                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3295                 unsigned int stat, i, count;
3296
3297                 if (xstats_names != NULL) {
3298                         count = 0;
3299
3300                         /* Note: limit >= cnt_stats checked upstream
3301                          * in rte_eth_xstats_names()
3302                          */
3303
3304                         /* Extended stats from ixgbe_hw_stats */
3305                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3306                                 snprintf(xstats_names[count].name,
3307                                         sizeof(xstats_names[count].name),
3308                                         "%s",
3309                                         rte_ixgbe_stats_strings[i].name);
3310                                 count++;
3311                         }
3312
3313                         /* MACsec Stats */
3314                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3315                                 snprintf(xstats_names[count].name,
3316                                         sizeof(xstats_names[count].name),
3317                                         "%s",
3318                                         rte_ixgbe_macsec_strings[i].name);
3319                                 count++;
3320                         }
3321
3322                         /* RX Priority Stats */
3323                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3324                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3325                                         snprintf(xstats_names[count].name,
3326                                             sizeof(xstats_names[count].name),
3327                                             "rx_priority%u_%s", i,
3328                                             rte_ixgbe_rxq_strings[stat].name);
3329                                         count++;
3330                                 }
3331                         }
3332
3333                         /* TX Priority Stats */
3334                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3335                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3336                                         snprintf(xstats_names[count].name,
3337                                             sizeof(xstats_names[count].name),
3338                                             "tx_priority%u_%s", i,
3339                                             rte_ixgbe_txq_strings[stat].name);
3340                                         count++;
3341                                 }
3342                         }
3343                 }
3344                 return cnt_stats;
3345         }
3346
3347         uint16_t i;
3348         uint16_t size = ixgbe_xstats_calc_num();
3349         struct rte_eth_xstat_name xstats_names_copy[size];
3350
3351         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3352                         size);
3353
3354         for (i = 0; i < limit; i++) {
3355                 if (ids[i] >= size) {
3356                         PMD_INIT_LOG(ERR, "id value isn't valid");
3357                         return -1;
3358                 }
3359                 strcpy(xstats_names[i].name,
3360                                 xstats_names_copy[ids[i]].name);
3361         }
3362         return limit;
3363 }
3364
3365 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3366         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3367 {
3368         unsigned i;
3369
3370         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3371                 return -ENOMEM;
3372
3373         if (xstats_names != NULL)
3374                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3375                         snprintf(xstats_names[i].name,
3376                                 sizeof(xstats_names[i].name),
3377                                 "%s", rte_ixgbevf_stats_strings[i].name);
3378         return IXGBEVF_NB_XSTATS;
3379 }
3380
3381 static int
3382 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3383                                          unsigned n)
3384 {
3385         struct ixgbe_hw *hw =
3386                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3387         struct ixgbe_hw_stats *hw_stats =
3388                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3389         struct ixgbe_macsec_stats *macsec_stats =
3390                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3391                                 dev->data->dev_private);
3392         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3393         unsigned i, stat, count = 0;
3394
3395         count = ixgbe_xstats_calc_num();
3396
3397         if (n < count)
3398                 return count;
3399
3400         total_missed_rx = 0;
3401         total_qbrc = 0;
3402         total_qprc = 0;
3403         total_qprdc = 0;
3404
3405         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3406                         &total_qbrc, &total_qprc, &total_qprdc);
3407
3408         /* If this is a reset xstats is NULL, and we have cleared the
3409          * registers by reading them.
3410          */
3411         if (!xstats)
3412                 return 0;
3413
3414         /* Extended stats from ixgbe_hw_stats */
3415         count = 0;
3416         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3417                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3418                                 rte_ixgbe_stats_strings[i].offset);
3419                 xstats[count].id = count;
3420                 count++;
3421         }
3422
3423         /* MACsec Stats */
3424         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3425                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3426                                 rte_ixgbe_macsec_strings[i].offset);
3427                 xstats[count].id = count;
3428                 count++;
3429         }
3430
3431         /* RX Priority Stats */
3432         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3433                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3434                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3435                                         rte_ixgbe_rxq_strings[stat].offset +
3436                                         (sizeof(uint64_t) * i));
3437                         xstats[count].id = count;
3438                         count++;
3439                 }
3440         }
3441
3442         /* TX Priority Stats */
3443         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3444                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3445                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3446                                         rte_ixgbe_txq_strings[stat].offset +
3447                                         (sizeof(uint64_t) * i));
3448                         xstats[count].id = count;
3449                         count++;
3450                 }
3451         }
3452         return count;
3453 }
3454
3455 static int
3456 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3457                 uint64_t *values, unsigned int n)
3458 {
3459         if (!ids) {
3460                 struct ixgbe_hw *hw =
3461                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462                 struct ixgbe_hw_stats *hw_stats =
3463                                 IXGBE_DEV_PRIVATE_TO_STATS(
3464                                                 dev->data->dev_private);
3465                 struct ixgbe_macsec_stats *macsec_stats =
3466                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3467                                         dev->data->dev_private);
3468                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3469                 unsigned int i, stat, count = 0;
3470
3471                 count = ixgbe_xstats_calc_num();
3472
3473                 if (!ids && n < count)
3474                         return count;
3475
3476                 total_missed_rx = 0;
3477                 total_qbrc = 0;
3478                 total_qprc = 0;
3479                 total_qprdc = 0;
3480
3481                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3482                                 &total_missed_rx, &total_qbrc, &total_qprc,
3483                                 &total_qprdc);
3484
3485                 /* If this is a reset xstats is NULL, and we have cleared the
3486                  * registers by reading them.
3487                  */
3488                 if (!ids && !values)
3489                         return 0;
3490
3491                 /* Extended stats from ixgbe_hw_stats */
3492                 count = 0;
3493                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3494                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3495                                         rte_ixgbe_stats_strings[i].offset);
3496                         count++;
3497                 }
3498
3499                 /* MACsec Stats */
3500                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3501                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3502                                         rte_ixgbe_macsec_strings[i].offset);
3503                         count++;
3504                 }
3505
3506                 /* RX Priority Stats */
3507                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3508                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3509                                 values[count] =
3510                                         *(uint64_t *)(((char *)hw_stats) +
3511                                         rte_ixgbe_rxq_strings[stat].offset +
3512                                         (sizeof(uint64_t) * i));
3513                                 count++;
3514                         }
3515                 }
3516
3517                 /* TX Priority Stats */
3518                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3519                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3520                                 values[count] =
3521                                         *(uint64_t *)(((char *)hw_stats) +
3522                                         rte_ixgbe_txq_strings[stat].offset +
3523                                         (sizeof(uint64_t) * i));
3524                                 count++;
3525                         }
3526                 }
3527                 return count;
3528         }
3529
3530         uint16_t i;
3531         uint16_t size = ixgbe_xstats_calc_num();
3532         uint64_t values_copy[size];
3533
3534         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3535
3536         for (i = 0; i < n; i++) {
3537                 if (ids[i] >= size) {
3538                         PMD_INIT_LOG(ERR, "id value isn't valid");
3539                         return -1;
3540                 }
3541                 values[i] = values_copy[ids[i]];
3542         }
3543         return n;
3544 }
3545
3546 static void
3547 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3548 {
3549         struct ixgbe_hw_stats *stats =
3550                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3551         struct ixgbe_macsec_stats *macsec_stats =
3552                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3553                                 dev->data->dev_private);
3554
3555         unsigned count = ixgbe_xstats_calc_num();
3556
3557         /* HW registers are cleared on read */
3558         ixgbe_dev_xstats_get(dev, NULL, count);
3559
3560         /* Reset software totals */
3561         memset(stats, 0, sizeof(*stats));
3562         memset(macsec_stats, 0, sizeof(*macsec_stats));
3563 }
3564
3565 static void
3566 ixgbevf_update_stats(struct rte_eth_dev *dev)
3567 {
3568         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3569         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3570                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3571
3572         /* Good Rx packet, include VF loopback */
3573         UPDATE_VF_STAT(IXGBE_VFGPRC,
3574             hw_stats->last_vfgprc, hw_stats->vfgprc);
3575
3576         /* Good Rx octets, include VF loopback */
3577         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3578             hw_stats->last_vfgorc, hw_stats->vfgorc);
3579
3580         /* Good Tx packet, include VF loopback */
3581         UPDATE_VF_STAT(IXGBE_VFGPTC,
3582             hw_stats->last_vfgptc, hw_stats->vfgptc);
3583
3584         /* Good Tx octets, include VF loopback */
3585         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3586             hw_stats->last_vfgotc, hw_stats->vfgotc);
3587
3588         /* Rx Multicst Packet */
3589         UPDATE_VF_STAT(IXGBE_VFMPRC,
3590             hw_stats->last_vfmprc, hw_stats->vfmprc);
3591 }
3592
3593 static int
3594 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3595                        unsigned n)
3596 {
3597         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3598                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3599         unsigned i;
3600
3601         if (n < IXGBEVF_NB_XSTATS)
3602                 return IXGBEVF_NB_XSTATS;
3603
3604         ixgbevf_update_stats(dev);
3605
3606         if (!xstats)
3607                 return 0;
3608
3609         /* Extended stats */
3610         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3611                 xstats[i].id = i;
3612                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3613                         rte_ixgbevf_stats_strings[i].offset);
3614         }
3615
3616         return IXGBEVF_NB_XSTATS;
3617 }
3618
3619 static int
3620 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3621 {
3622         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3623                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3624
3625         ixgbevf_update_stats(dev);
3626
3627         if (stats == NULL)
3628                 return -EINVAL;
3629
3630         stats->ipackets = hw_stats->vfgprc;
3631         stats->ibytes = hw_stats->vfgorc;
3632         stats->opackets = hw_stats->vfgptc;
3633         stats->obytes = hw_stats->vfgotc;
3634         return 0;
3635 }
3636
3637 static void
3638 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3639 {
3640         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3641                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3642
3643         /* Sync HW register to the last stats */
3644         ixgbevf_dev_stats_get(dev, NULL);
3645
3646         /* reset HW current stats*/
3647         hw_stats->vfgprc = 0;
3648         hw_stats->vfgorc = 0;
3649         hw_stats->vfgptc = 0;
3650         hw_stats->vfgotc = 0;
3651 }
3652
3653 static int
3654 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3655 {
3656         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3657         u16 eeprom_verh, eeprom_verl;
3658         u32 etrack_id;
3659         int ret;
3660
3661         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3662         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3663
3664         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3665         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3666
3667         ret += 1; /* add the size of '\0' */
3668         if (fw_size < (u32)ret)
3669                 return ret;
3670         else
3671                 return 0;
3672 }
3673
3674 static void
3675 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3676 {
3677         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3678         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3679         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3680
3681         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3682         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3683         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3684                 /*
3685                  * When DCB/VT is off, maximum number of queues changes,
3686                  * except for 82598EB, which remains constant.
3687                  */
3688                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3689                                 hw->mac.type != ixgbe_mac_82598EB)
3690                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3691         }
3692         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3693         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3694         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3695         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3696         dev_info->max_vfs = pci_dev->max_vfs;
3697         if (hw->mac.type == ixgbe_mac_82598EB)
3698                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3699         else
3700                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3701         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3702         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3703         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3704                                      dev_info->rx_queue_offload_capa);
3705         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3706         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3707
3708         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3709                 .rx_thresh = {
3710                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3711                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3712                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3713                 },
3714                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3715                 .rx_drop_en = 0,
3716                 .offloads = 0,
3717         };
3718
3719         dev_info->default_txconf = (struct rte_eth_txconf) {
3720                 .tx_thresh = {
3721                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3722                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3723                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3724                 },
3725                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3726                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3727                 .offloads = 0,
3728         };
3729
3730         dev_info->rx_desc_lim = rx_desc_lim;
3731         dev_info->tx_desc_lim = tx_desc_lim;
3732
3733         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3734         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3735         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3736
3737         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3738         if (hw->mac.type == ixgbe_mac_X540 ||
3739             hw->mac.type == ixgbe_mac_X540_vf ||
3740             hw->mac.type == ixgbe_mac_X550 ||
3741             hw->mac.type == ixgbe_mac_X550_vf) {
3742                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3743         }
3744         if (hw->mac.type == ixgbe_mac_X550) {
3745                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3746                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3747         }
3748 }
3749
3750 static const uint32_t *
3751 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3752 {
3753         static const uint32_t ptypes[] = {
3754                 /* For non-vec functions,
3755                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3756                  * for vec functions,
3757                  * refers to _recv_raw_pkts_vec().
3758                  */
3759                 RTE_PTYPE_L2_ETHER,
3760                 RTE_PTYPE_L3_IPV4,
3761                 RTE_PTYPE_L3_IPV4_EXT,
3762                 RTE_PTYPE_L3_IPV6,
3763                 RTE_PTYPE_L3_IPV6_EXT,
3764                 RTE_PTYPE_L4_SCTP,
3765                 RTE_PTYPE_L4_TCP,
3766                 RTE_PTYPE_L4_UDP,
3767                 RTE_PTYPE_TUNNEL_IP,
3768                 RTE_PTYPE_INNER_L3_IPV6,
3769                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3770                 RTE_PTYPE_INNER_L4_TCP,
3771                 RTE_PTYPE_INNER_L4_UDP,
3772                 RTE_PTYPE_UNKNOWN
3773         };
3774
3775         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3776             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3777             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3778             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3779                 return ptypes;
3780
3781 #if defined(RTE_ARCH_X86)
3782         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3783             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3784                 return ptypes;
3785 #endif
3786         return NULL;
3787 }
3788
3789 static void
3790 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3791                      struct rte_eth_dev_info *dev_info)
3792 {
3793         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3794         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3795
3796         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3797         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3798         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3799         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3800         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3801         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3802         dev_info->max_vfs = pci_dev->max_vfs;
3803         if (hw->mac.type == ixgbe_mac_82598EB)
3804                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3805         else
3806                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3807         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3808         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3809                                      dev_info->rx_queue_offload_capa);
3810         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3811         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3812
3813         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3814                 .rx_thresh = {
3815                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3816                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3817                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3818                 },
3819                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3820                 .rx_drop_en = 0,
3821                 .offloads = 0,
3822         };
3823
3824         dev_info->default_txconf = (struct rte_eth_txconf) {
3825                 .tx_thresh = {
3826                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3827                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3828                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3829                 },
3830                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3831                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3832                 .offloads = 0,
3833         };
3834
3835         dev_info->rx_desc_lim = rx_desc_lim;
3836         dev_info->tx_desc_lim = tx_desc_lim;
3837 }
3838
3839 static int
3840 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3841                    int *link_up, int wait_to_complete)
3842 {
3843         /**
3844          * for a quick link status checking, wait_to_compelet == 0,
3845          * skip PF link status checking
3846          */
3847         bool no_pflink_check = wait_to_complete == 0;
3848         struct ixgbe_mbx_info *mbx = &hw->mbx;
3849         struct ixgbe_mac_info *mac = &hw->mac;
3850         uint32_t links_reg, in_msg;
3851         int ret_val = 0;
3852
3853         /* If we were hit with a reset drop the link */
3854         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3855                 mac->get_link_status = true;
3856
3857         if (!mac->get_link_status)
3858                 goto out;
3859
3860         /* if link status is down no point in checking to see if pf is up */
3861         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3862         if (!(links_reg & IXGBE_LINKS_UP))
3863                 goto out;
3864
3865         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3866          * before the link status is correct
3867          */
3868         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3869                 int i;
3870
3871                 for (i = 0; i < 5; i++) {
3872                         rte_delay_us(100);
3873                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3874
3875                         if (!(links_reg & IXGBE_LINKS_UP))
3876                                 goto out;
3877                 }
3878         }
3879
3880         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3881         case IXGBE_LINKS_SPEED_10G_82599:
3882                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3883                 if (hw->mac.type >= ixgbe_mac_X550) {
3884                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3885                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3886                 }
3887                 break;
3888         case IXGBE_LINKS_SPEED_1G_82599:
3889                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3890                 break;
3891         case IXGBE_LINKS_SPEED_100_82599:
3892                 *speed = IXGBE_LINK_SPEED_100_FULL;
3893                 if (hw->mac.type == ixgbe_mac_X550) {
3894                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3895                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3896                 }
3897                 break;
3898         case IXGBE_LINKS_SPEED_10_X550EM_A:
3899                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3900                 /* Since Reserved in older MAC's */
3901                 if (hw->mac.type >= ixgbe_mac_X550)
3902                         *speed = IXGBE_LINK_SPEED_10_FULL;
3903                 break;
3904         default:
3905                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3906         }
3907
3908         if (no_pflink_check) {
3909                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3910                         mac->get_link_status = true;
3911                 else
3912                         mac->get_link_status = false;
3913
3914                 goto out;
3915         }
3916         /* if the read failed it could just be a mailbox collision, best wait
3917          * until we are called again and don't report an error
3918          */
3919         if (mbx->ops.read(hw, &in_msg, 1, 0))
3920                 goto out;
3921
3922         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3923                 /* msg is not CTS and is NACK we must have lost CTS status */
3924                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3925                         ret_val = -1;
3926                 goto out;
3927         }
3928
3929         /* the pf is talking, if we timed out in the past we reinit */
3930         if (!mbx->timeout) {
3931                 ret_val = -1;
3932                 goto out;
3933         }
3934
3935         /* if we passed all the tests above then the link is up and we no
3936          * longer need to check for link
3937          */
3938         mac->get_link_status = false;
3939
3940 out:
3941         *link_up = !mac->get_link_status;
3942         return ret_val;
3943 }
3944
3945 /* return 0 means link status changed, -1 means not changed */
3946 int
3947 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3948                             int wait_to_complete, int vf)
3949 {
3950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3951         struct rte_eth_link link;
3952         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3953         struct ixgbe_interrupt *intr =
3954                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3955         int link_up;
3956         int diag;
3957         u32 speed = 0;
3958         int wait = 1;
3959         bool autoneg = false;
3960
3961         memset(&link, 0, sizeof(link));
3962         link.link_status = ETH_LINK_DOWN;
3963         link.link_speed = ETH_SPEED_NUM_NONE;
3964         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3965         link.link_autoneg = ETH_LINK_AUTONEG;
3966
3967         hw->mac.get_link_status = true;
3968
3969         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3970                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3971                 speed = hw->phy.autoneg_advertised;
3972                 if (!speed)
3973                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3974                 ixgbe_setup_link(hw, speed, true);
3975         }
3976
3977         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3978         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3979                 wait = 0;
3980
3981         if (vf)
3982                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3983         else
3984                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3985
3986         if (diag != 0) {
3987                 link.link_speed = ETH_SPEED_NUM_100M;
3988                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3989                 return rte_eth_linkstatus_set(dev, &link);
3990         }
3991
3992         if (link_up == 0) {
3993                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3994                 return rte_eth_linkstatus_set(dev, &link);
3995         }
3996
3997         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3998         link.link_status = ETH_LINK_UP;
3999         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4000
4001         switch (link_speed) {
4002         default:
4003         case IXGBE_LINK_SPEED_UNKNOWN:
4004                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4005                 link.link_speed = ETH_SPEED_NUM_100M;
4006                 break;
4007
4008         case IXGBE_LINK_SPEED_100_FULL:
4009                 link.link_speed = ETH_SPEED_NUM_100M;
4010                 break;
4011
4012         case IXGBE_LINK_SPEED_1GB_FULL:
4013                 link.link_speed = ETH_SPEED_NUM_1G;
4014                 break;
4015
4016         case IXGBE_LINK_SPEED_2_5GB_FULL:
4017                 link.link_speed = ETH_SPEED_NUM_2_5G;
4018                 break;
4019
4020         case IXGBE_LINK_SPEED_5GB_FULL:
4021                 link.link_speed = ETH_SPEED_NUM_5G;
4022                 break;
4023
4024         case IXGBE_LINK_SPEED_10GB_FULL:
4025                 link.link_speed = ETH_SPEED_NUM_10G;
4026                 break;
4027         }
4028
4029         return rte_eth_linkstatus_set(dev, &link);
4030 }
4031
4032 static int
4033 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4034 {
4035         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4036 }
4037
4038 static int
4039 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4040 {
4041         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4042 }
4043
4044 static void
4045 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4046 {
4047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4048         uint32_t fctrl;
4049
4050         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4051         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4052         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4053 }
4054
4055 static void
4056 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4057 {
4058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4059         uint32_t fctrl;
4060
4061         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4062         fctrl &= (~IXGBE_FCTRL_UPE);
4063         if (dev->data->all_multicast == 1)
4064                 fctrl |= IXGBE_FCTRL_MPE;
4065         else
4066                 fctrl &= (~IXGBE_FCTRL_MPE);
4067         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4068 }
4069
4070 static void
4071 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4072 {
4073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4074         uint32_t fctrl;
4075
4076         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4077         fctrl |= IXGBE_FCTRL_MPE;
4078         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4079 }
4080
4081 static void
4082 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4083 {
4084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4085         uint32_t fctrl;
4086
4087         if (dev->data->promiscuous == 1)
4088                 return; /* must remain in all_multicast mode */
4089
4090         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4091         fctrl &= (~IXGBE_FCTRL_MPE);
4092         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4093 }
4094
4095 /**
4096  * It clears the interrupt causes and enables the interrupt.
4097  * It will be called once only during nic initialized.
4098  *
4099  * @param dev
4100  *  Pointer to struct rte_eth_dev.
4101  * @param on
4102  *  Enable or Disable.
4103  *
4104  * @return
4105  *  - On success, zero.
4106  *  - On failure, a negative value.
4107  */
4108 static int
4109 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4110 {
4111         struct ixgbe_interrupt *intr =
4112                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4113
4114         ixgbe_dev_link_status_print(dev);
4115         if (on)
4116                 intr->mask |= IXGBE_EICR_LSC;
4117         else
4118                 intr->mask &= ~IXGBE_EICR_LSC;
4119
4120         return 0;
4121 }
4122
4123 /**
4124  * It clears the interrupt causes and enables the interrupt.
4125  * It will be called once only during nic initialized.
4126  *
4127  * @param dev
4128  *  Pointer to struct rte_eth_dev.
4129  *
4130  * @return
4131  *  - On success, zero.
4132  *  - On failure, a negative value.
4133  */
4134 static int
4135 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4136 {
4137         struct ixgbe_interrupt *intr =
4138                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4139
4140         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4141
4142         return 0;
4143 }
4144
4145 /**
4146  * It clears the interrupt causes and enables the interrupt.
4147  * It will be called once only during nic initialized.
4148  *
4149  * @param dev
4150  *  Pointer to struct rte_eth_dev.
4151  *
4152  * @return
4153  *  - On success, zero.
4154  *  - On failure, a negative value.
4155  */
4156 static int
4157 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4158 {
4159         struct ixgbe_interrupt *intr =
4160                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4161
4162         intr->mask |= IXGBE_EICR_LINKSEC;
4163
4164         return 0;
4165 }
4166
4167 /*
4168  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4169  *
4170  * @param dev
4171  *  Pointer to struct rte_eth_dev.
4172  *
4173  * @return
4174  *  - On success, zero.
4175  *  - On failure, a negative value.
4176  */
4177 static int
4178 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4179 {
4180         uint32_t eicr;
4181         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182         struct ixgbe_interrupt *intr =
4183                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4184
4185         /* clear all cause mask */
4186         ixgbe_disable_intr(hw);
4187
4188         /* read-on-clear nic registers here */
4189         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4190         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4191
4192         intr->flags = 0;
4193
4194         /* set flag for async link update */
4195         if (eicr & IXGBE_EICR_LSC)
4196                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4197
4198         if (eicr & IXGBE_EICR_MAILBOX)
4199                 intr->flags |= IXGBE_FLAG_MAILBOX;
4200
4201         if (eicr & IXGBE_EICR_LINKSEC)
4202                 intr->flags |= IXGBE_FLAG_MACSEC;
4203
4204         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4205             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4206             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4207                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4208
4209         return 0;
4210 }
4211
4212 /**
4213  * It gets and then prints the link status.
4214  *
4215  * @param dev
4216  *  Pointer to struct rte_eth_dev.
4217  *
4218  * @return
4219  *  - On success, zero.
4220  *  - On failure, a negative value.
4221  */
4222 static void
4223 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4224 {
4225         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4226         struct rte_eth_link link;
4227
4228         rte_eth_linkstatus_get(dev, &link);
4229
4230         if (link.link_status) {
4231                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4232                                         (int)(dev->data->port_id),
4233                                         (unsigned)link.link_speed,
4234                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4235                                         "full-duplex" : "half-duplex");
4236         } else {
4237                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4238                                 (int)(dev->data->port_id));
4239         }
4240         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4241                                 pci_dev->addr.domain,
4242                                 pci_dev->addr.bus,
4243                                 pci_dev->addr.devid,
4244                                 pci_dev->addr.function);
4245 }
4246
4247 /*
4248  * It executes link_update after knowing an interrupt occurred.
4249  *
4250  * @param dev
4251  *  Pointer to struct rte_eth_dev.
4252  *
4253  * @return
4254  *  - On success, zero.
4255  *  - On failure, a negative value.
4256  */
4257 static int
4258 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4259                            struct rte_intr_handle *intr_handle)
4260 {
4261         struct ixgbe_interrupt *intr =
4262                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4263         int64_t timeout;
4264         struct ixgbe_hw *hw =
4265                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4266
4267         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4268
4269         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4270                 ixgbe_pf_mbx_process(dev);
4271                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4272         }
4273
4274         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4275                 ixgbe_handle_lasi(hw);
4276                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4277         }
4278
4279         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4280                 struct rte_eth_link link;
4281
4282                 /* get the link status before link update, for predicting later */
4283                 rte_eth_linkstatus_get(dev, &link);
4284
4285                 ixgbe_dev_link_update(dev, 0);
4286
4287                 /* likely to up */
4288                 if (!link.link_status)
4289                         /* handle it 1 sec later, wait it being stable */
4290                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4291                 /* likely to down */
4292                 else
4293                         /* handle it 4 sec later, wait it being stable */
4294                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4295
4296                 ixgbe_dev_link_status_print(dev);
4297                 if (rte_eal_alarm_set(timeout * 1000,
4298                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4299                         PMD_DRV_LOG(ERR, "Error setting alarm");
4300                 else {
4301                         /* remember original mask */
4302                         intr->mask_original = intr->mask;
4303                         /* only disable lsc interrupt */
4304                         intr->mask &= ~IXGBE_EIMS_LSC;
4305                 }
4306         }
4307
4308         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4309         ixgbe_enable_intr(dev);
4310         rte_intr_enable(intr_handle);
4311
4312         return 0;
4313 }
4314
4315 /**
4316  * Interrupt handler which shall be registered for alarm callback for delayed
4317  * handling specific interrupt to wait for the stable nic state. As the
4318  * NIC interrupt state is not stable for ixgbe after link is just down,
4319  * it needs to wait 4 seconds to get the stable status.
4320  *
4321  * @param handle
4322  *  Pointer to interrupt handle.
4323  * @param param
4324  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4325  *
4326  * @return
4327  *  void
4328  */
4329 static void
4330 ixgbe_dev_interrupt_delayed_handler(void *param)
4331 {
4332         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4333         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4334         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4335         struct ixgbe_interrupt *intr =
4336                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4337         struct ixgbe_hw *hw =
4338                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4339         uint32_t eicr;
4340
4341         ixgbe_disable_intr(hw);
4342
4343         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4344         if (eicr & IXGBE_EICR_MAILBOX)
4345                 ixgbe_pf_mbx_process(dev);
4346
4347         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4348                 ixgbe_handle_lasi(hw);
4349                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4350         }
4351
4352         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4353                 ixgbe_dev_link_update(dev, 0);
4354                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4355                 ixgbe_dev_link_status_print(dev);
4356                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4357                                               NULL);
4358         }
4359
4360         if (intr->flags & IXGBE_FLAG_MACSEC) {
4361                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4362                                               NULL);
4363                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4364         }
4365
4366         /* restore original mask */
4367         intr->mask = intr->mask_original;
4368         intr->mask_original = 0;
4369
4370         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4371         ixgbe_enable_intr(dev);
4372         rte_intr_enable(intr_handle);
4373 }
4374
4375 /**
4376  * Interrupt handler triggered by NIC  for handling
4377  * specific interrupt.
4378  *
4379  * @param handle
4380  *  Pointer to interrupt handle.
4381  * @param param
4382  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4383  *
4384  * @return
4385  *  void
4386  */
4387 static void
4388 ixgbe_dev_interrupt_handler(void *param)
4389 {
4390         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4391
4392         ixgbe_dev_interrupt_get_status(dev);
4393         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4394 }
4395
4396 static int
4397 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4398 {
4399         struct ixgbe_hw *hw;
4400
4401         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4402         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4403 }
4404
4405 static int
4406 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4407 {
4408         struct ixgbe_hw *hw;
4409
4410         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4411         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4412 }
4413
4414 static int
4415 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4416 {
4417         struct ixgbe_hw *hw;
4418         uint32_t mflcn_reg;
4419         uint32_t fccfg_reg;
4420         int rx_pause;
4421         int tx_pause;
4422
4423         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4424
4425         fc_conf->pause_time = hw->fc.pause_time;
4426         fc_conf->high_water = hw->fc.high_water[0];
4427         fc_conf->low_water = hw->fc.low_water[0];
4428         fc_conf->send_xon = hw->fc.send_xon;
4429         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4430
4431         /*
4432          * Return rx_pause status according to actual setting of
4433          * MFLCN register.
4434          */
4435         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4436         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4437                 rx_pause = 1;
4438         else
4439                 rx_pause = 0;
4440
4441         /*
4442          * Return tx_pause status according to actual setting of
4443          * FCCFG register.
4444          */
4445         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4446         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4447                 tx_pause = 1;
4448         else
4449                 tx_pause = 0;
4450
4451         if (rx_pause && tx_pause)
4452                 fc_conf->mode = RTE_FC_FULL;
4453         else if (rx_pause)
4454                 fc_conf->mode = RTE_FC_RX_PAUSE;
4455         else if (tx_pause)
4456                 fc_conf->mode = RTE_FC_TX_PAUSE;
4457         else
4458                 fc_conf->mode = RTE_FC_NONE;
4459
4460         return 0;
4461 }
4462
4463 static int
4464 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4465 {
4466         struct ixgbe_hw *hw;
4467         int err;
4468         uint32_t rx_buf_size;
4469         uint32_t max_high_water;
4470         uint32_t mflcn;
4471         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4472                 ixgbe_fc_none,
4473                 ixgbe_fc_rx_pause,
4474                 ixgbe_fc_tx_pause,
4475                 ixgbe_fc_full
4476         };
4477
4478         PMD_INIT_FUNC_TRACE();
4479
4480         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4482         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4483
4484         /*
4485          * At least reserve one Ethernet frame for watermark
4486          * high_water/low_water in kilo bytes for ixgbe
4487          */
4488         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4489         if ((fc_conf->high_water > max_high_water) ||
4490                 (fc_conf->high_water < fc_conf->low_water)) {
4491                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4492                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4493                 return -EINVAL;
4494         }
4495
4496         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4497         hw->fc.pause_time     = fc_conf->pause_time;
4498         hw->fc.high_water[0]  = fc_conf->high_water;
4499         hw->fc.low_water[0]   = fc_conf->low_water;
4500         hw->fc.send_xon       = fc_conf->send_xon;
4501         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4502
4503         err = ixgbe_fc_enable(hw);
4504
4505         /* Not negotiated is not an error case */
4506         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4507
4508                 /* check if we want to forward MAC frames - driver doesn't have native
4509                  * capability to do that, so we'll write the registers ourselves */
4510
4511                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4512
4513                 /* set or clear MFLCN.PMCF bit depending on configuration */
4514                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4515                         mflcn |= IXGBE_MFLCN_PMCF;
4516                 else
4517                         mflcn &= ~IXGBE_MFLCN_PMCF;
4518
4519                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4520                 IXGBE_WRITE_FLUSH(hw);
4521
4522                 return 0;
4523         }
4524
4525         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4526         return -EIO;
4527 }
4528
4529 /**
4530  *  ixgbe_pfc_enable_generic - Enable flow control
4531  *  @hw: pointer to hardware structure
4532  *  @tc_num: traffic class number
4533  *  Enable flow control according to the current settings.
4534  */
4535 static int
4536 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4537 {
4538         int ret_val = 0;
4539         uint32_t mflcn_reg, fccfg_reg;
4540         uint32_t reg;
4541         uint32_t fcrtl, fcrth;
4542         uint8_t i;
4543         uint8_t nb_rx_en;
4544
4545         /* Validate the water mark configuration */
4546         if (!hw->fc.pause_time) {
4547                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4548                 goto out;
4549         }
4550
4551         /* Low water mark of zero causes XOFF floods */
4552         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4553                  /* High/Low water can not be 0 */
4554                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4555                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4556                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4557                         goto out;
4558                 }
4559
4560                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4561                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4562                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4563                         goto out;
4564                 }
4565         }
4566         /* Negotiate the fc mode to use */
4567         ixgbe_fc_autoneg(hw);
4568
4569         /* Disable any previous flow control settings */
4570         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4571         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4572
4573         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4574         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4575
4576         switch (hw->fc.current_mode) {
4577         case ixgbe_fc_none:
4578                 /*
4579                  * If the count of enabled RX Priority Flow control >1,
4580                  * and the TX pause can not be disabled
4581                  */
4582                 nb_rx_en = 0;
4583                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4584                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4585                         if (reg & IXGBE_FCRTH_FCEN)
4586                                 nb_rx_en++;
4587                 }
4588                 if (nb_rx_en > 1)
4589                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4590                 break;
4591         case ixgbe_fc_rx_pause:
4592                 /*
4593                  * Rx Flow control is enabled and Tx Flow control is
4594                  * disabled by software override. Since there really
4595                  * isn't a way to advertise that we are capable of RX
4596                  * Pause ONLY, we will advertise that we support both
4597                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4598                  * disable the adapter's ability to send PAUSE frames.
4599                  */
4600                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4601                 /*
4602                  * If the count of enabled RX Priority Flow control >1,
4603                  * and the TX pause can not be disabled
4604                  */
4605                 nb_rx_en = 0;
4606                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4607                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4608                         if (reg & IXGBE_FCRTH_FCEN)
4609                                 nb_rx_en++;
4610                 }
4611                 if (nb_rx_en > 1)
4612                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4613                 break;
4614         case ixgbe_fc_tx_pause:
4615                 /*
4616                  * Tx Flow control is enabled, and Rx Flow control is
4617                  * disabled by software override.
4618                  */
4619                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4620                 break;
4621         case ixgbe_fc_full:
4622                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4623                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4624                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4625                 break;
4626         default:
4627                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4628                 ret_val = IXGBE_ERR_CONFIG;
4629                 goto out;
4630         }
4631
4632         /* Set 802.3x based flow control settings. */
4633         mflcn_reg |= IXGBE_MFLCN_DPF;
4634         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4635         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4636
4637         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4638         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4639                 hw->fc.high_water[tc_num]) {
4640                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4641                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4642                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4643         } else {
4644                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4645                 /*
4646                  * In order to prevent Tx hangs when the internal Tx
4647                  * switch is enabled we must set the high water mark
4648                  * to the maximum FCRTH value.  This allows the Tx
4649                  * switch to function even under heavy Rx workloads.
4650                  */
4651                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4652         }
4653         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4654
4655         /* Configure pause time (2 TCs per register) */
4656         reg = hw->fc.pause_time * 0x00010001;
4657         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4658                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4659
4660         /* Configure flow control refresh threshold value */
4661         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4662
4663 out:
4664         return ret_val;
4665 }
4666
4667 static int
4668 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4669 {
4670         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4671         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4672
4673         if (hw->mac.type != ixgbe_mac_82598EB) {
4674                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4675         }
4676         return ret_val;
4677 }
4678
4679 static int
4680 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4681 {
4682         int err;
4683         uint32_t rx_buf_size;
4684         uint32_t max_high_water;
4685         uint8_t tc_num;
4686         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4687         struct ixgbe_hw *hw =
4688                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4689         struct ixgbe_dcb_config *dcb_config =
4690                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4691
4692         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4693                 ixgbe_fc_none,
4694                 ixgbe_fc_rx_pause,
4695                 ixgbe_fc_tx_pause,
4696                 ixgbe_fc_full
4697         };
4698
4699         PMD_INIT_FUNC_TRACE();
4700
4701         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4702         tc_num = map[pfc_conf->priority];
4703         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4704         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4705         /*
4706          * At least reserve one Ethernet frame for watermark
4707          * high_water/low_water in kilo bytes for ixgbe
4708          */
4709         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4710         if ((pfc_conf->fc.high_water > max_high_water) ||
4711             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4712                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4713                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4714                 return -EINVAL;
4715         }
4716
4717         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4718         hw->fc.pause_time = pfc_conf->fc.pause_time;
4719         hw->fc.send_xon = pfc_conf->fc.send_xon;
4720         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4721         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4722
4723         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4724
4725         /* Not negotiated is not an error case */
4726         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4727                 return 0;
4728
4729         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4730         return -EIO;
4731 }
4732
4733 static int
4734 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4735                           struct rte_eth_rss_reta_entry64 *reta_conf,
4736                           uint16_t reta_size)
4737 {
4738         uint16_t i, sp_reta_size;
4739         uint8_t j, mask;
4740         uint32_t reta, r;
4741         uint16_t idx, shift;
4742         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4743         uint32_t reta_reg;
4744
4745         PMD_INIT_FUNC_TRACE();
4746
4747         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4748                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4749                         "NIC.");
4750                 return -ENOTSUP;
4751         }
4752
4753         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4754         if (reta_size != sp_reta_size) {
4755                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4756                         "(%d) doesn't match the number hardware can supported "
4757                         "(%d)", reta_size, sp_reta_size);
4758                 return -EINVAL;
4759         }
4760
4761         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4762                 idx = i / RTE_RETA_GROUP_SIZE;
4763                 shift = i % RTE_RETA_GROUP_SIZE;
4764                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4765                                                 IXGBE_4_BIT_MASK);
4766                 if (!mask)
4767                         continue;
4768                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4769                 if (mask == IXGBE_4_BIT_MASK)
4770                         r = 0;
4771                 else
4772                         r = IXGBE_READ_REG(hw, reta_reg);
4773                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4774                         if (mask & (0x1 << j))
4775                                 reta |= reta_conf[idx].reta[shift + j] <<
4776                                                         (CHAR_BIT * j);
4777                         else
4778                                 reta |= r & (IXGBE_8_BIT_MASK <<
4779                                                 (CHAR_BIT * j));
4780                 }
4781                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4782         }
4783
4784         return 0;
4785 }
4786
4787 static int
4788 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4789                          struct rte_eth_rss_reta_entry64 *reta_conf,
4790                          uint16_t reta_size)
4791 {
4792         uint16_t i, sp_reta_size;
4793         uint8_t j, mask;
4794         uint32_t reta;
4795         uint16_t idx, shift;
4796         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4797         uint32_t reta_reg;
4798
4799         PMD_INIT_FUNC_TRACE();
4800         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4801         if (reta_size != sp_reta_size) {
4802                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4803                         "(%d) doesn't match the number hardware can supported "
4804                         "(%d)", reta_size, sp_reta_size);
4805                 return -EINVAL;
4806         }
4807
4808         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4809                 idx = i / RTE_RETA_GROUP_SIZE;
4810                 shift = i % RTE_RETA_GROUP_SIZE;
4811                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4812                                                 IXGBE_4_BIT_MASK);
4813                 if (!mask)
4814                         continue;
4815
4816                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4817                 reta = IXGBE_READ_REG(hw, reta_reg);
4818                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4819                         if (mask & (0x1 << j))
4820                                 reta_conf[idx].reta[shift + j] =
4821                                         ((reta >> (CHAR_BIT * j)) &
4822                                                 IXGBE_8_BIT_MASK);
4823                 }
4824         }
4825
4826         return 0;
4827 }
4828
4829 static int
4830 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4831                                 uint32_t index, uint32_t pool)
4832 {
4833         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4834         uint32_t enable_addr = 1;
4835
4836         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4837                              pool, enable_addr);
4838 }
4839
4840 static void
4841 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4842 {
4843         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4844
4845         ixgbe_clear_rar(hw, index);
4846 }
4847
4848 static int
4849 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4850 {
4851         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4852
4853         ixgbe_remove_rar(dev, 0);
4854         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4855
4856         return 0;
4857 }
4858
4859 static bool
4860 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4861 {
4862         if (strcmp(dev->device->driver->name, drv->driver.name))
4863                 return false;
4864
4865         return true;
4866 }
4867
4868 bool
4869 is_ixgbe_supported(struct rte_eth_dev *dev)
4870 {
4871         return is_device_supported(dev, &rte_ixgbe_pmd);
4872 }
4873
4874 static int
4875 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4876 {
4877         uint32_t hlreg0;
4878         uint32_t maxfrs;
4879         struct ixgbe_hw *hw;
4880         struct rte_eth_dev_info dev_info;
4881         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4882         struct rte_eth_dev_data *dev_data = dev->data;
4883
4884         ixgbe_dev_info_get(dev, &dev_info);
4885
4886         /* check that mtu is within the allowed range */
4887         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4888                 return -EINVAL;
4889
4890         /* If device is started, refuse mtu that requires the support of
4891          * scattered packets when this feature has not been enabled before.
4892          */
4893         if (dev_data->dev_started && !dev_data->scattered_rx &&
4894             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4895              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4896                 PMD_INIT_LOG(ERR, "Stop port first.");
4897                 return -EINVAL;
4898         }
4899
4900         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4901         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4902
4903         /* switch to jumbo mode if needed */
4904         if (frame_size > ETHER_MAX_LEN) {
4905                 dev->data->dev_conf.rxmode.offloads |=
4906                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4907                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4908         } else {
4909                 dev->data->dev_conf.rxmode.offloads &=
4910                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4911                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4912         }
4913         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4914
4915         /* update max frame size */
4916         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4917
4918         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4919         maxfrs &= 0x0000FFFF;
4920         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4921         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4922
4923         return 0;
4924 }
4925
4926 /*
4927  * Virtual Function operations
4928  */
4929 static void
4930 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4931 {
4932         struct ixgbe_interrupt *intr =
4933                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4934         struct ixgbe_hw *hw =
4935                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4936
4937         PMD_INIT_FUNC_TRACE();
4938
4939         /* Clear interrupt mask to stop from interrupts being generated */
4940         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4941
4942         IXGBE_WRITE_FLUSH(hw);
4943
4944         /* Clear mask value. */
4945         intr->mask = 0;
4946 }
4947
4948 static void
4949 ixgbevf_intr_enable(struct rte_eth_dev *dev)
4950 {
4951         struct ixgbe_interrupt *intr =
4952                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4953         struct ixgbe_hw *hw =
4954                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955
4956         PMD_INIT_FUNC_TRACE();
4957
4958         /* VF enable interrupt autoclean */
4959         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4960         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4961         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4962
4963         IXGBE_WRITE_FLUSH(hw);
4964
4965         /* Save IXGBE_VTEIMS value to mask. */
4966         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
4967 }
4968
4969 static int
4970 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4971 {
4972         struct rte_eth_conf *conf = &dev->data->dev_conf;
4973         struct ixgbe_adapter *adapter =
4974                         (struct ixgbe_adapter *)dev->data->dev_private;
4975         struct rte_eth_dev_info dev_info;
4976         uint64_t rx_offloads;
4977         uint64_t tx_offloads;
4978
4979         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4980                      dev->data->port_id);
4981
4982         ixgbevf_dev_info_get(dev, &dev_info);
4983         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4984         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4985                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4986                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4987                             rx_offloads, dev_info.rx_offload_capa);
4988                 return -ENOTSUP;
4989         }
4990         tx_offloads = dev->data->dev_conf.txmode.offloads;
4991         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4992                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4993                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4994                             tx_offloads, dev_info.tx_offload_capa);
4995                 return -ENOTSUP;
4996         }
4997
4998         /*
4999          * VF has no ability to enable/disable HW CRC
5000          * Keep the persistent behavior the same as Host PF
5001          */
5002 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5003         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
5004                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5005                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
5006         }
5007 #else
5008         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
5009                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5010                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
5011         }
5012 #endif
5013
5014         /*
5015          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5016          * allocation or vector Rx preconditions we will reset it.
5017          */
5018         adapter->rx_bulk_alloc_allowed = true;
5019         adapter->rx_vec_allowed = true;
5020
5021         return 0;
5022 }
5023
5024 static int
5025 ixgbevf_dev_start(struct rte_eth_dev *dev)
5026 {
5027         struct ixgbe_hw *hw =
5028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5029         uint32_t intr_vector = 0;
5030         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5031         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5032
5033         int err, mask = 0;
5034
5035         PMD_INIT_FUNC_TRACE();
5036
5037         err = hw->mac.ops.reset_hw(hw);
5038         if (err) {
5039                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5040                 return err;
5041         }
5042         hw->mac.get_link_status = true;
5043
5044         /* negotiate mailbox API version to use with the PF. */
5045         ixgbevf_negotiate_api(hw);
5046
5047         ixgbevf_dev_tx_init(dev);
5048
5049         /* This can fail when allocating mbufs for descriptor rings */
5050         err = ixgbevf_dev_rx_init(dev);
5051         if (err) {
5052                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5053                 ixgbe_dev_clear_queues(dev);
5054                 return err;
5055         }
5056
5057         /* Set vfta */
5058         ixgbevf_set_vfta_all(dev, 1);
5059
5060         /* Set HW strip */
5061         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5062                 ETH_VLAN_EXTEND_MASK;
5063         err = ixgbevf_vlan_offload_set(dev, mask);
5064         if (err) {
5065                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5066                 ixgbe_dev_clear_queues(dev);
5067                 return err;
5068         }
5069
5070         ixgbevf_dev_rxtx_start(dev);
5071
5072         ixgbevf_dev_link_update(dev, 0);
5073
5074         /* check and configure queue intr-vector mapping */
5075         if (rte_intr_cap_multiple(intr_handle) &&
5076             dev->data->dev_conf.intr_conf.rxq) {
5077                 /* According to datasheet, only vector 0/1/2 can be used,
5078                  * now only one vector is used for Rx queue
5079                  */
5080                 intr_vector = 1;
5081                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5082                         return -1;
5083         }
5084
5085         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5086                 intr_handle->intr_vec =
5087                         rte_zmalloc("intr_vec",
5088                                     dev->data->nb_rx_queues * sizeof(int), 0);
5089                 if (intr_handle->intr_vec == NULL) {
5090                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5091                                      " intr_vec", dev->data->nb_rx_queues);
5092                         return -ENOMEM;
5093                 }
5094         }
5095         ixgbevf_configure_msix(dev);
5096
5097         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5098          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5099          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5100          * is not cleared, it will fail when following rte_intr_enable( ) tries
5101          * to map Rx queue interrupt to other VFIO vectors.
5102          * So clear uio/vfio intr/evevnfd first to avoid failure.
5103          */
5104         rte_intr_disable(intr_handle);
5105
5106         rte_intr_enable(intr_handle);
5107
5108         /* Re-enable interrupt for VF */
5109         ixgbevf_intr_enable(dev);
5110
5111         return 0;
5112 }
5113
5114 static void
5115 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5116 {
5117         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5118         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5119         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5120
5121         PMD_INIT_FUNC_TRACE();
5122
5123         ixgbevf_intr_disable(dev);
5124
5125         hw->adapter_stopped = 1;
5126         ixgbe_stop_adapter(hw);
5127
5128         /*
5129           * Clear what we set, but we still keep shadow_vfta to
5130           * restore after device starts
5131           */
5132         ixgbevf_set_vfta_all(dev, 0);
5133
5134         /* Clear stored conf */
5135         dev->data->scattered_rx = 0;
5136
5137         ixgbe_dev_clear_queues(dev);
5138
5139         /* Clean datapath event and queue/vec mapping */
5140         rte_intr_efd_disable(intr_handle);
5141         if (intr_handle->intr_vec != NULL) {
5142                 rte_free(intr_handle->intr_vec);
5143                 intr_handle->intr_vec = NULL;
5144         }
5145 }
5146
5147 static void
5148 ixgbevf_dev_close(struct rte_eth_dev *dev)
5149 {
5150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5151
5152         PMD_INIT_FUNC_TRACE();
5153
5154         ixgbe_reset_hw(hw);
5155
5156         ixgbevf_dev_stop(dev);
5157
5158         ixgbe_dev_free_queues(dev);
5159
5160         /**
5161          * Remove the VF MAC address ro ensure
5162          * that the VF traffic goes to the PF
5163          * after stop, close and detach of the VF
5164          **/
5165         ixgbevf_remove_mac_addr(dev, 0);
5166 }
5167
5168 /*
5169  * Reset VF device
5170  */
5171 static int
5172 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5173 {
5174         int ret;
5175
5176         ret = eth_ixgbevf_dev_uninit(dev);
5177         if (ret)
5178                 return ret;
5179
5180         ret = eth_ixgbevf_dev_init(dev);
5181
5182         return ret;
5183 }
5184
5185 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5186 {
5187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5188         struct ixgbe_vfta *shadow_vfta =
5189                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5190         int i = 0, j = 0, vfta = 0, mask = 1;
5191
5192         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5193                 vfta = shadow_vfta->vfta[i];
5194                 if (vfta) {
5195                         mask = 1;
5196                         for (j = 0; j < 32; j++) {
5197                                 if (vfta & mask)
5198                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5199                                                        on, false);
5200                                 mask <<= 1;
5201                         }
5202                 }
5203         }
5204
5205 }
5206
5207 static int
5208 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5209 {
5210         struct ixgbe_hw *hw =
5211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5212         struct ixgbe_vfta *shadow_vfta =
5213                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5214         uint32_t vid_idx = 0;
5215         uint32_t vid_bit = 0;
5216         int ret = 0;
5217
5218         PMD_INIT_FUNC_TRACE();
5219
5220         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5221         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5222         if (ret) {
5223                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5224                 return ret;
5225         }
5226         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5227         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5228
5229         /* Save what we set and retore it after device reset */
5230         if (on)
5231                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5232         else
5233                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5234
5235         return 0;
5236 }
5237
5238 static void
5239 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5240 {
5241         struct ixgbe_hw *hw =
5242                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5243         uint32_t ctrl;
5244
5245         PMD_INIT_FUNC_TRACE();
5246
5247         if (queue >= hw->mac.max_rx_queues)
5248                 return;
5249
5250         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5251         if (on)
5252                 ctrl |= IXGBE_RXDCTL_VME;
5253         else
5254                 ctrl &= ~IXGBE_RXDCTL_VME;
5255         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5256
5257         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5258 }
5259
5260 static int
5261 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5262 {
5263         struct ixgbe_rx_queue *rxq;
5264         uint16_t i;
5265         int on = 0;
5266
5267         /* VF function only support hw strip feature, others are not support */
5268         if (mask & ETH_VLAN_STRIP_MASK) {
5269                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5270                         rxq = dev->data->rx_queues[i];
5271                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5272                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5273                 }
5274         }
5275
5276         return 0;
5277 }
5278
5279 int
5280 ixgbe_vt_check(struct ixgbe_hw *hw)
5281 {
5282         uint32_t reg_val;
5283
5284         /* if Virtualization Technology is enabled */
5285         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5286         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5287                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5288                 return -1;
5289         }
5290
5291         return 0;
5292 }
5293
5294 static uint32_t
5295 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5296 {
5297         uint32_t vector = 0;
5298
5299         switch (hw->mac.mc_filter_type) {
5300         case 0:   /* use bits [47:36] of the address */
5301                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5302                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5303                 break;
5304         case 1:   /* use bits [46:35] of the address */
5305                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5306                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5307                 break;
5308         case 2:   /* use bits [45:34] of the address */
5309                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5310                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5311                 break;
5312         case 3:   /* use bits [43:32] of the address */
5313                 vector = ((uc_addr->addr_bytes[4]) |
5314                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5315                 break;
5316         default:  /* Invalid mc_filter_type */
5317                 break;
5318         }
5319
5320         /* vector can only be 12-bits or boundary will be exceeded */
5321         vector &= 0xFFF;
5322         return vector;
5323 }
5324
5325 static int
5326 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5327                         uint8_t on)
5328 {
5329         uint32_t vector;
5330         uint32_t uta_idx;
5331         uint32_t reg_val;
5332         uint32_t uta_shift;
5333         uint32_t rc;
5334         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5335         const uint32_t ixgbe_uta_bit_shift = 5;
5336         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5337         const uint32_t bit1 = 0x1;
5338
5339         struct ixgbe_hw *hw =
5340                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5341         struct ixgbe_uta_info *uta_info =
5342                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5343
5344         /* The UTA table only exists on 82599 hardware and newer */
5345         if (hw->mac.type < ixgbe_mac_82599EB)
5346                 return -ENOTSUP;
5347
5348         vector = ixgbe_uta_vector(hw, mac_addr);
5349         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5350         uta_shift = vector & ixgbe_uta_bit_mask;
5351
5352         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5353         if (rc == on)
5354                 return 0;
5355
5356         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5357         if (on) {
5358                 uta_info->uta_in_use++;
5359                 reg_val |= (bit1 << uta_shift);
5360                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5361         } else {
5362                 uta_info->uta_in_use--;
5363                 reg_val &= ~(bit1 << uta_shift);
5364                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5365         }
5366
5367         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5368
5369         if (uta_info->uta_in_use > 0)
5370                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5371                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5372         else
5373                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5374
5375         return 0;
5376 }
5377
5378 static int
5379 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5380 {
5381         int i;
5382         struct ixgbe_hw *hw =
5383                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5384         struct ixgbe_uta_info *uta_info =
5385                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5386
5387         /* The UTA table only exists on 82599 hardware and newer */
5388         if (hw->mac.type < ixgbe_mac_82599EB)
5389                 return -ENOTSUP;
5390
5391         if (on) {
5392                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5393                         uta_info->uta_shadow[i] = ~0;
5394                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5395                 }
5396         } else {
5397                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5398                         uta_info->uta_shadow[i] = 0;
5399                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5400                 }
5401         }
5402         return 0;
5403
5404 }
5405
5406 uint32_t
5407 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5408 {
5409         uint32_t new_val = orig_val;
5410
5411         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5412                 new_val |= IXGBE_VMOLR_AUPE;
5413         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5414                 new_val |= IXGBE_VMOLR_ROMPE;
5415         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5416                 new_val |= IXGBE_VMOLR_ROPE;
5417         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5418                 new_val |= IXGBE_VMOLR_BAM;
5419         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5420                 new_val |= IXGBE_VMOLR_MPE;
5421
5422         return new_val;
5423 }
5424
5425 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5426 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5427 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5428 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5429 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5430         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5431         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5432
5433 static int
5434 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5435                       struct rte_eth_mirror_conf *mirror_conf,
5436                       uint8_t rule_id, uint8_t on)
5437 {
5438         uint32_t mr_ctl, vlvf;
5439         uint32_t mp_lsb = 0;
5440         uint32_t mv_msb = 0;
5441         uint32_t mv_lsb = 0;
5442         uint32_t mp_msb = 0;
5443         uint8_t i = 0;
5444         int reg_index = 0;
5445         uint64_t vlan_mask = 0;
5446
5447         const uint8_t pool_mask_offset = 32;
5448         const uint8_t vlan_mask_offset = 32;
5449         const uint8_t dst_pool_offset = 8;
5450         const uint8_t rule_mr_offset  = 4;
5451         const uint8_t mirror_rule_mask = 0x0F;
5452
5453         struct ixgbe_mirror_info *mr_info =
5454                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5455         struct ixgbe_hw *hw =
5456                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5457         uint8_t mirror_type = 0;
5458
5459         if (ixgbe_vt_check(hw) < 0)
5460                 return -ENOTSUP;
5461
5462         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5463                 return -EINVAL;
5464
5465         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5466                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5467                             mirror_conf->rule_type);
5468                 return -EINVAL;
5469         }
5470
5471         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5472                 mirror_type |= IXGBE_MRCTL_VLME;
5473                 /* Check if vlan id is valid and find conresponding VLAN ID
5474                  * index in VLVF
5475                  */
5476                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5477                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5478                                 /* search vlan id related pool vlan filter
5479                                  * index
5480                                  */
5481                                 reg_index = ixgbe_find_vlvf_slot(
5482                                                 hw,
5483                                                 mirror_conf->vlan.vlan_id[i],
5484                                                 false);
5485                                 if (reg_index < 0)
5486                                         return -EINVAL;
5487                                 vlvf = IXGBE_READ_REG(hw,
5488                                                       IXGBE_VLVF(reg_index));
5489                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5490                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5491                                       mirror_conf->vlan.vlan_id[i]))
5492                                         vlan_mask |= (1ULL << reg_index);
5493                                 else
5494                                         return -EINVAL;
5495                         }
5496                 }
5497
5498                 if (on) {
5499                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5500                         mv_msb = vlan_mask >> vlan_mask_offset;
5501
5502                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5503                                                 mirror_conf->vlan.vlan_mask;
5504                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5505                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5506                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5507                                                 mirror_conf->vlan.vlan_id[i];
5508                         }
5509                 } else {
5510                         mv_lsb = 0;
5511                         mv_msb = 0;
5512                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5513                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5514                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5515                 }
5516         }
5517
5518         /**
5519          * if enable pool mirror, write related pool mask register,if disable
5520          * pool mirror, clear PFMRVM register
5521          */
5522         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5523                 mirror_type |= IXGBE_MRCTL_VPME;
5524                 if (on) {
5525                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5526                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5527                         mr_info->mr_conf[rule_id].pool_mask =
5528                                         mirror_conf->pool_mask;
5529
5530                 } else {
5531                         mp_lsb = 0;
5532                         mp_msb = 0;
5533                         mr_info->mr_conf[rule_id].pool_mask = 0;
5534                 }
5535         }
5536         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5537                 mirror_type |= IXGBE_MRCTL_UPME;
5538         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5539                 mirror_type |= IXGBE_MRCTL_DPME;
5540
5541         /* read  mirror control register and recalculate it */
5542         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5543
5544         if (on) {
5545                 mr_ctl |= mirror_type;
5546                 mr_ctl &= mirror_rule_mask;
5547                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5548         } else {
5549                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5550         }
5551
5552         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5553         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5554
5555         /* write mirrror control  register */
5556         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5557
5558         /* write pool mirrror control  register */
5559         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5560                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5561                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5562                                 mp_msb);
5563         }
5564         /* write VLAN mirrror control  register */
5565         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5566                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5567                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5568                                 mv_msb);
5569         }
5570
5571         return 0;
5572 }
5573
5574 static int
5575 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5576 {
5577         int mr_ctl = 0;
5578         uint32_t lsb_val = 0;
5579         uint32_t msb_val = 0;
5580         const uint8_t rule_mr_offset = 4;
5581
5582         struct ixgbe_hw *hw =
5583                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5584         struct ixgbe_mirror_info *mr_info =
5585                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5586
5587         if (ixgbe_vt_check(hw) < 0)
5588                 return -ENOTSUP;
5589
5590         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5591                 return -EINVAL;
5592
5593         memset(&mr_info->mr_conf[rule_id], 0,
5594                sizeof(struct rte_eth_mirror_conf));
5595
5596         /* clear PFVMCTL register */
5597         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5598
5599         /* clear pool mask register */
5600         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5601         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5602
5603         /* clear vlan mask register */
5604         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5605         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5606
5607         return 0;
5608 }
5609
5610 static int
5611 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5612 {
5613         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5614         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5615         struct ixgbe_interrupt *intr =
5616                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5617         struct ixgbe_hw *hw =
5618                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5619         uint32_t vec = IXGBE_MISC_VEC_ID;
5620
5621         if (rte_intr_allow_others(intr_handle))
5622                 vec = IXGBE_RX_VEC_START;
5623         intr->mask |= (1 << vec);
5624         RTE_SET_USED(queue_id);
5625         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5626
5627         rte_intr_enable(intr_handle);
5628
5629         return 0;
5630 }
5631
5632 static int
5633 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5634 {
5635         struct ixgbe_interrupt *intr =
5636                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5637         struct ixgbe_hw *hw =
5638                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5639         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5640         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5641         uint32_t vec = IXGBE_MISC_VEC_ID;
5642
5643         if (rte_intr_allow_others(intr_handle))
5644                 vec = IXGBE_RX_VEC_START;
5645         intr->mask &= ~(1 << vec);
5646         RTE_SET_USED(queue_id);
5647         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5648
5649         return 0;
5650 }
5651
5652 static int
5653 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5654 {
5655         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5656         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5657         uint32_t mask;
5658         struct ixgbe_hw *hw =
5659                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5660         struct ixgbe_interrupt *intr =
5661                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5662
5663         if (queue_id < 16) {
5664                 ixgbe_disable_intr(hw);
5665                 intr->mask |= (1 << queue_id);
5666                 ixgbe_enable_intr(dev);
5667         } else if (queue_id < 32) {
5668                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5669                 mask &= (1 << queue_id);
5670                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5671         } else if (queue_id < 64) {
5672                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5673                 mask &= (1 << (queue_id - 32));
5674                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5675         }
5676         rte_intr_enable(intr_handle);
5677
5678         return 0;
5679 }
5680
5681 static int
5682 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5683 {
5684         uint32_t mask;
5685         struct ixgbe_hw *hw =
5686                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5687         struct ixgbe_interrupt *intr =
5688                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5689
5690         if (queue_id < 16) {
5691                 ixgbe_disable_intr(hw);
5692                 intr->mask &= ~(1 << queue_id);
5693                 ixgbe_enable_intr(dev);
5694         } else if (queue_id < 32) {
5695                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5696                 mask &= ~(1 << queue_id);
5697                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5698         } else if (queue_id < 64) {
5699                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5700                 mask &= ~(1 << (queue_id - 32));
5701                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5702         }
5703
5704         return 0;
5705 }
5706
5707 static void
5708 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5709                      uint8_t queue, uint8_t msix_vector)
5710 {
5711         uint32_t tmp, idx;
5712
5713         if (direction == -1) {
5714                 /* other causes */
5715                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5716                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5717                 tmp &= ~0xFF;
5718                 tmp |= msix_vector;
5719                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5720         } else {
5721                 /* rx or tx cause */
5722                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5723                 idx = ((16 * (queue & 1)) + (8 * direction));
5724                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5725                 tmp &= ~(0xFF << idx);
5726                 tmp |= (msix_vector << idx);
5727                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5728         }
5729 }
5730
5731 /**
5732  * set the IVAR registers, mapping interrupt causes to vectors
5733  * @param hw
5734  *  pointer to ixgbe_hw struct
5735  * @direction
5736  *  0 for Rx, 1 for Tx, -1 for other causes
5737  * @queue
5738  *  queue to map the corresponding interrupt to
5739  * @msix_vector
5740  *  the vector to map to the corresponding queue
5741  */
5742 static void
5743 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5744                    uint8_t queue, uint8_t msix_vector)
5745 {
5746         uint32_t tmp, idx;
5747
5748         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5749         if (hw->mac.type == ixgbe_mac_82598EB) {
5750                 if (direction == -1)
5751                         direction = 0;
5752                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5753                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5754                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5755                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5756                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5757         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5758                         (hw->mac.type == ixgbe_mac_X540) ||
5759                         (hw->mac.type == ixgbe_mac_X550)) {
5760                 if (direction == -1) {
5761                         /* other causes */
5762                         idx = ((queue & 1) * 8);
5763                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5764                         tmp &= ~(0xFF << idx);
5765                         tmp |= (msix_vector << idx);
5766                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5767                 } else {
5768                         /* rx or tx causes */
5769                         idx = ((16 * (queue & 1)) + (8 * direction));
5770                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5771                         tmp &= ~(0xFF << idx);
5772                         tmp |= (msix_vector << idx);
5773                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5774                 }
5775         }
5776 }
5777
5778 static void
5779 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5780 {
5781         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5782         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5783         struct ixgbe_hw *hw =
5784                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5785         uint32_t q_idx;
5786         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5787         uint32_t base = IXGBE_MISC_VEC_ID;
5788
5789         /* Configure VF other cause ivar */
5790         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5791
5792         /* won't configure msix register if no mapping is done
5793          * between intr vector and event fd.
5794          */
5795         if (!rte_intr_dp_is_en(intr_handle))
5796                 return;
5797
5798         if (rte_intr_allow_others(intr_handle)) {
5799                 base = IXGBE_RX_VEC_START;
5800                 vector_idx = IXGBE_RX_VEC_START;
5801         }
5802
5803         /* Configure all RX queues of VF */
5804         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5805                 /* Force all queue use vector 0,
5806                  * as IXGBE_VF_MAXMSIVECOTR = 1
5807                  */
5808                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5809                 intr_handle->intr_vec[q_idx] = vector_idx;
5810                 if (vector_idx < base + intr_handle->nb_efd - 1)
5811                         vector_idx++;
5812         }
5813
5814         /* As RX queue setting above show, all queues use the vector 0.
5815          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5816          */
5817         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5818                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5819                         | IXGBE_EITR_CNT_WDIS);
5820 }
5821
5822 /**
5823  * Sets up the hardware to properly generate MSI-X interrupts
5824  * @hw
5825  *  board private structure
5826  */
5827 static void
5828 ixgbe_configure_msix(struct rte_eth_dev *dev)
5829 {
5830         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5831         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5832         struct ixgbe_hw *hw =
5833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5834         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5835         uint32_t vec = IXGBE_MISC_VEC_ID;
5836         uint32_t mask;
5837         uint32_t gpie;
5838
5839         /* won't configure msix register if no mapping is done
5840          * between intr vector and event fd
5841          */
5842         if (!rte_intr_dp_is_en(intr_handle))
5843                 return;
5844
5845         if (rte_intr_allow_others(intr_handle))
5846                 vec = base = IXGBE_RX_VEC_START;
5847
5848         /* setup GPIE for MSI-x mode */
5849         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5850         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5851                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5852         /* auto clearing and auto setting corresponding bits in EIMS
5853          * when MSI-X interrupt is triggered
5854          */
5855         if (hw->mac.type == ixgbe_mac_82598EB) {
5856                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5857         } else {
5858                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5859                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5860         }
5861         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5862
5863         /* Populate the IVAR table and set the ITR values to the
5864          * corresponding register.
5865          */
5866         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5867              queue_id++) {
5868                 /* by default, 1:1 mapping */
5869                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5870                 intr_handle->intr_vec[queue_id] = vec;
5871                 if (vec < base + intr_handle->nb_efd - 1)
5872                         vec++;
5873         }
5874
5875         switch (hw->mac.type) {
5876         case ixgbe_mac_82598EB:
5877                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5878                                    IXGBE_MISC_VEC_ID);
5879                 break;
5880         case ixgbe_mac_82599EB:
5881         case ixgbe_mac_X540:
5882         case ixgbe_mac_X550:
5883                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5884                 break;
5885         default:
5886                 break;
5887         }
5888         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5889                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5890                         | IXGBE_EITR_CNT_WDIS);
5891
5892         /* set up to autoclear timer, and the vectors */
5893         mask = IXGBE_EIMS_ENABLE_MASK;
5894         mask &= ~(IXGBE_EIMS_OTHER |
5895                   IXGBE_EIMS_MAILBOX |
5896                   IXGBE_EIMS_LSC);
5897
5898         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5899 }
5900
5901 int
5902 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5903                            uint16_t queue_idx, uint16_t tx_rate)
5904 {
5905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5906         struct rte_eth_rxmode *rxmode;
5907         uint32_t rf_dec, rf_int;
5908         uint32_t bcnrc_val;
5909         uint16_t link_speed = dev->data->dev_link.link_speed;
5910
5911         if (queue_idx >= hw->mac.max_tx_queues)
5912                 return -EINVAL;
5913
5914         if (tx_rate != 0) {
5915                 /* Calculate the rate factor values to set */
5916                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5917                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5918                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5919
5920                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5921                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5922                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5923                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5924         } else {
5925                 bcnrc_val = 0;
5926         }
5927
5928         rxmode = &dev->data->dev_conf.rxmode;
5929         /*
5930          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5931          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5932          * set as 0x4.
5933          */
5934         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5935             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5936                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5937                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5938         else
5939                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5940                         IXGBE_MMW_SIZE_DEFAULT);
5941
5942         /* Set RTTBCNRC of queue X */
5943         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5944         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5945         IXGBE_WRITE_FLUSH(hw);
5946
5947         return 0;
5948 }
5949
5950 static int
5951 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5952                      __attribute__((unused)) uint32_t index,
5953                      __attribute__((unused)) uint32_t pool)
5954 {
5955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5956         int diag;
5957
5958         /*
5959          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5960          * operation. Trap this case to avoid exhausting the [very limited]
5961          * set of PF resources used to store VF MAC addresses.
5962          */
5963         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5964                 return -1;
5965         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5966         if (diag != 0)
5967                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5968                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5969                             mac_addr->addr_bytes[0],
5970                             mac_addr->addr_bytes[1],
5971                             mac_addr->addr_bytes[2],
5972                             mac_addr->addr_bytes[3],
5973                             mac_addr->addr_bytes[4],
5974                             mac_addr->addr_bytes[5],
5975                             diag);
5976         return diag;
5977 }
5978
5979 static void
5980 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5981 {
5982         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5983         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5984         struct ether_addr *mac_addr;
5985         uint32_t i;
5986         int diag;
5987
5988         /*
5989          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5990          * not support the deletion of a given MAC address.
5991          * Instead, it imposes to delete all MAC addresses, then to add again
5992          * all MAC addresses with the exception of the one to be deleted.
5993          */
5994         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5995
5996         /*
5997          * Add again all MAC addresses, with the exception of the deleted one
5998          * and of the permanent MAC address.
5999          */
6000         for (i = 0, mac_addr = dev->data->mac_addrs;
6001              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6002                 /* Skip the deleted MAC address */
6003                 if (i == index)
6004                         continue;
6005                 /* Skip NULL MAC addresses */
6006                 if (is_zero_ether_addr(mac_addr))
6007                         continue;
6008                 /* Skip the permanent MAC address */
6009                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6010                         continue;
6011                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6012                 if (diag != 0)
6013                         PMD_DRV_LOG(ERR,
6014                                     "Adding again MAC address "
6015                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6016                                     "diag=%d",
6017                                     mac_addr->addr_bytes[0],
6018                                     mac_addr->addr_bytes[1],
6019                                     mac_addr->addr_bytes[2],
6020                                     mac_addr->addr_bytes[3],
6021                                     mac_addr->addr_bytes[4],
6022                                     mac_addr->addr_bytes[5],
6023                                     diag);
6024         }
6025 }
6026
6027 static int
6028 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6029 {
6030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6031
6032         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6033
6034         return 0;
6035 }
6036
6037 int
6038 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6039                         struct rte_eth_syn_filter *filter,
6040                         bool add)
6041 {
6042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6043         struct ixgbe_filter_info *filter_info =
6044                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6045         uint32_t syn_info;
6046         uint32_t synqf;
6047
6048         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6049                 return -EINVAL;
6050
6051         syn_info = filter_info->syn_info;
6052
6053         if (add) {
6054                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6055                         return -EINVAL;
6056                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6057                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6058
6059                 if (filter->hig_pri)
6060                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6061                 else
6062                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6063         } else {
6064                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6065                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6066                         return -ENOENT;
6067                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6068         }
6069
6070         filter_info->syn_info = synqf;
6071         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6072         IXGBE_WRITE_FLUSH(hw);
6073         return 0;
6074 }
6075
6076 static int
6077 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6078                         struct rte_eth_syn_filter *filter)
6079 {
6080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6081         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6082
6083         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6084                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6085                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6086                 return 0;
6087         }
6088         return -ENOENT;
6089 }
6090
6091 static int
6092 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6093                         enum rte_filter_op filter_op,
6094                         void *arg)
6095 {
6096         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6097         int ret;
6098
6099         MAC_TYPE_FILTER_SUP(hw->mac.type);
6100
6101         if (filter_op == RTE_ETH_FILTER_NOP)
6102                 return 0;
6103
6104         if (arg == NULL) {
6105                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6106                             filter_op);
6107                 return -EINVAL;
6108         }
6109
6110         switch (filter_op) {
6111         case RTE_ETH_FILTER_ADD:
6112                 ret = ixgbe_syn_filter_set(dev,
6113                                 (struct rte_eth_syn_filter *)arg,
6114                                 TRUE);
6115                 break;
6116         case RTE_ETH_FILTER_DELETE:
6117                 ret = ixgbe_syn_filter_set(dev,
6118                                 (struct rte_eth_syn_filter *)arg,
6119                                 FALSE);
6120                 break;
6121         case RTE_ETH_FILTER_GET:
6122                 ret = ixgbe_syn_filter_get(dev,
6123                                 (struct rte_eth_syn_filter *)arg);
6124                 break;
6125         default:
6126                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6127                 ret = -EINVAL;
6128                 break;
6129         }
6130
6131         return ret;
6132 }
6133
6134
6135 static inline enum ixgbe_5tuple_protocol
6136 convert_protocol_type(uint8_t protocol_value)
6137 {
6138         if (protocol_value == IPPROTO_TCP)
6139                 return IXGBE_FILTER_PROTOCOL_TCP;
6140         else if (protocol_value == IPPROTO_UDP)
6141                 return IXGBE_FILTER_PROTOCOL_UDP;
6142         else if (protocol_value == IPPROTO_SCTP)
6143                 return IXGBE_FILTER_PROTOCOL_SCTP;
6144         else
6145                 return IXGBE_FILTER_PROTOCOL_NONE;
6146 }
6147
6148 /* inject a 5-tuple filter to HW */
6149 static inline void
6150 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6151                            struct ixgbe_5tuple_filter *filter)
6152 {
6153         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6154         int i;
6155         uint32_t ftqf, sdpqf;
6156         uint32_t l34timir = 0;
6157         uint8_t mask = 0xff;
6158
6159         i = filter->index;
6160
6161         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6162                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6163         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6164
6165         ftqf = (uint32_t)(filter->filter_info.proto &
6166                 IXGBE_FTQF_PROTOCOL_MASK);
6167         ftqf |= (uint32_t)((filter->filter_info.priority &
6168                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6169         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6170                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6171         if (filter->filter_info.dst_ip_mask == 0)
6172                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6173         if (filter->filter_info.src_port_mask == 0)
6174                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6175         if (filter->filter_info.dst_port_mask == 0)
6176                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6177         if (filter->filter_info.proto_mask == 0)
6178                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6179         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6180         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6181         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6182
6183         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6184         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6185         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6186         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6187
6188         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6189         l34timir |= (uint32_t)(filter->queue <<
6190                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6191         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6192 }
6193
6194 /*
6195  * add a 5tuple filter
6196  *
6197  * @param
6198  * dev: Pointer to struct rte_eth_dev.
6199  * index: the index the filter allocates.
6200  * filter: ponter to the filter that will be added.
6201  * rx_queue: the queue id the filter assigned to.
6202  *
6203  * @return
6204  *    - On success, zero.
6205  *    - On failure, a negative value.
6206  */
6207 static int
6208 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6209                         struct ixgbe_5tuple_filter *filter)
6210 {
6211         struct ixgbe_filter_info *filter_info =
6212                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6213         int i, idx, shift;
6214
6215         /*
6216          * look for an unused 5tuple filter index,
6217          * and insert the filter to list.
6218          */
6219         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6220                 idx = i / (sizeof(uint32_t) * NBBY);
6221                 shift = i % (sizeof(uint32_t) * NBBY);
6222                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6223                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6224                         filter->index = i;
6225                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6226                                           filter,
6227                                           entries);
6228                         break;
6229                 }
6230         }
6231         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6232                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6233                 return -ENOSYS;
6234         }
6235
6236         ixgbe_inject_5tuple_filter(dev, filter);
6237
6238         return 0;
6239 }
6240
6241 /*
6242  * remove a 5tuple filter
6243  *
6244  * @param
6245  * dev: Pointer to struct rte_eth_dev.
6246  * filter: the pointer of the filter will be removed.
6247  */
6248 static void
6249 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6250                         struct ixgbe_5tuple_filter *filter)
6251 {
6252         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6253         struct ixgbe_filter_info *filter_info =
6254                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6255         uint16_t index = filter->index;
6256
6257         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6258                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6259         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6260         rte_free(filter);
6261
6262         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6263         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6264         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6265         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6266         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6267 }
6268
6269 static int
6270 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6271 {
6272         struct ixgbe_hw *hw;
6273         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6274         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6275
6276         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6277
6278         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6279                 return -EINVAL;
6280
6281         /* refuse mtu that requires the support of scattered packets when this
6282          * feature has not been enabled before.
6283          */
6284         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6285             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6286              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6287                 return -EINVAL;
6288
6289         /*
6290          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6291          * request of the version 2.0 of the mailbox API.
6292          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6293          * of the mailbox API.
6294          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6295          * prior to 3.11.33 which contains the following change:
6296          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6297          */
6298         ixgbevf_rlpml_set_vf(hw, max_frame);
6299
6300         /* update max frame size */
6301         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6302         return 0;
6303 }
6304
6305 static inline struct ixgbe_5tuple_filter *
6306 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6307                         struct ixgbe_5tuple_filter_info *key)
6308 {
6309         struct ixgbe_5tuple_filter *it;
6310
6311         TAILQ_FOREACH(it, filter_list, entries) {
6312                 if (memcmp(key, &it->filter_info,
6313                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6314                         return it;
6315                 }
6316         }
6317         return NULL;
6318 }
6319
6320 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6321 static inline int
6322 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6323                         struct ixgbe_5tuple_filter_info *filter_info)
6324 {
6325         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6326                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6327                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6328                 return -EINVAL;
6329
6330         switch (filter->dst_ip_mask) {
6331         case UINT32_MAX:
6332                 filter_info->dst_ip_mask = 0;
6333                 filter_info->dst_ip = filter->dst_ip;
6334                 break;
6335         case 0:
6336                 filter_info->dst_ip_mask = 1;
6337                 break;
6338         default:
6339                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6340                 return -EINVAL;
6341         }
6342
6343         switch (filter->src_ip_mask) {
6344         case UINT32_MAX:
6345                 filter_info->src_ip_mask = 0;
6346                 filter_info->src_ip = filter->src_ip;
6347                 break;
6348         case 0:
6349                 filter_info->src_ip_mask = 1;
6350                 break;
6351         default:
6352                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6353                 return -EINVAL;
6354         }
6355
6356         switch (filter->dst_port_mask) {
6357         case UINT16_MAX:
6358                 filter_info->dst_port_mask = 0;
6359                 filter_info->dst_port = filter->dst_port;
6360                 break;
6361         case 0:
6362                 filter_info->dst_port_mask = 1;
6363                 break;
6364         default:
6365                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6366                 return -EINVAL;
6367         }
6368
6369         switch (filter->src_port_mask) {
6370         case UINT16_MAX:
6371                 filter_info->src_port_mask = 0;
6372                 filter_info->src_port = filter->src_port;
6373                 break;
6374         case 0:
6375                 filter_info->src_port_mask = 1;
6376                 break;
6377         default:
6378                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6379                 return -EINVAL;
6380         }
6381
6382         switch (filter->proto_mask) {
6383         case UINT8_MAX:
6384                 filter_info->proto_mask = 0;
6385                 filter_info->proto =
6386                         convert_protocol_type(filter->proto);
6387                 break;
6388         case 0:
6389                 filter_info->proto_mask = 1;
6390                 break;
6391         default:
6392                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6393                 return -EINVAL;
6394         }
6395
6396         filter_info->priority = (uint8_t)filter->priority;
6397         return 0;
6398 }
6399
6400 /*
6401  * add or delete a ntuple filter
6402  *
6403  * @param
6404  * dev: Pointer to struct rte_eth_dev.
6405  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6406  * add: if true, add filter, if false, remove filter
6407  *
6408  * @return
6409  *    - On success, zero.
6410  *    - On failure, a negative value.
6411  */
6412 int
6413 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6414                         struct rte_eth_ntuple_filter *ntuple_filter,
6415                         bool add)
6416 {
6417         struct ixgbe_filter_info *filter_info =
6418                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6419         struct ixgbe_5tuple_filter_info filter_5tuple;
6420         struct ixgbe_5tuple_filter *filter;
6421         int ret;
6422
6423         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6424                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6425                 return -EINVAL;
6426         }
6427
6428         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6429         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6430         if (ret < 0)
6431                 return ret;
6432
6433         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6434                                          &filter_5tuple);
6435         if (filter != NULL && add) {
6436                 PMD_DRV_LOG(ERR, "filter exists.");
6437                 return -EEXIST;
6438         }
6439         if (filter == NULL && !add) {
6440                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6441                 return -ENOENT;
6442         }
6443
6444         if (add) {
6445                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6446                                 sizeof(struct ixgbe_5tuple_filter), 0);
6447                 if (filter == NULL)
6448                         return -ENOMEM;
6449                 rte_memcpy(&filter->filter_info,
6450                                  &filter_5tuple,
6451                                  sizeof(struct ixgbe_5tuple_filter_info));
6452                 filter->queue = ntuple_filter->queue;
6453                 ret = ixgbe_add_5tuple_filter(dev, filter);
6454                 if (ret < 0) {
6455                         rte_free(filter);
6456                         return ret;
6457                 }
6458         } else
6459                 ixgbe_remove_5tuple_filter(dev, filter);
6460
6461         return 0;
6462 }
6463
6464 /*
6465  * get a ntuple filter
6466  *
6467  * @param
6468  * dev: Pointer to struct rte_eth_dev.
6469  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6470  *
6471  * @return
6472  *    - On success, zero.
6473  *    - On failure, a negative value.
6474  */
6475 static int
6476 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6477                         struct rte_eth_ntuple_filter *ntuple_filter)
6478 {
6479         struct ixgbe_filter_info *filter_info =
6480                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6481         struct ixgbe_5tuple_filter_info filter_5tuple;
6482         struct ixgbe_5tuple_filter *filter;
6483         int ret;
6484
6485         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6486                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6487                 return -EINVAL;
6488         }
6489
6490         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6491         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6492         if (ret < 0)
6493                 return ret;
6494
6495         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6496                                          &filter_5tuple);
6497         if (filter == NULL) {
6498                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6499                 return -ENOENT;
6500         }
6501         ntuple_filter->queue = filter->queue;
6502         return 0;
6503 }
6504
6505 /*
6506  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6507  * @dev: pointer to rte_eth_dev structure
6508  * @filter_op:operation will be taken.
6509  * @arg: a pointer to specific structure corresponding to the filter_op
6510  *
6511  * @return
6512  *    - On success, zero.
6513  *    - On failure, a negative value.
6514  */
6515 static int
6516 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6517                                 enum rte_filter_op filter_op,
6518                                 void *arg)
6519 {
6520         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6521         int ret;
6522
6523         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6524
6525         if (filter_op == RTE_ETH_FILTER_NOP)
6526                 return 0;
6527
6528         if (arg == NULL) {
6529                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6530                             filter_op);
6531                 return -EINVAL;
6532         }
6533
6534         switch (filter_op) {
6535         case RTE_ETH_FILTER_ADD:
6536                 ret = ixgbe_add_del_ntuple_filter(dev,
6537                         (struct rte_eth_ntuple_filter *)arg,
6538                         TRUE);
6539                 break;
6540         case RTE_ETH_FILTER_DELETE:
6541                 ret = ixgbe_add_del_ntuple_filter(dev,
6542                         (struct rte_eth_ntuple_filter *)arg,
6543                         FALSE);
6544                 break;
6545         case RTE_ETH_FILTER_GET:
6546                 ret = ixgbe_get_ntuple_filter(dev,
6547                         (struct rte_eth_ntuple_filter *)arg);
6548                 break;
6549         default:
6550                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6551                 ret = -EINVAL;
6552                 break;
6553         }
6554         return ret;
6555 }
6556
6557 int
6558 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6559                         struct rte_eth_ethertype_filter *filter,
6560                         bool add)
6561 {
6562         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6563         struct ixgbe_filter_info *filter_info =
6564                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6565         uint32_t etqf = 0;
6566         uint32_t etqs = 0;
6567         int ret;
6568         struct ixgbe_ethertype_filter ethertype_filter;
6569
6570         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6571                 return -EINVAL;
6572
6573         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6574                 filter->ether_type == ETHER_TYPE_IPv6) {
6575                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6576                         " ethertype filter.", filter->ether_type);
6577                 return -EINVAL;
6578         }
6579
6580         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6581                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6582                 return -EINVAL;
6583         }
6584         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6585                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6586                 return -EINVAL;
6587         }
6588
6589         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6590         if (ret >= 0 && add) {
6591                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6592                             filter->ether_type);
6593                 return -EEXIST;
6594         }
6595         if (ret < 0 && !add) {
6596                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6597                             filter->ether_type);
6598                 return -ENOENT;
6599         }
6600
6601         if (add) {
6602                 etqf = IXGBE_ETQF_FILTER_EN;
6603                 etqf |= (uint32_t)filter->ether_type;
6604                 etqs |= (uint32_t)((filter->queue <<
6605                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6606                                     IXGBE_ETQS_RX_QUEUE);
6607                 etqs |= IXGBE_ETQS_QUEUE_EN;
6608
6609                 ethertype_filter.ethertype = filter->ether_type;
6610                 ethertype_filter.etqf = etqf;
6611                 ethertype_filter.etqs = etqs;
6612                 ethertype_filter.conf = FALSE;
6613                 ret = ixgbe_ethertype_filter_insert(filter_info,
6614                                                     &ethertype_filter);
6615                 if (ret < 0) {
6616                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6617                         return -ENOSPC;
6618                 }
6619         } else {
6620                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6621                 if (ret < 0)
6622                         return -ENOSYS;
6623         }
6624         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6625         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6626         IXGBE_WRITE_FLUSH(hw);
6627
6628         return 0;
6629 }
6630
6631 static int
6632 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6633                         struct rte_eth_ethertype_filter *filter)
6634 {
6635         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6636         struct ixgbe_filter_info *filter_info =
6637                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6638         uint32_t etqf, etqs;
6639         int ret;
6640
6641         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6642         if (ret < 0) {
6643                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6644                             filter->ether_type);
6645                 return -ENOENT;
6646         }
6647
6648         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6649         if (etqf & IXGBE_ETQF_FILTER_EN) {
6650                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6651                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6652                 filter->flags = 0;
6653                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6654                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6655                 return 0;
6656         }
6657         return -ENOENT;
6658 }
6659
6660 /*
6661  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6662  * @dev: pointer to rte_eth_dev structure
6663  * @filter_op:operation will be taken.
6664  * @arg: a pointer to specific structure corresponding to the filter_op
6665  */
6666 static int
6667 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6668                                 enum rte_filter_op filter_op,
6669                                 void *arg)
6670 {
6671         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6672         int ret;
6673
6674         MAC_TYPE_FILTER_SUP(hw->mac.type);
6675
6676         if (filter_op == RTE_ETH_FILTER_NOP)
6677                 return 0;
6678
6679         if (arg == NULL) {
6680                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6681                             filter_op);
6682                 return -EINVAL;
6683         }
6684
6685         switch (filter_op) {
6686         case RTE_ETH_FILTER_ADD:
6687                 ret = ixgbe_add_del_ethertype_filter(dev,
6688                         (struct rte_eth_ethertype_filter *)arg,
6689                         TRUE);
6690                 break;
6691         case RTE_ETH_FILTER_DELETE:
6692                 ret = ixgbe_add_del_ethertype_filter(dev,
6693                         (struct rte_eth_ethertype_filter *)arg,
6694                         FALSE);
6695                 break;
6696         case RTE_ETH_FILTER_GET:
6697                 ret = ixgbe_get_ethertype_filter(dev,
6698                         (struct rte_eth_ethertype_filter *)arg);
6699                 break;
6700         default:
6701                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6702                 ret = -EINVAL;
6703                 break;
6704         }
6705         return ret;
6706 }
6707
6708 static int
6709 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6710                      enum rte_filter_type filter_type,
6711                      enum rte_filter_op filter_op,
6712                      void *arg)
6713 {
6714         int ret = 0;
6715
6716         switch (filter_type) {
6717         case RTE_ETH_FILTER_NTUPLE:
6718                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6719                 break;
6720         case RTE_ETH_FILTER_ETHERTYPE:
6721                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6722                 break;
6723         case RTE_ETH_FILTER_SYN:
6724                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6725                 break;
6726         case RTE_ETH_FILTER_FDIR:
6727                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6728                 break;
6729         case RTE_ETH_FILTER_L2_TUNNEL:
6730                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6731                 break;
6732         case RTE_ETH_FILTER_GENERIC:
6733                 if (filter_op != RTE_ETH_FILTER_GET)
6734                         return -EINVAL;
6735                 *(const void **)arg = &ixgbe_flow_ops;
6736                 break;
6737         default:
6738                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6739                                                         filter_type);
6740                 ret = -EINVAL;
6741                 break;
6742         }
6743
6744         return ret;
6745 }
6746
6747 static u8 *
6748 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6749                         u8 **mc_addr_ptr, u32 *vmdq)
6750 {
6751         u8 *mc_addr;
6752
6753         *vmdq = 0;
6754         mc_addr = *mc_addr_ptr;
6755         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6756         return mc_addr;
6757 }
6758
6759 static int
6760 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6761                           struct ether_addr *mc_addr_set,
6762                           uint32_t nb_mc_addr)
6763 {
6764         struct ixgbe_hw *hw;
6765         u8 *mc_addr_list;
6766
6767         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6768         mc_addr_list = (u8 *)mc_addr_set;
6769         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6770                                          ixgbe_dev_addr_list_itr, TRUE);
6771 }
6772
6773 static uint64_t
6774 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6775 {
6776         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6777         uint64_t systime_cycles;
6778
6779         switch (hw->mac.type) {
6780         case ixgbe_mac_X550:
6781         case ixgbe_mac_X550EM_x:
6782         case ixgbe_mac_X550EM_a:
6783                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6784                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6785                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6786                                 * NSEC_PER_SEC;
6787                 break;
6788         default:
6789                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6790                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6791                                 << 32;
6792         }
6793
6794         return systime_cycles;
6795 }
6796
6797 static uint64_t
6798 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6799 {
6800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6801         uint64_t rx_tstamp_cycles;
6802
6803         switch (hw->mac.type) {
6804         case ixgbe_mac_X550:
6805         case ixgbe_mac_X550EM_x:
6806         case ixgbe_mac_X550EM_a:
6807                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6808                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6809                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6810                                 * NSEC_PER_SEC;
6811                 break;
6812         default:
6813                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6814                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6815                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6816                                 << 32;
6817         }
6818
6819         return rx_tstamp_cycles;
6820 }
6821
6822 static uint64_t
6823 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6824 {
6825         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6826         uint64_t tx_tstamp_cycles;
6827
6828         switch (hw->mac.type) {
6829         case ixgbe_mac_X550:
6830         case ixgbe_mac_X550EM_x:
6831         case ixgbe_mac_X550EM_a:
6832                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6833                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6834                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6835                                 * NSEC_PER_SEC;
6836                 break;
6837         default:
6838                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6839                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6840                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6841                                 << 32;
6842         }
6843
6844         return tx_tstamp_cycles;
6845 }
6846
6847 static void
6848 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6849 {
6850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6851         struct ixgbe_adapter *adapter =
6852                 (struct ixgbe_adapter *)dev->data->dev_private;
6853         struct rte_eth_link link;
6854         uint32_t incval = 0;
6855         uint32_t shift = 0;
6856
6857         /* Get current link speed. */
6858         ixgbe_dev_link_update(dev, 1);
6859         rte_eth_linkstatus_get(dev, &link);
6860
6861         switch (link.link_speed) {
6862         case ETH_SPEED_NUM_100M:
6863                 incval = IXGBE_INCVAL_100;
6864                 shift = IXGBE_INCVAL_SHIFT_100;
6865                 break;
6866         case ETH_SPEED_NUM_1G:
6867                 incval = IXGBE_INCVAL_1GB;
6868                 shift = IXGBE_INCVAL_SHIFT_1GB;
6869                 break;
6870         case ETH_SPEED_NUM_10G:
6871         default:
6872                 incval = IXGBE_INCVAL_10GB;
6873                 shift = IXGBE_INCVAL_SHIFT_10GB;
6874                 break;
6875         }
6876
6877         switch (hw->mac.type) {
6878         case ixgbe_mac_X550:
6879         case ixgbe_mac_X550EM_x:
6880         case ixgbe_mac_X550EM_a:
6881                 /* Independent of link speed. */
6882                 incval = 1;
6883                 /* Cycles read will be interpreted as ns. */
6884                 shift = 0;
6885                 /* Fall-through */
6886         case ixgbe_mac_X540:
6887                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6888                 break;
6889         case ixgbe_mac_82599EB:
6890                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6891                 shift -= IXGBE_INCVAL_SHIFT_82599;
6892                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6893                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6894                 break;
6895         default:
6896                 /* Not supported. */
6897                 return;
6898         }
6899
6900         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6901         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6902         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6903
6904         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6905         adapter->systime_tc.cc_shift = shift;
6906         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6907
6908         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6909         adapter->rx_tstamp_tc.cc_shift = shift;
6910         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6911
6912         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6913         adapter->tx_tstamp_tc.cc_shift = shift;
6914         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6915 }
6916
6917 static int
6918 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6919 {
6920         struct ixgbe_adapter *adapter =
6921                         (struct ixgbe_adapter *)dev->data->dev_private;
6922
6923         adapter->systime_tc.nsec += delta;
6924         adapter->rx_tstamp_tc.nsec += delta;
6925         adapter->tx_tstamp_tc.nsec += delta;
6926
6927         return 0;
6928 }
6929
6930 static int
6931 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6932 {
6933         uint64_t ns;
6934         struct ixgbe_adapter *adapter =
6935                         (struct ixgbe_adapter *)dev->data->dev_private;
6936
6937         ns = rte_timespec_to_ns(ts);
6938         /* Set the timecounters to a new value. */
6939         adapter->systime_tc.nsec = ns;
6940         adapter->rx_tstamp_tc.nsec = ns;
6941         adapter->tx_tstamp_tc.nsec = ns;
6942
6943         return 0;
6944 }
6945
6946 static int
6947 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6948 {
6949         uint64_t ns, systime_cycles;
6950         struct ixgbe_adapter *adapter =
6951                         (struct ixgbe_adapter *)dev->data->dev_private;
6952
6953         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6954         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6955         *ts = rte_ns_to_timespec(ns);
6956
6957         return 0;
6958 }
6959
6960 static int
6961 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6962 {
6963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6964         uint32_t tsync_ctl;
6965         uint32_t tsauxc;
6966
6967         /* Stop the timesync system time. */
6968         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6969         /* Reset the timesync system time value. */
6970         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6971         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6972
6973         /* Enable system time for platforms where it isn't on by default. */
6974         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6975         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6976         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6977
6978         ixgbe_start_timecounters(dev);
6979
6980         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6981         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6982                         (ETHER_TYPE_1588 |
6983                          IXGBE_ETQF_FILTER_EN |
6984                          IXGBE_ETQF_1588));
6985
6986         /* Enable timestamping of received PTP packets. */
6987         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6988         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6989         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6990
6991         /* Enable timestamping of transmitted PTP packets. */
6992         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6993         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6994         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6995
6996         IXGBE_WRITE_FLUSH(hw);
6997
6998         return 0;
6999 }
7000
7001 static int
7002 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7003 {
7004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7005         uint32_t tsync_ctl;
7006
7007         /* Disable timestamping of transmitted PTP packets. */
7008         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7009         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7010         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7011
7012         /* Disable timestamping of received PTP packets. */
7013         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7014         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7015         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7016
7017         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7018         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7019
7020         /* Stop incrementating the System Time registers. */
7021         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7022
7023         return 0;
7024 }
7025
7026 static int
7027 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7028                                  struct timespec *timestamp,
7029                                  uint32_t flags __rte_unused)
7030 {
7031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7032         struct ixgbe_adapter *adapter =
7033                 (struct ixgbe_adapter *)dev->data->dev_private;
7034         uint32_t tsync_rxctl;
7035         uint64_t rx_tstamp_cycles;
7036         uint64_t ns;
7037
7038         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7039         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7040                 return -EINVAL;
7041
7042         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7043         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7044         *timestamp = rte_ns_to_timespec(ns);
7045
7046         return  0;
7047 }
7048
7049 static int
7050 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7051                                  struct timespec *timestamp)
7052 {
7053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7054         struct ixgbe_adapter *adapter =
7055                 (struct ixgbe_adapter *)dev->data->dev_private;
7056         uint32_t tsync_txctl;
7057         uint64_t tx_tstamp_cycles;
7058         uint64_t ns;
7059
7060         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7061         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7062                 return -EINVAL;
7063
7064         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7065         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7066         *timestamp = rte_ns_to_timespec(ns);
7067
7068         return 0;
7069 }
7070
7071 static int
7072 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7073 {
7074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7075         int count = 0;
7076         int g_ind = 0;
7077         const struct reg_info *reg_group;
7078         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7079                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7080
7081         while ((reg_group = reg_set[g_ind++]))
7082                 count += ixgbe_regs_group_count(reg_group);
7083
7084         return count;
7085 }
7086
7087 static int
7088 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7089 {
7090         int count = 0;
7091         int g_ind = 0;
7092         const struct reg_info *reg_group;
7093
7094         while ((reg_group = ixgbevf_regs[g_ind++]))
7095                 count += ixgbe_regs_group_count(reg_group);
7096
7097         return count;
7098 }
7099
7100 static int
7101 ixgbe_get_regs(struct rte_eth_dev *dev,
7102               struct rte_dev_reg_info *regs)
7103 {
7104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7105         uint32_t *data = regs->data;
7106         int g_ind = 0;
7107         int count = 0;
7108         const struct reg_info *reg_group;
7109         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7110                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7111
7112         if (data == NULL) {
7113                 regs->length = ixgbe_get_reg_length(dev);
7114                 regs->width = sizeof(uint32_t);
7115                 return 0;
7116         }
7117
7118         /* Support only full register dump */
7119         if ((regs->length == 0) ||
7120             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7121                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7122                         hw->device_id;
7123                 while ((reg_group = reg_set[g_ind++]))
7124                         count += ixgbe_read_regs_group(dev, &data[count],
7125                                 reg_group);
7126                 return 0;
7127         }
7128
7129         return -ENOTSUP;
7130 }
7131
7132 static int
7133 ixgbevf_get_regs(struct rte_eth_dev *dev,
7134                 struct rte_dev_reg_info *regs)
7135 {
7136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7137         uint32_t *data = regs->data;
7138         int g_ind = 0;
7139         int count = 0;
7140         const struct reg_info *reg_group;
7141
7142         if (data == NULL) {
7143                 regs->length = ixgbevf_get_reg_length(dev);
7144                 regs->width = sizeof(uint32_t);
7145                 return 0;
7146         }
7147
7148         /* Support only full register dump */
7149         if ((regs->length == 0) ||
7150             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7151                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7152                         hw->device_id;
7153                 while ((reg_group = ixgbevf_regs[g_ind++]))
7154                         count += ixgbe_read_regs_group(dev, &data[count],
7155                                                       reg_group);
7156                 return 0;
7157         }
7158
7159         return -ENOTSUP;
7160 }
7161
7162 static int
7163 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7164 {
7165         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7166
7167         /* Return unit is byte count */
7168         return hw->eeprom.word_size * 2;
7169 }
7170
7171 static int
7172 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7173                 struct rte_dev_eeprom_info *in_eeprom)
7174 {
7175         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7176         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7177         uint16_t *data = in_eeprom->data;
7178         int first, length;
7179
7180         first = in_eeprom->offset >> 1;
7181         length = in_eeprom->length >> 1;
7182         if ((first > hw->eeprom.word_size) ||
7183             ((first + length) > hw->eeprom.word_size))
7184                 return -EINVAL;
7185
7186         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7187
7188         return eeprom->ops.read_buffer(hw, first, length, data);
7189 }
7190
7191 static int
7192 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7193                 struct rte_dev_eeprom_info *in_eeprom)
7194 {
7195         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7196         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7197         uint16_t *data = in_eeprom->data;
7198         int first, length;
7199
7200         first = in_eeprom->offset >> 1;
7201         length = in_eeprom->length >> 1;
7202         if ((first > hw->eeprom.word_size) ||
7203             ((first + length) > hw->eeprom.word_size))
7204                 return -EINVAL;
7205
7206         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7207
7208         return eeprom->ops.write_buffer(hw,  first, length, data);
7209 }
7210
7211 static int
7212 ixgbe_get_module_info(struct rte_eth_dev *dev,
7213                       struct rte_eth_dev_module_info *modinfo)
7214 {
7215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7216         uint32_t status;
7217         uint8_t sff8472_rev, addr_mode;
7218         bool page_swap = false;
7219
7220         /* Check whether we support SFF-8472 or not */
7221         status = hw->phy.ops.read_i2c_eeprom(hw,
7222                                              IXGBE_SFF_SFF_8472_COMP,
7223                                              &sff8472_rev);
7224         if (status != 0)
7225                 return -EIO;
7226
7227         /* addressing mode is not supported */
7228         status = hw->phy.ops.read_i2c_eeprom(hw,
7229                                              IXGBE_SFF_SFF_8472_SWAP,
7230                                              &addr_mode);
7231         if (status != 0)
7232                 return -EIO;
7233
7234         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7235                 PMD_DRV_LOG(ERR,
7236                             "Address change required to access page 0xA2, "
7237                             "but not supported. Please report the module "
7238                             "type to the driver maintainers.");
7239                 page_swap = true;
7240         }
7241
7242         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7243                 /* We have a SFP, but it does not support SFF-8472 */
7244                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7245                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7246         } else {
7247                 /* We have a SFP which supports a revision of SFF-8472. */
7248                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7249                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7250         }
7251
7252         return 0;
7253 }
7254
7255 static int
7256 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7257                         struct rte_dev_eeprom_info *info)
7258 {
7259         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7260         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7261         uint8_t databyte = 0xFF;
7262         uint8_t *data = info->data;
7263         uint32_t i = 0;
7264
7265         if (info->length == 0)
7266                 return -EINVAL;
7267
7268         for (i = info->offset; i < info->offset + info->length; i++) {
7269                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7270                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7271                 else
7272                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7273
7274                 if (status != 0)
7275                         return -EIO;
7276
7277                 data[i - info->offset] = databyte;
7278         }
7279
7280         return 0;
7281 }
7282
7283 uint16_t
7284 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7285         switch (mac_type) {
7286         case ixgbe_mac_X550:
7287         case ixgbe_mac_X550EM_x:
7288         case ixgbe_mac_X550EM_a:
7289                 return ETH_RSS_RETA_SIZE_512;
7290         case ixgbe_mac_X550_vf:
7291         case ixgbe_mac_X550EM_x_vf:
7292         case ixgbe_mac_X550EM_a_vf:
7293                 return ETH_RSS_RETA_SIZE_64;
7294         default:
7295                 return ETH_RSS_RETA_SIZE_128;
7296         }
7297 }
7298
7299 uint32_t
7300 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7301         switch (mac_type) {
7302         case ixgbe_mac_X550:
7303         case ixgbe_mac_X550EM_x:
7304         case ixgbe_mac_X550EM_a:
7305                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7306                         return IXGBE_RETA(reta_idx >> 2);
7307                 else
7308                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7309         case ixgbe_mac_X550_vf:
7310         case ixgbe_mac_X550EM_x_vf:
7311         case ixgbe_mac_X550EM_a_vf:
7312                 return IXGBE_VFRETA(reta_idx >> 2);
7313         default:
7314                 return IXGBE_RETA(reta_idx >> 2);
7315         }
7316 }
7317
7318 uint32_t
7319 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7320         switch (mac_type) {
7321         case ixgbe_mac_X550_vf:
7322         case ixgbe_mac_X550EM_x_vf:
7323         case ixgbe_mac_X550EM_a_vf:
7324                 return IXGBE_VFMRQC;
7325         default:
7326                 return IXGBE_MRQC;
7327         }
7328 }
7329
7330 uint32_t
7331 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7332         switch (mac_type) {
7333         case ixgbe_mac_X550_vf:
7334         case ixgbe_mac_X550EM_x_vf:
7335         case ixgbe_mac_X550EM_a_vf:
7336                 return IXGBE_VFRSSRK(i);
7337         default:
7338                 return IXGBE_RSSRK(i);
7339         }
7340 }
7341
7342 bool
7343 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7344         switch (mac_type) {
7345         case ixgbe_mac_82599_vf:
7346         case ixgbe_mac_X540_vf:
7347                 return 0;
7348         default:
7349                 return 1;
7350         }
7351 }
7352
7353 static int
7354 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7355                         struct rte_eth_dcb_info *dcb_info)
7356 {
7357         struct ixgbe_dcb_config *dcb_config =
7358                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7359         struct ixgbe_dcb_tc_config *tc;
7360         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7361         uint8_t nb_tcs;
7362         uint8_t i, j;
7363
7364         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7365                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7366         else
7367                 dcb_info->nb_tcs = 1;
7368
7369         tc_queue = &dcb_info->tc_queue;
7370         nb_tcs = dcb_info->nb_tcs;
7371
7372         if (dcb_config->vt_mode) { /* vt is enabled*/
7373                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7374                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7375                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7376                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7377                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7378                         for (j = 0; j < nb_tcs; j++) {
7379                                 tc_queue->tc_rxq[0][j].base = j;
7380                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7381                                 tc_queue->tc_txq[0][j].base = j;
7382                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7383                         }
7384                 } else {
7385                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7386                                 for (j = 0; j < nb_tcs; j++) {
7387                                         tc_queue->tc_rxq[i][j].base =
7388                                                 i * nb_tcs + j;
7389                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7390                                         tc_queue->tc_txq[i][j].base =
7391                                                 i * nb_tcs + j;
7392                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7393                                 }
7394                         }
7395                 }
7396         } else { /* vt is disabled*/
7397                 struct rte_eth_dcb_rx_conf *rx_conf =
7398                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7399                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7400                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7401                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7402                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7403                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7404                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7405                         }
7406                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7407                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7408                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7409                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7410                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7411                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7412                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7413                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7414                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7415                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7416                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7417                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7418                         }
7419                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7420                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7421                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7422                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7423                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7424                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7425                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7426                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7427                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7428                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7429                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7430                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7431                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7432                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7433                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7434                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7435                 }
7436         }
7437         for (i = 0; i < dcb_info->nb_tcs; i++) {
7438                 tc = &dcb_config->tc_config[i];
7439                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7440         }
7441         return 0;
7442 }
7443
7444 /* Update e-tag ether type */
7445 static int
7446 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7447                             uint16_t ether_type)
7448 {
7449         uint32_t etag_etype;
7450
7451         if (hw->mac.type != ixgbe_mac_X550 &&
7452             hw->mac.type != ixgbe_mac_X550EM_x &&
7453             hw->mac.type != ixgbe_mac_X550EM_a) {
7454                 return -ENOTSUP;
7455         }
7456
7457         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7458         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7459         etag_etype |= ether_type;
7460         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7461         IXGBE_WRITE_FLUSH(hw);
7462
7463         return 0;
7464 }
7465
7466 /* Config l2 tunnel ether type */
7467 static int
7468 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7469                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7470 {
7471         int ret = 0;
7472         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7473         struct ixgbe_l2_tn_info *l2_tn_info =
7474                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7475
7476         if (l2_tunnel == NULL)
7477                 return -EINVAL;
7478
7479         switch (l2_tunnel->l2_tunnel_type) {
7480         case RTE_L2_TUNNEL_TYPE_E_TAG:
7481                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7482                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7483                 break;
7484         default:
7485                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7486                 ret = -EINVAL;
7487                 break;
7488         }
7489
7490         return ret;
7491 }
7492
7493 /* Enable e-tag tunnel */
7494 static int
7495 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7496 {
7497         uint32_t etag_etype;
7498
7499         if (hw->mac.type != ixgbe_mac_X550 &&
7500             hw->mac.type != ixgbe_mac_X550EM_x &&
7501             hw->mac.type != ixgbe_mac_X550EM_a) {
7502                 return -ENOTSUP;
7503         }
7504
7505         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7506         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7507         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7508         IXGBE_WRITE_FLUSH(hw);
7509
7510         return 0;
7511 }
7512
7513 /* Enable l2 tunnel */
7514 static int
7515 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7516                            enum rte_eth_tunnel_type l2_tunnel_type)
7517 {
7518         int ret = 0;
7519         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7520         struct ixgbe_l2_tn_info *l2_tn_info =
7521                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7522
7523         switch (l2_tunnel_type) {
7524         case RTE_L2_TUNNEL_TYPE_E_TAG:
7525                 l2_tn_info->e_tag_en = TRUE;
7526                 ret = ixgbe_e_tag_enable(hw);
7527                 break;
7528         default:
7529                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7530                 ret = -EINVAL;
7531                 break;
7532         }
7533
7534         return ret;
7535 }
7536
7537 /* Disable e-tag tunnel */
7538 static int
7539 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7540 {
7541         uint32_t etag_etype;
7542
7543         if (hw->mac.type != ixgbe_mac_X550 &&
7544             hw->mac.type != ixgbe_mac_X550EM_x &&
7545             hw->mac.type != ixgbe_mac_X550EM_a) {
7546                 return -ENOTSUP;
7547         }
7548
7549         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7550         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7551         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7552         IXGBE_WRITE_FLUSH(hw);
7553
7554         return 0;
7555 }
7556
7557 /* Disable l2 tunnel */
7558 static int
7559 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7560                             enum rte_eth_tunnel_type l2_tunnel_type)
7561 {
7562         int ret = 0;
7563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7564         struct ixgbe_l2_tn_info *l2_tn_info =
7565                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7566
7567         switch (l2_tunnel_type) {
7568         case RTE_L2_TUNNEL_TYPE_E_TAG:
7569                 l2_tn_info->e_tag_en = FALSE;
7570                 ret = ixgbe_e_tag_disable(hw);
7571                 break;
7572         default:
7573                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7574                 ret = -EINVAL;
7575                 break;
7576         }
7577
7578         return ret;
7579 }
7580
7581 static int
7582 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7583                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7584 {
7585         int ret = 0;
7586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7587         uint32_t i, rar_entries;
7588         uint32_t rar_low, rar_high;
7589
7590         if (hw->mac.type != ixgbe_mac_X550 &&
7591             hw->mac.type != ixgbe_mac_X550EM_x &&
7592             hw->mac.type != ixgbe_mac_X550EM_a) {
7593                 return -ENOTSUP;
7594         }
7595
7596         rar_entries = ixgbe_get_num_rx_addrs(hw);
7597
7598         for (i = 1; i < rar_entries; i++) {
7599                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7600                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7601                 if ((rar_high & IXGBE_RAH_AV) &&
7602                     (rar_high & IXGBE_RAH_ADTYPE) &&
7603                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7604                      l2_tunnel->tunnel_id)) {
7605                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7606                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7607
7608                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7609
7610                         return ret;
7611                 }
7612         }
7613
7614         return ret;
7615 }
7616
7617 static int
7618 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7619                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7620 {
7621         int ret = 0;
7622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7623         uint32_t i, rar_entries;
7624         uint32_t rar_low, rar_high;
7625
7626         if (hw->mac.type != ixgbe_mac_X550 &&
7627             hw->mac.type != ixgbe_mac_X550EM_x &&
7628             hw->mac.type != ixgbe_mac_X550EM_a) {
7629                 return -ENOTSUP;
7630         }
7631
7632         /* One entry for one tunnel. Try to remove potential existing entry. */
7633         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7634
7635         rar_entries = ixgbe_get_num_rx_addrs(hw);
7636
7637         for (i = 1; i < rar_entries; i++) {
7638                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7639                 if (rar_high & IXGBE_RAH_AV) {
7640                         continue;
7641                 } else {
7642                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7643                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7644                         rar_low = l2_tunnel->tunnel_id;
7645
7646                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7647                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7648
7649                         return ret;
7650                 }
7651         }
7652
7653         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7654                      " Please remove a rule before adding a new one.");
7655         return -EINVAL;
7656 }
7657
7658 static inline struct ixgbe_l2_tn_filter *
7659 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7660                           struct ixgbe_l2_tn_key *key)
7661 {
7662         int ret;
7663
7664         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7665         if (ret < 0)
7666                 return NULL;
7667
7668         return l2_tn_info->hash_map[ret];
7669 }
7670
7671 static inline int
7672 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7673                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7674 {
7675         int ret;
7676
7677         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7678                                &l2_tn_filter->key);
7679
7680         if (ret < 0) {
7681                 PMD_DRV_LOG(ERR,
7682                             "Failed to insert L2 tunnel filter"
7683                             " to hash table %d!",
7684                             ret);
7685                 return ret;
7686         }
7687
7688         l2_tn_info->hash_map[ret] = l2_tn_filter;
7689
7690         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7691
7692         return 0;
7693 }
7694
7695 static inline int
7696 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7697                           struct ixgbe_l2_tn_key *key)
7698 {
7699         int ret;
7700         struct ixgbe_l2_tn_filter *l2_tn_filter;
7701
7702         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7703
7704         if (ret < 0) {
7705                 PMD_DRV_LOG(ERR,
7706                             "No such L2 tunnel filter to delete %d!",
7707                             ret);
7708                 return ret;
7709         }
7710
7711         l2_tn_filter = l2_tn_info->hash_map[ret];
7712         l2_tn_info->hash_map[ret] = NULL;
7713
7714         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7715         rte_free(l2_tn_filter);
7716
7717         return 0;
7718 }
7719
7720 /* Add l2 tunnel filter */
7721 int
7722 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7723                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7724                                bool restore)
7725 {
7726         int ret;
7727         struct ixgbe_l2_tn_info *l2_tn_info =
7728                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7729         struct ixgbe_l2_tn_key key;
7730         struct ixgbe_l2_tn_filter *node;
7731
7732         if (!restore) {
7733                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7734                 key.tn_id = l2_tunnel->tunnel_id;
7735
7736                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7737
7738                 if (node) {
7739                         PMD_DRV_LOG(ERR,
7740                                     "The L2 tunnel filter already exists!");
7741                         return -EINVAL;
7742                 }
7743
7744                 node = rte_zmalloc("ixgbe_l2_tn",
7745                                    sizeof(struct ixgbe_l2_tn_filter),
7746                                    0);
7747                 if (!node)
7748                         return -ENOMEM;
7749
7750                 rte_memcpy(&node->key,
7751                                  &key,
7752                                  sizeof(struct ixgbe_l2_tn_key));
7753                 node->pool = l2_tunnel->pool;
7754                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7755                 if (ret < 0) {
7756                         rte_free(node);
7757                         return ret;
7758                 }
7759         }
7760
7761         switch (l2_tunnel->l2_tunnel_type) {
7762         case RTE_L2_TUNNEL_TYPE_E_TAG:
7763                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7764                 break;
7765         default:
7766                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7767                 ret = -EINVAL;
7768                 break;
7769         }
7770
7771         if ((!restore) && (ret < 0))
7772                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7773
7774         return ret;
7775 }
7776
7777 /* Delete l2 tunnel filter */
7778 int
7779 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7780                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7781 {
7782         int ret;
7783         struct ixgbe_l2_tn_info *l2_tn_info =
7784                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7785         struct ixgbe_l2_tn_key key;
7786
7787         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7788         key.tn_id = l2_tunnel->tunnel_id;
7789         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7790         if (ret < 0)
7791                 return ret;
7792
7793         switch (l2_tunnel->l2_tunnel_type) {
7794         case RTE_L2_TUNNEL_TYPE_E_TAG:
7795                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7796                 break;
7797         default:
7798                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7799                 ret = -EINVAL;
7800                 break;
7801         }
7802
7803         return ret;
7804 }
7805
7806 /**
7807  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7808  * @dev: pointer to rte_eth_dev structure
7809  * @filter_op:operation will be taken.
7810  * @arg: a pointer to specific structure corresponding to the filter_op
7811  */
7812 static int
7813 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7814                                   enum rte_filter_op filter_op,
7815                                   void *arg)
7816 {
7817         int ret;
7818
7819         if (filter_op == RTE_ETH_FILTER_NOP)
7820                 return 0;
7821
7822         if (arg == NULL) {
7823                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7824                             filter_op);
7825                 return -EINVAL;
7826         }
7827
7828         switch (filter_op) {
7829         case RTE_ETH_FILTER_ADD:
7830                 ret = ixgbe_dev_l2_tunnel_filter_add
7831                         (dev,
7832                          (struct rte_eth_l2_tunnel_conf *)arg,
7833                          FALSE);
7834                 break;
7835         case RTE_ETH_FILTER_DELETE:
7836                 ret = ixgbe_dev_l2_tunnel_filter_del
7837                         (dev,
7838                          (struct rte_eth_l2_tunnel_conf *)arg);
7839                 break;
7840         default:
7841                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7842                 ret = -EINVAL;
7843                 break;
7844         }
7845         return ret;
7846 }
7847
7848 static int
7849 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7850 {
7851         int ret = 0;
7852         uint32_t ctrl;
7853         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7854
7855         if (hw->mac.type != ixgbe_mac_X550 &&
7856             hw->mac.type != ixgbe_mac_X550EM_x &&
7857             hw->mac.type != ixgbe_mac_X550EM_a) {
7858                 return -ENOTSUP;
7859         }
7860
7861         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7862         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7863         if (en)
7864                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7865         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7866
7867         return ret;
7868 }
7869
7870 /* Enable l2 tunnel forwarding */
7871 static int
7872 ixgbe_dev_l2_tunnel_forwarding_enable
7873         (struct rte_eth_dev *dev,
7874          enum rte_eth_tunnel_type l2_tunnel_type)
7875 {
7876         struct ixgbe_l2_tn_info *l2_tn_info =
7877                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7878         int ret = 0;
7879
7880         switch (l2_tunnel_type) {
7881         case RTE_L2_TUNNEL_TYPE_E_TAG:
7882                 l2_tn_info->e_tag_fwd_en = TRUE;
7883                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7884                 break;
7885         default:
7886                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7887                 ret = -EINVAL;
7888                 break;
7889         }
7890
7891         return ret;
7892 }
7893
7894 /* Disable l2 tunnel forwarding */
7895 static int
7896 ixgbe_dev_l2_tunnel_forwarding_disable
7897         (struct rte_eth_dev *dev,
7898          enum rte_eth_tunnel_type l2_tunnel_type)
7899 {
7900         struct ixgbe_l2_tn_info *l2_tn_info =
7901                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7902         int ret = 0;
7903
7904         switch (l2_tunnel_type) {
7905         case RTE_L2_TUNNEL_TYPE_E_TAG:
7906                 l2_tn_info->e_tag_fwd_en = FALSE;
7907                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7908                 break;
7909         default:
7910                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7911                 ret = -EINVAL;
7912                 break;
7913         }
7914
7915         return ret;
7916 }
7917
7918 static int
7919 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7920                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7921                              bool en)
7922 {
7923         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7924         int ret = 0;
7925         uint32_t vmtir, vmvir;
7926         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7927
7928         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7929                 PMD_DRV_LOG(ERR,
7930                             "VF id %u should be less than %u",
7931                             l2_tunnel->vf_id,
7932                             pci_dev->max_vfs);
7933                 return -EINVAL;
7934         }
7935
7936         if (hw->mac.type != ixgbe_mac_X550 &&
7937             hw->mac.type != ixgbe_mac_X550EM_x &&
7938             hw->mac.type != ixgbe_mac_X550EM_a) {
7939                 return -ENOTSUP;
7940         }
7941
7942         if (en)
7943                 vmtir = l2_tunnel->tunnel_id;
7944         else
7945                 vmtir = 0;
7946
7947         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7948
7949         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7950         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7951         if (en)
7952                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7953         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7954
7955         return ret;
7956 }
7957
7958 /* Enable l2 tunnel tag insertion */
7959 static int
7960 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7961                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7962 {
7963         int ret = 0;
7964
7965         switch (l2_tunnel->l2_tunnel_type) {
7966         case RTE_L2_TUNNEL_TYPE_E_TAG:
7967                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7968                 break;
7969         default:
7970                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7971                 ret = -EINVAL;
7972                 break;
7973         }
7974
7975         return ret;
7976 }
7977
7978 /* Disable l2 tunnel tag insertion */
7979 static int
7980 ixgbe_dev_l2_tunnel_insertion_disable
7981         (struct rte_eth_dev *dev,
7982          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7983 {
7984         int ret = 0;
7985
7986         switch (l2_tunnel->l2_tunnel_type) {
7987         case RTE_L2_TUNNEL_TYPE_E_TAG:
7988                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7989                 break;
7990         default:
7991                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7992                 ret = -EINVAL;
7993                 break;
7994         }
7995
7996         return ret;
7997 }
7998
7999 static int
8000 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8001                              bool en)
8002 {
8003         int ret = 0;
8004         uint32_t qde;
8005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8006
8007         if (hw->mac.type != ixgbe_mac_X550 &&
8008             hw->mac.type != ixgbe_mac_X550EM_x &&
8009             hw->mac.type != ixgbe_mac_X550EM_a) {
8010                 return -ENOTSUP;
8011         }
8012
8013         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8014         if (en)
8015                 qde |= IXGBE_QDE_STRIP_TAG;
8016         else
8017                 qde &= ~IXGBE_QDE_STRIP_TAG;
8018         qde &= ~IXGBE_QDE_READ;
8019         qde |= IXGBE_QDE_WRITE;
8020         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8021
8022         return ret;
8023 }
8024
8025 /* Enable l2 tunnel tag stripping */
8026 static int
8027 ixgbe_dev_l2_tunnel_stripping_enable
8028         (struct rte_eth_dev *dev,
8029          enum rte_eth_tunnel_type l2_tunnel_type)
8030 {
8031         int ret = 0;
8032
8033         switch (l2_tunnel_type) {
8034         case RTE_L2_TUNNEL_TYPE_E_TAG:
8035                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8036                 break;
8037         default:
8038                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8039                 ret = -EINVAL;
8040                 break;
8041         }
8042
8043         return ret;
8044 }
8045
8046 /* Disable l2 tunnel tag stripping */
8047 static int
8048 ixgbe_dev_l2_tunnel_stripping_disable
8049         (struct rte_eth_dev *dev,
8050          enum rte_eth_tunnel_type l2_tunnel_type)
8051 {
8052         int ret = 0;
8053
8054         switch (l2_tunnel_type) {
8055         case RTE_L2_TUNNEL_TYPE_E_TAG:
8056                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8057                 break;
8058         default:
8059                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8060                 ret = -EINVAL;
8061                 break;
8062         }
8063
8064         return ret;
8065 }
8066
8067 /* Enable/disable l2 tunnel offload functions */
8068 static int
8069 ixgbe_dev_l2_tunnel_offload_set
8070         (struct rte_eth_dev *dev,
8071          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8072          uint32_t mask,
8073          uint8_t en)
8074 {
8075         int ret = 0;
8076
8077         if (l2_tunnel == NULL)
8078                 return -EINVAL;
8079
8080         ret = -EINVAL;
8081         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8082                 if (en)
8083                         ret = ixgbe_dev_l2_tunnel_enable(
8084                                 dev,
8085                                 l2_tunnel->l2_tunnel_type);
8086                 else
8087                         ret = ixgbe_dev_l2_tunnel_disable(
8088                                 dev,
8089                                 l2_tunnel->l2_tunnel_type);
8090         }
8091
8092         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8093                 if (en)
8094                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8095                                 dev,
8096                                 l2_tunnel);
8097                 else
8098                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8099                                 dev,
8100                                 l2_tunnel);
8101         }
8102
8103         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8104                 if (en)
8105                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8106                                 dev,
8107                                 l2_tunnel->l2_tunnel_type);
8108                 else
8109                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8110                                 dev,
8111                                 l2_tunnel->l2_tunnel_type);
8112         }
8113
8114         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8115                 if (en)
8116                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8117                                 dev,
8118                                 l2_tunnel->l2_tunnel_type);
8119                 else
8120                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8121                                 dev,
8122                                 l2_tunnel->l2_tunnel_type);
8123         }
8124
8125         return ret;
8126 }
8127
8128 static int
8129 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8130                         uint16_t port)
8131 {
8132         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8133         IXGBE_WRITE_FLUSH(hw);
8134
8135         return 0;
8136 }
8137
8138 /* There's only one register for VxLAN UDP port.
8139  * So, we cannot add several ports. Will update it.
8140  */
8141 static int
8142 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8143                      uint16_t port)
8144 {
8145         if (port == 0) {
8146                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8147                 return -EINVAL;
8148         }
8149
8150         return ixgbe_update_vxlan_port(hw, port);
8151 }
8152
8153 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8154  * UDP port, it must have a value.
8155  * So, will reset it to the original value 0.
8156  */
8157 static int
8158 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8159                      uint16_t port)
8160 {
8161         uint16_t cur_port;
8162
8163         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8164
8165         if (cur_port != port) {
8166                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8167                 return -EINVAL;
8168         }
8169
8170         return ixgbe_update_vxlan_port(hw, 0);
8171 }
8172
8173 /* Add UDP tunneling port */
8174 static int
8175 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8176                               struct rte_eth_udp_tunnel *udp_tunnel)
8177 {
8178         int ret = 0;
8179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8180
8181         if (hw->mac.type != ixgbe_mac_X550 &&
8182             hw->mac.type != ixgbe_mac_X550EM_x &&
8183             hw->mac.type != ixgbe_mac_X550EM_a) {
8184                 return -ENOTSUP;
8185         }
8186
8187         if (udp_tunnel == NULL)
8188                 return -EINVAL;
8189
8190         switch (udp_tunnel->prot_type) {
8191         case RTE_TUNNEL_TYPE_VXLAN:
8192                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8193                 break;
8194
8195         case RTE_TUNNEL_TYPE_GENEVE:
8196         case RTE_TUNNEL_TYPE_TEREDO:
8197                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8198                 ret = -EINVAL;
8199                 break;
8200
8201         default:
8202                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8203                 ret = -EINVAL;
8204                 break;
8205         }
8206
8207         return ret;
8208 }
8209
8210 /* Remove UDP tunneling port */
8211 static int
8212 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8213                               struct rte_eth_udp_tunnel *udp_tunnel)
8214 {
8215         int ret = 0;
8216         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8217
8218         if (hw->mac.type != ixgbe_mac_X550 &&
8219             hw->mac.type != ixgbe_mac_X550EM_x &&
8220             hw->mac.type != ixgbe_mac_X550EM_a) {
8221                 return -ENOTSUP;
8222         }
8223
8224         if (udp_tunnel == NULL)
8225                 return -EINVAL;
8226
8227         switch (udp_tunnel->prot_type) {
8228         case RTE_TUNNEL_TYPE_VXLAN:
8229                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8230                 break;
8231         case RTE_TUNNEL_TYPE_GENEVE:
8232         case RTE_TUNNEL_TYPE_TEREDO:
8233                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8234                 ret = -EINVAL;
8235                 break;
8236         default:
8237                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8238                 ret = -EINVAL;
8239                 break;
8240         }
8241
8242         return ret;
8243 }
8244
8245 static void
8246 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8247 {
8248         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8249
8250         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8251 }
8252
8253 static void
8254 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8255 {
8256         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8257
8258         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8259 }
8260
8261 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8262 {
8263         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8264         u32 in_msg = 0;
8265
8266         /* peek the message first */
8267         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8268
8269         /* PF reset VF event */
8270         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8271                 /* dummy mbx read to ack pf */
8272                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8273                         return;
8274                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8275                                               NULL);
8276         }
8277 }
8278
8279 static int
8280 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8281 {
8282         uint32_t eicr;
8283         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8284         struct ixgbe_interrupt *intr =
8285                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8286         ixgbevf_intr_disable(dev);
8287
8288         /* read-on-clear nic registers here */
8289         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8290         intr->flags = 0;
8291
8292         /* only one misc vector supported - mailbox */
8293         eicr &= IXGBE_VTEICR_MASK;
8294         if (eicr == IXGBE_MISC_VEC_ID)
8295                 intr->flags |= IXGBE_FLAG_MAILBOX;
8296
8297         return 0;
8298 }
8299
8300 static int
8301 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8302 {
8303         struct ixgbe_interrupt *intr =
8304                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8305
8306         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8307                 ixgbevf_mbx_process(dev);
8308                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8309         }
8310
8311         ixgbevf_intr_enable(dev);
8312
8313         return 0;
8314 }
8315
8316 static void
8317 ixgbevf_dev_interrupt_handler(void *param)
8318 {
8319         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8320
8321         ixgbevf_dev_interrupt_get_status(dev);
8322         ixgbevf_dev_interrupt_action(dev);
8323 }
8324
8325 /**
8326  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8327  *  @hw: pointer to hardware structure
8328  *
8329  *  Stops the transmit data path and waits for the HW to internally empty
8330  *  the Tx security block
8331  **/
8332 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8333 {
8334 #define IXGBE_MAX_SECTX_POLL 40
8335
8336         int i;
8337         int sectxreg;
8338
8339         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8340         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8341         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8342         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8343                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8344                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8345                         break;
8346                 /* Use interrupt-safe sleep just in case */
8347                 usec_delay(1000);
8348         }
8349
8350         /* For informational purposes only */
8351         if (i >= IXGBE_MAX_SECTX_POLL)
8352                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8353                          "path fully disabled.  Continuing with init.");
8354
8355         return IXGBE_SUCCESS;
8356 }
8357
8358 /**
8359  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8360  *  @hw: pointer to hardware structure
8361  *
8362  *  Enables the transmit data path.
8363  **/
8364 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8365 {
8366         uint32_t sectxreg;
8367
8368         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8369         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8370         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8371         IXGBE_WRITE_FLUSH(hw);
8372
8373         return IXGBE_SUCCESS;
8374 }
8375
8376 /* restore n-tuple filter */
8377 static inline void
8378 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8379 {
8380         struct ixgbe_filter_info *filter_info =
8381                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8382         struct ixgbe_5tuple_filter *node;
8383
8384         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8385                 ixgbe_inject_5tuple_filter(dev, node);
8386         }
8387 }
8388
8389 /* restore ethernet type filter */
8390 static inline void
8391 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8392 {
8393         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8394         struct ixgbe_filter_info *filter_info =
8395                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8396         int i;
8397
8398         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8399                 if (filter_info->ethertype_mask & (1 << i)) {
8400                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8401                                         filter_info->ethertype_filters[i].etqf);
8402                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8403                                         filter_info->ethertype_filters[i].etqs);
8404                         IXGBE_WRITE_FLUSH(hw);
8405                 }
8406         }
8407 }
8408
8409 /* restore SYN filter */
8410 static inline void
8411 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8412 {
8413         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8414         struct ixgbe_filter_info *filter_info =
8415                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8416         uint32_t synqf;
8417
8418         synqf = filter_info->syn_info;
8419
8420         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8421                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8422                 IXGBE_WRITE_FLUSH(hw);
8423         }
8424 }
8425
8426 /* restore L2 tunnel filter */
8427 static inline void
8428 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8429 {
8430         struct ixgbe_l2_tn_info *l2_tn_info =
8431                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8432         struct ixgbe_l2_tn_filter *node;
8433         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8434
8435         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8436                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8437                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8438                 l2_tn_conf.pool           = node->pool;
8439                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8440         }
8441 }
8442
8443 /* restore rss filter */
8444 static inline void
8445 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8446 {
8447         struct ixgbe_filter_info *filter_info =
8448                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8449
8450         if (filter_info->rss_info.conf.queue_num)
8451                 ixgbe_config_rss_filter(dev,
8452                         &filter_info->rss_info, TRUE);
8453 }
8454
8455 static int
8456 ixgbe_filter_restore(struct rte_eth_dev *dev)
8457 {
8458         ixgbe_ntuple_filter_restore(dev);
8459         ixgbe_ethertype_filter_restore(dev);
8460         ixgbe_syn_filter_restore(dev);
8461         ixgbe_fdir_filter_restore(dev);
8462         ixgbe_l2_tn_filter_restore(dev);
8463         ixgbe_rss_filter_restore(dev);
8464
8465         return 0;
8466 }
8467
8468 static void
8469 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8470 {
8471         struct ixgbe_l2_tn_info *l2_tn_info =
8472                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8473         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8474
8475         if (l2_tn_info->e_tag_en)
8476                 (void)ixgbe_e_tag_enable(hw);
8477
8478         if (l2_tn_info->e_tag_fwd_en)
8479                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8480
8481         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8482 }
8483
8484 /* remove all the n-tuple filters */
8485 void
8486 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8487 {
8488         struct ixgbe_filter_info *filter_info =
8489                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8490         struct ixgbe_5tuple_filter *p_5tuple;
8491
8492         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8493                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8494 }
8495
8496 /* remove all the ether type filters */
8497 void
8498 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8499 {
8500         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8501         struct ixgbe_filter_info *filter_info =
8502                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8503         int i;
8504
8505         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8506                 if (filter_info->ethertype_mask & (1 << i) &&
8507                     !filter_info->ethertype_filters[i].conf) {
8508                         (void)ixgbe_ethertype_filter_remove(filter_info,
8509                                                             (uint8_t)i);
8510                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8511                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8512                         IXGBE_WRITE_FLUSH(hw);
8513                 }
8514         }
8515 }
8516
8517 /* remove the SYN filter */
8518 void
8519 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8520 {
8521         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8522         struct ixgbe_filter_info *filter_info =
8523                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8524
8525         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8526                 filter_info->syn_info = 0;
8527
8528                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8529                 IXGBE_WRITE_FLUSH(hw);
8530         }
8531 }
8532
8533 /* remove all the L2 tunnel filters */
8534 int
8535 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8536 {
8537         struct ixgbe_l2_tn_info *l2_tn_info =
8538                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8539         struct ixgbe_l2_tn_filter *l2_tn_filter;
8540         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8541         int ret = 0;
8542
8543         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8544                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8545                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8546                 l2_tn_conf.pool           = l2_tn_filter->pool;
8547                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8548                 if (ret < 0)
8549                         return ret;
8550         }
8551
8552         return 0;
8553 }
8554
8555 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8556 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8557 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8558 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8559 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8560 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8561
8562 RTE_INIT(ixgbe_init_log);
8563 static void
8564 ixgbe_init_log(void)
8565 {
8566         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8567         if (ixgbe_logtype_init >= 0)
8568                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8569         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8570         if (ixgbe_logtype_driver >= 0)
8571                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8572 }