drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Timer value included in XOFF frames. */
  63 #define IXGBE_FC_PAUSE 0x680
  64
  65 /*Default value of Max Rx Queue*/
  66 #define IXGBE_MAX_RX_QUEUE_NUM 128
  67
  68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  71
  72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  75
  76 /*
  77  *  Default values for RX/TX configuration
  78  */
  79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  80 #define IXGBE_DEFAULT_RX_PTHRESH      8
  81 #define IXGBE_DEFAULT_RX_HTHRESH      8
  82 #define IXGBE_DEFAULT_RX_WTHRESH      0
  83
  84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  85 #define IXGBE_DEFAULT_TX_PTHRESH      32
  86 #define IXGBE_DEFAULT_TX_HTHRESH      0
  87 #define IXGBE_DEFAULT_TX_WTHRESH      0
  88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  89
  90 /* Bit shift and mask */
  91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  94 #define IXGBE_8_BIT_MASK   UINT8_MAX
  95
  96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  97
  98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  99
 100 /* Additional timesync values. */
 101 #define NSEC_PER_SEC             1000000000L
 102 #define IXGBE_INCVAL_10GB        0x66666666
 103 #define IXGBE_INCVAL_1GB         0x40000000
 104 #define IXGBE_INCVAL_100         0x50000000
 105 #define IXGBE_INCVAL_SHIFT_10GB  28
 106 #define IXGBE_INCVAL_SHIFT_1GB   24
 107 #define IXGBE_INCVAL_SHIFT_100   21
 108 #define IXGBE_INCVAL_SHIFT_82599 7
 109 #define IXGBE_INCPER_SHIFT_82599 24
 110
 111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 115 #define IXGBE_ETAG_ETYPE                       0x00005084
 116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 118 #define IXGBE_RAH_ADTYPE                       0x40000000
 119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 124 #define IXGBE_VTEICR_MASK                      0x07
 125
 126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 128
 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 148                                 int wait_to_complete);
 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 150                                 struct rte_eth_stats *stats);
 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 152                                 struct rte_eth_xstat *xstats, unsigned n);
 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 154                                   struct rte_eth_xstat *xstats, unsigned n);
 155 static int
 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 157                 uint64_t *values, unsigned int n);
 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 161         struct rte_eth_xstat_name *xstats_names,
 162         unsigned int size);
 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 165 static int ixgbe_dev_xstats_get_names_by_id(
 166         struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         const uint64_t *ids,
 169         unsigned int limit);
 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 171                                              uint16_t queue_id,
 172                                              uint8_t stat_idx,
 173                                              uint8_t is_rx);
 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 175                                  size_t fw_size);
 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_dev_info *dev_info);
 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 180                                  struct rte_eth_dev_info *dev_info);
 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 182
 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 184                 uint16_t vlan_id, int on);
 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 186                                enum rte_vlan_type vlan_type,
 187                                uint16_t tpid_id);
 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 189                 uint16_t queue, bool on);
 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 191                 int on);
 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 193                                                   int mask);
 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 221 static void ixgbe_dev_interrupt_handler(void *param);
 222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 223 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 224
 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 226                          uint32_t index, uint32_t pool);
 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 228 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 229                                            struct ether_addr *mac_addr);
 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 231 static bool is_device_supported(struct rte_eth_dev *dev,
 232                                 struct rte_pci_driver *drv);
 233
 234 /* For Virtual Function support */
 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 237 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 238 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 240                                    int wait_to_complete);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 245 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 254 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 256 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 257                                             uint16_t queue_id);
 258 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 259                                              uint16_t queue_id);
 260 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 261                                  uint8_t queue, uint8_t msix_vector);
 262 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 265
 266 /* For Eth VMDQ APIs support */
 267 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 268                 ether_addr * mac_addr, uint8_t on);
 269 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 270 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 271                 struct rte_eth_mirror_conf *mirror_conf,
 272                 uint8_t rule_id, uint8_t on);
 273 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 274                 uint8_t rule_id);
 275 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 276                                           uint16_t queue_id);
 277 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 278                                            uint16_t queue_id);
 279 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 280                                uint8_t queue, uint8_t msix_vector);
 281 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 282
 283 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 284                                 struct ether_addr *mac_addr,
 285                                 uint32_t index, uint32_t pool);
 286 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 287 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 288                                              struct ether_addr *mac_addr);
 289 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 290                         struct rte_eth_syn_filter *filter);
 291 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 292                         enum rte_filter_op filter_op,
 293                         void *arg);
 294 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 295                         struct ixgbe_5tuple_filter *filter);
 296 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 297                         struct ixgbe_5tuple_filter *filter);
 298 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 299                                 enum rte_filter_op filter_op,
 300                                 void *arg);
 301 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 302                         struct rte_eth_ntuple_filter *filter);
 303 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 304                                 enum rte_filter_op filter_op,
 305                                 void *arg);
 306 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 307                         struct rte_eth_ethertype_filter *filter);
 308 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 309                      enum rte_filter_type filter_type,
 310                      enum rte_filter_op filter_op,
 311                      void *arg);
 312 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 313
 314 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 315                                       struct ether_addr *mc_addr_set,
 316                                       uint32_t nb_mc_addr);
 317 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 318                                    struct rte_eth_dcb_info *dcb_info);
 319
 320 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 321 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 322                             struct rte_dev_reg_info *regs);
 323 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 324 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 325                                 struct rte_dev_eeprom_info *eeprom);
 326 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 327                                 struct rte_dev_eeprom_info *eeprom);
 328
 329 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 330                                  struct rte_eth_dev_module_info *modinfo);
 331 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 332                                    struct rte_dev_eeprom_info *info);
 333
 334 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 336                                 struct rte_dev_reg_info *regs);
 337
 338 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 340 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 341                                             struct timespec *timestamp,
 342                                             uint32_t flags);
 343 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 344                                             struct timespec *timestamp);
 345 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 346 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 347                                    struct timespec *timestamp);
 348 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 349                                    const struct timespec *timestamp);
 350 static void ixgbevf_dev_interrupt_handler(void *param);
 351
 352 static int ixgbe_dev_l2_tunnel_eth_type_conf
 353         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 354 static int ixgbe_dev_l2_tunnel_offload_set
 355         (struct rte_eth_dev *dev,
 356          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 357          uint32_t mask,
 358          uint8_t en);
 359 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 360                                              enum rte_filter_op filter_op,
 361                                              void *arg);
 362
 363 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 364                                          struct rte_eth_udp_tunnel *udp_tunnel);
 365 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 366                                          struct rte_eth_udp_tunnel *udp_tunnel);
 367 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 368 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 369
 370 /*
 371  * Define VF Stats MACRO for Non "cleared on read" register
 372  */
 373 #define UPDATE_VF_STAT(reg, last, cur)                          \
 374 {                                                               \
 375         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 376         cur += (latest - last) & UINT_MAX;                      \
 377         last = latest;                                          \
 378 }
 379
 380 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 381 {                                                                \
 382         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 383         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 384         u64 latest = ((new_msb << 32) | new_lsb);                \
 385         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 386         last = latest;                                           \
 387 }
 388
 389 #define IXGBE_SET_HWSTRIP(h, q) do {\
 390                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 391                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 392                 (h)->bitmap[idx] |= 1 << bit;\
 393         } while (0)
 394
 395 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 396                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 397                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 398                 (h)->bitmap[idx] &= ~(1 << bit);\
 399         } while (0)
 400
 401 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (r) = (h)->bitmap[idx] >> bit & 1;\
 405         } while (0)
 406
 407 int ixgbe_logtype_init;
 408 int ixgbe_logtype_driver;
 409
 410 /*
 411  * The set of PCI devices this driver supports
 412  */
 413 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 461 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 463 #endif
 464         { .vendor_id = 0, /* sentinel */ },
 465 };
 466
 467 /*
 468  * The set of PCI devices this driver supports (for 82599 VF)
 469  */
 470 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 481         { .vendor_id = 0, /* sentinel */ },
 482 };
 483
 484 static const struct rte_eth_desc_lim rx_desc_lim = {
 485         .nb_max = IXGBE_MAX_RING_DESC,
 486         .nb_min = IXGBE_MIN_RING_DESC,
 487         .nb_align = IXGBE_RXD_ALIGN,
 488 };
 489
 490 static const struct rte_eth_desc_lim tx_desc_lim = {
 491         .nb_max = IXGBE_MAX_RING_DESC,
 492         .nb_min = IXGBE_MIN_RING_DESC,
 493         .nb_align = IXGBE_TXD_ALIGN,
 494         .nb_seg_max = IXGBE_TX_MAX_SEG,
 495         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 496 };
 497
 498 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 499         .dev_configure        = ixgbe_dev_configure,
 500         .dev_start            = ixgbe_dev_start,
 501         .dev_stop             = ixgbe_dev_stop,
 502         .dev_set_link_up    = ixgbe_dev_set_link_up,
 503         .dev_set_link_down  = ixgbe_dev_set_link_down,
 504         .dev_close            = ixgbe_dev_close,
 505         .dev_reset            = ixgbe_dev_reset,
 506         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 507         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 508         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 509         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 510         .link_update          = ixgbe_dev_link_update,
 511         .stats_get            = ixgbe_dev_stats_get,
 512         .xstats_get           = ixgbe_dev_xstats_get,
 513         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 514         .stats_reset          = ixgbe_dev_stats_reset,
 515         .xstats_reset         = ixgbe_dev_xstats_reset,
 516         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 517         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 518         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 519         .fw_version_get       = ixgbe_fw_version_get,
 520         .dev_infos_get        = ixgbe_dev_info_get,
 521         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 522         .mtu_set              = ixgbe_dev_mtu_set,
 523         .vlan_filter_set      = ixgbe_vlan_filter_set,
 524         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 525         .vlan_offload_set     = ixgbe_vlan_offload_set,
 526         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 527         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 528         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 529         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 530         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 531         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 532         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 533         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 534         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 535         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 536         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 537         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 538         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 539         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 540         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 541         .dev_led_on           = ixgbe_dev_led_on,
 542         .dev_led_off          = ixgbe_dev_led_off,
 543         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 544         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 545         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 546         .mac_addr_add         = ixgbe_add_rar,
 547         .mac_addr_remove      = ixgbe_remove_rar,
 548         .mac_addr_set         = ixgbe_set_default_mac_addr,
 549         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 550         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 551         .mirror_rule_set      = ixgbe_mirror_rule_set,
 552         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 553         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 554         .reta_update          = ixgbe_dev_rss_reta_update,
 555         .reta_query           = ixgbe_dev_rss_reta_query,
 556         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 557         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 558         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 559         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 560         .rxq_info_get         = ixgbe_rxq_info_get,
 561         .txq_info_get         = ixgbe_txq_info_get,
 562         .timesync_enable      = ixgbe_timesync_enable,
 563         .timesync_disable     = ixgbe_timesync_disable,
 564         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 565         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 566         .get_reg              = ixgbe_get_regs,
 567         .get_eeprom_length    = ixgbe_get_eeprom_length,
 568         .get_eeprom           = ixgbe_get_eeprom,
 569         .set_eeprom           = ixgbe_set_eeprom,
 570         .get_module_info      = ixgbe_get_module_info,
 571         .get_module_eeprom    = ixgbe_get_module_eeprom,
 572         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 573         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 574         .timesync_read_time   = ixgbe_timesync_read_time,
 575         .timesync_write_time  = ixgbe_timesync_write_time,
 576         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 577         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 578         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 579         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 580         .tm_ops_get           = ixgbe_tm_ops_get,
 581 };
 582
 583 /*
 584  * dev_ops for virtual function, bare necessities for basic vf
 585  * operation have been implemented
 586  */
 587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 588         .dev_configure        = ixgbevf_dev_configure,
 589         .dev_start            = ixgbevf_dev_start,
 590         .dev_stop             = ixgbevf_dev_stop,
 591         .link_update          = ixgbevf_dev_link_update,
 592         .stats_get            = ixgbevf_dev_stats_get,
 593         .xstats_get           = ixgbevf_dev_xstats_get,
 594         .stats_reset          = ixgbevf_dev_stats_reset,
 595         .xstats_reset         = ixgbevf_dev_stats_reset,
 596         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 597         .dev_close            = ixgbevf_dev_close,
 598         .dev_reset            = ixgbevf_dev_reset,
 599         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 600         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 601         .dev_infos_get        = ixgbevf_dev_info_get,
 602         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 603         .mtu_set              = ixgbevf_dev_set_mtu,
 604         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 605         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 606         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 607         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 608         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 609         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 610         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 611         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 612         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 613         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 614         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 615         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 616         .mac_addr_add         = ixgbevf_add_mac_addr,
 617         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 618         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 619         .rxq_info_get         = ixgbe_rxq_info_get,
 620         .txq_info_get         = ixgbe_txq_info_get,
 621         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 622         .get_reg              = ixgbevf_get_regs,
 623         .reta_update          = ixgbe_dev_rss_reta_update,
 624         .reta_query           = ixgbe_dev_rss_reta_query,
 625         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 626         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 627 };
 628
 629 /* store statistics names and its offset in stats structure */
 630 struct rte_ixgbe_xstats_name_off {
 631         char name[RTE_ETH_XSTATS_NAME_SIZE];
 632         unsigned offset;
 633 };
 634
 635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 636         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 637         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 638         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 639         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 640         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 641         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 642         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 643         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 644         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 645         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 646         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 647         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 648         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 649         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 650         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 651                 prc1023)},
 652         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 653                 prc1522)},
 654         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 655         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 656         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 657         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 658         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 659         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 660         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 661         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 662         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 663         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 664         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 665         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 666         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 667         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 668         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 669         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 670         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 671                 ptc1023)},
 672         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 673                 ptc1522)},
 674         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 675         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 676         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 677         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 678
 679         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 680                 fdirustat_add)},
 681         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 682                 fdirustat_remove)},
 683         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 684                 fdirfstat_fadd)},
 685         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 686                 fdirfstat_fremove)},
 687         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 688                 fdirmatch)},
 689         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirmiss)},
 691
 692         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 693         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 694         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 695                 fclast)},
 696         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 697         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 698         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 699         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 700         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 701                 fcoe_noddp)},
 702         {"rx_fcoe_no_direct_data_placement_ext_buff",
 703                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 704
 705         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxontxc)},
 707         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxonrxc)},
 709         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxofftxc)},
 711         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxoffrxc)},
 713         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 714 };
 715
 716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 717                            sizeof(rte_ixgbe_stats_strings[0]))
 718
 719 /* MACsec statistics */
 720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 721         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_untagged)},
 723         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_pkts_encrypted)},
 725         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_protected)},
 727         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 728                 out_octets_encrypted)},
 729         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 730                 out_octets_protected)},
 731         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_untagged)},
 733         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_badtag)},
 735         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_nosci)},
 737         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unknownsci)},
 739         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 740                 in_octets_decrypted)},
 741         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 742                 in_octets_validated)},
 743         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_unchecked)},
 745         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_delayed)},
 747         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_late)},
 749         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_ok)},
 751         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_invalid)},
 753         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notvalid)},
 755         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unusedsa)},
 757         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_notusingsa)},
 759 };
 760
 761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 762                            sizeof(rte_ixgbe_macsec_strings[0]))
 763
 764 /* Per-queue statistics */
 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 766         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 767         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 768         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 769         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 770 };
 771
 772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 773                            sizeof(rte_ixgbe_rxq_strings[0]))
 774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 775
 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 777         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 778         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 779         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 780                 pxon2offc)},
 781 };
 782
 783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 784                            sizeof(rte_ixgbe_txq_strings[0]))
 785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 786
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 788         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 789 };
 790
 791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 792                 sizeof(rte_ixgbevf_stats_strings[0]))
 793
 794 /*
 795  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 796  */
 797 static inline int
 798 ixgbe_is_sfp(struct ixgbe_hw *hw)
 799 {
 800         switch (hw->phy.type) {
 801         case ixgbe_phy_sfp_avago:
 802         case ixgbe_phy_sfp_ftl:
 803         case ixgbe_phy_sfp_intel:
 804         case ixgbe_phy_sfp_unknown:
 805         case ixgbe_phy_sfp_passive_tyco:
 806         case ixgbe_phy_sfp_passive_unknown:
 807                 return 1;
 808         default:
 809                 return 0;
 810         }
 811 }
 812
 813 static inline int32_t
 814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 815 {
 816         uint32_t ctrl_ext;
 817         int32_t status;
 818
 819         status = ixgbe_reset_hw(hw);
 820
 821         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 822         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 823         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 824         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 825         IXGBE_WRITE_FLUSH(hw);
 826
 827         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 828                 status = IXGBE_SUCCESS;
 829         return status;
 830 }
 831
 832 static inline void
 833 ixgbe_enable_intr(struct rte_eth_dev *dev)
 834 {
 835         struct ixgbe_interrupt *intr =
 836                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 837         struct ixgbe_hw *hw =
 838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839
 840         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 846  */
 847 static void
 848 ixgbe_disable_intr(struct ixgbe_hw *hw)
 849 {
 850         PMD_INIT_FUNC_TRACE();
 851
 852         if (hw->mac.type == ixgbe_mac_82598EB) {
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 854         } else {
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 858         }
 859         IXGBE_WRITE_FLUSH(hw);
 860 }
 861
 862 /*
 863  * This function resets queue statistics mapping registers.
 864  * From Niantic datasheet, Initialization of Statistics section:
 865  * "...if software requires the queue counters, the RQSMR and TQSM registers
 866  * must be re-programmed following a device reset.
 867  */
 868 static void
 869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 870 {
 871         uint32_t i;
 872
 873         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 875                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 876         }
 877 }
 878
 879
 880 static int
 881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 882                                   uint16_t queue_id,
 883                                   uint8_t stat_idx,
 884                                   uint8_t is_rx)
 885 {
 886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 889
 890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 891         struct ixgbe_stat_mapping_registers *stat_mappings =
 892                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 893         uint32_t qsmr_mask = 0;
 894         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 895         uint32_t q_map;
 896         uint8_t n, offset;
 897
 898         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 899                 (hw->mac.type != ixgbe_mac_X540) &&
 900                 (hw->mac.type != ixgbe_mac_X550) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 902                 (hw->mac.type != ixgbe_mac_X550EM_a))
 903                 return -ENOSYS;
 904
 905         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 906                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 907                      queue_id, stat_idx);
 908
 909         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 910         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 911                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 912                 return -EIO;
 913         }
 914         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 915
 916         /* Now clear any previous stat_idx set */
 917         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 918         if (!is_rx)
 919                 stat_mappings->tqsm[n] &= ~clearing_mask;
 920         else
 921                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 922
 923         q_map = (uint32_t)stat_idx;
 924         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 925         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 926         if (!is_rx)
 927                 stat_mappings->tqsm[n] |= qsmr_mask;
 928         else
 929                 stat_mappings->rqsmr[n] |= qsmr_mask;
 930
 931         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 932                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 933                      queue_id, stat_idx);
 934         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 935                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 936
 937         /* Now write the mapping in the appropriate register */
 938         if (is_rx) {
 939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 940                              stat_mappings->rqsmr[n], n);
 941                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 942         } else {
 943                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 944                              stat_mappings->tqsm[n], n);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 946         }
 947         return 0;
 948 }
 949
 950 static void
 951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 952 {
 953         struct ixgbe_stat_mapping_registers *stat_mappings =
 954                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956         int i;
 957
 958         /* write whatever was in stat mapping table to the NIC */
 959         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 960                 /* rx */
 961                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 962
 963                 /* tx */
 964                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 965         }
 966 }
 967
 968 static void
 969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 970 {
 971         uint8_t i;
 972         struct ixgbe_dcb_tc_config *tc;
 973         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 974
 975         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 976         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 977         for (i = 0; i < dcb_max_tc; i++) {
 978                 tc = &dcb_config->tc_config[i];
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 980                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 981                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 983                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 984                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 985                 tc->pfc = ixgbe_dcb_pfc_disabled;
 986         }
 987
 988         /* Initialize default user to priority mapping, UPx->TC0 */
 989         tc = &dcb_config->tc_config[0];
 990         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 992         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 993                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 994                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 995         }
 996         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 997         dcb_config->pfc_mode_enable = false;
 998         dcb_config->vt_mode = true;
 999         dcb_config->round_robin_enable = false;
1000         /* support all DCB capabilities in 82599 */
1001         dcb_config->support.capabilities = 0xFF;
1002
1003         /*we only support 4 Tcs for X540, X550 */
1004         if (hw->mac.type == ixgbe_mac_X540 ||
1005                 hw->mac.type == ixgbe_mac_X550 ||
1006                 hw->mac.type == ixgbe_mac_X550EM_x ||
1007                 hw->mac.type == ixgbe_mac_X550EM_a) {
1008                 dcb_config->num_tcs.pg_tcs = 4;
1009                 dcb_config->num_tcs.pfc_tcs = 4;
1010         }
1011 }
1012
1013 /*
1014  * Ensure that all locks are released before first NVM or PHY access
1015  */
1016 static void
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1018 {
1019         uint16_t mask;
1020
1021         /*
1022          * Phy lock should not fail in this early stage. If this is the case,
1023          * it is due to an improper exit of the application.
1024          * So force the release of the faulty lock. Release of common lock
1025          * is done automatically by swfw_sync function.
1026          */
1027         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1030         }
1031         ixgbe_release_swfw_semaphore(hw, mask);
1032
1033         /*
1034          * These ones are more tricky since they are common to all ports; but
1035          * swfw_sync retries last long enough (1s) to be almost sure that if
1036          * lock can not be taken it is due to an improper lock of the
1037          * semaphore.
1038          */
1039         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1042         }
1043         ixgbe_release_swfw_semaphore(hw, mask);
1044 }
1045
1046 /*
1047  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048  * It returns 0 on success.
1049  */
1050 static int
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1052 {
1053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1055         struct ixgbe_hw *hw =
1056                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1057         struct ixgbe_vfta *shadow_vfta =
1058                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1059         struct ixgbe_hwstrip *hwstrip =
1060                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1061         struct ixgbe_dcb_config *dcb_config =
1062                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1063         struct ixgbe_filter_info *filter_info =
1064                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1065         struct ixgbe_bw_conf *bw_conf =
1066                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1067         uint32_t ctrl_ext;
1068         uint16_t csum;
1069         int diag, i;
1070
1071         PMD_INIT_FUNC_TRACE();
1072
1073         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1074         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1075         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1076         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1077
1078         /*
1079          * For secondary processes, we don't initialise any further as primary
1080          * has already done this work. Only check we don't need a different
1081          * RX and TX function.
1082          */
1083         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1084                 struct ixgbe_tx_queue *txq;
1085                 /* TX queue function in primary, set by last queue initialized
1086                  * Tx queue may not initialized by primary process
1087                  */
1088                 if (eth_dev->data->tx_queues) {
1089                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1090                         ixgbe_set_tx_function(eth_dev, txq);
1091                 } else {
1092                         /* Use default TX function if we get here */
1093                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1094                                      "Using default TX function.");
1095                 }
1096
1097                 ixgbe_set_rx_function(eth_dev);
1098
1099                 return 0;
1100         }
1101
1102         rte_eth_copy_pci_info(eth_dev, pci_dev);
1103
1104         /* Vendor and Device ID need to be set before init of shared code */
1105         hw->device_id = pci_dev->id.device_id;
1106         hw->vendor_id = pci_dev->id.vendor_id;
1107         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1108         hw->allow_unsupported_sfp = 1;
1109
1110         /* Initialize the shared code (base driver) */
1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1112         diag = ixgbe_bypass_init_shared_code(hw);
1113 #else
1114         diag = ixgbe_init_shared_code(hw);
1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1116
1117         if (diag != IXGBE_SUCCESS) {
1118                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1119                 return -EIO;
1120         }
1121
1122         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1123                 PMD_INIT_LOG(ERR, "\nERROR: "
1124                         "Firmware recovery mode detected. Limiting functionality.\n"
1125                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1126                         "User Guide for details on firmware recovery mode.");
1127                 return -EIO;
1128         }
1129
1130         /* pick up the PCI bus settings for reporting later */
1131         ixgbe_get_bus_info(hw);
1132
1133         /* Unlock any pending hardware semaphore */
1134         ixgbe_swfw_lock_reset(hw);
1135
1136 #ifdef RTE_LIBRTE_SECURITY
1137         /* Initialize security_ctx only for primary process*/
1138         if (ixgbe_ipsec_ctx_create(eth_dev))
1139                 return -ENOMEM;
1140 #endif
1141
1142         /* Initialize DCB configuration*/
1143         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1144         ixgbe_dcb_init(hw, dcb_config);
1145         /* Get Hardware Flow Control setting */
1146         hw->fc.requested_mode = ixgbe_fc_full;
1147         hw->fc.current_mode = ixgbe_fc_full;
1148         hw->fc.pause_time = IXGBE_FC_PAUSE;
1149         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1150                 hw->fc.low_water[i] = IXGBE_FC_LO;
1151                 hw->fc.high_water[i] = IXGBE_FC_HI;
1152         }
1153         hw->fc.send_xon = 1;
1154
1155         /* Make sure we have a good EEPROM before we read from it */
1156         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1157         if (diag != IXGBE_SUCCESS) {
1158                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1159                 return -EIO;
1160         }
1161
1162 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1163         diag = ixgbe_bypass_init_hw(hw);
1164 #else
1165         diag = ixgbe_init_hw(hw);
1166 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1167
1168         /*
1169          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1170          * is called too soon after the kernel driver unbinding/binding occurs.
1171          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1172          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1173          * also called. See ixgbe_identify_phy_82599(). The reason for the
1174          * failure is not known, and only occuts when virtualisation features
1175          * are disabled in the bios. A delay of 100ms  was found to be enough by
1176          * trial-and-error, and is doubled to be safe.
1177          */
1178         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1179                 rte_delay_ms(200);
1180                 diag = ixgbe_init_hw(hw);
1181         }
1182
1183         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1184                 diag = IXGBE_SUCCESS;
1185
1186         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1187                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1188                              "LOM.  Please be aware there may be issues associated "
1189                              "with your hardware.");
1190                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1191                              "please contact your Intel or hardware representative "
1192                              "who provided you with this hardware.");
1193         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1194                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1195         if (diag) {
1196                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1197                 return -EIO;
1198         }
1199
1200         /* Reset the hw statistics */
1201         ixgbe_dev_stats_reset(eth_dev);
1202
1203         /* disable interrupt */
1204         ixgbe_disable_intr(hw);
1205
1206         /* reset mappings for queue statistics hw counters*/
1207         ixgbe_reset_qstat_mappings(hw);
1208
1209         /* Allocate memory for storing MAC addresses */
1210         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1211                                                hw->mac.num_rar_entries, 0);
1212         if (eth_dev->data->mac_addrs == NULL) {
1213                 PMD_INIT_LOG(ERR,
1214                              "Failed to allocate %u bytes needed to store "
1215                              "MAC addresses",
1216                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1217                 return -ENOMEM;
1218         }
1219         /* Copy the permanent MAC address */
1220         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1221                         &eth_dev->data->mac_addrs[0]);
1222
1223         /* Allocate memory for storing hash filter MAC addresses */
1224         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1225                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1226         if (eth_dev->data->hash_mac_addrs == NULL) {
1227                 PMD_INIT_LOG(ERR,
1228                              "Failed to allocate %d bytes needed to store MAC addresses",
1229                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1230                 return -ENOMEM;
1231         }
1232
1233         /* initialize the vfta */
1234         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1235
1236         /* initialize the hw strip bitmap*/
1237         memset(hwstrip, 0, sizeof(*hwstrip));
1238
1239         /* initialize PF if max_vfs not zero */
1240         ixgbe_pf_host_init(eth_dev);
1241
1242         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1243         /* let hardware know driver is loaded */
1244         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1245         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1246         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1247         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1248         IXGBE_WRITE_FLUSH(hw);
1249
1250         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1251                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1252                              (int) hw->mac.type, (int) hw->phy.type,
1253                              (int) hw->phy.sfp_type);
1254         else
1255                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1256                              (int) hw->mac.type, (int) hw->phy.type);
1257
1258         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1259                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1260                      pci_dev->id.device_id);
1261
1262         rte_intr_callback_register(intr_handle,
1263                                    ixgbe_dev_interrupt_handler, eth_dev);
1264
1265         /* enable uio/vfio intr/eventfd mapping */
1266         rte_intr_enable(intr_handle);
1267
1268         /* enable support intr */
1269         ixgbe_enable_intr(eth_dev);
1270
1271         /* initialize filter info */
1272         memset(filter_info, 0,
1273                sizeof(struct ixgbe_filter_info));
1274
1275         /* initialize 5tuple filter list */
1276         TAILQ_INIT(&filter_info->fivetuple_list);
1277
1278         /* initialize flow director filter list & hash */
1279         ixgbe_fdir_filter_init(eth_dev);
1280
1281         /* initialize l2 tunnel filter list & hash */
1282         ixgbe_l2_tn_filter_init(eth_dev);
1283
1284         /* initialize flow filter lists */
1285         ixgbe_filterlist_init();
1286
1287         /* initialize bandwidth configuration info */
1288         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1289
1290         /* initialize Traffic Manager configuration */
1291         ixgbe_tm_conf_init(eth_dev);
1292
1293         return 0;
1294 }
1295
1296 static int
1297 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1298 {
1299         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1300         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1301         struct ixgbe_hw *hw;
1302         int retries = 0;
1303         int ret;
1304
1305         PMD_INIT_FUNC_TRACE();
1306
1307         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1308                 return 0;
1309
1310         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1311
1312         if (hw->adapter_stopped == 0)
1313                 ixgbe_dev_close(eth_dev);
1314
1315         eth_dev->dev_ops = NULL;
1316         eth_dev->rx_pkt_burst = NULL;
1317         eth_dev->tx_pkt_burst = NULL;
1318
1319         /* Unlock any pending hardware semaphore */
1320         ixgbe_swfw_lock_reset(hw);
1321
1322         /* disable uio intr before callback unregister */
1323         rte_intr_disable(intr_handle);
1324
1325         do {
1326                 ret = rte_intr_callback_unregister(intr_handle,
1327                                 ixgbe_dev_interrupt_handler, eth_dev);
1328                 if (ret >= 0) {
1329                         break;
1330                 } else if (ret != -EAGAIN) {
1331                         PMD_INIT_LOG(ERR,
1332                                 "intr callback unregister failed: %d",
1333                                 ret);
1334                         return ret;
1335                 }
1336                 rte_delay_ms(100);
1337         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1338
1339         /* uninitialize PF if max_vfs not zero */
1340         ixgbe_pf_host_uninit(eth_dev);
1341
1342         /* remove all the fdir filters & hash */
1343         ixgbe_fdir_filter_uninit(eth_dev);
1344
1345         /* remove all the L2 tunnel filters & hash */
1346         ixgbe_l2_tn_filter_uninit(eth_dev);
1347
1348         /* Remove all ntuple filters of the device */
1349         ixgbe_ntuple_filter_uninit(eth_dev);
1350
1351         /* clear all the filters list */
1352         ixgbe_filterlist_flush();
1353
1354         /* Remove all Traffic Manager configuration */
1355         ixgbe_tm_conf_uninit(eth_dev);
1356
1357 #ifdef RTE_LIBRTE_SECURITY
1358         rte_free(eth_dev->security_ctx);
1359 #endif
1360
1361         return 0;
1362 }
1363
1364 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1365 {
1366         struct ixgbe_filter_info *filter_info =
1367                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1368         struct ixgbe_5tuple_filter *p_5tuple;
1369
1370         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1371                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1372                              p_5tuple,
1373                              entries);
1374                 rte_free(p_5tuple);
1375         }
1376         memset(filter_info->fivetuple_mask, 0,
1377                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1378
1379         return 0;
1380 }
1381
1382 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1383 {
1384         struct ixgbe_hw_fdir_info *fdir_info =
1385                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1386         struct ixgbe_fdir_filter *fdir_filter;
1387
1388                 if (fdir_info->hash_map)
1389                 rte_free(fdir_info->hash_map);
1390         if (fdir_info->hash_handle)
1391                 rte_hash_free(fdir_info->hash_handle);
1392
1393         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1394                 TAILQ_REMOVE(&fdir_info->fdir_list,
1395                              fdir_filter,
1396                              entries);
1397                 rte_free(fdir_filter);
1398         }
1399
1400         return 0;
1401 }
1402
1403 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1404 {
1405         struct ixgbe_l2_tn_info *l2_tn_info =
1406                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1407         struct ixgbe_l2_tn_filter *l2_tn_filter;
1408
1409         if (l2_tn_info->hash_map)
1410                 rte_free(l2_tn_info->hash_map);
1411         if (l2_tn_info->hash_handle)
1412                 rte_hash_free(l2_tn_info->hash_handle);
1413
1414         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1415                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1416                              l2_tn_filter,
1417                              entries);
1418                 rte_free(l2_tn_filter);
1419         }
1420
1421         return 0;
1422 }
1423
1424 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1425 {
1426         struct ixgbe_hw_fdir_info *fdir_info =
1427                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1428         char fdir_hash_name[RTE_HASH_NAMESIZE];
1429         struct rte_hash_parameters fdir_hash_params = {
1430                 .name = fdir_hash_name,
1431                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1432                 .key_len = sizeof(union ixgbe_atr_input),
1433                 .hash_func = rte_hash_crc,
1434                 .hash_func_init_val = 0,
1435                 .socket_id = rte_socket_id(),
1436         };
1437
1438         TAILQ_INIT(&fdir_info->fdir_list);
1439         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1440                  "fdir_%s", eth_dev->device->name);
1441         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1442         if (!fdir_info->hash_handle) {
1443                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1444                 return -EINVAL;
1445         }
1446         fdir_info->hash_map = rte_zmalloc("ixgbe",
1447                                           sizeof(struct ixgbe_fdir_filter *) *
1448                                           IXGBE_MAX_FDIR_FILTER_NUM,
1449                                           0);
1450         if (!fdir_info->hash_map) {
1451                 PMD_INIT_LOG(ERR,
1452                              "Failed to allocate memory for fdir hash map!");
1453                 return -ENOMEM;
1454         }
1455         fdir_info->mask_added = FALSE;
1456
1457         return 0;
1458 }
1459
1460 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1461 {
1462         struct ixgbe_l2_tn_info *l2_tn_info =
1463                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1464         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1465         struct rte_hash_parameters l2_tn_hash_params = {
1466                 .name = l2_tn_hash_name,
1467                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1468                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1469                 .hash_func = rte_hash_crc,
1470                 .hash_func_init_val = 0,
1471                 .socket_id = rte_socket_id(),
1472         };
1473
1474         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1475         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1476                  "l2_tn_%s", eth_dev->device->name);
1477         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1478         if (!l2_tn_info->hash_handle) {
1479                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1480                 return -EINVAL;
1481         }
1482         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1483                                    sizeof(struct ixgbe_l2_tn_filter *) *
1484                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1485                                    0);
1486         if (!l2_tn_info->hash_map) {
1487                 PMD_INIT_LOG(ERR,
1488                         "Failed to allocate memory for L2 TN hash map!");
1489                 return -ENOMEM;
1490         }
1491         l2_tn_info->e_tag_en = FALSE;
1492         l2_tn_info->e_tag_fwd_en = FALSE;
1493         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1494
1495         return 0;
1496 }
1497 /*
1498  * Negotiate mailbox API version with the PF.
1499  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1500  * Then we try to negotiate starting with the most recent one.
1501  * If all negotiation attempts fail, then we will proceed with
1502  * the default one (ixgbe_mbox_api_10).
1503  */
1504 static void
1505 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1506 {
1507         int32_t i;
1508
1509         /* start with highest supported, proceed down */
1510         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1511                 ixgbe_mbox_api_12,
1512                 ixgbe_mbox_api_11,
1513                 ixgbe_mbox_api_10,
1514         };
1515
1516         for (i = 0;
1517                         i != RTE_DIM(sup_ver) &&
1518                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1519                         i++)
1520                 ;
1521 }
1522
1523 static void
1524 generate_random_mac_addr(struct ether_addr *mac_addr)
1525 {
1526         uint64_t random;
1527
1528         /* Set Organizationally Unique Identifier (OUI) prefix. */
1529         mac_addr->addr_bytes[0] = 0x00;
1530         mac_addr->addr_bytes[1] = 0x09;
1531         mac_addr->addr_bytes[2] = 0xC0;
1532         /* Force indication of locally assigned MAC address. */
1533         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1534         /* Generate the last 3 bytes of the MAC address with a random number. */
1535         random = rte_rand();
1536         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1537 }
1538
1539 /*
1540  * Virtual Function device init
1541  */
1542 static int
1543 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1544 {
1545         int diag;
1546         uint32_t tc, tcs;
1547         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1548         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1549         struct ixgbe_hw *hw =
1550                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1551         struct ixgbe_vfta *shadow_vfta =
1552                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1553         struct ixgbe_hwstrip *hwstrip =
1554                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1555         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1556
1557         PMD_INIT_FUNC_TRACE();
1558
1559         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1560         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1561         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1562
1563         /* for secondary processes, we don't initialise any further as primary
1564          * has already done this work. Only check we don't need a different
1565          * RX function
1566          */
1567         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1568                 struct ixgbe_tx_queue *txq;
1569                 /* TX queue function in primary, set by last queue initialized
1570                  * Tx queue may not initialized by primary process
1571                  */
1572                 if (eth_dev->data->tx_queues) {
1573                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1574                         ixgbe_set_tx_function(eth_dev, txq);
1575                 } else {
1576                         /* Use default TX function if we get here */
1577                         PMD_INIT_LOG(NOTICE,
1578                                      "No TX queues configured yet. Using default TX function.");
1579                 }
1580
1581                 ixgbe_set_rx_function(eth_dev);
1582
1583                 return 0;
1584         }
1585
1586         rte_eth_copy_pci_info(eth_dev, pci_dev);
1587
1588         hw->device_id = pci_dev->id.device_id;
1589         hw->vendor_id = pci_dev->id.vendor_id;
1590         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1591
1592         /* initialize the vfta */
1593         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1594
1595         /* initialize the hw strip bitmap*/
1596         memset(hwstrip, 0, sizeof(*hwstrip));
1597
1598         /* Initialize the shared code (base driver) */
1599         diag = ixgbe_init_shared_code(hw);
1600         if (diag != IXGBE_SUCCESS) {
1601                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1602                 return -EIO;
1603         }
1604
1605         /* init_mailbox_params */
1606         hw->mbx.ops.init_params(hw);
1607
1608         /* Reset the hw statistics */
1609         ixgbevf_dev_stats_reset(eth_dev);
1610
1611         /* Disable the interrupts for VF */
1612         ixgbevf_intr_disable(eth_dev);
1613
1614         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1615         diag = hw->mac.ops.reset_hw(hw);
1616
1617         /*
1618          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1619          * the underlying PF driver has not assigned a MAC address to the VF.
1620          * In this case, assign a random MAC address.
1621          */
1622         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1623                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1624                 /*
1625                  * This error code will be propagated to the app by
1626                  * rte_eth_dev_reset, so use a public error code rather than
1627                  * the internal-only IXGBE_ERR_RESET_FAILED
1628                  */
1629                 return -EAGAIN;
1630         }
1631
1632         /* negotiate mailbox API version to use with the PF. */
1633         ixgbevf_negotiate_api(hw);
1634
1635         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1636         ixgbevf_get_queues(hw, &tcs, &tc);
1637
1638         /* Allocate memory for storing MAC addresses */
1639         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1640                                                hw->mac.num_rar_entries, 0);
1641         if (eth_dev->data->mac_addrs == NULL) {
1642                 PMD_INIT_LOG(ERR,
1643                              "Failed to allocate %u bytes needed to store "
1644                              "MAC addresses",
1645                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1646                 return -ENOMEM;
1647         }
1648
1649         /* Generate a random MAC address, if none was assigned by PF. */
1650         if (is_zero_ether_addr(perm_addr)) {
1651                 generate_random_mac_addr(perm_addr);
1652                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1653                 if (diag) {
1654                         rte_free(eth_dev->data->mac_addrs);
1655                         eth_dev->data->mac_addrs = NULL;
1656                         return diag;
1657                 }
1658                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1659                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1660                              "%02x:%02x:%02x:%02x:%02x:%02x",
1661                              perm_addr->addr_bytes[0],
1662                              perm_addr->addr_bytes[1],
1663                              perm_addr->addr_bytes[2],
1664                              perm_addr->addr_bytes[3],
1665                              perm_addr->addr_bytes[4],
1666                              perm_addr->addr_bytes[5]);
1667         }
1668
1669         /* Copy the permanent MAC address */
1670         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1671
1672         /* reset the hardware with the new settings */
1673         diag = hw->mac.ops.start_hw(hw);
1674         switch (diag) {
1675         case  0:
1676                 break;
1677
1678         default:
1679                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1680                 return -EIO;
1681         }
1682
1683         rte_intr_callback_register(intr_handle,
1684                                    ixgbevf_dev_interrupt_handler, eth_dev);
1685         rte_intr_enable(intr_handle);
1686         ixgbevf_intr_enable(eth_dev);
1687
1688         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1689                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1690                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1691
1692         return 0;
1693 }
1694
1695 /* Virtual Function device uninit */
1696
1697 static int
1698 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1699 {
1700         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1701         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1702         struct ixgbe_hw *hw;
1703
1704         PMD_INIT_FUNC_TRACE();
1705
1706         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1707                 return 0;
1708
1709         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1710
1711         if (hw->adapter_stopped == 0)
1712                 ixgbevf_dev_close(eth_dev);
1713
1714         eth_dev->dev_ops = NULL;
1715         eth_dev->rx_pkt_burst = NULL;
1716         eth_dev->tx_pkt_burst = NULL;
1717
1718         /* Disable the interrupts for VF */
1719         ixgbevf_intr_disable(eth_dev);
1720
1721         rte_intr_disable(intr_handle);
1722         rte_intr_callback_unregister(intr_handle,
1723                                      ixgbevf_dev_interrupt_handler, eth_dev);
1724
1725         return 0;
1726 }
1727
1728 static int
1729 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1730                 struct rte_pci_device *pci_dev)
1731 {
1732         char name[RTE_ETH_NAME_MAX_LEN];
1733         struct rte_eth_dev *pf_ethdev;
1734         struct rte_eth_devargs eth_da;
1735         int i, retval;
1736
1737         if (pci_dev->device.devargs) {
1738                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1739                                 &eth_da);
1740                 if (retval)
1741                         return retval;
1742         } else
1743                 memset(&eth_da, 0, sizeof(eth_da));
1744
1745         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1746                 sizeof(struct ixgbe_adapter),
1747                 eth_dev_pci_specific_init, pci_dev,
1748                 eth_ixgbe_dev_init, NULL);
1749
1750         if (retval || eth_da.nb_representor_ports < 1)
1751                 return retval;
1752
1753         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1754         if (pf_ethdev == NULL)
1755                 return -ENODEV;
1756
1757         /* probe VF representor ports */
1758         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1759                 struct ixgbe_vf_info *vfinfo;
1760                 struct ixgbe_vf_representor representor;
1761
1762                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1763                         pf_ethdev->data->dev_private);
1764                 if (vfinfo == NULL) {
1765                         PMD_DRV_LOG(ERR,
1766                                 "no virtual functions supported by PF");
1767                         break;
1768                 }
1769
1770                 representor.vf_id = eth_da.representor_ports[i];
1771                 representor.switch_domain_id = vfinfo->switch_domain_id;
1772                 representor.pf_ethdev = pf_ethdev;
1773
1774                 /* representor port net_bdf_port */
1775                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1776                         pci_dev->device.name,
1777                         eth_da.representor_ports[i]);
1778
1779                 retval = rte_eth_dev_create(&pci_dev->device, name,
1780                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1781                         ixgbe_vf_representor_init, &representor);
1782
1783                 if (retval)
1784                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1785                                 "representor %s.", name);
1786         }
1787
1788         return 0;
1789 }
1790
1791 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1792 {
1793         struct rte_eth_dev *ethdev;
1794
1795         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1796         if (!ethdev)
1797                 return -ENODEV;
1798
1799         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1800                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1801         else
1802                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1803 }
1804
1805 static struct rte_pci_driver rte_ixgbe_pmd = {
1806         .id_table = pci_id_ixgbe_map,
1807         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1808                      RTE_PCI_DRV_IOVA_AS_VA,
1809         .probe = eth_ixgbe_pci_probe,
1810         .remove = eth_ixgbe_pci_remove,
1811 };
1812
1813 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1814         struct rte_pci_device *pci_dev)
1815 {
1816         return rte_eth_dev_pci_generic_probe(pci_dev,
1817                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1818 }
1819
1820 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1821 {
1822         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1823 }
1824
1825 /*
1826  * virtual function driver struct
1827  */
1828 static struct rte_pci_driver rte_ixgbevf_pmd = {
1829         .id_table = pci_id_ixgbevf_map,
1830         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1831         .probe = eth_ixgbevf_pci_probe,
1832         .remove = eth_ixgbevf_pci_remove,
1833 };
1834
1835 static int
1836 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1837 {
1838         struct ixgbe_hw *hw =
1839                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         struct ixgbe_vfta *shadow_vfta =
1841                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1842         uint32_t vfta;
1843         uint32_t vid_idx;
1844         uint32_t vid_bit;
1845
1846         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1847         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1848         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1849         if (on)
1850                 vfta |= vid_bit;
1851         else
1852                 vfta &= ~vid_bit;
1853         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1854
1855         /* update local VFTA copy */
1856         shadow_vfta->vfta[vid_idx] = vfta;
1857
1858         return 0;
1859 }
1860
1861 static void
1862 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1863 {
1864         if (on)
1865                 ixgbe_vlan_hw_strip_enable(dev, queue);
1866         else
1867                 ixgbe_vlan_hw_strip_disable(dev, queue);
1868 }
1869
1870 static int
1871 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1872                     enum rte_vlan_type vlan_type,
1873                     uint16_t tpid)
1874 {
1875         struct ixgbe_hw *hw =
1876                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877         int ret = 0;
1878         uint32_t reg;
1879         uint32_t qinq;
1880
1881         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1882         qinq &= IXGBE_DMATXCTL_GDV;
1883
1884         switch (vlan_type) {
1885         case ETH_VLAN_TYPE_INNER:
1886                 if (qinq) {
1887                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1888                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1889                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1890                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1891                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1892                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1893                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1894                 } else {
1895                         ret = -ENOTSUP;
1896                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1897                                     " by single VLAN");
1898                 }
1899                 break;
1900         case ETH_VLAN_TYPE_OUTER:
1901                 if (qinq) {
1902                         /* Only the high 16-bits is valid */
1903                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1904                                         IXGBE_EXVET_VET_EXT_SHIFT);
1905                 } else {
1906                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1907                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1908                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1909                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1910                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1911                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1912                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1913                 }
1914
1915                 break;
1916         default:
1917                 ret = -EINVAL;
1918                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1919                 break;
1920         }
1921
1922         return ret;
1923 }
1924
1925 void
1926 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1927 {
1928         struct ixgbe_hw *hw =
1929                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         uint32_t vlnctrl;
1931
1932         PMD_INIT_FUNC_TRACE();
1933
1934         /* Filter Table Disable */
1935         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1936         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1937
1938         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1939 }
1940
1941 void
1942 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1943 {
1944         struct ixgbe_hw *hw =
1945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946         struct ixgbe_vfta *shadow_vfta =
1947                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1948         uint32_t vlnctrl;
1949         uint16_t i;
1950
1951         PMD_INIT_FUNC_TRACE();
1952
1953         /* Filter Table Enable */
1954         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1955         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1956         vlnctrl |= IXGBE_VLNCTRL_VFE;
1957
1958         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1959
1960         /* write whatever is in local vfta copy */
1961         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1962                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1963 }
1964
1965 static void
1966 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1967 {
1968         struct ixgbe_hwstrip *hwstrip =
1969                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1970         struct ixgbe_rx_queue *rxq;
1971
1972         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1973                 return;
1974
1975         if (on)
1976                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1977         else
1978                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1979
1980         if (queue >= dev->data->nb_rx_queues)
1981                 return;
1982
1983         rxq = dev->data->rx_queues[queue];
1984
1985         if (on) {
1986                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1987                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1988         } else {
1989                 rxq->vlan_flags = PKT_RX_VLAN;
1990                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1991         }
1992 }
1993
1994 static void
1995 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1996 {
1997         struct ixgbe_hw *hw =
1998                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1999         uint32_t ctrl;
2000
2001         PMD_INIT_FUNC_TRACE();
2002
2003         if (hw->mac.type == ixgbe_mac_82598EB) {
2004                 /* No queue level support */
2005                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2006                 return;
2007         }
2008
2009         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2010         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2011         ctrl &= ~IXGBE_RXDCTL_VME;
2012         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2013
2014         /* record those setting for HW strip per queue */
2015         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2016 }
2017
2018 static void
2019 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2020 {
2021         struct ixgbe_hw *hw =
2022                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023         uint32_t ctrl;
2024
2025         PMD_INIT_FUNC_TRACE();
2026
2027         if (hw->mac.type == ixgbe_mac_82598EB) {
2028                 /* No queue level supported */
2029                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2030                 return;
2031         }
2032
2033         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2034         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2035         ctrl |= IXGBE_RXDCTL_VME;
2036         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2037
2038         /* record those setting for HW strip per queue */
2039         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2040 }
2041
2042 static void
2043 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2044 {
2045         struct ixgbe_hw *hw =
2046                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2047         uint32_t ctrl;
2048
2049         PMD_INIT_FUNC_TRACE();
2050
2051         /* DMATXCTRL: Geric Double VLAN Disable */
2052         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2053         ctrl &= ~IXGBE_DMATXCTL_GDV;
2054         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2055
2056         /* CTRL_EXT: Global Double VLAN Disable */
2057         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2058         ctrl &= ~IXGBE_EXTENDED_VLAN;
2059         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2060
2061 }
2062
2063 static void
2064 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2065 {
2066         struct ixgbe_hw *hw =
2067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2068         uint32_t ctrl;
2069
2070         PMD_INIT_FUNC_TRACE();
2071
2072         /* DMATXCTRL: Geric Double VLAN Enable */
2073         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2074         ctrl |= IXGBE_DMATXCTL_GDV;
2075         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2076
2077         /* CTRL_EXT: Global Double VLAN Enable */
2078         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2079         ctrl |= IXGBE_EXTENDED_VLAN;
2080         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2081
2082         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2083         if (hw->mac.type == ixgbe_mac_X550 ||
2084             hw->mac.type == ixgbe_mac_X550EM_x ||
2085             hw->mac.type == ixgbe_mac_X550EM_a) {
2086                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2087                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2088                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2089         }
2090
2091         /*
2092          * VET EXT field in the EXVET register = 0x8100 by default
2093          * So no need to change. Same to VT field of DMATXCTL register
2094          */
2095 }
2096
2097 void
2098 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2099 {
2100         struct ixgbe_hw *hw =
2101                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2103         uint32_t ctrl;
2104         uint16_t i;
2105         struct ixgbe_rx_queue *rxq;
2106         bool on;
2107
2108         PMD_INIT_FUNC_TRACE();
2109
2110         if (hw->mac.type == ixgbe_mac_82598EB) {
2111                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2112                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2113                         ctrl |= IXGBE_VLNCTRL_VME;
2114                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2115                 } else {
2116                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2117                         ctrl &= ~IXGBE_VLNCTRL_VME;
2118                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2119                 }
2120         } else {
2121                 /*
2122                  * Other 10G NIC, the VLAN strip can be setup
2123                  * per queue in RXDCTL
2124                  */
2125                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2126                         rxq = dev->data->rx_queues[i];
2127                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2128                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2129                                 ctrl |= IXGBE_RXDCTL_VME;
2130                                 on = TRUE;
2131                         } else {
2132                                 ctrl &= ~IXGBE_RXDCTL_VME;
2133                                 on = FALSE;
2134                         }
2135                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2136
2137                         /* record those setting for HW strip per queue */
2138                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2139                 }
2140         }
2141 }
2142
2143 static void
2144 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2145 {
2146         uint16_t i;
2147         struct rte_eth_rxmode *rxmode;
2148         struct ixgbe_rx_queue *rxq;
2149
2150         if (mask & ETH_VLAN_STRIP_MASK) {
2151                 rxmode = &dev->data->dev_conf.rxmode;
2152                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2153                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2154                                 rxq = dev->data->rx_queues[i];
2155                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2156                         }
2157                 else
2158                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159                                 rxq = dev->data->rx_queues[i];
2160                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2161                         }
2162         }
2163 }
2164
2165 static int
2166 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2167 {
2168         struct rte_eth_rxmode *rxmode;
2169         rxmode = &dev->data->dev_conf.rxmode;
2170
2171         if (mask & ETH_VLAN_STRIP_MASK) {
2172                 ixgbe_vlan_hw_strip_config(dev);
2173         }
2174
2175         if (mask & ETH_VLAN_FILTER_MASK) {
2176                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2177                         ixgbe_vlan_hw_filter_enable(dev);
2178                 else
2179                         ixgbe_vlan_hw_filter_disable(dev);
2180         }
2181
2182         if (mask & ETH_VLAN_EXTEND_MASK) {
2183                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2184                         ixgbe_vlan_hw_extend_enable(dev);
2185                 else
2186                         ixgbe_vlan_hw_extend_disable(dev);
2187         }
2188
2189         return 0;
2190 }
2191
2192 static int
2193 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2194 {
2195         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2196
2197         ixgbe_vlan_offload_config(dev, mask);
2198
2199         return 0;
2200 }
2201
2202 static void
2203 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2204 {
2205         struct ixgbe_hw *hw =
2206                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2208         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2209
2210         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2211         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2212 }
2213
2214 static int
2215 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2216 {
2217         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2218
2219         switch (nb_rx_q) {
2220         case 1:
2221         case 2:
2222                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2223                 break;
2224         case 4:
2225                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2226                 break;
2227         default:
2228                 return -EINVAL;
2229         }
2230
2231         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2232                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2233         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2234                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2235         return 0;
2236 }
2237
2238 static int
2239 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2240 {
2241         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2243         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2244         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2245
2246         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2247                 /* check multi-queue mode */
2248                 switch (dev_conf->rxmode.mq_mode) {
2249                 case ETH_MQ_RX_VMDQ_DCB:
2250                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2251                         break;
2252                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2253                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2254                         PMD_INIT_LOG(ERR, "SRIOV active,"
2255                                         " unsupported mq_mode rx %d.",
2256                                         dev_conf->rxmode.mq_mode);
2257                         return -EINVAL;
2258                 case ETH_MQ_RX_RSS:
2259                 case ETH_MQ_RX_VMDQ_RSS:
2260                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2261                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2262                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2263                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2264                                                 " invalid queue number"
2265                                                 " for VMDQ RSS, allowed"
2266                                                 " value are 1, 2 or 4.");
2267                                         return -EINVAL;
2268                                 }
2269                         break;
2270                 case ETH_MQ_RX_VMDQ_ONLY:
2271                 case ETH_MQ_RX_NONE:
2272                         /* if nothing mq mode configure, use default scheme */
2273                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2274                         break;
2275                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2276                         /* SRIOV only works in VMDq enable mode */
2277                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2278                                         " wrong mq_mode rx %d.",
2279                                         dev_conf->rxmode.mq_mode);
2280                         return -EINVAL;
2281                 }
2282
2283                 switch (dev_conf->txmode.mq_mode) {
2284                 case ETH_MQ_TX_VMDQ_DCB:
2285                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2286                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2287                         break;
2288                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2289                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2290                         break;
2291                 }
2292
2293                 /* check valid queue number */
2294                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2295                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2296                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2297                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2298                                         " must be less than or equal to %d.",
2299                                         nb_rx_q, nb_tx_q,
2300                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2301                         return -EINVAL;
2302                 }
2303         } else {
2304                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2305                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2306                                           " not supported.");
2307                         return -EINVAL;
2308                 }
2309                 /* check configuration for vmdb+dcb mode */
2310                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2311                         const struct rte_eth_vmdq_dcb_conf *conf;
2312
2313                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2314                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2315                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2316                                 return -EINVAL;
2317                         }
2318                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2319                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2320                                conf->nb_queue_pools == ETH_32_POOLS)) {
2321                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2322                                                 " nb_queue_pools must be %d or %d.",
2323                                                 ETH_16_POOLS, ETH_32_POOLS);
2324                                 return -EINVAL;
2325                         }
2326                 }
2327                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2328                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2329
2330                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2331                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2332                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2333                                 return -EINVAL;
2334                         }
2335                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2336                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2337                                conf->nb_queue_pools == ETH_32_POOLS)) {
2338                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2339                                                 " nb_queue_pools != %d and"
2340                                                 " nb_queue_pools != %d.",
2341                                                 ETH_16_POOLS, ETH_32_POOLS);
2342                                 return -EINVAL;
2343                         }
2344                 }
2345
2346                 /* For DCB mode check our configuration before we go further */
2347                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2348                         const struct rte_eth_dcb_rx_conf *conf;
2349
2350                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2351                         if (!(conf->nb_tcs == ETH_4_TCS ||
2352                                conf->nb_tcs == ETH_8_TCS)) {
2353                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2354                                                 " and nb_tcs != %d.",
2355                                                 ETH_4_TCS, ETH_8_TCS);
2356                                 return -EINVAL;
2357                         }
2358                 }
2359
2360                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2361                         const struct rte_eth_dcb_tx_conf *conf;
2362
2363                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2364                         if (!(conf->nb_tcs == ETH_4_TCS ||
2365                                conf->nb_tcs == ETH_8_TCS)) {
2366                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2367                                                 " and nb_tcs != %d.",
2368                                                 ETH_4_TCS, ETH_8_TCS);
2369                                 return -EINVAL;
2370                         }
2371                 }
2372
2373                 /*
2374                  * When DCB/VT is off, maximum number of queues changes,
2375                  * except for 82598EB, which remains constant.
2376                  */
2377                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2378                                 hw->mac.type != ixgbe_mac_82598EB) {
2379                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2380                                 PMD_INIT_LOG(ERR,
2381                                              "Neither VT nor DCB are enabled, "
2382                                              "nb_tx_q > %d.",
2383                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2384                                 return -EINVAL;
2385                         }
2386                 }
2387         }
2388         return 0;
2389 }
2390
2391 static int
2392 ixgbe_dev_configure(struct rte_eth_dev *dev)
2393 {
2394         struct ixgbe_interrupt *intr =
2395                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2396         struct ixgbe_adapter *adapter =
2397                 (struct ixgbe_adapter *)dev->data->dev_private;
2398         int ret;
2399
2400         PMD_INIT_FUNC_TRACE();
2401         /* multipe queue mode checking */
2402         ret  = ixgbe_check_mq_mode(dev);
2403         if (ret != 0) {
2404                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2405                             ret);
2406                 return ret;
2407         }
2408
2409         /* set flag to update link status after init */
2410         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2411
2412         /*
2413          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2414          * allocation or vector Rx preconditions we will reset it.
2415          */
2416         adapter->rx_bulk_alloc_allowed = true;
2417         adapter->rx_vec_allowed = true;
2418
2419         return 0;
2420 }
2421
2422 static void
2423 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2424 {
2425         struct ixgbe_hw *hw =
2426                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427         struct ixgbe_interrupt *intr =
2428                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2429         uint32_t gpie;
2430
2431         /* only set up it on X550EM_X */
2432         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2433                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2434                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2435                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2436                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2437                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2438         }
2439 }
2440
2441 int
2442 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2443                         uint16_t tx_rate, uint64_t q_msk)
2444 {
2445         struct ixgbe_hw *hw;
2446         struct ixgbe_vf_info *vfinfo;
2447         struct rte_eth_link link;
2448         uint8_t  nb_q_per_pool;
2449         uint32_t queue_stride;
2450         uint32_t queue_idx, idx = 0, vf_idx;
2451         uint32_t queue_end;
2452         uint16_t total_rate = 0;
2453         struct rte_pci_device *pci_dev;
2454
2455         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2456         rte_eth_link_get_nowait(dev->data->port_id, &link);
2457
2458         if (vf >= pci_dev->max_vfs)
2459                 return -EINVAL;
2460
2461         if (tx_rate > link.link_speed)
2462                 return -EINVAL;
2463
2464         if (q_msk == 0)
2465                 return 0;
2466
2467         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2468         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2469         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2470         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2471         queue_idx = vf * queue_stride;
2472         queue_end = queue_idx + nb_q_per_pool - 1;
2473         if (queue_end >= hw->mac.max_tx_queues)
2474                 return -EINVAL;
2475
2476         if (vfinfo) {
2477                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2478                         if (vf_idx == vf)
2479                                 continue;
2480                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2481                                 idx++)
2482                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2483                 }
2484         } else {
2485                 return -EINVAL;
2486         }
2487
2488         /* Store tx_rate for this vf. */
2489         for (idx = 0; idx < nb_q_per_pool; idx++) {
2490                 if (((uint64_t)0x1 << idx) & q_msk) {
2491                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2492                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2493                         total_rate += tx_rate;
2494                 }
2495         }
2496
2497         if (total_rate > dev->data->dev_link.link_speed) {
2498                 /* Reset stored TX rate of the VF if it causes exceed
2499                  * link speed.
2500                  */
2501                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2502                 return -EINVAL;
2503         }
2504
2505         /* Set RTTBCNRC of each queue/pool for vf X  */
2506         for (; queue_idx <= queue_end; queue_idx++) {
2507                 if (0x1 & q_msk)
2508                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2509                 q_msk = q_msk >> 1;
2510         }
2511
2512         return 0;
2513 }
2514
2515 /*
2516  * Configure device link speed and setup link.
2517  * It returns 0 on success.
2518  */
2519 static int
2520 ixgbe_dev_start(struct rte_eth_dev *dev)
2521 {
2522         struct ixgbe_hw *hw =
2523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524         struct ixgbe_vf_info *vfinfo =
2525                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2526         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2527         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2528         uint32_t intr_vector = 0;
2529         int err, link_up = 0, negotiate = 0;
2530         uint32_t speed = 0;
2531         uint32_t allowed_speeds = 0;
2532         int mask = 0;
2533         int status;
2534         uint16_t vf, idx;
2535         uint32_t *link_speeds;
2536         struct ixgbe_tm_conf *tm_conf =
2537                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2538
2539         PMD_INIT_FUNC_TRACE();
2540
2541         /* IXGBE devices don't support:
2542         *    - half duplex (checked afterwards for valid speeds)
2543         *    - fixed speed: TODO implement
2544         */
2545         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2546                 PMD_INIT_LOG(ERR,
2547                 "Invalid link_speeds for port %u, fix speed not supported",
2548                                 dev->data->port_id);
2549                 return -EINVAL;
2550         }
2551
2552         /* Stop the link setup handler before resetting the HW. */
2553         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2554
2555         /* disable uio/vfio intr/eventfd mapping */
2556         rte_intr_disable(intr_handle);
2557
2558         /* stop adapter */
2559         hw->adapter_stopped = 0;
2560         ixgbe_stop_adapter(hw);
2561
2562         /* reinitialize adapter
2563          * this calls reset and start
2564          */
2565         status = ixgbe_pf_reset_hw(hw);
2566         if (status != 0)
2567                 return -1;
2568         hw->mac.ops.start_hw(hw);
2569         hw->mac.get_link_status = true;
2570
2571         /* configure PF module if SRIOV enabled */
2572         ixgbe_pf_host_configure(dev);
2573
2574         ixgbe_dev_phy_intr_setup(dev);
2575
2576         /* check and configure queue intr-vector mapping */
2577         if ((rte_intr_cap_multiple(intr_handle) ||
2578              !RTE_ETH_DEV_SRIOV(dev).active) &&
2579             dev->data->dev_conf.intr_conf.rxq != 0) {
2580                 intr_vector = dev->data->nb_rx_queues;
2581                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2582                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2583                                         IXGBE_MAX_INTR_QUEUE_NUM);
2584                         return -ENOTSUP;
2585                 }
2586                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2587                         return -1;
2588         }
2589
2590         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2591                 intr_handle->intr_vec =
2592                         rte_zmalloc("intr_vec",
2593                                     dev->data->nb_rx_queues * sizeof(int), 0);
2594                 if (intr_handle->intr_vec == NULL) {
2595                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2596                                      " intr_vec", dev->data->nb_rx_queues);
2597                         return -ENOMEM;
2598                 }
2599         }
2600
2601         /* confiugre msix for sleep until rx interrupt */
2602         ixgbe_configure_msix(dev);
2603
2604         /* initialize transmission unit */
2605         ixgbe_dev_tx_init(dev);
2606
2607         /* This can fail when allocating mbufs for descriptor rings */
2608         err = ixgbe_dev_rx_init(dev);
2609         if (err) {
2610                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2611                 goto error;
2612         }
2613
2614         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2615                 ETH_VLAN_EXTEND_MASK;
2616         err = ixgbe_vlan_offload_config(dev, mask);
2617         if (err) {
2618                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2619                 goto error;
2620         }
2621
2622         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2623                 /* Enable vlan filtering for VMDq */
2624                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2625         }
2626
2627         /* Configure DCB hw */
2628         ixgbe_configure_dcb(dev);
2629
2630         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2631                 err = ixgbe_fdir_configure(dev);
2632                 if (err)
2633                         goto error;
2634         }
2635
2636         /* Restore vf rate limit */
2637         if (vfinfo != NULL) {
2638                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2639                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2640                                 if (vfinfo[vf].tx_rate[idx] != 0)
2641                                         ixgbe_set_vf_rate_limit(
2642                                                 dev, vf,
2643                                                 vfinfo[vf].tx_rate[idx],
2644                                                 1 << idx);
2645         }
2646
2647         ixgbe_restore_statistics_mapping(dev);
2648
2649         err = ixgbe_dev_rxtx_start(dev);
2650         if (err < 0) {
2651                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2652                 goto error;
2653         }
2654
2655         /* Skip link setup if loopback mode is enabled for 82599. */
2656         if (hw->mac.type == ixgbe_mac_82599EB &&
2657                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2658                 goto skip_link_setup;
2659
2660         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2661                 err = hw->mac.ops.setup_sfp(hw);
2662                 if (err)
2663                         goto error;
2664         }
2665
2666         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2667                 /* Turn on the copper */
2668                 ixgbe_set_phy_power(hw, true);
2669         } else {
2670                 /* Turn on the laser */
2671                 ixgbe_enable_tx_laser(hw);
2672         }
2673
2674         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2675         if (err)
2676                 goto error;
2677         dev->data->dev_link.link_status = link_up;
2678
2679         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2680         if (err)
2681                 goto error;
2682
2683         switch (hw->mac.type) {
2684         case ixgbe_mac_X550:
2685         case ixgbe_mac_X550EM_x:
2686         case ixgbe_mac_X550EM_a:
2687                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2688                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2689                         ETH_LINK_SPEED_10G;
2690                 break;
2691         default:
2692                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2693                         ETH_LINK_SPEED_10G;
2694         }
2695
2696         link_speeds = &dev->data->dev_conf.link_speeds;
2697         if (*link_speeds & ~allowed_speeds) {
2698                 PMD_INIT_LOG(ERR, "Invalid link setting");
2699                 goto error;
2700         }
2701
2702         speed = 0x0;
2703         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2704                 switch (hw->mac.type) {
2705                 case ixgbe_mac_82598EB:
2706                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2707                         break;
2708                 case ixgbe_mac_82599EB:
2709                 case ixgbe_mac_X540:
2710                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2711                         break;
2712                 case ixgbe_mac_X550:
2713                 case ixgbe_mac_X550EM_x:
2714                 case ixgbe_mac_X550EM_a:
2715                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2716                         break;
2717                 default:
2718                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2719                 }
2720         } else {
2721                 if (*link_speeds & ETH_LINK_SPEED_10G)
2722                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2723                 if (*link_speeds & ETH_LINK_SPEED_5G)
2724                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2725                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2726                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2727                 if (*link_speeds & ETH_LINK_SPEED_1G)
2728                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2729                 if (*link_speeds & ETH_LINK_SPEED_100M)
2730                         speed |= IXGBE_LINK_SPEED_100_FULL;
2731         }
2732
2733         err = ixgbe_setup_link(hw, speed, link_up);
2734         if (err)
2735                 goto error;
2736
2737 skip_link_setup:
2738
2739         if (rte_intr_allow_others(intr_handle)) {
2740                 /* check if lsc interrupt is enabled */
2741                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2742                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2743                 else
2744                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2745                 ixgbe_dev_macsec_interrupt_setup(dev);
2746         } else {
2747                 rte_intr_callback_unregister(intr_handle,
2748                                              ixgbe_dev_interrupt_handler, dev);
2749                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2750                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2751                                      " no intr multiplex");
2752         }
2753
2754         /* check if rxq interrupt is enabled */
2755         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2756             rte_intr_dp_is_en(intr_handle))
2757                 ixgbe_dev_rxq_interrupt_setup(dev);
2758
2759         /* enable uio/vfio intr/eventfd mapping */
2760         rte_intr_enable(intr_handle);
2761
2762         /* resume enabled intr since hw reset */
2763         ixgbe_enable_intr(dev);
2764         ixgbe_l2_tunnel_conf(dev);
2765         ixgbe_filter_restore(dev);
2766
2767         if (tm_conf->root && !tm_conf->committed)
2768                 PMD_DRV_LOG(WARNING,
2769                             "please call hierarchy_commit() "
2770                             "before starting the port");
2771
2772         /*
2773          * Update link status right before return, because it may
2774          * start link configuration process in a separate thread.
2775          */
2776         ixgbe_dev_link_update(dev, 0);
2777
2778         return 0;
2779
2780 error:
2781         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2782         ixgbe_dev_clear_queues(dev);
2783         return -EIO;
2784 }
2785
2786 /*
2787  * Stop device: disable rx and tx functions to allow for reconfiguring.
2788  */
2789 static void
2790 ixgbe_dev_stop(struct rte_eth_dev *dev)
2791 {
2792         struct rte_eth_link link;
2793         struct ixgbe_adapter *adapter =
2794                 (struct ixgbe_adapter *)dev->data->dev_private;
2795         struct ixgbe_hw *hw =
2796                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2797         struct ixgbe_vf_info *vfinfo =
2798                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2799         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2800         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2801         int vf;
2802         struct ixgbe_tm_conf *tm_conf =
2803                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2804
2805         PMD_INIT_FUNC_TRACE();
2806
2807         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2808
2809         /* disable interrupts */
2810         ixgbe_disable_intr(hw);
2811
2812         /* reset the NIC */
2813         ixgbe_pf_reset_hw(hw);
2814         hw->adapter_stopped = 0;
2815
2816         /* stop adapter */
2817         ixgbe_stop_adapter(hw);
2818
2819         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2820                 vfinfo[vf].clear_to_send = false;
2821
2822         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2823                 /* Turn off the copper */
2824                 ixgbe_set_phy_power(hw, false);
2825         } else {
2826                 /* Turn off the laser */
2827                 ixgbe_disable_tx_laser(hw);
2828         }
2829
2830         ixgbe_dev_clear_queues(dev);
2831
2832         /* Clear stored conf */
2833         dev->data->scattered_rx = 0;
2834         dev->data->lro = 0;
2835
2836         /* Clear recorded link status */
2837         memset(&link, 0, sizeof(link));
2838         rte_eth_linkstatus_set(dev, &link);
2839
2840         if (!rte_intr_allow_others(intr_handle))
2841                 /* resume to the default handler */
2842                 rte_intr_callback_register(intr_handle,
2843                                            ixgbe_dev_interrupt_handler,
2844                                            (void *)dev);
2845
2846         /* Clean datapath event and queue/vec mapping */
2847         rte_intr_efd_disable(intr_handle);
2848         if (intr_handle->intr_vec != NULL) {
2849                 rte_free(intr_handle->intr_vec);
2850                 intr_handle->intr_vec = NULL;
2851         }
2852
2853         /* reset hierarchy commit */
2854         tm_conf->committed = false;
2855
2856         adapter->rss_reta_updated = 0;
2857 }
2858
2859 /*
2860  * Set device link up: enable tx.
2861  */
2862 static int
2863 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2864 {
2865         struct ixgbe_hw *hw =
2866                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2867         if (hw->mac.type == ixgbe_mac_82599EB) {
2868 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2869                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2870                         /* Not suported in bypass mode */
2871                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2872                                      "by device id 0x%x", hw->device_id);
2873                         return -ENOTSUP;
2874                 }
2875 #endif
2876         }
2877
2878         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2879                 /* Turn on the copper */
2880                 ixgbe_set_phy_power(hw, true);
2881         } else {
2882                 /* Turn on the laser */
2883                 ixgbe_enable_tx_laser(hw);
2884         }
2885
2886         return 0;
2887 }
2888
2889 /*
2890  * Set device link down: disable tx.
2891  */
2892 static int
2893 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2894 {
2895         struct ixgbe_hw *hw =
2896                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897         if (hw->mac.type == ixgbe_mac_82599EB) {
2898 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2899                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2900                         /* Not suported in bypass mode */
2901                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2902                                      "by device id 0x%x", hw->device_id);
2903                         return -ENOTSUP;
2904                 }
2905 #endif
2906         }
2907
2908         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2909                 /* Turn off the copper */
2910                 ixgbe_set_phy_power(hw, false);
2911         } else {
2912                 /* Turn off the laser */
2913                 ixgbe_disable_tx_laser(hw);
2914         }
2915
2916         return 0;
2917 }
2918
2919 /*
2920  * Reset and stop device.
2921  */
2922 static void
2923 ixgbe_dev_close(struct rte_eth_dev *dev)
2924 {
2925         struct ixgbe_hw *hw =
2926                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2927
2928         PMD_INIT_FUNC_TRACE();
2929
2930         ixgbe_pf_reset_hw(hw);
2931
2932         ixgbe_dev_stop(dev);
2933         hw->adapter_stopped = 1;
2934
2935         ixgbe_dev_free_queues(dev);
2936
2937         ixgbe_disable_pcie_master(hw);
2938
2939         /* reprogram the RAR[0] in case user changed it. */
2940         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2941 }
2942
2943 /*
2944  * Reset PF device.
2945  */
2946 static int
2947 ixgbe_dev_reset(struct rte_eth_dev *dev)
2948 {
2949         int ret;
2950
2951         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2952          * its VF to make them align with it. The detailed notification
2953          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2954          * To avoid unexpected behavior in VF, currently reset of PF with
2955          * SR-IOV activation is not supported. It might be supported later.
2956          */
2957         if (dev->data->sriov.active)
2958                 return -ENOTSUP;
2959
2960         ret = eth_ixgbe_dev_uninit(dev);
2961         if (ret)
2962                 return ret;
2963
2964         ret = eth_ixgbe_dev_init(dev, NULL);
2965
2966         return ret;
2967 }
2968
2969 static void
2970 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2971                            struct ixgbe_hw_stats *hw_stats,
2972                            struct ixgbe_macsec_stats *macsec_stats,
2973                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2974                            uint64_t *total_qprc, uint64_t *total_qprdc)
2975 {
2976         uint32_t bprc, lxon, lxoff, total;
2977         uint32_t delta_gprc = 0;
2978         unsigned i;
2979         /* Workaround for RX byte count not including CRC bytes when CRC
2980          * strip is enabled. CRC bytes are removed from counters when crc_strip
2981          * is disabled.
2982          */
2983         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2984                         IXGBE_HLREG0_RXCRCSTRP);
2985
2986         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2987         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2988         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2989         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2990
2991         for (i = 0; i < 8; i++) {
2992                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2993
2994                 /* global total per queue */
2995                 hw_stats->mpc[i] += mp;
2996                 /* Running comprehensive total for stats display */
2997                 *total_missed_rx += hw_stats->mpc[i];
2998                 if (hw->mac.type == ixgbe_mac_82598EB) {
2999                         hw_stats->rnbc[i] +=
3000                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3001                         hw_stats->pxonrxc[i] +=
3002                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3003                         hw_stats->pxoffrxc[i] +=
3004                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3005                 } else {
3006                         hw_stats->pxonrxc[i] +=
3007                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3008                         hw_stats->pxoffrxc[i] +=
3009                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3010                         hw_stats->pxon2offc[i] +=
3011                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3012                 }
3013                 hw_stats->pxontxc[i] +=
3014                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3015                 hw_stats->pxofftxc[i] +=
3016                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3017         }
3018         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3019                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3020                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3021                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3022
3023                 delta_gprc += delta_qprc;
3024
3025                 hw_stats->qprc[i] += delta_qprc;
3026                 hw_stats->qptc[i] += delta_qptc;
3027
3028                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3029                 hw_stats->qbrc[i] +=
3030                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3031                 if (crc_strip == 0)
3032                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3033
3034                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3035                 hw_stats->qbtc[i] +=
3036                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3037
3038                 hw_stats->qprdc[i] += delta_qprdc;
3039                 *total_qprdc += hw_stats->qprdc[i];
3040
3041                 *total_qprc += hw_stats->qprc[i];
3042                 *total_qbrc += hw_stats->qbrc[i];
3043         }
3044         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3045         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3046         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3047
3048         /*
3049          * An errata states that gprc actually counts good + missed packets:
3050          * Workaround to set gprc to summated queue packet receives
3051          */
3052         hw_stats->gprc = *total_qprc;
3053
3054         if (hw->mac.type != ixgbe_mac_82598EB) {
3055                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3056                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3057                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3058                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3059                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3060                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3061                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3062                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3063         } else {
3064                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3065                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3066                 /* 82598 only has a counter in the high register */
3067                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3068                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3069                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3070         }
3071         uint64_t old_tpr = hw_stats->tpr;
3072
3073         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3074         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3075
3076         if (crc_strip == 0)
3077                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3078
3079         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3080         hw_stats->gptc += delta_gptc;
3081         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3082         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3083
3084         /*
3085          * Workaround: mprc hardware is incorrectly counting
3086          * broadcasts, so for now we subtract those.
3087          */
3088         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3089         hw_stats->bprc += bprc;
3090         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3091         if (hw->mac.type == ixgbe_mac_82598EB)
3092                 hw_stats->mprc -= bprc;
3093
3094         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3095         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3096         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3097         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3098         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3099         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3100
3101         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3102         hw_stats->lxontxc += lxon;
3103         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3104         hw_stats->lxofftxc += lxoff;
3105         total = lxon + lxoff;
3106
3107         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3108         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3109         hw_stats->gptc -= total;
3110         hw_stats->mptc -= total;
3111         hw_stats->ptc64 -= total;
3112         hw_stats->gotc -= total * ETHER_MIN_LEN;
3113
3114         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3115         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3116         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3117         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3118         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3119         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3120         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3121         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3122         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3123         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3124         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3125         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3126         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3127         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3128         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3129         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3130         /* Only read FCOE on 82599 */
3131         if (hw->mac.type != ixgbe_mac_82598EB) {
3132                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3133                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3134                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3135                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3136                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3137         }
3138
3139         /* Flow Director Stats registers */
3140         if (hw->mac.type != ixgbe_mac_82598EB) {
3141                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3142                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3143                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3144                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3145                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3146                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3147                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3148                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3149                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3150                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3151         }
3152         /* MACsec Stats registers */
3153         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3154         macsec_stats->out_pkts_encrypted +=
3155                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3156         macsec_stats->out_pkts_protected +=
3157                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3158         macsec_stats->out_octets_encrypted +=
3159                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3160         macsec_stats->out_octets_protected +=
3161                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3162         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3163         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3164         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3165         macsec_stats->in_pkts_unknownsci +=
3166                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3167         macsec_stats->in_octets_decrypted +=
3168                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3169         macsec_stats->in_octets_validated +=
3170                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3171         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3172         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3173         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3174         for (i = 0; i < 2; i++) {
3175                 macsec_stats->in_pkts_ok +=
3176                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3177                 macsec_stats->in_pkts_invalid +=
3178                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3179                 macsec_stats->in_pkts_notvalid +=
3180                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3181         }
3182         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3183         macsec_stats->in_pkts_notusingsa +=
3184                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3185 }
3186
3187 /*
3188  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3189  */
3190 static int
3191 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3192 {
3193         struct ixgbe_hw *hw =
3194                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3195         struct ixgbe_hw_stats *hw_stats =
3196                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3197         struct ixgbe_macsec_stats *macsec_stats =
3198                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3199                                 dev->data->dev_private);
3200         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3201         unsigned i;
3202
3203         total_missed_rx = 0;
3204         total_qbrc = 0;
3205         total_qprc = 0;
3206         total_qprdc = 0;
3207
3208         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3209                         &total_qbrc, &total_qprc, &total_qprdc);
3210
3211         if (stats == NULL)
3212                 return -EINVAL;
3213
3214         /* Fill out the rte_eth_stats statistics structure */
3215         stats->ipackets = total_qprc;
3216         stats->ibytes = total_qbrc;
3217         stats->opackets = hw_stats->gptc;
3218         stats->obytes = hw_stats->gotc;
3219
3220         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3221                 stats->q_ipackets[i] = hw_stats->qprc[i];
3222                 stats->q_opackets[i] = hw_stats->qptc[i];
3223                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3224                 stats->q_obytes[i] = hw_stats->qbtc[i];
3225                 stats->q_errors[i] = hw_stats->qprdc[i];
3226         }
3227
3228         /* Rx Errors */
3229         stats->imissed  = total_missed_rx;
3230         stats->ierrors  = hw_stats->crcerrs +
3231                           hw_stats->mspdc +
3232                           hw_stats->rlec +
3233                           hw_stats->ruc +
3234                           hw_stats->roc +
3235                           hw_stats->illerrc +
3236                           hw_stats->errbc +
3237                           hw_stats->rfc +
3238                           hw_stats->fccrc +
3239                           hw_stats->fclast;
3240
3241         /* Tx Errors */
3242         stats->oerrors  = 0;
3243         return 0;
3244 }
3245
3246 static void
3247 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3248 {
3249         struct ixgbe_hw_stats *stats =
3250                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3251
3252         /* HW registers are cleared on read */
3253         ixgbe_dev_stats_get(dev, NULL);
3254
3255         /* Reset software totals */
3256         memset(stats, 0, sizeof(*stats));
3257 }
3258
3259 /* This function calculates the number of xstats based on the current config */
3260 static unsigned
3261 ixgbe_xstats_calc_num(void) {
3262         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3263                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3264                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3265 }
3266
3267 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3268         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3269 {
3270         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3271         unsigned stat, i, count;
3272
3273         if (xstats_names != NULL) {
3274                 count = 0;
3275
3276                 /* Note: limit >= cnt_stats checked upstream
3277                  * in rte_eth_xstats_names()
3278                  */
3279
3280                 /* Extended stats from ixgbe_hw_stats */
3281                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3282                         snprintf(xstats_names[count].name,
3283                                 sizeof(xstats_names[count].name),
3284                                 "%s",
3285                                 rte_ixgbe_stats_strings[i].name);
3286                         count++;
3287                 }
3288
3289                 /* MACsec Stats */
3290                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3291                         snprintf(xstats_names[count].name,
3292                                 sizeof(xstats_names[count].name),
3293                                 "%s",
3294                                 rte_ixgbe_macsec_strings[i].name);
3295                         count++;
3296                 }
3297
3298                 /* RX Priority Stats */
3299                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3300                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3301                                 snprintf(xstats_names[count].name,
3302                                         sizeof(xstats_names[count].name),
3303                                         "rx_priority%u_%s", i,
3304                                         rte_ixgbe_rxq_strings[stat].name);
3305                                 count++;
3306                         }
3307                 }
3308
3309                 /* TX Priority Stats */
3310                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3311                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3312                                 snprintf(xstats_names[count].name,
3313                                         sizeof(xstats_names[count].name),
3314                                         "tx_priority%u_%s", i,
3315                                         rte_ixgbe_txq_strings[stat].name);
3316                                 count++;
3317                         }
3318                 }
3319         }
3320         return cnt_stats;
3321 }
3322
3323 static int ixgbe_dev_xstats_get_names_by_id(
3324         struct rte_eth_dev *dev,
3325         struct rte_eth_xstat_name *xstats_names,
3326         const uint64_t *ids,
3327         unsigned int limit)
3328 {
3329         if (!ids) {
3330                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3331                 unsigned int stat, i, count;
3332
3333                 if (xstats_names != NULL) {
3334                         count = 0;
3335
3336                         /* Note: limit >= cnt_stats checked upstream
3337                          * in rte_eth_xstats_names()
3338                          */
3339
3340                         /* Extended stats from ixgbe_hw_stats */
3341                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3342                                 snprintf(xstats_names[count].name,
3343                                         sizeof(xstats_names[count].name),
3344                                         "%s",
3345                                         rte_ixgbe_stats_strings[i].name);
3346                                 count++;
3347                         }
3348
3349                         /* MACsec Stats */
3350                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3351                                 snprintf(xstats_names[count].name,
3352                                         sizeof(xstats_names[count].name),
3353                                         "%s",
3354                                         rte_ixgbe_macsec_strings[i].name);
3355                                 count++;
3356                         }
3357
3358                         /* RX Priority Stats */
3359                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3360                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3361                                         snprintf(xstats_names[count].name,
3362                                             sizeof(xstats_names[count].name),
3363                                             "rx_priority%u_%s", i,
3364                                             rte_ixgbe_rxq_strings[stat].name);
3365                                         count++;
3366                                 }
3367                         }
3368
3369                         /* TX Priority Stats */
3370                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3371                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3372                                         snprintf(xstats_names[count].name,
3373                                             sizeof(xstats_names[count].name),
3374                                             "tx_priority%u_%s", i,
3375                                             rte_ixgbe_txq_strings[stat].name);
3376                                         count++;
3377                                 }
3378                         }
3379                 }
3380                 return cnt_stats;
3381         }
3382
3383         uint16_t i;
3384         uint16_t size = ixgbe_xstats_calc_num();
3385         struct rte_eth_xstat_name xstats_names_copy[size];
3386
3387         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3388                         size);
3389
3390         for (i = 0; i < limit; i++) {
3391                 if (ids[i] >= size) {
3392                         PMD_INIT_LOG(ERR, "id value isn't valid");
3393                         return -1;
3394                 }
3395                 strcpy(xstats_names[i].name,
3396                                 xstats_names_copy[ids[i]].name);
3397         }
3398         return limit;
3399 }
3400
3401 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3402         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3403 {
3404         unsigned i;
3405
3406         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3407                 return -ENOMEM;
3408
3409         if (xstats_names != NULL)
3410                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3411                         snprintf(xstats_names[i].name,
3412                                 sizeof(xstats_names[i].name),
3413                                 "%s", rte_ixgbevf_stats_strings[i].name);
3414         return IXGBEVF_NB_XSTATS;
3415 }
3416
3417 static int
3418 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3419                                          unsigned n)
3420 {
3421         struct ixgbe_hw *hw =
3422                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3423         struct ixgbe_hw_stats *hw_stats =
3424                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3425         struct ixgbe_macsec_stats *macsec_stats =
3426                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3427                                 dev->data->dev_private);
3428         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3429         unsigned i, stat, count = 0;
3430
3431         count = ixgbe_xstats_calc_num();
3432
3433         if (n < count)
3434                 return count;
3435
3436         total_missed_rx = 0;
3437         total_qbrc = 0;
3438         total_qprc = 0;
3439         total_qprdc = 0;
3440
3441         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3442                         &total_qbrc, &total_qprc, &total_qprdc);
3443
3444         /* If this is a reset xstats is NULL, and we have cleared the
3445          * registers by reading them.
3446          */
3447         if (!xstats)
3448                 return 0;
3449
3450         /* Extended stats from ixgbe_hw_stats */
3451         count = 0;
3452         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3453                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3454                                 rte_ixgbe_stats_strings[i].offset);
3455                 xstats[count].id = count;
3456                 count++;
3457         }
3458
3459         /* MACsec Stats */
3460         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3461                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3462                                 rte_ixgbe_macsec_strings[i].offset);
3463                 xstats[count].id = count;
3464                 count++;
3465         }
3466
3467         /* RX Priority Stats */
3468         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3469                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3470                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3471                                         rte_ixgbe_rxq_strings[stat].offset +
3472                                         (sizeof(uint64_t) * i));
3473                         xstats[count].id = count;
3474                         count++;
3475                 }
3476         }
3477
3478         /* TX Priority Stats */
3479         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3480                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3481                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3482                                         rte_ixgbe_txq_strings[stat].offset +
3483                                         (sizeof(uint64_t) * i));
3484                         xstats[count].id = count;
3485                         count++;
3486                 }
3487         }
3488         return count;
3489 }
3490
3491 static int
3492 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3493                 uint64_t *values, unsigned int n)
3494 {
3495         if (!ids) {
3496                 struct ixgbe_hw *hw =
3497                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3498                 struct ixgbe_hw_stats *hw_stats =
3499                                 IXGBE_DEV_PRIVATE_TO_STATS(
3500                                                 dev->data->dev_private);
3501                 struct ixgbe_macsec_stats *macsec_stats =
3502                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3503                                         dev->data->dev_private);
3504                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3505                 unsigned int i, stat, count = 0;
3506
3507                 count = ixgbe_xstats_calc_num();
3508
3509                 if (!ids && n < count)
3510                         return count;
3511
3512                 total_missed_rx = 0;
3513                 total_qbrc = 0;
3514                 total_qprc = 0;
3515                 total_qprdc = 0;
3516
3517                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3518                                 &total_missed_rx, &total_qbrc, &total_qprc,
3519                                 &total_qprdc);
3520
3521                 /* If this is a reset xstats is NULL, and we have cleared the
3522                  * registers by reading them.
3523                  */
3524                 if (!ids && !values)
3525                         return 0;
3526
3527                 /* Extended stats from ixgbe_hw_stats */
3528                 count = 0;
3529                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3530                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3531                                         rte_ixgbe_stats_strings[i].offset);
3532                         count++;
3533                 }
3534
3535                 /* MACsec Stats */
3536                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3537                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3538                                         rte_ixgbe_macsec_strings[i].offset);
3539                         count++;
3540                 }
3541
3542                 /* RX Priority Stats */
3543                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3544                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3545                                 values[count] =
3546                                         *(uint64_t *)(((char *)hw_stats) +
3547                                         rte_ixgbe_rxq_strings[stat].offset +
3548                                         (sizeof(uint64_t) * i));
3549                                 count++;
3550                         }
3551                 }
3552
3553                 /* TX Priority Stats */
3554                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3555                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3556                                 values[count] =
3557                                         *(uint64_t *)(((char *)hw_stats) +
3558                                         rte_ixgbe_txq_strings[stat].offset +
3559                                         (sizeof(uint64_t) * i));
3560                                 count++;
3561                         }
3562                 }
3563                 return count;
3564         }
3565
3566         uint16_t i;
3567         uint16_t size = ixgbe_xstats_calc_num();
3568         uint64_t values_copy[size];
3569
3570         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3571
3572         for (i = 0; i < n; i++) {
3573                 if (ids[i] >= size) {
3574                         PMD_INIT_LOG(ERR, "id value isn't valid");
3575                         return -1;
3576                 }
3577                 values[i] = values_copy[ids[i]];
3578         }
3579         return n;
3580 }
3581
3582 static void
3583 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3584 {
3585         struct ixgbe_hw_stats *stats =
3586                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3587         struct ixgbe_macsec_stats *macsec_stats =
3588                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3589                                 dev->data->dev_private);
3590
3591         unsigned count = ixgbe_xstats_calc_num();
3592
3593         /* HW registers are cleared on read */
3594         ixgbe_dev_xstats_get(dev, NULL, count);
3595
3596         /* Reset software totals */
3597         memset(stats, 0, sizeof(*stats));
3598         memset(macsec_stats, 0, sizeof(*macsec_stats));
3599 }
3600
3601 static void
3602 ixgbevf_update_stats(struct rte_eth_dev *dev)
3603 {
3604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3606                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3607
3608         /* Good Rx packet, include VF loopback */
3609         UPDATE_VF_STAT(IXGBE_VFGPRC,
3610             hw_stats->last_vfgprc, hw_stats->vfgprc);
3611
3612         /* Good Rx octets, include VF loopback */
3613         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3614             hw_stats->last_vfgorc, hw_stats->vfgorc);
3615
3616         /* Good Tx packet, include VF loopback */
3617         UPDATE_VF_STAT(IXGBE_VFGPTC,
3618             hw_stats->last_vfgptc, hw_stats->vfgptc);
3619
3620         /* Good Tx octets, include VF loopback */
3621         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3622             hw_stats->last_vfgotc, hw_stats->vfgotc);
3623
3624         /* Rx Multicst Packet */
3625         UPDATE_VF_STAT(IXGBE_VFMPRC,
3626             hw_stats->last_vfmprc, hw_stats->vfmprc);
3627 }
3628
3629 static int
3630 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3631                        unsigned n)
3632 {
3633         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3634                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3635         unsigned i;
3636
3637         if (n < IXGBEVF_NB_XSTATS)
3638                 return IXGBEVF_NB_XSTATS;
3639
3640         ixgbevf_update_stats(dev);
3641
3642         if (!xstats)
3643                 return 0;
3644
3645         /* Extended stats */
3646         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3647                 xstats[i].id = i;
3648                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3649                         rte_ixgbevf_stats_strings[i].offset);
3650         }
3651
3652         return IXGBEVF_NB_XSTATS;
3653 }
3654
3655 static int
3656 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3657 {
3658         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3659                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3660
3661         ixgbevf_update_stats(dev);
3662
3663         if (stats == NULL)
3664                 return -EINVAL;
3665
3666         stats->ipackets = hw_stats->vfgprc;
3667         stats->ibytes = hw_stats->vfgorc;
3668         stats->opackets = hw_stats->vfgptc;
3669         stats->obytes = hw_stats->vfgotc;
3670         return 0;
3671 }
3672
3673 static void
3674 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3675 {
3676         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3677                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3678
3679         /* Sync HW register to the last stats */
3680         ixgbevf_dev_stats_get(dev, NULL);
3681
3682         /* reset HW current stats*/
3683         hw_stats->vfgprc = 0;
3684         hw_stats->vfgorc = 0;
3685         hw_stats->vfgptc = 0;
3686         hw_stats->vfgotc = 0;
3687 }
3688
3689 static int
3690 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3691 {
3692         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3693         u16 eeprom_verh, eeprom_verl;
3694         u32 etrack_id;
3695         int ret;
3696
3697         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3698         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3699
3700         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3701         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3702
3703         ret += 1; /* add the size of '\0' */
3704         if (fw_size < (u32)ret)
3705                 return ret;
3706         else
3707                 return 0;
3708 }
3709
3710 static void
3711 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3712 {
3713         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3714         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3715         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3716
3717         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3718         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3719         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3720                 /*
3721                  * When DCB/VT is off, maximum number of queues changes,
3722                  * except for 82598EB, which remains constant.
3723                  */
3724                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3725                                 hw->mac.type != ixgbe_mac_82598EB)
3726                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3727         }
3728         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3729         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3730         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3731         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3732         dev_info->max_vfs = pci_dev->max_vfs;
3733         if (hw->mac.type == ixgbe_mac_82598EB)
3734                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3735         else
3736                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3737         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3738         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3739         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3740                                      dev_info->rx_queue_offload_capa);
3741         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3742         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3743
3744         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3745                 .rx_thresh = {
3746                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3747                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3748                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3749                 },
3750                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3751                 .rx_drop_en = 0,
3752                 .offloads = 0,
3753         };
3754
3755         dev_info->default_txconf = (struct rte_eth_txconf) {
3756                 .tx_thresh = {
3757                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3758                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3759                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3760                 },
3761                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3762                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3763                 .offloads = 0,
3764         };
3765
3766         dev_info->rx_desc_lim = rx_desc_lim;
3767         dev_info->tx_desc_lim = tx_desc_lim;
3768
3769         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3770         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3771         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3772
3773         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3774         if (hw->mac.type == ixgbe_mac_X540 ||
3775             hw->mac.type == ixgbe_mac_X540_vf ||
3776             hw->mac.type == ixgbe_mac_X550 ||
3777             hw->mac.type == ixgbe_mac_X550_vf) {
3778                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3779         }
3780         if (hw->mac.type == ixgbe_mac_X550) {
3781                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3782                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3783         }
3784
3785         /* Driver-preferred Rx/Tx parameters */
3786         dev_info->default_rxportconf.burst_size = 32;
3787         dev_info->default_txportconf.burst_size = 32;
3788         dev_info->default_rxportconf.nb_queues = 1;
3789         dev_info->default_txportconf.nb_queues = 1;
3790         dev_info->default_rxportconf.ring_size = 256;
3791         dev_info->default_txportconf.ring_size = 256;
3792 }
3793
3794 static const uint32_t *
3795 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3796 {
3797         static const uint32_t ptypes[] = {
3798                 /* For non-vec functions,
3799                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3800                  * for vec functions,
3801                  * refers to _recv_raw_pkts_vec().
3802                  */
3803                 RTE_PTYPE_L2_ETHER,
3804                 RTE_PTYPE_L3_IPV4,
3805                 RTE_PTYPE_L3_IPV4_EXT,
3806                 RTE_PTYPE_L3_IPV6,
3807                 RTE_PTYPE_L3_IPV6_EXT,
3808                 RTE_PTYPE_L4_SCTP,
3809                 RTE_PTYPE_L4_TCP,
3810                 RTE_PTYPE_L4_UDP,
3811                 RTE_PTYPE_TUNNEL_IP,
3812                 RTE_PTYPE_INNER_L3_IPV6,
3813                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3814                 RTE_PTYPE_INNER_L4_TCP,
3815                 RTE_PTYPE_INNER_L4_UDP,
3816                 RTE_PTYPE_UNKNOWN
3817         };
3818
3819         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3820             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3821             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3822             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3823                 return ptypes;
3824
3825 #if defined(RTE_ARCH_X86)
3826         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3827             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3828                 return ptypes;
3829 #endif
3830         return NULL;
3831 }
3832
3833 static void
3834 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3835                      struct rte_eth_dev_info *dev_info)
3836 {
3837         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3839
3840         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3841         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3842         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3843         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3844         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3845         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3846         dev_info->max_vfs = pci_dev->max_vfs;
3847         if (hw->mac.type == ixgbe_mac_82598EB)
3848                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3849         else
3850                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3851         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3852         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3853                                      dev_info->rx_queue_offload_capa);
3854         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3855         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3856
3857         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3858                 .rx_thresh = {
3859                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3860                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3861                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3862                 },
3863                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3864                 .rx_drop_en = 0,
3865                 .offloads = 0,
3866         };
3867
3868         dev_info->default_txconf = (struct rte_eth_txconf) {
3869                 .tx_thresh = {
3870                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3871                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3872                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3873                 },
3874                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3875                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3876                 .offloads = 0,
3877         };
3878
3879         dev_info->rx_desc_lim = rx_desc_lim;
3880         dev_info->tx_desc_lim = tx_desc_lim;
3881 }
3882
3883 static int
3884 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3885                    int *link_up, int wait_to_complete)
3886 {
3887         struct ixgbe_mbx_info *mbx = &hw->mbx;
3888         struct ixgbe_mac_info *mac = &hw->mac;
3889         uint32_t links_reg, in_msg;
3890         int ret_val = 0;
3891
3892         /* If we were hit with a reset drop the link */
3893         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3894                 mac->get_link_status = true;
3895
3896         if (!mac->get_link_status)
3897                 goto out;
3898
3899         /* if link status is down no point in checking to see if pf is up */
3900         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3901         if (!(links_reg & IXGBE_LINKS_UP))
3902                 goto out;
3903
3904         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3905          * before the link status is correct
3906          */
3907         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3908                 int i;
3909
3910                 for (i = 0; i < 5; i++) {
3911                         rte_delay_us(100);
3912                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3913
3914                         if (!(links_reg & IXGBE_LINKS_UP))
3915                                 goto out;
3916                 }
3917         }
3918
3919         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3920         case IXGBE_LINKS_SPEED_10G_82599:
3921                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3922                 if (hw->mac.type >= ixgbe_mac_X550) {
3923                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3924                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3925                 }
3926                 break;
3927         case IXGBE_LINKS_SPEED_1G_82599:
3928                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3929                 break;
3930         case IXGBE_LINKS_SPEED_100_82599:
3931                 *speed = IXGBE_LINK_SPEED_100_FULL;
3932                 if (hw->mac.type == ixgbe_mac_X550) {
3933                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3934                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3935                 }
3936                 break;
3937         case IXGBE_LINKS_SPEED_10_X550EM_A:
3938                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3939                 /* Since Reserved in older MAC's */
3940                 if (hw->mac.type >= ixgbe_mac_X550)
3941                         *speed = IXGBE_LINK_SPEED_10_FULL;
3942                 break;
3943         default:
3944                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3945         }
3946
3947         /* if the read failed it could just be a mailbox collision, best wait
3948          * until we are called again and don't report an error
3949          */
3950         if (mbx->ops.read(hw, &in_msg, 1, 0))
3951                 goto out;
3952
3953         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3954                 /* msg is not CTS and is NACK we must have lost CTS status */
3955                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3956                         mac->get_link_status = false;
3957                 goto out;
3958         }
3959
3960         /* the pf is talking, if we timed out in the past we reinit */
3961         if (!mbx->timeout) {
3962                 ret_val = -1;
3963                 goto out;
3964         }
3965
3966         /* if we passed all the tests above then the link is up and we no
3967          * longer need to check for link
3968          */
3969         mac->get_link_status = false;
3970
3971 out:
3972         *link_up = !mac->get_link_status;
3973         return ret_val;
3974 }
3975
3976 static void
3977 ixgbe_dev_setup_link_alarm_handler(void *param)
3978 {
3979         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3981         struct ixgbe_interrupt *intr =
3982                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3983         u32 speed;
3984         bool autoneg = false;
3985
3986         speed = hw->phy.autoneg_advertised;
3987         if (!speed)
3988                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3989
3990         ixgbe_setup_link(hw, speed, true);
3991
3992         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3993 }
3994
3995 /* return 0 means link status changed, -1 means not changed */
3996 int
3997 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3998                             int wait_to_complete, int vf)
3999 {
4000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4001         struct rte_eth_link link;
4002         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4003         struct ixgbe_interrupt *intr =
4004                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4005         int link_up;
4006         int diag;
4007         int wait = 1;
4008
4009         memset(&link, 0, sizeof(link));
4010         link.link_status = ETH_LINK_DOWN;
4011         link.link_speed = ETH_SPEED_NUM_NONE;
4012         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4013         link.link_autoneg = ETH_LINK_AUTONEG;
4014
4015         hw->mac.get_link_status = true;
4016
4017         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4018                 return rte_eth_linkstatus_set(dev, &link);
4019
4020         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4021         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4022                 wait = 0;
4023
4024         if (vf)
4025                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4026         else
4027                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4028
4029         if (diag != 0) {
4030                 link.link_speed = ETH_SPEED_NUM_100M;
4031                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4032                 return rte_eth_linkstatus_set(dev, &link);
4033         }
4034
4035         if (link_up == 0) {
4036                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4037                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4038                         rte_eal_alarm_set(10,
4039                                 ixgbe_dev_setup_link_alarm_handler, dev);
4040                 }
4041                 return rte_eth_linkstatus_set(dev, &link);
4042         }
4043
4044         link.link_status = ETH_LINK_UP;
4045         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4046
4047         switch (link_speed) {
4048         default:
4049         case IXGBE_LINK_SPEED_UNKNOWN:
4050                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4051                 link.link_speed = ETH_SPEED_NUM_100M;
4052                 break;
4053
4054         case IXGBE_LINK_SPEED_100_FULL:
4055                 link.link_speed = ETH_SPEED_NUM_100M;
4056                 break;
4057
4058         case IXGBE_LINK_SPEED_1GB_FULL:
4059                 link.link_speed = ETH_SPEED_NUM_1G;
4060                 break;
4061
4062         case IXGBE_LINK_SPEED_2_5GB_FULL:
4063                 link.link_speed = ETH_SPEED_NUM_2_5G;
4064                 break;
4065
4066         case IXGBE_LINK_SPEED_5GB_FULL:
4067                 link.link_speed = ETH_SPEED_NUM_5G;
4068                 break;
4069
4070         case IXGBE_LINK_SPEED_10GB_FULL:
4071                 link.link_speed = ETH_SPEED_NUM_10G;
4072                 break;
4073         }
4074
4075         return rte_eth_linkstatus_set(dev, &link);
4076 }
4077
4078 static int
4079 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4080 {
4081         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4082 }
4083
4084 static int
4085 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4086 {
4087         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4088 }
4089
4090 static void
4091 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4092 {
4093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4094         uint32_t fctrl;
4095
4096         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4097         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4098         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4099 }
4100
4101 static void
4102 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4103 {
4104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4105         uint32_t fctrl;
4106
4107         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4108         fctrl &= (~IXGBE_FCTRL_UPE);
4109         if (dev->data->all_multicast == 1)
4110                 fctrl |= IXGBE_FCTRL_MPE;
4111         else
4112                 fctrl &= (~IXGBE_FCTRL_MPE);
4113         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4114 }
4115
4116 static void
4117 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4118 {
4119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4120         uint32_t fctrl;
4121
4122         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4123         fctrl |= IXGBE_FCTRL_MPE;
4124         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4125 }
4126
4127 static void
4128 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4129 {
4130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4131         uint32_t fctrl;
4132
4133         if (dev->data->promiscuous == 1)
4134                 return; /* must remain in all_multicast mode */
4135
4136         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4137         fctrl &= (~IXGBE_FCTRL_MPE);
4138         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4139 }
4140
4141 /**
4142  * It clears the interrupt causes and enables the interrupt.
4143  * It will be called once only during nic initialized.
4144  *
4145  * @param dev
4146  *  Pointer to struct rte_eth_dev.
4147  * @param on
4148  *  Enable or Disable.
4149  *
4150  * @return
4151  *  - On success, zero.
4152  *  - On failure, a negative value.
4153  */
4154 static int
4155 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4156 {
4157         struct ixgbe_interrupt *intr =
4158                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4159
4160         ixgbe_dev_link_status_print(dev);
4161         if (on)
4162                 intr->mask |= IXGBE_EICR_LSC;
4163         else
4164                 intr->mask &= ~IXGBE_EICR_LSC;
4165
4166         return 0;
4167 }
4168
4169 /**
4170  * It clears the interrupt causes and enables the interrupt.
4171  * It will be called once only during nic initialized.
4172  *
4173  * @param dev
4174  *  Pointer to struct rte_eth_dev.
4175  *
4176  * @return
4177  *  - On success, zero.
4178  *  - On failure, a negative value.
4179  */
4180 static int
4181 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4182 {
4183         struct ixgbe_interrupt *intr =
4184                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4185
4186         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4187
4188         return 0;
4189 }
4190
4191 /**
4192  * It clears the interrupt causes and enables the interrupt.
4193  * It will be called once only during nic initialized.
4194  *
4195  * @param dev
4196  *  Pointer to struct rte_eth_dev.
4197  *
4198  * @return
4199  *  - On success, zero.
4200  *  - On failure, a negative value.
4201  */
4202 static int
4203 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4204 {
4205         struct ixgbe_interrupt *intr =
4206                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4207
4208         intr->mask |= IXGBE_EICR_LINKSEC;
4209
4210         return 0;
4211 }
4212
4213 /*
4214  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4215  *
4216  * @param dev
4217  *  Pointer to struct rte_eth_dev.
4218  *
4219  * @return
4220  *  - On success, zero.
4221  *  - On failure, a negative value.
4222  */
4223 static int
4224 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4225 {
4226         uint32_t eicr;
4227         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4228         struct ixgbe_interrupt *intr =
4229                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4230
4231         /* clear all cause mask */
4232         ixgbe_disable_intr(hw);
4233
4234         /* read-on-clear nic registers here */
4235         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4236         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4237
4238         intr->flags = 0;
4239
4240         /* set flag for async link update */
4241         if (eicr & IXGBE_EICR_LSC)
4242                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4243
4244         if (eicr & IXGBE_EICR_MAILBOX)
4245                 intr->flags |= IXGBE_FLAG_MAILBOX;
4246
4247         if (eicr & IXGBE_EICR_LINKSEC)
4248                 intr->flags |= IXGBE_FLAG_MACSEC;
4249
4250         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4251             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4252             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4253                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4254
4255         return 0;
4256 }
4257
4258 /**
4259  * It gets and then prints the link status.
4260  *
4261  * @param dev
4262  *  Pointer to struct rte_eth_dev.
4263  *
4264  * @return
4265  *  - On success, zero.
4266  *  - On failure, a negative value.
4267  */
4268 static void
4269 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4270 {
4271         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4272         struct rte_eth_link link;
4273
4274         rte_eth_linkstatus_get(dev, &link);
4275
4276         if (link.link_status) {
4277                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4278                                         (int)(dev->data->port_id),
4279                                         (unsigned)link.link_speed,
4280                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4281                                         "full-duplex" : "half-duplex");
4282         } else {
4283                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4284                                 (int)(dev->data->port_id));
4285         }
4286         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4287                                 pci_dev->addr.domain,
4288                                 pci_dev->addr.bus,
4289                                 pci_dev->addr.devid,
4290                                 pci_dev->addr.function);
4291 }
4292
4293 /*
4294  * It executes link_update after knowing an interrupt occurred.
4295  *
4296  * @param dev
4297  *  Pointer to struct rte_eth_dev.
4298  *
4299  * @return
4300  *  - On success, zero.
4301  *  - On failure, a negative value.
4302  */
4303 static int
4304 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4305 {
4306         struct ixgbe_interrupt *intr =
4307                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4308         int64_t timeout;
4309         struct ixgbe_hw *hw =
4310                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4311
4312         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4313
4314         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4315                 ixgbe_pf_mbx_process(dev);
4316                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4317         }
4318
4319         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4320                 ixgbe_handle_lasi(hw);
4321                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4322         }
4323
4324         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4325                 struct rte_eth_link link;
4326
4327                 /* get the link status before link update, for predicting later */
4328                 rte_eth_linkstatus_get(dev, &link);
4329
4330                 ixgbe_dev_link_update(dev, 0);
4331
4332                 /* likely to up */
4333                 if (!link.link_status)
4334                         /* handle it 1 sec later, wait it being stable */
4335                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4336                 /* likely to down */
4337                 else
4338                         /* handle it 4 sec later, wait it being stable */
4339                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4340
4341                 ixgbe_dev_link_status_print(dev);
4342                 if (rte_eal_alarm_set(timeout * 1000,
4343                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4344                         PMD_DRV_LOG(ERR, "Error setting alarm");
4345                 else {
4346                         /* remember original mask */
4347                         intr->mask_original = intr->mask;
4348                         /* only disable lsc interrupt */
4349                         intr->mask &= ~IXGBE_EIMS_LSC;
4350                 }
4351         }
4352
4353         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4354         ixgbe_enable_intr(dev);
4355
4356         return 0;
4357 }
4358
4359 /**
4360  * Interrupt handler which shall be registered for alarm callback for delayed
4361  * handling specific interrupt to wait for the stable nic state. As the
4362  * NIC interrupt state is not stable for ixgbe after link is just down,
4363  * it needs to wait 4 seconds to get the stable status.
4364  *
4365  * @param handle
4366  *  Pointer to interrupt handle.
4367  * @param param
4368  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4369  *
4370  * @return
4371  *  void
4372  */
4373 static void
4374 ixgbe_dev_interrupt_delayed_handler(void *param)
4375 {
4376         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4377         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4378         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4379         struct ixgbe_interrupt *intr =
4380                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4381         struct ixgbe_hw *hw =
4382                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4383         uint32_t eicr;
4384
4385         ixgbe_disable_intr(hw);
4386
4387         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4388         if (eicr & IXGBE_EICR_MAILBOX)
4389                 ixgbe_pf_mbx_process(dev);
4390
4391         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4392                 ixgbe_handle_lasi(hw);
4393                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4394         }
4395
4396         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4397                 ixgbe_dev_link_update(dev, 0);
4398                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4399                 ixgbe_dev_link_status_print(dev);
4400                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4401                                               NULL);
4402         }
4403
4404         if (intr->flags & IXGBE_FLAG_MACSEC) {
4405                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4406                                               NULL);
4407                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4408         }
4409
4410         /* restore original mask */
4411         intr->mask = intr->mask_original;
4412         intr->mask_original = 0;
4413
4414         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4415         ixgbe_enable_intr(dev);
4416         rte_intr_enable(intr_handle);
4417 }
4418
4419 /**
4420  * Interrupt handler triggered by NIC  for handling
4421  * specific interrupt.
4422  *
4423  * @param handle
4424  *  Pointer to interrupt handle.
4425  * @param param
4426  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4427  *
4428  * @return
4429  *  void
4430  */
4431 static void
4432 ixgbe_dev_interrupt_handler(void *param)
4433 {
4434         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4435
4436         ixgbe_dev_interrupt_get_status(dev);
4437         ixgbe_dev_interrupt_action(dev);
4438 }
4439
4440 static int
4441 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4442 {
4443         struct ixgbe_hw *hw;
4444
4445         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4446         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4447 }
4448
4449 static int
4450 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4451 {
4452         struct ixgbe_hw *hw;
4453
4454         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4455         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4456 }
4457
4458 static int
4459 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4460 {
4461         struct ixgbe_hw *hw;
4462         uint32_t mflcn_reg;
4463         uint32_t fccfg_reg;
4464         int rx_pause;
4465         int tx_pause;
4466
4467         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4468
4469         fc_conf->pause_time = hw->fc.pause_time;
4470         fc_conf->high_water = hw->fc.high_water[0];
4471         fc_conf->low_water = hw->fc.low_water[0];
4472         fc_conf->send_xon = hw->fc.send_xon;
4473         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4474
4475         /*
4476          * Return rx_pause status according to actual setting of
4477          * MFLCN register.
4478          */
4479         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4480         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4481                 rx_pause = 1;
4482         else
4483                 rx_pause = 0;
4484
4485         /*
4486          * Return tx_pause status according to actual setting of
4487          * FCCFG register.
4488          */
4489         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4490         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4491                 tx_pause = 1;
4492         else
4493                 tx_pause = 0;
4494
4495         if (rx_pause && tx_pause)
4496                 fc_conf->mode = RTE_FC_FULL;
4497         else if (rx_pause)
4498                 fc_conf->mode = RTE_FC_RX_PAUSE;
4499         else if (tx_pause)
4500                 fc_conf->mode = RTE_FC_TX_PAUSE;
4501         else
4502                 fc_conf->mode = RTE_FC_NONE;
4503
4504         return 0;
4505 }
4506
4507 static int
4508 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4509 {
4510         struct ixgbe_hw *hw;
4511         int err;
4512         uint32_t rx_buf_size;
4513         uint32_t max_high_water;
4514         uint32_t mflcn;
4515         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4516                 ixgbe_fc_none,
4517                 ixgbe_fc_rx_pause,
4518                 ixgbe_fc_tx_pause,
4519                 ixgbe_fc_full
4520         };
4521
4522         PMD_INIT_FUNC_TRACE();
4523
4524         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4525         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4526         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4527
4528         /*
4529          * At least reserve one Ethernet frame for watermark
4530          * high_water/low_water in kilo bytes for ixgbe
4531          */
4532         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4533         if ((fc_conf->high_water > max_high_water) ||
4534                 (fc_conf->high_water < fc_conf->low_water)) {
4535                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4536                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4537                 return -EINVAL;
4538         }
4539
4540         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4541         hw->fc.pause_time     = fc_conf->pause_time;
4542         hw->fc.high_water[0]  = fc_conf->high_water;
4543         hw->fc.low_water[0]   = fc_conf->low_water;
4544         hw->fc.send_xon       = fc_conf->send_xon;
4545         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4546
4547         err = ixgbe_fc_enable(hw);
4548
4549         /* Not negotiated is not an error case */
4550         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4551
4552                 /* check if we want to forward MAC frames - driver doesn't have native
4553                  * capability to do that, so we'll write the registers ourselves */
4554
4555                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4556
4557                 /* set or clear MFLCN.PMCF bit depending on configuration */
4558                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4559                         mflcn |= IXGBE_MFLCN_PMCF;
4560                 else
4561                         mflcn &= ~IXGBE_MFLCN_PMCF;
4562
4563                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4564                 IXGBE_WRITE_FLUSH(hw);
4565
4566                 return 0;
4567         }
4568
4569         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4570         return -EIO;
4571 }
4572
4573 /**
4574  *  ixgbe_pfc_enable_generic - Enable flow control
4575  *  @hw: pointer to hardware structure
4576  *  @tc_num: traffic class number
4577  *  Enable flow control according to the current settings.
4578  */
4579 static int
4580 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4581 {
4582         int ret_val = 0;
4583         uint32_t mflcn_reg, fccfg_reg;
4584         uint32_t reg;
4585         uint32_t fcrtl, fcrth;
4586         uint8_t i;
4587         uint8_t nb_rx_en;
4588
4589         /* Validate the water mark configuration */
4590         if (!hw->fc.pause_time) {
4591                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4592                 goto out;
4593         }
4594
4595         /* Low water mark of zero causes XOFF floods */
4596         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4597                  /* High/Low water can not be 0 */
4598                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4599                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4600                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4601                         goto out;
4602                 }
4603
4604                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4605                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4606                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4607                         goto out;
4608                 }
4609         }
4610         /* Negotiate the fc mode to use */
4611         ixgbe_fc_autoneg(hw);
4612
4613         /* Disable any previous flow control settings */
4614         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4615         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4616
4617         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4618         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4619
4620         switch (hw->fc.current_mode) {
4621         case ixgbe_fc_none:
4622                 /*
4623                  * If the count of enabled RX Priority Flow control >1,
4624                  * and the TX pause can not be disabled
4625                  */
4626                 nb_rx_en = 0;
4627                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4628                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4629                         if (reg & IXGBE_FCRTH_FCEN)
4630                                 nb_rx_en++;
4631                 }
4632                 if (nb_rx_en > 1)
4633                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4634                 break;
4635         case ixgbe_fc_rx_pause:
4636                 /*
4637                  * Rx Flow control is enabled and Tx Flow control is
4638                  * disabled by software override. Since there really
4639                  * isn't a way to advertise that we are capable of RX
4640                  * Pause ONLY, we will advertise that we support both
4641                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4642                  * disable the adapter's ability to send PAUSE frames.
4643                  */
4644                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4645                 /*
4646                  * If the count of enabled RX Priority Flow control >1,
4647                  * and the TX pause can not be disabled
4648                  */
4649                 nb_rx_en = 0;
4650                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4651                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4652                         if (reg & IXGBE_FCRTH_FCEN)
4653                                 nb_rx_en++;
4654                 }
4655                 if (nb_rx_en > 1)
4656                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4657                 break;
4658         case ixgbe_fc_tx_pause:
4659                 /*
4660                  * Tx Flow control is enabled, and Rx Flow control is
4661                  * disabled by software override.
4662                  */
4663                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4664                 break;
4665         case ixgbe_fc_full:
4666                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4667                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4668                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4669                 break;
4670         default:
4671                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4672                 ret_val = IXGBE_ERR_CONFIG;
4673                 goto out;
4674         }
4675
4676         /* Set 802.3x based flow control settings. */
4677         mflcn_reg |= IXGBE_MFLCN_DPF;
4678         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4679         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4680
4681         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4682         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4683                 hw->fc.high_water[tc_num]) {
4684                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4685                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4686                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4687         } else {
4688                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4689                 /*
4690                  * In order to prevent Tx hangs when the internal Tx
4691                  * switch is enabled we must set the high water mark
4692                  * to the maximum FCRTH value.  This allows the Tx
4693                  * switch to function even under heavy Rx workloads.
4694                  */
4695                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4696         }
4697         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4698
4699         /* Configure pause time (2 TCs per register) */
4700         reg = hw->fc.pause_time * 0x00010001;
4701         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4702                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4703
4704         /* Configure flow control refresh threshold value */
4705         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4706
4707 out:
4708         return ret_val;
4709 }
4710
4711 static int
4712 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4713 {
4714         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4715         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4716
4717         if (hw->mac.type != ixgbe_mac_82598EB) {
4718                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4719         }
4720         return ret_val;
4721 }
4722
4723 static int
4724 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4725 {
4726         int err;
4727         uint32_t rx_buf_size;
4728         uint32_t max_high_water;
4729         uint8_t tc_num;
4730         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4731         struct ixgbe_hw *hw =
4732                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4733         struct ixgbe_dcb_config *dcb_config =
4734                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4735
4736         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4737                 ixgbe_fc_none,
4738                 ixgbe_fc_rx_pause,
4739                 ixgbe_fc_tx_pause,
4740                 ixgbe_fc_full
4741         };
4742
4743         PMD_INIT_FUNC_TRACE();
4744
4745         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4746         tc_num = map[pfc_conf->priority];
4747         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4748         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4749         /*
4750          * At least reserve one Ethernet frame for watermark
4751          * high_water/low_water in kilo bytes for ixgbe
4752          */
4753         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4754         if ((pfc_conf->fc.high_water > max_high_water) ||
4755             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4756                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4757                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4758                 return -EINVAL;
4759         }
4760
4761         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4762         hw->fc.pause_time = pfc_conf->fc.pause_time;
4763         hw->fc.send_xon = pfc_conf->fc.send_xon;
4764         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4765         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4766
4767         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4768
4769         /* Not negotiated is not an error case */
4770         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4771                 return 0;
4772
4773         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4774         return -EIO;
4775 }
4776
4777 static int
4778 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4779                           struct rte_eth_rss_reta_entry64 *reta_conf,
4780                           uint16_t reta_size)
4781 {
4782         uint16_t i, sp_reta_size;
4783         uint8_t j, mask;
4784         uint32_t reta, r;
4785         uint16_t idx, shift;
4786         struct ixgbe_adapter *adapter =
4787                 (struct ixgbe_adapter *)dev->data->dev_private;
4788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789         uint32_t reta_reg;
4790
4791         PMD_INIT_FUNC_TRACE();
4792
4793         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4794                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4795                         "NIC.");
4796                 return -ENOTSUP;
4797         }
4798
4799         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4800         if (reta_size != sp_reta_size) {
4801                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4802                         "(%d) doesn't match the number hardware can supported "
4803                         "(%d)", reta_size, sp_reta_size);
4804                 return -EINVAL;
4805         }
4806
4807         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4808                 idx = i / RTE_RETA_GROUP_SIZE;
4809                 shift = i % RTE_RETA_GROUP_SIZE;
4810                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4811                                                 IXGBE_4_BIT_MASK);
4812                 if (!mask)
4813                         continue;
4814                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4815                 if (mask == IXGBE_4_BIT_MASK)
4816                         r = 0;
4817                 else
4818                         r = IXGBE_READ_REG(hw, reta_reg);
4819                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4820                         if (mask & (0x1 << j))
4821                                 reta |= reta_conf[idx].reta[shift + j] <<
4822                                                         (CHAR_BIT * j);
4823                         else
4824                                 reta |= r & (IXGBE_8_BIT_MASK <<
4825                                                 (CHAR_BIT * j));
4826                 }
4827                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4828         }
4829         adapter->rss_reta_updated = 1;
4830
4831         return 0;
4832 }
4833
4834 static int
4835 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4836                          struct rte_eth_rss_reta_entry64 *reta_conf,
4837                          uint16_t reta_size)
4838 {
4839         uint16_t i, sp_reta_size;
4840         uint8_t j, mask;
4841         uint32_t reta;
4842         uint16_t idx, shift;
4843         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4844         uint32_t reta_reg;
4845
4846         PMD_INIT_FUNC_TRACE();
4847         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4848         if (reta_size != sp_reta_size) {
4849                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4850                         "(%d) doesn't match the number hardware can supported "
4851                         "(%d)", reta_size, sp_reta_size);
4852                 return -EINVAL;
4853         }
4854
4855         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4856                 idx = i / RTE_RETA_GROUP_SIZE;
4857                 shift = i % RTE_RETA_GROUP_SIZE;
4858                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4859                                                 IXGBE_4_BIT_MASK);
4860                 if (!mask)
4861                         continue;
4862
4863                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4864                 reta = IXGBE_READ_REG(hw, reta_reg);
4865                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4866                         if (mask & (0x1 << j))
4867                                 reta_conf[idx].reta[shift + j] =
4868                                         ((reta >> (CHAR_BIT * j)) &
4869                                                 IXGBE_8_BIT_MASK);
4870                 }
4871         }
4872
4873         return 0;
4874 }
4875
4876 static int
4877 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4878                                 uint32_t index, uint32_t pool)
4879 {
4880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4881         uint32_t enable_addr = 1;
4882
4883         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4884                              pool, enable_addr);
4885 }
4886
4887 static void
4888 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4889 {
4890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4891
4892         ixgbe_clear_rar(hw, index);
4893 }
4894
4895 static int
4896 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4897 {
4898         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4899
4900         ixgbe_remove_rar(dev, 0);
4901         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4902
4903         return 0;
4904 }
4905
4906 static bool
4907 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4908 {
4909         if (strcmp(dev->device->driver->name, drv->driver.name))
4910                 return false;
4911
4912         return true;
4913 }
4914
4915 bool
4916 is_ixgbe_supported(struct rte_eth_dev *dev)
4917 {
4918         return is_device_supported(dev, &rte_ixgbe_pmd);
4919 }
4920
4921 static int
4922 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4923 {
4924         uint32_t hlreg0;
4925         uint32_t maxfrs;
4926         struct ixgbe_hw *hw;
4927         struct rte_eth_dev_info dev_info;
4928         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4929         struct rte_eth_dev_data *dev_data = dev->data;
4930
4931         ixgbe_dev_info_get(dev, &dev_info);
4932
4933         /* check that mtu is within the allowed range */
4934         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4935                 return -EINVAL;
4936
4937         /* If device is started, refuse mtu that requires the support of
4938          * scattered packets when this feature has not been enabled before.
4939          */
4940         if (dev_data->dev_started && !dev_data->scattered_rx &&
4941             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4942              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4943                 PMD_INIT_LOG(ERR, "Stop port first.");
4944                 return -EINVAL;
4945         }
4946
4947         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4948         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4949
4950         /* switch to jumbo mode if needed */
4951         if (frame_size > ETHER_MAX_LEN) {
4952                 dev->data->dev_conf.rxmode.offloads |=
4953                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4954                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4955         } else {
4956                 dev->data->dev_conf.rxmode.offloads &=
4957                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4958                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4959         }
4960         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4961
4962         /* update max frame size */
4963         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4964
4965         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4966         maxfrs &= 0x0000FFFF;
4967         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4968         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4969
4970         return 0;
4971 }
4972
4973 /*
4974  * Virtual Function operations
4975  */
4976 static void
4977 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4978 {
4979         struct ixgbe_interrupt *intr =
4980                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4981         struct ixgbe_hw *hw =
4982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4983
4984         PMD_INIT_FUNC_TRACE();
4985
4986         /* Clear interrupt mask to stop from interrupts being generated */
4987         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4988
4989         IXGBE_WRITE_FLUSH(hw);
4990
4991         /* Clear mask value. */
4992         intr->mask = 0;
4993 }
4994
4995 static void
4996 ixgbevf_intr_enable(struct rte_eth_dev *dev)
4997 {
4998         struct ixgbe_interrupt *intr =
4999                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5000         struct ixgbe_hw *hw =
5001                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5002
5003         PMD_INIT_FUNC_TRACE();
5004
5005         /* VF enable interrupt autoclean */
5006         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5007         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5008         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5009
5010         IXGBE_WRITE_FLUSH(hw);
5011
5012         /* Save IXGBE_VTEIMS value to mask. */
5013         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5014 }
5015
5016 static int
5017 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5018 {
5019         struct rte_eth_conf *conf = &dev->data->dev_conf;
5020         struct ixgbe_adapter *adapter =
5021                         (struct ixgbe_adapter *)dev->data->dev_private;
5022
5023         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5024                      dev->data->port_id);
5025
5026         /*
5027          * VF has no ability to enable/disable HW CRC
5028          * Keep the persistent behavior the same as Host PF
5029          */
5030 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5031         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5032                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5033                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5034         }
5035 #else
5036         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5037                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5038                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5039         }
5040 #endif
5041
5042         /*
5043          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5044          * allocation or vector Rx preconditions we will reset it.
5045          */
5046         adapter->rx_bulk_alloc_allowed = true;
5047         adapter->rx_vec_allowed = true;
5048
5049         return 0;
5050 }
5051
5052 static int
5053 ixgbevf_dev_start(struct rte_eth_dev *dev)
5054 {
5055         struct ixgbe_hw *hw =
5056                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057         uint32_t intr_vector = 0;
5058         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5059         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5060
5061         int err, mask = 0;
5062
5063         PMD_INIT_FUNC_TRACE();
5064
5065         /* Stop the link setup handler before resetting the HW. */
5066         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5067
5068         err = hw->mac.ops.reset_hw(hw);
5069         if (err) {
5070                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5071                 return err;
5072         }
5073         hw->mac.get_link_status = true;
5074
5075         /* negotiate mailbox API version to use with the PF. */
5076         ixgbevf_negotiate_api(hw);
5077
5078         ixgbevf_dev_tx_init(dev);
5079
5080         /* This can fail when allocating mbufs for descriptor rings */
5081         err = ixgbevf_dev_rx_init(dev);
5082         if (err) {
5083                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5084                 ixgbe_dev_clear_queues(dev);
5085                 return err;
5086         }
5087
5088         /* Set vfta */
5089         ixgbevf_set_vfta_all(dev, 1);
5090
5091         /* Set HW strip */
5092         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5093                 ETH_VLAN_EXTEND_MASK;
5094         err = ixgbevf_vlan_offload_config(dev, mask);
5095         if (err) {
5096                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5097                 ixgbe_dev_clear_queues(dev);
5098                 return err;
5099         }
5100
5101         ixgbevf_dev_rxtx_start(dev);
5102
5103         /* check and configure queue intr-vector mapping */
5104         if (rte_intr_cap_multiple(intr_handle) &&
5105             dev->data->dev_conf.intr_conf.rxq) {
5106                 /* According to datasheet, only vector 0/1/2 can be used,
5107                  * now only one vector is used for Rx queue
5108                  */
5109                 intr_vector = 1;
5110                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5111                         return -1;
5112         }
5113
5114         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5115                 intr_handle->intr_vec =
5116                         rte_zmalloc("intr_vec",
5117                                     dev->data->nb_rx_queues * sizeof(int), 0);
5118                 if (intr_handle->intr_vec == NULL) {
5119                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5120                                      " intr_vec", dev->data->nb_rx_queues);
5121                         return -ENOMEM;
5122                 }
5123         }
5124         ixgbevf_configure_msix(dev);
5125
5126         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5127          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5128          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5129          * is not cleared, it will fail when following rte_intr_enable( ) tries
5130          * to map Rx queue interrupt to other VFIO vectors.
5131          * So clear uio/vfio intr/evevnfd first to avoid failure.
5132          */
5133         rte_intr_disable(intr_handle);
5134
5135         rte_intr_enable(intr_handle);
5136
5137         /* Re-enable interrupt for VF */
5138         ixgbevf_intr_enable(dev);
5139
5140         /*
5141          * Update link status right before return, because it may
5142          * start link configuration process in a separate thread.
5143          */
5144         ixgbevf_dev_link_update(dev, 0);
5145
5146         return 0;
5147 }
5148
5149 static void
5150 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5151 {
5152         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5153         struct ixgbe_adapter *adapter =
5154                 (struct ixgbe_adapter *)dev->data->dev_private;
5155         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5156         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5157
5158         PMD_INIT_FUNC_TRACE();
5159
5160         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5161
5162         ixgbevf_intr_disable(dev);
5163
5164         hw->adapter_stopped = 1;
5165         ixgbe_stop_adapter(hw);
5166
5167         /*
5168           * Clear what we set, but we still keep shadow_vfta to
5169           * restore after device starts
5170           */
5171         ixgbevf_set_vfta_all(dev, 0);
5172
5173         /* Clear stored conf */
5174         dev->data->scattered_rx = 0;
5175
5176         ixgbe_dev_clear_queues(dev);
5177
5178         /* Clean datapath event and queue/vec mapping */
5179         rte_intr_efd_disable(intr_handle);
5180         if (intr_handle->intr_vec != NULL) {
5181                 rte_free(intr_handle->intr_vec);
5182                 intr_handle->intr_vec = NULL;
5183         }
5184
5185         adapter->rss_reta_updated = 0;
5186 }
5187
5188 static void
5189 ixgbevf_dev_close(struct rte_eth_dev *dev)
5190 {
5191         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5192
5193         PMD_INIT_FUNC_TRACE();
5194
5195         ixgbe_reset_hw(hw);
5196
5197         ixgbevf_dev_stop(dev);
5198
5199         ixgbe_dev_free_queues(dev);
5200
5201         /**
5202          * Remove the VF MAC address ro ensure
5203          * that the VF traffic goes to the PF
5204          * after stop, close and detach of the VF
5205          **/
5206         ixgbevf_remove_mac_addr(dev, 0);
5207 }
5208
5209 /*
5210  * Reset VF device
5211  */
5212 static int
5213 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5214 {
5215         int ret;
5216
5217         ret = eth_ixgbevf_dev_uninit(dev);
5218         if (ret)
5219                 return ret;
5220
5221         ret = eth_ixgbevf_dev_init(dev);
5222
5223         return ret;
5224 }
5225
5226 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5227 {
5228         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5229         struct ixgbe_vfta *shadow_vfta =
5230                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5231         int i = 0, j = 0, vfta = 0, mask = 1;
5232
5233         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5234                 vfta = shadow_vfta->vfta[i];
5235                 if (vfta) {
5236                         mask = 1;
5237                         for (j = 0; j < 32; j++) {
5238                                 if (vfta & mask)
5239                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5240                                                        on, false);
5241                                 mask <<= 1;
5242                         }
5243                 }
5244         }
5245
5246 }
5247
5248 static int
5249 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5250 {
5251         struct ixgbe_hw *hw =
5252                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5253         struct ixgbe_vfta *shadow_vfta =
5254                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5255         uint32_t vid_idx = 0;
5256         uint32_t vid_bit = 0;
5257         int ret = 0;
5258
5259         PMD_INIT_FUNC_TRACE();
5260
5261         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5262         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5263         if (ret) {
5264                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5265                 return ret;
5266         }
5267         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5268         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5269
5270         /* Save what we set and retore it after device reset */
5271         if (on)
5272                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5273         else
5274                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5275
5276         return 0;
5277 }
5278
5279 static void
5280 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5281 {
5282         struct ixgbe_hw *hw =
5283                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5284         uint32_t ctrl;
5285
5286         PMD_INIT_FUNC_TRACE();
5287
5288         if (queue >= hw->mac.max_rx_queues)
5289                 return;
5290
5291         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5292         if (on)
5293                 ctrl |= IXGBE_RXDCTL_VME;
5294         else
5295                 ctrl &= ~IXGBE_RXDCTL_VME;
5296         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5297
5298         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5299 }
5300
5301 static int
5302 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5303 {
5304         struct ixgbe_rx_queue *rxq;
5305         uint16_t i;
5306         int on = 0;
5307
5308         /* VF function only support hw strip feature, others are not support */
5309         if (mask & ETH_VLAN_STRIP_MASK) {
5310                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5311                         rxq = dev->data->rx_queues[i];
5312                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5313                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5314                 }
5315         }
5316
5317         return 0;
5318 }
5319
5320 static int
5321 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5322 {
5323         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5324
5325         ixgbevf_vlan_offload_config(dev, mask);
5326
5327         return 0;
5328 }
5329
5330 int
5331 ixgbe_vt_check(struct ixgbe_hw *hw)
5332 {
5333         uint32_t reg_val;
5334
5335         /* if Virtualization Technology is enabled */
5336         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5337         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5338                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5339                 return -1;
5340         }
5341
5342         return 0;
5343 }
5344
5345 static uint32_t
5346 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5347 {
5348         uint32_t vector = 0;
5349
5350         switch (hw->mac.mc_filter_type) {
5351         case 0:   /* use bits [47:36] of the address */
5352                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5353                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5354                 break;
5355         case 1:   /* use bits [46:35] of the address */
5356                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5357                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5358                 break;
5359         case 2:   /* use bits [45:34] of the address */
5360                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5361                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5362                 break;
5363         case 3:   /* use bits [43:32] of the address */
5364                 vector = ((uc_addr->addr_bytes[4]) |
5365                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5366                 break;
5367         default:  /* Invalid mc_filter_type */
5368                 break;
5369         }
5370
5371         /* vector can only be 12-bits or boundary will be exceeded */
5372         vector &= 0xFFF;
5373         return vector;
5374 }
5375
5376 static int
5377 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5378                         uint8_t on)
5379 {
5380         uint32_t vector;
5381         uint32_t uta_idx;
5382         uint32_t reg_val;
5383         uint32_t uta_shift;
5384         uint32_t rc;
5385         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5386         const uint32_t ixgbe_uta_bit_shift = 5;
5387         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5388         const uint32_t bit1 = 0x1;
5389
5390         struct ixgbe_hw *hw =
5391                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5392         struct ixgbe_uta_info *uta_info =
5393                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5394
5395         /* The UTA table only exists on 82599 hardware and newer */
5396         if (hw->mac.type < ixgbe_mac_82599EB)
5397                 return -ENOTSUP;
5398
5399         vector = ixgbe_uta_vector(hw, mac_addr);
5400         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5401         uta_shift = vector & ixgbe_uta_bit_mask;
5402
5403         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5404         if (rc == on)
5405                 return 0;
5406
5407         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5408         if (on) {
5409                 uta_info->uta_in_use++;
5410                 reg_val |= (bit1 << uta_shift);
5411                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5412         } else {
5413                 uta_info->uta_in_use--;
5414                 reg_val &= ~(bit1 << uta_shift);
5415                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5416         }
5417
5418         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5419
5420         if (uta_info->uta_in_use > 0)
5421                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5422                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5423         else
5424                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5425
5426         return 0;
5427 }
5428
5429 static int
5430 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5431 {
5432         int i;
5433         struct ixgbe_hw *hw =
5434                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5435         struct ixgbe_uta_info *uta_info =
5436                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5437
5438         /* The UTA table only exists on 82599 hardware and newer */
5439         if (hw->mac.type < ixgbe_mac_82599EB)
5440                 return -ENOTSUP;
5441
5442         if (on) {
5443                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5444                         uta_info->uta_shadow[i] = ~0;
5445                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5446                 }
5447         } else {
5448                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5449                         uta_info->uta_shadow[i] = 0;
5450                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5451                 }
5452         }
5453         return 0;
5454
5455 }
5456
5457 uint32_t
5458 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5459 {
5460         uint32_t new_val = orig_val;
5461
5462         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5463                 new_val |= IXGBE_VMOLR_AUPE;
5464         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5465                 new_val |= IXGBE_VMOLR_ROMPE;
5466         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5467                 new_val |= IXGBE_VMOLR_ROPE;
5468         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5469                 new_val |= IXGBE_VMOLR_BAM;
5470         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5471                 new_val |= IXGBE_VMOLR_MPE;
5472
5473         return new_val;
5474 }
5475
5476 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5477 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5478 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5479 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5480 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5481         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5482         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5483
5484 static int
5485 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5486                       struct rte_eth_mirror_conf *mirror_conf,
5487                       uint8_t rule_id, uint8_t on)
5488 {
5489         uint32_t mr_ctl, vlvf;
5490         uint32_t mp_lsb = 0;
5491         uint32_t mv_msb = 0;
5492         uint32_t mv_lsb = 0;
5493         uint32_t mp_msb = 0;
5494         uint8_t i = 0;
5495         int reg_index = 0;
5496         uint64_t vlan_mask = 0;
5497
5498         const uint8_t pool_mask_offset = 32;
5499         const uint8_t vlan_mask_offset = 32;
5500         const uint8_t dst_pool_offset = 8;
5501         const uint8_t rule_mr_offset  = 4;
5502         const uint8_t mirror_rule_mask = 0x0F;
5503
5504         struct ixgbe_mirror_info *mr_info =
5505                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5506         struct ixgbe_hw *hw =
5507                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5508         uint8_t mirror_type = 0;
5509
5510         if (ixgbe_vt_check(hw) < 0)
5511                 return -ENOTSUP;
5512
5513         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5514                 return -EINVAL;
5515
5516         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5517                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5518                             mirror_conf->rule_type);
5519                 return -EINVAL;
5520         }
5521
5522         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5523                 mirror_type |= IXGBE_MRCTL_VLME;
5524                 /* Check if vlan id is valid and find conresponding VLAN ID
5525                  * index in VLVF
5526                  */
5527                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5528                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5529                                 /* search vlan id related pool vlan filter
5530                                  * index
5531                                  */
5532                                 reg_index = ixgbe_find_vlvf_slot(
5533                                                 hw,
5534                                                 mirror_conf->vlan.vlan_id[i],
5535                                                 false);
5536                                 if (reg_index < 0)
5537                                         return -EINVAL;
5538                                 vlvf = IXGBE_READ_REG(hw,
5539                                                       IXGBE_VLVF(reg_index));
5540                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5541                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5542                                       mirror_conf->vlan.vlan_id[i]))
5543                                         vlan_mask |= (1ULL << reg_index);
5544                                 else
5545                                         return -EINVAL;
5546                         }
5547                 }
5548
5549                 if (on) {
5550                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5551                         mv_msb = vlan_mask >> vlan_mask_offset;
5552
5553                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5554                                                 mirror_conf->vlan.vlan_mask;
5555                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5556                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5557                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5558                                                 mirror_conf->vlan.vlan_id[i];
5559                         }
5560                 } else {
5561                         mv_lsb = 0;
5562                         mv_msb = 0;
5563                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5564                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5565                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5566                 }
5567         }
5568
5569         /**
5570          * if enable pool mirror, write related pool mask register,if disable
5571          * pool mirror, clear PFMRVM register
5572          */
5573         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5574                 mirror_type |= IXGBE_MRCTL_VPME;
5575                 if (on) {
5576                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5577                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5578                         mr_info->mr_conf[rule_id].pool_mask =
5579                                         mirror_conf->pool_mask;
5580
5581                 } else {
5582                         mp_lsb = 0;
5583                         mp_msb = 0;
5584                         mr_info->mr_conf[rule_id].pool_mask = 0;
5585                 }
5586         }
5587         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5588                 mirror_type |= IXGBE_MRCTL_UPME;
5589         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5590                 mirror_type |= IXGBE_MRCTL_DPME;
5591
5592         /* read  mirror control register and recalculate it */
5593         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5594
5595         if (on) {
5596                 mr_ctl |= mirror_type;
5597                 mr_ctl &= mirror_rule_mask;
5598                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5599         } else {
5600                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5601         }
5602
5603         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5604         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5605
5606         /* write mirrror control  register */
5607         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5608
5609         /* write pool mirrror control  register */
5610         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5611                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5612                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5613                                 mp_msb);
5614         }
5615         /* write VLAN mirrror control  register */
5616         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5617                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5618                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5619                                 mv_msb);
5620         }
5621
5622         return 0;
5623 }
5624
5625 static int
5626 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5627 {
5628         int mr_ctl = 0;
5629         uint32_t lsb_val = 0;
5630         uint32_t msb_val = 0;
5631         const uint8_t rule_mr_offset = 4;
5632
5633         struct ixgbe_hw *hw =
5634                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5635         struct ixgbe_mirror_info *mr_info =
5636                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5637
5638         if (ixgbe_vt_check(hw) < 0)
5639                 return -ENOTSUP;
5640
5641         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5642                 return -EINVAL;
5643
5644         memset(&mr_info->mr_conf[rule_id], 0,
5645                sizeof(struct rte_eth_mirror_conf));
5646
5647         /* clear PFVMCTL register */
5648         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5649
5650         /* clear pool mask register */
5651         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5652         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5653
5654         /* clear vlan mask register */
5655         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5656         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5657
5658         return 0;
5659 }
5660
5661 static int
5662 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5663 {
5664         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5665         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5666         struct ixgbe_interrupt *intr =
5667                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5668         struct ixgbe_hw *hw =
5669                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5670         uint32_t vec = IXGBE_MISC_VEC_ID;
5671
5672         if (rte_intr_allow_others(intr_handle))
5673                 vec = IXGBE_RX_VEC_START;
5674         intr->mask |= (1 << vec);
5675         RTE_SET_USED(queue_id);
5676         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5677
5678         rte_intr_enable(intr_handle);
5679
5680         return 0;
5681 }
5682
5683 static int
5684 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5685 {
5686         struct ixgbe_interrupt *intr =
5687                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5688         struct ixgbe_hw *hw =
5689                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5690         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5691         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5692         uint32_t vec = IXGBE_MISC_VEC_ID;
5693
5694         if (rte_intr_allow_others(intr_handle))
5695                 vec = IXGBE_RX_VEC_START;
5696         intr->mask &= ~(1 << vec);
5697         RTE_SET_USED(queue_id);
5698         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5699
5700         return 0;
5701 }
5702
5703 static int
5704 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5705 {
5706         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5707         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5708         uint32_t mask;
5709         struct ixgbe_hw *hw =
5710                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5711         struct ixgbe_interrupt *intr =
5712                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5713
5714         if (queue_id < 16) {
5715                 ixgbe_disable_intr(hw);
5716                 intr->mask |= (1 << queue_id);
5717                 ixgbe_enable_intr(dev);
5718         } else if (queue_id < 32) {
5719                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5720                 mask &= (1 << queue_id);
5721                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5722         } else if (queue_id < 64) {
5723                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5724                 mask &= (1 << (queue_id - 32));
5725                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5726         }
5727         rte_intr_enable(intr_handle);
5728
5729         return 0;
5730 }
5731
5732 static int
5733 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5734 {
5735         uint32_t mask;
5736         struct ixgbe_hw *hw =
5737                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5738         struct ixgbe_interrupt *intr =
5739                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5740
5741         if (queue_id < 16) {
5742                 ixgbe_disable_intr(hw);
5743                 intr->mask &= ~(1 << queue_id);
5744                 ixgbe_enable_intr(dev);
5745         } else if (queue_id < 32) {
5746                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5747                 mask &= ~(1 << queue_id);
5748                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5749         } else if (queue_id < 64) {
5750                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5751                 mask &= ~(1 << (queue_id - 32));
5752                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5753         }
5754
5755         return 0;
5756 }
5757
5758 static void
5759 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5760                      uint8_t queue, uint8_t msix_vector)
5761 {
5762         uint32_t tmp, idx;
5763
5764         if (direction == -1) {
5765                 /* other causes */
5766                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5767                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5768                 tmp &= ~0xFF;
5769                 tmp |= msix_vector;
5770                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5771         } else {
5772                 /* rx or tx cause */
5773                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5774                 idx = ((16 * (queue & 1)) + (8 * direction));
5775                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5776                 tmp &= ~(0xFF << idx);
5777                 tmp |= (msix_vector << idx);
5778                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5779         }
5780 }
5781
5782 /**
5783  * set the IVAR registers, mapping interrupt causes to vectors
5784  * @param hw
5785  *  pointer to ixgbe_hw struct
5786  * @direction
5787  *  0 for Rx, 1 for Tx, -1 for other causes
5788  * @queue
5789  *  queue to map the corresponding interrupt to
5790  * @msix_vector
5791  *  the vector to map to the corresponding queue
5792  */
5793 static void
5794 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5795                    uint8_t queue, uint8_t msix_vector)
5796 {
5797         uint32_t tmp, idx;
5798
5799         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5800         if (hw->mac.type == ixgbe_mac_82598EB) {
5801                 if (direction == -1)
5802                         direction = 0;
5803                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5804                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5805                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5806                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5807                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5808         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5809                         (hw->mac.type == ixgbe_mac_X540) ||
5810                         (hw->mac.type == ixgbe_mac_X550)) {
5811                 if (direction == -1) {
5812                         /* other causes */
5813                         idx = ((queue & 1) * 8);
5814                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5815                         tmp &= ~(0xFF << idx);
5816                         tmp |= (msix_vector << idx);
5817                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5818                 } else {
5819                         /* rx or tx causes */
5820                         idx = ((16 * (queue & 1)) + (8 * direction));
5821                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5822                         tmp &= ~(0xFF << idx);
5823                         tmp |= (msix_vector << idx);
5824                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5825                 }
5826         }
5827 }
5828
5829 static void
5830 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5831 {
5832         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5833         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5834         struct ixgbe_hw *hw =
5835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5836         uint32_t q_idx;
5837         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5838         uint32_t base = IXGBE_MISC_VEC_ID;
5839
5840         /* Configure VF other cause ivar */
5841         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5842
5843         /* won't configure msix register if no mapping is done
5844          * between intr vector and event fd.
5845          */
5846         if (!rte_intr_dp_is_en(intr_handle))
5847                 return;
5848
5849         if (rte_intr_allow_others(intr_handle)) {
5850                 base = IXGBE_RX_VEC_START;
5851                 vector_idx = IXGBE_RX_VEC_START;
5852         }
5853
5854         /* Configure all RX queues of VF */
5855         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5856                 /* Force all queue use vector 0,
5857                  * as IXGBE_VF_MAXMSIVECOTR = 1
5858                  */
5859                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5860                 intr_handle->intr_vec[q_idx] = vector_idx;
5861                 if (vector_idx < base + intr_handle->nb_efd - 1)
5862                         vector_idx++;
5863         }
5864
5865         /* As RX queue setting above show, all queues use the vector 0.
5866          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5867          */
5868         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5869                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5870                         | IXGBE_EITR_CNT_WDIS);
5871 }
5872
5873 /**
5874  * Sets up the hardware to properly generate MSI-X interrupts
5875  * @hw
5876  *  board private structure
5877  */
5878 static void
5879 ixgbe_configure_msix(struct rte_eth_dev *dev)
5880 {
5881         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5882         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5883         struct ixgbe_hw *hw =
5884                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5885         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5886         uint32_t vec = IXGBE_MISC_VEC_ID;
5887         uint32_t mask;
5888         uint32_t gpie;
5889
5890         /* won't configure msix register if no mapping is done
5891          * between intr vector and event fd
5892          * but if misx has been enabled already, need to configure
5893          * auto clean, auto mask and throttling.
5894          */
5895         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5896         if (!rte_intr_dp_is_en(intr_handle) &&
5897             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5898                 return;
5899
5900         if (rte_intr_allow_others(intr_handle))
5901                 vec = base = IXGBE_RX_VEC_START;
5902
5903         /* setup GPIE for MSI-x mode */
5904         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5905         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5906                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5907         /* auto clearing and auto setting corresponding bits in EIMS
5908          * when MSI-X interrupt is triggered
5909          */
5910         if (hw->mac.type == ixgbe_mac_82598EB) {
5911                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5912         } else {
5913                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5914                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5915         }
5916         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5917
5918         /* Populate the IVAR table and set the ITR values to the
5919          * corresponding register.
5920          */
5921         if (rte_intr_dp_is_en(intr_handle)) {
5922                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5923                         queue_id++) {
5924                         /* by default, 1:1 mapping */
5925                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5926                         intr_handle->intr_vec[queue_id] = vec;
5927                         if (vec < base + intr_handle->nb_efd - 1)
5928                                 vec++;
5929                 }
5930
5931                 switch (hw->mac.type) {
5932                 case ixgbe_mac_82598EB:
5933                         ixgbe_set_ivar_map(hw, -1,
5934                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5935                                            IXGBE_MISC_VEC_ID);
5936                         break;
5937                 case ixgbe_mac_82599EB:
5938                 case ixgbe_mac_X540:
5939                 case ixgbe_mac_X550:
5940                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5941                         break;
5942                 default:
5943                         break;
5944                 }
5945         }
5946         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5947                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5948                         | IXGBE_EITR_CNT_WDIS);
5949
5950         /* set up to autoclear timer, and the vectors */
5951         mask = IXGBE_EIMS_ENABLE_MASK;
5952         mask &= ~(IXGBE_EIMS_OTHER |
5953                   IXGBE_EIMS_MAILBOX |
5954                   IXGBE_EIMS_LSC);
5955
5956         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5957 }
5958
5959 int
5960 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5961                            uint16_t queue_idx, uint16_t tx_rate)
5962 {
5963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5964         struct rte_eth_rxmode *rxmode;
5965         uint32_t rf_dec, rf_int;
5966         uint32_t bcnrc_val;
5967         uint16_t link_speed = dev->data->dev_link.link_speed;
5968
5969         if (queue_idx >= hw->mac.max_tx_queues)
5970                 return -EINVAL;
5971
5972         if (tx_rate != 0) {
5973                 /* Calculate the rate factor values to set */
5974                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5975                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5976                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5977
5978                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5979                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5980                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5981                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5982         } else {
5983                 bcnrc_val = 0;
5984         }
5985
5986         rxmode = &dev->data->dev_conf.rxmode;
5987         /*
5988          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5989          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5990          * set as 0x4.
5991          */
5992         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5993             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5994                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5995                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5996         else
5997                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5998                         IXGBE_MMW_SIZE_DEFAULT);
5999
6000         /* Set RTTBCNRC of queue X */
6001         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6002         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6003         IXGBE_WRITE_FLUSH(hw);
6004
6005         return 0;
6006 }
6007
6008 static int
6009 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
6010                      __attribute__((unused)) uint32_t index,
6011                      __attribute__((unused)) uint32_t pool)
6012 {
6013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6014         int diag;
6015
6016         /*
6017          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6018          * operation. Trap this case to avoid exhausting the [very limited]
6019          * set of PF resources used to store VF MAC addresses.
6020          */
6021         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6022                 return -1;
6023         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6024         if (diag != 0)
6025                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6026                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6027                             mac_addr->addr_bytes[0],
6028                             mac_addr->addr_bytes[1],
6029                             mac_addr->addr_bytes[2],
6030                             mac_addr->addr_bytes[3],
6031                             mac_addr->addr_bytes[4],
6032                             mac_addr->addr_bytes[5],
6033                             diag);
6034         return diag;
6035 }
6036
6037 static void
6038 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6039 {
6040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6041         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6042         struct ether_addr *mac_addr;
6043         uint32_t i;
6044         int diag;
6045
6046         /*
6047          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6048          * not support the deletion of a given MAC address.
6049          * Instead, it imposes to delete all MAC addresses, then to add again
6050          * all MAC addresses with the exception of the one to be deleted.
6051          */
6052         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6053
6054         /*
6055          * Add again all MAC addresses, with the exception of the deleted one
6056          * and of the permanent MAC address.
6057          */
6058         for (i = 0, mac_addr = dev->data->mac_addrs;
6059              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6060                 /* Skip the deleted MAC address */
6061                 if (i == index)
6062                         continue;
6063                 /* Skip NULL MAC addresses */
6064                 if (is_zero_ether_addr(mac_addr))
6065                         continue;
6066                 /* Skip the permanent MAC address */
6067                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6068                         continue;
6069                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6070                 if (diag != 0)
6071                         PMD_DRV_LOG(ERR,
6072                                     "Adding again MAC address "
6073                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6074                                     "diag=%d",
6075                                     mac_addr->addr_bytes[0],
6076                                     mac_addr->addr_bytes[1],
6077                                     mac_addr->addr_bytes[2],
6078                                     mac_addr->addr_bytes[3],
6079                                     mac_addr->addr_bytes[4],
6080                                     mac_addr->addr_bytes[5],
6081                                     diag);
6082         }
6083 }
6084
6085 static int
6086 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6087 {
6088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6089
6090         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6091
6092         return 0;
6093 }
6094
6095 int
6096 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6097                         struct rte_eth_syn_filter *filter,
6098                         bool add)
6099 {
6100         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6101         struct ixgbe_filter_info *filter_info =
6102                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6103         uint32_t syn_info;
6104         uint32_t synqf;
6105
6106         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6107                 return -EINVAL;
6108
6109         syn_info = filter_info->syn_info;
6110
6111         if (add) {
6112                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6113                         return -EINVAL;
6114                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6115                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6116
6117                 if (filter->hig_pri)
6118                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6119                 else
6120                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6121         } else {
6122                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6123                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6124                         return -ENOENT;
6125                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6126         }
6127
6128         filter_info->syn_info = synqf;
6129         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6130         IXGBE_WRITE_FLUSH(hw);
6131         return 0;
6132 }
6133
6134 static int
6135 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6136                         struct rte_eth_syn_filter *filter)
6137 {
6138         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6139         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6140
6141         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6142                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6143                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6144                 return 0;
6145         }
6146         return -ENOENT;
6147 }
6148
6149 static int
6150 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6151                         enum rte_filter_op filter_op,
6152                         void *arg)
6153 {
6154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155         int ret;
6156
6157         MAC_TYPE_FILTER_SUP(hw->mac.type);
6158
6159         if (filter_op == RTE_ETH_FILTER_NOP)
6160                 return 0;
6161
6162         if (arg == NULL) {
6163                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6164                             filter_op);
6165                 return -EINVAL;
6166         }
6167
6168         switch (filter_op) {
6169         case RTE_ETH_FILTER_ADD:
6170                 ret = ixgbe_syn_filter_set(dev,
6171                                 (struct rte_eth_syn_filter *)arg,
6172                                 TRUE);
6173                 break;
6174         case RTE_ETH_FILTER_DELETE:
6175                 ret = ixgbe_syn_filter_set(dev,
6176                                 (struct rte_eth_syn_filter *)arg,
6177                                 FALSE);
6178                 break;
6179         case RTE_ETH_FILTER_GET:
6180                 ret = ixgbe_syn_filter_get(dev,
6181                                 (struct rte_eth_syn_filter *)arg);
6182                 break;
6183         default:
6184                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6185                 ret = -EINVAL;
6186                 break;
6187         }
6188
6189         return ret;
6190 }
6191
6192
6193 static inline enum ixgbe_5tuple_protocol
6194 convert_protocol_type(uint8_t protocol_value)
6195 {
6196         if (protocol_value == IPPROTO_TCP)
6197                 return IXGBE_FILTER_PROTOCOL_TCP;
6198         else if (protocol_value == IPPROTO_UDP)
6199                 return IXGBE_FILTER_PROTOCOL_UDP;
6200         else if (protocol_value == IPPROTO_SCTP)
6201                 return IXGBE_FILTER_PROTOCOL_SCTP;
6202         else
6203                 return IXGBE_FILTER_PROTOCOL_NONE;
6204 }
6205
6206 /* inject a 5-tuple filter to HW */
6207 static inline void
6208 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6209                            struct ixgbe_5tuple_filter *filter)
6210 {
6211         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6212         int i;
6213         uint32_t ftqf, sdpqf;
6214         uint32_t l34timir = 0;
6215         uint8_t mask = 0xff;
6216
6217         i = filter->index;
6218
6219         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6220                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6221         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6222
6223         ftqf = (uint32_t)(filter->filter_info.proto &
6224                 IXGBE_FTQF_PROTOCOL_MASK);
6225         ftqf |= (uint32_t)((filter->filter_info.priority &
6226                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6227         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6228                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6229         if (filter->filter_info.dst_ip_mask == 0)
6230                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6231         if (filter->filter_info.src_port_mask == 0)
6232                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6233         if (filter->filter_info.dst_port_mask == 0)
6234                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6235         if (filter->filter_info.proto_mask == 0)
6236                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6237         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6238         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6239         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6240
6241         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6242         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6243         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6244         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6245
6246         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6247         l34timir |= (uint32_t)(filter->queue <<
6248                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6249         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6250 }
6251
6252 /*
6253  * add a 5tuple filter
6254  *
6255  * @param
6256  * dev: Pointer to struct rte_eth_dev.
6257  * index: the index the filter allocates.
6258  * filter: ponter to the filter that will be added.
6259  * rx_queue: the queue id the filter assigned to.
6260  *
6261  * @return
6262  *    - On success, zero.
6263  *    - On failure, a negative value.
6264  */
6265 static int
6266 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6267                         struct ixgbe_5tuple_filter *filter)
6268 {
6269         struct ixgbe_filter_info *filter_info =
6270                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6271         int i, idx, shift;
6272
6273         /*
6274          * look for an unused 5tuple filter index,
6275          * and insert the filter to list.
6276          */
6277         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6278                 idx = i / (sizeof(uint32_t) * NBBY);
6279                 shift = i % (sizeof(uint32_t) * NBBY);
6280                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6281                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6282                         filter->index = i;
6283                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6284                                           filter,
6285                                           entries);
6286                         break;
6287                 }
6288         }
6289         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6290                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6291                 return -ENOSYS;
6292         }
6293
6294         ixgbe_inject_5tuple_filter(dev, filter);
6295
6296         return 0;
6297 }
6298
6299 /*
6300  * remove a 5tuple filter
6301  *
6302  * @param
6303  * dev: Pointer to struct rte_eth_dev.
6304  * filter: the pointer of the filter will be removed.
6305  */
6306 static void
6307 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6308                         struct ixgbe_5tuple_filter *filter)
6309 {
6310         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6311         struct ixgbe_filter_info *filter_info =
6312                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6313         uint16_t index = filter->index;
6314
6315         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6316                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6317         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6318         rte_free(filter);
6319
6320         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6321         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6322         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6323         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6324         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6325 }
6326
6327 static int
6328 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6329 {
6330         struct ixgbe_hw *hw;
6331         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6332         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6333
6334         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6335
6336         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6337                 return -EINVAL;
6338
6339         /* refuse mtu that requires the support of scattered packets when this
6340          * feature has not been enabled before.
6341          */
6342         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6343             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6344              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6345                 return -EINVAL;
6346
6347         /*
6348          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6349          * request of the version 2.0 of the mailbox API.
6350          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6351          * of the mailbox API.
6352          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6353          * prior to 3.11.33 which contains the following change:
6354          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6355          */
6356         ixgbevf_rlpml_set_vf(hw, max_frame);
6357
6358         /* update max frame size */
6359         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6360         return 0;
6361 }
6362
6363 static inline struct ixgbe_5tuple_filter *
6364 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6365                         struct ixgbe_5tuple_filter_info *key)
6366 {
6367         struct ixgbe_5tuple_filter *it;
6368
6369         TAILQ_FOREACH(it, filter_list, entries) {
6370                 if (memcmp(key, &it->filter_info,
6371                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6372                         return it;
6373                 }
6374         }
6375         return NULL;
6376 }
6377
6378 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6379 static inline int
6380 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6381                         struct ixgbe_5tuple_filter_info *filter_info)
6382 {
6383         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6384                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6385                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6386                 return -EINVAL;
6387
6388         switch (filter->dst_ip_mask) {
6389         case UINT32_MAX:
6390                 filter_info->dst_ip_mask = 0;
6391                 filter_info->dst_ip = filter->dst_ip;
6392                 break;
6393         case 0:
6394                 filter_info->dst_ip_mask = 1;
6395                 break;
6396         default:
6397                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6398                 return -EINVAL;
6399         }
6400
6401         switch (filter->src_ip_mask) {
6402         case UINT32_MAX:
6403                 filter_info->src_ip_mask = 0;
6404                 filter_info->src_ip = filter->src_ip;
6405                 break;
6406         case 0:
6407                 filter_info->src_ip_mask = 1;
6408                 break;
6409         default:
6410                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6411                 return -EINVAL;
6412         }
6413
6414         switch (filter->dst_port_mask) {
6415         case UINT16_MAX:
6416                 filter_info->dst_port_mask = 0;
6417                 filter_info->dst_port = filter->dst_port;
6418                 break;
6419         case 0:
6420                 filter_info->dst_port_mask = 1;
6421                 break;
6422         default:
6423                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6424                 return -EINVAL;
6425         }
6426
6427         switch (filter->src_port_mask) {
6428         case UINT16_MAX:
6429                 filter_info->src_port_mask = 0;
6430                 filter_info->src_port = filter->src_port;
6431                 break;
6432         case 0:
6433                 filter_info->src_port_mask = 1;
6434                 break;
6435         default:
6436                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6437                 return -EINVAL;
6438         }
6439
6440         switch (filter->proto_mask) {
6441         case UINT8_MAX:
6442                 filter_info->proto_mask = 0;
6443                 filter_info->proto =
6444                         convert_protocol_type(filter->proto);
6445                 break;
6446         case 0:
6447                 filter_info->proto_mask = 1;
6448                 break;
6449         default:
6450                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6451                 return -EINVAL;
6452         }
6453
6454         filter_info->priority = (uint8_t)filter->priority;
6455         return 0;
6456 }
6457
6458 /*
6459  * add or delete a ntuple filter
6460  *
6461  * @param
6462  * dev: Pointer to struct rte_eth_dev.
6463  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6464  * add: if true, add filter, if false, remove filter
6465  *
6466  * @return
6467  *    - On success, zero.
6468  *    - On failure, a negative value.
6469  */
6470 int
6471 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6472                         struct rte_eth_ntuple_filter *ntuple_filter,
6473                         bool add)
6474 {
6475         struct ixgbe_filter_info *filter_info =
6476                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6477         struct ixgbe_5tuple_filter_info filter_5tuple;
6478         struct ixgbe_5tuple_filter *filter;
6479         int ret;
6480
6481         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6482                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6483                 return -EINVAL;
6484         }
6485
6486         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6487         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6488         if (ret < 0)
6489                 return ret;
6490
6491         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6492                                          &filter_5tuple);
6493         if (filter != NULL && add) {
6494                 PMD_DRV_LOG(ERR, "filter exists.");
6495                 return -EEXIST;
6496         }
6497         if (filter == NULL && !add) {
6498                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6499                 return -ENOENT;
6500         }
6501
6502         if (add) {
6503                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6504                                 sizeof(struct ixgbe_5tuple_filter), 0);
6505                 if (filter == NULL)
6506                         return -ENOMEM;
6507                 rte_memcpy(&filter->filter_info,
6508                                  &filter_5tuple,
6509                                  sizeof(struct ixgbe_5tuple_filter_info));
6510                 filter->queue = ntuple_filter->queue;
6511                 ret = ixgbe_add_5tuple_filter(dev, filter);
6512                 if (ret < 0) {
6513                         rte_free(filter);
6514                         return ret;
6515                 }
6516         } else
6517                 ixgbe_remove_5tuple_filter(dev, filter);
6518
6519         return 0;
6520 }
6521
6522 /*
6523  * get a ntuple filter
6524  *
6525  * @param
6526  * dev: Pointer to struct rte_eth_dev.
6527  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6528  *
6529  * @return
6530  *    - On success, zero.
6531  *    - On failure, a negative value.
6532  */
6533 static int
6534 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6535                         struct rte_eth_ntuple_filter *ntuple_filter)
6536 {
6537         struct ixgbe_filter_info *filter_info =
6538                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6539         struct ixgbe_5tuple_filter_info filter_5tuple;
6540         struct ixgbe_5tuple_filter *filter;
6541         int ret;
6542
6543         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6544                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6545                 return -EINVAL;
6546         }
6547
6548         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6549         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6550         if (ret < 0)
6551                 return ret;
6552
6553         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6554                                          &filter_5tuple);
6555         if (filter == NULL) {
6556                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6557                 return -ENOENT;
6558         }
6559         ntuple_filter->queue = filter->queue;
6560         return 0;
6561 }
6562
6563 /*
6564  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6565  * @dev: pointer to rte_eth_dev structure
6566  * @filter_op:operation will be taken.
6567  * @arg: a pointer to specific structure corresponding to the filter_op
6568  *
6569  * @return
6570  *    - On success, zero.
6571  *    - On failure, a negative value.
6572  */
6573 static int
6574 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6575                                 enum rte_filter_op filter_op,
6576                                 void *arg)
6577 {
6578         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6579         int ret;
6580
6581         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6582
6583         if (filter_op == RTE_ETH_FILTER_NOP)
6584                 return 0;
6585
6586         if (arg == NULL) {
6587                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6588                             filter_op);
6589                 return -EINVAL;
6590         }
6591
6592         switch (filter_op) {
6593         case RTE_ETH_FILTER_ADD:
6594                 ret = ixgbe_add_del_ntuple_filter(dev,
6595                         (struct rte_eth_ntuple_filter *)arg,
6596                         TRUE);
6597                 break;
6598         case RTE_ETH_FILTER_DELETE:
6599                 ret = ixgbe_add_del_ntuple_filter(dev,
6600                         (struct rte_eth_ntuple_filter *)arg,
6601                         FALSE);
6602                 break;
6603         case RTE_ETH_FILTER_GET:
6604                 ret = ixgbe_get_ntuple_filter(dev,
6605                         (struct rte_eth_ntuple_filter *)arg);
6606                 break;
6607         default:
6608                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6609                 ret = -EINVAL;
6610                 break;
6611         }
6612         return ret;
6613 }
6614
6615 int
6616 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6617                         struct rte_eth_ethertype_filter *filter,
6618                         bool add)
6619 {
6620         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6621         struct ixgbe_filter_info *filter_info =
6622                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6623         uint32_t etqf = 0;
6624         uint32_t etqs = 0;
6625         int ret;
6626         struct ixgbe_ethertype_filter ethertype_filter;
6627
6628         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6629                 return -EINVAL;
6630
6631         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6632                 filter->ether_type == ETHER_TYPE_IPv6) {
6633                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6634                         " ethertype filter.", filter->ether_type);
6635                 return -EINVAL;
6636         }
6637
6638         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6639                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6640                 return -EINVAL;
6641         }
6642         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6643                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6644                 return -EINVAL;
6645         }
6646
6647         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6648         if (ret >= 0 && add) {
6649                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6650                             filter->ether_type);
6651                 return -EEXIST;
6652         }
6653         if (ret < 0 && !add) {
6654                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6655                             filter->ether_type);
6656                 return -ENOENT;
6657         }
6658
6659         if (add) {
6660                 etqf = IXGBE_ETQF_FILTER_EN;
6661                 etqf |= (uint32_t)filter->ether_type;
6662                 etqs |= (uint32_t)((filter->queue <<
6663                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6664                                     IXGBE_ETQS_RX_QUEUE);
6665                 etqs |= IXGBE_ETQS_QUEUE_EN;
6666
6667                 ethertype_filter.ethertype = filter->ether_type;
6668                 ethertype_filter.etqf = etqf;
6669                 ethertype_filter.etqs = etqs;
6670                 ethertype_filter.conf = FALSE;
6671                 ret = ixgbe_ethertype_filter_insert(filter_info,
6672                                                     &ethertype_filter);
6673                 if (ret < 0) {
6674                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6675                         return -ENOSPC;
6676                 }
6677         } else {
6678                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6679                 if (ret < 0)
6680                         return -ENOSYS;
6681         }
6682         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6683         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6684         IXGBE_WRITE_FLUSH(hw);
6685
6686         return 0;
6687 }
6688
6689 static int
6690 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6691                         struct rte_eth_ethertype_filter *filter)
6692 {
6693         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6694         struct ixgbe_filter_info *filter_info =
6695                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6696         uint32_t etqf, etqs;
6697         int ret;
6698
6699         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6700         if (ret < 0) {
6701                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6702                             filter->ether_type);
6703                 return -ENOENT;
6704         }
6705
6706         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6707         if (etqf & IXGBE_ETQF_FILTER_EN) {
6708                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6709                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6710                 filter->flags = 0;
6711                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6712                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6713                 return 0;
6714         }
6715         return -ENOENT;
6716 }
6717
6718 /*
6719  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6720  * @dev: pointer to rte_eth_dev structure
6721  * @filter_op:operation will be taken.
6722  * @arg: a pointer to specific structure corresponding to the filter_op
6723  */
6724 static int
6725 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6726                                 enum rte_filter_op filter_op,
6727                                 void *arg)
6728 {
6729         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6730         int ret;
6731
6732         MAC_TYPE_FILTER_SUP(hw->mac.type);
6733
6734         if (filter_op == RTE_ETH_FILTER_NOP)
6735                 return 0;
6736
6737         if (arg == NULL) {
6738                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6739                             filter_op);
6740                 return -EINVAL;
6741         }
6742
6743         switch (filter_op) {
6744         case RTE_ETH_FILTER_ADD:
6745                 ret = ixgbe_add_del_ethertype_filter(dev,
6746                         (struct rte_eth_ethertype_filter *)arg,
6747                         TRUE);
6748                 break;
6749         case RTE_ETH_FILTER_DELETE:
6750                 ret = ixgbe_add_del_ethertype_filter(dev,
6751                         (struct rte_eth_ethertype_filter *)arg,
6752                         FALSE);
6753                 break;
6754         case RTE_ETH_FILTER_GET:
6755                 ret = ixgbe_get_ethertype_filter(dev,
6756                         (struct rte_eth_ethertype_filter *)arg);
6757                 break;
6758         default:
6759                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6760                 ret = -EINVAL;
6761                 break;
6762         }
6763         return ret;
6764 }
6765
6766 static int
6767 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6768                      enum rte_filter_type filter_type,
6769                      enum rte_filter_op filter_op,
6770                      void *arg)
6771 {
6772         int ret = 0;
6773
6774         switch (filter_type) {
6775         case RTE_ETH_FILTER_NTUPLE:
6776                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6777                 break;
6778         case RTE_ETH_FILTER_ETHERTYPE:
6779                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6780                 break;
6781         case RTE_ETH_FILTER_SYN:
6782                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6783                 break;
6784         case RTE_ETH_FILTER_FDIR:
6785                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6786                 break;
6787         case RTE_ETH_FILTER_L2_TUNNEL:
6788                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6789                 break;
6790         case RTE_ETH_FILTER_GENERIC:
6791                 if (filter_op != RTE_ETH_FILTER_GET)
6792                         return -EINVAL;
6793                 *(const void **)arg = &ixgbe_flow_ops;
6794                 break;
6795         default:
6796                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6797                                                         filter_type);
6798                 ret = -EINVAL;
6799                 break;
6800         }
6801
6802         return ret;
6803 }
6804
6805 static u8 *
6806 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6807                         u8 **mc_addr_ptr, u32 *vmdq)
6808 {
6809         u8 *mc_addr;
6810
6811         *vmdq = 0;
6812         mc_addr = *mc_addr_ptr;
6813         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6814         return mc_addr;
6815 }
6816
6817 static int
6818 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6819                           struct ether_addr *mc_addr_set,
6820                           uint32_t nb_mc_addr)
6821 {
6822         struct ixgbe_hw *hw;
6823         u8 *mc_addr_list;
6824
6825         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6826         mc_addr_list = (u8 *)mc_addr_set;
6827         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6828                                          ixgbe_dev_addr_list_itr, TRUE);
6829 }
6830
6831 static uint64_t
6832 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6833 {
6834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6835         uint64_t systime_cycles;
6836
6837         switch (hw->mac.type) {
6838         case ixgbe_mac_X550:
6839         case ixgbe_mac_X550EM_x:
6840         case ixgbe_mac_X550EM_a:
6841                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6842                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6843                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6844                                 * NSEC_PER_SEC;
6845                 break;
6846         default:
6847                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6848                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6849                                 << 32;
6850         }
6851
6852         return systime_cycles;
6853 }
6854
6855 static uint64_t
6856 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6857 {
6858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6859         uint64_t rx_tstamp_cycles;
6860
6861         switch (hw->mac.type) {
6862         case ixgbe_mac_X550:
6863         case ixgbe_mac_X550EM_x:
6864         case ixgbe_mac_X550EM_a:
6865                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6866                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6867                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6868                                 * NSEC_PER_SEC;
6869                 break;
6870         default:
6871                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6872                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6873                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6874                                 << 32;
6875         }
6876
6877         return rx_tstamp_cycles;
6878 }
6879
6880 static uint64_t
6881 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6882 {
6883         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6884         uint64_t tx_tstamp_cycles;
6885
6886         switch (hw->mac.type) {
6887         case ixgbe_mac_X550:
6888         case ixgbe_mac_X550EM_x:
6889         case ixgbe_mac_X550EM_a:
6890                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6891                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6892                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6893                                 * NSEC_PER_SEC;
6894                 break;
6895         default:
6896                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6897                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6898                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6899                                 << 32;
6900         }
6901
6902         return tx_tstamp_cycles;
6903 }
6904
6905 static void
6906 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6907 {
6908         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6909         struct ixgbe_adapter *adapter =
6910                 (struct ixgbe_adapter *)dev->data->dev_private;
6911         struct rte_eth_link link;
6912         uint32_t incval = 0;
6913         uint32_t shift = 0;
6914
6915         /* Get current link speed. */
6916         ixgbe_dev_link_update(dev, 1);
6917         rte_eth_linkstatus_get(dev, &link);
6918
6919         switch (link.link_speed) {
6920         case ETH_SPEED_NUM_100M:
6921                 incval = IXGBE_INCVAL_100;
6922                 shift = IXGBE_INCVAL_SHIFT_100;
6923                 break;
6924         case ETH_SPEED_NUM_1G:
6925                 incval = IXGBE_INCVAL_1GB;
6926                 shift = IXGBE_INCVAL_SHIFT_1GB;
6927                 break;
6928         case ETH_SPEED_NUM_10G:
6929         default:
6930                 incval = IXGBE_INCVAL_10GB;
6931                 shift = IXGBE_INCVAL_SHIFT_10GB;
6932                 break;
6933         }
6934
6935         switch (hw->mac.type) {
6936         case ixgbe_mac_X550:
6937         case ixgbe_mac_X550EM_x:
6938         case ixgbe_mac_X550EM_a:
6939                 /* Independent of link speed. */
6940                 incval = 1;
6941                 /* Cycles read will be interpreted as ns. */
6942                 shift = 0;
6943                 /* Fall-through */
6944         case ixgbe_mac_X540:
6945                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6946                 break;
6947         case ixgbe_mac_82599EB:
6948                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6949                 shift -= IXGBE_INCVAL_SHIFT_82599;
6950                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6951                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6952                 break;
6953         default:
6954                 /* Not supported. */
6955                 return;
6956         }
6957
6958         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6959         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6960         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6961
6962         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6963         adapter->systime_tc.cc_shift = shift;
6964         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6965
6966         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6967         adapter->rx_tstamp_tc.cc_shift = shift;
6968         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6969
6970         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6971         adapter->tx_tstamp_tc.cc_shift = shift;
6972         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6973 }
6974
6975 static int
6976 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6977 {
6978         struct ixgbe_adapter *adapter =
6979                         (struct ixgbe_adapter *)dev->data->dev_private;
6980
6981         adapter->systime_tc.nsec += delta;
6982         adapter->rx_tstamp_tc.nsec += delta;
6983         adapter->tx_tstamp_tc.nsec += delta;
6984
6985         return 0;
6986 }
6987
6988 static int
6989 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6990 {
6991         uint64_t ns;
6992         struct ixgbe_adapter *adapter =
6993                         (struct ixgbe_adapter *)dev->data->dev_private;
6994
6995         ns = rte_timespec_to_ns(ts);
6996         /* Set the timecounters to a new value. */
6997         adapter->systime_tc.nsec = ns;
6998         adapter->rx_tstamp_tc.nsec = ns;
6999         adapter->tx_tstamp_tc.nsec = ns;
7000
7001         return 0;
7002 }
7003
7004 static int
7005 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7006 {
7007         uint64_t ns, systime_cycles;
7008         struct ixgbe_adapter *adapter =
7009                         (struct ixgbe_adapter *)dev->data->dev_private;
7010
7011         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7012         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7013         *ts = rte_ns_to_timespec(ns);
7014
7015         return 0;
7016 }
7017
7018 static int
7019 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7020 {
7021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7022         uint32_t tsync_ctl;
7023         uint32_t tsauxc;
7024
7025         /* Stop the timesync system time. */
7026         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7027         /* Reset the timesync system time value. */
7028         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7029         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7030
7031         /* Enable system time for platforms where it isn't on by default. */
7032         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7033         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7034         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7035
7036         ixgbe_start_timecounters(dev);
7037
7038         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7039         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7040                         (ETHER_TYPE_1588 |
7041                          IXGBE_ETQF_FILTER_EN |
7042                          IXGBE_ETQF_1588));
7043
7044         /* Enable timestamping of received PTP packets. */
7045         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7046         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7047         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7048
7049         /* Enable timestamping of transmitted PTP packets. */
7050         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7051         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7052         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7053
7054         IXGBE_WRITE_FLUSH(hw);
7055
7056         return 0;
7057 }
7058
7059 static int
7060 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7061 {
7062         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7063         uint32_t tsync_ctl;
7064
7065         /* Disable timestamping of transmitted PTP packets. */
7066         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7067         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7068         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7069
7070         /* Disable timestamping of received PTP packets. */
7071         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7072         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7073         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7074
7075         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7076         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7077
7078         /* Stop incrementating the System Time registers. */
7079         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7080
7081         return 0;
7082 }
7083
7084 static int
7085 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7086                                  struct timespec *timestamp,
7087                                  uint32_t flags __rte_unused)
7088 {
7089         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7090         struct ixgbe_adapter *adapter =
7091                 (struct ixgbe_adapter *)dev->data->dev_private;
7092         uint32_t tsync_rxctl;
7093         uint64_t rx_tstamp_cycles;
7094         uint64_t ns;
7095
7096         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7097         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7098                 return -EINVAL;
7099
7100         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7101         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7102         *timestamp = rte_ns_to_timespec(ns);
7103
7104         return  0;
7105 }
7106
7107 static int
7108 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7109                                  struct timespec *timestamp)
7110 {
7111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7112         struct ixgbe_adapter *adapter =
7113                 (struct ixgbe_adapter *)dev->data->dev_private;
7114         uint32_t tsync_txctl;
7115         uint64_t tx_tstamp_cycles;
7116         uint64_t ns;
7117
7118         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7119         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7120                 return -EINVAL;
7121
7122         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7123         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7124         *timestamp = rte_ns_to_timespec(ns);
7125
7126         return 0;
7127 }
7128
7129 static int
7130 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7131 {
7132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7133         int count = 0;
7134         int g_ind = 0;
7135         const struct reg_info *reg_group;
7136         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7137                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7138
7139         while ((reg_group = reg_set[g_ind++]))
7140                 count += ixgbe_regs_group_count(reg_group);
7141
7142         return count;
7143 }
7144
7145 static int
7146 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7147 {
7148         int count = 0;
7149         int g_ind = 0;
7150         const struct reg_info *reg_group;
7151
7152         while ((reg_group = ixgbevf_regs[g_ind++]))
7153                 count += ixgbe_regs_group_count(reg_group);
7154
7155         return count;
7156 }
7157
7158 static int
7159 ixgbe_get_regs(struct rte_eth_dev *dev,
7160               struct rte_dev_reg_info *regs)
7161 {
7162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7163         uint32_t *data = regs->data;
7164         int g_ind = 0;
7165         int count = 0;
7166         const struct reg_info *reg_group;
7167         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7168                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7169
7170         if (data == NULL) {
7171                 regs->length = ixgbe_get_reg_length(dev);
7172                 regs->width = sizeof(uint32_t);
7173                 return 0;
7174         }
7175
7176         /* Support only full register dump */
7177         if ((regs->length == 0) ||
7178             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7179                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7180                         hw->device_id;
7181                 while ((reg_group = reg_set[g_ind++]))
7182                         count += ixgbe_read_regs_group(dev, &data[count],
7183                                 reg_group);
7184                 return 0;
7185         }
7186
7187         return -ENOTSUP;
7188 }
7189
7190 static int
7191 ixgbevf_get_regs(struct rte_eth_dev *dev,
7192                 struct rte_dev_reg_info *regs)
7193 {
7194         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7195         uint32_t *data = regs->data;
7196         int g_ind = 0;
7197         int count = 0;
7198         const struct reg_info *reg_group;
7199
7200         if (data == NULL) {
7201                 regs->length = ixgbevf_get_reg_length(dev);
7202                 regs->width = sizeof(uint32_t);
7203                 return 0;
7204         }
7205
7206         /* Support only full register dump */
7207         if ((regs->length == 0) ||
7208             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7209                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7210                         hw->device_id;
7211                 while ((reg_group = ixgbevf_regs[g_ind++]))
7212                         count += ixgbe_read_regs_group(dev, &data[count],
7213                                                       reg_group);
7214                 return 0;
7215         }
7216
7217         return -ENOTSUP;
7218 }
7219
7220 static int
7221 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7222 {
7223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7224
7225         /* Return unit is byte count */
7226         return hw->eeprom.word_size * 2;
7227 }
7228
7229 static int
7230 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7231                 struct rte_dev_eeprom_info *in_eeprom)
7232 {
7233         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7234         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7235         uint16_t *data = in_eeprom->data;
7236         int first, length;
7237
7238         first = in_eeprom->offset >> 1;
7239         length = in_eeprom->length >> 1;
7240         if ((first > hw->eeprom.word_size) ||
7241             ((first + length) > hw->eeprom.word_size))
7242                 return -EINVAL;
7243
7244         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7245
7246         return eeprom->ops.read_buffer(hw, first, length, data);
7247 }
7248
7249 static int
7250 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7251                 struct rte_dev_eeprom_info *in_eeprom)
7252 {
7253         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7254         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7255         uint16_t *data = in_eeprom->data;
7256         int first, length;
7257
7258         first = in_eeprom->offset >> 1;
7259         length = in_eeprom->length >> 1;
7260         if ((first > hw->eeprom.word_size) ||
7261             ((first + length) > hw->eeprom.word_size))
7262                 return -EINVAL;
7263
7264         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7265
7266         return eeprom->ops.write_buffer(hw,  first, length, data);
7267 }
7268
7269 static int
7270 ixgbe_get_module_info(struct rte_eth_dev *dev,
7271                       struct rte_eth_dev_module_info *modinfo)
7272 {
7273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7274         uint32_t status;
7275         uint8_t sff8472_rev, addr_mode;
7276         bool page_swap = false;
7277
7278         /* Check whether we support SFF-8472 or not */
7279         status = hw->phy.ops.read_i2c_eeprom(hw,
7280                                              IXGBE_SFF_SFF_8472_COMP,
7281                                              &sff8472_rev);
7282         if (status != 0)
7283                 return -EIO;
7284
7285         /* addressing mode is not supported */
7286         status = hw->phy.ops.read_i2c_eeprom(hw,
7287                                              IXGBE_SFF_SFF_8472_SWAP,
7288                                              &addr_mode);
7289         if (status != 0)
7290                 return -EIO;
7291
7292         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7293                 PMD_DRV_LOG(ERR,
7294                             "Address change required to access page 0xA2, "
7295                             "but not supported. Please report the module "
7296                             "type to the driver maintainers.");
7297                 page_swap = true;
7298         }
7299
7300         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7301                 /* We have a SFP, but it does not support SFF-8472 */
7302                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7303                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7304         } else {
7305                 /* We have a SFP which supports a revision of SFF-8472. */
7306                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7307                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7308         }
7309
7310         return 0;
7311 }
7312
7313 static int
7314 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7315                         struct rte_dev_eeprom_info *info)
7316 {
7317         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7318         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7319         uint8_t databyte = 0xFF;
7320         uint8_t *data = info->data;
7321         uint32_t i = 0;
7322
7323         if (info->length == 0)
7324                 return -EINVAL;
7325
7326         for (i = info->offset; i < info->offset + info->length; i++) {
7327                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7328                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7329                 else
7330                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7331
7332                 if (status != 0)
7333                         return -EIO;
7334
7335                 data[i - info->offset] = databyte;
7336         }
7337
7338         return 0;
7339 }
7340
7341 uint16_t
7342 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7343         switch (mac_type) {
7344         case ixgbe_mac_X550:
7345         case ixgbe_mac_X550EM_x:
7346         case ixgbe_mac_X550EM_a:
7347                 return ETH_RSS_RETA_SIZE_512;
7348         case ixgbe_mac_X550_vf:
7349         case ixgbe_mac_X550EM_x_vf:
7350         case ixgbe_mac_X550EM_a_vf:
7351                 return ETH_RSS_RETA_SIZE_64;
7352         default:
7353                 return ETH_RSS_RETA_SIZE_128;
7354         }
7355 }
7356
7357 uint32_t
7358 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7359         switch (mac_type) {
7360         case ixgbe_mac_X550:
7361         case ixgbe_mac_X550EM_x:
7362         case ixgbe_mac_X550EM_a:
7363                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7364                         return IXGBE_RETA(reta_idx >> 2);
7365                 else
7366                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7367         case ixgbe_mac_X550_vf:
7368         case ixgbe_mac_X550EM_x_vf:
7369         case ixgbe_mac_X550EM_a_vf:
7370                 return IXGBE_VFRETA(reta_idx >> 2);
7371         default:
7372                 return IXGBE_RETA(reta_idx >> 2);
7373         }
7374 }
7375
7376 uint32_t
7377 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7378         switch (mac_type) {
7379         case ixgbe_mac_X550_vf:
7380         case ixgbe_mac_X550EM_x_vf:
7381         case ixgbe_mac_X550EM_a_vf:
7382                 return IXGBE_VFMRQC;
7383         default:
7384                 return IXGBE_MRQC;
7385         }
7386 }
7387
7388 uint32_t
7389 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7390         switch (mac_type) {
7391         case ixgbe_mac_X550_vf:
7392         case ixgbe_mac_X550EM_x_vf:
7393         case ixgbe_mac_X550EM_a_vf:
7394                 return IXGBE_VFRSSRK(i);
7395         default:
7396                 return IXGBE_RSSRK(i);
7397         }
7398 }
7399
7400 bool
7401 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7402         switch (mac_type) {
7403         case ixgbe_mac_82599_vf:
7404         case ixgbe_mac_X540_vf:
7405                 return 0;
7406         default:
7407                 return 1;
7408         }
7409 }
7410
7411 static int
7412 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7413                         struct rte_eth_dcb_info *dcb_info)
7414 {
7415         struct ixgbe_dcb_config *dcb_config =
7416                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7417         struct ixgbe_dcb_tc_config *tc;
7418         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7419         uint8_t nb_tcs;
7420         uint8_t i, j;
7421
7422         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7423                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7424         else
7425                 dcb_info->nb_tcs = 1;
7426
7427         tc_queue = &dcb_info->tc_queue;
7428         nb_tcs = dcb_info->nb_tcs;
7429
7430         if (dcb_config->vt_mode) { /* vt is enabled*/
7431                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7432                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7433                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7434                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7435                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7436                         for (j = 0; j < nb_tcs; j++) {
7437                                 tc_queue->tc_rxq[0][j].base = j;
7438                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7439                                 tc_queue->tc_txq[0][j].base = j;
7440                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7441                         }
7442                 } else {
7443                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7444                                 for (j = 0; j < nb_tcs; j++) {
7445                                         tc_queue->tc_rxq[i][j].base =
7446                                                 i * nb_tcs + j;
7447                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7448                                         tc_queue->tc_txq[i][j].base =
7449                                                 i * nb_tcs + j;
7450                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7451                                 }
7452                         }
7453                 }
7454         } else { /* vt is disabled*/
7455                 struct rte_eth_dcb_rx_conf *rx_conf =
7456                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7457                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7458                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7459                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7460                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7461                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7462                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7463                         }
7464                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7465                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7466                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7467                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7468                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7469                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7470                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7471                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7472                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7473                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7474                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7475                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7476                         }
7477                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7478                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7479                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7480                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7481                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7482                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7483                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7484                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7485                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7486                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7487                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7488                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7489                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7490                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7491                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7492                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7493                 }
7494         }
7495         for (i = 0; i < dcb_info->nb_tcs; i++) {
7496                 tc = &dcb_config->tc_config[i];
7497                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7498         }
7499         return 0;
7500 }
7501
7502 /* Update e-tag ether type */
7503 static int
7504 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7505                             uint16_t ether_type)
7506 {
7507         uint32_t etag_etype;
7508
7509         if (hw->mac.type != ixgbe_mac_X550 &&
7510             hw->mac.type != ixgbe_mac_X550EM_x &&
7511             hw->mac.type != ixgbe_mac_X550EM_a) {
7512                 return -ENOTSUP;
7513         }
7514
7515         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7516         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7517         etag_etype |= ether_type;
7518         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7519         IXGBE_WRITE_FLUSH(hw);
7520
7521         return 0;
7522 }
7523
7524 /* Config l2 tunnel ether type */
7525 static int
7526 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7527                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7528 {
7529         int ret = 0;
7530         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7531         struct ixgbe_l2_tn_info *l2_tn_info =
7532                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7533
7534         if (l2_tunnel == NULL)
7535                 return -EINVAL;
7536
7537         switch (l2_tunnel->l2_tunnel_type) {
7538         case RTE_L2_TUNNEL_TYPE_E_TAG:
7539                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7540                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7541                 break;
7542         default:
7543                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7544                 ret = -EINVAL;
7545                 break;
7546         }
7547
7548         return ret;
7549 }
7550
7551 /* Enable e-tag tunnel */
7552 static int
7553 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7554 {
7555         uint32_t etag_etype;
7556
7557         if (hw->mac.type != ixgbe_mac_X550 &&
7558             hw->mac.type != ixgbe_mac_X550EM_x &&
7559             hw->mac.type != ixgbe_mac_X550EM_a) {
7560                 return -ENOTSUP;
7561         }
7562
7563         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7564         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7565         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7566         IXGBE_WRITE_FLUSH(hw);
7567
7568         return 0;
7569 }
7570
7571 /* Enable l2 tunnel */
7572 static int
7573 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7574                            enum rte_eth_tunnel_type l2_tunnel_type)
7575 {
7576         int ret = 0;
7577         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7578         struct ixgbe_l2_tn_info *l2_tn_info =
7579                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7580
7581         switch (l2_tunnel_type) {
7582         case RTE_L2_TUNNEL_TYPE_E_TAG:
7583                 l2_tn_info->e_tag_en = TRUE;
7584                 ret = ixgbe_e_tag_enable(hw);
7585                 break;
7586         default:
7587                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7588                 ret = -EINVAL;
7589                 break;
7590         }
7591
7592         return ret;
7593 }
7594
7595 /* Disable e-tag tunnel */
7596 static int
7597 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7598 {
7599         uint32_t etag_etype;
7600
7601         if (hw->mac.type != ixgbe_mac_X550 &&
7602             hw->mac.type != ixgbe_mac_X550EM_x &&
7603             hw->mac.type != ixgbe_mac_X550EM_a) {
7604                 return -ENOTSUP;
7605         }
7606
7607         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7608         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7609         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7610         IXGBE_WRITE_FLUSH(hw);
7611
7612         return 0;
7613 }
7614
7615 /* Disable l2 tunnel */
7616 static int
7617 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7618                             enum rte_eth_tunnel_type l2_tunnel_type)
7619 {
7620         int ret = 0;
7621         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7622         struct ixgbe_l2_tn_info *l2_tn_info =
7623                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7624
7625         switch (l2_tunnel_type) {
7626         case RTE_L2_TUNNEL_TYPE_E_TAG:
7627                 l2_tn_info->e_tag_en = FALSE;
7628                 ret = ixgbe_e_tag_disable(hw);
7629                 break;
7630         default:
7631                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7632                 ret = -EINVAL;
7633                 break;
7634         }
7635
7636         return ret;
7637 }
7638
7639 static int
7640 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7641                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7642 {
7643         int ret = 0;
7644         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7645         uint32_t i, rar_entries;
7646         uint32_t rar_low, rar_high;
7647
7648         if (hw->mac.type != ixgbe_mac_X550 &&
7649             hw->mac.type != ixgbe_mac_X550EM_x &&
7650             hw->mac.type != ixgbe_mac_X550EM_a) {
7651                 return -ENOTSUP;
7652         }
7653
7654         rar_entries = ixgbe_get_num_rx_addrs(hw);
7655
7656         for (i = 1; i < rar_entries; i++) {
7657                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7658                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7659                 if ((rar_high & IXGBE_RAH_AV) &&
7660                     (rar_high & IXGBE_RAH_ADTYPE) &&
7661                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7662                      l2_tunnel->tunnel_id)) {
7663                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7664                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7665
7666                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7667
7668                         return ret;
7669                 }
7670         }
7671
7672         return ret;
7673 }
7674
7675 static int
7676 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7677                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7678 {
7679         int ret = 0;
7680         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7681         uint32_t i, rar_entries;
7682         uint32_t rar_low, rar_high;
7683
7684         if (hw->mac.type != ixgbe_mac_X550 &&
7685             hw->mac.type != ixgbe_mac_X550EM_x &&
7686             hw->mac.type != ixgbe_mac_X550EM_a) {
7687                 return -ENOTSUP;
7688         }
7689
7690         /* One entry for one tunnel. Try to remove potential existing entry. */
7691         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7692
7693         rar_entries = ixgbe_get_num_rx_addrs(hw);
7694
7695         for (i = 1; i < rar_entries; i++) {
7696                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7697                 if (rar_high & IXGBE_RAH_AV) {
7698                         continue;
7699                 } else {
7700                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7701                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7702                         rar_low = l2_tunnel->tunnel_id;
7703
7704                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7705                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7706
7707                         return ret;
7708                 }
7709         }
7710
7711         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7712                      " Please remove a rule before adding a new one.");
7713         return -EINVAL;
7714 }
7715
7716 static inline struct ixgbe_l2_tn_filter *
7717 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7718                           struct ixgbe_l2_tn_key *key)
7719 {
7720         int ret;
7721
7722         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7723         if (ret < 0)
7724                 return NULL;
7725
7726         return l2_tn_info->hash_map[ret];
7727 }
7728
7729 static inline int
7730 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7731                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7732 {
7733         int ret;
7734
7735         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7736                                &l2_tn_filter->key);
7737
7738         if (ret < 0) {
7739                 PMD_DRV_LOG(ERR,
7740                             "Failed to insert L2 tunnel filter"
7741                             " to hash table %d!",
7742                             ret);
7743                 return ret;
7744         }
7745
7746         l2_tn_info->hash_map[ret] = l2_tn_filter;
7747
7748         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7749
7750         return 0;
7751 }
7752
7753 static inline int
7754 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7755                           struct ixgbe_l2_tn_key *key)
7756 {
7757         int ret;
7758         struct ixgbe_l2_tn_filter *l2_tn_filter;
7759
7760         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7761
7762         if (ret < 0) {
7763                 PMD_DRV_LOG(ERR,
7764                             "No such L2 tunnel filter to delete %d!",
7765                             ret);
7766                 return ret;
7767         }
7768
7769         l2_tn_filter = l2_tn_info->hash_map[ret];
7770         l2_tn_info->hash_map[ret] = NULL;
7771
7772         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7773         rte_free(l2_tn_filter);
7774
7775         return 0;
7776 }
7777
7778 /* Add l2 tunnel filter */
7779 int
7780 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7781                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7782                                bool restore)
7783 {
7784         int ret;
7785         struct ixgbe_l2_tn_info *l2_tn_info =
7786                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7787         struct ixgbe_l2_tn_key key;
7788         struct ixgbe_l2_tn_filter *node;
7789
7790         if (!restore) {
7791                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7792                 key.tn_id = l2_tunnel->tunnel_id;
7793
7794                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7795
7796                 if (node) {
7797                         PMD_DRV_LOG(ERR,
7798                                     "The L2 tunnel filter already exists!");
7799                         return -EINVAL;
7800                 }
7801
7802                 node = rte_zmalloc("ixgbe_l2_tn",
7803                                    sizeof(struct ixgbe_l2_tn_filter),
7804                                    0);
7805                 if (!node)
7806                         return -ENOMEM;
7807
7808                 rte_memcpy(&node->key,
7809                                  &key,
7810                                  sizeof(struct ixgbe_l2_tn_key));
7811                 node->pool = l2_tunnel->pool;
7812                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7813                 if (ret < 0) {
7814                         rte_free(node);
7815                         return ret;
7816                 }
7817         }
7818
7819         switch (l2_tunnel->l2_tunnel_type) {
7820         case RTE_L2_TUNNEL_TYPE_E_TAG:
7821                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7822                 break;
7823         default:
7824                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7825                 ret = -EINVAL;
7826                 break;
7827         }
7828
7829         if ((!restore) && (ret < 0))
7830                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7831
7832         return ret;
7833 }
7834
7835 /* Delete l2 tunnel filter */
7836 int
7837 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7838                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7839 {
7840         int ret;
7841         struct ixgbe_l2_tn_info *l2_tn_info =
7842                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7843         struct ixgbe_l2_tn_key key;
7844
7845         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7846         key.tn_id = l2_tunnel->tunnel_id;
7847         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7848         if (ret < 0)
7849                 return ret;
7850
7851         switch (l2_tunnel->l2_tunnel_type) {
7852         case RTE_L2_TUNNEL_TYPE_E_TAG:
7853                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7854                 break;
7855         default:
7856                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7857                 ret = -EINVAL;
7858                 break;
7859         }
7860
7861         return ret;
7862 }
7863
7864 /**
7865  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7866  * @dev: pointer to rte_eth_dev structure
7867  * @filter_op:operation will be taken.
7868  * @arg: a pointer to specific structure corresponding to the filter_op
7869  */
7870 static int
7871 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7872                                   enum rte_filter_op filter_op,
7873                                   void *arg)
7874 {
7875         int ret;
7876
7877         if (filter_op == RTE_ETH_FILTER_NOP)
7878                 return 0;
7879
7880         if (arg == NULL) {
7881                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7882                             filter_op);
7883                 return -EINVAL;
7884         }
7885
7886         switch (filter_op) {
7887         case RTE_ETH_FILTER_ADD:
7888                 ret = ixgbe_dev_l2_tunnel_filter_add
7889                         (dev,
7890                          (struct rte_eth_l2_tunnel_conf *)arg,
7891                          FALSE);
7892                 break;
7893         case RTE_ETH_FILTER_DELETE:
7894                 ret = ixgbe_dev_l2_tunnel_filter_del
7895                         (dev,
7896                          (struct rte_eth_l2_tunnel_conf *)arg);
7897                 break;
7898         default:
7899                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7900                 ret = -EINVAL;
7901                 break;
7902         }
7903         return ret;
7904 }
7905
7906 static int
7907 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7908 {
7909         int ret = 0;
7910         uint32_t ctrl;
7911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7912
7913         if (hw->mac.type != ixgbe_mac_X550 &&
7914             hw->mac.type != ixgbe_mac_X550EM_x &&
7915             hw->mac.type != ixgbe_mac_X550EM_a) {
7916                 return -ENOTSUP;
7917         }
7918
7919         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7920         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7921         if (en)
7922                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7923         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7924
7925         return ret;
7926 }
7927
7928 /* Enable l2 tunnel forwarding */
7929 static int
7930 ixgbe_dev_l2_tunnel_forwarding_enable
7931         (struct rte_eth_dev *dev,
7932          enum rte_eth_tunnel_type l2_tunnel_type)
7933 {
7934         struct ixgbe_l2_tn_info *l2_tn_info =
7935                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7936         int ret = 0;
7937
7938         switch (l2_tunnel_type) {
7939         case RTE_L2_TUNNEL_TYPE_E_TAG:
7940                 l2_tn_info->e_tag_fwd_en = TRUE;
7941                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7942                 break;
7943         default:
7944                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7945                 ret = -EINVAL;
7946                 break;
7947         }
7948
7949         return ret;
7950 }
7951
7952 /* Disable l2 tunnel forwarding */
7953 static int
7954 ixgbe_dev_l2_tunnel_forwarding_disable
7955         (struct rte_eth_dev *dev,
7956          enum rte_eth_tunnel_type l2_tunnel_type)
7957 {
7958         struct ixgbe_l2_tn_info *l2_tn_info =
7959                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7960         int ret = 0;
7961
7962         switch (l2_tunnel_type) {
7963         case RTE_L2_TUNNEL_TYPE_E_TAG:
7964                 l2_tn_info->e_tag_fwd_en = FALSE;
7965                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7966                 break;
7967         default:
7968                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7969                 ret = -EINVAL;
7970                 break;
7971         }
7972
7973         return ret;
7974 }
7975
7976 static int
7977 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7978                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7979                              bool en)
7980 {
7981         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7982         int ret = 0;
7983         uint32_t vmtir, vmvir;
7984         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7985
7986         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7987                 PMD_DRV_LOG(ERR,
7988                             "VF id %u should be less than %u",
7989                             l2_tunnel->vf_id,
7990                             pci_dev->max_vfs);
7991                 return -EINVAL;
7992         }
7993
7994         if (hw->mac.type != ixgbe_mac_X550 &&
7995             hw->mac.type != ixgbe_mac_X550EM_x &&
7996             hw->mac.type != ixgbe_mac_X550EM_a) {
7997                 return -ENOTSUP;
7998         }
7999
8000         if (en)
8001                 vmtir = l2_tunnel->tunnel_id;
8002         else
8003                 vmtir = 0;
8004
8005         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8006
8007         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8008         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8009         if (en)
8010                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8011         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8012
8013         return ret;
8014 }
8015
8016 /* Enable l2 tunnel tag insertion */
8017 static int
8018 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8019                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8020 {
8021         int ret = 0;
8022
8023         switch (l2_tunnel->l2_tunnel_type) {
8024         case RTE_L2_TUNNEL_TYPE_E_TAG:
8025                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8026                 break;
8027         default:
8028                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8029                 ret = -EINVAL;
8030                 break;
8031         }
8032
8033         return ret;
8034 }
8035
8036 /* Disable l2 tunnel tag insertion */
8037 static int
8038 ixgbe_dev_l2_tunnel_insertion_disable
8039         (struct rte_eth_dev *dev,
8040          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8041 {
8042         int ret = 0;
8043
8044         switch (l2_tunnel->l2_tunnel_type) {
8045         case RTE_L2_TUNNEL_TYPE_E_TAG:
8046                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8047                 break;
8048         default:
8049                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8050                 ret = -EINVAL;
8051                 break;
8052         }
8053
8054         return ret;
8055 }
8056
8057 static int
8058 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8059                              bool en)
8060 {
8061         int ret = 0;
8062         uint32_t qde;
8063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8064
8065         if (hw->mac.type != ixgbe_mac_X550 &&
8066             hw->mac.type != ixgbe_mac_X550EM_x &&
8067             hw->mac.type != ixgbe_mac_X550EM_a) {
8068                 return -ENOTSUP;
8069         }
8070
8071         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8072         if (en)
8073                 qde |= IXGBE_QDE_STRIP_TAG;
8074         else
8075                 qde &= ~IXGBE_QDE_STRIP_TAG;
8076         qde &= ~IXGBE_QDE_READ;
8077         qde |= IXGBE_QDE_WRITE;
8078         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8079
8080         return ret;
8081 }
8082
8083 /* Enable l2 tunnel tag stripping */
8084 static int
8085 ixgbe_dev_l2_tunnel_stripping_enable
8086         (struct rte_eth_dev *dev,
8087          enum rte_eth_tunnel_type l2_tunnel_type)
8088 {
8089         int ret = 0;
8090
8091         switch (l2_tunnel_type) {
8092         case RTE_L2_TUNNEL_TYPE_E_TAG:
8093                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8094                 break;
8095         default:
8096                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8097                 ret = -EINVAL;
8098                 break;
8099         }
8100
8101         return ret;
8102 }
8103
8104 /* Disable l2 tunnel tag stripping */
8105 static int
8106 ixgbe_dev_l2_tunnel_stripping_disable
8107         (struct rte_eth_dev *dev,
8108          enum rte_eth_tunnel_type l2_tunnel_type)
8109 {
8110         int ret = 0;
8111
8112         switch (l2_tunnel_type) {
8113         case RTE_L2_TUNNEL_TYPE_E_TAG:
8114                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8115                 break;
8116         default:
8117                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8118                 ret = -EINVAL;
8119                 break;
8120         }
8121
8122         return ret;
8123 }
8124
8125 /* Enable/disable l2 tunnel offload functions */
8126 static int
8127 ixgbe_dev_l2_tunnel_offload_set
8128         (struct rte_eth_dev *dev,
8129          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8130          uint32_t mask,
8131          uint8_t en)
8132 {
8133         int ret = 0;
8134
8135         if (l2_tunnel == NULL)
8136                 return -EINVAL;
8137
8138         ret = -EINVAL;
8139         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8140                 if (en)
8141                         ret = ixgbe_dev_l2_tunnel_enable(
8142                                 dev,
8143                                 l2_tunnel->l2_tunnel_type);
8144                 else
8145                         ret = ixgbe_dev_l2_tunnel_disable(
8146                                 dev,
8147                                 l2_tunnel->l2_tunnel_type);
8148         }
8149
8150         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8151                 if (en)
8152                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8153                                 dev,
8154                                 l2_tunnel);
8155                 else
8156                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8157                                 dev,
8158                                 l2_tunnel);
8159         }
8160
8161         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8162                 if (en)
8163                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8164                                 dev,
8165                                 l2_tunnel->l2_tunnel_type);
8166                 else
8167                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8168                                 dev,
8169                                 l2_tunnel->l2_tunnel_type);
8170         }
8171
8172         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8173                 if (en)
8174                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8175                                 dev,
8176                                 l2_tunnel->l2_tunnel_type);
8177                 else
8178                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8179                                 dev,
8180                                 l2_tunnel->l2_tunnel_type);
8181         }
8182
8183         return ret;
8184 }
8185
8186 static int
8187 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8188                         uint16_t port)
8189 {
8190         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8191         IXGBE_WRITE_FLUSH(hw);
8192
8193         return 0;
8194 }
8195
8196 /* There's only one register for VxLAN UDP port.
8197  * So, we cannot add several ports. Will update it.
8198  */
8199 static int
8200 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8201                      uint16_t port)
8202 {
8203         if (port == 0) {
8204                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8205                 return -EINVAL;
8206         }
8207
8208         return ixgbe_update_vxlan_port(hw, port);
8209 }
8210
8211 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8212  * UDP port, it must have a value.
8213  * So, will reset it to the original value 0.
8214  */
8215 static int
8216 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8217                      uint16_t port)
8218 {
8219         uint16_t cur_port;
8220
8221         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8222
8223         if (cur_port != port) {
8224                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8225                 return -EINVAL;
8226         }
8227
8228         return ixgbe_update_vxlan_port(hw, 0);
8229 }
8230
8231 /* Add UDP tunneling port */
8232 static int
8233 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8234                               struct rte_eth_udp_tunnel *udp_tunnel)
8235 {
8236         int ret = 0;
8237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8238
8239         if (hw->mac.type != ixgbe_mac_X550 &&
8240             hw->mac.type != ixgbe_mac_X550EM_x &&
8241             hw->mac.type != ixgbe_mac_X550EM_a) {
8242                 return -ENOTSUP;
8243         }
8244
8245         if (udp_tunnel == NULL)
8246                 return -EINVAL;
8247
8248         switch (udp_tunnel->prot_type) {
8249         case RTE_TUNNEL_TYPE_VXLAN:
8250                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8251                 break;
8252
8253         case RTE_TUNNEL_TYPE_GENEVE:
8254         case RTE_TUNNEL_TYPE_TEREDO:
8255                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8256                 ret = -EINVAL;
8257                 break;
8258
8259         default:
8260                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8261                 ret = -EINVAL;
8262                 break;
8263         }
8264
8265         return ret;
8266 }
8267
8268 /* Remove UDP tunneling port */
8269 static int
8270 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8271                               struct rte_eth_udp_tunnel *udp_tunnel)
8272 {
8273         int ret = 0;
8274         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8275
8276         if (hw->mac.type != ixgbe_mac_X550 &&
8277             hw->mac.type != ixgbe_mac_X550EM_x &&
8278             hw->mac.type != ixgbe_mac_X550EM_a) {
8279                 return -ENOTSUP;
8280         }
8281
8282         if (udp_tunnel == NULL)
8283                 return -EINVAL;
8284
8285         switch (udp_tunnel->prot_type) {
8286         case RTE_TUNNEL_TYPE_VXLAN:
8287                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8288                 break;
8289         case RTE_TUNNEL_TYPE_GENEVE:
8290         case RTE_TUNNEL_TYPE_TEREDO:
8291                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8292                 ret = -EINVAL;
8293                 break;
8294         default:
8295                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8296                 ret = -EINVAL;
8297                 break;
8298         }
8299
8300         return ret;
8301 }
8302
8303 static void
8304 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8305 {
8306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8307
8308         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8309 }
8310
8311 static void
8312 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8313 {
8314         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8315
8316         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8317 }
8318
8319 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8320 {
8321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8322         u32 in_msg = 0;
8323
8324         /* peek the message first */
8325         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8326
8327         /* PF reset VF event */
8328         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8329                 /* dummy mbx read to ack pf */
8330                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8331                         return;
8332                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8333                                               NULL);
8334         }
8335 }
8336
8337 static int
8338 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8339 {
8340         uint32_t eicr;
8341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8342         struct ixgbe_interrupt *intr =
8343                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8344         ixgbevf_intr_disable(dev);
8345
8346         /* read-on-clear nic registers here */
8347         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8348         intr->flags = 0;
8349
8350         /* only one misc vector supported - mailbox */
8351         eicr &= IXGBE_VTEICR_MASK;
8352         if (eicr == IXGBE_MISC_VEC_ID)
8353                 intr->flags |= IXGBE_FLAG_MAILBOX;
8354
8355         return 0;
8356 }
8357
8358 static int
8359 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8360 {
8361         struct ixgbe_interrupt *intr =
8362                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8363
8364         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8365                 ixgbevf_mbx_process(dev);
8366                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8367         }
8368
8369         ixgbevf_intr_enable(dev);
8370
8371         return 0;
8372 }
8373
8374 static void
8375 ixgbevf_dev_interrupt_handler(void *param)
8376 {
8377         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8378
8379         ixgbevf_dev_interrupt_get_status(dev);
8380         ixgbevf_dev_interrupt_action(dev);
8381 }
8382
8383 /**
8384  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8385  *  @hw: pointer to hardware structure
8386  *
8387  *  Stops the transmit data path and waits for the HW to internally empty
8388  *  the Tx security block
8389  **/
8390 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8391 {
8392 #define IXGBE_MAX_SECTX_POLL 40
8393
8394         int i;
8395         int sectxreg;
8396
8397         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8398         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8399         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8400         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8401                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8402                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8403                         break;
8404                 /* Use interrupt-safe sleep just in case */
8405                 usec_delay(1000);
8406         }
8407
8408         /* For informational purposes only */
8409         if (i >= IXGBE_MAX_SECTX_POLL)
8410                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8411                          "path fully disabled.  Continuing with init.");
8412
8413         return IXGBE_SUCCESS;
8414 }
8415
8416 /**
8417  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8418  *  @hw: pointer to hardware structure
8419  *
8420  *  Enables the transmit data path.
8421  **/
8422 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8423 {
8424         uint32_t sectxreg;
8425
8426         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8427         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8428         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8429         IXGBE_WRITE_FLUSH(hw);
8430
8431         return IXGBE_SUCCESS;
8432 }
8433
8434 /* restore n-tuple filter */
8435 static inline void
8436 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8437 {
8438         struct ixgbe_filter_info *filter_info =
8439                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8440         struct ixgbe_5tuple_filter *node;
8441
8442         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8443                 ixgbe_inject_5tuple_filter(dev, node);
8444         }
8445 }
8446
8447 /* restore ethernet type filter */
8448 static inline void
8449 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8450 {
8451         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8452         struct ixgbe_filter_info *filter_info =
8453                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8454         int i;
8455
8456         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8457                 if (filter_info->ethertype_mask & (1 << i)) {
8458                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8459                                         filter_info->ethertype_filters[i].etqf);
8460                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8461                                         filter_info->ethertype_filters[i].etqs);
8462                         IXGBE_WRITE_FLUSH(hw);
8463                 }
8464         }
8465 }
8466
8467 /* restore SYN filter */
8468 static inline void
8469 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8470 {
8471         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8472         struct ixgbe_filter_info *filter_info =
8473                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8474         uint32_t synqf;
8475
8476         synqf = filter_info->syn_info;
8477
8478         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8479                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8480                 IXGBE_WRITE_FLUSH(hw);
8481         }
8482 }
8483
8484 /* restore L2 tunnel filter */
8485 static inline void
8486 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8487 {
8488         struct ixgbe_l2_tn_info *l2_tn_info =
8489                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8490         struct ixgbe_l2_tn_filter *node;
8491         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8492
8493         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8494                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8495                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8496                 l2_tn_conf.pool           = node->pool;
8497                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8498         }
8499 }
8500
8501 /* restore rss filter */
8502 static inline void
8503 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8504 {
8505         struct ixgbe_filter_info *filter_info =
8506                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8507
8508         if (filter_info->rss_info.conf.queue_num)
8509                 ixgbe_config_rss_filter(dev,
8510                         &filter_info->rss_info, TRUE);
8511 }
8512
8513 static int
8514 ixgbe_filter_restore(struct rte_eth_dev *dev)
8515 {
8516         ixgbe_ntuple_filter_restore(dev);
8517         ixgbe_ethertype_filter_restore(dev);
8518         ixgbe_syn_filter_restore(dev);
8519         ixgbe_fdir_filter_restore(dev);
8520         ixgbe_l2_tn_filter_restore(dev);
8521         ixgbe_rss_filter_restore(dev);
8522
8523         return 0;
8524 }
8525
8526 static void
8527 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8528 {
8529         struct ixgbe_l2_tn_info *l2_tn_info =
8530                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8531         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8532
8533         if (l2_tn_info->e_tag_en)
8534                 (void)ixgbe_e_tag_enable(hw);
8535
8536         if (l2_tn_info->e_tag_fwd_en)
8537                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8538
8539         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8540 }
8541
8542 /* remove all the n-tuple filters */
8543 void
8544 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8545 {
8546         struct ixgbe_filter_info *filter_info =
8547                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8548         struct ixgbe_5tuple_filter *p_5tuple;
8549
8550         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8551                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8552 }
8553
8554 /* remove all the ether type filters */
8555 void
8556 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8557 {
8558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8559         struct ixgbe_filter_info *filter_info =
8560                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8561         int i;
8562
8563         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8564                 if (filter_info->ethertype_mask & (1 << i) &&
8565                     !filter_info->ethertype_filters[i].conf) {
8566                         (void)ixgbe_ethertype_filter_remove(filter_info,
8567                                                             (uint8_t)i);
8568                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8569                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8570                         IXGBE_WRITE_FLUSH(hw);
8571                 }
8572         }
8573 }
8574
8575 /* remove the SYN filter */
8576 void
8577 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8578 {
8579         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8580         struct ixgbe_filter_info *filter_info =
8581                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8582
8583         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8584                 filter_info->syn_info = 0;
8585
8586                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8587                 IXGBE_WRITE_FLUSH(hw);
8588         }
8589 }
8590
8591 /* remove all the L2 tunnel filters */
8592 int
8593 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8594 {
8595         struct ixgbe_l2_tn_info *l2_tn_info =
8596                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8597         struct ixgbe_l2_tn_filter *l2_tn_filter;
8598         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8599         int ret = 0;
8600
8601         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8602                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8603                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8604                 l2_tn_conf.pool           = l2_tn_filter->pool;
8605                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8606                 if (ret < 0)
8607                         return ret;
8608         }
8609
8610         return 0;
8611 }
8612
8613 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8614 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8615 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8616 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8617 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8618 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8619
8620 RTE_INIT(ixgbe_init_log)
8621 {
8622         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8623         if (ixgbe_logtype_init >= 0)
8624                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8625         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8626         if (ixgbe_logtype_driver >= 0)
8627                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8628 }