drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64 #include <rte_hash_crc.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 158 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 168 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static int
 186 ixgbe_dev_xstats_get_by_ids(struct rte_eth_dev *dev, uint64_t *ids,
 187                 uint64_t *values, unsigned int n);
 188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 193         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 194 static int ixgbe_dev_xstats_get_names_by_ids(
 195         __rte_unused struct rte_eth_dev *dev,
 196         struct rte_eth_xstat_name *xstats_names,
 197         uint64_t *ids,
 198         unsigned int limit);
 199 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 200                                              uint16_t queue_id,
 201                                              uint8_t stat_idx,
 202                                              uint8_t is_rx);
 203 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 204                                  size_t fw_size);
 205 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 206                                struct rte_eth_dev_info *dev_info);
 207 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 208 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 209                                  struct rte_eth_dev_info *dev_info);
 210 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 211
 212 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 213                 uint16_t vlan_id, int on);
 214 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 215                                enum rte_vlan_type vlan_type,
 216                                uint16_t tpid_id);
 217 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 218                 uint16_t queue, bool on);
 219 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 220                 int on);
 221 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 222 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 223 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 225 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 226
 227 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 229 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_fc_conf *fc_conf);
 231 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 232                                struct rte_eth_fc_conf *fc_conf);
 233 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 234                 struct rte_eth_pfc_conf *pfc_conf);
 235 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 236                         struct rte_eth_rss_reta_entry64 *reta_conf,
 237                         uint16_t reta_size);
 238 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 239                         struct rte_eth_rss_reta_entry64 *reta_conf,
 240                         uint16_t reta_size);
 241 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 242 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 247                                       struct rte_intr_handle *handle);
 248 static void ixgbe_dev_interrupt_handler(void *param);
 249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 250 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 251                 uint32_t index, uint32_t pool);
 252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 254                                            struct ether_addr *mac_addr);
 255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 256 static bool is_device_supported(struct rte_eth_dev *dev,
 257                                 struct rte_pci_driver *drv);
 258
 259 /* For Virtual Function support */
 260 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 261 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 262 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 263 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 266 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 267 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 268 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 269                 struct rte_eth_stats *stats);
 270 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 271 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 272                 uint16_t vlan_id, int on);
 273 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 274                 uint16_t queue, int on);
 275 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 276 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 277 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 278                                             uint16_t queue_id);
 279 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 280                                              uint16_t queue_id);
 281 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 282                                  uint8_t queue, uint8_t msix_vector);
 283 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 284 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 285 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 286
 287 /* For Eth VMDQ APIs support */
 288 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 289                 ether_addr * mac_addr, uint8_t on);
 290 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 291 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 292                 struct rte_eth_mirror_conf *mirror_conf,
 293                 uint8_t rule_id, uint8_t on);
 294 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 295                 uint8_t rule_id);
 296 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 297                                           uint16_t queue_id);
 298 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 299                                            uint16_t queue_id);
 300 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 301                                uint8_t queue, uint8_t msix_vector);
 302 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 303
 304 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 305                 uint16_t queue_idx, uint16_t tx_rate);
 306
 307 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 308                                  struct ether_addr *mac_addr,
 309                                  uint32_t index, uint32_t pool);
 310 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 311 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 312                                              struct ether_addr *mac_addr);
 313 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 314                         struct rte_eth_syn_filter *filter);
 315 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 316                         enum rte_filter_op filter_op,
 317                         void *arg);
 318 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 319                         struct ixgbe_5tuple_filter *filter);
 320 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ntuple_filter *filter);
 327 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 328                                 enum rte_filter_op filter_op,
 329                                 void *arg);
 330 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 331                         struct rte_eth_ethertype_filter *filter);
 332 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 333                      enum rte_filter_type filter_type,
 334                      enum rte_filter_op filter_op,
 335                      void *arg);
 336 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 337
 338 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 339                                       struct ether_addr *mc_addr_set,
 340                                       uint32_t nb_mc_addr);
 341 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 342                                    struct rte_eth_dcb_info *dcb_info);
 343
 344 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 345 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 346                             struct rte_dev_reg_info *regs);
 347 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 348 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 349                                 struct rte_dev_eeprom_info *eeprom);
 350 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 351                                 struct rte_dev_eeprom_info *eeprom);
 352
 353 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 354 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 355                                 struct rte_dev_reg_info *regs);
 356
 357 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 358 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 359 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 360                                             struct timespec *timestamp,
 361                                             uint32_t flags);
 362 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 363                                             struct timespec *timestamp);
 364 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 365 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 366                                    struct timespec *timestamp);
 367 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 368                                    const struct timespec *timestamp);
 369 static void ixgbevf_dev_interrupt_handler(void *param);
 370
 371 static int ixgbe_dev_l2_tunnel_eth_type_conf
 372         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 373 static int ixgbe_dev_l2_tunnel_offload_set
 374         (struct rte_eth_dev *dev,
 375          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 376          uint32_t mask,
 377          uint8_t en);
 378 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 379                                              enum rte_filter_op filter_op,
 380                                              void *arg);
 381
 382 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 383                                          struct rte_eth_udp_tunnel *udp_tunnel);
 384 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 385                                          struct rte_eth_udp_tunnel *udp_tunnel);
 386 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 387 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 388
 389 /*
 390  * Define VF Stats MACRO for Non "cleared on read" register
 391  */
 392 #define UPDATE_VF_STAT(reg, last, cur)                          \
 393 {                                                               \
 394         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 395         cur += (latest - last) & UINT_MAX;                      \
 396         last = latest;                                          \
 397 }
 398
 399 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 400 {                                                                \
 401         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 402         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 403         u64 latest = ((new_msb << 32) | new_lsb);                \
 404         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 405         last = latest;                                           \
 406 }
 407
 408 #define IXGBE_SET_HWSTRIP(h, q) do {\
 409                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 410                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 411                 (h)->bitmap[idx] |= 1 << bit;\
 412         } while (0)
 413
 414 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 415                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 416                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 417                 (h)->bitmap[idx] &= ~(1 << bit);\
 418         } while (0)
 419
 420 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 421                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 422                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 423                 (r) = (h)->bitmap[idx] >> bit & 1;\
 424         } while (0)
 425
 426 /*
 427  * The set of PCI devices this driver supports
 428  */
 429 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 483 #ifdef RTE_NIC_BYPASS
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 485 #endif
 486         { .vendor_id = 0, /* sentinel */ },
 487 };
 488
 489 /*
 490  * The set of PCI devices this driver supports (for 82599 VF)
 491  */
 492 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 503         { .vendor_id = 0, /* sentinel */ },
 504 };
 505
 506 static const struct rte_eth_desc_lim rx_desc_lim = {
 507         .nb_max = IXGBE_MAX_RING_DESC,
 508         .nb_min = IXGBE_MIN_RING_DESC,
 509         .nb_align = IXGBE_RXD_ALIGN,
 510 };
 511
 512 static const struct rte_eth_desc_lim tx_desc_lim = {
 513         .nb_max = IXGBE_MAX_RING_DESC,
 514         .nb_min = IXGBE_MIN_RING_DESC,
 515         .nb_align = IXGBE_TXD_ALIGN,
 516         .nb_seg_max = IXGBE_TX_MAX_SEG,
 517         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 518 };
 519
 520 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 521         .dev_configure        = ixgbe_dev_configure,
 522         .dev_start            = ixgbe_dev_start,
 523         .dev_stop             = ixgbe_dev_stop,
 524         .dev_set_link_up    = ixgbe_dev_set_link_up,
 525         .dev_set_link_down  = ixgbe_dev_set_link_down,
 526         .dev_close            = ixgbe_dev_close,
 527         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 528         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 529         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 530         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 531         .link_update          = ixgbe_dev_link_update,
 532         .stats_get            = ixgbe_dev_stats_get,
 533         .xstats_get           = ixgbe_dev_xstats_get,
 534         .xstats_get_by_ids    = ixgbe_dev_xstats_get_by_ids,
 535         .stats_reset          = ixgbe_dev_stats_reset,
 536         .xstats_reset         = ixgbe_dev_xstats_reset,
 537         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 538         .xstats_get_names_by_ids = ixgbe_dev_xstats_get_names_by_ids,
 539         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 540         .fw_version_get       = ixgbe_fw_version_get,
 541         .dev_infos_get        = ixgbe_dev_info_get,
 542         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 543         .mtu_set              = ixgbe_dev_mtu_set,
 544         .vlan_filter_set      = ixgbe_vlan_filter_set,
 545         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 546         .vlan_offload_set     = ixgbe_vlan_offload_set,
 547         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 548         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 549         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 550         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 551         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 552         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 553         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 554         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 555         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 556         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 557         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 558         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 559         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 560         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 561         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 562         .dev_led_on           = ixgbe_dev_led_on,
 563         .dev_led_off          = ixgbe_dev_led_off,
 564         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 565         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 566         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 567         .mac_addr_add         = ixgbe_add_rar,
 568         .mac_addr_remove      = ixgbe_remove_rar,
 569         .mac_addr_set         = ixgbe_set_default_mac_addr,
 570         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 571         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 572         .mirror_rule_set      = ixgbe_mirror_rule_set,
 573         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 574         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 575         .reta_update          = ixgbe_dev_rss_reta_update,
 576         .reta_query           = ixgbe_dev_rss_reta_query,
 577 #ifdef RTE_NIC_BYPASS
 578         .bypass_init          = ixgbe_bypass_init,
 579         .bypass_state_set     = ixgbe_bypass_state_store,
 580         .bypass_state_show    = ixgbe_bypass_state_show,
 581         .bypass_event_set     = ixgbe_bypass_event_store,
 582         .bypass_event_show    = ixgbe_bypass_event_show,
 583         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 584         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 585         .bypass_ver_show      = ixgbe_bypass_ver_show,
 586         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 587 #endif /* RTE_NIC_BYPASS */
 588         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 589         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 590         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 591         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 592         .rxq_info_get         = ixgbe_rxq_info_get,
 593         .txq_info_get         = ixgbe_txq_info_get,
 594         .timesync_enable      = ixgbe_timesync_enable,
 595         .timesync_disable     = ixgbe_timesync_disable,
 596         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 597         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 598         .get_reg              = ixgbe_get_regs,
 599         .get_eeprom_length    = ixgbe_get_eeprom_length,
 600         .get_eeprom           = ixgbe_get_eeprom,
 601         .set_eeprom           = ixgbe_set_eeprom,
 602         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 603         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 604         .timesync_read_time   = ixgbe_timesync_read_time,
 605         .timesync_write_time  = ixgbe_timesync_write_time,
 606         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 607         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 608         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 609         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 610 };
 611
 612 /*
 613  * dev_ops for virtual function, bare necessities for basic vf
 614  * operation have been implemented
 615  */
 616 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 617         .dev_configure        = ixgbevf_dev_configure,
 618         .dev_start            = ixgbevf_dev_start,
 619         .dev_stop             = ixgbevf_dev_stop,
 620         .link_update          = ixgbe_dev_link_update,
 621         .stats_get            = ixgbevf_dev_stats_get,
 622         .xstats_get           = ixgbevf_dev_xstats_get,
 623         .stats_reset          = ixgbevf_dev_stats_reset,
 624         .xstats_reset         = ixgbevf_dev_stats_reset,
 625         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 626         .dev_close            = ixgbevf_dev_close,
 627         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 628         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 629         .dev_infos_get        = ixgbevf_dev_info_get,
 630         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 631         .mtu_set              = ixgbevf_dev_set_mtu,
 632         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 633         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 634         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 635         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 636         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 637         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 638         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 639         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 640         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 641         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 642         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 643         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 644         .mac_addr_add         = ixgbevf_add_mac_addr,
 645         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 646         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 647         .rxq_info_get         = ixgbe_rxq_info_get,
 648         .txq_info_get         = ixgbe_txq_info_get,
 649         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 650         .get_reg              = ixgbevf_get_regs,
 651         .reta_update          = ixgbe_dev_rss_reta_update,
 652         .reta_query           = ixgbe_dev_rss_reta_query,
 653         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 654         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 655 };
 656
 657 /* store statistics names and its offset in stats structure */
 658 struct rte_ixgbe_xstats_name_off {
 659         char name[RTE_ETH_XSTATS_NAME_SIZE];
 660         unsigned offset;
 661 };
 662
 663 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 664         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 665         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 666         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 667         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 668         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 669         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 670         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 671         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 672         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 673         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 674         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 675         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 676         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 677         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 678         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 679                 prc1023)},
 680         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 681                 prc1522)},
 682         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 683         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 684         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 685         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 686         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 687         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 688         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 689         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 690         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 691         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 692         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 693         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 694         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 695         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 696         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 697         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 698         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 699                 ptc1023)},
 700         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 701                 ptc1522)},
 702         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 703         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 704         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 705         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 706
 707         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirustat_add)},
 709         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 710                 fdirustat_remove)},
 711         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 712                 fdirfstat_fadd)},
 713         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 714                 fdirfstat_fremove)},
 715         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 716                 fdirmatch)},
 717         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 718                 fdirmiss)},
 719
 720         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 721         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 722         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 723                 fclast)},
 724         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 725         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 726         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 727         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 728         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 729                 fcoe_noddp)},
 730         {"rx_fcoe_no_direct_data_placement_ext_buff",
 731                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 732
 733         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 734                 lxontxc)},
 735         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 736                 lxonrxc)},
 737         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 738                 lxofftxc)},
 739         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 740                 lxoffrxc)},
 741         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 742 };
 743
 744 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 745                            sizeof(rte_ixgbe_stats_strings[0]))
 746
 747 /* MACsec statistics */
 748 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 749         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 750                 out_pkts_untagged)},
 751         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 752                 out_pkts_encrypted)},
 753         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 754                 out_pkts_protected)},
 755         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 756                 out_octets_encrypted)},
 757         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 758                 out_octets_protected)},
 759         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_untagged)},
 761         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_badtag)},
 763         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_nosci)},
 765         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_unknownsci)},
 767         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 768                 in_octets_decrypted)},
 769         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 770                 in_octets_validated)},
 771         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_unchecked)},
 773         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_delayed)},
 775         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_late)},
 777         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_ok)},
 779         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_invalid)},
 781         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 782                 in_pkts_notvalid)},
 783         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 784                 in_pkts_unusedsa)},
 785         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 786                 in_pkts_notusingsa)},
 787 };
 788
 789 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 790                            sizeof(rte_ixgbe_macsec_strings[0]))
 791
 792 /* Per-queue statistics */
 793 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 794         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 795         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 796         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 797         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 798 };
 799
 800 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 801                            sizeof(rte_ixgbe_rxq_strings[0]))
 802 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 803
 804 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 805         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 806         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 807         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 808                 pxon2offc)},
 809 };
 810
 811 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 812                            sizeof(rte_ixgbe_txq_strings[0]))
 813 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 814
 815 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 816         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 817 };
 818
 819 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 820                 sizeof(rte_ixgbevf_stats_strings[0]))
 821
 822 /**
 823  * Atomically reads the link status information from global
 824  * structure rte_eth_dev.
 825  *
 826  * @param dev
 827  *   - Pointer to the structure rte_eth_dev to read from.
 828  *   - Pointer to the buffer to be saved with the link status.
 829  *
 830  * @return
 831  *   - On success, zero.
 832  *   - On failure, negative value.
 833  */
 834 static inline int
 835 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 836                                 struct rte_eth_link *link)
 837 {
 838         struct rte_eth_link *dst = link;
 839         struct rte_eth_link *src = &(dev->data->dev_link);
 840
 841         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 842                                         *(uint64_t *)src) == 0)
 843                 return -1;
 844
 845         return 0;
 846 }
 847
 848 /**
 849  * Atomically writes the link status information into global
 850  * structure rte_eth_dev.
 851  *
 852  * @param dev
 853  *   - Pointer to the structure rte_eth_dev to read from.
 854  *   - Pointer to the buffer to be saved with the link status.
 855  *
 856  * @return
 857  *   - On success, zero.
 858  *   - On failure, negative value.
 859  */
 860 static inline int
 861 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 862                                 struct rte_eth_link *link)
 863 {
 864         struct rte_eth_link *dst = &(dev->data->dev_link);
 865         struct rte_eth_link *src = link;
 866
 867         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 868                                         *(uint64_t *)src) == 0)
 869                 return -1;
 870
 871         return 0;
 872 }
 873
 874 /*
 875  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 876  */
 877 static inline int
 878 ixgbe_is_sfp(struct ixgbe_hw *hw)
 879 {
 880         switch (hw->phy.type) {
 881         case ixgbe_phy_sfp_avago:
 882         case ixgbe_phy_sfp_ftl:
 883         case ixgbe_phy_sfp_intel:
 884         case ixgbe_phy_sfp_unknown:
 885         case ixgbe_phy_sfp_passive_tyco:
 886         case ixgbe_phy_sfp_passive_unknown:
 887                 return 1;
 888         default:
 889                 return 0;
 890         }
 891 }
 892
 893 static inline int32_t
 894 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 895 {
 896         uint32_t ctrl_ext;
 897         int32_t status;
 898
 899         status = ixgbe_reset_hw(hw);
 900
 901         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 902         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 903         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 904         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 905         IXGBE_WRITE_FLUSH(hw);
 906
 907         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 908                 status = IXGBE_SUCCESS;
 909         return status;
 910 }
 911
 912 static inline void
 913 ixgbe_enable_intr(struct rte_eth_dev *dev)
 914 {
 915         struct ixgbe_interrupt *intr =
 916                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 917         struct ixgbe_hw *hw =
 918                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 919
 920         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 921         IXGBE_WRITE_FLUSH(hw);
 922 }
 923
 924 /*
 925  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 926  */
 927 static void
 928 ixgbe_disable_intr(struct ixgbe_hw *hw)
 929 {
 930         PMD_INIT_FUNC_TRACE();
 931
 932         if (hw->mac.type == ixgbe_mac_82598EB) {
 933                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 934         } else {
 935                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 936                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 937                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 938         }
 939         IXGBE_WRITE_FLUSH(hw);
 940 }
 941
 942 /*
 943  * This function resets queue statistics mapping registers.
 944  * From Niantic datasheet, Initialization of Statistics section:
 945  * "...if software requires the queue counters, the RQSMR and TQSM registers
 946  * must be re-programmed following a device reset.
 947  */
 948 static void
 949 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 950 {
 951         uint32_t i;
 952
 953         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 954                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 955                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 956         }
 957 }
 958
 959
 960 static int
 961 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 962                                   uint16_t queue_id,
 963                                   uint8_t stat_idx,
 964                                   uint8_t is_rx)
 965 {
 966 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 967 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 968 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 969
 970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 971         struct ixgbe_stat_mapping_registers *stat_mappings =
 972                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 973         uint32_t qsmr_mask = 0;
 974         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 975         uint32_t q_map;
 976         uint8_t n, offset;
 977
 978         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 979                 (hw->mac.type != ixgbe_mac_X540) &&
 980                 (hw->mac.type != ixgbe_mac_X550) &&
 981                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 982                 (hw->mac.type != ixgbe_mac_X550EM_a))
 983                 return -ENOSYS;
 984
 985         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 986                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 987                      queue_id, stat_idx);
 988
 989         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 990         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 991                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 992                 return -EIO;
 993         }
 994         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 995
 996         /* Now clear any previous stat_idx set */
 997         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 998         if (!is_rx)
 999                 stat_mappings->tqsm[n] &= ~clearing_mask;
1000         else
1001                 stat_mappings->rqsmr[n] &= ~clearing_mask;
1002
1003         q_map = (uint32_t)stat_idx;
1004         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1005         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1006         if (!is_rx)
1007                 stat_mappings->tqsm[n] |= qsmr_mask;
1008         else
1009                 stat_mappings->rqsmr[n] |= qsmr_mask;
1010
1011         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1012                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1013                      queue_id, stat_idx);
1014         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1015                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1016
1017         /* Now write the mapping in the appropriate register */
1018         if (is_rx) {
1019                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1020                              stat_mappings->rqsmr[n], n);
1021                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1022         } else {
1023                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1024                              stat_mappings->tqsm[n], n);
1025                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1026         }
1027         return 0;
1028 }
1029
1030 static void
1031 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1032 {
1033         struct ixgbe_stat_mapping_registers *stat_mappings =
1034                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036         int i;
1037
1038         /* write whatever was in stat mapping table to the NIC */
1039         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1040                 /* rx */
1041                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1042
1043                 /* tx */
1044                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1045         }
1046 }
1047
1048 static void
1049 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1050 {
1051         uint8_t i;
1052         struct ixgbe_dcb_tc_config *tc;
1053         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1054
1055         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1056         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1057         for (i = 0; i < dcb_max_tc; i++) {
1058                 tc = &dcb_config->tc_config[i];
1059                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1060                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1061                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1062                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1063                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1064                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1065                 tc->pfc = ixgbe_dcb_pfc_disabled;
1066         }
1067
1068         /* Initialize default user to priority mapping, UPx->TC0 */
1069         tc = &dcb_config->tc_config[0];
1070         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1071         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1072         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1073                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1074                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1075         }
1076         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1077         dcb_config->pfc_mode_enable = false;
1078         dcb_config->vt_mode = true;
1079         dcb_config->round_robin_enable = false;
1080         /* support all DCB capabilities in 82599 */
1081         dcb_config->support.capabilities = 0xFF;
1082
1083         /*we only support 4 Tcs for X540, X550 */
1084         if (hw->mac.type == ixgbe_mac_X540 ||
1085                 hw->mac.type == ixgbe_mac_X550 ||
1086                 hw->mac.type == ixgbe_mac_X550EM_x ||
1087                 hw->mac.type == ixgbe_mac_X550EM_a) {
1088                 dcb_config->num_tcs.pg_tcs = 4;
1089                 dcb_config->num_tcs.pfc_tcs = 4;
1090         }
1091 }
1092
1093 /*
1094  * Ensure that all locks are released before first NVM or PHY access
1095  */
1096 static void
1097 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1098 {
1099         uint16_t mask;
1100
1101         /*
1102          * Phy lock should not fail in this early stage. If this is the case,
1103          * it is due to an improper exit of the application.
1104          * So force the release of the faulty lock. Release of common lock
1105          * is done automatically by swfw_sync function.
1106          */
1107         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1108         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1109                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1110         }
1111         ixgbe_release_swfw_semaphore(hw, mask);
1112
1113         /*
1114          * These ones are more tricky since they are common to all ports; but
1115          * swfw_sync retries last long enough (1s) to be almost sure that if
1116          * lock can not be taken it is due to an improper lock of the
1117          * semaphore.
1118          */
1119         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1120         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1121                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1122         }
1123         ixgbe_release_swfw_semaphore(hw, mask);
1124 }
1125
1126 /*
1127  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1128  * It returns 0 on success.
1129  */
1130 static int
1131 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1132 {
1133         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1134         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1135         struct ixgbe_hw *hw =
1136                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1137         struct ixgbe_vfta *shadow_vfta =
1138                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1139         struct ixgbe_hwstrip *hwstrip =
1140                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1141         struct ixgbe_dcb_config *dcb_config =
1142                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1143         struct ixgbe_filter_info *filter_info =
1144                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1145         struct ixgbe_bw_conf *bw_conf =
1146                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1147         uint32_t ctrl_ext;
1148         uint16_t csum;
1149         int diag, i;
1150
1151         PMD_INIT_FUNC_TRACE();
1152
1153         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1154         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1155         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1156         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1157
1158         /*
1159          * For secondary processes, we don't initialise any further as primary
1160          * has already done this work. Only check we don't need a different
1161          * RX and TX function.
1162          */
1163         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1164                 struct ixgbe_tx_queue *txq;
1165                 /* TX queue function in primary, set by last queue initialized
1166                  * Tx queue may not initialized by primary process
1167                  */
1168                 if (eth_dev->data->tx_queues) {
1169                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1170                         ixgbe_set_tx_function(eth_dev, txq);
1171                 } else {
1172                         /* Use default TX function if we get here */
1173                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1174                                      "Using default TX function.");
1175                 }
1176
1177                 ixgbe_set_rx_function(eth_dev);
1178
1179                 return 0;
1180         }
1181
1182         rte_eth_copy_pci_info(eth_dev, pci_dev);
1183         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1184
1185         /* Vendor and Device ID need to be set before init of shared code */
1186         hw->device_id = pci_dev->id.device_id;
1187         hw->vendor_id = pci_dev->id.vendor_id;
1188         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1189         hw->allow_unsupported_sfp = 1;
1190
1191         /* Initialize the shared code (base driver) */
1192 #ifdef RTE_NIC_BYPASS
1193         diag = ixgbe_bypass_init_shared_code(hw);
1194 #else
1195         diag = ixgbe_init_shared_code(hw);
1196 #endif /* RTE_NIC_BYPASS */
1197
1198         if (diag != IXGBE_SUCCESS) {
1199                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1200                 return -EIO;
1201         }
1202
1203         /* pick up the PCI bus settings for reporting later */
1204         ixgbe_get_bus_info(hw);
1205
1206         /* Unlock any pending hardware semaphore */
1207         ixgbe_swfw_lock_reset(hw);
1208
1209         /* Initialize DCB configuration*/
1210         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1211         ixgbe_dcb_init(hw, dcb_config);
1212         /* Get Hardware Flow Control setting */
1213         hw->fc.requested_mode = ixgbe_fc_full;
1214         hw->fc.current_mode = ixgbe_fc_full;
1215         hw->fc.pause_time = IXGBE_FC_PAUSE;
1216         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1217                 hw->fc.low_water[i] = IXGBE_FC_LO;
1218                 hw->fc.high_water[i] = IXGBE_FC_HI;
1219         }
1220         hw->fc.send_xon = 1;
1221
1222         /* Make sure we have a good EEPROM before we read from it */
1223         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1224         if (diag != IXGBE_SUCCESS) {
1225                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1226                 return -EIO;
1227         }
1228
1229 #ifdef RTE_NIC_BYPASS
1230         diag = ixgbe_bypass_init_hw(hw);
1231 #else
1232         diag = ixgbe_init_hw(hw);
1233 #endif /* RTE_NIC_BYPASS */
1234
1235         /*
1236          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1237          * is called too soon after the kernel driver unbinding/binding occurs.
1238          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1239          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1240          * also called. See ixgbe_identify_phy_82599(). The reason for the
1241          * failure is not known, and only occuts when virtualisation features
1242          * are disabled in the bios. A delay of 100ms  was found to be enough by
1243          * trial-and-error, and is doubled to be safe.
1244          */
1245         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1246                 rte_delay_ms(200);
1247                 diag = ixgbe_init_hw(hw);
1248         }
1249
1250         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1251                 diag = IXGBE_SUCCESS;
1252
1253         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1254                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1255                              "LOM.  Please be aware there may be issues associated "
1256                              "with your hardware.");
1257                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1258                              "please contact your Intel or hardware representative "
1259                              "who provided you with this hardware.");
1260         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1261                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1262         if (diag) {
1263                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1264                 return -EIO;
1265         }
1266
1267         /* Reset the hw statistics */
1268         ixgbe_dev_stats_reset(eth_dev);
1269
1270         /* disable interrupt */
1271         ixgbe_disable_intr(hw);
1272
1273         /* reset mappings for queue statistics hw counters*/
1274         ixgbe_reset_qstat_mappings(hw);
1275
1276         /* Allocate memory for storing MAC addresses */
1277         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1278                                                hw->mac.num_rar_entries, 0);
1279         if (eth_dev->data->mac_addrs == NULL) {
1280                 PMD_INIT_LOG(ERR,
1281                              "Failed to allocate %u bytes needed to store "
1282                              "MAC addresses",
1283                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1284                 return -ENOMEM;
1285         }
1286         /* Copy the permanent MAC address */
1287         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1288                         &eth_dev->data->mac_addrs[0]);
1289
1290         /* Allocate memory for storing hash filter MAC addresses */
1291         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1292                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1293         if (eth_dev->data->hash_mac_addrs == NULL) {
1294                 PMD_INIT_LOG(ERR,
1295                              "Failed to allocate %d bytes needed to store MAC addresses",
1296                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1297                 return -ENOMEM;
1298         }
1299
1300         /* initialize the vfta */
1301         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1302
1303         /* initialize the hw strip bitmap*/
1304         memset(hwstrip, 0, sizeof(*hwstrip));
1305
1306         /* initialize PF if max_vfs not zero */
1307         ixgbe_pf_host_init(eth_dev);
1308
1309         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1310         /* let hardware know driver is loaded */
1311         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1312         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1313         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1314         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1315         IXGBE_WRITE_FLUSH(hw);
1316
1317         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1318                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1319                              (int) hw->mac.type, (int) hw->phy.type,
1320                              (int) hw->phy.sfp_type);
1321         else
1322                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1323                              (int) hw->mac.type, (int) hw->phy.type);
1324
1325         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1326                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1327                      pci_dev->id.device_id);
1328
1329         rte_intr_callback_register(intr_handle,
1330                                    ixgbe_dev_interrupt_handler, eth_dev);
1331
1332         /* enable uio/vfio intr/eventfd mapping */
1333         rte_intr_enable(intr_handle);
1334
1335         /* enable support intr */
1336         ixgbe_enable_intr(eth_dev);
1337
1338         /* initialize filter info */
1339         memset(filter_info, 0,
1340                sizeof(struct ixgbe_filter_info));
1341
1342         /* initialize 5tuple filter list */
1343         TAILQ_INIT(&filter_info->fivetuple_list);
1344
1345         /* initialize flow director filter list & hash */
1346         ixgbe_fdir_filter_init(eth_dev);
1347
1348         /* initialize l2 tunnel filter list & hash */
1349         ixgbe_l2_tn_filter_init(eth_dev);
1350
1351         TAILQ_INIT(&filter_ntuple_list);
1352         TAILQ_INIT(&filter_ethertype_list);
1353         TAILQ_INIT(&filter_syn_list);
1354         TAILQ_INIT(&filter_fdir_list);
1355         TAILQ_INIT(&filter_l2_tunnel_list);
1356         TAILQ_INIT(&ixgbe_flow_list);
1357
1358         /* initialize bandwidth configuration info */
1359         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1360
1361         return 0;
1362 }
1363
1364 static int
1365 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1366 {
1367         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1368         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1369         struct ixgbe_hw *hw;
1370
1371         PMD_INIT_FUNC_TRACE();
1372
1373         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1374                 return -EPERM;
1375
1376         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1377
1378         if (hw->adapter_stopped == 0)
1379                 ixgbe_dev_close(eth_dev);
1380
1381         eth_dev->dev_ops = NULL;
1382         eth_dev->rx_pkt_burst = NULL;
1383         eth_dev->tx_pkt_burst = NULL;
1384
1385         /* Unlock any pending hardware semaphore */
1386         ixgbe_swfw_lock_reset(hw);
1387
1388         /* disable uio intr before callback unregister */
1389         rte_intr_disable(intr_handle);
1390         rte_intr_callback_unregister(intr_handle,
1391                                      ixgbe_dev_interrupt_handler, eth_dev);
1392
1393         /* uninitialize PF if max_vfs not zero */
1394         ixgbe_pf_host_uninit(eth_dev);
1395
1396         rte_free(eth_dev->data->mac_addrs);
1397         eth_dev->data->mac_addrs = NULL;
1398
1399         rte_free(eth_dev->data->hash_mac_addrs);
1400         eth_dev->data->hash_mac_addrs = NULL;
1401
1402         /* remove all the fdir filters & hash */
1403         ixgbe_fdir_filter_uninit(eth_dev);
1404
1405         /* remove all the L2 tunnel filters & hash */
1406         ixgbe_l2_tn_filter_uninit(eth_dev);
1407
1408         /* Remove all ntuple filters of the device */
1409         ixgbe_ntuple_filter_uninit(eth_dev);
1410
1411         /* clear all the filters list */
1412         ixgbe_filterlist_flush();
1413
1414         return 0;
1415 }
1416
1417 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1418 {
1419         struct ixgbe_filter_info *filter_info =
1420                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1421         struct ixgbe_5tuple_filter *p_5tuple;
1422
1423         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1424                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1425                              p_5tuple,
1426                              entries);
1427                 rte_free(p_5tuple);
1428         }
1429         memset(filter_info->fivetuple_mask, 0,
1430                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1431
1432         return 0;
1433 }
1434
1435 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1436 {
1437         struct ixgbe_hw_fdir_info *fdir_info =
1438                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1439         struct ixgbe_fdir_filter *fdir_filter;
1440
1441                 if (fdir_info->hash_map)
1442                 rte_free(fdir_info->hash_map);
1443         if (fdir_info->hash_handle)
1444                 rte_hash_free(fdir_info->hash_handle);
1445
1446         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1447                 TAILQ_REMOVE(&fdir_info->fdir_list,
1448                              fdir_filter,
1449                              entries);
1450                 rte_free(fdir_filter);
1451         }
1452
1453         return 0;
1454 }
1455
1456 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1457 {
1458         struct ixgbe_l2_tn_info *l2_tn_info =
1459                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1460         struct ixgbe_l2_tn_filter *l2_tn_filter;
1461
1462         if (l2_tn_info->hash_map)
1463                 rte_free(l2_tn_info->hash_map);
1464         if (l2_tn_info->hash_handle)
1465                 rte_hash_free(l2_tn_info->hash_handle);
1466
1467         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1468                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1469                              l2_tn_filter,
1470                              entries);
1471                 rte_free(l2_tn_filter);
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1478 {
1479         struct ixgbe_hw_fdir_info *fdir_info =
1480                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1481         char fdir_hash_name[RTE_HASH_NAMESIZE];
1482         struct rte_hash_parameters fdir_hash_params = {
1483                 .name = fdir_hash_name,
1484                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1485                 .key_len = sizeof(union ixgbe_atr_input),
1486                 .hash_func = rte_hash_crc,
1487                 .hash_func_init_val = 0,
1488                 .socket_id = rte_socket_id(),
1489         };
1490
1491         TAILQ_INIT(&fdir_info->fdir_list);
1492         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1493                  "fdir_%s", eth_dev->data->name);
1494         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1495         if (!fdir_info->hash_handle) {
1496                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1497                 return -EINVAL;
1498         }
1499         fdir_info->hash_map = rte_zmalloc("ixgbe",
1500                                           sizeof(struct ixgbe_fdir_filter *) *
1501                                           IXGBE_MAX_FDIR_FILTER_NUM,
1502                                           0);
1503         if (!fdir_info->hash_map) {
1504                 PMD_INIT_LOG(ERR,
1505                              "Failed to allocate memory for fdir hash map!");
1506                 return -ENOMEM;
1507         }
1508         fdir_info->mask_added = FALSE;
1509
1510         return 0;
1511 }
1512
1513 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1514 {
1515         struct ixgbe_l2_tn_info *l2_tn_info =
1516                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1517         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1518         struct rte_hash_parameters l2_tn_hash_params = {
1519                 .name = l2_tn_hash_name,
1520                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1521                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1522                 .hash_func = rte_hash_crc,
1523                 .hash_func_init_val = 0,
1524                 .socket_id = rte_socket_id(),
1525         };
1526
1527         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1528         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1529                  "l2_tn_%s", eth_dev->data->name);
1530         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1531         if (!l2_tn_info->hash_handle) {
1532                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1533                 return -EINVAL;
1534         }
1535         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1536                                    sizeof(struct ixgbe_l2_tn_filter *) *
1537                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1538                                    0);
1539         if (!l2_tn_info->hash_map) {
1540                 PMD_INIT_LOG(ERR,
1541                         "Failed to allocate memory for L2 TN hash map!");
1542                 return -ENOMEM;
1543         }
1544         l2_tn_info->e_tag_en = FALSE;
1545         l2_tn_info->e_tag_fwd_en = FALSE;
1546         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1547
1548         return 0;
1549 }
1550 /*
1551  * Negotiate mailbox API version with the PF.
1552  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1553  * Then we try to negotiate starting with the most recent one.
1554  * If all negotiation attempts fail, then we will proceed with
1555  * the default one (ixgbe_mbox_api_10).
1556  */
1557 static void
1558 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1559 {
1560         int32_t i;
1561
1562         /* start with highest supported, proceed down */
1563         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1564                 ixgbe_mbox_api_12,
1565                 ixgbe_mbox_api_11,
1566                 ixgbe_mbox_api_10,
1567         };
1568
1569         for (i = 0;
1570                         i != RTE_DIM(sup_ver) &&
1571                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1572                         i++)
1573                 ;
1574 }
1575
1576 static void
1577 generate_random_mac_addr(struct ether_addr *mac_addr)
1578 {
1579         uint64_t random;
1580
1581         /* Set Organizationally Unique Identifier (OUI) prefix. */
1582         mac_addr->addr_bytes[0] = 0x00;
1583         mac_addr->addr_bytes[1] = 0x09;
1584         mac_addr->addr_bytes[2] = 0xC0;
1585         /* Force indication of locally assigned MAC address. */
1586         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1587         /* Generate the last 3 bytes of the MAC address with a random number. */
1588         random = rte_rand();
1589         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1590 }
1591
1592 /*
1593  * Virtual Function device init
1594  */
1595 static int
1596 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1597 {
1598         int diag;
1599         uint32_t tc, tcs;
1600         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1601         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1602         struct ixgbe_hw *hw =
1603                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1604         struct ixgbe_vfta *shadow_vfta =
1605                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1606         struct ixgbe_hwstrip *hwstrip =
1607                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1608         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1609
1610         PMD_INIT_FUNC_TRACE();
1611
1612         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1613         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1614         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1615
1616         /* for secondary processes, we don't initialise any further as primary
1617          * has already done this work. Only check we don't need a different
1618          * RX function
1619          */
1620         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1621                 struct ixgbe_tx_queue *txq;
1622                 /* TX queue function in primary, set by last queue initialized
1623                  * Tx queue may not initialized by primary process
1624                  */
1625                 if (eth_dev->data->tx_queues) {
1626                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1627                         ixgbe_set_tx_function(eth_dev, txq);
1628                 } else {
1629                         /* Use default TX function if we get here */
1630                         PMD_INIT_LOG(NOTICE,
1631                                      "No TX queues configured yet. Using default TX function.");
1632                 }
1633
1634                 ixgbe_set_rx_function(eth_dev);
1635
1636                 return 0;
1637         }
1638
1639         rte_eth_copy_pci_info(eth_dev, pci_dev);
1640         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1641
1642         hw->device_id = pci_dev->id.device_id;
1643         hw->vendor_id = pci_dev->id.vendor_id;
1644         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1645
1646         /* initialize the vfta */
1647         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1648
1649         /* initialize the hw strip bitmap*/
1650         memset(hwstrip, 0, sizeof(*hwstrip));
1651
1652         /* Initialize the shared code (base driver) */
1653         diag = ixgbe_init_shared_code(hw);
1654         if (diag != IXGBE_SUCCESS) {
1655                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1656                 return -EIO;
1657         }
1658
1659         /* init_mailbox_params */
1660         hw->mbx.ops.init_params(hw);
1661
1662         /* Reset the hw statistics */
1663         ixgbevf_dev_stats_reset(eth_dev);
1664
1665         /* Disable the interrupts for VF */
1666         ixgbevf_intr_disable(hw);
1667
1668         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1669         diag = hw->mac.ops.reset_hw(hw);
1670
1671         /*
1672          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1673          * the underlying PF driver has not assigned a MAC address to the VF.
1674          * In this case, assign a random MAC address.
1675          */
1676         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1677                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1678                 return diag;
1679         }
1680
1681         /* negotiate mailbox API version to use with the PF. */
1682         ixgbevf_negotiate_api(hw);
1683
1684         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1685         ixgbevf_get_queues(hw, &tcs, &tc);
1686
1687         /* Allocate memory for storing MAC addresses */
1688         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1689                                                hw->mac.num_rar_entries, 0);
1690         if (eth_dev->data->mac_addrs == NULL) {
1691                 PMD_INIT_LOG(ERR,
1692                              "Failed to allocate %u bytes needed to store "
1693                              "MAC addresses",
1694                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1695                 return -ENOMEM;
1696         }
1697
1698         /* Generate a random MAC address, if none was assigned by PF. */
1699         if (is_zero_ether_addr(perm_addr)) {
1700                 generate_random_mac_addr(perm_addr);
1701                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1702                 if (diag) {
1703                         rte_free(eth_dev->data->mac_addrs);
1704                         eth_dev->data->mac_addrs = NULL;
1705                         return diag;
1706                 }
1707                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1708                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1709                              "%02x:%02x:%02x:%02x:%02x:%02x",
1710                              perm_addr->addr_bytes[0],
1711                              perm_addr->addr_bytes[1],
1712                              perm_addr->addr_bytes[2],
1713                              perm_addr->addr_bytes[3],
1714                              perm_addr->addr_bytes[4],
1715                              perm_addr->addr_bytes[5]);
1716         }
1717
1718         /* Copy the permanent MAC address */
1719         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1720
1721         /* reset the hardware with the new settings */
1722         diag = hw->mac.ops.start_hw(hw);
1723         switch (diag) {
1724         case  0:
1725                 break;
1726
1727         default:
1728                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1729                 return -EIO;
1730         }
1731
1732         rte_intr_callback_register(intr_handle,
1733                                    ixgbevf_dev_interrupt_handler, eth_dev);
1734         rte_intr_enable(intr_handle);
1735         ixgbevf_intr_enable(hw);
1736
1737         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1738                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1739                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1740
1741         return 0;
1742 }
1743
1744 /* Virtual Function device uninit */
1745
1746 static int
1747 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1748 {
1749         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1750         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1751         struct ixgbe_hw *hw;
1752
1753         PMD_INIT_FUNC_TRACE();
1754
1755         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1756                 return -EPERM;
1757
1758         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1759
1760         if (hw->adapter_stopped == 0)
1761                 ixgbevf_dev_close(eth_dev);
1762
1763         eth_dev->dev_ops = NULL;
1764         eth_dev->rx_pkt_burst = NULL;
1765         eth_dev->tx_pkt_burst = NULL;
1766
1767         /* Disable the interrupts for VF */
1768         ixgbevf_intr_disable(hw);
1769
1770         rte_free(eth_dev->data->mac_addrs);
1771         eth_dev->data->mac_addrs = NULL;
1772
1773         rte_intr_disable(intr_handle);
1774         rte_intr_callback_unregister(intr_handle,
1775                                      ixgbevf_dev_interrupt_handler, eth_dev);
1776
1777         return 0;
1778 }
1779
1780 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1781         struct rte_pci_device *pci_dev)
1782 {
1783         return rte_eth_dev_pci_generic_probe(pci_dev,
1784                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1785 }
1786
1787 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1788 {
1789         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1790 }
1791
1792 static struct rte_pci_driver rte_ixgbe_pmd = {
1793         .id_table = pci_id_ixgbe_map,
1794         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1795         .probe = eth_ixgbe_pci_probe,
1796         .remove = eth_ixgbe_pci_remove,
1797 };
1798
1799 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1800         struct rte_pci_device *pci_dev)
1801 {
1802         return rte_eth_dev_pci_generic_probe(pci_dev,
1803                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1804 }
1805
1806 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1807 {
1808         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1809 }
1810
1811 /*
1812  * virtual function driver struct
1813  */
1814 static struct rte_pci_driver rte_ixgbevf_pmd = {
1815         .id_table = pci_id_ixgbevf_map,
1816         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1817         .probe = eth_ixgbevf_pci_probe,
1818         .remove = eth_ixgbevf_pci_remove,
1819 };
1820
1821 static int
1822 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1823 {
1824         struct ixgbe_hw *hw =
1825                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1826         struct ixgbe_vfta *shadow_vfta =
1827                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1828         uint32_t vfta;
1829         uint32_t vid_idx;
1830         uint32_t vid_bit;
1831
1832         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1833         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1834         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1835         if (on)
1836                 vfta |= vid_bit;
1837         else
1838                 vfta &= ~vid_bit;
1839         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1840
1841         /* update local VFTA copy */
1842         shadow_vfta->vfta[vid_idx] = vfta;
1843
1844         return 0;
1845 }
1846
1847 static void
1848 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1849 {
1850         if (on)
1851                 ixgbe_vlan_hw_strip_enable(dev, queue);
1852         else
1853                 ixgbe_vlan_hw_strip_disable(dev, queue);
1854 }
1855
1856 static int
1857 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1858                     enum rte_vlan_type vlan_type,
1859                     uint16_t tpid)
1860 {
1861         struct ixgbe_hw *hw =
1862                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1863         int ret = 0;
1864         uint32_t reg;
1865         uint32_t qinq;
1866
1867         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1868         qinq &= IXGBE_DMATXCTL_GDV;
1869
1870         switch (vlan_type) {
1871         case ETH_VLAN_TYPE_INNER:
1872                 if (qinq) {
1873                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1874                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1875                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1876                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1877                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1878                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1879                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1880                 } else {
1881                         ret = -ENOTSUP;
1882                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1883                                     " by single VLAN");
1884                 }
1885                 break;
1886         case ETH_VLAN_TYPE_OUTER:
1887                 if (qinq) {
1888                         /* Only the high 16-bits is valid */
1889                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1890                                         IXGBE_EXVET_VET_EXT_SHIFT);
1891                 } else {
1892                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1893                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1894                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1895                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1896                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1897                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1898                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1899                 }
1900
1901                 break;
1902         default:
1903                 ret = -EINVAL;
1904                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1905                 break;
1906         }
1907
1908         return ret;
1909 }
1910
1911 void
1912 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1913 {
1914         struct ixgbe_hw *hw =
1915                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1916         uint32_t vlnctrl;
1917
1918         PMD_INIT_FUNC_TRACE();
1919
1920         /* Filter Table Disable */
1921         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1922         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1923
1924         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1925 }
1926
1927 void
1928 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1929 {
1930         struct ixgbe_hw *hw =
1931                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1932         struct ixgbe_vfta *shadow_vfta =
1933                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1934         uint32_t vlnctrl;
1935         uint16_t i;
1936
1937         PMD_INIT_FUNC_TRACE();
1938
1939         /* Filter Table Enable */
1940         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1941         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1942         vlnctrl |= IXGBE_VLNCTRL_VFE;
1943
1944         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1945
1946         /* write whatever is in local vfta copy */
1947         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1948                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1949 }
1950
1951 static void
1952 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1953 {
1954         struct ixgbe_hwstrip *hwstrip =
1955                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1956         struct ixgbe_rx_queue *rxq;
1957
1958         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1959                 return;
1960
1961         if (on)
1962                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1963         else
1964                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1965
1966         if (queue >= dev->data->nb_rx_queues)
1967                 return;
1968
1969         rxq = dev->data->rx_queues[queue];
1970
1971         if (on)
1972                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1973         else
1974                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1975 }
1976
1977 static void
1978 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1979 {
1980         struct ixgbe_hw *hw =
1981                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1982         uint32_t ctrl;
1983
1984         PMD_INIT_FUNC_TRACE();
1985
1986         if (hw->mac.type == ixgbe_mac_82598EB) {
1987                 /* No queue level support */
1988                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1989                 return;
1990         }
1991
1992         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1993         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1994         ctrl &= ~IXGBE_RXDCTL_VME;
1995         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1996
1997         /* record those setting for HW strip per queue */
1998         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1999 }
2000
2001 static void
2002 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2003 {
2004         struct ixgbe_hw *hw =
2005                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006         uint32_t ctrl;
2007
2008         PMD_INIT_FUNC_TRACE();
2009
2010         if (hw->mac.type == ixgbe_mac_82598EB) {
2011                 /* No queue level supported */
2012                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2013                 return;
2014         }
2015
2016         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2017         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2018         ctrl |= IXGBE_RXDCTL_VME;
2019         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2020
2021         /* record those setting for HW strip per queue */
2022         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2023 }
2024
2025 void
2026 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2027 {
2028         struct ixgbe_hw *hw =
2029                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030         uint32_t ctrl;
2031         uint16_t i;
2032         struct ixgbe_rx_queue *rxq;
2033
2034         PMD_INIT_FUNC_TRACE();
2035
2036         if (hw->mac.type == ixgbe_mac_82598EB) {
2037                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2038                 ctrl &= ~IXGBE_VLNCTRL_VME;
2039                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2040         } else {
2041                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2042                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2043                         rxq = dev->data->rx_queues[i];
2044                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2045                         ctrl &= ~IXGBE_RXDCTL_VME;
2046                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2047
2048                         /* record those setting for HW strip per queue */
2049                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2050                 }
2051         }
2052 }
2053
2054 void
2055 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2056 {
2057         struct ixgbe_hw *hw =
2058                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059         uint32_t ctrl;
2060         uint16_t i;
2061         struct ixgbe_rx_queue *rxq;
2062
2063         PMD_INIT_FUNC_TRACE();
2064
2065         if (hw->mac.type == ixgbe_mac_82598EB) {
2066                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2067                 ctrl |= IXGBE_VLNCTRL_VME;
2068                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2069         } else {
2070                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2071                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2072                         rxq = dev->data->rx_queues[i];
2073                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2074                         ctrl |= IXGBE_RXDCTL_VME;
2075                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2076
2077                         /* record those setting for HW strip per queue */
2078                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2079                 }
2080         }
2081 }
2082
2083 static void
2084 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2085 {
2086         struct ixgbe_hw *hw =
2087                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088         uint32_t ctrl;
2089
2090         PMD_INIT_FUNC_TRACE();
2091
2092         /* DMATXCTRL: Geric Double VLAN Disable */
2093         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2094         ctrl &= ~IXGBE_DMATXCTL_GDV;
2095         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2096
2097         /* CTRL_EXT: Global Double VLAN Disable */
2098         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2099         ctrl &= ~IXGBE_EXTENDED_VLAN;
2100         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2101
2102 }
2103
2104 static void
2105 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2106 {
2107         struct ixgbe_hw *hw =
2108                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109         uint32_t ctrl;
2110
2111         PMD_INIT_FUNC_TRACE();
2112
2113         /* DMATXCTRL: Geric Double VLAN Enable */
2114         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2115         ctrl |= IXGBE_DMATXCTL_GDV;
2116         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2117
2118         /* CTRL_EXT: Global Double VLAN Enable */
2119         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2120         ctrl |= IXGBE_EXTENDED_VLAN;
2121         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2122
2123         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2124         if (hw->mac.type == ixgbe_mac_X550 ||
2125             hw->mac.type == ixgbe_mac_X550EM_x ||
2126             hw->mac.type == ixgbe_mac_X550EM_a) {
2127                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2128                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2129                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2130         }
2131
2132         /*
2133          * VET EXT field in the EXVET register = 0x8100 by default
2134          * So no need to change. Same to VT field of DMATXCTL register
2135          */
2136 }
2137
2138 static void
2139 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2140 {
2141         if (mask & ETH_VLAN_STRIP_MASK) {
2142                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2143                         ixgbe_vlan_hw_strip_enable_all(dev);
2144                 else
2145                         ixgbe_vlan_hw_strip_disable_all(dev);
2146         }
2147
2148         if (mask & ETH_VLAN_FILTER_MASK) {
2149                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2150                         ixgbe_vlan_hw_filter_enable(dev);
2151                 else
2152                         ixgbe_vlan_hw_filter_disable(dev);
2153         }
2154
2155         if (mask & ETH_VLAN_EXTEND_MASK) {
2156                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2157                         ixgbe_vlan_hw_extend_enable(dev);
2158                 else
2159                         ixgbe_vlan_hw_extend_disable(dev);
2160         }
2161 }
2162
2163 static void
2164 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2165 {
2166         struct ixgbe_hw *hw =
2167                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2169         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2170
2171         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2172         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2173 }
2174
2175 static int
2176 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2177 {
2178         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2179
2180         switch (nb_rx_q) {
2181         case 1:
2182         case 2:
2183                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2184                 break;
2185         case 4:
2186                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2187                 break;
2188         default:
2189                 return -EINVAL;
2190         }
2191
2192         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2193         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2194
2195         return 0;
2196 }
2197
2198 static int
2199 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2200 {
2201         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2202         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2204         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2205
2206         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2207                 /* check multi-queue mode */
2208                 switch (dev_conf->rxmode.mq_mode) {
2209                 case ETH_MQ_RX_VMDQ_DCB:
2210                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2211                         break;
2212                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2213                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2214                         PMD_INIT_LOG(ERR, "SRIOV active,"
2215                                         " unsupported mq_mode rx %d.",
2216                                         dev_conf->rxmode.mq_mode);
2217                         return -EINVAL;
2218                 case ETH_MQ_RX_RSS:
2219                 case ETH_MQ_RX_VMDQ_RSS:
2220                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2221                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2222                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2223                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2224                                                 " invalid queue number"
2225                                                 " for VMDQ RSS, allowed"
2226                                                 " value are 1, 2 or 4.");
2227                                         return -EINVAL;
2228                                 }
2229                         break;
2230                 case ETH_MQ_RX_VMDQ_ONLY:
2231                 case ETH_MQ_RX_NONE:
2232                         /* if nothing mq mode configure, use default scheme */
2233                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2234                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2235                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2236                         break;
2237                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2238                         /* SRIOV only works in VMDq enable mode */
2239                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2240                                         " wrong mq_mode rx %d.",
2241                                         dev_conf->rxmode.mq_mode);
2242                         return -EINVAL;
2243                 }
2244
2245                 switch (dev_conf->txmode.mq_mode) {
2246                 case ETH_MQ_TX_VMDQ_DCB:
2247                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2248                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2249                         break;
2250                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2251                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2252                         break;
2253                 }
2254
2255                 /* check valid queue number */
2256                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2257                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2258                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2259                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2260                                         " must be less than or equal to %d.",
2261                                         nb_rx_q, nb_tx_q,
2262                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2263                         return -EINVAL;
2264                 }
2265         } else {
2266                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2267                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2268                                           " not supported.");
2269                         return -EINVAL;
2270                 }
2271                 /* check configuration for vmdb+dcb mode */
2272                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2273                         const struct rte_eth_vmdq_dcb_conf *conf;
2274
2275                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2276                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2277                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2278                                 return -EINVAL;
2279                         }
2280                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2281                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2282                                conf->nb_queue_pools == ETH_32_POOLS)) {
2283                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2284                                                 " nb_queue_pools must be %d or %d.",
2285                                                 ETH_16_POOLS, ETH_32_POOLS);
2286                                 return -EINVAL;
2287                         }
2288                 }
2289                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2290                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2291
2292                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2293                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2294                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2295                                 return -EINVAL;
2296                         }
2297                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2298                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2299                                conf->nb_queue_pools == ETH_32_POOLS)) {
2300                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2301                                                 " nb_queue_pools != %d and"
2302                                                 " nb_queue_pools != %d.",
2303                                                 ETH_16_POOLS, ETH_32_POOLS);
2304                                 return -EINVAL;
2305                         }
2306                 }
2307
2308                 /* For DCB mode check our configuration before we go further */
2309                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2310                         const struct rte_eth_dcb_rx_conf *conf;
2311
2312                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2313                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2314                                                  IXGBE_DCB_NB_QUEUES);
2315                                 return -EINVAL;
2316                         }
2317                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2318                         if (!(conf->nb_tcs == ETH_4_TCS ||
2319                                conf->nb_tcs == ETH_8_TCS)) {
2320                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2321                                                 " and nb_tcs != %d.",
2322                                                 ETH_4_TCS, ETH_8_TCS);
2323                                 return -EINVAL;
2324                         }
2325                 }
2326
2327                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2328                         const struct rte_eth_dcb_tx_conf *conf;
2329
2330                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2331                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2332                                                  IXGBE_DCB_NB_QUEUES);
2333                                 return -EINVAL;
2334                         }
2335                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2336                         if (!(conf->nb_tcs == ETH_4_TCS ||
2337                                conf->nb_tcs == ETH_8_TCS)) {
2338                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2339                                                 " and nb_tcs != %d.",
2340                                                 ETH_4_TCS, ETH_8_TCS);
2341                                 return -EINVAL;
2342                         }
2343                 }
2344
2345                 /*
2346                  * When DCB/VT is off, maximum number of queues changes,
2347                  * except for 82598EB, which remains constant.
2348                  */
2349                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2350                                 hw->mac.type != ixgbe_mac_82598EB) {
2351                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2352                                 PMD_INIT_LOG(ERR,
2353                                              "Neither VT nor DCB are enabled, "
2354                                              "nb_tx_q > %d.",
2355                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2356                                 return -EINVAL;
2357                         }
2358                 }
2359         }
2360         return 0;
2361 }
2362
2363 static int
2364 ixgbe_dev_configure(struct rte_eth_dev *dev)
2365 {
2366         struct ixgbe_interrupt *intr =
2367                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2368         struct ixgbe_adapter *adapter =
2369                 (struct ixgbe_adapter *)dev->data->dev_private;
2370         int ret;
2371
2372         PMD_INIT_FUNC_TRACE();
2373         /* multipe queue mode checking */
2374         ret  = ixgbe_check_mq_mode(dev);
2375         if (ret != 0) {
2376                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2377                             ret);
2378                 return ret;
2379         }
2380
2381         /* set flag to update link status after init */
2382         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2383
2384         /*
2385          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2386          * allocation or vector Rx preconditions we will reset it.
2387          */
2388         adapter->rx_bulk_alloc_allowed = true;
2389         adapter->rx_vec_allowed = true;
2390
2391         return 0;
2392 }
2393
2394 static void
2395 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2396 {
2397         struct ixgbe_hw *hw =
2398                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399         struct ixgbe_interrupt *intr =
2400                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2401         uint32_t gpie;
2402
2403         /* only set up it on X550EM_X */
2404         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2405                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2406                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2407                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2408                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2409                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2410         }
2411 }
2412
2413 int
2414 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2415                         uint16_t tx_rate, uint64_t q_msk)
2416 {
2417         struct ixgbe_hw *hw;
2418         struct ixgbe_vf_info *vfinfo;
2419         struct rte_eth_link link;
2420         uint8_t  nb_q_per_pool;
2421         uint32_t queue_stride;
2422         uint32_t queue_idx, idx = 0, vf_idx;
2423         uint32_t queue_end;
2424         uint16_t total_rate = 0;
2425         struct rte_pci_device *pci_dev;
2426
2427         pci_dev = IXGBE_DEV_TO_PCI(dev);
2428         rte_eth_link_get_nowait(dev->data->port_id, &link);
2429
2430         if (vf >= pci_dev->max_vfs)
2431                 return -EINVAL;
2432
2433         if (tx_rate > link.link_speed)
2434                 return -EINVAL;
2435
2436         if (q_msk == 0)
2437                 return 0;
2438
2439         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2440         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2441         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2442         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2443         queue_idx = vf * queue_stride;
2444         queue_end = queue_idx + nb_q_per_pool - 1;
2445         if (queue_end >= hw->mac.max_tx_queues)
2446                 return -EINVAL;
2447
2448         if (vfinfo) {
2449                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2450                         if (vf_idx == vf)
2451                                 continue;
2452                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2453                                 idx++)
2454                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2455                 }
2456         } else {
2457                 return -EINVAL;
2458         }
2459
2460         /* Store tx_rate for this vf. */
2461         for (idx = 0; idx < nb_q_per_pool; idx++) {
2462                 if (((uint64_t)0x1 << idx) & q_msk) {
2463                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2464                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2465                         total_rate += tx_rate;
2466                 }
2467         }
2468
2469         if (total_rate > dev->data->dev_link.link_speed) {
2470                 /* Reset stored TX rate of the VF if it causes exceed
2471                  * link speed.
2472                  */
2473                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2474                 return -EINVAL;
2475         }
2476
2477         /* Set RTTBCNRC of each queue/pool for vf X  */
2478         for (; queue_idx <= queue_end; queue_idx++) {
2479                 if (0x1 & q_msk)
2480                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2481                 q_msk = q_msk >> 1;
2482         }
2483
2484         return 0;
2485 }
2486
2487 /*
2488  * Configure device link speed and setup link.
2489  * It returns 0 on success.
2490  */
2491 static int
2492 ixgbe_dev_start(struct rte_eth_dev *dev)
2493 {
2494         struct ixgbe_hw *hw =
2495                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496         struct ixgbe_vf_info *vfinfo =
2497                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2498         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2499         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2500         uint32_t intr_vector = 0;
2501         int err, link_up = 0, negotiate = 0;
2502         uint32_t speed = 0;
2503         int mask = 0;
2504         int status;
2505         uint16_t vf, idx;
2506         uint32_t *link_speeds;
2507
2508         PMD_INIT_FUNC_TRACE();
2509
2510         /* IXGBE devices don't support:
2511         *    - half duplex (checked afterwards for valid speeds)
2512         *    - fixed speed: TODO implement
2513         */
2514         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2515                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2516                              dev->data->port_id);
2517                 return -EINVAL;
2518         }
2519
2520         /* disable uio/vfio intr/eventfd mapping */
2521         rte_intr_disable(intr_handle);
2522
2523         /* stop adapter */
2524         hw->adapter_stopped = 0;
2525         ixgbe_stop_adapter(hw);
2526
2527         /* reinitialize adapter
2528          * this calls reset and start
2529          */
2530         status = ixgbe_pf_reset_hw(hw);
2531         if (status != 0)
2532                 return -1;
2533         hw->mac.ops.start_hw(hw);
2534         hw->mac.get_link_status = true;
2535
2536         /* configure PF module if SRIOV enabled */
2537         ixgbe_pf_host_configure(dev);
2538
2539         ixgbe_dev_phy_intr_setup(dev);
2540
2541         /* check and configure queue intr-vector mapping */
2542         if ((rte_intr_cap_multiple(intr_handle) ||
2543              !RTE_ETH_DEV_SRIOV(dev).active) &&
2544             dev->data->dev_conf.intr_conf.rxq != 0) {
2545                 intr_vector = dev->data->nb_rx_queues;
2546                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2547                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2548                                         IXGBE_MAX_INTR_QUEUE_NUM);
2549                         return -ENOTSUP;
2550                 }
2551                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2552                         return -1;
2553         }
2554
2555         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2556                 intr_handle->intr_vec =
2557                         rte_zmalloc("intr_vec",
2558                                     dev->data->nb_rx_queues * sizeof(int), 0);
2559                 if (intr_handle->intr_vec == NULL) {
2560                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2561                                      " intr_vec", dev->data->nb_rx_queues);
2562                         return -ENOMEM;
2563                 }
2564         }
2565
2566         /* confiugre msix for sleep until rx interrupt */
2567         ixgbe_configure_msix(dev);
2568
2569         /* initialize transmission unit */
2570         ixgbe_dev_tx_init(dev);
2571
2572         /* This can fail when allocating mbufs for descriptor rings */
2573         err = ixgbe_dev_rx_init(dev);
2574         if (err) {
2575                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2576                 goto error;
2577         }
2578
2579     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2580                 ETH_VLAN_EXTEND_MASK;
2581         ixgbe_vlan_offload_set(dev, mask);
2582
2583         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2584                 /* Enable vlan filtering for VMDq */
2585                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2586         }
2587
2588         /* Configure DCB hw */
2589         ixgbe_configure_dcb(dev);
2590
2591         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2592                 err = ixgbe_fdir_configure(dev);
2593                 if (err)
2594                         goto error;
2595         }
2596
2597         /* Restore vf rate limit */
2598         if (vfinfo != NULL) {
2599                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2600                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2601                                 if (vfinfo[vf].tx_rate[idx] != 0)
2602                                         ixgbe_set_vf_rate_limit(
2603                                                 dev, vf,
2604                                                 vfinfo[vf].tx_rate[idx],
2605                                                 1 << idx);
2606         }
2607
2608         ixgbe_restore_statistics_mapping(dev);
2609
2610         err = ixgbe_dev_rxtx_start(dev);
2611         if (err < 0) {
2612                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2613                 goto error;
2614         }
2615
2616         /* Skip link setup if loopback mode is enabled for 82599. */
2617         if (hw->mac.type == ixgbe_mac_82599EB &&
2618                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2619                 goto skip_link_setup;
2620
2621         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2622                 err = hw->mac.ops.setup_sfp(hw);
2623                 if (err)
2624                         goto error;
2625         }
2626
2627         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2628                 /* Turn on the copper */
2629                 ixgbe_set_phy_power(hw, true);
2630         } else {
2631                 /* Turn on the laser */
2632                 ixgbe_enable_tx_laser(hw);
2633         }
2634
2635         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2636         if (err)
2637                 goto error;
2638         dev->data->dev_link.link_status = link_up;
2639
2640         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2641         if (err)
2642                 goto error;
2643
2644         link_speeds = &dev->data->dev_conf.link_speeds;
2645         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2646                         ETH_LINK_SPEED_10G)) {
2647                 PMD_INIT_LOG(ERR, "Invalid link setting");
2648                 goto error;
2649         }
2650
2651         speed = 0x0;
2652         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2653                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2654                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2655                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2656         } else {
2657                 if (*link_speeds & ETH_LINK_SPEED_10G)
2658                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2659                 if (*link_speeds & ETH_LINK_SPEED_1G)
2660                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2661                 if (*link_speeds & ETH_LINK_SPEED_100M)
2662                         speed |= IXGBE_LINK_SPEED_100_FULL;
2663         }
2664
2665         err = ixgbe_setup_link(hw, speed, link_up);
2666         if (err)
2667                 goto error;
2668
2669 skip_link_setup:
2670
2671         if (rte_intr_allow_others(intr_handle)) {
2672                 /* check if lsc interrupt is enabled */
2673                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2674                         ixgbe_dev_lsc_interrupt_setup(dev);
2675                 ixgbe_dev_macsec_interrupt_setup(dev);
2676         } else {
2677                 rte_intr_callback_unregister(intr_handle,
2678                                              ixgbe_dev_interrupt_handler, dev);
2679                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2680                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2681                                      " no intr multiplex");
2682         }
2683
2684         /* check if rxq interrupt is enabled */
2685         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2686             rte_intr_dp_is_en(intr_handle))
2687                 ixgbe_dev_rxq_interrupt_setup(dev);
2688
2689         /* enable uio/vfio intr/eventfd mapping */
2690         rte_intr_enable(intr_handle);
2691
2692         /* resume enabled intr since hw reset */
2693         ixgbe_enable_intr(dev);
2694         ixgbe_l2_tunnel_conf(dev);
2695         ixgbe_filter_restore(dev);
2696
2697         return 0;
2698
2699 error:
2700         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2701         ixgbe_dev_clear_queues(dev);
2702         return -EIO;
2703 }
2704
2705 /*
2706  * Stop device: disable rx and tx functions to allow for reconfiguring.
2707  */
2708 static void
2709 ixgbe_dev_stop(struct rte_eth_dev *dev)
2710 {
2711         struct rte_eth_link link;
2712         struct ixgbe_hw *hw =
2713                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2714         struct ixgbe_vf_info *vfinfo =
2715                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2716         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2717         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2718         int vf;
2719
2720         PMD_INIT_FUNC_TRACE();
2721
2722         /* disable interrupts */
2723         ixgbe_disable_intr(hw);
2724
2725         /* reset the NIC */
2726         ixgbe_pf_reset_hw(hw);
2727         hw->adapter_stopped = 0;
2728
2729         /* stop adapter */
2730         ixgbe_stop_adapter(hw);
2731
2732         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2733                 vfinfo[vf].clear_to_send = false;
2734
2735         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2736                 /* Turn off the copper */
2737                 ixgbe_set_phy_power(hw, false);
2738         } else {
2739                 /* Turn off the laser */
2740                 ixgbe_disable_tx_laser(hw);
2741         }
2742
2743         ixgbe_dev_clear_queues(dev);
2744
2745         /* Clear stored conf */
2746         dev->data->scattered_rx = 0;
2747         dev->data->lro = 0;
2748
2749         /* Clear recorded link status */
2750         memset(&link, 0, sizeof(link));
2751         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2752
2753         if (!rte_intr_allow_others(intr_handle))
2754                 /* resume to the default handler */
2755                 rte_intr_callback_register(intr_handle,
2756                                            ixgbe_dev_interrupt_handler,
2757                                            (void *)dev);
2758
2759         /* Clean datapath event and queue/vec mapping */
2760         rte_intr_efd_disable(intr_handle);
2761         if (intr_handle->intr_vec != NULL) {
2762                 rte_free(intr_handle->intr_vec);
2763                 intr_handle->intr_vec = NULL;
2764         }
2765 }
2766
2767 /*
2768  * Set device link up: enable tx.
2769  */
2770 static int
2771 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2772 {
2773         struct ixgbe_hw *hw =
2774                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2775         if (hw->mac.type == ixgbe_mac_82599EB) {
2776 #ifdef RTE_NIC_BYPASS
2777                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2778                         /* Not suported in bypass mode */
2779                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2780                                      "by device id 0x%x", hw->device_id);
2781                         return -ENOTSUP;
2782                 }
2783 #endif
2784         }
2785
2786         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2787                 /* Turn on the copper */
2788                 ixgbe_set_phy_power(hw, true);
2789         } else {
2790                 /* Turn on the laser */
2791                 ixgbe_enable_tx_laser(hw);
2792         }
2793
2794         return 0;
2795 }
2796
2797 /*
2798  * Set device link down: disable tx.
2799  */
2800 static int
2801 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2802 {
2803         struct ixgbe_hw *hw =
2804                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2805         if (hw->mac.type == ixgbe_mac_82599EB) {
2806 #ifdef RTE_NIC_BYPASS
2807                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2808                         /* Not suported in bypass mode */
2809                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2810                                      "by device id 0x%x", hw->device_id);
2811                         return -ENOTSUP;
2812                 }
2813 #endif
2814         }
2815
2816         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2817                 /* Turn off the copper */
2818                 ixgbe_set_phy_power(hw, false);
2819         } else {
2820                 /* Turn off the laser */
2821                 ixgbe_disable_tx_laser(hw);
2822         }
2823
2824         return 0;
2825 }
2826
2827 /*
2828  * Reest and stop device.
2829  */
2830 static void
2831 ixgbe_dev_close(struct rte_eth_dev *dev)
2832 {
2833         struct ixgbe_hw *hw =
2834                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835
2836         PMD_INIT_FUNC_TRACE();
2837
2838         ixgbe_pf_reset_hw(hw);
2839
2840         ixgbe_dev_stop(dev);
2841         hw->adapter_stopped = 1;
2842
2843         ixgbe_dev_free_queues(dev);
2844
2845         ixgbe_disable_pcie_master(hw);
2846
2847         /* reprogram the RAR[0] in case user changed it. */
2848         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2849 }
2850
2851 static void
2852 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2853                            struct ixgbe_hw_stats *hw_stats,
2854                            struct ixgbe_macsec_stats *macsec_stats,
2855                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2856                            uint64_t *total_qprc, uint64_t *total_qprdc)
2857 {
2858         uint32_t bprc, lxon, lxoff, total;
2859         uint32_t delta_gprc = 0;
2860         unsigned i;
2861         /* Workaround for RX byte count not including CRC bytes when CRC
2862          * strip is enabled. CRC bytes are removed from counters when crc_strip
2863          * is disabled.
2864          */
2865         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2866                         IXGBE_HLREG0_RXCRCSTRP);
2867
2868         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2869         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2870         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2871         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2872
2873         for (i = 0; i < 8; i++) {
2874                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2875
2876                 /* global total per queue */
2877                 hw_stats->mpc[i] += mp;
2878                 /* Running comprehensive total for stats display */
2879                 *total_missed_rx += hw_stats->mpc[i];
2880                 if (hw->mac.type == ixgbe_mac_82598EB) {
2881                         hw_stats->rnbc[i] +=
2882                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2883                         hw_stats->pxonrxc[i] +=
2884                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2885                         hw_stats->pxoffrxc[i] +=
2886                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2887                 } else {
2888                         hw_stats->pxonrxc[i] +=
2889                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2890                         hw_stats->pxoffrxc[i] +=
2891                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2892                         hw_stats->pxon2offc[i] +=
2893                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2894                 }
2895                 hw_stats->pxontxc[i] +=
2896                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2897                 hw_stats->pxofftxc[i] +=
2898                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2899         }
2900         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2901                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2902                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2903                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2904
2905                 delta_gprc += delta_qprc;
2906
2907                 hw_stats->qprc[i] += delta_qprc;
2908                 hw_stats->qptc[i] += delta_qptc;
2909
2910                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2911                 hw_stats->qbrc[i] +=
2912                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2913                 if (crc_strip == 0)
2914                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2915
2916                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2917                 hw_stats->qbtc[i] +=
2918                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2919
2920                 hw_stats->qprdc[i] += delta_qprdc;
2921                 *total_qprdc += hw_stats->qprdc[i];
2922
2923                 *total_qprc += hw_stats->qprc[i];
2924                 *total_qbrc += hw_stats->qbrc[i];
2925         }
2926         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2927         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2928         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2929
2930         /*
2931          * An errata states that gprc actually counts good + missed packets:
2932          * Workaround to set gprc to summated queue packet receives
2933          */
2934         hw_stats->gprc = *total_qprc;
2935
2936         if (hw->mac.type != ixgbe_mac_82598EB) {
2937                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2938                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2939                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2940                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2941                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2942                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2943                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2944                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2945         } else {
2946                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2947                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2948                 /* 82598 only has a counter in the high register */
2949                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2950                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2951                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2952         }
2953         uint64_t old_tpr = hw_stats->tpr;
2954
2955         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2956         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2957
2958         if (crc_strip == 0)
2959                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2960
2961         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2962         hw_stats->gptc += delta_gptc;
2963         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2964         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2965
2966         /*
2967          * Workaround: mprc hardware is incorrectly counting
2968          * broadcasts, so for now we subtract those.
2969          */
2970         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2971         hw_stats->bprc += bprc;
2972         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2973         if (hw->mac.type == ixgbe_mac_82598EB)
2974                 hw_stats->mprc -= bprc;
2975
2976         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2977         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2978         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2979         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2980         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2981         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2982
2983         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2984         hw_stats->lxontxc += lxon;
2985         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2986         hw_stats->lxofftxc += lxoff;
2987         total = lxon + lxoff;
2988
2989         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2990         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2991         hw_stats->gptc -= total;
2992         hw_stats->mptc -= total;
2993         hw_stats->ptc64 -= total;
2994         hw_stats->gotc -= total * ETHER_MIN_LEN;
2995
2996         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2997         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2998         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2999         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3000         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3001         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3002         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3003         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3004         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3005         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3006         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3007         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3008         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3009         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3010         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3011         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3012         /* Only read FCOE on 82599 */
3013         if (hw->mac.type != ixgbe_mac_82598EB) {
3014                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3015                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3016                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3017                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3018                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3019         }
3020
3021         /* Flow Director Stats registers */
3022         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3023         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3024
3025         /* MACsec Stats registers */
3026         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3027         macsec_stats->out_pkts_encrypted +=
3028                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3029         macsec_stats->out_pkts_protected +=
3030                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3031         macsec_stats->out_octets_encrypted +=
3032                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3033         macsec_stats->out_octets_protected +=
3034                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3035         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3036         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3037         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3038         macsec_stats->in_pkts_unknownsci +=
3039                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3040         macsec_stats->in_octets_decrypted +=
3041                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3042         macsec_stats->in_octets_validated +=
3043                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3044         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3045         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3046         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3047         for (i = 0; i < 2; i++) {
3048                 macsec_stats->in_pkts_ok +=
3049                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3050                 macsec_stats->in_pkts_invalid +=
3051                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3052                 macsec_stats->in_pkts_notvalid +=
3053                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3054         }
3055         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3056         macsec_stats->in_pkts_notusingsa +=
3057                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3058 }
3059
3060 /*
3061  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3062  */
3063 static void
3064 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3065 {
3066         struct ixgbe_hw *hw =
3067                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         struct ixgbe_hw_stats *hw_stats =
3069                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3070         struct ixgbe_macsec_stats *macsec_stats =
3071                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3072                                 dev->data->dev_private);
3073         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3074         unsigned i;
3075
3076         total_missed_rx = 0;
3077         total_qbrc = 0;
3078         total_qprc = 0;
3079         total_qprdc = 0;
3080
3081         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3082                         &total_qbrc, &total_qprc, &total_qprdc);
3083
3084         if (stats == NULL)
3085                 return;
3086
3087         /* Fill out the rte_eth_stats statistics structure */
3088         stats->ipackets = total_qprc;
3089         stats->ibytes = total_qbrc;
3090         stats->opackets = hw_stats->gptc;
3091         stats->obytes = hw_stats->gotc;
3092
3093         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3094                 stats->q_ipackets[i] = hw_stats->qprc[i];
3095                 stats->q_opackets[i] = hw_stats->qptc[i];
3096                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3097                 stats->q_obytes[i] = hw_stats->qbtc[i];
3098                 stats->q_errors[i] = hw_stats->qprdc[i];
3099         }
3100
3101         /* Rx Errors */
3102         stats->imissed  = total_missed_rx;
3103         stats->ierrors  = hw_stats->crcerrs +
3104                           hw_stats->mspdc +
3105                           hw_stats->rlec +
3106                           hw_stats->ruc +
3107                           hw_stats->roc +
3108                           hw_stats->illerrc +
3109                           hw_stats->errbc +
3110                           hw_stats->rfc +
3111                           hw_stats->fccrc +
3112                           hw_stats->fclast;
3113
3114         /* Tx Errors */
3115         stats->oerrors  = 0;
3116 }
3117
3118 static void
3119 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3120 {
3121         struct ixgbe_hw_stats *stats =
3122                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3123
3124         /* HW registers are cleared on read */
3125         ixgbe_dev_stats_get(dev, NULL);
3126
3127         /* Reset software totals */
3128         memset(stats, 0, sizeof(*stats));
3129 }
3130
3131 /* This function calculates the number of xstats based on the current config */
3132 static unsigned
3133 ixgbe_xstats_calc_num(void) {
3134         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3135                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3136                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3137 }
3138
3139 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3140         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3141 {
3142         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3143         unsigned stat, i, count;
3144
3145         if (xstats_names != NULL) {
3146                 count = 0;
3147
3148                 /* Note: limit >= cnt_stats checked upstream
3149                  * in rte_eth_xstats_names()
3150                  */
3151
3152                 /* Extended stats from ixgbe_hw_stats */
3153                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3154                         snprintf(xstats_names[count].name,
3155                                 sizeof(xstats_names[count].name),
3156                                 "%s",
3157                                 rte_ixgbe_stats_strings[i].name);
3158                         count++;
3159                 }
3160
3161                 /* MACsec Stats */
3162                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3163                         snprintf(xstats_names[count].name,
3164                                 sizeof(xstats_names[count].name),
3165                                 "%s",
3166                                 rte_ixgbe_macsec_strings[i].name);
3167                         count++;
3168                 }
3169
3170                 /* RX Priority Stats */
3171                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3172                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3173                                 snprintf(xstats_names[count].name,
3174                                         sizeof(xstats_names[count].name),
3175                                         "rx_priority%u_%s", i,
3176                                         rte_ixgbe_rxq_strings[stat].name);
3177                                 count++;
3178                         }
3179                 }
3180
3181                 /* TX Priority Stats */
3182                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3183                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3184                                 snprintf(xstats_names[count].name,
3185                                         sizeof(xstats_names[count].name),
3186                                         "tx_priority%u_%s", i,
3187                                         rte_ixgbe_txq_strings[stat].name);
3188                                 count++;
3189                         }
3190                 }
3191         }
3192         return cnt_stats;
3193 }
3194
3195 static int ixgbe_dev_xstats_get_names_by_ids(
3196         __rte_unused struct rte_eth_dev *dev,
3197         struct rte_eth_xstat_name *xstats_names,
3198         uint64_t *ids,
3199         unsigned int limit)
3200 {
3201         if (!ids) {
3202                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3203                 unsigned int stat, i, count;
3204
3205                 if (xstats_names != NULL) {
3206                         count = 0;
3207
3208                         /* Note: limit >= cnt_stats checked upstream
3209                          * in rte_eth_xstats_names()
3210                          */
3211
3212                         /* Extended stats from ixgbe_hw_stats */
3213                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3214                                 snprintf(xstats_names[count].name,
3215                                         sizeof(xstats_names[count].name),
3216                                         "%s",
3217                                         rte_ixgbe_stats_strings[i].name);
3218                                 count++;
3219                         }
3220
3221                         /* MACsec Stats */
3222                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3223                                 snprintf(xstats_names[count].name,
3224                                         sizeof(xstats_names[count].name),
3225                                         "%s",
3226                                         rte_ixgbe_macsec_strings[i].name);
3227                                 count++;
3228                         }
3229
3230                         /* RX Priority Stats */
3231                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3232                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3233                                         snprintf(xstats_names[count].name,
3234                                             sizeof(xstats_names[count].name),
3235                                             "rx_priority%u_%s", i,
3236                                             rte_ixgbe_rxq_strings[stat].name);
3237                                         count++;
3238                                 }
3239                         }
3240
3241                         /* TX Priority Stats */
3242                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3243                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3244                                         snprintf(xstats_names[count].name,
3245                                             sizeof(xstats_names[count].name),
3246                                             "tx_priority%u_%s", i,
3247                                             rte_ixgbe_txq_strings[stat].name);
3248                                         count++;
3249                                 }
3250                         }
3251                 }
3252                 return cnt_stats;
3253         }
3254
3255         uint16_t i;
3256         uint16_t size = ixgbe_xstats_calc_num();
3257         struct rte_eth_xstat_name xstats_names_copy[size];
3258
3259         ixgbe_dev_xstats_get_names_by_ids(dev, xstats_names_copy, NULL,
3260                         size);
3261
3262         for (i = 0; i < limit; i++) {
3263                 if (ids[i] >= size) {
3264                         PMD_INIT_LOG(ERR, "id value isn't valid");
3265                         return -1;
3266                 }
3267                 strcpy(xstats_names[i].name,
3268                                 xstats_names_copy[ids[i]].name);
3269         }
3270         return limit;
3271 }
3272
3273 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3274         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3275 {
3276         unsigned i;
3277
3278         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3279                 return -ENOMEM;
3280
3281         if (xstats_names != NULL)
3282                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3283                         snprintf(xstats_names[i].name,
3284                                 sizeof(xstats_names[i].name),
3285                                 "%s", rte_ixgbevf_stats_strings[i].name);
3286         return IXGBEVF_NB_XSTATS;
3287 }
3288
3289 static int
3290 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3291                                          unsigned n)
3292 {
3293         struct ixgbe_hw *hw =
3294                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295         struct ixgbe_hw_stats *hw_stats =
3296                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3297         struct ixgbe_macsec_stats *macsec_stats =
3298                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3299                                 dev->data->dev_private);
3300         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3301         unsigned i, stat, count = 0;
3302
3303         count = ixgbe_xstats_calc_num();
3304
3305         if (n < count)
3306                 return count;
3307
3308         total_missed_rx = 0;
3309         total_qbrc = 0;
3310         total_qprc = 0;
3311         total_qprdc = 0;
3312
3313         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3314                         &total_qbrc, &total_qprc, &total_qprdc);
3315
3316         /* If this is a reset xstats is NULL, and we have cleared the
3317          * registers by reading them.
3318          */
3319         if (!xstats)
3320                 return 0;
3321
3322         /* Extended stats from ixgbe_hw_stats */
3323         count = 0;
3324         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3325                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3326                                 rte_ixgbe_stats_strings[i].offset);
3327                 xstats[count].id = count;
3328                 count++;
3329         }
3330
3331         /* MACsec Stats */
3332         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3333                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3334                                 rte_ixgbe_macsec_strings[i].offset);
3335                 xstats[count].id = count;
3336                 count++;
3337         }
3338
3339         /* RX Priority Stats */
3340         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3341                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3342                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3343                                         rte_ixgbe_rxq_strings[stat].offset +
3344                                         (sizeof(uint64_t) * i));
3345                         xstats[count].id = count;
3346                         count++;
3347                 }
3348         }
3349
3350         /* TX Priority Stats */
3351         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3352                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3353                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3354                                         rte_ixgbe_txq_strings[stat].offset +
3355                                         (sizeof(uint64_t) * i));
3356                         xstats[count].id = count;
3357                         count++;
3358                 }
3359         }
3360         return count;
3361 }
3362
3363 static int
3364 ixgbe_dev_xstats_get_by_ids(struct rte_eth_dev *dev, uint64_t *ids,
3365                 uint64_t *values, unsigned int n)
3366 {
3367         if (!ids) {
3368                 struct ixgbe_hw *hw =
3369                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3370                 struct ixgbe_hw_stats *hw_stats =
3371                                 IXGBE_DEV_PRIVATE_TO_STATS(
3372                                                 dev->data->dev_private);
3373                 struct ixgbe_macsec_stats *macsec_stats =
3374                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3375                                         dev->data->dev_private);
3376                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3377                 unsigned int i, stat, count = 0;
3378
3379                 count = ixgbe_xstats_calc_num();
3380
3381                 if (!ids && n < count)
3382                         return count;
3383
3384                 total_missed_rx = 0;
3385                 total_qbrc = 0;
3386                 total_qprc = 0;
3387                 total_qprdc = 0;
3388
3389                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3390                                 &total_missed_rx, &total_qbrc, &total_qprc,
3391                                 &total_qprdc);
3392
3393                 /* If this is a reset xstats is NULL, and we have cleared the
3394                  * registers by reading them.
3395                  */
3396                 if (!ids && !values)
3397                         return 0;
3398
3399                 /* Extended stats from ixgbe_hw_stats */
3400                 count = 0;
3401                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3402                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3403                                         rte_ixgbe_stats_strings[i].offset);
3404                         count++;
3405                 }
3406
3407                 /* MACsec Stats */
3408                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3409                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3410                                         rte_ixgbe_macsec_strings[i].offset);
3411                         count++;
3412                 }
3413
3414                 /* RX Priority Stats */
3415                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3416                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3417                                 values[count] =
3418                                         *(uint64_t *)(((char *)hw_stats) +
3419                                         rte_ixgbe_rxq_strings[stat].offset +
3420                                         (sizeof(uint64_t) * i));
3421                                 count++;
3422                         }
3423                 }
3424
3425                 /* TX Priority Stats */
3426                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3427                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3428                                 values[count] =
3429                                         *(uint64_t *)(((char *)hw_stats) +
3430                                         rte_ixgbe_txq_strings[stat].offset +
3431                                         (sizeof(uint64_t) * i));
3432                                 count++;
3433                         }
3434                 }
3435                 return count;
3436         }
3437
3438         uint16_t i;
3439         uint16_t size = ixgbe_xstats_calc_num();
3440         uint64_t values_copy[size];
3441
3442         ixgbe_dev_xstats_get_by_ids(dev, NULL, values_copy, size);
3443
3444         for (i = 0; i < n; i++) {
3445                 if (ids[i] >= size) {
3446                         PMD_INIT_LOG(ERR, "id value isn't valid");
3447                         return -1;
3448                 }
3449                 values[i] = values_copy[ids[i]];
3450         }
3451         return n;
3452 }
3453
3454 static void
3455 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3456 {
3457         struct ixgbe_hw_stats *stats =
3458                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3459         struct ixgbe_macsec_stats *macsec_stats =
3460                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3461                                 dev->data->dev_private);
3462
3463         unsigned count = ixgbe_xstats_calc_num();
3464
3465         /* HW registers are cleared on read */
3466         ixgbe_dev_xstats_get(dev, NULL, count);
3467
3468         /* Reset software totals */
3469         memset(stats, 0, sizeof(*stats));
3470         memset(macsec_stats, 0, sizeof(*macsec_stats));
3471 }
3472
3473 static void
3474 ixgbevf_update_stats(struct rte_eth_dev *dev)
3475 {
3476         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3477         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3478                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3479
3480         /* Good Rx packet, include VF loopback */
3481         UPDATE_VF_STAT(IXGBE_VFGPRC,
3482             hw_stats->last_vfgprc, hw_stats->vfgprc);
3483
3484         /* Good Rx octets, include VF loopback */
3485         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3486             hw_stats->last_vfgorc, hw_stats->vfgorc);
3487
3488         /* Good Tx packet, include VF loopback */
3489         UPDATE_VF_STAT(IXGBE_VFGPTC,
3490             hw_stats->last_vfgptc, hw_stats->vfgptc);
3491
3492         /* Good Tx octets, include VF loopback */
3493         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3494             hw_stats->last_vfgotc, hw_stats->vfgotc);
3495
3496         /* Rx Multicst Packet */
3497         UPDATE_VF_STAT(IXGBE_VFMPRC,
3498             hw_stats->last_vfmprc, hw_stats->vfmprc);
3499 }
3500
3501 static int
3502 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3503                        unsigned n)
3504 {
3505         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3506                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3507         unsigned i;
3508
3509         if (n < IXGBEVF_NB_XSTATS)
3510                 return IXGBEVF_NB_XSTATS;
3511
3512         ixgbevf_update_stats(dev);
3513
3514         if (!xstats)
3515                 return 0;
3516
3517         /* Extended stats */
3518         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3519                 xstats[i].id = i;
3520                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3521                         rte_ixgbevf_stats_strings[i].offset);
3522         }
3523
3524         return IXGBEVF_NB_XSTATS;
3525 }
3526
3527 static void
3528 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3529 {
3530         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3531                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3532
3533         ixgbevf_update_stats(dev);
3534
3535         if (stats == NULL)
3536                 return;
3537
3538         stats->ipackets = hw_stats->vfgprc;
3539         stats->ibytes = hw_stats->vfgorc;
3540         stats->opackets = hw_stats->vfgptc;
3541         stats->obytes = hw_stats->vfgotc;
3542 }
3543
3544 static void
3545 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3546 {
3547         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3548                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3549
3550         /* Sync HW register to the last stats */
3551         ixgbevf_dev_stats_get(dev, NULL);
3552
3553         /* reset HW current stats*/
3554         hw_stats->vfgprc = 0;
3555         hw_stats->vfgorc = 0;
3556         hw_stats->vfgptc = 0;
3557         hw_stats->vfgotc = 0;
3558 }
3559
3560 static int
3561 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3562 {
3563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3564         u16 eeprom_verh, eeprom_verl;
3565         u32 etrack_id;
3566         int ret;
3567
3568         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3569         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3570
3571         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3572         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3573
3574         ret += 1; /* add the size of '\0' */
3575         if (fw_size < (u32)ret)
3576                 return ret;
3577         else
3578                 return 0;
3579 }
3580
3581 static void
3582 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3583 {
3584         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3585         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3587
3588         dev_info->pci_dev = pci_dev;
3589         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3590         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3591         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3592                 /*
3593                  * When DCB/VT is off, maximum number of queues changes,
3594                  * except for 82598EB, which remains constant.
3595                  */
3596                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3597                                 hw->mac.type != ixgbe_mac_82598EB)
3598                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3599         }
3600         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3601         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3602         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3603         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3604         dev_info->max_vfs = pci_dev->max_vfs;
3605         if (hw->mac.type == ixgbe_mac_82598EB)
3606                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3607         else
3608                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3609         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3610         dev_info->rx_offload_capa =
3611                 DEV_RX_OFFLOAD_VLAN_STRIP |
3612                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3613                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3614                 DEV_RX_OFFLOAD_TCP_CKSUM;
3615
3616         /*
3617          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3618          * mode.
3619          */
3620         if ((hw->mac.type == ixgbe_mac_82599EB ||
3621              hw->mac.type == ixgbe_mac_X540) &&
3622             !RTE_ETH_DEV_SRIOV(dev).active)
3623                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3624
3625         if (hw->mac.type == ixgbe_mac_82599EB ||
3626             hw->mac.type == ixgbe_mac_X540)
3627                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3628
3629         if (hw->mac.type == ixgbe_mac_X550 ||
3630             hw->mac.type == ixgbe_mac_X550EM_x ||
3631             hw->mac.type == ixgbe_mac_X550EM_a)
3632                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3633
3634         dev_info->tx_offload_capa =
3635                 DEV_TX_OFFLOAD_VLAN_INSERT |
3636                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3637                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3638                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3639                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3640                 DEV_TX_OFFLOAD_TCP_TSO;
3641
3642         if (hw->mac.type == ixgbe_mac_82599EB ||
3643             hw->mac.type == ixgbe_mac_X540)
3644                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3645
3646         if (hw->mac.type == ixgbe_mac_X550 ||
3647             hw->mac.type == ixgbe_mac_X550EM_x ||
3648             hw->mac.type == ixgbe_mac_X550EM_a)
3649                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3650
3651         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3652                 .rx_thresh = {
3653                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3654                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3655                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3656                 },
3657                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3658                 .rx_drop_en = 0,
3659         };
3660
3661         dev_info->default_txconf = (struct rte_eth_txconf) {
3662                 .tx_thresh = {
3663                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3664                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3665                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3666                 },
3667                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3668                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3669                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3670                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3671         };
3672
3673         dev_info->rx_desc_lim = rx_desc_lim;
3674         dev_info->tx_desc_lim = tx_desc_lim;
3675
3676         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3677         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3678         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3679
3680         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3681         if (hw->mac.type == ixgbe_mac_X540 ||
3682             hw->mac.type == ixgbe_mac_X540_vf ||
3683             hw->mac.type == ixgbe_mac_X550 ||
3684             hw->mac.type == ixgbe_mac_X550_vf) {
3685                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3686         }
3687 }
3688
3689 static const uint32_t *
3690 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3691 {
3692         static const uint32_t ptypes[] = {
3693                 /* For non-vec functions,
3694                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3695                  * for vec functions,
3696                  * refers to _recv_raw_pkts_vec().
3697                  */
3698                 RTE_PTYPE_L2_ETHER,
3699                 RTE_PTYPE_L3_IPV4,
3700                 RTE_PTYPE_L3_IPV4_EXT,
3701                 RTE_PTYPE_L3_IPV6,
3702                 RTE_PTYPE_L3_IPV6_EXT,
3703                 RTE_PTYPE_L4_SCTP,
3704                 RTE_PTYPE_L4_TCP,
3705                 RTE_PTYPE_L4_UDP,
3706                 RTE_PTYPE_TUNNEL_IP,
3707                 RTE_PTYPE_INNER_L3_IPV6,
3708                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3709                 RTE_PTYPE_INNER_L4_TCP,
3710                 RTE_PTYPE_INNER_L4_UDP,
3711                 RTE_PTYPE_UNKNOWN
3712         };
3713
3714         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3715             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3716             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3717             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3718                 return ptypes;
3719         return NULL;
3720 }
3721
3722 static void
3723 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3724                      struct rte_eth_dev_info *dev_info)
3725 {
3726         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3728
3729         dev_info->pci_dev = pci_dev;
3730         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3731         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3732         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3733         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3734         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3735         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3736         dev_info->max_vfs = pci_dev->max_vfs;
3737         if (hw->mac.type == ixgbe_mac_82598EB)
3738                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3739         else
3740                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3741         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3742                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3743                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3744                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3745         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3746                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3747                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3748                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3749                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3750                                 DEV_TX_OFFLOAD_TCP_TSO;
3751
3752         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3753                 .rx_thresh = {
3754                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3755                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3756                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3757                 },
3758                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3759                 .rx_drop_en = 0,
3760         };
3761
3762         dev_info->default_txconf = (struct rte_eth_txconf) {
3763                 .tx_thresh = {
3764                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3765                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3766                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3767                 },
3768                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3769                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3770                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3771                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3772         };
3773
3774         dev_info->rx_desc_lim = rx_desc_lim;
3775         dev_info->tx_desc_lim = tx_desc_lim;
3776 }
3777
3778 /* return 0 means link status changed, -1 means not changed */
3779 static int
3780 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3781 {
3782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783         struct rte_eth_link link, old;
3784         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3785         int link_up;
3786         int diag;
3787
3788         link.link_status = ETH_LINK_DOWN;
3789         link.link_speed = 0;
3790         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3791         memset(&old, 0, sizeof(old));
3792         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3793
3794         hw->mac.get_link_status = true;
3795
3796         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3797         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3798                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3799         else
3800                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3801
3802         if (diag != 0) {
3803                 link.link_speed = ETH_SPEED_NUM_100M;
3804                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3805                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3806                 if (link.link_status == old.link_status)
3807                         return -1;
3808                 return 0;
3809         }
3810
3811         if (link_up == 0) {
3812                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3813                 if (link.link_status == old.link_status)
3814                         return -1;
3815                 return 0;
3816         }
3817         link.link_status = ETH_LINK_UP;
3818         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3819
3820         switch (link_speed) {
3821         default:
3822         case IXGBE_LINK_SPEED_UNKNOWN:
3823                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3824                 link.link_speed = ETH_SPEED_NUM_100M;
3825                 break;
3826
3827         case IXGBE_LINK_SPEED_100_FULL:
3828                 link.link_speed = ETH_SPEED_NUM_100M;
3829                 break;
3830
3831         case IXGBE_LINK_SPEED_1GB_FULL:
3832                 link.link_speed = ETH_SPEED_NUM_1G;
3833                 break;
3834
3835         case IXGBE_LINK_SPEED_10GB_FULL:
3836                 link.link_speed = ETH_SPEED_NUM_10G;
3837                 break;
3838         }
3839         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3840
3841         if (link.link_status == old.link_status)
3842                 return -1;
3843
3844         return 0;
3845 }
3846
3847 static void
3848 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3849 {
3850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3851         uint32_t fctrl;
3852
3853         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3854         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3855         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3856 }
3857
3858 static void
3859 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3860 {
3861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3862         uint32_t fctrl;
3863
3864         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3865         fctrl &= (~IXGBE_FCTRL_UPE);
3866         if (dev->data->all_multicast == 1)
3867                 fctrl |= IXGBE_FCTRL_MPE;
3868         else
3869                 fctrl &= (~IXGBE_FCTRL_MPE);
3870         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3871 }
3872
3873 static void
3874 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3875 {
3876         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3877         uint32_t fctrl;
3878
3879         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3880         fctrl |= IXGBE_FCTRL_MPE;
3881         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3882 }
3883
3884 static void
3885 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3886 {
3887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3888         uint32_t fctrl;
3889
3890         if (dev->data->promiscuous == 1)
3891                 return; /* must remain in all_multicast mode */
3892
3893         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3894         fctrl &= (~IXGBE_FCTRL_MPE);
3895         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3896 }
3897
3898 /**
3899  * It clears the interrupt causes and enables the interrupt.
3900  * It will be called once only during nic initialized.
3901  *
3902  * @param dev
3903  *  Pointer to struct rte_eth_dev.
3904  *
3905  * @return
3906  *  - On success, zero.
3907  *  - On failure, a negative value.
3908  */
3909 static int
3910 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3911 {
3912         struct ixgbe_interrupt *intr =
3913                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3914
3915         ixgbe_dev_link_status_print(dev);
3916         intr->mask |= IXGBE_EICR_LSC;
3917
3918         return 0;
3919 }
3920
3921 /**
3922  * It clears the interrupt causes and enables the interrupt.
3923  * It will be called once only during nic initialized.
3924  *
3925  * @param dev
3926  *  Pointer to struct rte_eth_dev.
3927  *
3928  * @return
3929  *  - On success, zero.
3930  *  - On failure, a negative value.
3931  */
3932 static int
3933 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3934 {
3935         struct ixgbe_interrupt *intr =
3936                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3937
3938         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3939
3940         return 0;
3941 }
3942
3943 /**
3944  * It clears the interrupt causes and enables the interrupt.
3945  * It will be called once only during nic initialized.
3946  *
3947  * @param dev
3948  *  Pointer to struct rte_eth_dev.
3949  *
3950  * @return
3951  *  - On success, zero.
3952  *  - On failure, a negative value.
3953  */
3954 static int
3955 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3956 {
3957         struct ixgbe_interrupt *intr =
3958                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3959
3960         intr->mask |= IXGBE_EICR_LINKSEC;
3961
3962         return 0;
3963 }
3964
3965 /*
3966  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3967  *
3968  * @param dev
3969  *  Pointer to struct rte_eth_dev.
3970  *
3971  * @return
3972  *  - On success, zero.
3973  *  - On failure, a negative value.
3974  */
3975 static int
3976 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3977 {
3978         uint32_t eicr;
3979         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3980         struct ixgbe_interrupt *intr =
3981                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3982
3983         /* clear all cause mask */
3984         ixgbe_disable_intr(hw);
3985
3986         /* read-on-clear nic registers here */
3987         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3988         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3989
3990         intr->flags = 0;
3991
3992         /* set flag for async link update */
3993         if (eicr & IXGBE_EICR_LSC)
3994                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3995
3996         if (eicr & IXGBE_EICR_MAILBOX)
3997                 intr->flags |= IXGBE_FLAG_MAILBOX;
3998
3999         if (eicr & IXGBE_EICR_LINKSEC)
4000                 intr->flags |= IXGBE_FLAG_MACSEC;
4001
4002         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4003             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4004             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4005                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4006
4007         return 0;
4008 }
4009
4010 /**
4011  * It gets and then prints the link status.
4012  *
4013  * @param dev
4014  *  Pointer to struct rte_eth_dev.
4015  *
4016  * @return
4017  *  - On success, zero.
4018  *  - On failure, a negative value.
4019  */
4020 static void
4021 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4022 {
4023         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4024         struct rte_eth_link link;
4025
4026         memset(&link, 0, sizeof(link));
4027         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4028         if (link.link_status) {
4029                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4030                                         (int)(dev->data->port_id),
4031                                         (unsigned)link.link_speed,
4032                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4033                                         "full-duplex" : "half-duplex");
4034         } else {
4035                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4036                                 (int)(dev->data->port_id));
4037         }
4038         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4039                                 pci_dev->addr.domain,
4040                                 pci_dev->addr.bus,
4041                                 pci_dev->addr.devid,
4042                                 pci_dev->addr.function);
4043 }
4044
4045 /*
4046  * It executes link_update after knowing an interrupt occurred.
4047  *
4048  * @param dev
4049  *  Pointer to struct rte_eth_dev.
4050  *
4051  * @return
4052  *  - On success, zero.
4053  *  - On failure, a negative value.
4054  */
4055 static int
4056 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4057                            struct rte_intr_handle *intr_handle)
4058 {
4059         struct ixgbe_interrupt *intr =
4060                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4061         int64_t timeout;
4062         struct rte_eth_link link;
4063         struct ixgbe_hw *hw =
4064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4065
4066         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4067
4068         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4069                 ixgbe_pf_mbx_process(dev);
4070                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4071         }
4072
4073         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4074                 ixgbe_handle_lasi(hw);
4075                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4076         }
4077
4078         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4079                 /* get the link status before link update, for predicting later */
4080                 memset(&link, 0, sizeof(link));
4081                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4082
4083                 ixgbe_dev_link_update(dev, 0);
4084
4085                 /* likely to up */
4086                 if (!link.link_status)
4087                         /* handle it 1 sec later, wait it being stable */
4088                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4089                 /* likely to down */
4090                 else
4091                         /* handle it 4 sec later, wait it being stable */
4092                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4093
4094                 ixgbe_dev_link_status_print(dev);
4095                 intr->mask_original = intr->mask;
4096                 /* only disable lsc interrupt */
4097                 intr->mask &= ~IXGBE_EIMS_LSC;
4098                 if (rte_eal_alarm_set(timeout * 1000,
4099                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4100                         PMD_DRV_LOG(ERR, "Error setting alarm");
4101                 else
4102                         intr->mask = intr->mask_original;
4103         }
4104
4105         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4106         ixgbe_enable_intr(dev);
4107         rte_intr_enable(intr_handle);
4108
4109         return 0;
4110 }
4111
4112 /**
4113  * Interrupt handler which shall be registered for alarm callback for delayed
4114  * handling specific interrupt to wait for the stable nic state. As the
4115  * NIC interrupt state is not stable for ixgbe after link is just down,
4116  * it needs to wait 4 seconds to get the stable status.
4117  *
4118  * @param handle
4119  *  Pointer to interrupt handle.
4120  * @param param
4121  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4122  *
4123  * @return
4124  *  void
4125  */
4126 static void
4127 ixgbe_dev_interrupt_delayed_handler(void *param)
4128 {
4129         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4130         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4131         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4132         struct ixgbe_interrupt *intr =
4133                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4134         struct ixgbe_hw *hw =
4135                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4136         uint32_t eicr;
4137
4138         ixgbe_disable_intr(hw);
4139
4140         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4141         if (eicr & IXGBE_EICR_MAILBOX)
4142                 ixgbe_pf_mbx_process(dev);
4143
4144         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4145                 ixgbe_handle_lasi(hw);
4146                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4147         }
4148
4149         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4150                 ixgbe_dev_link_update(dev, 0);
4151                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4152                 ixgbe_dev_link_status_print(dev);
4153                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4154         }
4155
4156         if (intr->flags & IXGBE_FLAG_MACSEC) {
4157                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4158                                               NULL);
4159                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4160         }
4161
4162         /* restore original mask */
4163         intr->mask = intr->mask_original;
4164         intr->mask_original = 0;
4165
4166         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4167         ixgbe_enable_intr(dev);
4168         rte_intr_enable(intr_handle);
4169 }
4170
4171 /**
4172  * Interrupt handler triggered by NIC  for handling
4173  * specific interrupt.
4174  *
4175  * @param handle
4176  *  Pointer to interrupt handle.
4177  * @param param
4178  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4179  *
4180  * @return
4181  *  void
4182  */
4183 static void
4184 ixgbe_dev_interrupt_handler(void *param)
4185 {
4186         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4187
4188         ixgbe_dev_interrupt_get_status(dev);
4189         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4190 }
4191
4192 static int
4193 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4194 {
4195         struct ixgbe_hw *hw;
4196
4197         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4198         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4199 }
4200
4201 static int
4202 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4203 {
4204         struct ixgbe_hw *hw;
4205
4206         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4207         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4208 }
4209
4210 static int
4211 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4212 {
4213         struct ixgbe_hw *hw;
4214         uint32_t mflcn_reg;
4215         uint32_t fccfg_reg;
4216         int rx_pause;
4217         int tx_pause;
4218
4219         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4220
4221         fc_conf->pause_time = hw->fc.pause_time;
4222         fc_conf->high_water = hw->fc.high_water[0];
4223         fc_conf->low_water = hw->fc.low_water[0];
4224         fc_conf->send_xon = hw->fc.send_xon;
4225         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4226
4227         /*
4228          * Return rx_pause status according to actual setting of
4229          * MFLCN register.
4230          */
4231         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4232         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4233                 rx_pause = 1;
4234         else
4235                 rx_pause = 0;
4236
4237         /*
4238          * Return tx_pause status according to actual setting of
4239          * FCCFG register.
4240          */
4241         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4242         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4243                 tx_pause = 1;
4244         else
4245                 tx_pause = 0;
4246
4247         if (rx_pause && tx_pause)
4248                 fc_conf->mode = RTE_FC_FULL;
4249         else if (rx_pause)
4250                 fc_conf->mode = RTE_FC_RX_PAUSE;
4251         else if (tx_pause)
4252                 fc_conf->mode = RTE_FC_TX_PAUSE;
4253         else
4254                 fc_conf->mode = RTE_FC_NONE;
4255
4256         return 0;
4257 }
4258
4259 static int
4260 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4261 {
4262         struct ixgbe_hw *hw;
4263         int err;
4264         uint32_t rx_buf_size;
4265         uint32_t max_high_water;
4266         uint32_t mflcn;
4267         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4268                 ixgbe_fc_none,
4269                 ixgbe_fc_rx_pause,
4270                 ixgbe_fc_tx_pause,
4271                 ixgbe_fc_full
4272         };
4273
4274         PMD_INIT_FUNC_TRACE();
4275
4276         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4277         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4278         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4279
4280         /*
4281          * At least reserve one Ethernet frame for watermark
4282          * high_water/low_water in kilo bytes for ixgbe
4283          */
4284         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4285         if ((fc_conf->high_water > max_high_water) ||
4286                 (fc_conf->high_water < fc_conf->low_water)) {
4287                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4288                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4289                 return -EINVAL;
4290         }
4291
4292         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4293         hw->fc.pause_time     = fc_conf->pause_time;
4294         hw->fc.high_water[0]  = fc_conf->high_water;
4295         hw->fc.low_water[0]   = fc_conf->low_water;
4296         hw->fc.send_xon       = fc_conf->send_xon;
4297         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4298
4299         err = ixgbe_fc_enable(hw);
4300
4301         /* Not negotiated is not an error case */
4302         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4303
4304                 /* check if we want to forward MAC frames - driver doesn't have native
4305                  * capability to do that, so we'll write the registers ourselves */
4306
4307                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4308
4309                 /* set or clear MFLCN.PMCF bit depending on configuration */
4310                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4311                         mflcn |= IXGBE_MFLCN_PMCF;
4312                 else
4313                         mflcn &= ~IXGBE_MFLCN_PMCF;
4314
4315                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4316                 IXGBE_WRITE_FLUSH(hw);
4317
4318                 return 0;
4319         }
4320
4321         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4322         return -EIO;
4323 }
4324
4325 /**
4326  *  ixgbe_pfc_enable_generic - Enable flow control
4327  *  @hw: pointer to hardware structure
4328  *  @tc_num: traffic class number
4329  *  Enable flow control according to the current settings.
4330  */
4331 static int
4332 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4333 {
4334         int ret_val = 0;
4335         uint32_t mflcn_reg, fccfg_reg;
4336         uint32_t reg;
4337         uint32_t fcrtl, fcrth;
4338         uint8_t i;
4339         uint8_t nb_rx_en;
4340
4341         /* Validate the water mark configuration */
4342         if (!hw->fc.pause_time) {
4343                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4344                 goto out;
4345         }
4346
4347         /* Low water mark of zero causes XOFF floods */
4348         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4349                  /* High/Low water can not be 0 */
4350                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4351                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4352                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4353                         goto out;
4354                 }
4355
4356                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4357                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4358                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4359                         goto out;
4360                 }
4361         }
4362         /* Negotiate the fc mode to use */
4363         ixgbe_fc_autoneg(hw);
4364
4365         /* Disable any previous flow control settings */
4366         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4367         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4368
4369         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4370         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4371
4372         switch (hw->fc.current_mode) {
4373         case ixgbe_fc_none:
4374                 /*
4375                  * If the count of enabled RX Priority Flow control >1,
4376                  * and the TX pause can not be disabled
4377                  */
4378                 nb_rx_en = 0;
4379                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4380                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4381                         if (reg & IXGBE_FCRTH_FCEN)
4382                                 nb_rx_en++;
4383                 }
4384                 if (nb_rx_en > 1)
4385                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4386                 break;
4387         case ixgbe_fc_rx_pause:
4388                 /*
4389                  * Rx Flow control is enabled and Tx Flow control is
4390                  * disabled by software override. Since there really
4391                  * isn't a way to advertise that we are capable of RX
4392                  * Pause ONLY, we will advertise that we support both
4393                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4394                  * disable the adapter's ability to send PAUSE frames.
4395                  */
4396                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4397                 /*
4398                  * If the count of enabled RX Priority Flow control >1,
4399                  * and the TX pause can not be disabled
4400                  */
4401                 nb_rx_en = 0;
4402                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4403                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4404                         if (reg & IXGBE_FCRTH_FCEN)
4405                                 nb_rx_en++;
4406                 }
4407                 if (nb_rx_en > 1)
4408                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4409                 break;
4410         case ixgbe_fc_tx_pause:
4411                 /*
4412                  * Tx Flow control is enabled, and Rx Flow control is
4413                  * disabled by software override.
4414                  */
4415                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4416                 break;
4417         case ixgbe_fc_full:
4418                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4419                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4420                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4421                 break;
4422         default:
4423                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4424                 ret_val = IXGBE_ERR_CONFIG;
4425                 goto out;
4426         }
4427
4428         /* Set 802.3x based flow control settings. */
4429         mflcn_reg |= IXGBE_MFLCN_DPF;
4430         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4431         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4432
4433         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4434         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4435                 hw->fc.high_water[tc_num]) {
4436                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4437                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4438                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4439         } else {
4440                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4441                 /*
4442                  * In order to prevent Tx hangs when the internal Tx
4443                  * switch is enabled we must set the high water mark
4444                  * to the maximum FCRTH value.  This allows the Tx
4445                  * switch to function even under heavy Rx workloads.
4446                  */
4447                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4448         }
4449         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4450
4451         /* Configure pause time (2 TCs per register) */
4452         reg = hw->fc.pause_time * 0x00010001;
4453         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4454                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4455
4456         /* Configure flow control refresh threshold value */
4457         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4458
4459 out:
4460         return ret_val;
4461 }
4462
4463 static int
4464 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4465 {
4466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4467         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4468
4469         if (hw->mac.type != ixgbe_mac_82598EB) {
4470                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4471         }
4472         return ret_val;
4473 }
4474
4475 static int
4476 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4477 {
4478         int err;
4479         uint32_t rx_buf_size;
4480         uint32_t max_high_water;
4481         uint8_t tc_num;
4482         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4483         struct ixgbe_hw *hw =
4484                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4485         struct ixgbe_dcb_config *dcb_config =
4486                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4487
4488         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4489                 ixgbe_fc_none,
4490                 ixgbe_fc_rx_pause,
4491                 ixgbe_fc_tx_pause,
4492                 ixgbe_fc_full
4493         };
4494
4495         PMD_INIT_FUNC_TRACE();
4496
4497         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4498         tc_num = map[pfc_conf->priority];
4499         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4500         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4501         /*
4502          * At least reserve one Ethernet frame for watermark
4503          * high_water/low_water in kilo bytes for ixgbe
4504          */
4505         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4506         if ((pfc_conf->fc.high_water > max_high_water) ||
4507             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4508                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4509                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4510                 return -EINVAL;
4511         }
4512
4513         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4514         hw->fc.pause_time = pfc_conf->fc.pause_time;
4515         hw->fc.send_xon = pfc_conf->fc.send_xon;
4516         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4517         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4518
4519         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4520
4521         /* Not negotiated is not an error case */
4522         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4523                 return 0;
4524
4525         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4526         return -EIO;
4527 }
4528
4529 static int
4530 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4531                           struct rte_eth_rss_reta_entry64 *reta_conf,
4532                           uint16_t reta_size)
4533 {
4534         uint16_t i, sp_reta_size;
4535         uint8_t j, mask;
4536         uint32_t reta, r;
4537         uint16_t idx, shift;
4538         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4539         uint32_t reta_reg;
4540
4541         PMD_INIT_FUNC_TRACE();
4542
4543         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4544                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4545                         "NIC.");
4546                 return -ENOTSUP;
4547         }
4548
4549         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4550         if (reta_size != sp_reta_size) {
4551                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4552                         "(%d) doesn't match the number hardware can supported "
4553                         "(%d)", reta_size, sp_reta_size);
4554                 return -EINVAL;
4555         }
4556
4557         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4558                 idx = i / RTE_RETA_GROUP_SIZE;
4559                 shift = i % RTE_RETA_GROUP_SIZE;
4560                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4561                                                 IXGBE_4_BIT_MASK);
4562                 if (!mask)
4563                         continue;
4564                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4565                 if (mask == IXGBE_4_BIT_MASK)
4566                         r = 0;
4567                 else
4568                         r = IXGBE_READ_REG(hw, reta_reg);
4569                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4570                         if (mask & (0x1 << j))
4571                                 reta |= reta_conf[idx].reta[shift + j] <<
4572                                                         (CHAR_BIT * j);
4573                         else
4574                                 reta |= r & (IXGBE_8_BIT_MASK <<
4575                                                 (CHAR_BIT * j));
4576                 }
4577                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4578         }
4579
4580         return 0;
4581 }
4582
4583 static int
4584 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4585                          struct rte_eth_rss_reta_entry64 *reta_conf,
4586                          uint16_t reta_size)
4587 {
4588         uint16_t i, sp_reta_size;
4589         uint8_t j, mask;
4590         uint32_t reta;
4591         uint16_t idx, shift;
4592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4593         uint32_t reta_reg;
4594
4595         PMD_INIT_FUNC_TRACE();
4596         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4597         if (reta_size != sp_reta_size) {
4598                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4599                         "(%d) doesn't match the number hardware can supported "
4600                         "(%d)", reta_size, sp_reta_size);
4601                 return -EINVAL;
4602         }
4603
4604         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4605                 idx = i / RTE_RETA_GROUP_SIZE;
4606                 shift = i % RTE_RETA_GROUP_SIZE;
4607                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4608                                                 IXGBE_4_BIT_MASK);
4609                 if (!mask)
4610                         continue;
4611
4612                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4613                 reta = IXGBE_READ_REG(hw, reta_reg);
4614                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4615                         if (mask & (0x1 << j))
4616                                 reta_conf[idx].reta[shift + j] =
4617                                         ((reta >> (CHAR_BIT * j)) &
4618                                                 IXGBE_8_BIT_MASK);
4619                 }
4620         }
4621
4622         return 0;
4623 }
4624
4625 static void
4626 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4627                                 uint32_t index, uint32_t pool)
4628 {
4629         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4630         uint32_t enable_addr = 1;
4631
4632         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4633 }
4634
4635 static void
4636 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4637 {
4638         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4639
4640         ixgbe_clear_rar(hw, index);
4641 }
4642
4643 static void
4644 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4645 {
4646         ixgbe_remove_rar(dev, 0);
4647
4648         ixgbe_add_rar(dev, addr, 0, 0);
4649 }
4650
4651 static bool
4652 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4653 {
4654         if (strcmp(dev->data->drv_name, drv->driver.name))
4655                 return false;
4656
4657         return true;
4658 }
4659
4660 bool
4661 is_ixgbe_supported(struct rte_eth_dev *dev)
4662 {
4663         return is_device_supported(dev, &rte_ixgbe_pmd);
4664 }
4665
4666 static int
4667 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4668 {
4669         uint32_t hlreg0;
4670         uint32_t maxfrs;
4671         struct ixgbe_hw *hw;
4672         struct rte_eth_dev_info dev_info;
4673         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4674
4675         ixgbe_dev_info_get(dev, &dev_info);
4676
4677         /* check that mtu is within the allowed range */
4678         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4679                 return -EINVAL;
4680
4681         /* refuse mtu that requires the support of scattered packets when this
4682          * feature has not been enabled before.
4683          */
4684         if (!dev->data->scattered_rx &&
4685             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4686              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4687                 return -EINVAL;
4688
4689         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4690         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4691
4692         /* switch to jumbo mode if needed */
4693         if (frame_size > ETHER_MAX_LEN) {
4694                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4695                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4696         } else {
4697                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4698                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4699         }
4700         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4701
4702         /* update max frame size */
4703         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4704
4705         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4706         maxfrs &= 0x0000FFFF;
4707         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4708         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4709
4710         return 0;
4711 }
4712
4713 /*
4714  * Virtual Function operations
4715  */
4716 static void
4717 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4718 {
4719         PMD_INIT_FUNC_TRACE();
4720
4721         /* Clear interrupt mask to stop from interrupts being generated */
4722         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4723
4724         IXGBE_WRITE_FLUSH(hw);
4725 }
4726
4727 static void
4728 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4729 {
4730         PMD_INIT_FUNC_TRACE();
4731
4732         /* VF enable interrupt autoclean */
4733         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4734         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4735         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4736
4737         IXGBE_WRITE_FLUSH(hw);
4738 }
4739
4740 static int
4741 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4742 {
4743         struct rte_eth_conf *conf = &dev->data->dev_conf;
4744         struct ixgbe_adapter *adapter =
4745                         (struct ixgbe_adapter *)dev->data->dev_private;
4746
4747         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4748                      dev->data->port_id);
4749
4750         /*
4751          * VF has no ability to enable/disable HW CRC
4752          * Keep the persistent behavior the same as Host PF
4753          */
4754 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4755         if (!conf->rxmode.hw_strip_crc) {
4756                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4757                 conf->rxmode.hw_strip_crc = 1;
4758         }
4759 #else
4760         if (conf->rxmode.hw_strip_crc) {
4761                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4762                 conf->rxmode.hw_strip_crc = 0;
4763         }
4764 #endif
4765
4766         /*
4767          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4768          * allocation or vector Rx preconditions we will reset it.
4769          */
4770         adapter->rx_bulk_alloc_allowed = true;
4771         adapter->rx_vec_allowed = true;
4772
4773         return 0;
4774 }
4775
4776 static int
4777 ixgbevf_dev_start(struct rte_eth_dev *dev)
4778 {
4779         struct ixgbe_hw *hw =
4780                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4781         uint32_t intr_vector = 0;
4782         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4783         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4784
4785         int err, mask = 0;
4786
4787         PMD_INIT_FUNC_TRACE();
4788
4789         hw->mac.ops.reset_hw(hw);
4790         hw->mac.get_link_status = true;
4791
4792         /* negotiate mailbox API version to use with the PF. */
4793         ixgbevf_negotiate_api(hw);
4794
4795         ixgbevf_dev_tx_init(dev);
4796
4797         /* This can fail when allocating mbufs for descriptor rings */
4798         err = ixgbevf_dev_rx_init(dev);
4799         if (err) {
4800                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4801                 ixgbe_dev_clear_queues(dev);
4802                 return err;
4803         }
4804
4805         /* Set vfta */
4806         ixgbevf_set_vfta_all(dev, 1);
4807
4808         /* Set HW strip */
4809         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4810                 ETH_VLAN_EXTEND_MASK;
4811         ixgbevf_vlan_offload_set(dev, mask);
4812
4813         ixgbevf_dev_rxtx_start(dev);
4814
4815         /* check and configure queue intr-vector mapping */
4816         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4817                 intr_vector = dev->data->nb_rx_queues;
4818                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4819                         return -1;
4820         }
4821
4822         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4823                 intr_handle->intr_vec =
4824                         rte_zmalloc("intr_vec",
4825                                     dev->data->nb_rx_queues * sizeof(int), 0);
4826                 if (intr_handle->intr_vec == NULL) {
4827                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4828                                      " intr_vec", dev->data->nb_rx_queues);
4829                         return -ENOMEM;
4830                 }
4831         }
4832         ixgbevf_configure_msix(dev);
4833
4834         rte_intr_enable(intr_handle);
4835
4836         /* Re-enable interrupt for VF */
4837         ixgbevf_intr_enable(hw);
4838
4839         return 0;
4840 }
4841
4842 static void
4843 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4844 {
4845         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4846         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4847         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4848
4849         PMD_INIT_FUNC_TRACE();
4850
4851         ixgbevf_intr_disable(hw);
4852
4853         hw->adapter_stopped = 1;
4854         ixgbe_stop_adapter(hw);
4855
4856         /*
4857           * Clear what we set, but we still keep shadow_vfta to
4858           * restore after device starts
4859           */
4860         ixgbevf_set_vfta_all(dev, 0);
4861
4862         /* Clear stored conf */
4863         dev->data->scattered_rx = 0;
4864
4865         ixgbe_dev_clear_queues(dev);
4866
4867         /* Clean datapath event and queue/vec mapping */
4868         rte_intr_efd_disable(intr_handle);
4869         if (intr_handle->intr_vec != NULL) {
4870                 rte_free(intr_handle->intr_vec);
4871                 intr_handle->intr_vec = NULL;
4872         }
4873 }
4874
4875 static void
4876 ixgbevf_dev_close(struct rte_eth_dev *dev)
4877 {
4878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4879
4880         PMD_INIT_FUNC_TRACE();
4881
4882         ixgbe_reset_hw(hw);
4883
4884         ixgbevf_dev_stop(dev);
4885
4886         ixgbe_dev_free_queues(dev);
4887
4888         /**
4889          * Remove the VF MAC address ro ensure
4890          * that the VF traffic goes to the PF
4891          * after stop, close and detach of the VF
4892          **/
4893         ixgbevf_remove_mac_addr(dev, 0);
4894 }
4895
4896 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4897 {
4898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4899         struct ixgbe_vfta *shadow_vfta =
4900                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4901         int i = 0, j = 0, vfta = 0, mask = 1;
4902
4903         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4904                 vfta = shadow_vfta->vfta[i];
4905                 if (vfta) {
4906                         mask = 1;
4907                         for (j = 0; j < 32; j++) {
4908                                 if (vfta & mask)
4909                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4910                                                        on, false);
4911                                 mask <<= 1;
4912                         }
4913                 }
4914         }
4915
4916 }
4917
4918 static int
4919 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4920 {
4921         struct ixgbe_hw *hw =
4922                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4923         struct ixgbe_vfta *shadow_vfta =
4924                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4925         uint32_t vid_idx = 0;
4926         uint32_t vid_bit = 0;
4927         int ret = 0;
4928
4929         PMD_INIT_FUNC_TRACE();
4930
4931         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4932         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4933         if (ret) {
4934                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4935                 return ret;
4936         }
4937         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4938         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4939
4940         /* Save what we set and retore it after device reset */
4941         if (on)
4942                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4943         else
4944                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4945
4946         return 0;
4947 }
4948
4949 static void
4950 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4951 {
4952         struct ixgbe_hw *hw =
4953                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4954         uint32_t ctrl;
4955
4956         PMD_INIT_FUNC_TRACE();
4957
4958         if (queue >= hw->mac.max_rx_queues)
4959                 return;
4960
4961         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4962         if (on)
4963                 ctrl |= IXGBE_RXDCTL_VME;
4964         else
4965                 ctrl &= ~IXGBE_RXDCTL_VME;
4966         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4967
4968         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4969 }
4970
4971 static void
4972 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4973 {
4974         struct ixgbe_hw *hw =
4975                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976         uint16_t i;
4977         int on = 0;
4978
4979         /* VF function only support hw strip feature, others are not support */
4980         if (mask & ETH_VLAN_STRIP_MASK) {
4981                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4982
4983                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4984                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4985         }
4986 }
4987
4988 int
4989 ixgbe_vt_check(struct ixgbe_hw *hw)
4990 {
4991         uint32_t reg_val;
4992
4993         /* if Virtualization Technology is enabled */
4994         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4995         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4996                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4997                 return -1;
4998         }
4999
5000         return 0;
5001 }
5002
5003 static uint32_t
5004 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5005 {
5006         uint32_t vector = 0;
5007
5008         switch (hw->mac.mc_filter_type) {
5009         case 0:   /* use bits [47:36] of the address */
5010                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5011                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5012                 break;
5013         case 1:   /* use bits [46:35] of the address */
5014                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5015                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5016                 break;
5017         case 2:   /* use bits [45:34] of the address */
5018                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5019                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5020                 break;
5021         case 3:   /* use bits [43:32] of the address */
5022                 vector = ((uc_addr->addr_bytes[4]) |
5023                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5024                 break;
5025         default:  /* Invalid mc_filter_type */
5026                 break;
5027         }
5028
5029         /* vector can only be 12-bits or boundary will be exceeded */
5030         vector &= 0xFFF;
5031         return vector;
5032 }
5033
5034 static int
5035 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5036                         uint8_t on)
5037 {
5038         uint32_t vector;
5039         uint32_t uta_idx;
5040         uint32_t reg_val;
5041         uint32_t uta_shift;
5042         uint32_t rc;
5043         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5044         const uint32_t ixgbe_uta_bit_shift = 5;
5045         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5046         const uint32_t bit1 = 0x1;
5047
5048         struct ixgbe_hw *hw =
5049                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5050         struct ixgbe_uta_info *uta_info =
5051                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5052
5053         /* The UTA table only exists on 82599 hardware and newer */
5054         if (hw->mac.type < ixgbe_mac_82599EB)
5055                 return -ENOTSUP;
5056
5057         vector = ixgbe_uta_vector(hw, mac_addr);
5058         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5059         uta_shift = vector & ixgbe_uta_bit_mask;
5060
5061         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5062         if (rc == on)
5063                 return 0;
5064
5065         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5066         if (on) {
5067                 uta_info->uta_in_use++;
5068                 reg_val |= (bit1 << uta_shift);
5069                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5070         } else {
5071                 uta_info->uta_in_use--;
5072                 reg_val &= ~(bit1 << uta_shift);
5073                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5074         }
5075
5076         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5077
5078         if (uta_info->uta_in_use > 0)
5079                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5080                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5081         else
5082                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5083
5084         return 0;
5085 }
5086
5087 static int
5088 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5089 {
5090         int i;
5091         struct ixgbe_hw *hw =
5092                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5093         struct ixgbe_uta_info *uta_info =
5094                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5095
5096         /* The UTA table only exists on 82599 hardware and newer */
5097         if (hw->mac.type < ixgbe_mac_82599EB)
5098                 return -ENOTSUP;
5099
5100         if (on) {
5101                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5102                         uta_info->uta_shadow[i] = ~0;
5103                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5104                 }
5105         } else {
5106                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5107                         uta_info->uta_shadow[i] = 0;
5108                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5109                 }
5110         }
5111         return 0;
5112
5113 }
5114
5115 uint32_t
5116 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5117 {
5118         uint32_t new_val = orig_val;
5119
5120         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5121                 new_val |= IXGBE_VMOLR_AUPE;
5122         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5123                 new_val |= IXGBE_VMOLR_ROMPE;
5124         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5125                 new_val |= IXGBE_VMOLR_ROPE;
5126         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5127                 new_val |= IXGBE_VMOLR_BAM;
5128         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5129                 new_val |= IXGBE_VMOLR_MPE;
5130
5131         return new_val;
5132 }
5133
5134 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5135 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5136 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5137 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5138 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5139         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5140         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5141
5142 static int
5143 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5144                       struct rte_eth_mirror_conf *mirror_conf,
5145                       uint8_t rule_id, uint8_t on)
5146 {
5147         uint32_t mr_ctl, vlvf;
5148         uint32_t mp_lsb = 0;
5149         uint32_t mv_msb = 0;
5150         uint32_t mv_lsb = 0;
5151         uint32_t mp_msb = 0;
5152         uint8_t i = 0;
5153         int reg_index = 0;
5154         uint64_t vlan_mask = 0;
5155
5156         const uint8_t pool_mask_offset = 32;
5157         const uint8_t vlan_mask_offset = 32;
5158         const uint8_t dst_pool_offset = 8;
5159         const uint8_t rule_mr_offset  = 4;
5160         const uint8_t mirror_rule_mask = 0x0F;
5161
5162         struct ixgbe_mirror_info *mr_info =
5163                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5164         struct ixgbe_hw *hw =
5165                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5166         uint8_t mirror_type = 0;
5167
5168         if (ixgbe_vt_check(hw) < 0)
5169                 return -ENOTSUP;
5170
5171         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5172                 return -EINVAL;
5173
5174         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5175                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5176                             mirror_conf->rule_type);
5177                 return -EINVAL;
5178         }
5179
5180         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5181                 mirror_type |= IXGBE_MRCTL_VLME;
5182                 /* Check if vlan id is valid and find conresponding VLAN ID
5183                  * index in VLVF
5184                  */
5185                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5186                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5187                                 /* search vlan id related pool vlan filter
5188                                  * index
5189                                  */
5190                                 reg_index = ixgbe_find_vlvf_slot(
5191                                                 hw,
5192                                                 mirror_conf->vlan.vlan_id[i],
5193                                                 false);
5194                                 if (reg_index < 0)
5195                                         return -EINVAL;
5196                                 vlvf = IXGBE_READ_REG(hw,
5197                                                       IXGBE_VLVF(reg_index));
5198                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5199                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5200                                       mirror_conf->vlan.vlan_id[i]))
5201                                         vlan_mask |= (1ULL << reg_index);
5202                                 else
5203                                         return -EINVAL;
5204                         }
5205                 }
5206
5207                 if (on) {
5208                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5209                         mv_msb = vlan_mask >> vlan_mask_offset;
5210
5211                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5212                                                 mirror_conf->vlan.vlan_mask;
5213                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5214                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5215                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5216                                                 mirror_conf->vlan.vlan_id[i];
5217                         }
5218                 } else {
5219                         mv_lsb = 0;
5220                         mv_msb = 0;
5221                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5222                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5223                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5224                 }
5225         }
5226
5227         /**
5228          * if enable pool mirror, write related pool mask register,if disable
5229          * pool mirror, clear PFMRVM register
5230          */
5231         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5232                 mirror_type |= IXGBE_MRCTL_VPME;
5233                 if (on) {
5234                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5235                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5236                         mr_info->mr_conf[rule_id].pool_mask =
5237                                         mirror_conf->pool_mask;
5238
5239                 } else {
5240                         mp_lsb = 0;
5241                         mp_msb = 0;
5242                         mr_info->mr_conf[rule_id].pool_mask = 0;
5243                 }
5244         }
5245         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5246                 mirror_type |= IXGBE_MRCTL_UPME;
5247         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5248                 mirror_type |= IXGBE_MRCTL_DPME;
5249
5250         /* read  mirror control register and recalculate it */
5251         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5252
5253         if (on) {
5254                 mr_ctl |= mirror_type;
5255                 mr_ctl &= mirror_rule_mask;
5256                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5257         } else {
5258                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5259         }
5260
5261         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5262         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5263
5264         /* write mirrror control  register */
5265         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5266
5267         /* write pool mirrror control  register */
5268         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5269                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5270                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5271                                 mp_msb);
5272         }
5273         /* write VLAN mirrror control  register */
5274         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5275                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5276                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5277                                 mv_msb);
5278         }
5279
5280         return 0;
5281 }
5282
5283 static int
5284 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5285 {
5286         int mr_ctl = 0;
5287         uint32_t lsb_val = 0;
5288         uint32_t msb_val = 0;
5289         const uint8_t rule_mr_offset = 4;
5290
5291         struct ixgbe_hw *hw =
5292                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5293         struct ixgbe_mirror_info *mr_info =
5294                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5295
5296         if (ixgbe_vt_check(hw) < 0)
5297                 return -ENOTSUP;
5298
5299         memset(&mr_info->mr_conf[rule_id], 0,
5300                sizeof(struct rte_eth_mirror_conf));
5301
5302         /* clear PFVMCTL register */
5303         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5304
5305         /* clear pool mask register */
5306         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5307         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5308
5309         /* clear vlan mask register */
5310         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5311         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5312
5313         return 0;
5314 }
5315
5316 static int
5317 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5318 {
5319         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5320         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5321         uint32_t mask;
5322         struct ixgbe_hw *hw =
5323                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5324
5325         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5326         mask |= (1 << IXGBE_MISC_VEC_ID);
5327         RTE_SET_USED(queue_id);
5328         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5329
5330         rte_intr_enable(intr_handle);
5331
5332         return 0;
5333 }
5334
5335 static int
5336 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5337 {
5338         uint32_t mask;
5339         struct ixgbe_hw *hw =
5340                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5341
5342         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5343         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5344         RTE_SET_USED(queue_id);
5345         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5346
5347         return 0;
5348 }
5349
5350 static int
5351 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5352 {
5353         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5354         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5355         uint32_t mask;
5356         struct ixgbe_hw *hw =
5357                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5358         struct ixgbe_interrupt *intr =
5359                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5360
5361         if (queue_id < 16) {
5362                 ixgbe_disable_intr(hw);
5363                 intr->mask |= (1 << queue_id);
5364                 ixgbe_enable_intr(dev);
5365         } else if (queue_id < 32) {
5366                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5367                 mask &= (1 << queue_id);
5368                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5369         } else if (queue_id < 64) {
5370                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5371                 mask &= (1 << (queue_id - 32));
5372                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5373         }
5374         rte_intr_enable(intr_handle);
5375
5376         return 0;
5377 }
5378
5379 static int
5380 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5381 {
5382         uint32_t mask;
5383         struct ixgbe_hw *hw =
5384                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5385         struct ixgbe_interrupt *intr =
5386                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5387
5388         if (queue_id < 16) {
5389                 ixgbe_disable_intr(hw);
5390                 intr->mask &= ~(1 << queue_id);
5391                 ixgbe_enable_intr(dev);
5392         } else if (queue_id < 32) {
5393                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5394                 mask &= ~(1 << queue_id);
5395                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5396         } else if (queue_id < 64) {
5397                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5398                 mask &= ~(1 << (queue_id - 32));
5399                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5400         }
5401
5402         return 0;
5403 }
5404
5405 static void
5406 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5407                      uint8_t queue, uint8_t msix_vector)
5408 {
5409         uint32_t tmp, idx;
5410
5411         if (direction == -1) {
5412                 /* other causes */
5413                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5414                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5415                 tmp &= ~0xFF;
5416                 tmp |= msix_vector;
5417                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5418         } else {
5419                 /* rx or tx cause */
5420                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5421                 idx = ((16 * (queue & 1)) + (8 * direction));
5422                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5423                 tmp &= ~(0xFF << idx);
5424                 tmp |= (msix_vector << idx);
5425                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5426         }
5427 }
5428
5429 /**
5430  * set the IVAR registers, mapping interrupt causes to vectors
5431  * @param hw
5432  *  pointer to ixgbe_hw struct
5433  * @direction
5434  *  0 for Rx, 1 for Tx, -1 for other causes
5435  * @queue
5436  *  queue to map the corresponding interrupt to
5437  * @msix_vector
5438  *  the vector to map to the corresponding queue
5439  */
5440 static void
5441 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5442                    uint8_t queue, uint8_t msix_vector)
5443 {
5444         uint32_t tmp, idx;
5445
5446         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5447         if (hw->mac.type == ixgbe_mac_82598EB) {
5448                 if (direction == -1)
5449                         direction = 0;
5450                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5451                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5452                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5453                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5454                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5455         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5456                         (hw->mac.type == ixgbe_mac_X540)) {
5457                 if (direction == -1) {
5458                         /* other causes */
5459                         idx = ((queue & 1) * 8);
5460                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5461                         tmp &= ~(0xFF << idx);
5462                         tmp |= (msix_vector << idx);
5463                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5464                 } else {
5465                         /* rx or tx causes */
5466                         idx = ((16 * (queue & 1)) + (8 * direction));
5467                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5468                         tmp &= ~(0xFF << idx);
5469                         tmp |= (msix_vector << idx);
5470                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5471                 }
5472         }
5473 }
5474
5475 static void
5476 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5477 {
5478         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5479         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5480         struct ixgbe_hw *hw =
5481                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5482         uint32_t q_idx;
5483         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5484
5485         /* Configure VF other cause ivar */
5486         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5487
5488         /* won't configure msix register if no mapping is done
5489          * between intr vector and event fd.
5490          */
5491         if (!rte_intr_dp_is_en(intr_handle))
5492                 return;
5493
5494         /* Configure all RX queues of VF */
5495         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5496                 /* Force all queue use vector 0,
5497                  * as IXGBE_VF_MAXMSIVECOTR = 1
5498                  */
5499                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5500                 intr_handle->intr_vec[q_idx] = vector_idx;
5501         }
5502 }
5503
5504 /**
5505  * Sets up the hardware to properly generate MSI-X interrupts
5506  * @hw
5507  *  board private structure
5508  */
5509 static void
5510 ixgbe_configure_msix(struct rte_eth_dev *dev)
5511 {
5512         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5513         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5514         struct ixgbe_hw *hw =
5515                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5516         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5517         uint32_t vec = IXGBE_MISC_VEC_ID;
5518         uint32_t mask;
5519         uint32_t gpie;
5520
5521         /* won't configure msix register if no mapping is done
5522          * between intr vector and event fd
5523          */
5524         if (!rte_intr_dp_is_en(intr_handle))
5525                 return;
5526
5527         if (rte_intr_allow_others(intr_handle))
5528                 vec = base = IXGBE_RX_VEC_START;
5529
5530         /* setup GPIE for MSI-x mode */
5531         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5532         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5533                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5534         /* auto clearing and auto setting corresponding bits in EIMS
5535          * when MSI-X interrupt is triggered
5536          */
5537         if (hw->mac.type == ixgbe_mac_82598EB) {
5538                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5539         } else {
5540                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5541                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5542         }
5543         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5544
5545         /* Populate the IVAR table and set the ITR values to the
5546          * corresponding register.
5547          */
5548         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5549              queue_id++) {
5550                 /* by default, 1:1 mapping */
5551                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5552                 intr_handle->intr_vec[queue_id] = vec;
5553                 if (vec < base + intr_handle->nb_efd - 1)
5554                         vec++;
5555         }
5556
5557         switch (hw->mac.type) {
5558         case ixgbe_mac_82598EB:
5559                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5560                                    IXGBE_MISC_VEC_ID);
5561                 break;
5562         case ixgbe_mac_82599EB:
5563         case ixgbe_mac_X540:
5564                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5565                 break;
5566         default:
5567                 break;
5568         }
5569         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5570                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5571
5572         /* set up to autoclear timer, and the vectors */
5573         mask = IXGBE_EIMS_ENABLE_MASK;
5574         mask &= ~(IXGBE_EIMS_OTHER |
5575                   IXGBE_EIMS_MAILBOX |
5576                   IXGBE_EIMS_LSC);
5577
5578         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5579 }
5580
5581 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5582         uint16_t queue_idx, uint16_t tx_rate)
5583 {
5584         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5585         uint32_t rf_dec, rf_int;
5586         uint32_t bcnrc_val;
5587         uint16_t link_speed = dev->data->dev_link.link_speed;
5588
5589         if (queue_idx >= hw->mac.max_tx_queues)
5590                 return -EINVAL;
5591
5592         if (tx_rate != 0) {
5593                 /* Calculate the rate factor values to set */
5594                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5595                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5596                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5597
5598                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5599                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5600                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5601                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5602         } else {
5603                 bcnrc_val = 0;
5604         }
5605
5606         /*
5607          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5608          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5609          * set as 0x4.
5610          */
5611         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5612                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5613                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5614                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5615                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5616         else
5617                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5618                         IXGBE_MMW_SIZE_DEFAULT);
5619
5620         /* Set RTTBCNRC of queue X */
5621         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5622         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5623         IXGBE_WRITE_FLUSH(hw);
5624
5625         return 0;
5626 }
5627
5628 static void
5629 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5630                      __attribute__((unused)) uint32_t index,
5631                      __attribute__((unused)) uint32_t pool)
5632 {
5633         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5634         int diag;
5635
5636         /*
5637          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5638          * operation. Trap this case to avoid exhausting the [very limited]
5639          * set of PF resources used to store VF MAC addresses.
5640          */
5641         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5642                 return;
5643         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5644         if (diag == 0)
5645                 return;
5646         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5647 }
5648
5649 static void
5650 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5651 {
5652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5653         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5654         struct ether_addr *mac_addr;
5655         uint32_t i;
5656         int diag;
5657
5658         /*
5659          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5660          * not support the deletion of a given MAC address.
5661          * Instead, it imposes to delete all MAC addresses, then to add again
5662          * all MAC addresses with the exception of the one to be deleted.
5663          */
5664         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5665
5666         /*
5667          * Add again all MAC addresses, with the exception of the deleted one
5668          * and of the permanent MAC address.
5669          */
5670         for (i = 0, mac_addr = dev->data->mac_addrs;
5671              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5672                 /* Skip the deleted MAC address */
5673                 if (i == index)
5674                         continue;
5675                 /* Skip NULL MAC addresses */
5676                 if (is_zero_ether_addr(mac_addr))
5677                         continue;
5678                 /* Skip the permanent MAC address */
5679                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5680                         continue;
5681                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5682                 if (diag != 0)
5683                         PMD_DRV_LOG(ERR,
5684                                     "Adding again MAC address "
5685                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5686                                     "diag=%d",
5687                                     mac_addr->addr_bytes[0],
5688                                     mac_addr->addr_bytes[1],
5689                                     mac_addr->addr_bytes[2],
5690                                     mac_addr->addr_bytes[3],
5691                                     mac_addr->addr_bytes[4],
5692                                     mac_addr->addr_bytes[5],
5693                                     diag);
5694         }
5695 }
5696
5697 static void
5698 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5699 {
5700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5701
5702         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5703 }
5704
5705 int
5706 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5707                         struct rte_eth_syn_filter *filter,
5708                         bool add)
5709 {
5710         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5711         struct ixgbe_filter_info *filter_info =
5712                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5713         uint32_t syn_info;
5714         uint32_t synqf;
5715
5716         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5717                 return -EINVAL;
5718
5719         syn_info = filter_info->syn_info;
5720
5721         if (add) {
5722                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5723                         return -EINVAL;
5724                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5725                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5726
5727                 if (filter->hig_pri)
5728                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5729                 else
5730                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5731         } else {
5732                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5733                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5734                         return -ENOENT;
5735                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5736         }
5737
5738         filter_info->syn_info = synqf;
5739         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5740         IXGBE_WRITE_FLUSH(hw);
5741         return 0;
5742 }
5743
5744 static int
5745 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5746                         struct rte_eth_syn_filter *filter)
5747 {
5748         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5749         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5750
5751         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5752                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5753                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5754                 return 0;
5755         }
5756         return -ENOENT;
5757 }
5758
5759 static int
5760 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5761                         enum rte_filter_op filter_op,
5762                         void *arg)
5763 {
5764         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5765         int ret;
5766
5767         MAC_TYPE_FILTER_SUP(hw->mac.type);
5768
5769         if (filter_op == RTE_ETH_FILTER_NOP)
5770                 return 0;
5771
5772         if (arg == NULL) {
5773                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5774                             filter_op);
5775                 return -EINVAL;
5776         }
5777
5778         switch (filter_op) {
5779         case RTE_ETH_FILTER_ADD:
5780                 ret = ixgbe_syn_filter_set(dev,
5781                                 (struct rte_eth_syn_filter *)arg,
5782                                 TRUE);
5783                 break;
5784         case RTE_ETH_FILTER_DELETE:
5785                 ret = ixgbe_syn_filter_set(dev,
5786                                 (struct rte_eth_syn_filter *)arg,
5787                                 FALSE);
5788                 break;
5789         case RTE_ETH_FILTER_GET:
5790                 ret = ixgbe_syn_filter_get(dev,
5791                                 (struct rte_eth_syn_filter *)arg);
5792                 break;
5793         default:
5794                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5795                 ret = -EINVAL;
5796                 break;
5797         }
5798
5799         return ret;
5800 }
5801
5802
5803 static inline enum ixgbe_5tuple_protocol
5804 convert_protocol_type(uint8_t protocol_value)
5805 {
5806         if (protocol_value == IPPROTO_TCP)
5807                 return IXGBE_FILTER_PROTOCOL_TCP;
5808         else if (protocol_value == IPPROTO_UDP)
5809                 return IXGBE_FILTER_PROTOCOL_UDP;
5810         else if (protocol_value == IPPROTO_SCTP)
5811                 return IXGBE_FILTER_PROTOCOL_SCTP;
5812         else
5813                 return IXGBE_FILTER_PROTOCOL_NONE;
5814 }
5815
5816 /* inject a 5-tuple filter to HW */
5817 static inline void
5818 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5819                            struct ixgbe_5tuple_filter *filter)
5820 {
5821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5822         int i;
5823         uint32_t ftqf, sdpqf;
5824         uint32_t l34timir = 0;
5825         uint8_t mask = 0xff;
5826
5827         i = filter->index;
5828
5829         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5830                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5831         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5832
5833         ftqf = (uint32_t)(filter->filter_info.proto &
5834                 IXGBE_FTQF_PROTOCOL_MASK);
5835         ftqf |= (uint32_t)((filter->filter_info.priority &
5836                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5837         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5838                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5839         if (filter->filter_info.dst_ip_mask == 0)
5840                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5841         if (filter->filter_info.src_port_mask == 0)
5842                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5843         if (filter->filter_info.dst_port_mask == 0)
5844                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5845         if (filter->filter_info.proto_mask == 0)
5846                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5847         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5848         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5849         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5850
5851         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5852         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5853         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5854         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5855
5856         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5857         l34timir |= (uint32_t)(filter->queue <<
5858                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5859         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5860 }
5861
5862 /*
5863  * add a 5tuple filter
5864  *
5865  * @param
5866  * dev: Pointer to struct rte_eth_dev.
5867  * index: the index the filter allocates.
5868  * filter: ponter to the filter that will be added.
5869  * rx_queue: the queue id the filter assigned to.
5870  *
5871  * @return
5872  *    - On success, zero.
5873  *    - On failure, a negative value.
5874  */
5875 static int
5876 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5877                         struct ixgbe_5tuple_filter *filter)
5878 {
5879         struct ixgbe_filter_info *filter_info =
5880                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5881         int i, idx, shift;
5882
5883         /*
5884          * look for an unused 5tuple filter index,
5885          * and insert the filter to list.
5886          */
5887         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5888                 idx = i / (sizeof(uint32_t) * NBBY);
5889                 shift = i % (sizeof(uint32_t) * NBBY);
5890                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5891                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5892                         filter->index = i;
5893                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5894                                           filter,
5895                                           entries);
5896                         break;
5897                 }
5898         }
5899         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5900                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5901                 return -ENOSYS;
5902         }
5903
5904         ixgbe_inject_5tuple_filter(dev, filter);
5905
5906         return 0;
5907 }
5908
5909 /*
5910  * remove a 5tuple filter
5911  *
5912  * @param
5913  * dev: Pointer to struct rte_eth_dev.
5914  * filter: the pointer of the filter will be removed.
5915  */
5916 static void
5917 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5918                         struct ixgbe_5tuple_filter *filter)
5919 {
5920         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5921         struct ixgbe_filter_info *filter_info =
5922                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5923         uint16_t index = filter->index;
5924
5925         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5926                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5927         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5928         rte_free(filter);
5929
5930         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5931         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5932         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5933         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5934         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5935 }
5936
5937 static int
5938 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5939 {
5940         struct ixgbe_hw *hw;
5941         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5942
5943         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5944
5945         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5946                 return -EINVAL;
5947
5948         /* refuse mtu that requires the support of scattered packets when this
5949          * feature has not been enabled before.
5950          */
5951         if (!dev->data->scattered_rx &&
5952             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5953              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5954                 return -EINVAL;
5955
5956         /*
5957          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5958          * request of the version 2.0 of the mailbox API.
5959          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5960          * of the mailbox API.
5961          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5962          * prior to 3.11.33 which contains the following change:
5963          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5964          */
5965         ixgbevf_rlpml_set_vf(hw, max_frame);
5966
5967         /* update max frame size */
5968         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5969         return 0;
5970 }
5971
5972 static inline struct ixgbe_5tuple_filter *
5973 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5974                         struct ixgbe_5tuple_filter_info *key)
5975 {
5976         struct ixgbe_5tuple_filter *it;
5977
5978         TAILQ_FOREACH(it, filter_list, entries) {
5979                 if (memcmp(key, &it->filter_info,
5980                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5981                         return it;
5982                 }
5983         }
5984         return NULL;
5985 }
5986
5987 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5988 static inline int
5989 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5990                         struct ixgbe_5tuple_filter_info *filter_info)
5991 {
5992         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5993                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5994                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5995                 return -EINVAL;
5996
5997         switch (filter->dst_ip_mask) {
5998         case UINT32_MAX:
5999                 filter_info->dst_ip_mask = 0;
6000                 filter_info->dst_ip = filter->dst_ip;
6001                 break;
6002         case 0:
6003                 filter_info->dst_ip_mask = 1;
6004                 break;
6005         default:
6006                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6007                 return -EINVAL;
6008         }
6009
6010         switch (filter->src_ip_mask) {
6011         case UINT32_MAX:
6012                 filter_info->src_ip_mask = 0;
6013                 filter_info->src_ip = filter->src_ip;
6014                 break;
6015         case 0:
6016                 filter_info->src_ip_mask = 1;
6017                 break;
6018         default:
6019                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6020                 return -EINVAL;
6021         }
6022
6023         switch (filter->dst_port_mask) {
6024         case UINT16_MAX:
6025                 filter_info->dst_port_mask = 0;
6026                 filter_info->dst_port = filter->dst_port;
6027                 break;
6028         case 0:
6029                 filter_info->dst_port_mask = 1;
6030                 break;
6031         default:
6032                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6033                 return -EINVAL;
6034         }
6035
6036         switch (filter->src_port_mask) {
6037         case UINT16_MAX:
6038                 filter_info->src_port_mask = 0;
6039                 filter_info->src_port = filter->src_port;
6040                 break;
6041         case 0:
6042                 filter_info->src_port_mask = 1;
6043                 break;
6044         default:
6045                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6046                 return -EINVAL;
6047         }
6048
6049         switch (filter->proto_mask) {
6050         case UINT8_MAX:
6051                 filter_info->proto_mask = 0;
6052                 filter_info->proto =
6053                         convert_protocol_type(filter->proto);
6054                 break;
6055         case 0:
6056                 filter_info->proto_mask = 1;
6057                 break;
6058         default:
6059                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6060                 return -EINVAL;
6061         }
6062
6063         filter_info->priority = (uint8_t)filter->priority;
6064         return 0;
6065 }
6066
6067 /*
6068  * add or delete a ntuple filter
6069  *
6070  * @param
6071  * dev: Pointer to struct rte_eth_dev.
6072  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6073  * add: if true, add filter, if false, remove filter
6074  *
6075  * @return
6076  *    - On success, zero.
6077  *    - On failure, a negative value.
6078  */
6079 int
6080 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6081                         struct rte_eth_ntuple_filter *ntuple_filter,
6082                         bool add)
6083 {
6084         struct ixgbe_filter_info *filter_info =
6085                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6086         struct ixgbe_5tuple_filter_info filter_5tuple;
6087         struct ixgbe_5tuple_filter *filter;
6088         int ret;
6089
6090         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6091                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6092                 return -EINVAL;
6093         }
6094
6095         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6096         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6097         if (ret < 0)
6098                 return ret;
6099
6100         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6101                                          &filter_5tuple);
6102         if (filter != NULL && add) {
6103                 PMD_DRV_LOG(ERR, "filter exists.");
6104                 return -EEXIST;
6105         }
6106         if (filter == NULL && !add) {
6107                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6108                 return -ENOENT;
6109         }
6110
6111         if (add) {
6112                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6113                                 sizeof(struct ixgbe_5tuple_filter), 0);
6114                 if (filter == NULL)
6115                         return -ENOMEM;
6116                 (void)rte_memcpy(&filter->filter_info,
6117                                  &filter_5tuple,
6118                                  sizeof(struct ixgbe_5tuple_filter_info));
6119                 filter->queue = ntuple_filter->queue;
6120                 ret = ixgbe_add_5tuple_filter(dev, filter);
6121                 if (ret < 0) {
6122                         rte_free(filter);
6123                         return ret;
6124                 }
6125         } else
6126                 ixgbe_remove_5tuple_filter(dev, filter);
6127
6128         return 0;
6129 }
6130
6131 /*
6132  * get a ntuple filter
6133  *
6134  * @param
6135  * dev: Pointer to struct rte_eth_dev.
6136  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6137  *
6138  * @return
6139  *    - On success, zero.
6140  *    - On failure, a negative value.
6141  */
6142 static int
6143 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6144                         struct rte_eth_ntuple_filter *ntuple_filter)
6145 {
6146         struct ixgbe_filter_info *filter_info =
6147                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6148         struct ixgbe_5tuple_filter_info filter_5tuple;
6149         struct ixgbe_5tuple_filter *filter;
6150         int ret;
6151
6152         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6153                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6154                 return -EINVAL;
6155         }
6156
6157         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6158         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6159         if (ret < 0)
6160                 return ret;
6161
6162         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6163                                          &filter_5tuple);
6164         if (filter == NULL) {
6165                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6166                 return -ENOENT;
6167         }
6168         ntuple_filter->queue = filter->queue;
6169         return 0;
6170 }
6171
6172 /*
6173  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6174  * @dev: pointer to rte_eth_dev structure
6175  * @filter_op:operation will be taken.
6176  * @arg: a pointer to specific structure corresponding to the filter_op
6177  *
6178  * @return
6179  *    - On success, zero.
6180  *    - On failure, a negative value.
6181  */
6182 static int
6183 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6184                                 enum rte_filter_op filter_op,
6185                                 void *arg)
6186 {
6187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6188         int ret;
6189
6190         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6191
6192         if (filter_op == RTE_ETH_FILTER_NOP)
6193                 return 0;
6194
6195         if (arg == NULL) {
6196                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6197                             filter_op);
6198                 return -EINVAL;
6199         }
6200
6201         switch (filter_op) {
6202         case RTE_ETH_FILTER_ADD:
6203                 ret = ixgbe_add_del_ntuple_filter(dev,
6204                         (struct rte_eth_ntuple_filter *)arg,
6205                         TRUE);
6206                 break;
6207         case RTE_ETH_FILTER_DELETE:
6208                 ret = ixgbe_add_del_ntuple_filter(dev,
6209                         (struct rte_eth_ntuple_filter *)arg,
6210                         FALSE);
6211                 break;
6212         case RTE_ETH_FILTER_GET:
6213                 ret = ixgbe_get_ntuple_filter(dev,
6214                         (struct rte_eth_ntuple_filter *)arg);
6215                 break;
6216         default:
6217                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6218                 ret = -EINVAL;
6219                 break;
6220         }
6221         return ret;
6222 }
6223
6224 int
6225 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6226                         struct rte_eth_ethertype_filter *filter,
6227                         bool add)
6228 {
6229         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6230         struct ixgbe_filter_info *filter_info =
6231                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6232         uint32_t etqf = 0;
6233         uint32_t etqs = 0;
6234         int ret;
6235         struct ixgbe_ethertype_filter ethertype_filter;
6236
6237         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6238                 return -EINVAL;
6239
6240         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6241                 filter->ether_type == ETHER_TYPE_IPv6) {
6242                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6243                         " ethertype filter.", filter->ether_type);
6244                 return -EINVAL;
6245         }
6246
6247         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6248                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6249                 return -EINVAL;
6250         }
6251         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6252                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6253                 return -EINVAL;
6254         }
6255
6256         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6257         if (ret >= 0 && add) {
6258                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6259                             filter->ether_type);
6260                 return -EEXIST;
6261         }
6262         if (ret < 0 && !add) {
6263                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6264                             filter->ether_type);
6265                 return -ENOENT;
6266         }
6267
6268         if (add) {
6269                 etqf = IXGBE_ETQF_FILTER_EN;
6270                 etqf |= (uint32_t)filter->ether_type;
6271                 etqs |= (uint32_t)((filter->queue <<
6272                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6273                                     IXGBE_ETQS_RX_QUEUE);
6274                 etqs |= IXGBE_ETQS_QUEUE_EN;
6275
6276                 ethertype_filter.ethertype = filter->ether_type;
6277                 ethertype_filter.etqf = etqf;
6278                 ethertype_filter.etqs = etqs;
6279                 ethertype_filter.conf = FALSE;
6280                 ret = ixgbe_ethertype_filter_insert(filter_info,
6281                                                     &ethertype_filter);
6282                 if (ret < 0) {
6283                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6284                         return -ENOSPC;
6285                 }
6286         } else {
6287                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6288                 if (ret < 0)
6289                         return -ENOSYS;
6290         }
6291         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6292         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6293         IXGBE_WRITE_FLUSH(hw);
6294
6295         return 0;
6296 }
6297
6298 static int
6299 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6300                         struct rte_eth_ethertype_filter *filter)
6301 {
6302         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6303         struct ixgbe_filter_info *filter_info =
6304                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6305         uint32_t etqf, etqs;
6306         int ret;
6307
6308         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6309         if (ret < 0) {
6310                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6311                             filter->ether_type);
6312                 return -ENOENT;
6313         }
6314
6315         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6316         if (etqf & IXGBE_ETQF_FILTER_EN) {
6317                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6318                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6319                 filter->flags = 0;
6320                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6321                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6322                 return 0;
6323         }
6324         return -ENOENT;
6325 }
6326
6327 /*
6328  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6329  * @dev: pointer to rte_eth_dev structure
6330  * @filter_op:operation will be taken.
6331  * @arg: a pointer to specific structure corresponding to the filter_op
6332  */
6333 static int
6334 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6335                                 enum rte_filter_op filter_op,
6336                                 void *arg)
6337 {
6338         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6339         int ret;
6340
6341         MAC_TYPE_FILTER_SUP(hw->mac.type);
6342
6343         if (filter_op == RTE_ETH_FILTER_NOP)
6344                 return 0;
6345
6346         if (arg == NULL) {
6347                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6348                             filter_op);
6349                 return -EINVAL;
6350         }
6351
6352         switch (filter_op) {
6353         case RTE_ETH_FILTER_ADD:
6354                 ret = ixgbe_add_del_ethertype_filter(dev,
6355                         (struct rte_eth_ethertype_filter *)arg,
6356                         TRUE);
6357                 break;
6358         case RTE_ETH_FILTER_DELETE:
6359                 ret = ixgbe_add_del_ethertype_filter(dev,
6360                         (struct rte_eth_ethertype_filter *)arg,
6361                         FALSE);
6362                 break;
6363         case RTE_ETH_FILTER_GET:
6364                 ret = ixgbe_get_ethertype_filter(dev,
6365                         (struct rte_eth_ethertype_filter *)arg);
6366                 break;
6367         default:
6368                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6369                 ret = -EINVAL;
6370                 break;
6371         }
6372         return ret;
6373 }
6374
6375 static int
6376 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6377                      enum rte_filter_type filter_type,
6378                      enum rte_filter_op filter_op,
6379                      void *arg)
6380 {
6381         int ret = 0;
6382
6383         switch (filter_type) {
6384         case RTE_ETH_FILTER_NTUPLE:
6385                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6386                 break;
6387         case RTE_ETH_FILTER_ETHERTYPE:
6388                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6389                 break;
6390         case RTE_ETH_FILTER_SYN:
6391                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6392                 break;
6393         case RTE_ETH_FILTER_FDIR:
6394                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6395                 break;
6396         case RTE_ETH_FILTER_L2_TUNNEL:
6397                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6398                 break;
6399         case RTE_ETH_FILTER_GENERIC:
6400                 if (filter_op != RTE_ETH_FILTER_GET)
6401                         return -EINVAL;
6402                 *(const void **)arg = &ixgbe_flow_ops;
6403                 break;
6404         default:
6405                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6406                                                         filter_type);
6407                 ret = -EINVAL;
6408                 break;
6409         }
6410
6411         return ret;
6412 }
6413
6414 static u8 *
6415 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6416                         u8 **mc_addr_ptr, u32 *vmdq)
6417 {
6418         u8 *mc_addr;
6419
6420         *vmdq = 0;
6421         mc_addr = *mc_addr_ptr;
6422         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6423         return mc_addr;
6424 }
6425
6426 static int
6427 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6428                           struct ether_addr *mc_addr_set,
6429                           uint32_t nb_mc_addr)
6430 {
6431         struct ixgbe_hw *hw;
6432         u8 *mc_addr_list;
6433
6434         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6435         mc_addr_list = (u8 *)mc_addr_set;
6436         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6437                                          ixgbe_dev_addr_list_itr, TRUE);
6438 }
6439
6440 static uint64_t
6441 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6442 {
6443         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6444         uint64_t systime_cycles;
6445
6446         switch (hw->mac.type) {
6447         case ixgbe_mac_X550:
6448         case ixgbe_mac_X550EM_x:
6449         case ixgbe_mac_X550EM_a:
6450                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6451                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6452                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6453                                 * NSEC_PER_SEC;
6454                 break;
6455         default:
6456                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6457                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6458                                 << 32;
6459         }
6460
6461         return systime_cycles;
6462 }
6463
6464 static uint64_t
6465 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6466 {
6467         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6468         uint64_t rx_tstamp_cycles;
6469
6470         switch (hw->mac.type) {
6471         case ixgbe_mac_X550:
6472         case ixgbe_mac_X550EM_x:
6473         case ixgbe_mac_X550EM_a:
6474                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6475                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6476                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6477                                 * NSEC_PER_SEC;
6478                 break;
6479         default:
6480                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6481                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6482                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6483                                 << 32;
6484         }
6485
6486         return rx_tstamp_cycles;
6487 }
6488
6489 static uint64_t
6490 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6491 {
6492         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6493         uint64_t tx_tstamp_cycles;
6494
6495         switch (hw->mac.type) {
6496         case ixgbe_mac_X550:
6497         case ixgbe_mac_X550EM_x:
6498         case ixgbe_mac_X550EM_a:
6499                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6500                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6501                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6502                                 * NSEC_PER_SEC;
6503                 break;
6504         default:
6505                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6506                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6507                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6508                                 << 32;
6509         }
6510
6511         return tx_tstamp_cycles;
6512 }
6513
6514 static void
6515 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6516 {
6517         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6518         struct ixgbe_adapter *adapter =
6519                 (struct ixgbe_adapter *)dev->data->dev_private;
6520         struct rte_eth_link link;
6521         uint32_t incval = 0;
6522         uint32_t shift = 0;
6523
6524         /* Get current link speed. */
6525         memset(&link, 0, sizeof(link));
6526         ixgbe_dev_link_update(dev, 1);
6527         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6528
6529         switch (link.link_speed) {
6530         case ETH_SPEED_NUM_100M:
6531                 incval = IXGBE_INCVAL_100;
6532                 shift = IXGBE_INCVAL_SHIFT_100;
6533                 break;
6534         case ETH_SPEED_NUM_1G:
6535                 incval = IXGBE_INCVAL_1GB;
6536                 shift = IXGBE_INCVAL_SHIFT_1GB;
6537                 break;
6538         case ETH_SPEED_NUM_10G:
6539         default:
6540                 incval = IXGBE_INCVAL_10GB;
6541                 shift = IXGBE_INCVAL_SHIFT_10GB;
6542                 break;
6543         }
6544
6545         switch (hw->mac.type) {
6546         case ixgbe_mac_X550:
6547         case ixgbe_mac_X550EM_x:
6548         case ixgbe_mac_X550EM_a:
6549                 /* Independent of link speed. */
6550                 incval = 1;
6551                 /* Cycles read will be interpreted as ns. */
6552                 shift = 0;
6553                 /* Fall-through */
6554         case ixgbe_mac_X540:
6555                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6556                 break;
6557         case ixgbe_mac_82599EB:
6558                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6559                 shift -= IXGBE_INCVAL_SHIFT_82599;
6560                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6561                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6562                 break;
6563         default:
6564                 /* Not supported. */
6565                 return;
6566         }
6567
6568         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6569         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6570         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6571
6572         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6573         adapter->systime_tc.cc_shift = shift;
6574         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6575
6576         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6577         adapter->rx_tstamp_tc.cc_shift = shift;
6578         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6579
6580         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6581         adapter->tx_tstamp_tc.cc_shift = shift;
6582         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6583 }
6584
6585 static int
6586 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6587 {
6588         struct ixgbe_adapter *adapter =
6589                         (struct ixgbe_adapter *)dev->data->dev_private;
6590
6591         adapter->systime_tc.nsec += delta;
6592         adapter->rx_tstamp_tc.nsec += delta;
6593         adapter->tx_tstamp_tc.nsec += delta;
6594
6595         return 0;
6596 }
6597
6598 static int
6599 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6600 {
6601         uint64_t ns;
6602         struct ixgbe_adapter *adapter =
6603                         (struct ixgbe_adapter *)dev->data->dev_private;
6604
6605         ns = rte_timespec_to_ns(ts);
6606         /* Set the timecounters to a new value. */
6607         adapter->systime_tc.nsec = ns;
6608         adapter->rx_tstamp_tc.nsec = ns;
6609         adapter->tx_tstamp_tc.nsec = ns;
6610
6611         return 0;
6612 }
6613
6614 static int
6615 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6616 {
6617         uint64_t ns, systime_cycles;
6618         struct ixgbe_adapter *adapter =
6619                         (struct ixgbe_adapter *)dev->data->dev_private;
6620
6621         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6622         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6623         *ts = rte_ns_to_timespec(ns);
6624
6625         return 0;
6626 }
6627
6628 static int
6629 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6630 {
6631         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6632         uint32_t tsync_ctl;
6633         uint32_t tsauxc;
6634
6635         /* Stop the timesync system time. */
6636         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6637         /* Reset the timesync system time value. */
6638         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6639         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6640
6641         /* Enable system time for platforms where it isn't on by default. */
6642         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6643         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6644         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6645
6646         ixgbe_start_timecounters(dev);
6647
6648         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6649         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6650                         (ETHER_TYPE_1588 |
6651                          IXGBE_ETQF_FILTER_EN |
6652                          IXGBE_ETQF_1588));
6653
6654         /* Enable timestamping of received PTP packets. */
6655         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6656         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6657         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6658
6659         /* Enable timestamping of transmitted PTP packets. */
6660         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6661         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6662         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6663
6664         IXGBE_WRITE_FLUSH(hw);
6665
6666         return 0;
6667 }
6668
6669 static int
6670 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6671 {
6672         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6673         uint32_t tsync_ctl;
6674
6675         /* Disable timestamping of transmitted PTP packets. */
6676         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6677         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6678         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6679
6680         /* Disable timestamping of received PTP packets. */
6681         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6682         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6683         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6684
6685         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6686         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6687
6688         /* Stop incrementating the System Time registers. */
6689         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6690
6691         return 0;
6692 }
6693
6694 static int
6695 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6696                                  struct timespec *timestamp,
6697                                  uint32_t flags __rte_unused)
6698 {
6699         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6700         struct ixgbe_adapter *adapter =
6701                 (struct ixgbe_adapter *)dev->data->dev_private;
6702         uint32_t tsync_rxctl;
6703         uint64_t rx_tstamp_cycles;
6704         uint64_t ns;
6705
6706         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6707         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6708                 return -EINVAL;
6709
6710         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6711         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6712         *timestamp = rte_ns_to_timespec(ns);
6713
6714         return  0;
6715 }
6716
6717 static int
6718 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6719                                  struct timespec *timestamp)
6720 {
6721         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6722         struct ixgbe_adapter *adapter =
6723                 (struct ixgbe_adapter *)dev->data->dev_private;
6724         uint32_t tsync_txctl;
6725         uint64_t tx_tstamp_cycles;
6726         uint64_t ns;
6727
6728         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6729         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6730                 return -EINVAL;
6731
6732         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6733         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6734         *timestamp = rte_ns_to_timespec(ns);
6735
6736         return 0;
6737 }
6738
6739 static int
6740 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6741 {
6742         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6743         int count = 0;
6744         int g_ind = 0;
6745         const struct reg_info *reg_group;
6746         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6747                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6748
6749         while ((reg_group = reg_set[g_ind++]))
6750                 count += ixgbe_regs_group_count(reg_group);
6751
6752         return count;
6753 }
6754
6755 static int
6756 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6757 {
6758         int count = 0;
6759         int g_ind = 0;
6760         const struct reg_info *reg_group;
6761
6762         while ((reg_group = ixgbevf_regs[g_ind++]))
6763                 count += ixgbe_regs_group_count(reg_group);
6764
6765         return count;
6766 }
6767
6768 static int
6769 ixgbe_get_regs(struct rte_eth_dev *dev,
6770               struct rte_dev_reg_info *regs)
6771 {
6772         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6773         uint32_t *data = regs->data;
6774         int g_ind = 0;
6775         int count = 0;
6776         const struct reg_info *reg_group;
6777         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6778                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6779
6780         if (data == NULL) {
6781                 regs->length = ixgbe_get_reg_length(dev);
6782                 regs->width = sizeof(uint32_t);
6783                 return 0;
6784         }
6785
6786         /* Support only full register dump */
6787         if ((regs->length == 0) ||
6788             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6789                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6790                         hw->device_id;
6791                 while ((reg_group = reg_set[g_ind++]))
6792                         count += ixgbe_read_regs_group(dev, &data[count],
6793                                 reg_group);
6794                 return 0;
6795         }
6796
6797         return -ENOTSUP;
6798 }
6799
6800 static int
6801 ixgbevf_get_regs(struct rte_eth_dev *dev,
6802                 struct rte_dev_reg_info *regs)
6803 {
6804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6805         uint32_t *data = regs->data;
6806         int g_ind = 0;
6807         int count = 0;
6808         const struct reg_info *reg_group;
6809
6810         if (data == NULL) {
6811                 regs->length = ixgbevf_get_reg_length(dev);
6812                 regs->width = sizeof(uint32_t);
6813                 return 0;
6814         }
6815
6816         /* Support only full register dump */
6817         if ((regs->length == 0) ||
6818             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6819                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6820                         hw->device_id;
6821                 while ((reg_group = ixgbevf_regs[g_ind++]))
6822                         count += ixgbe_read_regs_group(dev, &data[count],
6823                                                       reg_group);
6824                 return 0;
6825         }
6826
6827         return -ENOTSUP;
6828 }
6829
6830 static int
6831 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6832 {
6833         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6834
6835         /* Return unit is byte count */
6836         return hw->eeprom.word_size * 2;
6837 }
6838
6839 static int
6840 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6841                 struct rte_dev_eeprom_info *in_eeprom)
6842 {
6843         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6844         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6845         uint16_t *data = in_eeprom->data;
6846         int first, length;
6847
6848         first = in_eeprom->offset >> 1;
6849         length = in_eeprom->length >> 1;
6850         if ((first > hw->eeprom.word_size) ||
6851             ((first + length) > hw->eeprom.word_size))
6852                 return -EINVAL;
6853
6854         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6855
6856         return eeprom->ops.read_buffer(hw, first, length, data);
6857 }
6858
6859 static int
6860 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6861                 struct rte_dev_eeprom_info *in_eeprom)
6862 {
6863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6864         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6865         uint16_t *data = in_eeprom->data;
6866         int first, length;
6867
6868         first = in_eeprom->offset >> 1;
6869         length = in_eeprom->length >> 1;
6870         if ((first > hw->eeprom.word_size) ||
6871             ((first + length) > hw->eeprom.word_size))
6872                 return -EINVAL;
6873
6874         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6875
6876         return eeprom->ops.write_buffer(hw,  first, length, data);
6877 }
6878
6879 uint16_t
6880 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6881         switch (mac_type) {
6882         case ixgbe_mac_X550:
6883         case ixgbe_mac_X550EM_x:
6884         case ixgbe_mac_X550EM_a:
6885                 return ETH_RSS_RETA_SIZE_512;
6886         case ixgbe_mac_X550_vf:
6887         case ixgbe_mac_X550EM_x_vf:
6888         case ixgbe_mac_X550EM_a_vf:
6889                 return ETH_RSS_RETA_SIZE_64;
6890         default:
6891                 return ETH_RSS_RETA_SIZE_128;
6892         }
6893 }
6894
6895 uint32_t
6896 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6897         switch (mac_type) {
6898         case ixgbe_mac_X550:
6899         case ixgbe_mac_X550EM_x:
6900         case ixgbe_mac_X550EM_a:
6901                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6902                         return IXGBE_RETA(reta_idx >> 2);
6903                 else
6904                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6905         case ixgbe_mac_X550_vf:
6906         case ixgbe_mac_X550EM_x_vf:
6907         case ixgbe_mac_X550EM_a_vf:
6908                 return IXGBE_VFRETA(reta_idx >> 2);
6909         default:
6910                 return IXGBE_RETA(reta_idx >> 2);
6911         }
6912 }
6913
6914 uint32_t
6915 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6916         switch (mac_type) {
6917         case ixgbe_mac_X550_vf:
6918         case ixgbe_mac_X550EM_x_vf:
6919         case ixgbe_mac_X550EM_a_vf:
6920                 return IXGBE_VFMRQC;
6921         default:
6922                 return IXGBE_MRQC;
6923         }
6924 }
6925
6926 uint32_t
6927 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6928         switch (mac_type) {
6929         case ixgbe_mac_X550_vf:
6930         case ixgbe_mac_X550EM_x_vf:
6931         case ixgbe_mac_X550EM_a_vf:
6932                 return IXGBE_VFRSSRK(i);
6933         default:
6934                 return IXGBE_RSSRK(i);
6935         }
6936 }
6937
6938 bool
6939 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6940         switch (mac_type) {
6941         case ixgbe_mac_82599_vf:
6942         case ixgbe_mac_X540_vf:
6943                 return 0;
6944         default:
6945                 return 1;
6946         }
6947 }
6948
6949 static int
6950 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6951                         struct rte_eth_dcb_info *dcb_info)
6952 {
6953         struct ixgbe_dcb_config *dcb_config =
6954                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6955         struct ixgbe_dcb_tc_config *tc;
6956         uint8_t i, j;
6957
6958         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6959                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6960         else
6961                 dcb_info->nb_tcs = 1;
6962
6963         if (dcb_config->vt_mode) { /* vt is enabled*/
6964                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6965                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6966                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6967                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6968                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6969                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6970                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6971                                                 i * dcb_info->nb_tcs + j;
6972                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6973                                 dcb_info->tc_queue.tc_txq[i][j].base =
6974                                                 i * dcb_info->nb_tcs + j;
6975                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6976                         }
6977                 }
6978         } else { /* vt is disabled*/
6979                 struct rte_eth_dcb_rx_conf *rx_conf =
6980                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6981                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6982                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6983                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6984                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6985                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6986                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6987                         }
6988                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6989                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6990                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6991                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6992                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6993                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6994                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6995                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6996                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6997                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6998                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6999                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7000                         }
7001                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7002                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7003                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7004                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7005                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7006                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7007                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7008                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7009                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7010                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7011                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7012                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7013                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7014                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7015                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7016                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7017                 }
7018         }
7019         for (i = 0; i < dcb_info->nb_tcs; i++) {
7020                 tc = &dcb_config->tc_config[i];
7021                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7022         }
7023         return 0;
7024 }
7025
7026 /* Update e-tag ether type */
7027 static int
7028 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7029                             uint16_t ether_type)
7030 {
7031         uint32_t etag_etype;
7032
7033         if (hw->mac.type != ixgbe_mac_X550 &&
7034             hw->mac.type != ixgbe_mac_X550EM_x &&
7035             hw->mac.type != ixgbe_mac_X550EM_a) {
7036                 return -ENOTSUP;
7037         }
7038
7039         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7040         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7041         etag_etype |= ether_type;
7042         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7043         IXGBE_WRITE_FLUSH(hw);
7044
7045         return 0;
7046 }
7047
7048 /* Config l2 tunnel ether type */
7049 static int
7050 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7051                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7052 {
7053         int ret = 0;
7054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7055         struct ixgbe_l2_tn_info *l2_tn_info =
7056                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7057
7058         if (l2_tunnel == NULL)
7059                 return -EINVAL;
7060
7061         switch (l2_tunnel->l2_tunnel_type) {
7062         case RTE_L2_TUNNEL_TYPE_E_TAG:
7063                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7064                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7065                 break;
7066         default:
7067                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7068                 ret = -EINVAL;
7069                 break;
7070         }
7071
7072         return ret;
7073 }
7074
7075 /* Enable e-tag tunnel */
7076 static int
7077 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7078 {
7079         uint32_t etag_etype;
7080
7081         if (hw->mac.type != ixgbe_mac_X550 &&
7082             hw->mac.type != ixgbe_mac_X550EM_x &&
7083             hw->mac.type != ixgbe_mac_X550EM_a) {
7084                 return -ENOTSUP;
7085         }
7086
7087         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7088         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7089         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7090         IXGBE_WRITE_FLUSH(hw);
7091
7092         return 0;
7093 }
7094
7095 /* Enable l2 tunnel */
7096 static int
7097 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7098                            enum rte_eth_tunnel_type l2_tunnel_type)
7099 {
7100         int ret = 0;
7101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7102         struct ixgbe_l2_tn_info *l2_tn_info =
7103                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7104
7105         switch (l2_tunnel_type) {
7106         case RTE_L2_TUNNEL_TYPE_E_TAG:
7107                 l2_tn_info->e_tag_en = TRUE;
7108                 ret = ixgbe_e_tag_enable(hw);
7109                 break;
7110         default:
7111                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7112                 ret = -EINVAL;
7113                 break;
7114         }
7115
7116         return ret;
7117 }
7118
7119 /* Disable e-tag tunnel */
7120 static int
7121 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7122 {
7123         uint32_t etag_etype;
7124
7125         if (hw->mac.type != ixgbe_mac_X550 &&
7126             hw->mac.type != ixgbe_mac_X550EM_x &&
7127             hw->mac.type != ixgbe_mac_X550EM_a) {
7128                 return -ENOTSUP;
7129         }
7130
7131         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7132         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7133         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7134         IXGBE_WRITE_FLUSH(hw);
7135
7136         return 0;
7137 }
7138
7139 /* Disable l2 tunnel */
7140 static int
7141 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7142                             enum rte_eth_tunnel_type l2_tunnel_type)
7143 {
7144         int ret = 0;
7145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7146         struct ixgbe_l2_tn_info *l2_tn_info =
7147                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7148
7149         switch (l2_tunnel_type) {
7150         case RTE_L2_TUNNEL_TYPE_E_TAG:
7151                 l2_tn_info->e_tag_en = FALSE;
7152                 ret = ixgbe_e_tag_disable(hw);
7153                 break;
7154         default:
7155                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7156                 ret = -EINVAL;
7157                 break;
7158         }
7159
7160         return ret;
7161 }
7162
7163 static int
7164 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7165                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7166 {
7167         int ret = 0;
7168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7169         uint32_t i, rar_entries;
7170         uint32_t rar_low, rar_high;
7171
7172         if (hw->mac.type != ixgbe_mac_X550 &&
7173             hw->mac.type != ixgbe_mac_X550EM_x &&
7174             hw->mac.type != ixgbe_mac_X550EM_a) {
7175                 return -ENOTSUP;
7176         }
7177
7178         rar_entries = ixgbe_get_num_rx_addrs(hw);
7179
7180         for (i = 1; i < rar_entries; i++) {
7181                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7182                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7183                 if ((rar_high & IXGBE_RAH_AV) &&
7184                     (rar_high & IXGBE_RAH_ADTYPE) &&
7185                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7186                      l2_tunnel->tunnel_id)) {
7187                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7188                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7189
7190                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7191
7192                         return ret;
7193                 }
7194         }
7195
7196         return ret;
7197 }
7198
7199 static int
7200 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7201                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7202 {
7203         int ret = 0;
7204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7205         uint32_t i, rar_entries;
7206         uint32_t rar_low, rar_high;
7207
7208         if (hw->mac.type != ixgbe_mac_X550 &&
7209             hw->mac.type != ixgbe_mac_X550EM_x &&
7210             hw->mac.type != ixgbe_mac_X550EM_a) {
7211                 return -ENOTSUP;
7212         }
7213
7214         /* One entry for one tunnel. Try to remove potential existing entry. */
7215         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7216
7217         rar_entries = ixgbe_get_num_rx_addrs(hw);
7218
7219         for (i = 1; i < rar_entries; i++) {
7220                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7221                 if (rar_high & IXGBE_RAH_AV) {
7222                         continue;
7223                 } else {
7224                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7225                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7226                         rar_low = l2_tunnel->tunnel_id;
7227
7228                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7229                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7230
7231                         return ret;
7232                 }
7233         }
7234
7235         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7236                      " Please remove a rule before adding a new one.");
7237         return -EINVAL;
7238 }
7239
7240 static inline struct ixgbe_l2_tn_filter *
7241 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7242                           struct ixgbe_l2_tn_key *key)
7243 {
7244         int ret;
7245
7246         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7247         if (ret < 0)
7248                 return NULL;
7249
7250         return l2_tn_info->hash_map[ret];
7251 }
7252
7253 static inline int
7254 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7255                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7256 {
7257         int ret;
7258
7259         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7260                                &l2_tn_filter->key);
7261
7262         if (ret < 0) {
7263                 PMD_DRV_LOG(ERR,
7264                             "Failed to insert L2 tunnel filter"
7265                             " to hash table %d!",
7266                             ret);
7267                 return ret;
7268         }
7269
7270         l2_tn_info->hash_map[ret] = l2_tn_filter;
7271
7272         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7273
7274         return 0;
7275 }
7276
7277 static inline int
7278 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7279                           struct ixgbe_l2_tn_key *key)
7280 {
7281         int ret;
7282         struct ixgbe_l2_tn_filter *l2_tn_filter;
7283
7284         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7285
7286         if (ret < 0) {
7287                 PMD_DRV_LOG(ERR,
7288                             "No such L2 tunnel filter to delete %d!",
7289                             ret);
7290                 return ret;
7291         }
7292
7293         l2_tn_filter = l2_tn_info->hash_map[ret];
7294         l2_tn_info->hash_map[ret] = NULL;
7295
7296         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7297         rte_free(l2_tn_filter);
7298
7299         return 0;
7300 }
7301
7302 /* Add l2 tunnel filter */
7303 int
7304 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7305                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7306                                bool restore)
7307 {
7308         int ret;
7309         struct ixgbe_l2_tn_info *l2_tn_info =
7310                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7311         struct ixgbe_l2_tn_key key;
7312         struct ixgbe_l2_tn_filter *node;
7313
7314         if (!restore) {
7315                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7316                 key.tn_id = l2_tunnel->tunnel_id;
7317
7318                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7319
7320                 if (node) {
7321                         PMD_DRV_LOG(ERR,
7322                                     "The L2 tunnel filter already exists!");
7323                         return -EINVAL;
7324                 }
7325
7326                 node = rte_zmalloc("ixgbe_l2_tn",
7327                                    sizeof(struct ixgbe_l2_tn_filter),
7328                                    0);
7329                 if (!node)
7330                         return -ENOMEM;
7331
7332                 (void)rte_memcpy(&node->key,
7333                                  &key,
7334                                  sizeof(struct ixgbe_l2_tn_key));
7335                 node->pool = l2_tunnel->pool;
7336                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7337                 if (ret < 0) {
7338                         rte_free(node);
7339                         return ret;
7340                 }
7341         }
7342
7343         switch (l2_tunnel->l2_tunnel_type) {
7344         case RTE_L2_TUNNEL_TYPE_E_TAG:
7345                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7346                 break;
7347         default:
7348                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7349                 ret = -EINVAL;
7350                 break;
7351         }
7352
7353         if ((!restore) && (ret < 0))
7354                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7355
7356         return ret;
7357 }
7358
7359 /* Delete l2 tunnel filter */
7360 int
7361 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7362                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7363 {
7364         int ret;
7365         struct ixgbe_l2_tn_info *l2_tn_info =
7366                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7367         struct ixgbe_l2_tn_key key;
7368
7369         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7370         key.tn_id = l2_tunnel->tunnel_id;
7371         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7372         if (ret < 0)
7373                 return ret;
7374
7375         switch (l2_tunnel->l2_tunnel_type) {
7376         case RTE_L2_TUNNEL_TYPE_E_TAG:
7377                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7378                 break;
7379         default:
7380                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7381                 ret = -EINVAL;
7382                 break;
7383         }
7384
7385         return ret;
7386 }
7387
7388 /**
7389  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7390  * @dev: pointer to rte_eth_dev structure
7391  * @filter_op:operation will be taken.
7392  * @arg: a pointer to specific structure corresponding to the filter_op
7393  */
7394 static int
7395 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7396                                   enum rte_filter_op filter_op,
7397                                   void *arg)
7398 {
7399         int ret;
7400
7401         if (filter_op == RTE_ETH_FILTER_NOP)
7402                 return 0;
7403
7404         if (arg == NULL) {
7405                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7406                             filter_op);
7407                 return -EINVAL;
7408         }
7409
7410         switch (filter_op) {
7411         case RTE_ETH_FILTER_ADD:
7412                 ret = ixgbe_dev_l2_tunnel_filter_add
7413                         (dev,
7414                          (struct rte_eth_l2_tunnel_conf *)arg,
7415                          FALSE);
7416                 break;
7417         case RTE_ETH_FILTER_DELETE:
7418                 ret = ixgbe_dev_l2_tunnel_filter_del
7419                         (dev,
7420                          (struct rte_eth_l2_tunnel_conf *)arg);
7421                 break;
7422         default:
7423                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7424                 ret = -EINVAL;
7425                 break;
7426         }
7427         return ret;
7428 }
7429
7430 static int
7431 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7432 {
7433         int ret = 0;
7434         uint32_t ctrl;
7435         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7436
7437         if (hw->mac.type != ixgbe_mac_X550 &&
7438             hw->mac.type != ixgbe_mac_X550EM_x &&
7439             hw->mac.type != ixgbe_mac_X550EM_a) {
7440                 return -ENOTSUP;
7441         }
7442
7443         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7444         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7445         if (en)
7446                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7447         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7448
7449         return ret;
7450 }
7451
7452 /* Enable l2 tunnel forwarding */
7453 static int
7454 ixgbe_dev_l2_tunnel_forwarding_enable
7455         (struct rte_eth_dev *dev,
7456          enum rte_eth_tunnel_type l2_tunnel_type)
7457 {
7458         struct ixgbe_l2_tn_info *l2_tn_info =
7459                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7460         int ret = 0;
7461
7462         switch (l2_tunnel_type) {
7463         case RTE_L2_TUNNEL_TYPE_E_TAG:
7464                 l2_tn_info->e_tag_fwd_en = TRUE;
7465                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7466                 break;
7467         default:
7468                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7469                 ret = -EINVAL;
7470                 break;
7471         }
7472
7473         return ret;
7474 }
7475
7476 /* Disable l2 tunnel forwarding */
7477 static int
7478 ixgbe_dev_l2_tunnel_forwarding_disable
7479         (struct rte_eth_dev *dev,
7480          enum rte_eth_tunnel_type l2_tunnel_type)
7481 {
7482         struct ixgbe_l2_tn_info *l2_tn_info =
7483                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7484         int ret = 0;
7485
7486         switch (l2_tunnel_type) {
7487         case RTE_L2_TUNNEL_TYPE_E_TAG:
7488                 l2_tn_info->e_tag_fwd_en = FALSE;
7489                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7490                 break;
7491         default:
7492                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7493                 ret = -EINVAL;
7494                 break;
7495         }
7496
7497         return ret;
7498 }
7499
7500 static int
7501 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7502                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7503                              bool en)
7504 {
7505         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7506         int ret = 0;
7507         uint32_t vmtir, vmvir;
7508         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7509
7510         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7511                 PMD_DRV_LOG(ERR,
7512                             "VF id %u should be less than %u",
7513                             l2_tunnel->vf_id,
7514                             pci_dev->max_vfs);
7515                 return -EINVAL;
7516         }
7517
7518         if (hw->mac.type != ixgbe_mac_X550 &&
7519             hw->mac.type != ixgbe_mac_X550EM_x &&
7520             hw->mac.type != ixgbe_mac_X550EM_a) {
7521                 return -ENOTSUP;
7522         }
7523
7524         if (en)
7525                 vmtir = l2_tunnel->tunnel_id;
7526         else
7527                 vmtir = 0;
7528
7529         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7530
7531         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7532         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7533         if (en)
7534                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7535         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7536
7537         return ret;
7538 }
7539
7540 /* Enable l2 tunnel tag insertion */
7541 static int
7542 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7543                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7544 {
7545         int ret = 0;
7546
7547         switch (l2_tunnel->l2_tunnel_type) {
7548         case RTE_L2_TUNNEL_TYPE_E_TAG:
7549                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7550                 break;
7551         default:
7552                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7553                 ret = -EINVAL;
7554                 break;
7555         }
7556
7557         return ret;
7558 }
7559
7560 /* Disable l2 tunnel tag insertion */
7561 static int
7562 ixgbe_dev_l2_tunnel_insertion_disable
7563         (struct rte_eth_dev *dev,
7564          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7565 {
7566         int ret = 0;
7567
7568         switch (l2_tunnel->l2_tunnel_type) {
7569         case RTE_L2_TUNNEL_TYPE_E_TAG:
7570                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7571                 break;
7572         default:
7573                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7574                 ret = -EINVAL;
7575                 break;
7576         }
7577
7578         return ret;
7579 }
7580
7581 static int
7582 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7583                              bool en)
7584 {
7585         int ret = 0;
7586         uint32_t qde;
7587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7588
7589         if (hw->mac.type != ixgbe_mac_X550 &&
7590             hw->mac.type != ixgbe_mac_X550EM_x &&
7591             hw->mac.type != ixgbe_mac_X550EM_a) {
7592                 return -ENOTSUP;
7593         }
7594
7595         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7596         if (en)
7597                 qde |= IXGBE_QDE_STRIP_TAG;
7598         else
7599                 qde &= ~IXGBE_QDE_STRIP_TAG;
7600         qde &= ~IXGBE_QDE_READ;
7601         qde |= IXGBE_QDE_WRITE;
7602         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7603
7604         return ret;
7605 }
7606
7607 /* Enable l2 tunnel tag stripping */
7608 static int
7609 ixgbe_dev_l2_tunnel_stripping_enable
7610         (struct rte_eth_dev *dev,
7611          enum rte_eth_tunnel_type l2_tunnel_type)
7612 {
7613         int ret = 0;
7614
7615         switch (l2_tunnel_type) {
7616         case RTE_L2_TUNNEL_TYPE_E_TAG:
7617                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7618                 break;
7619         default:
7620                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7621                 ret = -EINVAL;
7622                 break;
7623         }
7624
7625         return ret;
7626 }
7627
7628 /* Disable l2 tunnel tag stripping */
7629 static int
7630 ixgbe_dev_l2_tunnel_stripping_disable
7631         (struct rte_eth_dev *dev,
7632          enum rte_eth_tunnel_type l2_tunnel_type)
7633 {
7634         int ret = 0;
7635
7636         switch (l2_tunnel_type) {
7637         case RTE_L2_TUNNEL_TYPE_E_TAG:
7638                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7639                 break;
7640         default:
7641                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7642                 ret = -EINVAL;
7643                 break;
7644         }
7645
7646         return ret;
7647 }
7648
7649 /* Enable/disable l2 tunnel offload functions */
7650 static int
7651 ixgbe_dev_l2_tunnel_offload_set
7652         (struct rte_eth_dev *dev,
7653          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7654          uint32_t mask,
7655          uint8_t en)
7656 {
7657         int ret = 0;
7658
7659         if (l2_tunnel == NULL)
7660                 return -EINVAL;
7661
7662         ret = -EINVAL;
7663         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7664                 if (en)
7665                         ret = ixgbe_dev_l2_tunnel_enable(
7666                                 dev,
7667                                 l2_tunnel->l2_tunnel_type);
7668                 else
7669                         ret = ixgbe_dev_l2_tunnel_disable(
7670                                 dev,
7671                                 l2_tunnel->l2_tunnel_type);
7672         }
7673
7674         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7675                 if (en)
7676                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7677                                 dev,
7678                                 l2_tunnel);
7679                 else
7680                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7681                                 dev,
7682                                 l2_tunnel);
7683         }
7684
7685         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7686                 if (en)
7687                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7688                                 dev,
7689                                 l2_tunnel->l2_tunnel_type);
7690                 else
7691                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7692                                 dev,
7693                                 l2_tunnel->l2_tunnel_type);
7694         }
7695
7696         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7697                 if (en)
7698                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7699                                 dev,
7700                                 l2_tunnel->l2_tunnel_type);
7701                 else
7702                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7703                                 dev,
7704                                 l2_tunnel->l2_tunnel_type);
7705         }
7706
7707         return ret;
7708 }
7709
7710 static int
7711 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7712                         uint16_t port)
7713 {
7714         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7715         IXGBE_WRITE_FLUSH(hw);
7716
7717         return 0;
7718 }
7719
7720 /* There's only one register for VxLAN UDP port.
7721  * So, we cannot add several ports. Will update it.
7722  */
7723 static int
7724 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7725                      uint16_t port)
7726 {
7727         if (port == 0) {
7728                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7729                 return -EINVAL;
7730         }
7731
7732         return ixgbe_update_vxlan_port(hw, port);
7733 }
7734
7735 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7736  * UDP port, it must have a value.
7737  * So, will reset it to the original value 0.
7738  */
7739 static int
7740 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7741                      uint16_t port)
7742 {
7743         uint16_t cur_port;
7744
7745         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7746
7747         if (cur_port != port) {
7748                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7749                 return -EINVAL;
7750         }
7751
7752         return ixgbe_update_vxlan_port(hw, 0);
7753 }
7754
7755 /* Add UDP tunneling port */
7756 static int
7757 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7758                               struct rte_eth_udp_tunnel *udp_tunnel)
7759 {
7760         int ret = 0;
7761         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7762
7763         if (hw->mac.type != ixgbe_mac_X550 &&
7764             hw->mac.type != ixgbe_mac_X550EM_x &&
7765             hw->mac.type != ixgbe_mac_X550EM_a) {
7766                 return -ENOTSUP;
7767         }
7768
7769         if (udp_tunnel == NULL)
7770                 return -EINVAL;
7771
7772         switch (udp_tunnel->prot_type) {
7773         case RTE_TUNNEL_TYPE_VXLAN:
7774                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7775                 break;
7776
7777         case RTE_TUNNEL_TYPE_GENEVE:
7778         case RTE_TUNNEL_TYPE_TEREDO:
7779                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7780                 ret = -EINVAL;
7781                 break;
7782
7783         default:
7784                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7785                 ret = -EINVAL;
7786                 break;
7787         }
7788
7789         return ret;
7790 }
7791
7792 /* Remove UDP tunneling port */
7793 static int
7794 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7795                               struct rte_eth_udp_tunnel *udp_tunnel)
7796 {
7797         int ret = 0;
7798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7799
7800         if (hw->mac.type != ixgbe_mac_X550 &&
7801             hw->mac.type != ixgbe_mac_X550EM_x &&
7802             hw->mac.type != ixgbe_mac_X550EM_a) {
7803                 return -ENOTSUP;
7804         }
7805
7806         if (udp_tunnel == NULL)
7807                 return -EINVAL;
7808
7809         switch (udp_tunnel->prot_type) {
7810         case RTE_TUNNEL_TYPE_VXLAN:
7811                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7812                 break;
7813         case RTE_TUNNEL_TYPE_GENEVE:
7814         case RTE_TUNNEL_TYPE_TEREDO:
7815                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7816                 ret = -EINVAL;
7817                 break;
7818         default:
7819                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7820                 ret = -EINVAL;
7821                 break;
7822         }
7823
7824         return ret;
7825 }
7826
7827 static void
7828 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7829 {
7830         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7831
7832         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7833 }
7834
7835 static void
7836 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7837 {
7838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7839
7840         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7841 }
7842
7843 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7844 {
7845         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7846         u32 in_msg = 0;
7847
7848         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7849                 return;
7850
7851         /* PF reset VF event */
7852         if (in_msg == IXGBE_PF_CONTROL_MSG)
7853                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7854 }
7855
7856 static int
7857 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7858 {
7859         uint32_t eicr;
7860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7861         struct ixgbe_interrupt *intr =
7862                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7863         ixgbevf_intr_disable(hw);
7864
7865         /* read-on-clear nic registers here */
7866         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7867         intr->flags = 0;
7868
7869         /* only one misc vector supported - mailbox */
7870         eicr &= IXGBE_VTEICR_MASK;
7871         if (eicr == IXGBE_MISC_VEC_ID)
7872                 intr->flags |= IXGBE_FLAG_MAILBOX;
7873
7874         return 0;
7875 }
7876
7877 static int
7878 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7879 {
7880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7881         struct ixgbe_interrupt *intr =
7882                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7883
7884         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7885                 ixgbevf_mbx_process(dev);
7886                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7887         }
7888
7889         ixgbevf_intr_enable(hw);
7890
7891         return 0;
7892 }
7893
7894 static void
7895 ixgbevf_dev_interrupt_handler(void *param)
7896 {
7897         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7898
7899         ixgbevf_dev_interrupt_get_status(dev);
7900         ixgbevf_dev_interrupt_action(dev);
7901 }
7902
7903 /**
7904  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7905  *  @hw: pointer to hardware structure
7906  *
7907  *  Stops the transmit data path and waits for the HW to internally empty
7908  *  the Tx security block
7909  **/
7910 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7911 {
7912 #define IXGBE_MAX_SECTX_POLL 40
7913
7914         int i;
7915         int sectxreg;
7916
7917         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7918         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7919         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7920         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7921                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7922                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7923                         break;
7924                 /* Use interrupt-safe sleep just in case */
7925                 usec_delay(1000);
7926         }
7927
7928         /* For informational purposes only */
7929         if (i >= IXGBE_MAX_SECTX_POLL)
7930                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7931                          "path fully disabled.  Continuing with init.");
7932
7933         return IXGBE_SUCCESS;
7934 }
7935
7936 /**
7937  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7938  *  @hw: pointer to hardware structure
7939  *
7940  *  Enables the transmit data path.
7941  **/
7942 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7943 {
7944         uint32_t sectxreg;
7945
7946         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7947         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7948         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7949         IXGBE_WRITE_FLUSH(hw);
7950
7951         return IXGBE_SUCCESS;
7952 }
7953
7954 /* restore n-tuple filter */
7955 static inline void
7956 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7957 {
7958         struct ixgbe_filter_info *filter_info =
7959                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7960         struct ixgbe_5tuple_filter *node;
7961
7962         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
7963                 ixgbe_inject_5tuple_filter(dev, node);
7964         }
7965 }
7966
7967 /* restore ethernet type filter */
7968 static inline void
7969 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
7970 {
7971         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7972         struct ixgbe_filter_info *filter_info =
7973                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7974         int i;
7975
7976         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
7977                 if (filter_info->ethertype_mask & (1 << i)) {
7978                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
7979                                         filter_info->ethertype_filters[i].etqf);
7980                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
7981                                         filter_info->ethertype_filters[i].etqs);
7982                         IXGBE_WRITE_FLUSH(hw);
7983                 }
7984         }
7985 }
7986
7987 /* restore SYN filter */
7988 static inline void
7989 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
7990 {
7991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7992         struct ixgbe_filter_info *filter_info =
7993                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7994         uint32_t synqf;
7995
7996         synqf = filter_info->syn_info;
7997
7998         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
7999                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8000                 IXGBE_WRITE_FLUSH(hw);
8001         }
8002 }
8003
8004 /* restore L2 tunnel filter */
8005 static inline void
8006 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8007 {
8008         struct ixgbe_l2_tn_info *l2_tn_info =
8009                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8010         struct ixgbe_l2_tn_filter *node;
8011         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8012
8013         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8014                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8015                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8016                 l2_tn_conf.pool           = node->pool;
8017                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8018         }
8019 }
8020
8021 static int
8022 ixgbe_filter_restore(struct rte_eth_dev *dev)
8023 {
8024         ixgbe_ntuple_filter_restore(dev);
8025         ixgbe_ethertype_filter_restore(dev);
8026         ixgbe_syn_filter_restore(dev);
8027         ixgbe_fdir_filter_restore(dev);
8028         ixgbe_l2_tn_filter_restore(dev);
8029
8030         return 0;
8031 }
8032
8033 static void
8034 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8035 {
8036         struct ixgbe_l2_tn_info *l2_tn_info =
8037                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8039
8040         if (l2_tn_info->e_tag_en)
8041                 (void)ixgbe_e_tag_enable(hw);
8042
8043         if (l2_tn_info->e_tag_fwd_en)
8044                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8045
8046         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8047 }
8048
8049 /* remove all the n-tuple filters */
8050 void
8051 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8052 {
8053         struct ixgbe_filter_info *filter_info =
8054                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8055         struct ixgbe_5tuple_filter *p_5tuple;
8056
8057         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8058                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8059 }
8060
8061 /* remove all the ether type filters */
8062 void
8063 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8064 {
8065         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8066         struct ixgbe_filter_info *filter_info =
8067                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8068         int i;
8069
8070         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8071                 if (filter_info->ethertype_mask & (1 << i) &&
8072                     !filter_info->ethertype_filters[i].conf) {
8073                         (void)ixgbe_ethertype_filter_remove(filter_info,
8074                                                             (uint8_t)i);
8075                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8076                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8077                         IXGBE_WRITE_FLUSH(hw);
8078                 }
8079         }
8080 }
8081
8082 /* remove the SYN filter */
8083 void
8084 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8085 {
8086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8087         struct ixgbe_filter_info *filter_info =
8088                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8089
8090         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8091                 filter_info->syn_info = 0;
8092
8093                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8094                 IXGBE_WRITE_FLUSH(hw);
8095         }
8096 }
8097
8098 /* remove all the L2 tunnel filters */
8099 int
8100 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8101 {
8102         struct ixgbe_l2_tn_info *l2_tn_info =
8103                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8104         struct ixgbe_l2_tn_filter *l2_tn_filter;
8105         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8106         int ret = 0;
8107
8108         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8109                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8110                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8111                 l2_tn_conf.pool           = l2_tn_filter->pool;
8112                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8113                 if (ret < 0)
8114                         return ret;
8115         }
8116
8117         return 0;
8118 }
8119
8120 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8121 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8122 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8123 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8124 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8125 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");