drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 /* Additional timesync values. */
 104 #define NSEC_PER_SEC             1000000000L
 105 #define IXGBE_INCVAL_10GB        0x66666666
 106 #define IXGBE_INCVAL_1GB         0x40000000
 107 #define IXGBE_INCVAL_100         0x50000000
 108 #define IXGBE_INCVAL_SHIFT_10GB  28
 109 #define IXGBE_INCVAL_SHIFT_1GB   24
 110 #define IXGBE_INCVAL_SHIFT_100   21
 111 #define IXGBE_INCVAL_SHIFT_82599 7
 112 #define IXGBE_INCPER_SHIFT_82599 24
 113
 114 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 117 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 118 #define IXGBE_ETAG_ETYPE                       0x00005084
 119 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 120 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 121 #define IXGBE_RAH_ADTYPE                       0x40000000
 122 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 123 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 124 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 125 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 126 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 127 #define IXGBE_VTEICR_MASK                      0x07
 128
 129 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 130 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 131
 132 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 133 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 151                                 int wait_to_complete);
 152 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 153                                 struct rte_eth_stats *stats);
 154 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 155                                 struct rte_eth_xstat *xstats, unsigned n);
 156 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 157                                   struct rte_eth_xstat *xstats, unsigned n);
 158 static int
 159 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 160                 uint64_t *values, unsigned int n);
 161 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 163 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names,
 165         unsigned int size);
 166 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 168 static int ixgbe_dev_xstats_get_names_by_id(
 169         struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         const uint64_t *ids,
 172         unsigned int limit);
 173 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 174                                              uint16_t queue_id,
 175                                              uint8_t stat_idx,
 176                                              uint8_t is_rx);
 177 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 178                                  size_t fw_size);
 179 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 180                                struct rte_eth_dev_info *dev_info);
 181 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 182 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 183                                  struct rte_eth_dev_info *dev_info);
 184 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 185
 186 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 187                 uint16_t vlan_id, int on);
 188 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 189                                enum rte_vlan_type vlan_type,
 190                                uint16_t tpid_id);
 191 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 192                 uint16_t queue, bool on);
 193 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 194                 int on);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 221                                       struct rte_intr_handle *handle);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 225                          uint32_t index, uint32_t pool);
 226 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 227 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 228                                            struct ether_addr *mac_addr);
 229 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 230 static bool is_device_supported(struct rte_eth_dev *dev,
 231                                 struct rte_pci_driver *drv);
 232
 233 /* For Virtual Function support */
 234 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 235 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 236 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 237 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 238 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 239                                    int wait_to_complete);
 240 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 242 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 245 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 255                                             uint16_t queue_id);
 256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 257                                              uint16_t queue_id);
 258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 259                                  uint8_t queue, uint8_t msix_vector);
 260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 263
 264 /* For Eth VMDQ APIs support */
 265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 266                 ether_addr * mac_addr, uint8_t on);
 267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 268 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 269                 struct rte_eth_mirror_conf *mirror_conf,
 270                 uint8_t rule_id, uint8_t on);
 271 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 272                 uint8_t rule_id);
 273 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 274                                           uint16_t queue_id);
 275 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 276                                            uint16_t queue_id);
 277 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 278                                uint8_t queue, uint8_t msix_vector);
 279 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 280
 281 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 282                                 struct ether_addr *mac_addr,
 283                                 uint32_t index, uint32_t pool);
 284 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 285 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 286                                              struct ether_addr *mac_addr);
 287 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 288                         struct rte_eth_syn_filter *filter);
 289 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 290                         enum rte_filter_op filter_op,
 291                         void *arg);
 292 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 293                         struct ixgbe_5tuple_filter *filter);
 294 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 295                         struct ixgbe_5tuple_filter *filter);
 296 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 297                                 enum rte_filter_op filter_op,
 298                                 void *arg);
 299 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 300                         struct rte_eth_ntuple_filter *filter);
 301 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 302                                 enum rte_filter_op filter_op,
 303                                 void *arg);
 304 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 305                         struct rte_eth_ethertype_filter *filter);
 306 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 307                      enum rte_filter_type filter_type,
 308                      enum rte_filter_op filter_op,
 309                      void *arg);
 310 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 311
 312 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 313                                       struct ether_addr *mc_addr_set,
 314                                       uint32_t nb_mc_addr);
 315 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 316                                    struct rte_eth_dcb_info *dcb_info);
 317
 318 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 319 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 320                             struct rte_dev_reg_info *regs);
 321 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 323                                 struct rte_dev_eeprom_info *eeprom);
 324 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 325                                 struct rte_dev_eeprom_info *eeprom);
 326
 327 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 328                                  struct rte_eth_dev_module_info *modinfo);
 329 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 330                                    struct rte_dev_eeprom_info *info);
 331
 332 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 334                                 struct rte_dev_reg_info *regs);
 335
 336 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 339                                             struct timespec *timestamp,
 340                                             uint32_t flags);
 341 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 342                                             struct timespec *timestamp);
 343 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 344 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 345                                    struct timespec *timestamp);
 346 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 347                                    const struct timespec *timestamp);
 348 static void ixgbevf_dev_interrupt_handler(void *param);
 349
 350 static int ixgbe_dev_l2_tunnel_eth_type_conf
 351         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 352 static int ixgbe_dev_l2_tunnel_offload_set
 353         (struct rte_eth_dev *dev,
 354          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 355          uint32_t mask,
 356          uint8_t en);
 357 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 358                                              enum rte_filter_op filter_op,
 359                                              void *arg);
 360
 361 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 364                                          struct rte_eth_udp_tunnel *udp_tunnel);
 365 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 366 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 367
 368 /*
 369  * Define VF Stats MACRO for Non "cleared on read" register
 370  */
 371 #define UPDATE_VF_STAT(reg, last, cur)                          \
 372 {                                                               \
 373         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 374         cur += (latest - last) & UINT_MAX;                      \
 375         last = latest;                                          \
 376 }
 377
 378 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 379 {                                                                \
 380         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 381         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 382         u64 latest = ((new_msb << 32) | new_lsb);                \
 383         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 384         last = latest;                                           \
 385 }
 386
 387 #define IXGBE_SET_HWSTRIP(h, q) do {\
 388                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 389                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 390                 (h)->bitmap[idx] |= 1 << bit;\
 391         } while (0)
 392
 393 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 394                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 395                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 396                 (h)->bitmap[idx] &= ~(1 << bit);\
 397         } while (0)
 398
 399 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 400                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 402                 (r) = (h)->bitmap[idx] >> bit & 1;\
 403         } while (0)
 404
 405 int ixgbe_logtype_init;
 406 int ixgbe_logtype_driver;
 407
 408 /*
 409  * The set of PCI devices this driver supports
 410  */
 411 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 460 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 462 #endif
 463         { .vendor_id = 0, /* sentinel */ },
 464 };
 465
 466 /*
 467  * The set of PCI devices this driver supports (for 82599 VF)
 468  */
 469 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 480         { .vendor_id = 0, /* sentinel */ },
 481 };
 482
 483 static const struct rte_eth_desc_lim rx_desc_lim = {
 484         .nb_max = IXGBE_MAX_RING_DESC,
 485         .nb_min = IXGBE_MIN_RING_DESC,
 486         .nb_align = IXGBE_RXD_ALIGN,
 487 };
 488
 489 static const struct rte_eth_desc_lim tx_desc_lim = {
 490         .nb_max = IXGBE_MAX_RING_DESC,
 491         .nb_min = IXGBE_MIN_RING_DESC,
 492         .nb_align = IXGBE_TXD_ALIGN,
 493         .nb_seg_max = IXGBE_TX_MAX_SEG,
 494         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 495 };
 496
 497 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 498         .dev_configure        = ixgbe_dev_configure,
 499         .dev_start            = ixgbe_dev_start,
 500         .dev_stop             = ixgbe_dev_stop,
 501         .dev_set_link_up    = ixgbe_dev_set_link_up,
 502         .dev_set_link_down  = ixgbe_dev_set_link_down,
 503         .dev_close            = ixgbe_dev_close,
 504         .dev_reset            = ixgbe_dev_reset,
 505         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 506         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 507         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 508         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 509         .link_update          = ixgbe_dev_link_update,
 510         .stats_get            = ixgbe_dev_stats_get,
 511         .xstats_get           = ixgbe_dev_xstats_get,
 512         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 513         .stats_reset          = ixgbe_dev_stats_reset,
 514         .xstats_reset         = ixgbe_dev_xstats_reset,
 515         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 516         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 517         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 518         .fw_version_get       = ixgbe_fw_version_get,
 519         .dev_infos_get        = ixgbe_dev_info_get,
 520         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 521         .mtu_set              = ixgbe_dev_mtu_set,
 522         .vlan_filter_set      = ixgbe_vlan_filter_set,
 523         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 524         .vlan_offload_set     = ixgbe_vlan_offload_set,
 525         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 526         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 527         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 528         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 529         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 530         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 531         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 532         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 533         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 534         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 535         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 536         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 537         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 538         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 539         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 540         .dev_led_on           = ixgbe_dev_led_on,
 541         .dev_led_off          = ixgbe_dev_led_off,
 542         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 543         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 544         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 545         .mac_addr_add         = ixgbe_add_rar,
 546         .mac_addr_remove      = ixgbe_remove_rar,
 547         .mac_addr_set         = ixgbe_set_default_mac_addr,
 548         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 549         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 550         .mirror_rule_set      = ixgbe_mirror_rule_set,
 551         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 552         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 553         .reta_update          = ixgbe_dev_rss_reta_update,
 554         .reta_query           = ixgbe_dev_rss_reta_query,
 555         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 556         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 557         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 558         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 559         .rxq_info_get         = ixgbe_rxq_info_get,
 560         .txq_info_get         = ixgbe_txq_info_get,
 561         .timesync_enable      = ixgbe_timesync_enable,
 562         .timesync_disable     = ixgbe_timesync_disable,
 563         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 564         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 565         .get_reg              = ixgbe_get_regs,
 566         .get_eeprom_length    = ixgbe_get_eeprom_length,
 567         .get_eeprom           = ixgbe_get_eeprom,
 568         .set_eeprom           = ixgbe_set_eeprom,
 569         .get_module_info      = ixgbe_get_module_info,
 570         .get_module_eeprom    = ixgbe_get_module_eeprom,
 571         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 572         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 573         .timesync_read_time   = ixgbe_timesync_read_time,
 574         .timesync_write_time  = ixgbe_timesync_write_time,
 575         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 576         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 577         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 578         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 579         .tm_ops_get           = ixgbe_tm_ops_get,
 580 };
 581
 582 /*
 583  * dev_ops for virtual function, bare necessities for basic vf
 584  * operation have been implemented
 585  */
 586 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 587         .dev_configure        = ixgbevf_dev_configure,
 588         .dev_start            = ixgbevf_dev_start,
 589         .dev_stop             = ixgbevf_dev_stop,
 590         .link_update          = ixgbevf_dev_link_update,
 591         .stats_get            = ixgbevf_dev_stats_get,
 592         .xstats_get           = ixgbevf_dev_xstats_get,
 593         .stats_reset          = ixgbevf_dev_stats_reset,
 594         .xstats_reset         = ixgbevf_dev_stats_reset,
 595         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 596         .dev_close            = ixgbevf_dev_close,
 597         .dev_reset            = ixgbevf_dev_reset,
 598         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 599         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 600         .dev_infos_get        = ixgbevf_dev_info_get,
 601         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 602         .mtu_set              = ixgbevf_dev_set_mtu,
 603         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 604         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 605         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 606         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 607         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 608         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 609         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 610         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 611         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 612         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 613         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 614         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 615         .mac_addr_add         = ixgbevf_add_mac_addr,
 616         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 617         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 618         .rxq_info_get         = ixgbe_rxq_info_get,
 619         .txq_info_get         = ixgbe_txq_info_get,
 620         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 621         .get_reg              = ixgbevf_get_regs,
 622         .reta_update          = ixgbe_dev_rss_reta_update,
 623         .reta_query           = ixgbe_dev_rss_reta_query,
 624         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 625         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 626 };
 627
 628 /* store statistics names and its offset in stats structure */
 629 struct rte_ixgbe_xstats_name_off {
 630         char name[RTE_ETH_XSTATS_NAME_SIZE];
 631         unsigned offset;
 632 };
 633
 634 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 635         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 636         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 637         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 638         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 639         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 640         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 641         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 642         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 643         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 644         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 645         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 646         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 647         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 648         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 649         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 650                 prc1023)},
 651         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 652                 prc1522)},
 653         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 654         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 655         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 656         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 657         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 658         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 659         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 660         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 661         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 662         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 663         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 664         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 665         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 666         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 667         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 668         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 669         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 670                 ptc1023)},
 671         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 672                 ptc1522)},
 673         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 674         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 675         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 676         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 677
 678         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 679                 fdirustat_add)},
 680         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 681                 fdirustat_remove)},
 682         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 683                 fdirfstat_fadd)},
 684         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 685                 fdirfstat_fremove)},
 686         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 687                 fdirmatch)},
 688         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 689                 fdirmiss)},
 690
 691         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 692         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 693         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 694                 fclast)},
 695         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 696         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 697         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 698         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 699         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 700                 fcoe_noddp)},
 701         {"rx_fcoe_no_direct_data_placement_ext_buff",
 702                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 703
 704         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxontxc)},
 706         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxonrxc)},
 708         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 709                 lxofftxc)},
 710         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 711                 lxoffrxc)},
 712         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 713 };
 714
 715 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 716                            sizeof(rte_ixgbe_stats_strings[0]))
 717
 718 /* MACsec statistics */
 719 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 720         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_untagged)},
 722         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_pkts_encrypted)},
 724         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_pkts_protected)},
 726         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 727                 out_octets_encrypted)},
 728         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 729                 out_octets_protected)},
 730         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_untagged)},
 732         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_badtag)},
 734         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 735                 in_pkts_nosci)},
 736         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_unknownsci)},
 738         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 739                 in_octets_decrypted)},
 740         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 741                 in_octets_validated)},
 742         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_unchecked)},
 744         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_delayed)},
 746         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_late)},
 748         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_ok)},
 750         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_invalid)},
 752         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notvalid)},
 754         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_unusedsa)},
 756         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_notusingsa)},
 758 };
 759
 760 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 761                            sizeof(rte_ixgbe_macsec_strings[0]))
 762
 763 /* Per-queue statistics */
 764 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 765         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 766         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 767         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 768         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 769 };
 770
 771 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 772                            sizeof(rte_ixgbe_rxq_strings[0]))
 773 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 774
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 776         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 777         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 778         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 779                 pxon2offc)},
 780 };
 781
 782 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 783                            sizeof(rte_ixgbe_txq_strings[0]))
 784 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 785
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 787         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 788 };
 789
 790 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 791                 sizeof(rte_ixgbevf_stats_strings[0]))
 792
 793 /*
 794  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 795  */
 796 static inline int
 797 ixgbe_is_sfp(struct ixgbe_hw *hw)
 798 {
 799         switch (hw->phy.type) {
 800         case ixgbe_phy_sfp_avago:
 801         case ixgbe_phy_sfp_ftl:
 802         case ixgbe_phy_sfp_intel:
 803         case ixgbe_phy_sfp_unknown:
 804         case ixgbe_phy_sfp_passive_tyco:
 805         case ixgbe_phy_sfp_passive_unknown:
 806                 return 1;
 807         default:
 808                 return 0;
 809         }
 810 }
 811
 812 static inline int32_t
 813 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 814 {
 815         uint32_t ctrl_ext;
 816         int32_t status;
 817
 818         status = ixgbe_reset_hw(hw);
 819
 820         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 821         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 822         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 823         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 824         IXGBE_WRITE_FLUSH(hw);
 825
 826         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 827                 status = IXGBE_SUCCESS;
 828         return status;
 829 }
 830
 831 static inline void
 832 ixgbe_enable_intr(struct rte_eth_dev *dev)
 833 {
 834         struct ixgbe_interrupt *intr =
 835                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 836         struct ixgbe_hw *hw =
 837                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 838
 839         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 840         IXGBE_WRITE_FLUSH(hw);
 841 }
 842
 843 /*
 844  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 845  */
 846 static void
 847 ixgbe_disable_intr(struct ixgbe_hw *hw)
 848 {
 849         PMD_INIT_FUNC_TRACE();
 850
 851         if (hw->mac.type == ixgbe_mac_82598EB) {
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 853         } else {
 854                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 857         }
 858         IXGBE_WRITE_FLUSH(hw);
 859 }
 860
 861 /*
 862  * This function resets queue statistics mapping registers.
 863  * From Niantic datasheet, Initialization of Statistics section:
 864  * "...if software requires the queue counters, the RQSMR and TQSM registers
 865  * must be re-programmed following a device reset.
 866  */
 867 static void
 868 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 869 {
 870         uint32_t i;
 871
 872         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 873                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 874                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 875         }
 876 }
 877
 878
 879 static int
 880 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 881                                   uint16_t queue_id,
 882                                   uint8_t stat_idx,
 883                                   uint8_t is_rx)
 884 {
 885 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 886 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 887 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 888
 889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 890         struct ixgbe_stat_mapping_registers *stat_mappings =
 891                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 892         uint32_t qsmr_mask = 0;
 893         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 894         uint32_t q_map;
 895         uint8_t n, offset;
 896
 897         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 898                 (hw->mac.type != ixgbe_mac_X540) &&
 899                 (hw->mac.type != ixgbe_mac_X550) &&
 900                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_a))
 902                 return -ENOSYS;
 903
 904         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 905                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 906                      queue_id, stat_idx);
 907
 908         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 909         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 910                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 911                 return -EIO;
 912         }
 913         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 914
 915         /* Now clear any previous stat_idx set */
 916         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 917         if (!is_rx)
 918                 stat_mappings->tqsm[n] &= ~clearing_mask;
 919         else
 920                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 921
 922         q_map = (uint32_t)stat_idx;
 923         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 924         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 925         if (!is_rx)
 926                 stat_mappings->tqsm[n] |= qsmr_mask;
 927         else
 928                 stat_mappings->rqsmr[n] |= qsmr_mask;
 929
 930         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 931                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 932                      queue_id, stat_idx);
 933         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 934                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 935
 936         /* Now write the mapping in the appropriate register */
 937         if (is_rx) {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 939                              stat_mappings->rqsmr[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 941         } else {
 942                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 943                              stat_mappings->tqsm[n], n);
 944                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 945         }
 946         return 0;
 947 }
 948
 949 static void
 950 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 951 {
 952         struct ixgbe_stat_mapping_registers *stat_mappings =
 953                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 955         int i;
 956
 957         /* write whatever was in stat mapping table to the NIC */
 958         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 959                 /* rx */
 960                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 961
 962                 /* tx */
 963                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 964         }
 965 }
 966
 967 static void
 968 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 969 {
 970         uint8_t i;
 971         struct ixgbe_dcb_tc_config *tc;
 972         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 973
 974         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 975         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 976         for (i = 0; i < dcb_max_tc; i++) {
 977                 tc = &dcb_config->tc_config[i];
 978                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 980                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 981                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 983                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 984                 tc->pfc = ixgbe_dcb_pfc_disabled;
 985         }
 986
 987         /* Initialize default user to priority mapping, UPx->TC0 */
 988         tc = &dcb_config->tc_config[0];
 989         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 990         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 992                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 993                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 994         }
 995         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 996         dcb_config->pfc_mode_enable = false;
 997         dcb_config->vt_mode = true;
 998         dcb_config->round_robin_enable = false;
 999         /* support all DCB capabilities in 82599 */
1000         dcb_config->support.capabilities = 0xFF;
1001
1002         /*we only support 4 Tcs for X540, X550 */
1003         if (hw->mac.type == ixgbe_mac_X540 ||
1004                 hw->mac.type == ixgbe_mac_X550 ||
1005                 hw->mac.type == ixgbe_mac_X550EM_x ||
1006                 hw->mac.type == ixgbe_mac_X550EM_a) {
1007                 dcb_config->num_tcs.pg_tcs = 4;
1008                 dcb_config->num_tcs.pfc_tcs = 4;
1009         }
1010 }
1011
1012 /*
1013  * Ensure that all locks are released before first NVM or PHY access
1014  */
1015 static void
1016 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1017 {
1018         uint16_t mask;
1019
1020         /*
1021          * Phy lock should not fail in this early stage. If this is the case,
1022          * it is due to an improper exit of the application.
1023          * So force the release of the faulty lock. Release of common lock
1024          * is done automatically by swfw_sync function.
1025          */
1026         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1027         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1028                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1029         }
1030         ixgbe_release_swfw_semaphore(hw, mask);
1031
1032         /*
1033          * These ones are more tricky since they are common to all ports; but
1034          * swfw_sync retries last long enough (1s) to be almost sure that if
1035          * lock can not be taken it is due to an improper lock of the
1036          * semaphore.
1037          */
1038         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1039         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1040                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1041         }
1042         ixgbe_release_swfw_semaphore(hw, mask);
1043 }
1044
1045 /*
1046  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1047  * It returns 0 on success.
1048  */
1049 static int
1050 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1051 {
1052         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1053         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1054         struct ixgbe_hw *hw =
1055                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1056         struct ixgbe_vfta *shadow_vfta =
1057                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1058         struct ixgbe_hwstrip *hwstrip =
1059                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1060         struct ixgbe_dcb_config *dcb_config =
1061                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1062         struct ixgbe_filter_info *filter_info =
1063                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1064         struct ixgbe_bw_conf *bw_conf =
1065                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1066         uint32_t ctrl_ext;
1067         uint16_t csum;
1068         int diag, i;
1069
1070         PMD_INIT_FUNC_TRACE();
1071
1072         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1073         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1074         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1075         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1076
1077         /*
1078          * For secondary processes, we don't initialise any further as primary
1079          * has already done this work. Only check we don't need a different
1080          * RX and TX function.
1081          */
1082         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1083                 struct ixgbe_tx_queue *txq;
1084                 /* TX queue function in primary, set by last queue initialized
1085                  * Tx queue may not initialized by primary process
1086                  */
1087                 if (eth_dev->data->tx_queues) {
1088                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1089                         ixgbe_set_tx_function(eth_dev, txq);
1090                 } else {
1091                         /* Use default TX function if we get here */
1092                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1093                                      "Using default TX function.");
1094                 }
1095
1096                 ixgbe_set_rx_function(eth_dev);
1097
1098                 return 0;
1099         }
1100
1101         rte_eth_copy_pci_info(eth_dev, pci_dev);
1102
1103         /* Vendor and Device ID need to be set before init of shared code */
1104         hw->device_id = pci_dev->id.device_id;
1105         hw->vendor_id = pci_dev->id.vendor_id;
1106         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1107         hw->allow_unsupported_sfp = 1;
1108
1109         /* Initialize the shared code (base driver) */
1110 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1111         diag = ixgbe_bypass_init_shared_code(hw);
1112 #else
1113         diag = ixgbe_init_shared_code(hw);
1114 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1115
1116         if (diag != IXGBE_SUCCESS) {
1117                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1118                 return -EIO;
1119         }
1120
1121         /* pick up the PCI bus settings for reporting later */
1122         ixgbe_get_bus_info(hw);
1123
1124         /* Unlock any pending hardware semaphore */
1125         ixgbe_swfw_lock_reset(hw);
1126
1127 #ifdef RTE_LIBRTE_SECURITY
1128         /* Initialize security_ctx only for primary process*/
1129         if (ixgbe_ipsec_ctx_create(eth_dev))
1130                 return -ENOMEM;
1131 #endif
1132
1133         /* Initialize DCB configuration*/
1134         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1135         ixgbe_dcb_init(hw, dcb_config);
1136         /* Get Hardware Flow Control setting */
1137         hw->fc.requested_mode = ixgbe_fc_full;
1138         hw->fc.current_mode = ixgbe_fc_full;
1139         hw->fc.pause_time = IXGBE_FC_PAUSE;
1140         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1141                 hw->fc.low_water[i] = IXGBE_FC_LO;
1142                 hw->fc.high_water[i] = IXGBE_FC_HI;
1143         }
1144         hw->fc.send_xon = 1;
1145
1146         /* Make sure we have a good EEPROM before we read from it */
1147         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1150                 return -EIO;
1151         }
1152
1153 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1154         diag = ixgbe_bypass_init_hw(hw);
1155 #else
1156         diag = ixgbe_init_hw(hw);
1157 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1158
1159         /*
1160          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1161          * is called too soon after the kernel driver unbinding/binding occurs.
1162          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1163          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1164          * also called. See ixgbe_identify_phy_82599(). The reason for the
1165          * failure is not known, and only occuts when virtualisation features
1166          * are disabled in the bios. A delay of 100ms  was found to be enough by
1167          * trial-and-error, and is doubled to be safe.
1168          */
1169         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1170                 rte_delay_ms(200);
1171                 diag = ixgbe_init_hw(hw);
1172         }
1173
1174         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1175                 diag = IXGBE_SUCCESS;
1176
1177         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1178                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1179                              "LOM.  Please be aware there may be issues associated "
1180                              "with your hardware.");
1181                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1182                              "please contact your Intel or hardware representative "
1183                              "who provided you with this hardware.");
1184         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1185                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1186         if (diag) {
1187                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1188                 return -EIO;
1189         }
1190
1191         /* Reset the hw statistics */
1192         ixgbe_dev_stats_reset(eth_dev);
1193
1194         /* disable interrupt */
1195         ixgbe_disable_intr(hw);
1196
1197         /* reset mappings for queue statistics hw counters*/
1198         ixgbe_reset_qstat_mappings(hw);
1199
1200         /* Allocate memory for storing MAC addresses */
1201         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1202                                                hw->mac.num_rar_entries, 0);
1203         if (eth_dev->data->mac_addrs == NULL) {
1204                 PMD_INIT_LOG(ERR,
1205                              "Failed to allocate %u bytes needed to store "
1206                              "MAC addresses",
1207                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1208                 return -ENOMEM;
1209         }
1210         /* Copy the permanent MAC address */
1211         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1212                         &eth_dev->data->mac_addrs[0]);
1213
1214         /* Allocate memory for storing hash filter MAC addresses */
1215         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1216                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1217         if (eth_dev->data->hash_mac_addrs == NULL) {
1218                 PMD_INIT_LOG(ERR,
1219                              "Failed to allocate %d bytes needed to store MAC addresses",
1220                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1221                 return -ENOMEM;
1222         }
1223
1224         /* initialize the vfta */
1225         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1226
1227         /* initialize the hw strip bitmap*/
1228         memset(hwstrip, 0, sizeof(*hwstrip));
1229
1230         /* initialize PF if max_vfs not zero */
1231         ixgbe_pf_host_init(eth_dev);
1232
1233         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1234         /* let hardware know driver is loaded */
1235         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1236         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1237         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1238         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1239         IXGBE_WRITE_FLUSH(hw);
1240
1241         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type,
1244                              (int) hw->phy.sfp_type);
1245         else
1246                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1247                              (int) hw->mac.type, (int) hw->phy.type);
1248
1249         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1250                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1251                      pci_dev->id.device_id);
1252
1253         rte_intr_callback_register(intr_handle,
1254                                    ixgbe_dev_interrupt_handler, eth_dev);
1255
1256         /* enable uio/vfio intr/eventfd mapping */
1257         rte_intr_enable(intr_handle);
1258
1259         /* enable support intr */
1260         ixgbe_enable_intr(eth_dev);
1261
1262         /* initialize filter info */
1263         memset(filter_info, 0,
1264                sizeof(struct ixgbe_filter_info));
1265
1266         /* initialize 5tuple filter list */
1267         TAILQ_INIT(&filter_info->fivetuple_list);
1268
1269         /* initialize flow director filter list & hash */
1270         ixgbe_fdir_filter_init(eth_dev);
1271
1272         /* initialize l2 tunnel filter list & hash */
1273         ixgbe_l2_tn_filter_init(eth_dev);
1274
1275         /* initialize flow filter lists */
1276         ixgbe_filterlist_init();
1277
1278         /* initialize bandwidth configuration info */
1279         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1280
1281         /* initialize Traffic Manager configuration */
1282         ixgbe_tm_conf_init(eth_dev);
1283
1284         return 0;
1285 }
1286
1287 static int
1288 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1289 {
1290         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1291         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1292         struct ixgbe_hw *hw;
1293         int retries = 0;
1294         int ret;
1295
1296         PMD_INIT_FUNC_TRACE();
1297
1298         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1299                 return -EPERM;
1300
1301         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1302
1303         if (hw->adapter_stopped == 0)
1304                 ixgbe_dev_close(eth_dev);
1305
1306         eth_dev->dev_ops = NULL;
1307         eth_dev->rx_pkt_burst = NULL;
1308         eth_dev->tx_pkt_burst = NULL;
1309
1310         /* Unlock any pending hardware semaphore */
1311         ixgbe_swfw_lock_reset(hw);
1312
1313         /* disable uio intr before callback unregister */
1314         rte_intr_disable(intr_handle);
1315
1316         do {
1317                 ret = rte_intr_callback_unregister(intr_handle,
1318                                 ixgbe_dev_interrupt_handler, eth_dev);
1319                 if (ret >= 0) {
1320                         break;
1321                 } else if (ret != -EAGAIN) {
1322                         PMD_INIT_LOG(ERR,
1323                                 "intr callback unregister failed: %d",
1324                                 ret);
1325                         return ret;
1326                 }
1327                 rte_delay_ms(100);
1328         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1329
1330         /* uninitialize PF if max_vfs not zero */
1331         ixgbe_pf_host_uninit(eth_dev);
1332
1333         rte_free(eth_dev->data->mac_addrs);
1334         eth_dev->data->mac_addrs = NULL;
1335
1336         rte_free(eth_dev->data->hash_mac_addrs);
1337         eth_dev->data->hash_mac_addrs = NULL;
1338
1339         /* remove all the fdir filters & hash */
1340         ixgbe_fdir_filter_uninit(eth_dev);
1341
1342         /* remove all the L2 tunnel filters & hash */
1343         ixgbe_l2_tn_filter_uninit(eth_dev);
1344
1345         /* Remove all ntuple filters of the device */
1346         ixgbe_ntuple_filter_uninit(eth_dev);
1347
1348         /* clear all the filters list */
1349         ixgbe_filterlist_flush();
1350
1351         /* Remove all Traffic Manager configuration */
1352         ixgbe_tm_conf_uninit(eth_dev);
1353
1354 #ifdef RTE_LIBRTE_SECURITY
1355         rte_free(eth_dev->security_ctx);
1356 #endif
1357
1358         return 0;
1359 }
1360
1361 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1362 {
1363         struct ixgbe_filter_info *filter_info =
1364                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1365         struct ixgbe_5tuple_filter *p_5tuple;
1366
1367         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1368                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1369                              p_5tuple,
1370                              entries);
1371                 rte_free(p_5tuple);
1372         }
1373         memset(filter_info->fivetuple_mask, 0,
1374                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1375
1376         return 0;
1377 }
1378
1379 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1380 {
1381         struct ixgbe_hw_fdir_info *fdir_info =
1382                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1383         struct ixgbe_fdir_filter *fdir_filter;
1384
1385                 if (fdir_info->hash_map)
1386                 rte_free(fdir_info->hash_map);
1387         if (fdir_info->hash_handle)
1388                 rte_hash_free(fdir_info->hash_handle);
1389
1390         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1391                 TAILQ_REMOVE(&fdir_info->fdir_list,
1392                              fdir_filter,
1393                              entries);
1394                 rte_free(fdir_filter);
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1401 {
1402         struct ixgbe_l2_tn_info *l2_tn_info =
1403                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1404         struct ixgbe_l2_tn_filter *l2_tn_filter;
1405
1406         if (l2_tn_info->hash_map)
1407                 rte_free(l2_tn_info->hash_map);
1408         if (l2_tn_info->hash_handle)
1409                 rte_hash_free(l2_tn_info->hash_handle);
1410
1411         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1412                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1413                              l2_tn_filter,
1414                              entries);
1415                 rte_free(l2_tn_filter);
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1422 {
1423         struct ixgbe_hw_fdir_info *fdir_info =
1424                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1425         char fdir_hash_name[RTE_HASH_NAMESIZE];
1426         struct rte_hash_parameters fdir_hash_params = {
1427                 .name = fdir_hash_name,
1428                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1429                 .key_len = sizeof(union ixgbe_atr_input),
1430                 .hash_func = rte_hash_crc,
1431                 .hash_func_init_val = 0,
1432                 .socket_id = rte_socket_id(),
1433         };
1434
1435         TAILQ_INIT(&fdir_info->fdir_list);
1436         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1437                  "fdir_%s", eth_dev->device->name);
1438         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1439         if (!fdir_info->hash_handle) {
1440                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1441                 return -EINVAL;
1442         }
1443         fdir_info->hash_map = rte_zmalloc("ixgbe",
1444                                           sizeof(struct ixgbe_fdir_filter *) *
1445                                           IXGBE_MAX_FDIR_FILTER_NUM,
1446                                           0);
1447         if (!fdir_info->hash_map) {
1448                 PMD_INIT_LOG(ERR,
1449                              "Failed to allocate memory for fdir hash map!");
1450                 return -ENOMEM;
1451         }
1452         fdir_info->mask_added = FALSE;
1453
1454         return 0;
1455 }
1456
1457 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1458 {
1459         struct ixgbe_l2_tn_info *l2_tn_info =
1460                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1461         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1462         struct rte_hash_parameters l2_tn_hash_params = {
1463                 .name = l2_tn_hash_name,
1464                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1465                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1466                 .hash_func = rte_hash_crc,
1467                 .hash_func_init_val = 0,
1468                 .socket_id = rte_socket_id(),
1469         };
1470
1471         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1472         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1473                  "l2_tn_%s", eth_dev->device->name);
1474         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1475         if (!l2_tn_info->hash_handle) {
1476                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1477                 return -EINVAL;
1478         }
1479         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1480                                    sizeof(struct ixgbe_l2_tn_filter *) *
1481                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1482                                    0);
1483         if (!l2_tn_info->hash_map) {
1484                 PMD_INIT_LOG(ERR,
1485                         "Failed to allocate memory for L2 TN hash map!");
1486                 return -ENOMEM;
1487         }
1488         l2_tn_info->e_tag_en = FALSE;
1489         l2_tn_info->e_tag_fwd_en = FALSE;
1490         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1491
1492         return 0;
1493 }
1494 /*
1495  * Negotiate mailbox API version with the PF.
1496  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1497  * Then we try to negotiate starting with the most recent one.
1498  * If all negotiation attempts fail, then we will proceed with
1499  * the default one (ixgbe_mbox_api_10).
1500  */
1501 static void
1502 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1503 {
1504         int32_t i;
1505
1506         /* start with highest supported, proceed down */
1507         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1508                 ixgbe_mbox_api_12,
1509                 ixgbe_mbox_api_11,
1510                 ixgbe_mbox_api_10,
1511         };
1512
1513         for (i = 0;
1514                         i != RTE_DIM(sup_ver) &&
1515                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1516                         i++)
1517                 ;
1518 }
1519
1520 static void
1521 generate_random_mac_addr(struct ether_addr *mac_addr)
1522 {
1523         uint64_t random;
1524
1525         /* Set Organizationally Unique Identifier (OUI) prefix. */
1526         mac_addr->addr_bytes[0] = 0x00;
1527         mac_addr->addr_bytes[1] = 0x09;
1528         mac_addr->addr_bytes[2] = 0xC0;
1529         /* Force indication of locally assigned MAC address. */
1530         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1531         /* Generate the last 3 bytes of the MAC address with a random number. */
1532         random = rte_rand();
1533         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1534 }
1535
1536 /*
1537  * Virtual Function device init
1538  */
1539 static int
1540 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1541 {
1542         int diag;
1543         uint32_t tc, tcs;
1544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1546         struct ixgbe_hw *hw =
1547                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1548         struct ixgbe_vfta *shadow_vfta =
1549                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1550         struct ixgbe_hwstrip *hwstrip =
1551                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1552         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1553
1554         PMD_INIT_FUNC_TRACE();
1555
1556         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1557         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1558         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1559
1560         /* for secondary processes, we don't initialise any further as primary
1561          * has already done this work. Only check we don't need a different
1562          * RX function
1563          */
1564         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1565                 struct ixgbe_tx_queue *txq;
1566                 /* TX queue function in primary, set by last queue initialized
1567                  * Tx queue may not initialized by primary process
1568                  */
1569                 if (eth_dev->data->tx_queues) {
1570                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1571                         ixgbe_set_tx_function(eth_dev, txq);
1572                 } else {
1573                         /* Use default TX function if we get here */
1574                         PMD_INIT_LOG(NOTICE,
1575                                      "No TX queues configured yet. Using default TX function.");
1576                 }
1577
1578                 ixgbe_set_rx_function(eth_dev);
1579
1580                 return 0;
1581         }
1582
1583         rte_eth_copy_pci_info(eth_dev, pci_dev);
1584
1585         hw->device_id = pci_dev->id.device_id;
1586         hw->vendor_id = pci_dev->id.vendor_id;
1587         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1588
1589         /* initialize the vfta */
1590         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1591
1592         /* initialize the hw strip bitmap*/
1593         memset(hwstrip, 0, sizeof(*hwstrip));
1594
1595         /* Initialize the shared code (base driver) */
1596         diag = ixgbe_init_shared_code(hw);
1597         if (diag != IXGBE_SUCCESS) {
1598                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1599                 return -EIO;
1600         }
1601
1602         /* init_mailbox_params */
1603         hw->mbx.ops.init_params(hw);
1604
1605         /* Reset the hw statistics */
1606         ixgbevf_dev_stats_reset(eth_dev);
1607
1608         /* Disable the interrupts for VF */
1609         ixgbevf_intr_disable(hw);
1610
1611         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1612         diag = hw->mac.ops.reset_hw(hw);
1613
1614         /*
1615          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1616          * the underlying PF driver has not assigned a MAC address to the VF.
1617          * In this case, assign a random MAC address.
1618          */
1619         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1620                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1621                 return diag;
1622         }
1623
1624         /* negotiate mailbox API version to use with the PF. */
1625         ixgbevf_negotiate_api(hw);
1626
1627         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1628         ixgbevf_get_queues(hw, &tcs, &tc);
1629
1630         /* Allocate memory for storing MAC addresses */
1631         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1632                                                hw->mac.num_rar_entries, 0);
1633         if (eth_dev->data->mac_addrs == NULL) {
1634                 PMD_INIT_LOG(ERR,
1635                              "Failed to allocate %u bytes needed to store "
1636                              "MAC addresses",
1637                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1638                 return -ENOMEM;
1639         }
1640
1641         /* Generate a random MAC address, if none was assigned by PF. */
1642         if (is_zero_ether_addr(perm_addr)) {
1643                 generate_random_mac_addr(perm_addr);
1644                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1645                 if (diag) {
1646                         rte_free(eth_dev->data->mac_addrs);
1647                         eth_dev->data->mac_addrs = NULL;
1648                         return diag;
1649                 }
1650                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1651                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1652                              "%02x:%02x:%02x:%02x:%02x:%02x",
1653                              perm_addr->addr_bytes[0],
1654                              perm_addr->addr_bytes[1],
1655                              perm_addr->addr_bytes[2],
1656                              perm_addr->addr_bytes[3],
1657                              perm_addr->addr_bytes[4],
1658                              perm_addr->addr_bytes[5]);
1659         }
1660
1661         /* Copy the permanent MAC address */
1662         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1663
1664         /* reset the hardware with the new settings */
1665         diag = hw->mac.ops.start_hw(hw);
1666         switch (diag) {
1667         case  0:
1668                 break;
1669
1670         default:
1671                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1672                 return -EIO;
1673         }
1674
1675         rte_intr_callback_register(intr_handle,
1676                                    ixgbevf_dev_interrupt_handler, eth_dev);
1677         rte_intr_enable(intr_handle);
1678         ixgbevf_intr_enable(hw);
1679
1680         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1681                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1682                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1683
1684         return 0;
1685 }
1686
1687 /* Virtual Function device uninit */
1688
1689 static int
1690 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1691 {
1692         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1693         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1694         struct ixgbe_hw *hw;
1695
1696         PMD_INIT_FUNC_TRACE();
1697
1698         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1699                 return -EPERM;
1700
1701         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1702
1703         if (hw->adapter_stopped == 0)
1704                 ixgbevf_dev_close(eth_dev);
1705
1706         eth_dev->dev_ops = NULL;
1707         eth_dev->rx_pkt_burst = NULL;
1708         eth_dev->tx_pkt_burst = NULL;
1709
1710         /* Disable the interrupts for VF */
1711         ixgbevf_intr_disable(hw);
1712
1713         rte_free(eth_dev->data->mac_addrs);
1714         eth_dev->data->mac_addrs = NULL;
1715
1716         rte_intr_disable(intr_handle);
1717         rte_intr_callback_unregister(intr_handle,
1718                                      ixgbevf_dev_interrupt_handler, eth_dev);
1719
1720         return 0;
1721 }
1722
1723 static int
1724 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1725                 struct rte_pci_device *pci_dev)
1726 {
1727         char name[RTE_ETH_NAME_MAX_LEN];
1728         struct rte_eth_dev *pf_ethdev;
1729         struct rte_eth_devargs eth_da;
1730         int i, retval;
1731
1732         if (pci_dev->device.devargs) {
1733                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1734                                 &eth_da);
1735                 if (retval)
1736                         return retval;
1737         } else
1738                 memset(&eth_da, 0, sizeof(eth_da));
1739
1740         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1741                 sizeof(struct ixgbe_adapter),
1742                 eth_dev_pci_specific_init, pci_dev,
1743                 eth_ixgbe_dev_init, NULL);
1744
1745         if (retval || eth_da.nb_representor_ports < 1)
1746                 return retval;
1747
1748         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1749         if (pf_ethdev == NULL)
1750                 return -ENODEV;
1751
1752         /* probe VF representor ports */
1753         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1754                 struct ixgbe_vf_info *vfinfo;
1755                 struct ixgbe_vf_representor representor;
1756
1757                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1758                         pf_ethdev->data->dev_private);
1759                 if (vfinfo == NULL) {
1760                         PMD_DRV_LOG(ERR,
1761                                 "no virtual functions supported by PF");
1762                         break;
1763                 }
1764
1765                 representor.vf_id = eth_da.representor_ports[i];
1766                 representor.switch_domain_id = vfinfo->switch_domain_id;
1767                 representor.pf_ethdev = pf_ethdev;
1768
1769                 /* representor port net_bdf_port */
1770                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1771                         pci_dev->device.name,
1772                         eth_da.representor_ports[i]);
1773
1774                 retval = rte_eth_dev_create(&pci_dev->device, name,
1775                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1776                         ixgbe_vf_representor_init, &representor);
1777
1778                 if (retval)
1779                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1780                                 "representor %s.", name);
1781         }
1782
1783         return 0;
1784 }
1785
1786 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1787 {
1788         struct rte_eth_dev *ethdev;
1789
1790         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1791         if (!ethdev)
1792                 return -ENODEV;
1793
1794         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1795                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1796         else
1797                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1798 }
1799
1800 static struct rte_pci_driver rte_ixgbe_pmd = {
1801         .id_table = pci_id_ixgbe_map,
1802         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1803                      RTE_PCI_DRV_IOVA_AS_VA,
1804         .probe = eth_ixgbe_pci_probe,
1805         .remove = eth_ixgbe_pci_remove,
1806 };
1807
1808 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1809         struct rte_pci_device *pci_dev)
1810 {
1811         return rte_eth_dev_pci_generic_probe(pci_dev,
1812                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1813 }
1814
1815 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1816 {
1817         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1818 }
1819
1820 /*
1821  * virtual function driver struct
1822  */
1823 static struct rte_pci_driver rte_ixgbevf_pmd = {
1824         .id_table = pci_id_ixgbevf_map,
1825         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1826         .probe = eth_ixgbevf_pci_probe,
1827         .remove = eth_ixgbevf_pci_remove,
1828 };
1829
1830 static int
1831 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1832 {
1833         struct ixgbe_hw *hw =
1834                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         struct ixgbe_vfta *shadow_vfta =
1836                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1837         uint32_t vfta;
1838         uint32_t vid_idx;
1839         uint32_t vid_bit;
1840
1841         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1842         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1843         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1844         if (on)
1845                 vfta |= vid_bit;
1846         else
1847                 vfta &= ~vid_bit;
1848         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1849
1850         /* update local VFTA copy */
1851         shadow_vfta->vfta[vid_idx] = vfta;
1852
1853         return 0;
1854 }
1855
1856 static void
1857 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1858 {
1859         if (on)
1860                 ixgbe_vlan_hw_strip_enable(dev, queue);
1861         else
1862                 ixgbe_vlan_hw_strip_disable(dev, queue);
1863 }
1864
1865 static int
1866 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1867                     enum rte_vlan_type vlan_type,
1868                     uint16_t tpid)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         int ret = 0;
1873         uint32_t reg;
1874         uint32_t qinq;
1875
1876         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1877         qinq &= IXGBE_DMATXCTL_GDV;
1878
1879         switch (vlan_type) {
1880         case ETH_VLAN_TYPE_INNER:
1881                 if (qinq) {
1882                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1889                 } else {
1890                         ret = -ENOTSUP;
1891                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1892                                     " by single VLAN");
1893                 }
1894                 break;
1895         case ETH_VLAN_TYPE_OUTER:
1896                 if (qinq) {
1897                         /* Only the high 16-bits is valid */
1898                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1899                                         IXGBE_EXVET_VET_EXT_SHIFT);
1900                 } else {
1901                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1902                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1903                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1904                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1905                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1906                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1907                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1908                 }
1909
1910                 break;
1911         default:
1912                 ret = -EINVAL;
1913                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1914                 break;
1915         }
1916
1917         return ret;
1918 }
1919
1920 void
1921 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1922 {
1923         struct ixgbe_hw *hw =
1924                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925         uint32_t vlnctrl;
1926
1927         PMD_INIT_FUNC_TRACE();
1928
1929         /* Filter Table Disable */
1930         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1932
1933         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1934 }
1935
1936 void
1937 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1938 {
1939         struct ixgbe_hw *hw =
1940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct ixgbe_vfta *shadow_vfta =
1942                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1943         uint32_t vlnctrl;
1944         uint16_t i;
1945
1946         PMD_INIT_FUNC_TRACE();
1947
1948         /* Filter Table Enable */
1949         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1950         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1951         vlnctrl |= IXGBE_VLNCTRL_VFE;
1952
1953         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1954
1955         /* write whatever is in local vfta copy */
1956         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1957                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1958 }
1959
1960 static void
1961 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1962 {
1963         struct ixgbe_hwstrip *hwstrip =
1964                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1965         struct ixgbe_rx_queue *rxq;
1966
1967         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1968                 return;
1969
1970         if (on)
1971                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1972         else
1973                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1974
1975         if (queue >= dev->data->nb_rx_queues)
1976                 return;
1977
1978         rxq = dev->data->rx_queues[queue];
1979
1980         if (on)
1981                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1982         else
1983                 rxq->vlan_flags = PKT_RX_VLAN;
1984 }
1985
1986 static void
1987 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1988 {
1989         struct ixgbe_hw *hw =
1990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         uint32_t ctrl;
1992
1993         PMD_INIT_FUNC_TRACE();
1994
1995         if (hw->mac.type == ixgbe_mac_82598EB) {
1996                 /* No queue level support */
1997                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1998                 return;
1999         }
2000
2001         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2002         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2003         ctrl &= ~IXGBE_RXDCTL_VME;
2004         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2005
2006         /* record those setting for HW strip per queue */
2007         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2008 }
2009
2010 static void
2011 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2012 {
2013         struct ixgbe_hw *hw =
2014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2015         uint32_t ctrl;
2016
2017         PMD_INIT_FUNC_TRACE();
2018
2019         if (hw->mac.type == ixgbe_mac_82598EB) {
2020                 /* No queue level supported */
2021                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2022                 return;
2023         }
2024
2025         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2026         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2027         ctrl |= IXGBE_RXDCTL_VME;
2028         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2029
2030         /* record those setting for HW strip per queue */
2031         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2032 }
2033
2034 static void
2035 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2036 {
2037         struct ixgbe_hw *hw =
2038                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039         uint32_t ctrl;
2040
2041         PMD_INIT_FUNC_TRACE();
2042
2043         /* DMATXCTRL: Geric Double VLAN Disable */
2044         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2045         ctrl &= ~IXGBE_DMATXCTL_GDV;
2046         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2047
2048         /* CTRL_EXT: Global Double VLAN Disable */
2049         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2050         ctrl &= ~IXGBE_EXTENDED_VLAN;
2051         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2052
2053 }
2054
2055 static void
2056 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2057 {
2058         struct ixgbe_hw *hw =
2059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         uint32_t ctrl;
2061
2062         PMD_INIT_FUNC_TRACE();
2063
2064         /* DMATXCTRL: Geric Double VLAN Enable */
2065         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2066         ctrl |= IXGBE_DMATXCTL_GDV;
2067         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2068
2069         /* CTRL_EXT: Global Double VLAN Enable */
2070         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2071         ctrl |= IXGBE_EXTENDED_VLAN;
2072         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2073
2074         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2075         if (hw->mac.type == ixgbe_mac_X550 ||
2076             hw->mac.type == ixgbe_mac_X550EM_x ||
2077             hw->mac.type == ixgbe_mac_X550EM_a) {
2078                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2079                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2080                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2081         }
2082
2083         /*
2084          * VET EXT field in the EXVET register = 0x8100 by default
2085          * So no need to change. Same to VT field of DMATXCTL register
2086          */
2087 }
2088
2089 void
2090 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2091 {
2092         struct ixgbe_hw *hw =
2093                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2094         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2095         uint32_t ctrl;
2096         uint16_t i;
2097         struct ixgbe_rx_queue *rxq;
2098         bool on;
2099
2100         PMD_INIT_FUNC_TRACE();
2101
2102         if (hw->mac.type == ixgbe_mac_82598EB) {
2103                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2104                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2105                         ctrl |= IXGBE_VLNCTRL_VME;
2106                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2107                 } else {
2108                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2109                         ctrl &= ~IXGBE_VLNCTRL_VME;
2110                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2111                 }
2112         } else {
2113                 /*
2114                  * Other 10G NIC, the VLAN strip can be setup
2115                  * per queue in RXDCTL
2116                  */
2117                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2118                         rxq = dev->data->rx_queues[i];
2119                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2120                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2121                                 ctrl |= IXGBE_RXDCTL_VME;
2122                                 on = TRUE;
2123                         } else {
2124                                 ctrl &= ~IXGBE_RXDCTL_VME;
2125                                 on = FALSE;
2126                         }
2127                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2128
2129                         /* record those setting for HW strip per queue */
2130                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2131                 }
2132         }
2133 }
2134
2135 static int
2136 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2137 {
2138         struct rte_eth_rxmode *rxmode;
2139         rxmode = &dev->data->dev_conf.rxmode;
2140
2141         if (mask & ETH_VLAN_STRIP_MASK) {
2142                 ixgbe_vlan_hw_strip_config(dev);
2143         }
2144
2145         if (mask & ETH_VLAN_FILTER_MASK) {
2146                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2147                         ixgbe_vlan_hw_filter_enable(dev);
2148                 else
2149                         ixgbe_vlan_hw_filter_disable(dev);
2150         }
2151
2152         if (mask & ETH_VLAN_EXTEND_MASK) {
2153                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2154                         ixgbe_vlan_hw_extend_enable(dev);
2155                 else
2156                         ixgbe_vlan_hw_extend_disable(dev);
2157         }
2158
2159         return 0;
2160 }
2161
2162 static void
2163 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2164 {
2165         struct ixgbe_hw *hw =
2166                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2168         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2169
2170         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2171         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2172 }
2173
2174 static int
2175 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2176 {
2177         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2178
2179         switch (nb_rx_q) {
2180         case 1:
2181         case 2:
2182                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2183                 break;
2184         case 4:
2185                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2186                 break;
2187         default:
2188                 return -EINVAL;
2189         }
2190
2191         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2192                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2193         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2194                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2195         return 0;
2196 }
2197
2198 static int
2199 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2200 {
2201         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2202         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2204         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2205
2206         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2207                 /* check multi-queue mode */
2208                 switch (dev_conf->rxmode.mq_mode) {
2209                 case ETH_MQ_RX_VMDQ_DCB:
2210                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2211                         break;
2212                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2213                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2214                         PMD_INIT_LOG(ERR, "SRIOV active,"
2215                                         " unsupported mq_mode rx %d.",
2216                                         dev_conf->rxmode.mq_mode);
2217                         return -EINVAL;
2218                 case ETH_MQ_RX_RSS:
2219                 case ETH_MQ_RX_VMDQ_RSS:
2220                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2221                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2222                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2223                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2224                                                 " invalid queue number"
2225                                                 " for VMDQ RSS, allowed"
2226                                                 " value are 1, 2 or 4.");
2227                                         return -EINVAL;
2228                                 }
2229                         break;
2230                 case ETH_MQ_RX_VMDQ_ONLY:
2231                 case ETH_MQ_RX_NONE:
2232                         /* if nothing mq mode configure, use default scheme */
2233                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2234                         break;
2235                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2236                         /* SRIOV only works in VMDq enable mode */
2237                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2238                                         " wrong mq_mode rx %d.",
2239                                         dev_conf->rxmode.mq_mode);
2240                         return -EINVAL;
2241                 }
2242
2243                 switch (dev_conf->txmode.mq_mode) {
2244                 case ETH_MQ_TX_VMDQ_DCB:
2245                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2246                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2247                         break;
2248                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2249                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2250                         break;
2251                 }
2252
2253                 /* check valid queue number */
2254                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2255                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2256                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2257                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2258                                         " must be less than or equal to %d.",
2259                                         nb_rx_q, nb_tx_q,
2260                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2261                         return -EINVAL;
2262                 }
2263         } else {
2264                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2265                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2266                                           " not supported.");
2267                         return -EINVAL;
2268                 }
2269                 /* check configuration for vmdb+dcb mode */
2270                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2271                         const struct rte_eth_vmdq_dcb_conf *conf;
2272
2273                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2274                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2275                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2276                                 return -EINVAL;
2277                         }
2278                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2279                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2280                                conf->nb_queue_pools == ETH_32_POOLS)) {
2281                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2282                                                 " nb_queue_pools must be %d or %d.",
2283                                                 ETH_16_POOLS, ETH_32_POOLS);
2284                                 return -EINVAL;
2285                         }
2286                 }
2287                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2288                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2289
2290                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2291                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2292                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2293                                 return -EINVAL;
2294                         }
2295                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2296                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2297                                conf->nb_queue_pools == ETH_32_POOLS)) {
2298                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2299                                                 " nb_queue_pools != %d and"
2300                                                 " nb_queue_pools != %d.",
2301                                                 ETH_16_POOLS, ETH_32_POOLS);
2302                                 return -EINVAL;
2303                         }
2304                 }
2305
2306                 /* For DCB mode check our configuration before we go further */
2307                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2308                         const struct rte_eth_dcb_rx_conf *conf;
2309
2310                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2311                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2312                                                  IXGBE_DCB_NB_QUEUES);
2313                                 return -EINVAL;
2314                         }
2315                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2316                         if (!(conf->nb_tcs == ETH_4_TCS ||
2317                                conf->nb_tcs == ETH_8_TCS)) {
2318                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2319                                                 " and nb_tcs != %d.",
2320                                                 ETH_4_TCS, ETH_8_TCS);
2321                                 return -EINVAL;
2322                         }
2323                 }
2324
2325                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2326                         const struct rte_eth_dcb_tx_conf *conf;
2327
2328                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2329                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2330                                                  IXGBE_DCB_NB_QUEUES);
2331                                 return -EINVAL;
2332                         }
2333                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2334                         if (!(conf->nb_tcs == ETH_4_TCS ||
2335                                conf->nb_tcs == ETH_8_TCS)) {
2336                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2337                                                 " and nb_tcs != %d.",
2338                                                 ETH_4_TCS, ETH_8_TCS);
2339                                 return -EINVAL;
2340                         }
2341                 }
2342
2343                 /*
2344                  * When DCB/VT is off, maximum number of queues changes,
2345                  * except for 82598EB, which remains constant.
2346                  */
2347                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2348                                 hw->mac.type != ixgbe_mac_82598EB) {
2349                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2350                                 PMD_INIT_LOG(ERR,
2351                                              "Neither VT nor DCB are enabled, "
2352                                              "nb_tx_q > %d.",
2353                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2354                                 return -EINVAL;
2355                         }
2356                 }
2357         }
2358         return 0;
2359 }
2360
2361 static int
2362 ixgbe_dev_configure(struct rte_eth_dev *dev)
2363 {
2364         struct ixgbe_interrupt *intr =
2365                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2366         struct ixgbe_adapter *adapter =
2367                 (struct ixgbe_adapter *)dev->data->dev_private;
2368         struct rte_eth_dev_info dev_info;
2369         uint64_t rx_offloads;
2370         uint64_t tx_offloads;
2371         int ret;
2372
2373         PMD_INIT_FUNC_TRACE();
2374         /* multipe queue mode checking */
2375         ret  = ixgbe_check_mq_mode(dev);
2376         if (ret != 0) {
2377                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2378                             ret);
2379                 return ret;
2380         }
2381
2382         ixgbe_dev_info_get(dev, &dev_info);
2383         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2384         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2385                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2386                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2387                             rx_offloads, dev_info.rx_offload_capa);
2388                 return -ENOTSUP;
2389         }
2390         tx_offloads = dev->data->dev_conf.txmode.offloads;
2391         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2392                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2393                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2394                             tx_offloads, dev_info.tx_offload_capa);
2395                 return -ENOTSUP;
2396         }
2397
2398         /* set flag to update link status after init */
2399         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2400
2401         /*
2402          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2403          * allocation or vector Rx preconditions we will reset it.
2404          */
2405         adapter->rx_bulk_alloc_allowed = true;
2406         adapter->rx_vec_allowed = true;
2407
2408         return 0;
2409 }
2410
2411 static void
2412 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2413 {
2414         struct ixgbe_hw *hw =
2415                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2416         struct ixgbe_interrupt *intr =
2417                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2418         uint32_t gpie;
2419
2420         /* only set up it on X550EM_X */
2421         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2422                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2423                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2424                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2425                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2426                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2427         }
2428 }
2429
2430 int
2431 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2432                         uint16_t tx_rate, uint64_t q_msk)
2433 {
2434         struct ixgbe_hw *hw;
2435         struct ixgbe_vf_info *vfinfo;
2436         struct rte_eth_link link;
2437         uint8_t  nb_q_per_pool;
2438         uint32_t queue_stride;
2439         uint32_t queue_idx, idx = 0, vf_idx;
2440         uint32_t queue_end;
2441         uint16_t total_rate = 0;
2442         struct rte_pci_device *pci_dev;
2443
2444         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2445         rte_eth_link_get_nowait(dev->data->port_id, &link);
2446
2447         if (vf >= pci_dev->max_vfs)
2448                 return -EINVAL;
2449
2450         if (tx_rate > link.link_speed)
2451                 return -EINVAL;
2452
2453         if (q_msk == 0)
2454                 return 0;
2455
2456         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2458         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2459         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2460         queue_idx = vf * queue_stride;
2461         queue_end = queue_idx + nb_q_per_pool - 1;
2462         if (queue_end >= hw->mac.max_tx_queues)
2463                 return -EINVAL;
2464
2465         if (vfinfo) {
2466                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2467                         if (vf_idx == vf)
2468                                 continue;
2469                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2470                                 idx++)
2471                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2472                 }
2473         } else {
2474                 return -EINVAL;
2475         }
2476
2477         /* Store tx_rate for this vf. */
2478         for (idx = 0; idx < nb_q_per_pool; idx++) {
2479                 if (((uint64_t)0x1 << idx) & q_msk) {
2480                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2481                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2482                         total_rate += tx_rate;
2483                 }
2484         }
2485
2486         if (total_rate > dev->data->dev_link.link_speed) {
2487                 /* Reset stored TX rate of the VF if it causes exceed
2488                  * link speed.
2489                  */
2490                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2491                 return -EINVAL;
2492         }
2493
2494         /* Set RTTBCNRC of each queue/pool for vf X  */
2495         for (; queue_idx <= queue_end; queue_idx++) {
2496                 if (0x1 & q_msk)
2497                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2498                 q_msk = q_msk >> 1;
2499         }
2500
2501         return 0;
2502 }
2503
2504 /*
2505  * Configure device link speed and setup link.
2506  * It returns 0 on success.
2507  */
2508 static int
2509 ixgbe_dev_start(struct rte_eth_dev *dev)
2510 {
2511         struct ixgbe_hw *hw =
2512                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513         struct ixgbe_vf_info *vfinfo =
2514                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2515         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2516         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2517         uint32_t intr_vector = 0;
2518         int err, link_up = 0, negotiate = 0;
2519         uint32_t speed = 0;
2520         uint32_t allowed_speeds = 0;
2521         int mask = 0;
2522         int status;
2523         uint16_t vf, idx;
2524         uint32_t *link_speeds;
2525         struct ixgbe_tm_conf *tm_conf =
2526                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2527
2528         PMD_INIT_FUNC_TRACE();
2529
2530         /* IXGBE devices don't support:
2531         *    - half duplex (checked afterwards for valid speeds)
2532         *    - fixed speed: TODO implement
2533         */
2534         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2535                 PMD_INIT_LOG(ERR,
2536                 "Invalid link_speeds for port %u, fix speed not supported",
2537                                 dev->data->port_id);
2538                 return -EINVAL;
2539         }
2540
2541         /* disable uio/vfio intr/eventfd mapping */
2542         rte_intr_disable(intr_handle);
2543
2544         /* stop adapter */
2545         hw->adapter_stopped = 0;
2546         ixgbe_stop_adapter(hw);
2547
2548         /* reinitialize adapter
2549          * this calls reset and start
2550          */
2551         status = ixgbe_pf_reset_hw(hw);
2552         if (status != 0)
2553                 return -1;
2554         hw->mac.ops.start_hw(hw);
2555         hw->mac.get_link_status = true;
2556
2557         /* configure PF module if SRIOV enabled */
2558         ixgbe_pf_host_configure(dev);
2559
2560         ixgbe_dev_phy_intr_setup(dev);
2561
2562         /* check and configure queue intr-vector mapping */
2563         if ((rte_intr_cap_multiple(intr_handle) ||
2564              !RTE_ETH_DEV_SRIOV(dev).active) &&
2565             dev->data->dev_conf.intr_conf.rxq != 0) {
2566                 intr_vector = dev->data->nb_rx_queues;
2567                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2568                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2569                                         IXGBE_MAX_INTR_QUEUE_NUM);
2570                         return -ENOTSUP;
2571                 }
2572                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2573                         return -1;
2574         }
2575
2576         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2577                 intr_handle->intr_vec =
2578                         rte_zmalloc("intr_vec",
2579                                     dev->data->nb_rx_queues * sizeof(int), 0);
2580                 if (intr_handle->intr_vec == NULL) {
2581                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2582                                      " intr_vec", dev->data->nb_rx_queues);
2583                         return -ENOMEM;
2584                 }
2585         }
2586
2587         /* confiugre msix for sleep until rx interrupt */
2588         ixgbe_configure_msix(dev);
2589
2590         /* initialize transmission unit */
2591         ixgbe_dev_tx_init(dev);
2592
2593         /* This can fail when allocating mbufs for descriptor rings */
2594         err = ixgbe_dev_rx_init(dev);
2595         if (err) {
2596                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2597                 goto error;
2598         }
2599
2600         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2601                 ETH_VLAN_EXTEND_MASK;
2602         err = ixgbe_vlan_offload_set(dev, mask);
2603         if (err) {
2604                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2605                 goto error;
2606         }
2607
2608         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2609                 /* Enable vlan filtering for VMDq */
2610                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2611         }
2612
2613         /* Configure DCB hw */
2614         ixgbe_configure_dcb(dev);
2615
2616         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2617                 err = ixgbe_fdir_configure(dev);
2618                 if (err)
2619                         goto error;
2620         }
2621
2622         /* Restore vf rate limit */
2623         if (vfinfo != NULL) {
2624                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2625                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2626                                 if (vfinfo[vf].tx_rate[idx] != 0)
2627                                         ixgbe_set_vf_rate_limit(
2628                                                 dev, vf,
2629                                                 vfinfo[vf].tx_rate[idx],
2630                                                 1 << idx);
2631         }
2632
2633         ixgbe_restore_statistics_mapping(dev);
2634
2635         err = ixgbe_dev_rxtx_start(dev);
2636         if (err < 0) {
2637                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2638                 goto error;
2639         }
2640
2641         /* Skip link setup if loopback mode is enabled for 82599. */
2642         if (hw->mac.type == ixgbe_mac_82599EB &&
2643                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2644                 goto skip_link_setup;
2645
2646         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2647                 err = hw->mac.ops.setup_sfp(hw);
2648                 if (err)
2649                         goto error;
2650         }
2651
2652         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2653                 /* Turn on the copper */
2654                 ixgbe_set_phy_power(hw, true);
2655         } else {
2656                 /* Turn on the laser */
2657                 ixgbe_enable_tx_laser(hw);
2658         }
2659
2660         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2661         if (err)
2662                 goto error;
2663         dev->data->dev_link.link_status = link_up;
2664
2665         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2666         if (err)
2667                 goto error;
2668
2669         switch (hw->mac.type) {
2670         case ixgbe_mac_X550:
2671         case ixgbe_mac_X550EM_x:
2672         case ixgbe_mac_X550EM_a:
2673                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2674                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2675                         ETH_LINK_SPEED_10G;
2676                 break;
2677         default:
2678                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2679                         ETH_LINK_SPEED_10G;
2680         }
2681
2682         link_speeds = &dev->data->dev_conf.link_speeds;
2683         if (*link_speeds & ~allowed_speeds) {
2684                 PMD_INIT_LOG(ERR, "Invalid link setting");
2685                 goto error;
2686         }
2687
2688         speed = 0x0;
2689         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2690                 switch (hw->mac.type) {
2691                 case ixgbe_mac_82598EB:
2692                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2693                         break;
2694                 case ixgbe_mac_82599EB:
2695                 case ixgbe_mac_X540:
2696                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2697                         break;
2698                 case ixgbe_mac_X550:
2699                 case ixgbe_mac_X550EM_x:
2700                 case ixgbe_mac_X550EM_a:
2701                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2702                         break;
2703                 default:
2704                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2705                 }
2706         } else {
2707                 if (*link_speeds & ETH_LINK_SPEED_10G)
2708                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2709                 if (*link_speeds & ETH_LINK_SPEED_5G)
2710                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2711                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2712                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2713                 if (*link_speeds & ETH_LINK_SPEED_1G)
2714                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2715                 if (*link_speeds & ETH_LINK_SPEED_100M)
2716                         speed |= IXGBE_LINK_SPEED_100_FULL;
2717         }
2718
2719         err = ixgbe_setup_link(hw, speed, link_up);
2720         if (err)
2721                 goto error;
2722
2723         ixgbe_dev_link_update(dev, 0);
2724
2725 skip_link_setup:
2726
2727         if (rte_intr_allow_others(intr_handle)) {
2728                 /* check if lsc interrupt is enabled */
2729                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2730                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2731                 else
2732                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2733                 ixgbe_dev_macsec_interrupt_setup(dev);
2734         } else {
2735                 rte_intr_callback_unregister(intr_handle,
2736                                              ixgbe_dev_interrupt_handler, dev);
2737                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2738                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2739                                      " no intr multiplex");
2740         }
2741
2742         /* check if rxq interrupt is enabled */
2743         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2744             rte_intr_dp_is_en(intr_handle))
2745                 ixgbe_dev_rxq_interrupt_setup(dev);
2746
2747         /* enable uio/vfio intr/eventfd mapping */
2748         rte_intr_enable(intr_handle);
2749
2750         /* resume enabled intr since hw reset */
2751         ixgbe_enable_intr(dev);
2752         ixgbe_l2_tunnel_conf(dev);
2753         ixgbe_filter_restore(dev);
2754
2755         if (tm_conf->root && !tm_conf->committed)
2756                 PMD_DRV_LOG(WARNING,
2757                             "please call hierarchy_commit() "
2758                             "before starting the port");
2759
2760         return 0;
2761
2762 error:
2763         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2764         ixgbe_dev_clear_queues(dev);
2765         return -EIO;
2766 }
2767
2768 /*
2769  * Stop device: disable rx and tx functions to allow for reconfiguring.
2770  */
2771 static void
2772 ixgbe_dev_stop(struct rte_eth_dev *dev)
2773 {
2774         struct rte_eth_link link;
2775         struct ixgbe_hw *hw =
2776                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2777         struct ixgbe_vf_info *vfinfo =
2778                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2779         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2780         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2781         int vf;
2782         struct ixgbe_tm_conf *tm_conf =
2783                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2784
2785         PMD_INIT_FUNC_TRACE();
2786
2787         /* disable interrupts */
2788         ixgbe_disable_intr(hw);
2789
2790         /* reset the NIC */
2791         ixgbe_pf_reset_hw(hw);
2792         hw->adapter_stopped = 0;
2793
2794         /* stop adapter */
2795         ixgbe_stop_adapter(hw);
2796
2797         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2798                 vfinfo[vf].clear_to_send = false;
2799
2800         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2801                 /* Turn off the copper */
2802                 ixgbe_set_phy_power(hw, false);
2803         } else {
2804                 /* Turn off the laser */
2805                 ixgbe_disable_tx_laser(hw);
2806         }
2807
2808         ixgbe_dev_clear_queues(dev);
2809
2810         /* Clear stored conf */
2811         dev->data->scattered_rx = 0;
2812         dev->data->lro = 0;
2813
2814         /* Clear recorded link status */
2815         memset(&link, 0, sizeof(link));
2816         rte_eth_linkstatus_set(dev, &link);
2817
2818         if (!rte_intr_allow_others(intr_handle))
2819                 /* resume to the default handler */
2820                 rte_intr_callback_register(intr_handle,
2821                                            ixgbe_dev_interrupt_handler,
2822                                            (void *)dev);
2823
2824         /* Clean datapath event and queue/vec mapping */
2825         rte_intr_efd_disable(intr_handle);
2826         if (intr_handle->intr_vec != NULL) {
2827                 rte_free(intr_handle->intr_vec);
2828                 intr_handle->intr_vec = NULL;
2829         }
2830
2831         /* reset hierarchy commit */
2832         tm_conf->committed = false;
2833 }
2834
2835 /*
2836  * Set device link up: enable tx.
2837  */
2838 static int
2839 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2840 {
2841         struct ixgbe_hw *hw =
2842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843         if (hw->mac.type == ixgbe_mac_82599EB) {
2844 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2845                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2846                         /* Not suported in bypass mode */
2847                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2848                                      "by device id 0x%x", hw->device_id);
2849                         return -ENOTSUP;
2850                 }
2851 #endif
2852         }
2853
2854         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2855                 /* Turn on the copper */
2856                 ixgbe_set_phy_power(hw, true);
2857         } else {
2858                 /* Turn on the laser */
2859                 ixgbe_enable_tx_laser(hw);
2860         }
2861
2862         return 0;
2863 }
2864
2865 /*
2866  * Set device link down: disable tx.
2867  */
2868 static int
2869 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2870 {
2871         struct ixgbe_hw *hw =
2872                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873         if (hw->mac.type == ixgbe_mac_82599EB) {
2874 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2875                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2876                         /* Not suported in bypass mode */
2877                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2878                                      "by device id 0x%x", hw->device_id);
2879                         return -ENOTSUP;
2880                 }
2881 #endif
2882         }
2883
2884         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2885                 /* Turn off the copper */
2886                 ixgbe_set_phy_power(hw, false);
2887         } else {
2888                 /* Turn off the laser */
2889                 ixgbe_disable_tx_laser(hw);
2890         }
2891
2892         return 0;
2893 }
2894
2895 /*
2896  * Reset and stop device.
2897  */
2898 static void
2899 ixgbe_dev_close(struct rte_eth_dev *dev)
2900 {
2901         struct ixgbe_hw *hw =
2902                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2903
2904         PMD_INIT_FUNC_TRACE();
2905
2906         ixgbe_pf_reset_hw(hw);
2907
2908         ixgbe_dev_stop(dev);
2909         hw->adapter_stopped = 1;
2910
2911         ixgbe_dev_free_queues(dev);
2912
2913         ixgbe_disable_pcie_master(hw);
2914
2915         /* reprogram the RAR[0] in case user changed it. */
2916         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2917 }
2918
2919 /*
2920  * Reset PF device.
2921  */
2922 static int
2923 ixgbe_dev_reset(struct rte_eth_dev *dev)
2924 {
2925         int ret;
2926
2927         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2928          * its VF to make them align with it. The detailed notification
2929          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2930          * To avoid unexpected behavior in VF, currently reset of PF with
2931          * SR-IOV activation is not supported. It might be supported later.
2932          */
2933         if (dev->data->sriov.active)
2934                 return -ENOTSUP;
2935
2936         ret = eth_ixgbe_dev_uninit(dev);
2937         if (ret)
2938                 return ret;
2939
2940         ret = eth_ixgbe_dev_init(dev, NULL);
2941
2942         return ret;
2943 }
2944
2945 static void
2946 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2947                            struct ixgbe_hw_stats *hw_stats,
2948                            struct ixgbe_macsec_stats *macsec_stats,
2949                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2950                            uint64_t *total_qprc, uint64_t *total_qprdc)
2951 {
2952         uint32_t bprc, lxon, lxoff, total;
2953         uint32_t delta_gprc = 0;
2954         unsigned i;
2955         /* Workaround for RX byte count not including CRC bytes when CRC
2956          * strip is enabled. CRC bytes are removed from counters when crc_strip
2957          * is disabled.
2958          */
2959         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2960                         IXGBE_HLREG0_RXCRCSTRP);
2961
2962         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2963         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2964         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2965         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2966
2967         for (i = 0; i < 8; i++) {
2968                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2969
2970                 /* global total per queue */
2971                 hw_stats->mpc[i] += mp;
2972                 /* Running comprehensive total for stats display */
2973                 *total_missed_rx += hw_stats->mpc[i];
2974                 if (hw->mac.type == ixgbe_mac_82598EB) {
2975                         hw_stats->rnbc[i] +=
2976                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2977                         hw_stats->pxonrxc[i] +=
2978                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2979                         hw_stats->pxoffrxc[i] +=
2980                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2981                 } else {
2982                         hw_stats->pxonrxc[i] +=
2983                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2984                         hw_stats->pxoffrxc[i] +=
2985                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2986                         hw_stats->pxon2offc[i] +=
2987                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2988                 }
2989                 hw_stats->pxontxc[i] +=
2990                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2991                 hw_stats->pxofftxc[i] +=
2992                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2993         }
2994         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2995                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2996                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2997                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2998
2999                 delta_gprc += delta_qprc;
3000
3001                 hw_stats->qprc[i] += delta_qprc;
3002                 hw_stats->qptc[i] += delta_qptc;
3003
3004                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3005                 hw_stats->qbrc[i] +=
3006                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3007                 if (crc_strip == 0)
3008                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3009
3010                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3011                 hw_stats->qbtc[i] +=
3012                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3013
3014                 hw_stats->qprdc[i] += delta_qprdc;
3015                 *total_qprdc += hw_stats->qprdc[i];
3016
3017                 *total_qprc += hw_stats->qprc[i];
3018                 *total_qbrc += hw_stats->qbrc[i];
3019         }
3020         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3021         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3022         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3023
3024         /*
3025          * An errata states that gprc actually counts good + missed packets:
3026          * Workaround to set gprc to summated queue packet receives
3027          */
3028         hw_stats->gprc = *total_qprc;
3029
3030         if (hw->mac.type != ixgbe_mac_82598EB) {
3031                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3032                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3033                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3034                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3035                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3036                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3037                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3038                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3039         } else {
3040                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3041                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3042                 /* 82598 only has a counter in the high register */
3043                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3044                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3045                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3046         }
3047         uint64_t old_tpr = hw_stats->tpr;
3048
3049         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3050         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3051
3052         if (crc_strip == 0)
3053                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3054
3055         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3056         hw_stats->gptc += delta_gptc;
3057         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3058         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3059
3060         /*
3061          * Workaround: mprc hardware is incorrectly counting
3062          * broadcasts, so for now we subtract those.
3063          */
3064         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3065         hw_stats->bprc += bprc;
3066         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3067         if (hw->mac.type == ixgbe_mac_82598EB)
3068                 hw_stats->mprc -= bprc;
3069
3070         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3071         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3072         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3073         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3074         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3075         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3076
3077         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3078         hw_stats->lxontxc += lxon;
3079         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3080         hw_stats->lxofftxc += lxoff;
3081         total = lxon + lxoff;
3082
3083         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3084         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3085         hw_stats->gptc -= total;
3086         hw_stats->mptc -= total;
3087         hw_stats->ptc64 -= total;
3088         hw_stats->gotc -= total * ETHER_MIN_LEN;
3089
3090         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3091         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3092         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3093         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3094         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3095         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3096         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3097         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3098         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3099         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3100         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3101         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3102         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3103         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3104         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3105         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3106         /* Only read FCOE on 82599 */
3107         if (hw->mac.type != ixgbe_mac_82598EB) {
3108                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3109                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3110                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3111                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3112                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3113         }
3114
3115         /* Flow Director Stats registers */
3116         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3117         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3118
3119         /* MACsec Stats registers */
3120         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3121         macsec_stats->out_pkts_encrypted +=
3122                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3123         macsec_stats->out_pkts_protected +=
3124                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3125         macsec_stats->out_octets_encrypted +=
3126                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3127         macsec_stats->out_octets_protected +=
3128                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3129         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3130         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3131         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3132         macsec_stats->in_pkts_unknownsci +=
3133                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3134         macsec_stats->in_octets_decrypted +=
3135                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3136         macsec_stats->in_octets_validated +=
3137                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3138         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3139         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3140         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3141         for (i = 0; i < 2; i++) {
3142                 macsec_stats->in_pkts_ok +=
3143                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3144                 macsec_stats->in_pkts_invalid +=
3145                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3146                 macsec_stats->in_pkts_notvalid +=
3147                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3148         }
3149         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3150         macsec_stats->in_pkts_notusingsa +=
3151                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3152 }
3153
3154 /*
3155  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3156  */
3157 static int
3158 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3159 {
3160         struct ixgbe_hw *hw =
3161                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3162         struct ixgbe_hw_stats *hw_stats =
3163                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3164         struct ixgbe_macsec_stats *macsec_stats =
3165                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3166                                 dev->data->dev_private);
3167         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3168         unsigned i;
3169
3170         total_missed_rx = 0;
3171         total_qbrc = 0;
3172         total_qprc = 0;
3173         total_qprdc = 0;
3174
3175         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3176                         &total_qbrc, &total_qprc, &total_qprdc);
3177
3178         if (stats == NULL)
3179                 return -EINVAL;
3180
3181         /* Fill out the rte_eth_stats statistics structure */
3182         stats->ipackets = total_qprc;
3183         stats->ibytes = total_qbrc;
3184         stats->opackets = hw_stats->gptc;
3185         stats->obytes = hw_stats->gotc;
3186
3187         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3188                 stats->q_ipackets[i] = hw_stats->qprc[i];
3189                 stats->q_opackets[i] = hw_stats->qptc[i];
3190                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3191                 stats->q_obytes[i] = hw_stats->qbtc[i];
3192                 stats->q_errors[i] = hw_stats->qprdc[i];
3193         }
3194
3195         /* Rx Errors */
3196         stats->imissed  = total_missed_rx;
3197         stats->ierrors  = hw_stats->crcerrs +
3198                           hw_stats->mspdc +
3199                           hw_stats->rlec +
3200                           hw_stats->ruc +
3201                           hw_stats->roc +
3202                           hw_stats->illerrc +
3203                           hw_stats->errbc +
3204                           hw_stats->rfc +
3205                           hw_stats->fccrc +
3206                           hw_stats->fclast;
3207
3208         /* Tx Errors */
3209         stats->oerrors  = 0;
3210         return 0;
3211 }
3212
3213 static void
3214 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3215 {
3216         struct ixgbe_hw_stats *stats =
3217                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3218
3219         /* HW registers are cleared on read */
3220         ixgbe_dev_stats_get(dev, NULL);
3221
3222         /* Reset software totals */
3223         memset(stats, 0, sizeof(*stats));
3224 }
3225
3226 /* This function calculates the number of xstats based on the current config */
3227 static unsigned
3228 ixgbe_xstats_calc_num(void) {
3229         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3230                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3231                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3232 }
3233
3234 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3235         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3236 {
3237         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3238         unsigned stat, i, count;
3239
3240         if (xstats_names != NULL) {
3241                 count = 0;
3242
3243                 /* Note: limit >= cnt_stats checked upstream
3244                  * in rte_eth_xstats_names()
3245                  */
3246
3247                 /* Extended stats from ixgbe_hw_stats */
3248                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3249                         snprintf(xstats_names[count].name,
3250                                 sizeof(xstats_names[count].name),
3251                                 "%s",
3252                                 rte_ixgbe_stats_strings[i].name);
3253                         count++;
3254                 }
3255
3256                 /* MACsec Stats */
3257                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3258                         snprintf(xstats_names[count].name,
3259                                 sizeof(xstats_names[count].name),
3260                                 "%s",
3261                                 rte_ixgbe_macsec_strings[i].name);
3262                         count++;
3263                 }
3264
3265                 /* RX Priority Stats */
3266                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3267                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3268                                 snprintf(xstats_names[count].name,
3269                                         sizeof(xstats_names[count].name),
3270                                         "rx_priority%u_%s", i,
3271                                         rte_ixgbe_rxq_strings[stat].name);
3272                                 count++;
3273                         }
3274                 }
3275
3276                 /* TX Priority Stats */
3277                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3278                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3279                                 snprintf(xstats_names[count].name,
3280                                         sizeof(xstats_names[count].name),
3281                                         "tx_priority%u_%s", i,
3282                                         rte_ixgbe_txq_strings[stat].name);
3283                                 count++;
3284                         }
3285                 }
3286         }
3287         return cnt_stats;
3288 }
3289
3290 static int ixgbe_dev_xstats_get_names_by_id(
3291         struct rte_eth_dev *dev,
3292         struct rte_eth_xstat_name *xstats_names,
3293         const uint64_t *ids,
3294         unsigned int limit)
3295 {
3296         if (!ids) {
3297                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3298                 unsigned int stat, i, count;
3299
3300                 if (xstats_names != NULL) {
3301                         count = 0;
3302
3303                         /* Note: limit >= cnt_stats checked upstream
3304                          * in rte_eth_xstats_names()
3305                          */
3306
3307                         /* Extended stats from ixgbe_hw_stats */
3308                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3309                                 snprintf(xstats_names[count].name,
3310                                         sizeof(xstats_names[count].name),
3311                                         "%s",
3312                                         rte_ixgbe_stats_strings[i].name);
3313                                 count++;
3314                         }
3315
3316                         /* MACsec Stats */
3317                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3318                                 snprintf(xstats_names[count].name,
3319                                         sizeof(xstats_names[count].name),
3320                                         "%s",
3321                                         rte_ixgbe_macsec_strings[i].name);
3322                                 count++;
3323                         }
3324
3325                         /* RX Priority Stats */
3326                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3327                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3328                                         snprintf(xstats_names[count].name,
3329                                             sizeof(xstats_names[count].name),
3330                                             "rx_priority%u_%s", i,
3331                                             rte_ixgbe_rxq_strings[stat].name);
3332                                         count++;
3333                                 }
3334                         }
3335
3336                         /* TX Priority Stats */
3337                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3338                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3339                                         snprintf(xstats_names[count].name,
3340                                             sizeof(xstats_names[count].name),
3341                                             "tx_priority%u_%s", i,
3342                                             rte_ixgbe_txq_strings[stat].name);
3343                                         count++;
3344                                 }
3345                         }
3346                 }
3347                 return cnt_stats;
3348         }
3349
3350         uint16_t i;
3351         uint16_t size = ixgbe_xstats_calc_num();
3352         struct rte_eth_xstat_name xstats_names_copy[size];
3353
3354         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3355                         size);
3356
3357         for (i = 0; i < limit; i++) {
3358                 if (ids[i] >= size) {
3359                         PMD_INIT_LOG(ERR, "id value isn't valid");
3360                         return -1;
3361                 }
3362                 strcpy(xstats_names[i].name,
3363                                 xstats_names_copy[ids[i]].name);
3364         }
3365         return limit;
3366 }
3367
3368 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3369         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3370 {
3371         unsigned i;
3372
3373         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3374                 return -ENOMEM;
3375
3376         if (xstats_names != NULL)
3377                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3378                         snprintf(xstats_names[i].name,
3379                                 sizeof(xstats_names[i].name),
3380                                 "%s", rte_ixgbevf_stats_strings[i].name);
3381         return IXGBEVF_NB_XSTATS;
3382 }
3383
3384 static int
3385 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3386                                          unsigned n)
3387 {
3388         struct ixgbe_hw *hw =
3389                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3390         struct ixgbe_hw_stats *hw_stats =
3391                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3392         struct ixgbe_macsec_stats *macsec_stats =
3393                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3394                                 dev->data->dev_private);
3395         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3396         unsigned i, stat, count = 0;
3397
3398         count = ixgbe_xstats_calc_num();
3399
3400         if (n < count)
3401                 return count;
3402
3403         total_missed_rx = 0;
3404         total_qbrc = 0;
3405         total_qprc = 0;
3406         total_qprdc = 0;
3407
3408         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3409                         &total_qbrc, &total_qprc, &total_qprdc);
3410
3411         /* If this is a reset xstats is NULL, and we have cleared the
3412          * registers by reading them.
3413          */
3414         if (!xstats)
3415                 return 0;
3416
3417         /* Extended stats from ixgbe_hw_stats */
3418         count = 0;
3419         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3420                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3421                                 rte_ixgbe_stats_strings[i].offset);
3422                 xstats[count].id = count;
3423                 count++;
3424         }
3425
3426         /* MACsec Stats */
3427         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3428                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3429                                 rte_ixgbe_macsec_strings[i].offset);
3430                 xstats[count].id = count;
3431                 count++;
3432         }
3433
3434         /* RX Priority Stats */
3435         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3436                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3437                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3438                                         rte_ixgbe_rxq_strings[stat].offset +
3439                                         (sizeof(uint64_t) * i));
3440                         xstats[count].id = count;
3441                         count++;
3442                 }
3443         }
3444
3445         /* TX Priority Stats */
3446         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3447                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3448                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3449                                         rte_ixgbe_txq_strings[stat].offset +
3450                                         (sizeof(uint64_t) * i));
3451                         xstats[count].id = count;
3452                         count++;
3453                 }
3454         }
3455         return count;
3456 }
3457
3458 static int
3459 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3460                 uint64_t *values, unsigned int n)
3461 {
3462         if (!ids) {
3463                 struct ixgbe_hw *hw =
3464                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3465                 struct ixgbe_hw_stats *hw_stats =
3466                                 IXGBE_DEV_PRIVATE_TO_STATS(
3467                                                 dev->data->dev_private);
3468                 struct ixgbe_macsec_stats *macsec_stats =
3469                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3470                                         dev->data->dev_private);
3471                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3472                 unsigned int i, stat, count = 0;
3473
3474                 count = ixgbe_xstats_calc_num();
3475
3476                 if (!ids && n < count)
3477                         return count;
3478
3479                 total_missed_rx = 0;
3480                 total_qbrc = 0;
3481                 total_qprc = 0;
3482                 total_qprdc = 0;
3483
3484                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3485                                 &total_missed_rx, &total_qbrc, &total_qprc,
3486                                 &total_qprdc);
3487
3488                 /* If this is a reset xstats is NULL, and we have cleared the
3489                  * registers by reading them.
3490                  */
3491                 if (!ids && !values)
3492                         return 0;
3493
3494                 /* Extended stats from ixgbe_hw_stats */
3495                 count = 0;
3496                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3497                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3498                                         rte_ixgbe_stats_strings[i].offset);
3499                         count++;
3500                 }
3501
3502                 /* MACsec Stats */
3503                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3504                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3505                                         rte_ixgbe_macsec_strings[i].offset);
3506                         count++;
3507                 }
3508
3509                 /* RX Priority Stats */
3510                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3511                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3512                                 values[count] =
3513                                         *(uint64_t *)(((char *)hw_stats) +
3514                                         rte_ixgbe_rxq_strings[stat].offset +
3515                                         (sizeof(uint64_t) * i));
3516                                 count++;
3517                         }
3518                 }
3519
3520                 /* TX Priority Stats */
3521                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3522                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3523                                 values[count] =
3524                                         *(uint64_t *)(((char *)hw_stats) +
3525                                         rte_ixgbe_txq_strings[stat].offset +
3526                                         (sizeof(uint64_t) * i));
3527                                 count++;
3528                         }
3529                 }
3530                 return count;
3531         }
3532
3533         uint16_t i;
3534         uint16_t size = ixgbe_xstats_calc_num();
3535         uint64_t values_copy[size];
3536
3537         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3538
3539         for (i = 0; i < n; i++) {
3540                 if (ids[i] >= size) {
3541                         PMD_INIT_LOG(ERR, "id value isn't valid");
3542                         return -1;
3543                 }
3544                 values[i] = values_copy[ids[i]];
3545         }
3546         return n;
3547 }
3548
3549 static void
3550 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3551 {
3552         struct ixgbe_hw_stats *stats =
3553                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3554         struct ixgbe_macsec_stats *macsec_stats =
3555                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3556                                 dev->data->dev_private);
3557
3558         unsigned count = ixgbe_xstats_calc_num();
3559
3560         /* HW registers are cleared on read */
3561         ixgbe_dev_xstats_get(dev, NULL, count);
3562
3563         /* Reset software totals */
3564         memset(stats, 0, sizeof(*stats));
3565         memset(macsec_stats, 0, sizeof(*macsec_stats));
3566 }
3567
3568 static void
3569 ixgbevf_update_stats(struct rte_eth_dev *dev)
3570 {
3571         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3573                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3574
3575         /* Good Rx packet, include VF loopback */
3576         UPDATE_VF_STAT(IXGBE_VFGPRC,
3577             hw_stats->last_vfgprc, hw_stats->vfgprc);
3578
3579         /* Good Rx octets, include VF loopback */
3580         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3581             hw_stats->last_vfgorc, hw_stats->vfgorc);
3582
3583         /* Good Tx packet, include VF loopback */
3584         UPDATE_VF_STAT(IXGBE_VFGPTC,
3585             hw_stats->last_vfgptc, hw_stats->vfgptc);
3586
3587         /* Good Tx octets, include VF loopback */
3588         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3589             hw_stats->last_vfgotc, hw_stats->vfgotc);
3590
3591         /* Rx Multicst Packet */
3592         UPDATE_VF_STAT(IXGBE_VFMPRC,
3593             hw_stats->last_vfmprc, hw_stats->vfmprc);
3594 }
3595
3596 static int
3597 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3598                        unsigned n)
3599 {
3600         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3601                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3602         unsigned i;
3603
3604         if (n < IXGBEVF_NB_XSTATS)
3605                 return IXGBEVF_NB_XSTATS;
3606
3607         ixgbevf_update_stats(dev);
3608
3609         if (!xstats)
3610                 return 0;
3611
3612         /* Extended stats */
3613         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3614                 xstats[i].id = i;
3615                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3616                         rte_ixgbevf_stats_strings[i].offset);
3617         }
3618
3619         return IXGBEVF_NB_XSTATS;
3620 }
3621
3622 static int
3623 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3624 {
3625         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3626                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3627
3628         ixgbevf_update_stats(dev);
3629
3630         if (stats == NULL)
3631                 return -EINVAL;
3632
3633         stats->ipackets = hw_stats->vfgprc;
3634         stats->ibytes = hw_stats->vfgorc;
3635         stats->opackets = hw_stats->vfgptc;
3636         stats->obytes = hw_stats->vfgotc;
3637         return 0;
3638 }
3639
3640 static void
3641 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3642 {
3643         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3644                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3645
3646         /* Sync HW register to the last stats */
3647         ixgbevf_dev_stats_get(dev, NULL);
3648
3649         /* reset HW current stats*/
3650         hw_stats->vfgprc = 0;
3651         hw_stats->vfgorc = 0;
3652         hw_stats->vfgptc = 0;
3653         hw_stats->vfgotc = 0;
3654 }
3655
3656 static int
3657 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3658 {
3659         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3660         u16 eeprom_verh, eeprom_verl;
3661         u32 etrack_id;
3662         int ret;
3663
3664         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3665         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3666
3667         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3668         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3669
3670         ret += 1; /* add the size of '\0' */
3671         if (fw_size < (u32)ret)
3672                 return ret;
3673         else
3674                 return 0;
3675 }
3676
3677 static void
3678 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3679 {
3680         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3683
3684         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3685         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3686         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3687                 /*
3688                  * When DCB/VT is off, maximum number of queues changes,
3689                  * except for 82598EB, which remains constant.
3690                  */
3691                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3692                                 hw->mac.type != ixgbe_mac_82598EB)
3693                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3694         }
3695         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3696         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3697         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3698         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3699         dev_info->max_vfs = pci_dev->max_vfs;
3700         if (hw->mac.type == ixgbe_mac_82598EB)
3701                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3702         else
3703                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3704         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3705         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3706         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3707                                      dev_info->rx_queue_offload_capa);
3708         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3709         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3710
3711         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3712                 .rx_thresh = {
3713                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3714                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3715                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3716                 },
3717                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3718                 .rx_drop_en = 0,
3719                 .offloads = 0,
3720         };
3721
3722         dev_info->default_txconf = (struct rte_eth_txconf) {
3723                 .tx_thresh = {
3724                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3725                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3726                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3727                 },
3728                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3729                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3730                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3731                              ETH_TXQ_FLAGS_NOOFFLOADS |
3732                              ETH_TXQ_FLAGS_IGNORE,
3733                 .offloads = 0,
3734         };
3735
3736         dev_info->rx_desc_lim = rx_desc_lim;
3737         dev_info->tx_desc_lim = tx_desc_lim;
3738
3739         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3740         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3741         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3742
3743         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3744         if (hw->mac.type == ixgbe_mac_X540 ||
3745             hw->mac.type == ixgbe_mac_X540_vf ||
3746             hw->mac.type == ixgbe_mac_X550 ||
3747             hw->mac.type == ixgbe_mac_X550_vf) {
3748                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3749         }
3750         if (hw->mac.type == ixgbe_mac_X550) {
3751                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3752                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3753         }
3754 }
3755
3756 static const uint32_t *
3757 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3758 {
3759         static const uint32_t ptypes[] = {
3760                 /* For non-vec functions,
3761                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3762                  * for vec functions,
3763                  * refers to _recv_raw_pkts_vec().
3764                  */
3765                 RTE_PTYPE_L2_ETHER,
3766                 RTE_PTYPE_L3_IPV4,
3767                 RTE_PTYPE_L3_IPV4_EXT,
3768                 RTE_PTYPE_L3_IPV6,
3769                 RTE_PTYPE_L3_IPV6_EXT,
3770                 RTE_PTYPE_L4_SCTP,
3771                 RTE_PTYPE_L4_TCP,
3772                 RTE_PTYPE_L4_UDP,
3773                 RTE_PTYPE_TUNNEL_IP,
3774                 RTE_PTYPE_INNER_L3_IPV6,
3775                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3776                 RTE_PTYPE_INNER_L4_TCP,
3777                 RTE_PTYPE_INNER_L4_UDP,
3778                 RTE_PTYPE_UNKNOWN
3779         };
3780
3781         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3782             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3783             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3784             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3785                 return ptypes;
3786
3787 #if defined(RTE_ARCH_X86)
3788         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3789             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3790                 return ptypes;
3791 #endif
3792         return NULL;
3793 }
3794
3795 static void
3796 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3797                      struct rte_eth_dev_info *dev_info)
3798 {
3799         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3801
3802         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3803         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3804         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3805         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3806         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3807         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3808         dev_info->max_vfs = pci_dev->max_vfs;
3809         if (hw->mac.type == ixgbe_mac_82598EB)
3810                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3811         else
3812                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3813         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3814         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3815                                      dev_info->rx_queue_offload_capa);
3816         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3817         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3818
3819         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3820                 .rx_thresh = {
3821                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3822                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3823                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3824                 },
3825                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3826                 .rx_drop_en = 0,
3827                 .offloads = 0,
3828         };
3829
3830         dev_info->default_txconf = (struct rte_eth_txconf) {
3831                 .tx_thresh = {
3832                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3833                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3834                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3835                 },
3836                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3837                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3838                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3839                              ETH_TXQ_FLAGS_NOOFFLOADS |
3840                              ETH_TXQ_FLAGS_IGNORE,
3841                 .offloads = 0,
3842         };
3843
3844         dev_info->rx_desc_lim = rx_desc_lim;
3845         dev_info->tx_desc_lim = tx_desc_lim;
3846 }
3847
3848 static int
3849 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3850                    int *link_up, int wait_to_complete)
3851 {
3852         /**
3853          * for a quick link status checking, wait_to_compelet == 0,
3854          * skip PF link status checking
3855          */
3856         bool no_pflink_check = wait_to_complete == 0;
3857         struct ixgbe_mbx_info *mbx = &hw->mbx;
3858         struct ixgbe_mac_info *mac = &hw->mac;
3859         uint32_t links_reg, in_msg;
3860         int ret_val = 0;
3861
3862         /* If we were hit with a reset drop the link */
3863         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3864                 mac->get_link_status = true;
3865
3866         if (!mac->get_link_status)
3867                 goto out;
3868
3869         /* if link status is down no point in checking to see if pf is up */
3870         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3871         if (!(links_reg & IXGBE_LINKS_UP))
3872                 goto out;
3873
3874         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3875          * before the link status is correct
3876          */
3877         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3878                 int i;
3879
3880                 for (i = 0; i < 5; i++) {
3881                         rte_delay_us(100);
3882                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3883
3884                         if (!(links_reg & IXGBE_LINKS_UP))
3885                                 goto out;
3886                 }
3887         }
3888
3889         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3890         case IXGBE_LINKS_SPEED_10G_82599:
3891                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3892                 if (hw->mac.type >= ixgbe_mac_X550) {
3893                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3894                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3895                 }
3896                 break;
3897         case IXGBE_LINKS_SPEED_1G_82599:
3898                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3899                 break;
3900         case IXGBE_LINKS_SPEED_100_82599:
3901                 *speed = IXGBE_LINK_SPEED_100_FULL;
3902                 if (hw->mac.type == ixgbe_mac_X550) {
3903                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3904                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3905                 }
3906                 break;
3907         case IXGBE_LINKS_SPEED_10_X550EM_A:
3908                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3909                 /* Since Reserved in older MAC's */
3910                 if (hw->mac.type >= ixgbe_mac_X550)
3911                         *speed = IXGBE_LINK_SPEED_10_FULL;
3912                 break;
3913         default:
3914                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3915         }
3916
3917         if (no_pflink_check) {
3918                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3919                         mac->get_link_status = true;
3920                 else
3921                         mac->get_link_status = false;
3922
3923                 goto out;
3924         }
3925         /* if the read failed it could just be a mailbox collision, best wait
3926          * until we are called again and don't report an error
3927          */
3928         if (mbx->ops.read(hw, &in_msg, 1, 0))
3929                 goto out;
3930
3931         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3932                 /* msg is not CTS and is NACK we must have lost CTS status */
3933                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3934                         ret_val = -1;
3935                 goto out;
3936         }
3937
3938         /* the pf is talking, if we timed out in the past we reinit */
3939         if (!mbx->timeout) {
3940                 ret_val = -1;
3941                 goto out;
3942         }
3943
3944         /* if we passed all the tests above then the link is up and we no
3945          * longer need to check for link
3946          */
3947         mac->get_link_status = false;
3948
3949 out:
3950         *link_up = !mac->get_link_status;
3951         return ret_val;
3952 }
3953
3954 /* return 0 means link status changed, -1 means not changed */
3955 int
3956 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3957                             int wait_to_complete, int vf)
3958 {
3959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3960         struct rte_eth_link link;
3961         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3962         struct ixgbe_interrupt *intr =
3963                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3964         int link_up;
3965         int diag;
3966         u32 speed = 0;
3967         int wait = 1;
3968         bool autoneg = false;
3969
3970         memset(&link, 0, sizeof(link));
3971         link.link_status = ETH_LINK_DOWN;
3972         link.link_speed = ETH_SPEED_NUM_NONE;
3973         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3974         link.link_autoneg = ETH_LINK_AUTONEG;
3975
3976         hw->mac.get_link_status = true;
3977
3978         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3979                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3980                 speed = hw->phy.autoneg_advertised;
3981                 if (!speed)
3982                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3983                 ixgbe_setup_link(hw, speed, true);
3984         }
3985
3986         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3987         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3988                 wait = 0;
3989
3990         if (vf)
3991                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3992         else
3993                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3994
3995         if (diag != 0) {
3996                 link.link_speed = ETH_SPEED_NUM_100M;
3997                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3998                 return rte_eth_linkstatus_set(dev, &link);
3999         }
4000
4001         if (link_up == 0) {
4002                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4003                 return rte_eth_linkstatus_set(dev, &link);
4004         }
4005
4006         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4007         link.link_status = ETH_LINK_UP;
4008         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4009
4010         switch (link_speed) {
4011         default:
4012         case IXGBE_LINK_SPEED_UNKNOWN:
4013                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4014                 link.link_speed = ETH_SPEED_NUM_100M;
4015                 break;
4016
4017         case IXGBE_LINK_SPEED_100_FULL:
4018                 link.link_speed = ETH_SPEED_NUM_100M;
4019                 break;
4020
4021         case IXGBE_LINK_SPEED_1GB_FULL:
4022                 link.link_speed = ETH_SPEED_NUM_1G;
4023                 break;
4024
4025         case IXGBE_LINK_SPEED_2_5GB_FULL:
4026                 link.link_speed = ETH_SPEED_NUM_2_5G;
4027                 break;
4028
4029         case IXGBE_LINK_SPEED_5GB_FULL:
4030                 link.link_speed = ETH_SPEED_NUM_5G;
4031                 break;
4032
4033         case IXGBE_LINK_SPEED_10GB_FULL:
4034                 link.link_speed = ETH_SPEED_NUM_10G;
4035                 break;
4036         }
4037
4038         return rte_eth_linkstatus_set(dev, &link);
4039 }
4040
4041 static int
4042 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4043 {
4044         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4045 }
4046
4047 static int
4048 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4049 {
4050         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4051 }
4052
4053 static void
4054 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4055 {
4056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4057         uint32_t fctrl;
4058
4059         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4060         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4061         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4062 }
4063
4064 static void
4065 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4066 {
4067         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4068         uint32_t fctrl;
4069
4070         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4071         fctrl &= (~IXGBE_FCTRL_UPE);
4072         if (dev->data->all_multicast == 1)
4073                 fctrl |= IXGBE_FCTRL_MPE;
4074         else
4075                 fctrl &= (~IXGBE_FCTRL_MPE);
4076         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4077 }
4078
4079 static void
4080 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4081 {
4082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4083         uint32_t fctrl;
4084
4085         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4086         fctrl |= IXGBE_FCTRL_MPE;
4087         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4088 }
4089
4090 static void
4091 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4092 {
4093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4094         uint32_t fctrl;
4095
4096         if (dev->data->promiscuous == 1)
4097                 return; /* must remain in all_multicast mode */
4098
4099         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4100         fctrl &= (~IXGBE_FCTRL_MPE);
4101         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4102 }
4103
4104 /**
4105  * It clears the interrupt causes and enables the interrupt.
4106  * It will be called once only during nic initialized.
4107  *
4108  * @param dev
4109  *  Pointer to struct rte_eth_dev.
4110  * @param on
4111  *  Enable or Disable.
4112  *
4113  * @return
4114  *  - On success, zero.
4115  *  - On failure, a negative value.
4116  */
4117 static int
4118 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4119 {
4120         struct ixgbe_interrupt *intr =
4121                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4122
4123         ixgbe_dev_link_status_print(dev);
4124         if (on)
4125                 intr->mask |= IXGBE_EICR_LSC;
4126         else
4127                 intr->mask &= ~IXGBE_EICR_LSC;
4128
4129         return 0;
4130 }
4131
4132 /**
4133  * It clears the interrupt causes and enables the interrupt.
4134  * It will be called once only during nic initialized.
4135  *
4136  * @param dev
4137  *  Pointer to struct rte_eth_dev.
4138  *
4139  * @return
4140  *  - On success, zero.
4141  *  - On failure, a negative value.
4142  */
4143 static int
4144 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4145 {
4146         struct ixgbe_interrupt *intr =
4147                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4148
4149         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4150
4151         return 0;
4152 }
4153
4154 /**
4155  * It clears the interrupt causes and enables the interrupt.
4156  * It will be called once only during nic initialized.
4157  *
4158  * @param dev
4159  *  Pointer to struct rte_eth_dev.
4160  *
4161  * @return
4162  *  - On success, zero.
4163  *  - On failure, a negative value.
4164  */
4165 static int
4166 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4167 {
4168         struct ixgbe_interrupt *intr =
4169                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4170
4171         intr->mask |= IXGBE_EICR_LINKSEC;
4172
4173         return 0;
4174 }
4175
4176 /*
4177  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4178  *
4179  * @param dev
4180  *  Pointer to struct rte_eth_dev.
4181  *
4182  * @return
4183  *  - On success, zero.
4184  *  - On failure, a negative value.
4185  */
4186 static int
4187 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4188 {
4189         uint32_t eicr;
4190         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4191         struct ixgbe_interrupt *intr =
4192                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4193
4194         /* clear all cause mask */
4195         ixgbe_disable_intr(hw);
4196
4197         /* read-on-clear nic registers here */
4198         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4199         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4200
4201         intr->flags = 0;
4202
4203         /* set flag for async link update */
4204         if (eicr & IXGBE_EICR_LSC)
4205                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4206
4207         if (eicr & IXGBE_EICR_MAILBOX)
4208                 intr->flags |= IXGBE_FLAG_MAILBOX;
4209
4210         if (eicr & IXGBE_EICR_LINKSEC)
4211                 intr->flags |= IXGBE_FLAG_MACSEC;
4212
4213         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4214             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4215             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4216                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4217
4218         return 0;
4219 }
4220
4221 /**
4222  * It gets and then prints the link status.
4223  *
4224  * @param dev
4225  *  Pointer to struct rte_eth_dev.
4226  *
4227  * @return
4228  *  - On success, zero.
4229  *  - On failure, a negative value.
4230  */
4231 static void
4232 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4233 {
4234         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4235         struct rte_eth_link link;
4236
4237         rte_eth_linkstatus_get(dev, &link);
4238
4239         if (link.link_status) {
4240                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4241                                         (int)(dev->data->port_id),
4242                                         (unsigned)link.link_speed,
4243                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4244                                         "full-duplex" : "half-duplex");
4245         } else {
4246                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4247                                 (int)(dev->data->port_id));
4248         }
4249         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4250                                 pci_dev->addr.domain,
4251                                 pci_dev->addr.bus,
4252                                 pci_dev->addr.devid,
4253                                 pci_dev->addr.function);
4254 }
4255
4256 /*
4257  * It executes link_update after knowing an interrupt occurred.
4258  *
4259  * @param dev
4260  *  Pointer to struct rte_eth_dev.
4261  *
4262  * @return
4263  *  - On success, zero.
4264  *  - On failure, a negative value.
4265  */
4266 static int
4267 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4268                            struct rte_intr_handle *intr_handle)
4269 {
4270         struct ixgbe_interrupt *intr =
4271                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4272         int64_t timeout;
4273         struct ixgbe_hw *hw =
4274                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4275
4276         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4277
4278         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4279                 ixgbe_pf_mbx_process(dev);
4280                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4281         }
4282
4283         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4284                 ixgbe_handle_lasi(hw);
4285                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4286         }
4287
4288         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4289                 struct rte_eth_link link;
4290
4291                 /* get the link status before link update, for predicting later */
4292                 rte_eth_linkstatus_get(dev, &link);
4293
4294                 ixgbe_dev_link_update(dev, 0);
4295
4296                 /* likely to up */
4297                 if (!link.link_status)
4298                         /* handle it 1 sec later, wait it being stable */
4299                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4300                 /* likely to down */
4301                 else
4302                         /* handle it 4 sec later, wait it being stable */
4303                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4304
4305                 ixgbe_dev_link_status_print(dev);
4306                 if (rte_eal_alarm_set(timeout * 1000,
4307                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4308                         PMD_DRV_LOG(ERR, "Error setting alarm");
4309                 else {
4310                         /* remember original mask */
4311                         intr->mask_original = intr->mask;
4312                         /* only disable lsc interrupt */
4313                         intr->mask &= ~IXGBE_EIMS_LSC;
4314                 }
4315         }
4316
4317         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4318         ixgbe_enable_intr(dev);
4319         rte_intr_enable(intr_handle);
4320
4321         return 0;
4322 }
4323
4324 /**
4325  * Interrupt handler which shall be registered for alarm callback for delayed
4326  * handling specific interrupt to wait for the stable nic state. As the
4327  * NIC interrupt state is not stable for ixgbe after link is just down,
4328  * it needs to wait 4 seconds to get the stable status.
4329  *
4330  * @param handle
4331  *  Pointer to interrupt handle.
4332  * @param param
4333  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4334  *
4335  * @return
4336  *  void
4337  */
4338 static void
4339 ixgbe_dev_interrupt_delayed_handler(void *param)
4340 {
4341         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4342         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4343         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4344         struct ixgbe_interrupt *intr =
4345                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4346         struct ixgbe_hw *hw =
4347                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4348         uint32_t eicr;
4349
4350         ixgbe_disable_intr(hw);
4351
4352         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4353         if (eicr & IXGBE_EICR_MAILBOX)
4354                 ixgbe_pf_mbx_process(dev);
4355
4356         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4357                 ixgbe_handle_lasi(hw);
4358                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4359         }
4360
4361         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4362                 ixgbe_dev_link_update(dev, 0);
4363                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4364                 ixgbe_dev_link_status_print(dev);
4365                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4366                                               NULL);
4367         }
4368
4369         if (intr->flags & IXGBE_FLAG_MACSEC) {
4370                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4371                                               NULL);
4372                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4373         }
4374
4375         /* restore original mask */
4376         intr->mask = intr->mask_original;
4377         intr->mask_original = 0;
4378
4379         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4380         ixgbe_enable_intr(dev);
4381         rte_intr_enable(intr_handle);
4382 }
4383
4384 /**
4385  * Interrupt handler triggered by NIC  for handling
4386  * specific interrupt.
4387  *
4388  * @param handle
4389  *  Pointer to interrupt handle.
4390  * @param param
4391  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4392  *
4393  * @return
4394  *  void
4395  */
4396 static void
4397 ixgbe_dev_interrupt_handler(void *param)
4398 {
4399         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4400
4401         ixgbe_dev_interrupt_get_status(dev);
4402         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4403 }
4404
4405 static int
4406 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4407 {
4408         struct ixgbe_hw *hw;
4409
4410         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4411         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4412 }
4413
4414 static int
4415 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4416 {
4417         struct ixgbe_hw *hw;
4418
4419         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4420         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4421 }
4422
4423 static int
4424 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4425 {
4426         struct ixgbe_hw *hw;
4427         uint32_t mflcn_reg;
4428         uint32_t fccfg_reg;
4429         int rx_pause;
4430         int tx_pause;
4431
4432         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4433
4434         fc_conf->pause_time = hw->fc.pause_time;
4435         fc_conf->high_water = hw->fc.high_water[0];
4436         fc_conf->low_water = hw->fc.low_water[0];
4437         fc_conf->send_xon = hw->fc.send_xon;
4438         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4439
4440         /*
4441          * Return rx_pause status according to actual setting of
4442          * MFLCN register.
4443          */
4444         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4445         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4446                 rx_pause = 1;
4447         else
4448                 rx_pause = 0;
4449
4450         /*
4451          * Return tx_pause status according to actual setting of
4452          * FCCFG register.
4453          */
4454         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4455         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4456                 tx_pause = 1;
4457         else
4458                 tx_pause = 0;
4459
4460         if (rx_pause && tx_pause)
4461                 fc_conf->mode = RTE_FC_FULL;
4462         else if (rx_pause)
4463                 fc_conf->mode = RTE_FC_RX_PAUSE;
4464         else if (tx_pause)
4465                 fc_conf->mode = RTE_FC_TX_PAUSE;
4466         else
4467                 fc_conf->mode = RTE_FC_NONE;
4468
4469         return 0;
4470 }
4471
4472 static int
4473 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4474 {
4475         struct ixgbe_hw *hw;
4476         int err;
4477         uint32_t rx_buf_size;
4478         uint32_t max_high_water;
4479         uint32_t mflcn;
4480         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4481                 ixgbe_fc_none,
4482                 ixgbe_fc_rx_pause,
4483                 ixgbe_fc_tx_pause,
4484                 ixgbe_fc_full
4485         };
4486
4487         PMD_INIT_FUNC_TRACE();
4488
4489         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4490         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4491         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4492
4493         /*
4494          * At least reserve one Ethernet frame for watermark
4495          * high_water/low_water in kilo bytes for ixgbe
4496          */
4497         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4498         if ((fc_conf->high_water > max_high_water) ||
4499                 (fc_conf->high_water < fc_conf->low_water)) {
4500                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4501                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4502                 return -EINVAL;
4503         }
4504
4505         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4506         hw->fc.pause_time     = fc_conf->pause_time;
4507         hw->fc.high_water[0]  = fc_conf->high_water;
4508         hw->fc.low_water[0]   = fc_conf->low_water;
4509         hw->fc.send_xon       = fc_conf->send_xon;
4510         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4511
4512         err = ixgbe_fc_enable(hw);
4513
4514         /* Not negotiated is not an error case */
4515         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4516
4517                 /* check if we want to forward MAC frames - driver doesn't have native
4518                  * capability to do that, so we'll write the registers ourselves */
4519
4520                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4521
4522                 /* set or clear MFLCN.PMCF bit depending on configuration */
4523                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4524                         mflcn |= IXGBE_MFLCN_PMCF;
4525                 else
4526                         mflcn &= ~IXGBE_MFLCN_PMCF;
4527
4528                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4529                 IXGBE_WRITE_FLUSH(hw);
4530
4531                 return 0;
4532         }
4533
4534         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4535         return -EIO;
4536 }
4537
4538 /**
4539  *  ixgbe_pfc_enable_generic - Enable flow control
4540  *  @hw: pointer to hardware structure
4541  *  @tc_num: traffic class number
4542  *  Enable flow control according to the current settings.
4543  */
4544 static int
4545 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4546 {
4547         int ret_val = 0;
4548         uint32_t mflcn_reg, fccfg_reg;
4549         uint32_t reg;
4550         uint32_t fcrtl, fcrth;
4551         uint8_t i;
4552         uint8_t nb_rx_en;
4553
4554         /* Validate the water mark configuration */
4555         if (!hw->fc.pause_time) {
4556                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4557                 goto out;
4558         }
4559
4560         /* Low water mark of zero causes XOFF floods */
4561         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4562                  /* High/Low water can not be 0 */
4563                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4564                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4565                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4566                         goto out;
4567                 }
4568
4569                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4570                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4571                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4572                         goto out;
4573                 }
4574         }
4575         /* Negotiate the fc mode to use */
4576         ixgbe_fc_autoneg(hw);
4577
4578         /* Disable any previous flow control settings */
4579         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4580         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4581
4582         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4583         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4584
4585         switch (hw->fc.current_mode) {
4586         case ixgbe_fc_none:
4587                 /*
4588                  * If the count of enabled RX Priority Flow control >1,
4589                  * and the TX pause can not be disabled
4590                  */
4591                 nb_rx_en = 0;
4592                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4593                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4594                         if (reg & IXGBE_FCRTH_FCEN)
4595                                 nb_rx_en++;
4596                 }
4597                 if (nb_rx_en > 1)
4598                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4599                 break;
4600         case ixgbe_fc_rx_pause:
4601                 /*
4602                  * Rx Flow control is enabled and Tx Flow control is
4603                  * disabled by software override. Since there really
4604                  * isn't a way to advertise that we are capable of RX
4605                  * Pause ONLY, we will advertise that we support both
4606                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4607                  * disable the adapter's ability to send PAUSE frames.
4608                  */
4609                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4610                 /*
4611                  * If the count of enabled RX Priority Flow control >1,
4612                  * and the TX pause can not be disabled
4613                  */
4614                 nb_rx_en = 0;
4615                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4616                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4617                         if (reg & IXGBE_FCRTH_FCEN)
4618                                 nb_rx_en++;
4619                 }
4620                 if (nb_rx_en > 1)
4621                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4622                 break;
4623         case ixgbe_fc_tx_pause:
4624                 /*
4625                  * Tx Flow control is enabled, and Rx Flow control is
4626                  * disabled by software override.
4627                  */
4628                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4629                 break;
4630         case ixgbe_fc_full:
4631                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4632                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4633                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4634                 break;
4635         default:
4636                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4637                 ret_val = IXGBE_ERR_CONFIG;
4638                 goto out;
4639         }
4640
4641         /* Set 802.3x based flow control settings. */
4642         mflcn_reg |= IXGBE_MFLCN_DPF;
4643         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4644         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4645
4646         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4647         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4648                 hw->fc.high_water[tc_num]) {
4649                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4650                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4651                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4652         } else {
4653                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4654                 /*
4655                  * In order to prevent Tx hangs when the internal Tx
4656                  * switch is enabled we must set the high water mark
4657                  * to the maximum FCRTH value.  This allows the Tx
4658                  * switch to function even under heavy Rx workloads.
4659                  */
4660                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4661         }
4662         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4663
4664         /* Configure pause time (2 TCs per register) */
4665         reg = hw->fc.pause_time * 0x00010001;
4666         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4667                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4668
4669         /* Configure flow control refresh threshold value */
4670         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4671
4672 out:
4673         return ret_val;
4674 }
4675
4676 static int
4677 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4678 {
4679         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4680         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4681
4682         if (hw->mac.type != ixgbe_mac_82598EB) {
4683                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4684         }
4685         return ret_val;
4686 }
4687
4688 static int
4689 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4690 {
4691         int err;
4692         uint32_t rx_buf_size;
4693         uint32_t max_high_water;
4694         uint8_t tc_num;
4695         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4696         struct ixgbe_hw *hw =
4697                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4698         struct ixgbe_dcb_config *dcb_config =
4699                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4700
4701         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4702                 ixgbe_fc_none,
4703                 ixgbe_fc_rx_pause,
4704                 ixgbe_fc_tx_pause,
4705                 ixgbe_fc_full
4706         };
4707
4708         PMD_INIT_FUNC_TRACE();
4709
4710         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4711         tc_num = map[pfc_conf->priority];
4712         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4713         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4714         /*
4715          * At least reserve one Ethernet frame for watermark
4716          * high_water/low_water in kilo bytes for ixgbe
4717          */
4718         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4719         if ((pfc_conf->fc.high_water > max_high_water) ||
4720             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4721                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4722                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4723                 return -EINVAL;
4724         }
4725
4726         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4727         hw->fc.pause_time = pfc_conf->fc.pause_time;
4728         hw->fc.send_xon = pfc_conf->fc.send_xon;
4729         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4730         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4731
4732         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4733
4734         /* Not negotiated is not an error case */
4735         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4736                 return 0;
4737
4738         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4739         return -EIO;
4740 }
4741
4742 static int
4743 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4744                           struct rte_eth_rss_reta_entry64 *reta_conf,
4745                           uint16_t reta_size)
4746 {
4747         uint16_t i, sp_reta_size;
4748         uint8_t j, mask;
4749         uint32_t reta, r;
4750         uint16_t idx, shift;
4751         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4752         uint32_t reta_reg;
4753
4754         PMD_INIT_FUNC_TRACE();
4755
4756         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4757                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4758                         "NIC.");
4759                 return -ENOTSUP;
4760         }
4761
4762         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4763         if (reta_size != sp_reta_size) {
4764                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4765                         "(%d) doesn't match the number hardware can supported "
4766                         "(%d)", reta_size, sp_reta_size);
4767                 return -EINVAL;
4768         }
4769
4770         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4771                 idx = i / RTE_RETA_GROUP_SIZE;
4772                 shift = i % RTE_RETA_GROUP_SIZE;
4773                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4774                                                 IXGBE_4_BIT_MASK);
4775                 if (!mask)
4776                         continue;
4777                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4778                 if (mask == IXGBE_4_BIT_MASK)
4779                         r = 0;
4780                 else
4781                         r = IXGBE_READ_REG(hw, reta_reg);
4782                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4783                         if (mask & (0x1 << j))
4784                                 reta |= reta_conf[idx].reta[shift + j] <<
4785                                                         (CHAR_BIT * j);
4786                         else
4787                                 reta |= r & (IXGBE_8_BIT_MASK <<
4788                                                 (CHAR_BIT * j));
4789                 }
4790                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4791         }
4792
4793         return 0;
4794 }
4795
4796 static int
4797 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4798                          struct rte_eth_rss_reta_entry64 *reta_conf,
4799                          uint16_t reta_size)
4800 {
4801         uint16_t i, sp_reta_size;
4802         uint8_t j, mask;
4803         uint32_t reta;
4804         uint16_t idx, shift;
4805         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4806         uint32_t reta_reg;
4807
4808         PMD_INIT_FUNC_TRACE();
4809         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4810         if (reta_size != sp_reta_size) {
4811                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4812                         "(%d) doesn't match the number hardware can supported "
4813                         "(%d)", reta_size, sp_reta_size);
4814                 return -EINVAL;
4815         }
4816
4817         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4818                 idx = i / RTE_RETA_GROUP_SIZE;
4819                 shift = i % RTE_RETA_GROUP_SIZE;
4820                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4821                                                 IXGBE_4_BIT_MASK);
4822                 if (!mask)
4823                         continue;
4824
4825                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4826                 reta = IXGBE_READ_REG(hw, reta_reg);
4827                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4828                         if (mask & (0x1 << j))
4829                                 reta_conf[idx].reta[shift + j] =
4830                                         ((reta >> (CHAR_BIT * j)) &
4831                                                 IXGBE_8_BIT_MASK);
4832                 }
4833         }
4834
4835         return 0;
4836 }
4837
4838 static int
4839 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4840                                 uint32_t index, uint32_t pool)
4841 {
4842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4843         uint32_t enable_addr = 1;
4844
4845         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4846                              pool, enable_addr);
4847 }
4848
4849 static void
4850 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4851 {
4852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4853
4854         ixgbe_clear_rar(hw, index);
4855 }
4856
4857 static int
4858 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4859 {
4860         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4861
4862         ixgbe_remove_rar(dev, 0);
4863         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4864
4865         return 0;
4866 }
4867
4868 static bool
4869 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4870 {
4871         if (strcmp(dev->device->driver->name, drv->driver.name))
4872                 return false;
4873
4874         return true;
4875 }
4876
4877 bool
4878 is_ixgbe_supported(struct rte_eth_dev *dev)
4879 {
4880         return is_device_supported(dev, &rte_ixgbe_pmd);
4881 }
4882
4883 static int
4884 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4885 {
4886         uint32_t hlreg0;
4887         uint32_t maxfrs;
4888         struct ixgbe_hw *hw;
4889         struct rte_eth_dev_info dev_info;
4890         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4891         struct rte_eth_dev_data *dev_data = dev->data;
4892
4893         ixgbe_dev_info_get(dev, &dev_info);
4894
4895         /* check that mtu is within the allowed range */
4896         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4897                 return -EINVAL;
4898
4899         /* If device is started, refuse mtu that requires the support of
4900          * scattered packets when this feature has not been enabled before.
4901          */
4902         if (dev_data->dev_started && !dev_data->scattered_rx &&
4903             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4904              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4905                 PMD_INIT_LOG(ERR, "Stop port first.");
4906                 return -EINVAL;
4907         }
4908
4909         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4910         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4911
4912         /* switch to jumbo mode if needed */
4913         if (frame_size > ETHER_MAX_LEN) {
4914                 dev->data->dev_conf.rxmode.offloads |=
4915                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4916                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4917         } else {
4918                 dev->data->dev_conf.rxmode.offloads &=
4919                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4920                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4921         }
4922         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4923
4924         /* update max frame size */
4925         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4926
4927         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4928         maxfrs &= 0x0000FFFF;
4929         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4930         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4931
4932         return 0;
4933 }
4934
4935 /*
4936  * Virtual Function operations
4937  */
4938 static void
4939 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4940 {
4941         PMD_INIT_FUNC_TRACE();
4942
4943         /* Clear interrupt mask to stop from interrupts being generated */
4944         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4945
4946         IXGBE_WRITE_FLUSH(hw);
4947 }
4948
4949 static void
4950 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4951 {
4952         PMD_INIT_FUNC_TRACE();
4953
4954         /* VF enable interrupt autoclean */
4955         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4956         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4957         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4958
4959         IXGBE_WRITE_FLUSH(hw);
4960 }
4961
4962 static int
4963 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4964 {
4965         struct rte_eth_conf *conf = &dev->data->dev_conf;
4966         struct ixgbe_adapter *adapter =
4967                         (struct ixgbe_adapter *)dev->data->dev_private;
4968         struct rte_eth_dev_info dev_info;
4969         uint64_t rx_offloads;
4970         uint64_t tx_offloads;
4971
4972         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4973                      dev->data->port_id);
4974
4975         ixgbevf_dev_info_get(dev, &dev_info);
4976         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4977         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4978                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4979                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4980                             rx_offloads, dev_info.rx_offload_capa);
4981                 return -ENOTSUP;
4982         }
4983         tx_offloads = dev->data->dev_conf.txmode.offloads;
4984         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4985                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4986                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4987                             tx_offloads, dev_info.tx_offload_capa);
4988                 return -ENOTSUP;
4989         }
4990
4991         /*
4992          * VF has no ability to enable/disable HW CRC
4993          * Keep the persistent behavior the same as Host PF
4994          */
4995 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4996         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4997                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4998                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4999         }
5000 #else
5001         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
5002                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5003                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
5004         }
5005 #endif
5006
5007         /*
5008          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5009          * allocation or vector Rx preconditions we will reset it.
5010          */
5011         adapter->rx_bulk_alloc_allowed = true;
5012         adapter->rx_vec_allowed = true;
5013
5014         return 0;
5015 }
5016
5017 static int
5018 ixgbevf_dev_start(struct rte_eth_dev *dev)
5019 {
5020         struct ixgbe_hw *hw =
5021                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5022         uint32_t intr_vector = 0;
5023         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5024         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5025
5026         int err, mask = 0;
5027
5028         PMD_INIT_FUNC_TRACE();
5029
5030         err = hw->mac.ops.reset_hw(hw);
5031         if (err) {
5032                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5033                 return err;
5034         }
5035         hw->mac.get_link_status = true;
5036
5037         /* negotiate mailbox API version to use with the PF. */
5038         ixgbevf_negotiate_api(hw);
5039
5040         ixgbevf_dev_tx_init(dev);
5041
5042         /* This can fail when allocating mbufs for descriptor rings */
5043         err = ixgbevf_dev_rx_init(dev);
5044         if (err) {
5045                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5046                 ixgbe_dev_clear_queues(dev);
5047                 return err;
5048         }
5049
5050         /* Set vfta */
5051         ixgbevf_set_vfta_all(dev, 1);
5052
5053         /* Set HW strip */
5054         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5055                 ETH_VLAN_EXTEND_MASK;
5056         err = ixgbevf_vlan_offload_set(dev, mask);
5057         if (err) {
5058                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5059                 ixgbe_dev_clear_queues(dev);
5060                 return err;
5061         }
5062
5063         ixgbevf_dev_rxtx_start(dev);
5064
5065         ixgbevf_dev_link_update(dev, 0);
5066
5067         /* check and configure queue intr-vector mapping */
5068         if (rte_intr_cap_multiple(intr_handle) &&
5069             dev->data->dev_conf.intr_conf.rxq) {
5070                 /* According to datasheet, only vector 0/1/2 can be used,
5071                  * now only one vector is used for Rx queue
5072                  */
5073                 intr_vector = 1;
5074                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5075                         return -1;
5076         }
5077
5078         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5079                 intr_handle->intr_vec =
5080                         rte_zmalloc("intr_vec",
5081                                     dev->data->nb_rx_queues * sizeof(int), 0);
5082                 if (intr_handle->intr_vec == NULL) {
5083                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5084                                      " intr_vec", dev->data->nb_rx_queues);
5085                         return -ENOMEM;
5086                 }
5087         }
5088         ixgbevf_configure_msix(dev);
5089
5090         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5091          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5092          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5093          * is not cleared, it will fail when following rte_intr_enable( ) tries
5094          * to map Rx queue interrupt to other VFIO vectors.
5095          * So clear uio/vfio intr/evevnfd first to avoid failure.
5096          */
5097         rte_intr_disable(intr_handle);
5098
5099         rte_intr_enable(intr_handle);
5100
5101         /* Re-enable interrupt for VF */
5102         ixgbevf_intr_enable(hw);
5103
5104         return 0;
5105 }
5106
5107 static void
5108 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5109 {
5110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5111         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5112         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5113
5114         PMD_INIT_FUNC_TRACE();
5115
5116         ixgbevf_intr_disable(hw);
5117
5118         hw->adapter_stopped = 1;
5119         ixgbe_stop_adapter(hw);
5120
5121         /*
5122           * Clear what we set, but we still keep shadow_vfta to
5123           * restore after device starts
5124           */
5125         ixgbevf_set_vfta_all(dev, 0);
5126
5127         /* Clear stored conf */
5128         dev->data->scattered_rx = 0;
5129
5130         ixgbe_dev_clear_queues(dev);
5131
5132         /* Clean datapath event and queue/vec mapping */
5133         rte_intr_efd_disable(intr_handle);
5134         if (intr_handle->intr_vec != NULL) {
5135                 rte_free(intr_handle->intr_vec);
5136                 intr_handle->intr_vec = NULL;
5137         }
5138 }
5139
5140 static void
5141 ixgbevf_dev_close(struct rte_eth_dev *dev)
5142 {
5143         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5144
5145         PMD_INIT_FUNC_TRACE();
5146
5147         ixgbe_reset_hw(hw);
5148
5149         ixgbevf_dev_stop(dev);
5150
5151         ixgbe_dev_free_queues(dev);
5152
5153         /**
5154          * Remove the VF MAC address ro ensure
5155          * that the VF traffic goes to the PF
5156          * after stop, close and detach of the VF
5157          **/
5158         ixgbevf_remove_mac_addr(dev, 0);
5159 }
5160
5161 /*
5162  * Reset VF device
5163  */
5164 static int
5165 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5166 {
5167         int ret;
5168
5169         ret = eth_ixgbevf_dev_uninit(dev);
5170         if (ret)
5171                 return ret;
5172
5173         ret = eth_ixgbevf_dev_init(dev);
5174
5175         return ret;
5176 }
5177
5178 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5179 {
5180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5181         struct ixgbe_vfta *shadow_vfta =
5182                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5183         int i = 0, j = 0, vfta = 0, mask = 1;
5184
5185         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5186                 vfta = shadow_vfta->vfta[i];
5187                 if (vfta) {
5188                         mask = 1;
5189                         for (j = 0; j < 32; j++) {
5190                                 if (vfta & mask)
5191                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5192                                                        on, false);
5193                                 mask <<= 1;
5194                         }
5195                 }
5196         }
5197
5198 }
5199
5200 static int
5201 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5202 {
5203         struct ixgbe_hw *hw =
5204                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205         struct ixgbe_vfta *shadow_vfta =
5206                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5207         uint32_t vid_idx = 0;
5208         uint32_t vid_bit = 0;
5209         int ret = 0;
5210
5211         PMD_INIT_FUNC_TRACE();
5212
5213         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5214         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5215         if (ret) {
5216                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5217                 return ret;
5218         }
5219         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5220         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5221
5222         /* Save what we set and retore it after device reset */
5223         if (on)
5224                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5225         else
5226                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5227
5228         return 0;
5229 }
5230
5231 static void
5232 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5233 {
5234         struct ixgbe_hw *hw =
5235                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5236         uint32_t ctrl;
5237
5238         PMD_INIT_FUNC_TRACE();
5239
5240         if (queue >= hw->mac.max_rx_queues)
5241                 return;
5242
5243         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5244         if (on)
5245                 ctrl |= IXGBE_RXDCTL_VME;
5246         else
5247                 ctrl &= ~IXGBE_RXDCTL_VME;
5248         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5249
5250         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5251 }
5252
5253 static int
5254 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5255 {
5256         struct ixgbe_rx_queue *rxq;
5257         uint16_t i;
5258         int on = 0;
5259
5260         /* VF function only support hw strip feature, others are not support */
5261         if (mask & ETH_VLAN_STRIP_MASK) {
5262                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5263                         rxq = dev->data->rx_queues[i];
5264                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5265                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5266                 }
5267         }
5268
5269         return 0;
5270 }
5271
5272 int
5273 ixgbe_vt_check(struct ixgbe_hw *hw)
5274 {
5275         uint32_t reg_val;
5276
5277         /* if Virtualization Technology is enabled */
5278         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5279         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5280                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5281                 return -1;
5282         }
5283
5284         return 0;
5285 }
5286
5287 static uint32_t
5288 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5289 {
5290         uint32_t vector = 0;
5291
5292         switch (hw->mac.mc_filter_type) {
5293         case 0:   /* use bits [47:36] of the address */
5294                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5295                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5296                 break;
5297         case 1:   /* use bits [46:35] of the address */
5298                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5299                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5300                 break;
5301         case 2:   /* use bits [45:34] of the address */
5302                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5303                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5304                 break;
5305         case 3:   /* use bits [43:32] of the address */
5306                 vector = ((uc_addr->addr_bytes[4]) |
5307                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5308                 break;
5309         default:  /* Invalid mc_filter_type */
5310                 break;
5311         }
5312
5313         /* vector can only be 12-bits or boundary will be exceeded */
5314         vector &= 0xFFF;
5315         return vector;
5316 }
5317
5318 static int
5319 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5320                         uint8_t on)
5321 {
5322         uint32_t vector;
5323         uint32_t uta_idx;
5324         uint32_t reg_val;
5325         uint32_t uta_shift;
5326         uint32_t rc;
5327         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5328         const uint32_t ixgbe_uta_bit_shift = 5;
5329         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5330         const uint32_t bit1 = 0x1;
5331
5332         struct ixgbe_hw *hw =
5333                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5334         struct ixgbe_uta_info *uta_info =
5335                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5336
5337         /* The UTA table only exists on 82599 hardware and newer */
5338         if (hw->mac.type < ixgbe_mac_82599EB)
5339                 return -ENOTSUP;
5340
5341         vector = ixgbe_uta_vector(hw, mac_addr);
5342         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5343         uta_shift = vector & ixgbe_uta_bit_mask;
5344
5345         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5346         if (rc == on)
5347                 return 0;
5348
5349         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5350         if (on) {
5351                 uta_info->uta_in_use++;
5352                 reg_val |= (bit1 << uta_shift);
5353                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5354         } else {
5355                 uta_info->uta_in_use--;
5356                 reg_val &= ~(bit1 << uta_shift);
5357                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5358         }
5359
5360         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5361
5362         if (uta_info->uta_in_use > 0)
5363                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5364                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5365         else
5366                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5367
5368         return 0;
5369 }
5370
5371 static int
5372 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5373 {
5374         int i;
5375         struct ixgbe_hw *hw =
5376                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5377         struct ixgbe_uta_info *uta_info =
5378                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5379
5380         /* The UTA table only exists on 82599 hardware and newer */
5381         if (hw->mac.type < ixgbe_mac_82599EB)
5382                 return -ENOTSUP;
5383
5384         if (on) {
5385                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5386                         uta_info->uta_shadow[i] = ~0;
5387                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5388                 }
5389         } else {
5390                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5391                         uta_info->uta_shadow[i] = 0;
5392                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5393                 }
5394         }
5395         return 0;
5396
5397 }
5398
5399 uint32_t
5400 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5401 {
5402         uint32_t new_val = orig_val;
5403
5404         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5405                 new_val |= IXGBE_VMOLR_AUPE;
5406         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5407                 new_val |= IXGBE_VMOLR_ROMPE;
5408         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5409                 new_val |= IXGBE_VMOLR_ROPE;
5410         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5411                 new_val |= IXGBE_VMOLR_BAM;
5412         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5413                 new_val |= IXGBE_VMOLR_MPE;
5414
5415         return new_val;
5416 }
5417
5418 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5419 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5420 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5421 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5422 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5423         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5424         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5425
5426 static int
5427 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5428                       struct rte_eth_mirror_conf *mirror_conf,
5429                       uint8_t rule_id, uint8_t on)
5430 {
5431         uint32_t mr_ctl, vlvf;
5432         uint32_t mp_lsb = 0;
5433         uint32_t mv_msb = 0;
5434         uint32_t mv_lsb = 0;
5435         uint32_t mp_msb = 0;
5436         uint8_t i = 0;
5437         int reg_index = 0;
5438         uint64_t vlan_mask = 0;
5439
5440         const uint8_t pool_mask_offset = 32;
5441         const uint8_t vlan_mask_offset = 32;
5442         const uint8_t dst_pool_offset = 8;
5443         const uint8_t rule_mr_offset  = 4;
5444         const uint8_t mirror_rule_mask = 0x0F;
5445
5446         struct ixgbe_mirror_info *mr_info =
5447                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5448         struct ixgbe_hw *hw =
5449                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5450         uint8_t mirror_type = 0;
5451
5452         if (ixgbe_vt_check(hw) < 0)
5453                 return -ENOTSUP;
5454
5455         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5456                 return -EINVAL;
5457
5458         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5459                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5460                             mirror_conf->rule_type);
5461                 return -EINVAL;
5462         }
5463
5464         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5465                 mirror_type |= IXGBE_MRCTL_VLME;
5466                 /* Check if vlan id is valid and find conresponding VLAN ID
5467                  * index in VLVF
5468                  */
5469                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5470                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5471                                 /* search vlan id related pool vlan filter
5472                                  * index
5473                                  */
5474                                 reg_index = ixgbe_find_vlvf_slot(
5475                                                 hw,
5476                                                 mirror_conf->vlan.vlan_id[i],
5477                                                 false);
5478                                 if (reg_index < 0)
5479                                         return -EINVAL;
5480                                 vlvf = IXGBE_READ_REG(hw,
5481                                                       IXGBE_VLVF(reg_index));
5482                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5483                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5484                                       mirror_conf->vlan.vlan_id[i]))
5485                                         vlan_mask |= (1ULL << reg_index);
5486                                 else
5487                                         return -EINVAL;
5488                         }
5489                 }
5490
5491                 if (on) {
5492                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5493                         mv_msb = vlan_mask >> vlan_mask_offset;
5494
5495                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5496                                                 mirror_conf->vlan.vlan_mask;
5497                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5498                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5499                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5500                                                 mirror_conf->vlan.vlan_id[i];
5501                         }
5502                 } else {
5503                         mv_lsb = 0;
5504                         mv_msb = 0;
5505                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5506                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5507                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5508                 }
5509         }
5510
5511         /**
5512          * if enable pool mirror, write related pool mask register,if disable
5513          * pool mirror, clear PFMRVM register
5514          */
5515         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5516                 mirror_type |= IXGBE_MRCTL_VPME;
5517                 if (on) {
5518                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5519                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5520                         mr_info->mr_conf[rule_id].pool_mask =
5521                                         mirror_conf->pool_mask;
5522
5523                 } else {
5524                         mp_lsb = 0;
5525                         mp_msb = 0;
5526                         mr_info->mr_conf[rule_id].pool_mask = 0;
5527                 }
5528         }
5529         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5530                 mirror_type |= IXGBE_MRCTL_UPME;
5531         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5532                 mirror_type |= IXGBE_MRCTL_DPME;
5533
5534         /* read  mirror control register and recalculate it */
5535         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5536
5537         if (on) {
5538                 mr_ctl |= mirror_type;
5539                 mr_ctl &= mirror_rule_mask;
5540                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5541         } else {
5542                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5543         }
5544
5545         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5546         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5547
5548         /* write mirrror control  register */
5549         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5550
5551         /* write pool mirrror control  register */
5552         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5553                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5554                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5555                                 mp_msb);
5556         }
5557         /* write VLAN mirrror control  register */
5558         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5559                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5560                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5561                                 mv_msb);
5562         }
5563
5564         return 0;
5565 }
5566
5567 static int
5568 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5569 {
5570         int mr_ctl = 0;
5571         uint32_t lsb_val = 0;
5572         uint32_t msb_val = 0;
5573         const uint8_t rule_mr_offset = 4;
5574
5575         struct ixgbe_hw *hw =
5576                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5577         struct ixgbe_mirror_info *mr_info =
5578                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5579
5580         if (ixgbe_vt_check(hw) < 0)
5581                 return -ENOTSUP;
5582
5583         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5584                 return -EINVAL;
5585
5586         memset(&mr_info->mr_conf[rule_id], 0,
5587                sizeof(struct rte_eth_mirror_conf));
5588
5589         /* clear PFVMCTL register */
5590         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5591
5592         /* clear pool mask register */
5593         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5594         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5595
5596         /* clear vlan mask register */
5597         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5598         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5599
5600         return 0;
5601 }
5602
5603 static int
5604 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5605 {
5606         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5607         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5608         uint32_t mask;
5609         struct ixgbe_hw *hw =
5610                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5611         uint32_t vec = IXGBE_MISC_VEC_ID;
5612
5613         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5614         if (rte_intr_allow_others(intr_handle))
5615                 vec = IXGBE_RX_VEC_START;
5616         mask |= (1 << vec);
5617         RTE_SET_USED(queue_id);
5618         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5619
5620         rte_intr_enable(intr_handle);
5621
5622         return 0;
5623 }
5624
5625 static int
5626 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5627 {
5628         uint32_t mask;
5629         struct ixgbe_hw *hw =
5630                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5631         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5632         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5633         uint32_t vec = IXGBE_MISC_VEC_ID;
5634
5635         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5636         if (rte_intr_allow_others(intr_handle))
5637                 vec = IXGBE_RX_VEC_START;
5638         mask &= ~(1 << vec);
5639         RTE_SET_USED(queue_id);
5640         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5641
5642         return 0;
5643 }
5644
5645 static int
5646 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5647 {
5648         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5649         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5650         uint32_t mask;
5651         struct ixgbe_hw *hw =
5652                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5653         struct ixgbe_interrupt *intr =
5654                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5655
5656         if (queue_id < 16) {
5657                 ixgbe_disable_intr(hw);
5658                 intr->mask |= (1 << queue_id);
5659                 ixgbe_enable_intr(dev);
5660         } else if (queue_id < 32) {
5661                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5662                 mask &= (1 << queue_id);
5663                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5664         } else if (queue_id < 64) {
5665                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5666                 mask &= (1 << (queue_id - 32));
5667                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5668         }
5669         rte_intr_enable(intr_handle);
5670
5671         return 0;
5672 }
5673
5674 static int
5675 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5676 {
5677         uint32_t mask;
5678         struct ixgbe_hw *hw =
5679                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5680         struct ixgbe_interrupt *intr =
5681                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5682
5683         if (queue_id < 16) {
5684                 ixgbe_disable_intr(hw);
5685                 intr->mask &= ~(1 << queue_id);
5686                 ixgbe_enable_intr(dev);
5687         } else if (queue_id < 32) {
5688                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5689                 mask &= ~(1 << queue_id);
5690                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5691         } else if (queue_id < 64) {
5692                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5693                 mask &= ~(1 << (queue_id - 32));
5694                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5695         }
5696
5697         return 0;
5698 }
5699
5700 static void
5701 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5702                      uint8_t queue, uint8_t msix_vector)
5703 {
5704         uint32_t tmp, idx;
5705
5706         if (direction == -1) {
5707                 /* other causes */
5708                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5709                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5710                 tmp &= ~0xFF;
5711                 tmp |= msix_vector;
5712                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5713         } else {
5714                 /* rx or tx cause */
5715                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5716                 idx = ((16 * (queue & 1)) + (8 * direction));
5717                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5718                 tmp &= ~(0xFF << idx);
5719                 tmp |= (msix_vector << idx);
5720                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5721         }
5722 }
5723
5724 /**
5725  * set the IVAR registers, mapping interrupt causes to vectors
5726  * @param hw
5727  *  pointer to ixgbe_hw struct
5728  * @direction
5729  *  0 for Rx, 1 for Tx, -1 for other causes
5730  * @queue
5731  *  queue to map the corresponding interrupt to
5732  * @msix_vector
5733  *  the vector to map to the corresponding queue
5734  */
5735 static void
5736 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5737                    uint8_t queue, uint8_t msix_vector)
5738 {
5739         uint32_t tmp, idx;
5740
5741         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5742         if (hw->mac.type == ixgbe_mac_82598EB) {
5743                 if (direction == -1)
5744                         direction = 0;
5745                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5746                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5747                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5748                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5749                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5750         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5751                         (hw->mac.type == ixgbe_mac_X540) ||
5752                         (hw->mac.type == ixgbe_mac_X550)) {
5753                 if (direction == -1) {
5754                         /* other causes */
5755                         idx = ((queue & 1) * 8);
5756                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5757                         tmp &= ~(0xFF << idx);
5758                         tmp |= (msix_vector << idx);
5759                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5760                 } else {
5761                         /* rx or tx causes */
5762                         idx = ((16 * (queue & 1)) + (8 * direction));
5763                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5764                         tmp &= ~(0xFF << idx);
5765                         tmp |= (msix_vector << idx);
5766                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5767                 }
5768         }
5769 }
5770
5771 static void
5772 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5773 {
5774         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5775         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5776         struct ixgbe_hw *hw =
5777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5778         uint32_t q_idx;
5779         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5780         uint32_t base = IXGBE_MISC_VEC_ID;
5781
5782         /* Configure VF other cause ivar */
5783         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5784
5785         /* won't configure msix register if no mapping is done
5786          * between intr vector and event fd.
5787          */
5788         if (!rte_intr_dp_is_en(intr_handle))
5789                 return;
5790
5791         if (rte_intr_allow_others(intr_handle)) {
5792                 base = IXGBE_RX_VEC_START;
5793                 vector_idx = IXGBE_RX_VEC_START;
5794         }
5795
5796         /* Configure all RX queues of VF */
5797         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5798                 /* Force all queue use vector 0,
5799                  * as IXGBE_VF_MAXMSIVECOTR = 1
5800                  */
5801                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5802                 intr_handle->intr_vec[q_idx] = vector_idx;
5803                 if (vector_idx < base + intr_handle->nb_efd - 1)
5804                         vector_idx++;
5805         }
5806 }
5807
5808 /**
5809  * Sets up the hardware to properly generate MSI-X interrupts
5810  * @hw
5811  *  board private structure
5812  */
5813 static void
5814 ixgbe_configure_msix(struct rte_eth_dev *dev)
5815 {
5816         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5817         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5818         struct ixgbe_hw *hw =
5819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5820         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5821         uint32_t vec = IXGBE_MISC_VEC_ID;
5822         uint32_t mask;
5823         uint32_t gpie;
5824
5825         /* won't configure msix register if no mapping is done
5826          * between intr vector and event fd
5827          */
5828         if (!rte_intr_dp_is_en(intr_handle))
5829                 return;
5830
5831         if (rte_intr_allow_others(intr_handle))
5832                 vec = base = IXGBE_RX_VEC_START;
5833
5834         /* setup GPIE for MSI-x mode */
5835         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5836         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5837                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5838         /* auto clearing and auto setting corresponding bits in EIMS
5839          * when MSI-X interrupt is triggered
5840          */
5841         if (hw->mac.type == ixgbe_mac_82598EB) {
5842                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5843         } else {
5844                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5845                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5846         }
5847         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5848
5849         /* Populate the IVAR table and set the ITR values to the
5850          * corresponding register.
5851          */
5852         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5853              queue_id++) {
5854                 /* by default, 1:1 mapping */
5855                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5856                 intr_handle->intr_vec[queue_id] = vec;
5857                 if (vec < base + intr_handle->nb_efd - 1)
5858                         vec++;
5859         }
5860
5861         switch (hw->mac.type) {
5862         case ixgbe_mac_82598EB:
5863                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5864                                    IXGBE_MISC_VEC_ID);
5865                 break;
5866         case ixgbe_mac_82599EB:
5867         case ixgbe_mac_X540:
5868         case ixgbe_mac_X550:
5869                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5870                 break;
5871         default:
5872                 break;
5873         }
5874         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5875                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5876
5877         /* set up to autoclear timer, and the vectors */
5878         mask = IXGBE_EIMS_ENABLE_MASK;
5879         mask &= ~(IXGBE_EIMS_OTHER |
5880                   IXGBE_EIMS_MAILBOX |
5881                   IXGBE_EIMS_LSC);
5882
5883         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5884 }
5885
5886 int
5887 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5888                            uint16_t queue_idx, uint16_t tx_rate)
5889 {
5890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5891         struct rte_eth_rxmode *rxmode;
5892         uint32_t rf_dec, rf_int;
5893         uint32_t bcnrc_val;
5894         uint16_t link_speed = dev->data->dev_link.link_speed;
5895
5896         if (queue_idx >= hw->mac.max_tx_queues)
5897                 return -EINVAL;
5898
5899         if (tx_rate != 0) {
5900                 /* Calculate the rate factor values to set */
5901                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5902                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5903                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5904
5905                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5906                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5907                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5908                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5909         } else {
5910                 bcnrc_val = 0;
5911         }
5912
5913         rxmode = &dev->data->dev_conf.rxmode;
5914         /*
5915          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5916          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5917          * set as 0x4.
5918          */
5919         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5920             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5921                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5922                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5923         else
5924                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5925                         IXGBE_MMW_SIZE_DEFAULT);
5926
5927         /* Set RTTBCNRC of queue X */
5928         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5929         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5930         IXGBE_WRITE_FLUSH(hw);
5931
5932         return 0;
5933 }
5934
5935 static int
5936 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5937                      __attribute__((unused)) uint32_t index,
5938                      __attribute__((unused)) uint32_t pool)
5939 {
5940         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941         int diag;
5942
5943         /*
5944          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5945          * operation. Trap this case to avoid exhausting the [very limited]
5946          * set of PF resources used to store VF MAC addresses.
5947          */
5948         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5949                 return -1;
5950         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5951         if (diag != 0)
5952                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5953                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5954                             mac_addr->addr_bytes[0],
5955                             mac_addr->addr_bytes[1],
5956                             mac_addr->addr_bytes[2],
5957                             mac_addr->addr_bytes[3],
5958                             mac_addr->addr_bytes[4],
5959                             mac_addr->addr_bytes[5],
5960                             diag);
5961         return diag;
5962 }
5963
5964 static void
5965 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5966 {
5967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5968         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5969         struct ether_addr *mac_addr;
5970         uint32_t i;
5971         int diag;
5972
5973         /*
5974          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5975          * not support the deletion of a given MAC address.
5976          * Instead, it imposes to delete all MAC addresses, then to add again
5977          * all MAC addresses with the exception of the one to be deleted.
5978          */
5979         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5980
5981         /*
5982          * Add again all MAC addresses, with the exception of the deleted one
5983          * and of the permanent MAC address.
5984          */
5985         for (i = 0, mac_addr = dev->data->mac_addrs;
5986              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5987                 /* Skip the deleted MAC address */
5988                 if (i == index)
5989                         continue;
5990                 /* Skip NULL MAC addresses */
5991                 if (is_zero_ether_addr(mac_addr))
5992                         continue;
5993                 /* Skip the permanent MAC address */
5994                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5995                         continue;
5996                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5997                 if (diag != 0)
5998                         PMD_DRV_LOG(ERR,
5999                                     "Adding again MAC address "
6000                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6001                                     "diag=%d",
6002                                     mac_addr->addr_bytes[0],
6003                                     mac_addr->addr_bytes[1],
6004                                     mac_addr->addr_bytes[2],
6005                                     mac_addr->addr_bytes[3],
6006                                     mac_addr->addr_bytes[4],
6007                                     mac_addr->addr_bytes[5],
6008                                     diag);
6009         }
6010 }
6011
6012 static int
6013 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6014 {
6015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6016
6017         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6018
6019         return 0;
6020 }
6021
6022 int
6023 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6024                         struct rte_eth_syn_filter *filter,
6025                         bool add)
6026 {
6027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6028         struct ixgbe_filter_info *filter_info =
6029                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6030         uint32_t syn_info;
6031         uint32_t synqf;
6032
6033         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6034                 return -EINVAL;
6035
6036         syn_info = filter_info->syn_info;
6037
6038         if (add) {
6039                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6040                         return -EINVAL;
6041                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6042                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6043
6044                 if (filter->hig_pri)
6045                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6046                 else
6047                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6048         } else {
6049                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6050                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6051                         return -ENOENT;
6052                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6053         }
6054
6055         filter_info->syn_info = synqf;
6056         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6057         IXGBE_WRITE_FLUSH(hw);
6058         return 0;
6059 }
6060
6061 static int
6062 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6063                         struct rte_eth_syn_filter *filter)
6064 {
6065         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6066         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6067
6068         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6069                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6070                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6071                 return 0;
6072         }
6073         return -ENOENT;
6074 }
6075
6076 static int
6077 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6078                         enum rte_filter_op filter_op,
6079                         void *arg)
6080 {
6081         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6082         int ret;
6083
6084         MAC_TYPE_FILTER_SUP(hw->mac.type);
6085
6086         if (filter_op == RTE_ETH_FILTER_NOP)
6087                 return 0;
6088
6089         if (arg == NULL) {
6090                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6091                             filter_op);
6092                 return -EINVAL;
6093         }
6094
6095         switch (filter_op) {
6096         case RTE_ETH_FILTER_ADD:
6097                 ret = ixgbe_syn_filter_set(dev,
6098                                 (struct rte_eth_syn_filter *)arg,
6099                                 TRUE);
6100                 break;
6101         case RTE_ETH_FILTER_DELETE:
6102                 ret = ixgbe_syn_filter_set(dev,
6103                                 (struct rte_eth_syn_filter *)arg,
6104                                 FALSE);
6105                 break;
6106         case RTE_ETH_FILTER_GET:
6107                 ret = ixgbe_syn_filter_get(dev,
6108                                 (struct rte_eth_syn_filter *)arg);
6109                 break;
6110         default:
6111                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6112                 ret = -EINVAL;
6113                 break;
6114         }
6115
6116         return ret;
6117 }
6118
6119
6120 static inline enum ixgbe_5tuple_protocol
6121 convert_protocol_type(uint8_t protocol_value)
6122 {
6123         if (protocol_value == IPPROTO_TCP)
6124                 return IXGBE_FILTER_PROTOCOL_TCP;
6125         else if (protocol_value == IPPROTO_UDP)
6126                 return IXGBE_FILTER_PROTOCOL_UDP;
6127         else if (protocol_value == IPPROTO_SCTP)
6128                 return IXGBE_FILTER_PROTOCOL_SCTP;
6129         else
6130                 return IXGBE_FILTER_PROTOCOL_NONE;
6131 }
6132
6133 /* inject a 5-tuple filter to HW */
6134 static inline void
6135 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6136                            struct ixgbe_5tuple_filter *filter)
6137 {
6138         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6139         int i;
6140         uint32_t ftqf, sdpqf;
6141         uint32_t l34timir = 0;
6142         uint8_t mask = 0xff;
6143
6144         i = filter->index;
6145
6146         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6147                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6148         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6149
6150         ftqf = (uint32_t)(filter->filter_info.proto &
6151                 IXGBE_FTQF_PROTOCOL_MASK);
6152         ftqf |= (uint32_t)((filter->filter_info.priority &
6153                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6154         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6155                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6156         if (filter->filter_info.dst_ip_mask == 0)
6157                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6158         if (filter->filter_info.src_port_mask == 0)
6159                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6160         if (filter->filter_info.dst_port_mask == 0)
6161                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6162         if (filter->filter_info.proto_mask == 0)
6163                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6164         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6165         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6166         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6167
6168         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6169         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6170         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6171         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6172
6173         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6174         l34timir |= (uint32_t)(filter->queue <<
6175                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6176         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6177 }
6178
6179 /*
6180  * add a 5tuple filter
6181  *
6182  * @param
6183  * dev: Pointer to struct rte_eth_dev.
6184  * index: the index the filter allocates.
6185  * filter: ponter to the filter that will be added.
6186  * rx_queue: the queue id the filter assigned to.
6187  *
6188  * @return
6189  *    - On success, zero.
6190  *    - On failure, a negative value.
6191  */
6192 static int
6193 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6194                         struct ixgbe_5tuple_filter *filter)
6195 {
6196         struct ixgbe_filter_info *filter_info =
6197                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6198         int i, idx, shift;
6199
6200         /*
6201          * look for an unused 5tuple filter index,
6202          * and insert the filter to list.
6203          */
6204         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6205                 idx = i / (sizeof(uint32_t) * NBBY);
6206                 shift = i % (sizeof(uint32_t) * NBBY);
6207                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6208                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6209                         filter->index = i;
6210                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6211                                           filter,
6212                                           entries);
6213                         break;
6214                 }
6215         }
6216         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6217                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6218                 return -ENOSYS;
6219         }
6220
6221         ixgbe_inject_5tuple_filter(dev, filter);
6222
6223         return 0;
6224 }
6225
6226 /*
6227  * remove a 5tuple filter
6228  *
6229  * @param
6230  * dev: Pointer to struct rte_eth_dev.
6231  * filter: the pointer of the filter will be removed.
6232  */
6233 static void
6234 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6235                         struct ixgbe_5tuple_filter *filter)
6236 {
6237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6238         struct ixgbe_filter_info *filter_info =
6239                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6240         uint16_t index = filter->index;
6241
6242         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6243                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6244         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6245         rte_free(filter);
6246
6247         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6248         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6249         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6250         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6251         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6252 }
6253
6254 static int
6255 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6256 {
6257         struct ixgbe_hw *hw;
6258         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6259         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6260
6261         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6262
6263         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6264                 return -EINVAL;
6265
6266         /* refuse mtu that requires the support of scattered packets when this
6267          * feature has not been enabled before.
6268          */
6269         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6270             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6271              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6272                 return -EINVAL;
6273
6274         /*
6275          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6276          * request of the version 2.0 of the mailbox API.
6277          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6278          * of the mailbox API.
6279          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6280          * prior to 3.11.33 which contains the following change:
6281          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6282          */
6283         ixgbevf_rlpml_set_vf(hw, max_frame);
6284
6285         /* update max frame size */
6286         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6287         return 0;
6288 }
6289
6290 static inline struct ixgbe_5tuple_filter *
6291 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6292                         struct ixgbe_5tuple_filter_info *key)
6293 {
6294         struct ixgbe_5tuple_filter *it;
6295
6296         TAILQ_FOREACH(it, filter_list, entries) {
6297                 if (memcmp(key, &it->filter_info,
6298                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6299                         return it;
6300                 }
6301         }
6302         return NULL;
6303 }
6304
6305 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6306 static inline int
6307 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6308                         struct ixgbe_5tuple_filter_info *filter_info)
6309 {
6310         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6311                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6312                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6313                 return -EINVAL;
6314
6315         switch (filter->dst_ip_mask) {
6316         case UINT32_MAX:
6317                 filter_info->dst_ip_mask = 0;
6318                 filter_info->dst_ip = filter->dst_ip;
6319                 break;
6320         case 0:
6321                 filter_info->dst_ip_mask = 1;
6322                 break;
6323         default:
6324                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6325                 return -EINVAL;
6326         }
6327
6328         switch (filter->src_ip_mask) {
6329         case UINT32_MAX:
6330                 filter_info->src_ip_mask = 0;
6331                 filter_info->src_ip = filter->src_ip;
6332                 break;
6333         case 0:
6334                 filter_info->src_ip_mask = 1;
6335                 break;
6336         default:
6337                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6338                 return -EINVAL;
6339         }
6340
6341         switch (filter->dst_port_mask) {
6342         case UINT16_MAX:
6343                 filter_info->dst_port_mask = 0;
6344                 filter_info->dst_port = filter->dst_port;
6345                 break;
6346         case 0:
6347                 filter_info->dst_port_mask = 1;
6348                 break;
6349         default:
6350                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6351                 return -EINVAL;
6352         }
6353
6354         switch (filter->src_port_mask) {
6355         case UINT16_MAX:
6356                 filter_info->src_port_mask = 0;
6357                 filter_info->src_port = filter->src_port;
6358                 break;
6359         case 0:
6360                 filter_info->src_port_mask = 1;
6361                 break;
6362         default:
6363                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6364                 return -EINVAL;
6365         }
6366
6367         switch (filter->proto_mask) {
6368         case UINT8_MAX:
6369                 filter_info->proto_mask = 0;
6370                 filter_info->proto =
6371                         convert_protocol_type(filter->proto);
6372                 break;
6373         case 0:
6374                 filter_info->proto_mask = 1;
6375                 break;
6376         default:
6377                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6378                 return -EINVAL;
6379         }
6380
6381         filter_info->priority = (uint8_t)filter->priority;
6382         return 0;
6383 }
6384
6385 /*
6386  * add or delete a ntuple filter
6387  *
6388  * @param
6389  * dev: Pointer to struct rte_eth_dev.
6390  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6391  * add: if true, add filter, if false, remove filter
6392  *
6393  * @return
6394  *    - On success, zero.
6395  *    - On failure, a negative value.
6396  */
6397 int
6398 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6399                         struct rte_eth_ntuple_filter *ntuple_filter,
6400                         bool add)
6401 {
6402         struct ixgbe_filter_info *filter_info =
6403                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6404         struct ixgbe_5tuple_filter_info filter_5tuple;
6405         struct ixgbe_5tuple_filter *filter;
6406         int ret;
6407
6408         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6409                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6410                 return -EINVAL;
6411         }
6412
6413         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6414         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6415         if (ret < 0)
6416                 return ret;
6417
6418         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6419                                          &filter_5tuple);
6420         if (filter != NULL && add) {
6421                 PMD_DRV_LOG(ERR, "filter exists.");
6422                 return -EEXIST;
6423         }
6424         if (filter == NULL && !add) {
6425                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6426                 return -ENOENT;
6427         }
6428
6429         if (add) {
6430                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6431                                 sizeof(struct ixgbe_5tuple_filter), 0);
6432                 if (filter == NULL)
6433                         return -ENOMEM;
6434                 rte_memcpy(&filter->filter_info,
6435                                  &filter_5tuple,
6436                                  sizeof(struct ixgbe_5tuple_filter_info));
6437                 filter->queue = ntuple_filter->queue;
6438                 ret = ixgbe_add_5tuple_filter(dev, filter);
6439                 if (ret < 0) {
6440                         rte_free(filter);
6441                         return ret;
6442                 }
6443         } else
6444                 ixgbe_remove_5tuple_filter(dev, filter);
6445
6446         return 0;
6447 }
6448
6449 /*
6450  * get a ntuple filter
6451  *
6452  * @param
6453  * dev: Pointer to struct rte_eth_dev.
6454  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6455  *
6456  * @return
6457  *    - On success, zero.
6458  *    - On failure, a negative value.
6459  */
6460 static int
6461 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6462                         struct rte_eth_ntuple_filter *ntuple_filter)
6463 {
6464         struct ixgbe_filter_info *filter_info =
6465                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6466         struct ixgbe_5tuple_filter_info filter_5tuple;
6467         struct ixgbe_5tuple_filter *filter;
6468         int ret;
6469
6470         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6471                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6472                 return -EINVAL;
6473         }
6474
6475         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6476         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6477         if (ret < 0)
6478                 return ret;
6479
6480         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6481                                          &filter_5tuple);
6482         if (filter == NULL) {
6483                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6484                 return -ENOENT;
6485         }
6486         ntuple_filter->queue = filter->queue;
6487         return 0;
6488 }
6489
6490 /*
6491  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6492  * @dev: pointer to rte_eth_dev structure
6493  * @filter_op:operation will be taken.
6494  * @arg: a pointer to specific structure corresponding to the filter_op
6495  *
6496  * @return
6497  *    - On success, zero.
6498  *    - On failure, a negative value.
6499  */
6500 static int
6501 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6502                                 enum rte_filter_op filter_op,
6503                                 void *arg)
6504 {
6505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6506         int ret;
6507
6508         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6509
6510         if (filter_op == RTE_ETH_FILTER_NOP)
6511                 return 0;
6512
6513         if (arg == NULL) {
6514                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6515                             filter_op);
6516                 return -EINVAL;
6517         }
6518
6519         switch (filter_op) {
6520         case RTE_ETH_FILTER_ADD:
6521                 ret = ixgbe_add_del_ntuple_filter(dev,
6522                         (struct rte_eth_ntuple_filter *)arg,
6523                         TRUE);
6524                 break;
6525         case RTE_ETH_FILTER_DELETE:
6526                 ret = ixgbe_add_del_ntuple_filter(dev,
6527                         (struct rte_eth_ntuple_filter *)arg,
6528                         FALSE);
6529                 break;
6530         case RTE_ETH_FILTER_GET:
6531                 ret = ixgbe_get_ntuple_filter(dev,
6532                         (struct rte_eth_ntuple_filter *)arg);
6533                 break;
6534         default:
6535                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6536                 ret = -EINVAL;
6537                 break;
6538         }
6539         return ret;
6540 }
6541
6542 int
6543 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6544                         struct rte_eth_ethertype_filter *filter,
6545                         bool add)
6546 {
6547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6548         struct ixgbe_filter_info *filter_info =
6549                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6550         uint32_t etqf = 0;
6551         uint32_t etqs = 0;
6552         int ret;
6553         struct ixgbe_ethertype_filter ethertype_filter;
6554
6555         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6556                 return -EINVAL;
6557
6558         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6559                 filter->ether_type == ETHER_TYPE_IPv6) {
6560                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6561                         " ethertype filter.", filter->ether_type);
6562                 return -EINVAL;
6563         }
6564
6565         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6566                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6567                 return -EINVAL;
6568         }
6569         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6570                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6571                 return -EINVAL;
6572         }
6573
6574         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6575         if (ret >= 0 && add) {
6576                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6577                             filter->ether_type);
6578                 return -EEXIST;
6579         }
6580         if (ret < 0 && !add) {
6581                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6582                             filter->ether_type);
6583                 return -ENOENT;
6584         }
6585
6586         if (add) {
6587                 etqf = IXGBE_ETQF_FILTER_EN;
6588                 etqf |= (uint32_t)filter->ether_type;
6589                 etqs |= (uint32_t)((filter->queue <<
6590                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6591                                     IXGBE_ETQS_RX_QUEUE);
6592                 etqs |= IXGBE_ETQS_QUEUE_EN;
6593
6594                 ethertype_filter.ethertype = filter->ether_type;
6595                 ethertype_filter.etqf = etqf;
6596                 ethertype_filter.etqs = etqs;
6597                 ethertype_filter.conf = FALSE;
6598                 ret = ixgbe_ethertype_filter_insert(filter_info,
6599                                                     &ethertype_filter);
6600                 if (ret < 0) {
6601                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6602                         return -ENOSPC;
6603                 }
6604         } else {
6605                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6606                 if (ret < 0)
6607                         return -ENOSYS;
6608         }
6609         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6610         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6611         IXGBE_WRITE_FLUSH(hw);
6612
6613         return 0;
6614 }
6615
6616 static int
6617 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6618                         struct rte_eth_ethertype_filter *filter)
6619 {
6620         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6621         struct ixgbe_filter_info *filter_info =
6622                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6623         uint32_t etqf, etqs;
6624         int ret;
6625
6626         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6627         if (ret < 0) {
6628                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6629                             filter->ether_type);
6630                 return -ENOENT;
6631         }
6632
6633         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6634         if (etqf & IXGBE_ETQF_FILTER_EN) {
6635                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6636                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6637                 filter->flags = 0;
6638                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6639                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6640                 return 0;
6641         }
6642         return -ENOENT;
6643 }
6644
6645 /*
6646  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6647  * @dev: pointer to rte_eth_dev structure
6648  * @filter_op:operation will be taken.
6649  * @arg: a pointer to specific structure corresponding to the filter_op
6650  */
6651 static int
6652 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6653                                 enum rte_filter_op filter_op,
6654                                 void *arg)
6655 {
6656         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6657         int ret;
6658
6659         MAC_TYPE_FILTER_SUP(hw->mac.type);
6660
6661         if (filter_op == RTE_ETH_FILTER_NOP)
6662                 return 0;
6663
6664         if (arg == NULL) {
6665                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6666                             filter_op);
6667                 return -EINVAL;
6668         }
6669
6670         switch (filter_op) {
6671         case RTE_ETH_FILTER_ADD:
6672                 ret = ixgbe_add_del_ethertype_filter(dev,
6673                         (struct rte_eth_ethertype_filter *)arg,
6674                         TRUE);
6675                 break;
6676         case RTE_ETH_FILTER_DELETE:
6677                 ret = ixgbe_add_del_ethertype_filter(dev,
6678                         (struct rte_eth_ethertype_filter *)arg,
6679                         FALSE);
6680                 break;
6681         case RTE_ETH_FILTER_GET:
6682                 ret = ixgbe_get_ethertype_filter(dev,
6683                         (struct rte_eth_ethertype_filter *)arg);
6684                 break;
6685         default:
6686                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6687                 ret = -EINVAL;
6688                 break;
6689         }
6690         return ret;
6691 }
6692
6693 static int
6694 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6695                      enum rte_filter_type filter_type,
6696                      enum rte_filter_op filter_op,
6697                      void *arg)
6698 {
6699         int ret = 0;
6700
6701         switch (filter_type) {
6702         case RTE_ETH_FILTER_NTUPLE:
6703                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6704                 break;
6705         case RTE_ETH_FILTER_ETHERTYPE:
6706                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6707                 break;
6708         case RTE_ETH_FILTER_SYN:
6709                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6710                 break;
6711         case RTE_ETH_FILTER_FDIR:
6712                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6713                 break;
6714         case RTE_ETH_FILTER_L2_TUNNEL:
6715                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6716                 break;
6717         case RTE_ETH_FILTER_GENERIC:
6718                 if (filter_op != RTE_ETH_FILTER_GET)
6719                         return -EINVAL;
6720                 *(const void **)arg = &ixgbe_flow_ops;
6721                 break;
6722         default:
6723                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6724                                                         filter_type);
6725                 ret = -EINVAL;
6726                 break;
6727         }
6728
6729         return ret;
6730 }
6731
6732 static u8 *
6733 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6734                         u8 **mc_addr_ptr, u32 *vmdq)
6735 {
6736         u8 *mc_addr;
6737
6738         *vmdq = 0;
6739         mc_addr = *mc_addr_ptr;
6740         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6741         return mc_addr;
6742 }
6743
6744 static int
6745 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6746                           struct ether_addr *mc_addr_set,
6747                           uint32_t nb_mc_addr)
6748 {
6749         struct ixgbe_hw *hw;
6750         u8 *mc_addr_list;
6751
6752         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6753         mc_addr_list = (u8 *)mc_addr_set;
6754         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6755                                          ixgbe_dev_addr_list_itr, TRUE);
6756 }
6757
6758 static uint64_t
6759 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6760 {
6761         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6762         uint64_t systime_cycles;
6763
6764         switch (hw->mac.type) {
6765         case ixgbe_mac_X550:
6766         case ixgbe_mac_X550EM_x:
6767         case ixgbe_mac_X550EM_a:
6768                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6769                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6770                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6771                                 * NSEC_PER_SEC;
6772                 break;
6773         default:
6774                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6775                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6776                                 << 32;
6777         }
6778
6779         return systime_cycles;
6780 }
6781
6782 static uint64_t
6783 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6784 {
6785         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6786         uint64_t rx_tstamp_cycles;
6787
6788         switch (hw->mac.type) {
6789         case ixgbe_mac_X550:
6790         case ixgbe_mac_X550EM_x:
6791         case ixgbe_mac_X550EM_a:
6792                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6793                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6794                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6795                                 * NSEC_PER_SEC;
6796                 break;
6797         default:
6798                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6799                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6800                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6801                                 << 32;
6802         }
6803
6804         return rx_tstamp_cycles;
6805 }
6806
6807 static uint64_t
6808 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6809 {
6810         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6811         uint64_t tx_tstamp_cycles;
6812
6813         switch (hw->mac.type) {
6814         case ixgbe_mac_X550:
6815         case ixgbe_mac_X550EM_x:
6816         case ixgbe_mac_X550EM_a:
6817                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6818                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6819                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6820                                 * NSEC_PER_SEC;
6821                 break;
6822         default:
6823                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6824                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6825                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6826                                 << 32;
6827         }
6828
6829         return tx_tstamp_cycles;
6830 }
6831
6832 static void
6833 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6834 {
6835         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6836         struct ixgbe_adapter *adapter =
6837                 (struct ixgbe_adapter *)dev->data->dev_private;
6838         struct rte_eth_link link;
6839         uint32_t incval = 0;
6840         uint32_t shift = 0;
6841
6842         /* Get current link speed. */
6843         ixgbe_dev_link_update(dev, 1);
6844         rte_eth_linkstatus_get(dev, &link);
6845
6846         switch (link.link_speed) {
6847         case ETH_SPEED_NUM_100M:
6848                 incval = IXGBE_INCVAL_100;
6849                 shift = IXGBE_INCVAL_SHIFT_100;
6850                 break;
6851         case ETH_SPEED_NUM_1G:
6852                 incval = IXGBE_INCVAL_1GB;
6853                 shift = IXGBE_INCVAL_SHIFT_1GB;
6854                 break;
6855         case ETH_SPEED_NUM_10G:
6856         default:
6857                 incval = IXGBE_INCVAL_10GB;
6858                 shift = IXGBE_INCVAL_SHIFT_10GB;
6859                 break;
6860         }
6861
6862         switch (hw->mac.type) {
6863         case ixgbe_mac_X550:
6864         case ixgbe_mac_X550EM_x:
6865         case ixgbe_mac_X550EM_a:
6866                 /* Independent of link speed. */
6867                 incval = 1;
6868                 /* Cycles read will be interpreted as ns. */
6869                 shift = 0;
6870                 /* Fall-through */
6871         case ixgbe_mac_X540:
6872                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6873                 break;
6874         case ixgbe_mac_82599EB:
6875                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6876                 shift -= IXGBE_INCVAL_SHIFT_82599;
6877                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6878                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6879                 break;
6880         default:
6881                 /* Not supported. */
6882                 return;
6883         }
6884
6885         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6886         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6887         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6888
6889         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6890         adapter->systime_tc.cc_shift = shift;
6891         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6892
6893         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6894         adapter->rx_tstamp_tc.cc_shift = shift;
6895         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6896
6897         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6898         adapter->tx_tstamp_tc.cc_shift = shift;
6899         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6900 }
6901
6902 static int
6903 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6904 {
6905         struct ixgbe_adapter *adapter =
6906                         (struct ixgbe_adapter *)dev->data->dev_private;
6907
6908         adapter->systime_tc.nsec += delta;
6909         adapter->rx_tstamp_tc.nsec += delta;
6910         adapter->tx_tstamp_tc.nsec += delta;
6911
6912         return 0;
6913 }
6914
6915 static int
6916 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6917 {
6918         uint64_t ns;
6919         struct ixgbe_adapter *adapter =
6920                         (struct ixgbe_adapter *)dev->data->dev_private;
6921
6922         ns = rte_timespec_to_ns(ts);
6923         /* Set the timecounters to a new value. */
6924         adapter->systime_tc.nsec = ns;
6925         adapter->rx_tstamp_tc.nsec = ns;
6926         adapter->tx_tstamp_tc.nsec = ns;
6927
6928         return 0;
6929 }
6930
6931 static int
6932 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6933 {
6934         uint64_t ns, systime_cycles;
6935         struct ixgbe_adapter *adapter =
6936                         (struct ixgbe_adapter *)dev->data->dev_private;
6937
6938         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6939         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6940         *ts = rte_ns_to_timespec(ns);
6941
6942         return 0;
6943 }
6944
6945 static int
6946 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6947 {
6948         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6949         uint32_t tsync_ctl;
6950         uint32_t tsauxc;
6951
6952         /* Stop the timesync system time. */
6953         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6954         /* Reset the timesync system time value. */
6955         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6956         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6957
6958         /* Enable system time for platforms where it isn't on by default. */
6959         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6960         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6961         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6962
6963         ixgbe_start_timecounters(dev);
6964
6965         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6966         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6967                         (ETHER_TYPE_1588 |
6968                          IXGBE_ETQF_FILTER_EN |
6969                          IXGBE_ETQF_1588));
6970
6971         /* Enable timestamping of received PTP packets. */
6972         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6973         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6974         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6975
6976         /* Enable timestamping of transmitted PTP packets. */
6977         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6978         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6979         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6980
6981         IXGBE_WRITE_FLUSH(hw);
6982
6983         return 0;
6984 }
6985
6986 static int
6987 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6988 {
6989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6990         uint32_t tsync_ctl;
6991
6992         /* Disable timestamping of transmitted PTP packets. */
6993         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6994         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6995         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6996
6997         /* Disable timestamping of received PTP packets. */
6998         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6999         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7000         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7001
7002         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7003         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7004
7005         /* Stop incrementating the System Time registers. */
7006         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7007
7008         return 0;
7009 }
7010
7011 static int
7012 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7013                                  struct timespec *timestamp,
7014                                  uint32_t flags __rte_unused)
7015 {
7016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7017         struct ixgbe_adapter *adapter =
7018                 (struct ixgbe_adapter *)dev->data->dev_private;
7019         uint32_t tsync_rxctl;
7020         uint64_t rx_tstamp_cycles;
7021         uint64_t ns;
7022
7023         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7024         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7025                 return -EINVAL;
7026
7027         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7028         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7029         *timestamp = rte_ns_to_timespec(ns);
7030
7031         return  0;
7032 }
7033
7034 static int
7035 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7036                                  struct timespec *timestamp)
7037 {
7038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7039         struct ixgbe_adapter *adapter =
7040                 (struct ixgbe_adapter *)dev->data->dev_private;
7041         uint32_t tsync_txctl;
7042         uint64_t tx_tstamp_cycles;
7043         uint64_t ns;
7044
7045         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7046         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7047                 return -EINVAL;
7048
7049         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7050         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7051         *timestamp = rte_ns_to_timespec(ns);
7052
7053         return 0;
7054 }
7055
7056 static int
7057 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7058 {
7059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7060         int count = 0;
7061         int g_ind = 0;
7062         const struct reg_info *reg_group;
7063         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7064                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7065
7066         while ((reg_group = reg_set[g_ind++]))
7067                 count += ixgbe_regs_group_count(reg_group);
7068
7069         return count;
7070 }
7071
7072 static int
7073 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7074 {
7075         int count = 0;
7076         int g_ind = 0;
7077         const struct reg_info *reg_group;
7078
7079         while ((reg_group = ixgbevf_regs[g_ind++]))
7080                 count += ixgbe_regs_group_count(reg_group);
7081
7082         return count;
7083 }
7084
7085 static int
7086 ixgbe_get_regs(struct rte_eth_dev *dev,
7087               struct rte_dev_reg_info *regs)
7088 {
7089         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7090         uint32_t *data = regs->data;
7091         int g_ind = 0;
7092         int count = 0;
7093         const struct reg_info *reg_group;
7094         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7095                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7096
7097         if (data == NULL) {
7098                 regs->length = ixgbe_get_reg_length(dev);
7099                 regs->width = sizeof(uint32_t);
7100                 return 0;
7101         }
7102
7103         /* Support only full register dump */
7104         if ((regs->length == 0) ||
7105             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7106                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7107                         hw->device_id;
7108                 while ((reg_group = reg_set[g_ind++]))
7109                         count += ixgbe_read_regs_group(dev, &data[count],
7110                                 reg_group);
7111                 return 0;
7112         }
7113
7114         return -ENOTSUP;
7115 }
7116
7117 static int
7118 ixgbevf_get_regs(struct rte_eth_dev *dev,
7119                 struct rte_dev_reg_info *regs)
7120 {
7121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122         uint32_t *data = regs->data;
7123         int g_ind = 0;
7124         int count = 0;
7125         const struct reg_info *reg_group;
7126
7127         if (data == NULL) {
7128                 regs->length = ixgbevf_get_reg_length(dev);
7129                 regs->width = sizeof(uint32_t);
7130                 return 0;
7131         }
7132
7133         /* Support only full register dump */
7134         if ((regs->length == 0) ||
7135             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7136                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7137                         hw->device_id;
7138                 while ((reg_group = ixgbevf_regs[g_ind++]))
7139                         count += ixgbe_read_regs_group(dev, &data[count],
7140                                                       reg_group);
7141                 return 0;
7142         }
7143
7144         return -ENOTSUP;
7145 }
7146
7147 static int
7148 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7149 {
7150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7151
7152         /* Return unit is byte count */
7153         return hw->eeprom.word_size * 2;
7154 }
7155
7156 static int
7157 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7158                 struct rte_dev_eeprom_info *in_eeprom)
7159 {
7160         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7161         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7162         uint16_t *data = in_eeprom->data;
7163         int first, length;
7164
7165         first = in_eeprom->offset >> 1;
7166         length = in_eeprom->length >> 1;
7167         if ((first > hw->eeprom.word_size) ||
7168             ((first + length) > hw->eeprom.word_size))
7169                 return -EINVAL;
7170
7171         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7172
7173         return eeprom->ops.read_buffer(hw, first, length, data);
7174 }
7175
7176 static int
7177 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7178                 struct rte_dev_eeprom_info *in_eeprom)
7179 {
7180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7181         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7182         uint16_t *data = in_eeprom->data;
7183         int first, length;
7184
7185         first = in_eeprom->offset >> 1;
7186         length = in_eeprom->length >> 1;
7187         if ((first > hw->eeprom.word_size) ||
7188             ((first + length) > hw->eeprom.word_size))
7189                 return -EINVAL;
7190
7191         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7192
7193         return eeprom->ops.write_buffer(hw,  first, length, data);
7194 }
7195
7196 static int
7197 ixgbe_get_module_info(struct rte_eth_dev *dev,
7198                       struct rte_eth_dev_module_info *modinfo)
7199 {
7200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7201         uint32_t status;
7202         uint8_t sff8472_rev, addr_mode;
7203         bool page_swap = false;
7204
7205         /* Check whether we support SFF-8472 or not */
7206         status = hw->phy.ops.read_i2c_eeprom(hw,
7207                                              IXGBE_SFF_SFF_8472_COMP,
7208                                              &sff8472_rev);
7209         if (status != 0)
7210                 return -EIO;
7211
7212         /* addressing mode is not supported */
7213         status = hw->phy.ops.read_i2c_eeprom(hw,
7214                                              IXGBE_SFF_SFF_8472_SWAP,
7215                                              &addr_mode);
7216         if (status != 0)
7217                 return -EIO;
7218
7219         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7220                 PMD_DRV_LOG(ERR,
7221                             "Address change required to access page 0xA2, "
7222                             "but not supported. Please report the module "
7223                             "type to the driver maintainers.");
7224                 page_swap = true;
7225         }
7226
7227         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7228                 /* We have a SFP, but it does not support SFF-8472 */
7229                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7230                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7231         } else {
7232                 /* We have a SFP which supports a revision of SFF-8472. */
7233                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7234                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7235         }
7236
7237         return 0;
7238 }
7239
7240 static int
7241 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7242                         struct rte_dev_eeprom_info *info)
7243 {
7244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7245         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7246         uint8_t databyte = 0xFF;
7247         uint8_t *data = info->data;
7248         uint32_t i = 0;
7249
7250         if (info->length == 0)
7251                 return -EINVAL;
7252
7253         for (i = info->offset; i < info->offset + info->length; i++) {
7254                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7255                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7256                 else
7257                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7258
7259                 if (status != 0)
7260                         return -EIO;
7261
7262                 data[i - info->offset] = databyte;
7263         }
7264
7265         return 0;
7266 }
7267
7268 uint16_t
7269 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7270         switch (mac_type) {
7271         case ixgbe_mac_X550:
7272         case ixgbe_mac_X550EM_x:
7273         case ixgbe_mac_X550EM_a:
7274                 return ETH_RSS_RETA_SIZE_512;
7275         case ixgbe_mac_X550_vf:
7276         case ixgbe_mac_X550EM_x_vf:
7277         case ixgbe_mac_X550EM_a_vf:
7278                 return ETH_RSS_RETA_SIZE_64;
7279         default:
7280                 return ETH_RSS_RETA_SIZE_128;
7281         }
7282 }
7283
7284 uint32_t
7285 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7286         switch (mac_type) {
7287         case ixgbe_mac_X550:
7288         case ixgbe_mac_X550EM_x:
7289         case ixgbe_mac_X550EM_a:
7290                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7291                         return IXGBE_RETA(reta_idx >> 2);
7292                 else
7293                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7294         case ixgbe_mac_X550_vf:
7295         case ixgbe_mac_X550EM_x_vf:
7296         case ixgbe_mac_X550EM_a_vf:
7297                 return IXGBE_VFRETA(reta_idx >> 2);
7298         default:
7299                 return IXGBE_RETA(reta_idx >> 2);
7300         }
7301 }
7302
7303 uint32_t
7304 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7305         switch (mac_type) {
7306         case ixgbe_mac_X550_vf:
7307         case ixgbe_mac_X550EM_x_vf:
7308         case ixgbe_mac_X550EM_a_vf:
7309                 return IXGBE_VFMRQC;
7310         default:
7311                 return IXGBE_MRQC;
7312         }
7313 }
7314
7315 uint32_t
7316 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7317         switch (mac_type) {
7318         case ixgbe_mac_X550_vf:
7319         case ixgbe_mac_X550EM_x_vf:
7320         case ixgbe_mac_X550EM_a_vf:
7321                 return IXGBE_VFRSSRK(i);
7322         default:
7323                 return IXGBE_RSSRK(i);
7324         }
7325 }
7326
7327 bool
7328 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7329         switch (mac_type) {
7330         case ixgbe_mac_82599_vf:
7331         case ixgbe_mac_X540_vf:
7332                 return 0;
7333         default:
7334                 return 1;
7335         }
7336 }
7337
7338 static int
7339 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7340                         struct rte_eth_dcb_info *dcb_info)
7341 {
7342         struct ixgbe_dcb_config *dcb_config =
7343                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7344         struct ixgbe_dcb_tc_config *tc;
7345         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7346         uint8_t nb_tcs;
7347         uint8_t i, j;
7348
7349         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7350                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7351         else
7352                 dcb_info->nb_tcs = 1;
7353
7354         tc_queue = &dcb_info->tc_queue;
7355         nb_tcs = dcb_info->nb_tcs;
7356
7357         if (dcb_config->vt_mode) { /* vt is enabled*/
7358                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7359                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7360                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7361                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7362                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7363                         for (j = 0; j < nb_tcs; j++) {
7364                                 tc_queue->tc_rxq[0][j].base = j;
7365                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7366                                 tc_queue->tc_txq[0][j].base = j;
7367                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7368                         }
7369                 } else {
7370                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7371                                 for (j = 0; j < nb_tcs; j++) {
7372                                         tc_queue->tc_rxq[i][j].base =
7373                                                 i * nb_tcs + j;
7374                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7375                                         tc_queue->tc_txq[i][j].base =
7376                                                 i * nb_tcs + j;
7377                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7378                                 }
7379                         }
7380                 }
7381         } else { /* vt is disabled*/
7382                 struct rte_eth_dcb_rx_conf *rx_conf =
7383                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7384                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7385                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7386                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7387                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7388                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7389                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7390                         }
7391                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7392                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7393                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7394                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7395                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7396                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7397                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7398                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7399                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7400                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7401                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7402                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7403                         }
7404                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7405                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7406                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7407                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7408                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7409                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7410                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7411                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7412                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7413                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7414                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7415                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7416                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7417                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7418                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7419                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7420                 }
7421         }
7422         for (i = 0; i < dcb_info->nb_tcs; i++) {
7423                 tc = &dcb_config->tc_config[i];
7424                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7425         }
7426         return 0;
7427 }
7428
7429 /* Update e-tag ether type */
7430 static int
7431 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7432                             uint16_t ether_type)
7433 {
7434         uint32_t etag_etype;
7435
7436         if (hw->mac.type != ixgbe_mac_X550 &&
7437             hw->mac.type != ixgbe_mac_X550EM_x &&
7438             hw->mac.type != ixgbe_mac_X550EM_a) {
7439                 return -ENOTSUP;
7440         }
7441
7442         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7443         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7444         etag_etype |= ether_type;
7445         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7446         IXGBE_WRITE_FLUSH(hw);
7447
7448         return 0;
7449 }
7450
7451 /* Config l2 tunnel ether type */
7452 static int
7453 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7454                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7455 {
7456         int ret = 0;
7457         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7458         struct ixgbe_l2_tn_info *l2_tn_info =
7459                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7460
7461         if (l2_tunnel == NULL)
7462                 return -EINVAL;
7463
7464         switch (l2_tunnel->l2_tunnel_type) {
7465         case RTE_L2_TUNNEL_TYPE_E_TAG:
7466                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7467                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7468                 break;
7469         default:
7470                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7471                 ret = -EINVAL;
7472                 break;
7473         }
7474
7475         return ret;
7476 }
7477
7478 /* Enable e-tag tunnel */
7479 static int
7480 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7481 {
7482         uint32_t etag_etype;
7483
7484         if (hw->mac.type != ixgbe_mac_X550 &&
7485             hw->mac.type != ixgbe_mac_X550EM_x &&
7486             hw->mac.type != ixgbe_mac_X550EM_a) {
7487                 return -ENOTSUP;
7488         }
7489
7490         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7491         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7492         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7493         IXGBE_WRITE_FLUSH(hw);
7494
7495         return 0;
7496 }
7497
7498 /* Enable l2 tunnel */
7499 static int
7500 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7501                            enum rte_eth_tunnel_type l2_tunnel_type)
7502 {
7503         int ret = 0;
7504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7505         struct ixgbe_l2_tn_info *l2_tn_info =
7506                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7507
7508         switch (l2_tunnel_type) {
7509         case RTE_L2_TUNNEL_TYPE_E_TAG:
7510                 l2_tn_info->e_tag_en = TRUE;
7511                 ret = ixgbe_e_tag_enable(hw);
7512                 break;
7513         default:
7514                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7515                 ret = -EINVAL;
7516                 break;
7517         }
7518
7519         return ret;
7520 }
7521
7522 /* Disable e-tag tunnel */
7523 static int
7524 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7525 {
7526         uint32_t etag_etype;
7527
7528         if (hw->mac.type != ixgbe_mac_X550 &&
7529             hw->mac.type != ixgbe_mac_X550EM_x &&
7530             hw->mac.type != ixgbe_mac_X550EM_a) {
7531                 return -ENOTSUP;
7532         }
7533
7534         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7535         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7536         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7537         IXGBE_WRITE_FLUSH(hw);
7538
7539         return 0;
7540 }
7541
7542 /* Disable l2 tunnel */
7543 static int
7544 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7545                             enum rte_eth_tunnel_type l2_tunnel_type)
7546 {
7547         int ret = 0;
7548         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7549         struct ixgbe_l2_tn_info *l2_tn_info =
7550                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7551
7552         switch (l2_tunnel_type) {
7553         case RTE_L2_TUNNEL_TYPE_E_TAG:
7554                 l2_tn_info->e_tag_en = FALSE;
7555                 ret = ixgbe_e_tag_disable(hw);
7556                 break;
7557         default:
7558                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7559                 ret = -EINVAL;
7560                 break;
7561         }
7562
7563         return ret;
7564 }
7565
7566 static int
7567 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7568                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7569 {
7570         int ret = 0;
7571         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7572         uint32_t i, rar_entries;
7573         uint32_t rar_low, rar_high;
7574
7575         if (hw->mac.type != ixgbe_mac_X550 &&
7576             hw->mac.type != ixgbe_mac_X550EM_x &&
7577             hw->mac.type != ixgbe_mac_X550EM_a) {
7578                 return -ENOTSUP;
7579         }
7580
7581         rar_entries = ixgbe_get_num_rx_addrs(hw);
7582
7583         for (i = 1; i < rar_entries; i++) {
7584                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7585                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7586                 if ((rar_high & IXGBE_RAH_AV) &&
7587                     (rar_high & IXGBE_RAH_ADTYPE) &&
7588                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7589                      l2_tunnel->tunnel_id)) {
7590                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7591                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7592
7593                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7594
7595                         return ret;
7596                 }
7597         }
7598
7599         return ret;
7600 }
7601
7602 static int
7603 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7604                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7605 {
7606         int ret = 0;
7607         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7608         uint32_t i, rar_entries;
7609         uint32_t rar_low, rar_high;
7610
7611         if (hw->mac.type != ixgbe_mac_X550 &&
7612             hw->mac.type != ixgbe_mac_X550EM_x &&
7613             hw->mac.type != ixgbe_mac_X550EM_a) {
7614                 return -ENOTSUP;
7615         }
7616
7617         /* One entry for one tunnel. Try to remove potential existing entry. */
7618         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7619
7620         rar_entries = ixgbe_get_num_rx_addrs(hw);
7621
7622         for (i = 1; i < rar_entries; i++) {
7623                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7624                 if (rar_high & IXGBE_RAH_AV) {
7625                         continue;
7626                 } else {
7627                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7628                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7629                         rar_low = l2_tunnel->tunnel_id;
7630
7631                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7632                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7633
7634                         return ret;
7635                 }
7636         }
7637
7638         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7639                      " Please remove a rule before adding a new one.");
7640         return -EINVAL;
7641 }
7642
7643 static inline struct ixgbe_l2_tn_filter *
7644 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7645                           struct ixgbe_l2_tn_key *key)
7646 {
7647         int ret;
7648
7649         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7650         if (ret < 0)
7651                 return NULL;
7652
7653         return l2_tn_info->hash_map[ret];
7654 }
7655
7656 static inline int
7657 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7658                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7659 {
7660         int ret;
7661
7662         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7663                                &l2_tn_filter->key);
7664
7665         if (ret < 0) {
7666                 PMD_DRV_LOG(ERR,
7667                             "Failed to insert L2 tunnel filter"
7668                             " to hash table %d!",
7669                             ret);
7670                 return ret;
7671         }
7672
7673         l2_tn_info->hash_map[ret] = l2_tn_filter;
7674
7675         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7676
7677         return 0;
7678 }
7679
7680 static inline int
7681 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7682                           struct ixgbe_l2_tn_key *key)
7683 {
7684         int ret;
7685         struct ixgbe_l2_tn_filter *l2_tn_filter;
7686
7687         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7688
7689         if (ret < 0) {
7690                 PMD_DRV_LOG(ERR,
7691                             "No such L2 tunnel filter to delete %d!",
7692                             ret);
7693                 return ret;
7694         }
7695
7696         l2_tn_filter = l2_tn_info->hash_map[ret];
7697         l2_tn_info->hash_map[ret] = NULL;
7698
7699         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7700         rte_free(l2_tn_filter);
7701
7702         return 0;
7703 }
7704
7705 /* Add l2 tunnel filter */
7706 int
7707 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7708                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7709                                bool restore)
7710 {
7711         int ret;
7712         struct ixgbe_l2_tn_info *l2_tn_info =
7713                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7714         struct ixgbe_l2_tn_key key;
7715         struct ixgbe_l2_tn_filter *node;
7716
7717         if (!restore) {
7718                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7719                 key.tn_id = l2_tunnel->tunnel_id;
7720
7721                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7722
7723                 if (node) {
7724                         PMD_DRV_LOG(ERR,
7725                                     "The L2 tunnel filter already exists!");
7726                         return -EINVAL;
7727                 }
7728
7729                 node = rte_zmalloc("ixgbe_l2_tn",
7730                                    sizeof(struct ixgbe_l2_tn_filter),
7731                                    0);
7732                 if (!node)
7733                         return -ENOMEM;
7734
7735                 rte_memcpy(&node->key,
7736                                  &key,
7737                                  sizeof(struct ixgbe_l2_tn_key));
7738                 node->pool = l2_tunnel->pool;
7739                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7740                 if (ret < 0) {
7741                         rte_free(node);
7742                         return ret;
7743                 }
7744         }
7745
7746         switch (l2_tunnel->l2_tunnel_type) {
7747         case RTE_L2_TUNNEL_TYPE_E_TAG:
7748                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7749                 break;
7750         default:
7751                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7752                 ret = -EINVAL;
7753                 break;
7754         }
7755
7756         if ((!restore) && (ret < 0))
7757                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7758
7759         return ret;
7760 }
7761
7762 /* Delete l2 tunnel filter */
7763 int
7764 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7765                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7766 {
7767         int ret;
7768         struct ixgbe_l2_tn_info *l2_tn_info =
7769                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7770         struct ixgbe_l2_tn_key key;
7771
7772         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7773         key.tn_id = l2_tunnel->tunnel_id;
7774         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7775         if (ret < 0)
7776                 return ret;
7777
7778         switch (l2_tunnel->l2_tunnel_type) {
7779         case RTE_L2_TUNNEL_TYPE_E_TAG:
7780                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7781                 break;
7782         default:
7783                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7784                 ret = -EINVAL;
7785                 break;
7786         }
7787
7788         return ret;
7789 }
7790
7791 /**
7792  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7793  * @dev: pointer to rte_eth_dev structure
7794  * @filter_op:operation will be taken.
7795  * @arg: a pointer to specific structure corresponding to the filter_op
7796  */
7797 static int
7798 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7799                                   enum rte_filter_op filter_op,
7800                                   void *arg)
7801 {
7802         int ret;
7803
7804         if (filter_op == RTE_ETH_FILTER_NOP)
7805                 return 0;
7806
7807         if (arg == NULL) {
7808                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7809                             filter_op);
7810                 return -EINVAL;
7811         }
7812
7813         switch (filter_op) {
7814         case RTE_ETH_FILTER_ADD:
7815                 ret = ixgbe_dev_l2_tunnel_filter_add
7816                         (dev,
7817                          (struct rte_eth_l2_tunnel_conf *)arg,
7818                          FALSE);
7819                 break;
7820         case RTE_ETH_FILTER_DELETE:
7821                 ret = ixgbe_dev_l2_tunnel_filter_del
7822                         (dev,
7823                          (struct rte_eth_l2_tunnel_conf *)arg);
7824                 break;
7825         default:
7826                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7827                 ret = -EINVAL;
7828                 break;
7829         }
7830         return ret;
7831 }
7832
7833 static int
7834 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7835 {
7836         int ret = 0;
7837         uint32_t ctrl;
7838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7839
7840         if (hw->mac.type != ixgbe_mac_X550 &&
7841             hw->mac.type != ixgbe_mac_X550EM_x &&
7842             hw->mac.type != ixgbe_mac_X550EM_a) {
7843                 return -ENOTSUP;
7844         }
7845
7846         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7847         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7848         if (en)
7849                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7850         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7851
7852         return ret;
7853 }
7854
7855 /* Enable l2 tunnel forwarding */
7856 static int
7857 ixgbe_dev_l2_tunnel_forwarding_enable
7858         (struct rte_eth_dev *dev,
7859          enum rte_eth_tunnel_type l2_tunnel_type)
7860 {
7861         struct ixgbe_l2_tn_info *l2_tn_info =
7862                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7863         int ret = 0;
7864
7865         switch (l2_tunnel_type) {
7866         case RTE_L2_TUNNEL_TYPE_E_TAG:
7867                 l2_tn_info->e_tag_fwd_en = TRUE;
7868                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7869                 break;
7870         default:
7871                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7872                 ret = -EINVAL;
7873                 break;
7874         }
7875
7876         return ret;
7877 }
7878
7879 /* Disable l2 tunnel forwarding */
7880 static int
7881 ixgbe_dev_l2_tunnel_forwarding_disable
7882         (struct rte_eth_dev *dev,
7883          enum rte_eth_tunnel_type l2_tunnel_type)
7884 {
7885         struct ixgbe_l2_tn_info *l2_tn_info =
7886                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7887         int ret = 0;
7888
7889         switch (l2_tunnel_type) {
7890         case RTE_L2_TUNNEL_TYPE_E_TAG:
7891                 l2_tn_info->e_tag_fwd_en = FALSE;
7892                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7893                 break;
7894         default:
7895                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7896                 ret = -EINVAL;
7897                 break;
7898         }
7899
7900         return ret;
7901 }
7902
7903 static int
7904 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7905                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7906                              bool en)
7907 {
7908         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7909         int ret = 0;
7910         uint32_t vmtir, vmvir;
7911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7912
7913         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7914                 PMD_DRV_LOG(ERR,
7915                             "VF id %u should be less than %u",
7916                             l2_tunnel->vf_id,
7917                             pci_dev->max_vfs);
7918                 return -EINVAL;
7919         }
7920
7921         if (hw->mac.type != ixgbe_mac_X550 &&
7922             hw->mac.type != ixgbe_mac_X550EM_x &&
7923             hw->mac.type != ixgbe_mac_X550EM_a) {
7924                 return -ENOTSUP;
7925         }
7926
7927         if (en)
7928                 vmtir = l2_tunnel->tunnel_id;
7929         else
7930                 vmtir = 0;
7931
7932         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7933
7934         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7935         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7936         if (en)
7937                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7938         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7939
7940         return ret;
7941 }
7942
7943 /* Enable l2 tunnel tag insertion */
7944 static int
7945 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7946                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7947 {
7948         int ret = 0;
7949
7950         switch (l2_tunnel->l2_tunnel_type) {
7951         case RTE_L2_TUNNEL_TYPE_E_TAG:
7952                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7953                 break;
7954         default:
7955                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7956                 ret = -EINVAL;
7957                 break;
7958         }
7959
7960         return ret;
7961 }
7962
7963 /* Disable l2 tunnel tag insertion */
7964 static int
7965 ixgbe_dev_l2_tunnel_insertion_disable
7966         (struct rte_eth_dev *dev,
7967          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7968 {
7969         int ret = 0;
7970
7971         switch (l2_tunnel->l2_tunnel_type) {
7972         case RTE_L2_TUNNEL_TYPE_E_TAG:
7973                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7974                 break;
7975         default:
7976                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7977                 ret = -EINVAL;
7978                 break;
7979         }
7980
7981         return ret;
7982 }
7983
7984 static int
7985 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7986                              bool en)
7987 {
7988         int ret = 0;
7989         uint32_t qde;
7990         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7991
7992         if (hw->mac.type != ixgbe_mac_X550 &&
7993             hw->mac.type != ixgbe_mac_X550EM_x &&
7994             hw->mac.type != ixgbe_mac_X550EM_a) {
7995                 return -ENOTSUP;
7996         }
7997
7998         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7999         if (en)
8000                 qde |= IXGBE_QDE_STRIP_TAG;
8001         else
8002                 qde &= ~IXGBE_QDE_STRIP_TAG;
8003         qde &= ~IXGBE_QDE_READ;
8004         qde |= IXGBE_QDE_WRITE;
8005         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8006
8007         return ret;
8008 }
8009
8010 /* Enable l2 tunnel tag stripping */
8011 static int
8012 ixgbe_dev_l2_tunnel_stripping_enable
8013         (struct rte_eth_dev *dev,
8014          enum rte_eth_tunnel_type l2_tunnel_type)
8015 {
8016         int ret = 0;
8017
8018         switch (l2_tunnel_type) {
8019         case RTE_L2_TUNNEL_TYPE_E_TAG:
8020                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8021                 break;
8022         default:
8023                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8024                 ret = -EINVAL;
8025                 break;
8026         }
8027
8028         return ret;
8029 }
8030
8031 /* Disable l2 tunnel tag stripping */
8032 static int
8033 ixgbe_dev_l2_tunnel_stripping_disable
8034         (struct rte_eth_dev *dev,
8035          enum rte_eth_tunnel_type l2_tunnel_type)
8036 {
8037         int ret = 0;
8038
8039         switch (l2_tunnel_type) {
8040         case RTE_L2_TUNNEL_TYPE_E_TAG:
8041                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8042                 break;
8043         default:
8044                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8045                 ret = -EINVAL;
8046                 break;
8047         }
8048
8049         return ret;
8050 }
8051
8052 /* Enable/disable l2 tunnel offload functions */
8053 static int
8054 ixgbe_dev_l2_tunnel_offload_set
8055         (struct rte_eth_dev *dev,
8056          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8057          uint32_t mask,
8058          uint8_t en)
8059 {
8060         int ret = 0;
8061
8062         if (l2_tunnel == NULL)
8063                 return -EINVAL;
8064
8065         ret = -EINVAL;
8066         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8067                 if (en)
8068                         ret = ixgbe_dev_l2_tunnel_enable(
8069                                 dev,
8070                                 l2_tunnel->l2_tunnel_type);
8071                 else
8072                         ret = ixgbe_dev_l2_tunnel_disable(
8073                                 dev,
8074                                 l2_tunnel->l2_tunnel_type);
8075         }
8076
8077         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8078                 if (en)
8079                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8080                                 dev,
8081                                 l2_tunnel);
8082                 else
8083                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8084                                 dev,
8085                                 l2_tunnel);
8086         }
8087
8088         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8089                 if (en)
8090                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8091                                 dev,
8092                                 l2_tunnel->l2_tunnel_type);
8093                 else
8094                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8095                                 dev,
8096                                 l2_tunnel->l2_tunnel_type);
8097         }
8098
8099         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8100                 if (en)
8101                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8102                                 dev,
8103                                 l2_tunnel->l2_tunnel_type);
8104                 else
8105                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8106                                 dev,
8107                                 l2_tunnel->l2_tunnel_type);
8108         }
8109
8110         return ret;
8111 }
8112
8113 static int
8114 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8115                         uint16_t port)
8116 {
8117         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8118         IXGBE_WRITE_FLUSH(hw);
8119
8120         return 0;
8121 }
8122
8123 /* There's only one register for VxLAN UDP port.
8124  * So, we cannot add several ports. Will update it.
8125  */
8126 static int
8127 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8128                      uint16_t port)
8129 {
8130         if (port == 0) {
8131                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8132                 return -EINVAL;
8133         }
8134
8135         return ixgbe_update_vxlan_port(hw, port);
8136 }
8137
8138 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8139  * UDP port, it must have a value.
8140  * So, will reset it to the original value 0.
8141  */
8142 static int
8143 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8144                      uint16_t port)
8145 {
8146         uint16_t cur_port;
8147
8148         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8149
8150         if (cur_port != port) {
8151                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8152                 return -EINVAL;
8153         }
8154
8155         return ixgbe_update_vxlan_port(hw, 0);
8156 }
8157
8158 /* Add UDP tunneling port */
8159 static int
8160 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8161                               struct rte_eth_udp_tunnel *udp_tunnel)
8162 {
8163         int ret = 0;
8164         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8165
8166         if (hw->mac.type != ixgbe_mac_X550 &&
8167             hw->mac.type != ixgbe_mac_X550EM_x &&
8168             hw->mac.type != ixgbe_mac_X550EM_a) {
8169                 return -ENOTSUP;
8170         }
8171
8172         if (udp_tunnel == NULL)
8173                 return -EINVAL;
8174
8175         switch (udp_tunnel->prot_type) {
8176         case RTE_TUNNEL_TYPE_VXLAN:
8177                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8178                 break;
8179
8180         case RTE_TUNNEL_TYPE_GENEVE:
8181         case RTE_TUNNEL_TYPE_TEREDO:
8182                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8183                 ret = -EINVAL;
8184                 break;
8185
8186         default:
8187                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8188                 ret = -EINVAL;
8189                 break;
8190         }
8191
8192         return ret;
8193 }
8194
8195 /* Remove UDP tunneling port */
8196 static int
8197 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8198                               struct rte_eth_udp_tunnel *udp_tunnel)
8199 {
8200         int ret = 0;
8201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8202
8203         if (hw->mac.type != ixgbe_mac_X550 &&
8204             hw->mac.type != ixgbe_mac_X550EM_x &&
8205             hw->mac.type != ixgbe_mac_X550EM_a) {
8206                 return -ENOTSUP;
8207         }
8208
8209         if (udp_tunnel == NULL)
8210                 return -EINVAL;
8211
8212         switch (udp_tunnel->prot_type) {
8213         case RTE_TUNNEL_TYPE_VXLAN:
8214                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8215                 break;
8216         case RTE_TUNNEL_TYPE_GENEVE:
8217         case RTE_TUNNEL_TYPE_TEREDO:
8218                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8219                 ret = -EINVAL;
8220                 break;
8221         default:
8222                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8223                 ret = -EINVAL;
8224                 break;
8225         }
8226
8227         return ret;
8228 }
8229
8230 static void
8231 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8232 {
8233         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8234
8235         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8236 }
8237
8238 static void
8239 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8240 {
8241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8242
8243         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8244 }
8245
8246 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8247 {
8248         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8249         u32 in_msg = 0;
8250
8251         /* peek the message first */
8252         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8253
8254         /* PF reset VF event */
8255         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8256                 /* dummy mbx read to ack pf */
8257                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8258                         return;
8259                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8260                                               NULL);
8261         }
8262 }
8263
8264 static int
8265 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8266 {
8267         uint32_t eicr;
8268         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8269         struct ixgbe_interrupt *intr =
8270                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8271         ixgbevf_intr_disable(hw);
8272
8273         /* read-on-clear nic registers here */
8274         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8275         intr->flags = 0;
8276
8277         /* only one misc vector supported - mailbox */
8278         eicr &= IXGBE_VTEICR_MASK;
8279         if (eicr == IXGBE_MISC_VEC_ID)
8280                 intr->flags |= IXGBE_FLAG_MAILBOX;
8281
8282         return 0;
8283 }
8284
8285 static int
8286 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8287 {
8288         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8289         struct ixgbe_interrupt *intr =
8290                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8291
8292         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8293                 ixgbevf_mbx_process(dev);
8294                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8295         }
8296
8297         ixgbevf_intr_enable(hw);
8298
8299         return 0;
8300 }
8301
8302 static void
8303 ixgbevf_dev_interrupt_handler(void *param)
8304 {
8305         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8306
8307         ixgbevf_dev_interrupt_get_status(dev);
8308         ixgbevf_dev_interrupt_action(dev);
8309 }
8310
8311 /**
8312  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8313  *  @hw: pointer to hardware structure
8314  *
8315  *  Stops the transmit data path and waits for the HW to internally empty
8316  *  the Tx security block
8317  **/
8318 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8319 {
8320 #define IXGBE_MAX_SECTX_POLL 40
8321
8322         int i;
8323         int sectxreg;
8324
8325         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8326         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8327         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8328         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8329                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8330                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8331                         break;
8332                 /* Use interrupt-safe sleep just in case */
8333                 usec_delay(1000);
8334         }
8335
8336         /* For informational purposes only */
8337         if (i >= IXGBE_MAX_SECTX_POLL)
8338                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8339                          "path fully disabled.  Continuing with init.");
8340
8341         return IXGBE_SUCCESS;
8342 }
8343
8344 /**
8345  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8346  *  @hw: pointer to hardware structure
8347  *
8348  *  Enables the transmit data path.
8349  **/
8350 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8351 {
8352         uint32_t sectxreg;
8353
8354         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8355         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8356         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8357         IXGBE_WRITE_FLUSH(hw);
8358
8359         return IXGBE_SUCCESS;
8360 }
8361
8362 /* restore n-tuple filter */
8363 static inline void
8364 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8365 {
8366         struct ixgbe_filter_info *filter_info =
8367                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8368         struct ixgbe_5tuple_filter *node;
8369
8370         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8371                 ixgbe_inject_5tuple_filter(dev, node);
8372         }
8373 }
8374
8375 /* restore ethernet type filter */
8376 static inline void
8377 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8378 {
8379         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8380         struct ixgbe_filter_info *filter_info =
8381                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8382         int i;
8383
8384         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8385                 if (filter_info->ethertype_mask & (1 << i)) {
8386                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8387                                         filter_info->ethertype_filters[i].etqf);
8388                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8389                                         filter_info->ethertype_filters[i].etqs);
8390                         IXGBE_WRITE_FLUSH(hw);
8391                 }
8392         }
8393 }
8394
8395 /* restore SYN filter */
8396 static inline void
8397 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8398 {
8399         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8400         struct ixgbe_filter_info *filter_info =
8401                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8402         uint32_t synqf;
8403
8404         synqf = filter_info->syn_info;
8405
8406         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8407                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8408                 IXGBE_WRITE_FLUSH(hw);
8409         }
8410 }
8411
8412 /* restore L2 tunnel filter */
8413 static inline void
8414 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8415 {
8416         struct ixgbe_l2_tn_info *l2_tn_info =
8417                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8418         struct ixgbe_l2_tn_filter *node;
8419         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8420
8421         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8422                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8423                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8424                 l2_tn_conf.pool           = node->pool;
8425                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8426         }
8427 }
8428
8429 /* restore rss filter */
8430 static inline void
8431 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8432 {
8433         struct ixgbe_filter_info *filter_info =
8434                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8435
8436         if (filter_info->rss_info.conf.queue_num)
8437                 ixgbe_config_rss_filter(dev,
8438                         &filter_info->rss_info, TRUE);
8439 }
8440
8441 static int
8442 ixgbe_filter_restore(struct rte_eth_dev *dev)
8443 {
8444         ixgbe_ntuple_filter_restore(dev);
8445         ixgbe_ethertype_filter_restore(dev);
8446         ixgbe_syn_filter_restore(dev);
8447         ixgbe_fdir_filter_restore(dev);
8448         ixgbe_l2_tn_filter_restore(dev);
8449         ixgbe_rss_filter_restore(dev);
8450
8451         return 0;
8452 }
8453
8454 static void
8455 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8456 {
8457         struct ixgbe_l2_tn_info *l2_tn_info =
8458                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8459         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8460
8461         if (l2_tn_info->e_tag_en)
8462                 (void)ixgbe_e_tag_enable(hw);
8463
8464         if (l2_tn_info->e_tag_fwd_en)
8465                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8466
8467         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8468 }
8469
8470 /* remove all the n-tuple filters */
8471 void
8472 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8473 {
8474         struct ixgbe_filter_info *filter_info =
8475                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8476         struct ixgbe_5tuple_filter *p_5tuple;
8477
8478         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8479                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8480 }
8481
8482 /* remove all the ether type filters */
8483 void
8484 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8485 {
8486         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8487         struct ixgbe_filter_info *filter_info =
8488                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8489         int i;
8490
8491         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8492                 if (filter_info->ethertype_mask & (1 << i) &&
8493                     !filter_info->ethertype_filters[i].conf) {
8494                         (void)ixgbe_ethertype_filter_remove(filter_info,
8495                                                             (uint8_t)i);
8496                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8497                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8498                         IXGBE_WRITE_FLUSH(hw);
8499                 }
8500         }
8501 }
8502
8503 /* remove the SYN filter */
8504 void
8505 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8506 {
8507         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8508         struct ixgbe_filter_info *filter_info =
8509                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8510
8511         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8512                 filter_info->syn_info = 0;
8513
8514                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8515                 IXGBE_WRITE_FLUSH(hw);
8516         }
8517 }
8518
8519 /* remove all the L2 tunnel filters */
8520 int
8521 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8522 {
8523         struct ixgbe_l2_tn_info *l2_tn_info =
8524                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8525         struct ixgbe_l2_tn_filter *l2_tn_filter;
8526         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8527         int ret = 0;
8528
8529         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8530                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8531                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8532                 l2_tn_conf.pool           = l2_tn_filter->pool;
8533                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8534                 if (ret < 0)
8535                         return ret;
8536         }
8537
8538         return 0;
8539 }
8540
8541 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8542 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8543 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8544 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8545 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8546 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8547
8548 RTE_INIT(ixgbe_init_log);
8549 static void
8550 ixgbe_init_log(void)
8551 {
8552         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8553         if (ixgbe_logtype_init >= 0)
8554                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8555         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8556         if (ixgbe_logtype_driver >= 0)
8557                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8558 }