drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64 #include <rte_hash_crc.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 158 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 168 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 186 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 187 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 188         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 189 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 190         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 191 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 192                                              uint16_t queue_id,
 193                                              uint8_t stat_idx,
 194                                              uint8_t is_rx);
 195 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 196                                  size_t fw_size);
 197 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 198                                struct rte_eth_dev_info *dev_info);
 199 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 200 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 201                                  struct rte_eth_dev_info *dev_info);
 202 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 203
 204 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 205                 uint16_t vlan_id, int on);
 206 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 207                                enum rte_vlan_type vlan_type,
 208                                uint16_t tpid_id);
 209 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 210                 uint16_t queue, bool on);
 211 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 212                 int on);
 213 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 214 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 215 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 216 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 217 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 218
 219 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 221 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 222                                struct rte_eth_fc_conf *fc_conf);
 223 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 224                                struct rte_eth_fc_conf *fc_conf);
 225 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 226                 struct rte_eth_pfc_conf *pfc_conf);
 227 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 228                         struct rte_eth_rss_reta_entry64 *reta_conf,
 229                         uint16_t reta_size);
 230 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 231                         struct rte_eth_rss_reta_entry64 *reta_conf,
 232                         uint16_t reta_size);
 233 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 239                                       struct rte_intr_handle *handle);
 240 static void ixgbe_dev_interrupt_handler(void *param);
 241 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 242 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 243                 uint32_t index, uint32_t pool);
 244 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 245 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 246                                            struct ether_addr *mac_addr);
 247 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 248 static bool is_device_supported(struct rte_eth_dev *dev,
 249                                 struct rte_pci_driver *drv);
 250
 251 /* For Virtual Function support */
 252 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 253 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 254 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 256 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 257 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 258 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 259 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 260 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 261                 struct rte_eth_stats *stats);
 262 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 263 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 264                 uint16_t vlan_id, int on);
 265 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 266                 uint16_t queue, int on);
 267 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 268 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 269 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 270                                             uint16_t queue_id);
 271 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 272                                              uint16_t queue_id);
 273 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 274                                  uint8_t queue, uint8_t msix_vector);
 275 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 276 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 277 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 278
 279 /* For Eth VMDQ APIs support */
 280 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 281                 ether_addr * mac_addr, uint8_t on);
 282 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 284                 struct rte_eth_mirror_conf *mirror_conf,
 285                 uint8_t rule_id, uint8_t on);
 286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 287                 uint8_t rule_id);
 288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 289                                           uint16_t queue_id);
 290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 291                                            uint16_t queue_id);
 292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 293                                uint8_t queue, uint8_t msix_vector);
 294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 295
 296 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 297                 uint16_t queue_idx, uint16_t tx_rate);
 298
 299 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 300                                  struct ether_addr *mac_addr,
 301                                  uint32_t index, uint32_t pool);
 302 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 303 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 304                                              struct ether_addr *mac_addr);
 305 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 306                         struct rte_eth_syn_filter *filter);
 307 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 308                         enum rte_filter_op filter_op,
 309                         void *arg);
 310 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 313                         struct ixgbe_5tuple_filter *filter);
 314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 315                                 enum rte_filter_op filter_op,
 316                                 void *arg);
 317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 318                         struct rte_eth_ntuple_filter *filter);
 319 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 323                         struct rte_eth_ethertype_filter *filter);
 324 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 325                      enum rte_filter_type filter_type,
 326                      enum rte_filter_op filter_op,
 327                      void *arg);
 328 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 329
 330 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 331                                       struct ether_addr *mc_addr_set,
 332                                       uint32_t nb_mc_addr);
 333 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 334                                    struct rte_eth_dcb_info *dcb_info);
 335
 336 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 337 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 338                             struct rte_dev_reg_info *regs);
 339 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 340 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 341                                 struct rte_dev_eeprom_info *eeprom);
 342 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 343                                 struct rte_dev_eeprom_info *eeprom);
 344
 345 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 346 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 347                                 struct rte_dev_reg_info *regs);
 348
 349 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 350 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 351 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 352                                             struct timespec *timestamp,
 353                                             uint32_t flags);
 354 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp);
 356 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 357 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 358                                    struct timespec *timestamp);
 359 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 360                                    const struct timespec *timestamp);
 361 static void ixgbevf_dev_interrupt_handler(void *param);
 362
 363 static int ixgbe_dev_l2_tunnel_eth_type_conf
 364         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 365 static int ixgbe_dev_l2_tunnel_offload_set
 366         (struct rte_eth_dev *dev,
 367          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 368          uint32_t mask,
 369          uint8_t en);
 370 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 371                                              enum rte_filter_op filter_op,
 372                                              void *arg);
 373
 374 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 375                                          struct rte_eth_udp_tunnel *udp_tunnel);
 376 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 377                                          struct rte_eth_udp_tunnel *udp_tunnel);
 378 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 379 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 380
 381 /*
 382  * Define VF Stats MACRO for Non "cleared on read" register
 383  */
 384 #define UPDATE_VF_STAT(reg, last, cur)                          \
 385 {                                                               \
 386         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 387         cur += (latest - last) & UINT_MAX;                      \
 388         last = latest;                                          \
 389 }
 390
 391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 392 {                                                                \
 393         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 394         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 395         u64 latest = ((new_msb << 32) | new_lsb);                \
 396         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 397         last = latest;                                           \
 398 }
 399
 400 #define IXGBE_SET_HWSTRIP(h, q) do {\
 401                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 403                 (h)->bitmap[idx] |= 1 << bit;\
 404         } while (0)
 405
 406 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 407                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 408                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 409                 (h)->bitmap[idx] &= ~(1 << bit);\
 410         } while (0)
 411
 412 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 413                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 414                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 415                 (r) = (h)->bitmap[idx] >> bit & 1;\
 416         } while (0)
 417
 418 /*
 419  * The set of PCI devices this driver supports
 420  */
 421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 475 #ifdef RTE_NIC_BYPASS
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 477 #endif
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 /*
 482  * The set of PCI devices this driver supports (for 82599 VF)
 483  */
 484 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 495         { .vendor_id = 0, /* sentinel */ },
 496 };
 497
 498 static const struct rte_eth_desc_lim rx_desc_lim = {
 499         .nb_max = IXGBE_MAX_RING_DESC,
 500         .nb_min = IXGBE_MIN_RING_DESC,
 501         .nb_align = IXGBE_RXD_ALIGN,
 502 };
 503
 504 static const struct rte_eth_desc_lim tx_desc_lim = {
 505         .nb_max = IXGBE_MAX_RING_DESC,
 506         .nb_min = IXGBE_MIN_RING_DESC,
 507         .nb_align = IXGBE_TXD_ALIGN,
 508         .nb_seg_max = IXGBE_TX_MAX_SEG,
 509         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 510 };
 511
 512 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 513         .dev_configure        = ixgbe_dev_configure,
 514         .dev_start            = ixgbe_dev_start,
 515         .dev_stop             = ixgbe_dev_stop,
 516         .dev_set_link_up    = ixgbe_dev_set_link_up,
 517         .dev_set_link_down  = ixgbe_dev_set_link_down,
 518         .dev_close            = ixgbe_dev_close,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .stats_reset          = ixgbe_dev_stats_reset,
 527         .xstats_reset         = ixgbe_dev_xstats_reset,
 528         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 529         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 530         .fw_version_get       = ixgbe_fw_version_get,
 531         .dev_infos_get        = ixgbe_dev_info_get,
 532         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 533         .mtu_set              = ixgbe_dev_mtu_set,
 534         .vlan_filter_set      = ixgbe_vlan_filter_set,
 535         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 536         .vlan_offload_set     = ixgbe_vlan_offload_set,
 537         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 538         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 539         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 540         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 541         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 542         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 543         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 544         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 545         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 546         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 547         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 548         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 549         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 550         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 551         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 552         .dev_led_on           = ixgbe_dev_led_on,
 553         .dev_led_off          = ixgbe_dev_led_off,
 554         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 555         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 556         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 557         .mac_addr_add         = ixgbe_add_rar,
 558         .mac_addr_remove      = ixgbe_remove_rar,
 559         .mac_addr_set         = ixgbe_set_default_mac_addr,
 560         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 561         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 562         .mirror_rule_set      = ixgbe_mirror_rule_set,
 563         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 564         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 565         .reta_update          = ixgbe_dev_rss_reta_update,
 566         .reta_query           = ixgbe_dev_rss_reta_query,
 567 #ifdef RTE_NIC_BYPASS
 568         .bypass_init          = ixgbe_bypass_init,
 569         .bypass_state_set     = ixgbe_bypass_state_store,
 570         .bypass_state_show    = ixgbe_bypass_state_show,
 571         .bypass_event_set     = ixgbe_bypass_event_store,
 572         .bypass_event_show    = ixgbe_bypass_event_show,
 573         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 574         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 575         .bypass_ver_show      = ixgbe_bypass_ver_show,
 576         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 577 #endif /* RTE_NIC_BYPASS */
 578         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 579         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 580         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 581         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 582         .rxq_info_get         = ixgbe_rxq_info_get,
 583         .txq_info_get         = ixgbe_txq_info_get,
 584         .timesync_enable      = ixgbe_timesync_enable,
 585         .timesync_disable     = ixgbe_timesync_disable,
 586         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 587         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 588         .get_reg              = ixgbe_get_regs,
 589         .get_eeprom_length    = ixgbe_get_eeprom_length,
 590         .get_eeprom           = ixgbe_get_eeprom,
 591         .set_eeprom           = ixgbe_set_eeprom,
 592         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 593         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 594         .timesync_read_time   = ixgbe_timesync_read_time,
 595         .timesync_write_time  = ixgbe_timesync_write_time,
 596         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 597         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 598         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 599         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 600 };
 601
 602 /*
 603  * dev_ops for virtual function, bare necessities for basic vf
 604  * operation have been implemented
 605  */
 606 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 607         .dev_configure        = ixgbevf_dev_configure,
 608         .dev_start            = ixgbevf_dev_start,
 609         .dev_stop             = ixgbevf_dev_stop,
 610         .link_update          = ixgbe_dev_link_update,
 611         .stats_get            = ixgbevf_dev_stats_get,
 612         .xstats_get           = ixgbevf_dev_xstats_get,
 613         .stats_reset          = ixgbevf_dev_stats_reset,
 614         .xstats_reset         = ixgbevf_dev_stats_reset,
 615         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 616         .dev_close            = ixgbevf_dev_close,
 617         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 618         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 619         .dev_infos_get        = ixgbevf_dev_info_get,
 620         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 621         .mtu_set              = ixgbevf_dev_set_mtu,
 622         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 623         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 624         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 625         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 626         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 627         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 628         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 629         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 630         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 631         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 632         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 633         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 634         .mac_addr_add         = ixgbevf_add_mac_addr,
 635         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 636         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 637         .rxq_info_get         = ixgbe_rxq_info_get,
 638         .txq_info_get         = ixgbe_txq_info_get,
 639         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 640         .get_reg              = ixgbevf_get_regs,
 641         .reta_update          = ixgbe_dev_rss_reta_update,
 642         .reta_query           = ixgbe_dev_rss_reta_query,
 643         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 644         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 645 };
 646
 647 /* store statistics names and its offset in stats structure */
 648 struct rte_ixgbe_xstats_name_off {
 649         char name[RTE_ETH_XSTATS_NAME_SIZE];
 650         unsigned offset;
 651 };
 652
 653 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 654         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 655         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 656         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 657         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 658         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 659         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 660         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 661         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 662         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 663         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 664         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 665         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 666         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 667         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 668         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 669                 prc1023)},
 670         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 671                 prc1522)},
 672         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 673         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 674         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 675         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 676         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 677         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 678         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 679         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 680         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 681         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 682         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 683         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 684         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 685         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 686         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 687         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 688         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 689                 ptc1023)},
 690         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 691                 ptc1522)},
 692         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 693         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 694         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 695         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 696
 697         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirustat_add)},
 699         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirustat_remove)},
 701         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 702                 fdirfstat_fadd)},
 703         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 704                 fdirfstat_fremove)},
 705         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirmatch)},
 707         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirmiss)},
 709
 710         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 711         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 712         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 713                 fclast)},
 714         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 715         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 716         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 717         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 718         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 719                 fcoe_noddp)},
 720         {"rx_fcoe_no_direct_data_placement_ext_buff",
 721                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 722
 723         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 724                 lxontxc)},
 725         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 726                 lxonrxc)},
 727         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 728                 lxofftxc)},
 729         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 730                 lxoffrxc)},
 731         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 732 };
 733
 734 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 735                            sizeof(rte_ixgbe_stats_strings[0]))
 736
 737 /* MACsec statistics */
 738 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 739         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 740                 out_pkts_untagged)},
 741         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 742                 out_pkts_encrypted)},
 743         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 744                 out_pkts_protected)},
 745         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 746                 out_octets_encrypted)},
 747         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 748                 out_octets_protected)},
 749         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_untagged)},
 751         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_badtag)},
 753         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_nosci)},
 755         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unknownsci)},
 757         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 758                 in_octets_decrypted)},
 759         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 760                 in_octets_validated)},
 761         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_unchecked)},
 763         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_delayed)},
 765         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_late)},
 767         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_ok)},
 769         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_invalid)},
 771         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_notvalid)},
 773         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_unusedsa)},
 775         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_notusingsa)},
 777 };
 778
 779 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 780                            sizeof(rte_ixgbe_macsec_strings[0]))
 781
 782 /* Per-queue statistics */
 783 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 784         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 785         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 786         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 787         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 788 };
 789
 790 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 791                            sizeof(rte_ixgbe_rxq_strings[0]))
 792 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 793
 794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 795         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 796         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 797         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 798                 pxon2offc)},
 799 };
 800
 801 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 802                            sizeof(rte_ixgbe_txq_strings[0]))
 803 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 804
 805 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 806         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 807 };
 808
 809 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 810                 sizeof(rte_ixgbevf_stats_strings[0]))
 811
 812 /**
 813  * Atomically reads the link status information from global
 814  * structure rte_eth_dev.
 815  *
 816  * @param dev
 817  *   - Pointer to the structure rte_eth_dev to read from.
 818  *   - Pointer to the buffer to be saved with the link status.
 819  *
 820  * @return
 821  *   - On success, zero.
 822  *   - On failure, negative value.
 823  */
 824 static inline int
 825 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 826                                 struct rte_eth_link *link)
 827 {
 828         struct rte_eth_link *dst = link;
 829         struct rte_eth_link *src = &(dev->data->dev_link);
 830
 831         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 832                                         *(uint64_t *)src) == 0)
 833                 return -1;
 834
 835         return 0;
 836 }
 837
 838 /**
 839  * Atomically writes the link status information into global
 840  * structure rte_eth_dev.
 841  *
 842  * @param dev
 843  *   - Pointer to the structure rte_eth_dev to read from.
 844  *   - Pointer to the buffer to be saved with the link status.
 845  *
 846  * @return
 847  *   - On success, zero.
 848  *   - On failure, negative value.
 849  */
 850 static inline int
 851 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 852                                 struct rte_eth_link *link)
 853 {
 854         struct rte_eth_link *dst = &(dev->data->dev_link);
 855         struct rte_eth_link *src = link;
 856
 857         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 858                                         *(uint64_t *)src) == 0)
 859                 return -1;
 860
 861         return 0;
 862 }
 863
 864 /*
 865  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 866  */
 867 static inline int
 868 ixgbe_is_sfp(struct ixgbe_hw *hw)
 869 {
 870         switch (hw->phy.type) {
 871         case ixgbe_phy_sfp_avago:
 872         case ixgbe_phy_sfp_ftl:
 873         case ixgbe_phy_sfp_intel:
 874         case ixgbe_phy_sfp_unknown:
 875         case ixgbe_phy_sfp_passive_tyco:
 876         case ixgbe_phy_sfp_passive_unknown:
 877                 return 1;
 878         default:
 879                 return 0;
 880         }
 881 }
 882
 883 static inline int32_t
 884 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 885 {
 886         uint32_t ctrl_ext;
 887         int32_t status;
 888
 889         status = ixgbe_reset_hw(hw);
 890
 891         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 892         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 893         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 894         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 895         IXGBE_WRITE_FLUSH(hw);
 896
 897         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 898                 status = IXGBE_SUCCESS;
 899         return status;
 900 }
 901
 902 static inline void
 903 ixgbe_enable_intr(struct rte_eth_dev *dev)
 904 {
 905         struct ixgbe_interrupt *intr =
 906                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 907         struct ixgbe_hw *hw =
 908                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 909
 910         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 911         IXGBE_WRITE_FLUSH(hw);
 912 }
 913
 914 /*
 915  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 916  */
 917 static void
 918 ixgbe_disable_intr(struct ixgbe_hw *hw)
 919 {
 920         PMD_INIT_FUNC_TRACE();
 921
 922         if (hw->mac.type == ixgbe_mac_82598EB) {
 923                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 924         } else {
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 927                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 928         }
 929         IXGBE_WRITE_FLUSH(hw);
 930 }
 931
 932 /*
 933  * This function resets queue statistics mapping registers.
 934  * From Niantic datasheet, Initialization of Statistics section:
 935  * "...if software requires the queue counters, the RQSMR and TQSM registers
 936  * must be re-programmed following a device reset.
 937  */
 938 static void
 939 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 940 {
 941         uint32_t i;
 942
 943         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 944                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 946         }
 947 }
 948
 949
 950 static int
 951 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 952                                   uint16_t queue_id,
 953                                   uint8_t stat_idx,
 954                                   uint8_t is_rx)
 955 {
 956 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 957 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 958 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 959
 960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 961         struct ixgbe_stat_mapping_registers *stat_mappings =
 962                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 963         uint32_t qsmr_mask = 0;
 964         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 965         uint32_t q_map;
 966         uint8_t n, offset;
 967
 968         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 969                 (hw->mac.type != ixgbe_mac_X540) &&
 970                 (hw->mac.type != ixgbe_mac_X550) &&
 971                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 972                 (hw->mac.type != ixgbe_mac_X550EM_a))
 973                 return -ENOSYS;
 974
 975         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 976                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 977                      queue_id, stat_idx);
 978
 979         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 980         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 981                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 982                 return -EIO;
 983         }
 984         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 985
 986         /* Now clear any previous stat_idx set */
 987         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 988         if (!is_rx)
 989                 stat_mappings->tqsm[n] &= ~clearing_mask;
 990         else
 991                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 992
 993         q_map = (uint32_t)stat_idx;
 994         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 995         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 996         if (!is_rx)
 997                 stat_mappings->tqsm[n] |= qsmr_mask;
 998         else
 999                 stat_mappings->rqsmr[n] |= qsmr_mask;
1000
1001         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1002                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1003                      queue_id, stat_idx);
1004         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1005                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1006
1007         /* Now write the mapping in the appropriate register */
1008         if (is_rx) {
1009                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1010                              stat_mappings->rqsmr[n], n);
1011                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1012         } else {
1013                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1014                              stat_mappings->tqsm[n], n);
1015                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1016         }
1017         return 0;
1018 }
1019
1020 static void
1021 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1022 {
1023         struct ixgbe_stat_mapping_registers *stat_mappings =
1024                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026         int i;
1027
1028         /* write whatever was in stat mapping table to the NIC */
1029         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1030                 /* rx */
1031                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1032
1033                 /* tx */
1034                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1035         }
1036 }
1037
1038 static void
1039 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1040 {
1041         uint8_t i;
1042         struct ixgbe_dcb_tc_config *tc;
1043         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1044
1045         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1046         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1047         for (i = 0; i < dcb_max_tc; i++) {
1048                 tc = &dcb_config->tc_config[i];
1049                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1050                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1051                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1052                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1053                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1054                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1055                 tc->pfc = ixgbe_dcb_pfc_disabled;
1056         }
1057
1058         /* Initialize default user to priority mapping, UPx->TC0 */
1059         tc = &dcb_config->tc_config[0];
1060         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1061         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1062         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1063                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1064                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1065         }
1066         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1067         dcb_config->pfc_mode_enable = false;
1068         dcb_config->vt_mode = true;
1069         dcb_config->round_robin_enable = false;
1070         /* support all DCB capabilities in 82599 */
1071         dcb_config->support.capabilities = 0xFF;
1072
1073         /*we only support 4 Tcs for X540, X550 */
1074         if (hw->mac.type == ixgbe_mac_X540 ||
1075                 hw->mac.type == ixgbe_mac_X550 ||
1076                 hw->mac.type == ixgbe_mac_X550EM_x ||
1077                 hw->mac.type == ixgbe_mac_X550EM_a) {
1078                 dcb_config->num_tcs.pg_tcs = 4;
1079                 dcb_config->num_tcs.pfc_tcs = 4;
1080         }
1081 }
1082
1083 /*
1084  * Ensure that all locks are released before first NVM or PHY access
1085  */
1086 static void
1087 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1088 {
1089         uint16_t mask;
1090
1091         /*
1092          * Phy lock should not fail in this early stage. If this is the case,
1093          * it is due to an improper exit of the application.
1094          * So force the release of the faulty lock. Release of common lock
1095          * is done automatically by swfw_sync function.
1096          */
1097         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1098         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1099                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1100         }
1101         ixgbe_release_swfw_semaphore(hw, mask);
1102
1103         /*
1104          * These ones are more tricky since they are common to all ports; but
1105          * swfw_sync retries last long enough (1s) to be almost sure that if
1106          * lock can not be taken it is due to an improper lock of the
1107          * semaphore.
1108          */
1109         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1110         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1111                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1112         }
1113         ixgbe_release_swfw_semaphore(hw, mask);
1114 }
1115
1116 /*
1117  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1118  * It returns 0 on success.
1119  */
1120 static int
1121 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1122 {
1123         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1124         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1125         struct ixgbe_hw *hw =
1126                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1127         struct ixgbe_vfta *shadow_vfta =
1128                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1129         struct ixgbe_hwstrip *hwstrip =
1130                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1131         struct ixgbe_dcb_config *dcb_config =
1132                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1133         struct ixgbe_filter_info *filter_info =
1134                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1135         struct ixgbe_bw_conf *bw_conf =
1136                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1137         uint32_t ctrl_ext;
1138         uint16_t csum;
1139         int diag, i;
1140
1141         PMD_INIT_FUNC_TRACE();
1142
1143         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1144         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1145         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1146         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1147
1148         /*
1149          * For secondary processes, we don't initialise any further as primary
1150          * has already done this work. Only check we don't need a different
1151          * RX and TX function.
1152          */
1153         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1154                 struct ixgbe_tx_queue *txq;
1155                 /* TX queue function in primary, set by last queue initialized
1156                  * Tx queue may not initialized by primary process
1157                  */
1158                 if (eth_dev->data->tx_queues) {
1159                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1160                         ixgbe_set_tx_function(eth_dev, txq);
1161                 } else {
1162                         /* Use default TX function if we get here */
1163                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1164                                      "Using default TX function.");
1165                 }
1166
1167                 ixgbe_set_rx_function(eth_dev);
1168
1169                 return 0;
1170         }
1171
1172         rte_eth_copy_pci_info(eth_dev, pci_dev);
1173         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1174
1175         /* Vendor and Device ID need to be set before init of shared code */
1176         hw->device_id = pci_dev->id.device_id;
1177         hw->vendor_id = pci_dev->id.vendor_id;
1178         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1179         hw->allow_unsupported_sfp = 1;
1180
1181         /* Initialize the shared code (base driver) */
1182 #ifdef RTE_NIC_BYPASS
1183         diag = ixgbe_bypass_init_shared_code(hw);
1184 #else
1185         diag = ixgbe_init_shared_code(hw);
1186 #endif /* RTE_NIC_BYPASS */
1187
1188         if (diag != IXGBE_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1190                 return -EIO;
1191         }
1192
1193         /* pick up the PCI bus settings for reporting later */
1194         ixgbe_get_bus_info(hw);
1195
1196         /* Unlock any pending hardware semaphore */
1197         ixgbe_swfw_lock_reset(hw);
1198
1199         /* Initialize DCB configuration*/
1200         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1201         ixgbe_dcb_init(hw, dcb_config);
1202         /* Get Hardware Flow Control setting */
1203         hw->fc.requested_mode = ixgbe_fc_full;
1204         hw->fc.current_mode = ixgbe_fc_full;
1205         hw->fc.pause_time = IXGBE_FC_PAUSE;
1206         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1207                 hw->fc.low_water[i] = IXGBE_FC_LO;
1208                 hw->fc.high_water[i] = IXGBE_FC_HI;
1209         }
1210         hw->fc.send_xon = 1;
1211
1212         /* Make sure we have a good EEPROM before we read from it */
1213         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1214         if (diag != IXGBE_SUCCESS) {
1215                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1216                 return -EIO;
1217         }
1218
1219 #ifdef RTE_NIC_BYPASS
1220         diag = ixgbe_bypass_init_hw(hw);
1221 #else
1222         diag = ixgbe_init_hw(hw);
1223 #endif /* RTE_NIC_BYPASS */
1224
1225         /*
1226          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1227          * is called too soon after the kernel driver unbinding/binding occurs.
1228          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1229          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1230          * also called. See ixgbe_identify_phy_82599(). The reason for the
1231          * failure is not known, and only occuts when virtualisation features
1232          * are disabled in the bios. A delay of 100ms  was found to be enough by
1233          * trial-and-error, and is doubled to be safe.
1234          */
1235         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1236                 rte_delay_ms(200);
1237                 diag = ixgbe_init_hw(hw);
1238         }
1239
1240         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1241                 diag = IXGBE_SUCCESS;
1242
1243         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1244                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1245                              "LOM.  Please be aware there may be issues associated "
1246                              "with your hardware.");
1247                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1248                              "please contact your Intel or hardware representative "
1249                              "who provided you with this hardware.");
1250         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1251                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1252         if (diag) {
1253                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1254                 return -EIO;
1255         }
1256
1257         /* Reset the hw statistics */
1258         ixgbe_dev_stats_reset(eth_dev);
1259
1260         /* disable interrupt */
1261         ixgbe_disable_intr(hw);
1262
1263         /* reset mappings for queue statistics hw counters*/
1264         ixgbe_reset_qstat_mappings(hw);
1265
1266         /* Allocate memory for storing MAC addresses */
1267         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1268                                                hw->mac.num_rar_entries, 0);
1269         if (eth_dev->data->mac_addrs == NULL) {
1270                 PMD_INIT_LOG(ERR,
1271                              "Failed to allocate %u bytes needed to store "
1272                              "MAC addresses",
1273                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1274                 return -ENOMEM;
1275         }
1276         /* Copy the permanent MAC address */
1277         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1278                         &eth_dev->data->mac_addrs[0]);
1279
1280         /* Allocate memory for storing hash filter MAC addresses */
1281         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1282                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1283         if (eth_dev->data->hash_mac_addrs == NULL) {
1284                 PMD_INIT_LOG(ERR,
1285                              "Failed to allocate %d bytes needed to store MAC addresses",
1286                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1287                 return -ENOMEM;
1288         }
1289
1290         /* initialize the vfta */
1291         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1292
1293         /* initialize the hw strip bitmap*/
1294         memset(hwstrip, 0, sizeof(*hwstrip));
1295
1296         /* initialize PF if max_vfs not zero */
1297         ixgbe_pf_host_init(eth_dev);
1298
1299         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1300         /* let hardware know driver is loaded */
1301         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1302         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1303         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1304         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1305         IXGBE_WRITE_FLUSH(hw);
1306
1307         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1308                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1309                              (int) hw->mac.type, (int) hw->phy.type,
1310                              (int) hw->phy.sfp_type);
1311         else
1312                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1313                              (int) hw->mac.type, (int) hw->phy.type);
1314
1315         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1316                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1317                      pci_dev->id.device_id);
1318
1319         rte_intr_callback_register(intr_handle,
1320                                    ixgbe_dev_interrupt_handler, eth_dev);
1321
1322         /* enable uio/vfio intr/eventfd mapping */
1323         rte_intr_enable(intr_handle);
1324
1325         /* enable support intr */
1326         ixgbe_enable_intr(eth_dev);
1327
1328         /* initialize filter info */
1329         memset(filter_info, 0,
1330                sizeof(struct ixgbe_filter_info));
1331
1332         /* initialize 5tuple filter list */
1333         TAILQ_INIT(&filter_info->fivetuple_list);
1334
1335         /* initialize flow director filter list & hash */
1336         ixgbe_fdir_filter_init(eth_dev);
1337
1338         /* initialize l2 tunnel filter list & hash */
1339         ixgbe_l2_tn_filter_init(eth_dev);
1340
1341         TAILQ_INIT(&filter_ntuple_list);
1342         TAILQ_INIT(&filter_ethertype_list);
1343         TAILQ_INIT(&filter_syn_list);
1344         TAILQ_INIT(&filter_fdir_list);
1345         TAILQ_INIT(&filter_l2_tunnel_list);
1346         TAILQ_INIT(&ixgbe_flow_list);
1347
1348         /* initialize bandwidth configuration info */
1349         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1350
1351         return 0;
1352 }
1353
1354 static int
1355 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1356 {
1357         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1358         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1359         struct ixgbe_hw *hw;
1360
1361         PMD_INIT_FUNC_TRACE();
1362
1363         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1364                 return -EPERM;
1365
1366         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1367
1368         if (hw->adapter_stopped == 0)
1369                 ixgbe_dev_close(eth_dev);
1370
1371         eth_dev->dev_ops = NULL;
1372         eth_dev->rx_pkt_burst = NULL;
1373         eth_dev->tx_pkt_burst = NULL;
1374
1375         /* Unlock any pending hardware semaphore */
1376         ixgbe_swfw_lock_reset(hw);
1377
1378         /* disable uio intr before callback unregister */
1379         rte_intr_disable(intr_handle);
1380         rte_intr_callback_unregister(intr_handle,
1381                                      ixgbe_dev_interrupt_handler, eth_dev);
1382
1383         /* uninitialize PF if max_vfs not zero */
1384         ixgbe_pf_host_uninit(eth_dev);
1385
1386         rte_free(eth_dev->data->mac_addrs);
1387         eth_dev->data->mac_addrs = NULL;
1388
1389         rte_free(eth_dev->data->hash_mac_addrs);
1390         eth_dev->data->hash_mac_addrs = NULL;
1391
1392         /* remove all the fdir filters & hash */
1393         ixgbe_fdir_filter_uninit(eth_dev);
1394
1395         /* remove all the L2 tunnel filters & hash */
1396         ixgbe_l2_tn_filter_uninit(eth_dev);
1397
1398         /* Remove all ntuple filters of the device */
1399         ixgbe_ntuple_filter_uninit(eth_dev);
1400
1401         /* clear all the filters list */
1402         ixgbe_filterlist_flush();
1403
1404         return 0;
1405 }
1406
1407 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1408 {
1409         struct ixgbe_filter_info *filter_info =
1410                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1411         struct ixgbe_5tuple_filter *p_5tuple;
1412
1413         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1414                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1415                              p_5tuple,
1416                              entries);
1417                 rte_free(p_5tuple);
1418         }
1419         memset(filter_info->fivetuple_mask, 0,
1420                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1421
1422         return 0;
1423 }
1424
1425 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1426 {
1427         struct ixgbe_hw_fdir_info *fdir_info =
1428                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1429         struct ixgbe_fdir_filter *fdir_filter;
1430
1431                 if (fdir_info->hash_map)
1432                 rte_free(fdir_info->hash_map);
1433         if (fdir_info->hash_handle)
1434                 rte_hash_free(fdir_info->hash_handle);
1435
1436         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1437                 TAILQ_REMOVE(&fdir_info->fdir_list,
1438                              fdir_filter,
1439                              entries);
1440                 rte_free(fdir_filter);
1441         }
1442
1443         return 0;
1444 }
1445
1446 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1447 {
1448         struct ixgbe_l2_tn_info *l2_tn_info =
1449                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1450         struct ixgbe_l2_tn_filter *l2_tn_filter;
1451
1452         if (l2_tn_info->hash_map)
1453                 rte_free(l2_tn_info->hash_map);
1454         if (l2_tn_info->hash_handle)
1455                 rte_hash_free(l2_tn_info->hash_handle);
1456
1457         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1458                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1459                              l2_tn_filter,
1460                              entries);
1461                 rte_free(l2_tn_filter);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1468 {
1469         struct ixgbe_hw_fdir_info *fdir_info =
1470                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1471         char fdir_hash_name[RTE_HASH_NAMESIZE];
1472         struct rte_hash_parameters fdir_hash_params = {
1473                 .name = fdir_hash_name,
1474                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1475                 .key_len = sizeof(union ixgbe_atr_input),
1476                 .hash_func = rte_hash_crc,
1477                 .hash_func_init_val = 0,
1478                 .socket_id = rte_socket_id(),
1479         };
1480
1481         TAILQ_INIT(&fdir_info->fdir_list);
1482         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1483                  "fdir_%s", eth_dev->data->name);
1484         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1485         if (!fdir_info->hash_handle) {
1486                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1487                 return -EINVAL;
1488         }
1489         fdir_info->hash_map = rte_zmalloc("ixgbe",
1490                                           sizeof(struct ixgbe_fdir_filter *) *
1491                                           IXGBE_MAX_FDIR_FILTER_NUM,
1492                                           0);
1493         if (!fdir_info->hash_map) {
1494                 PMD_INIT_LOG(ERR,
1495                              "Failed to allocate memory for fdir hash map!");
1496                 return -ENOMEM;
1497         }
1498         fdir_info->mask_added = FALSE;
1499
1500         return 0;
1501 }
1502
1503 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1504 {
1505         struct ixgbe_l2_tn_info *l2_tn_info =
1506                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1507         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1508         struct rte_hash_parameters l2_tn_hash_params = {
1509                 .name = l2_tn_hash_name,
1510                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1511                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1512                 .hash_func = rte_hash_crc,
1513                 .hash_func_init_val = 0,
1514                 .socket_id = rte_socket_id(),
1515         };
1516
1517         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1518         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1519                  "l2_tn_%s", eth_dev->data->name);
1520         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1521         if (!l2_tn_info->hash_handle) {
1522                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1523                 return -EINVAL;
1524         }
1525         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1526                                    sizeof(struct ixgbe_l2_tn_filter *) *
1527                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1528                                    0);
1529         if (!l2_tn_info->hash_map) {
1530                 PMD_INIT_LOG(ERR,
1531                         "Failed to allocate memory for L2 TN hash map!");
1532                 return -ENOMEM;
1533         }
1534         l2_tn_info->e_tag_en = FALSE;
1535         l2_tn_info->e_tag_fwd_en = FALSE;
1536         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1537
1538         return 0;
1539 }
1540 /*
1541  * Negotiate mailbox API version with the PF.
1542  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1543  * Then we try to negotiate starting with the most recent one.
1544  * If all negotiation attempts fail, then we will proceed with
1545  * the default one (ixgbe_mbox_api_10).
1546  */
1547 static void
1548 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1549 {
1550         int32_t i;
1551
1552         /* start with highest supported, proceed down */
1553         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1554                 ixgbe_mbox_api_12,
1555                 ixgbe_mbox_api_11,
1556                 ixgbe_mbox_api_10,
1557         };
1558
1559         for (i = 0;
1560                         i != RTE_DIM(sup_ver) &&
1561                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1562                         i++)
1563                 ;
1564 }
1565
1566 static void
1567 generate_random_mac_addr(struct ether_addr *mac_addr)
1568 {
1569         uint64_t random;
1570
1571         /* Set Organizationally Unique Identifier (OUI) prefix. */
1572         mac_addr->addr_bytes[0] = 0x00;
1573         mac_addr->addr_bytes[1] = 0x09;
1574         mac_addr->addr_bytes[2] = 0xC0;
1575         /* Force indication of locally assigned MAC address. */
1576         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1577         /* Generate the last 3 bytes of the MAC address with a random number. */
1578         random = rte_rand();
1579         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1580 }
1581
1582 /*
1583  * Virtual Function device init
1584  */
1585 static int
1586 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1587 {
1588         int diag;
1589         uint32_t tc, tcs;
1590         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1591         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1592         struct ixgbe_hw *hw =
1593                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1594         struct ixgbe_vfta *shadow_vfta =
1595                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1596         struct ixgbe_hwstrip *hwstrip =
1597                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1598         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1603         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1604         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1605
1606         /* for secondary processes, we don't initialise any further as primary
1607          * has already done this work. Only check we don't need a different
1608          * RX function
1609          */
1610         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1611                 struct ixgbe_tx_queue *txq;
1612                 /* TX queue function in primary, set by last queue initialized
1613                  * Tx queue may not initialized by primary process
1614                  */
1615                 if (eth_dev->data->tx_queues) {
1616                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1617                         ixgbe_set_tx_function(eth_dev, txq);
1618                 } else {
1619                         /* Use default TX function if we get here */
1620                         PMD_INIT_LOG(NOTICE,
1621                                      "No TX queues configured yet. Using default TX function.");
1622                 }
1623
1624                 ixgbe_set_rx_function(eth_dev);
1625
1626                 return 0;
1627         }
1628
1629         rte_eth_copy_pci_info(eth_dev, pci_dev);
1630         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1631
1632         hw->device_id = pci_dev->id.device_id;
1633         hw->vendor_id = pci_dev->id.vendor_id;
1634         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1635
1636         /* initialize the vfta */
1637         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1638
1639         /* initialize the hw strip bitmap*/
1640         memset(hwstrip, 0, sizeof(*hwstrip));
1641
1642         /* Initialize the shared code (base driver) */
1643         diag = ixgbe_init_shared_code(hw);
1644         if (diag != IXGBE_SUCCESS) {
1645                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1646                 return -EIO;
1647         }
1648
1649         /* init_mailbox_params */
1650         hw->mbx.ops.init_params(hw);
1651
1652         /* Reset the hw statistics */
1653         ixgbevf_dev_stats_reset(eth_dev);
1654
1655         /* Disable the interrupts for VF */
1656         ixgbevf_intr_disable(hw);
1657
1658         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1659         diag = hw->mac.ops.reset_hw(hw);
1660
1661         /*
1662          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1663          * the underlying PF driver has not assigned a MAC address to the VF.
1664          * In this case, assign a random MAC address.
1665          */
1666         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return diag;
1669         }
1670
1671         /* negotiate mailbox API version to use with the PF. */
1672         ixgbevf_negotiate_api(hw);
1673
1674         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1675         ixgbevf_get_queues(hw, &tcs, &tc);
1676
1677         /* Allocate memory for storing MAC addresses */
1678         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1679                                                hw->mac.num_rar_entries, 0);
1680         if (eth_dev->data->mac_addrs == NULL) {
1681                 PMD_INIT_LOG(ERR,
1682                              "Failed to allocate %u bytes needed to store "
1683                              "MAC addresses",
1684                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1685                 return -ENOMEM;
1686         }
1687
1688         /* Generate a random MAC address, if none was assigned by PF. */
1689         if (is_zero_ether_addr(perm_addr)) {
1690                 generate_random_mac_addr(perm_addr);
1691                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1692                 if (diag) {
1693                         rte_free(eth_dev->data->mac_addrs);
1694                         eth_dev->data->mac_addrs = NULL;
1695                         return diag;
1696                 }
1697                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1698                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1699                              "%02x:%02x:%02x:%02x:%02x:%02x",
1700                              perm_addr->addr_bytes[0],
1701                              perm_addr->addr_bytes[1],
1702                              perm_addr->addr_bytes[2],
1703                              perm_addr->addr_bytes[3],
1704                              perm_addr->addr_bytes[4],
1705                              perm_addr->addr_bytes[5]);
1706         }
1707
1708         /* Copy the permanent MAC address */
1709         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1710
1711         /* reset the hardware with the new settings */
1712         diag = hw->mac.ops.start_hw(hw);
1713         switch (diag) {
1714         case  0:
1715                 break;
1716
1717         default:
1718                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1719                 return -EIO;
1720         }
1721
1722         rte_intr_callback_register(intr_handle,
1723                                    ixgbevf_dev_interrupt_handler, eth_dev);
1724         rte_intr_enable(intr_handle);
1725         ixgbevf_intr_enable(hw);
1726
1727         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1728                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1729                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1730
1731         return 0;
1732 }
1733
1734 /* Virtual Function device uninit */
1735
1736 static int
1737 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1738 {
1739         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1740         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741         struct ixgbe_hw *hw;
1742
1743         PMD_INIT_FUNC_TRACE();
1744
1745         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1746                 return -EPERM;
1747
1748         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1749
1750         if (hw->adapter_stopped == 0)
1751                 ixgbevf_dev_close(eth_dev);
1752
1753         eth_dev->dev_ops = NULL;
1754         eth_dev->rx_pkt_burst = NULL;
1755         eth_dev->tx_pkt_burst = NULL;
1756
1757         /* Disable the interrupts for VF */
1758         ixgbevf_intr_disable(hw);
1759
1760         rte_free(eth_dev->data->mac_addrs);
1761         eth_dev->data->mac_addrs = NULL;
1762
1763         rte_intr_disable(intr_handle);
1764         rte_intr_callback_unregister(intr_handle,
1765                                      ixgbevf_dev_interrupt_handler, eth_dev);
1766
1767         return 0;
1768 }
1769
1770 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1771         struct rte_pci_device *pci_dev)
1772 {
1773         return rte_eth_dev_pci_generic_probe(pci_dev,
1774                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1775 }
1776
1777 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1778 {
1779         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1780 }
1781
1782 static struct rte_pci_driver rte_ixgbe_pmd = {
1783         .id_table = pci_id_ixgbe_map,
1784         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1785         .probe = eth_ixgbe_pci_probe,
1786         .remove = eth_ixgbe_pci_remove,
1787 };
1788
1789 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1790         struct rte_pci_device *pci_dev)
1791 {
1792         return rte_eth_dev_pci_generic_probe(pci_dev,
1793                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1794 }
1795
1796 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1797 {
1798         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1799 }
1800
1801 /*
1802  * virtual function driver struct
1803  */
1804 static struct rte_pci_driver rte_ixgbevf_pmd = {
1805         .id_table = pci_id_ixgbevf_map,
1806         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1807         .probe = eth_ixgbevf_pci_probe,
1808         .remove = eth_ixgbevf_pci_remove,
1809 };
1810
1811 static int
1812 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1813 {
1814         struct ixgbe_hw *hw =
1815                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816         struct ixgbe_vfta *shadow_vfta =
1817                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1818         uint32_t vfta;
1819         uint32_t vid_idx;
1820         uint32_t vid_bit;
1821
1822         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1823         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1824         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1825         if (on)
1826                 vfta |= vid_bit;
1827         else
1828                 vfta &= ~vid_bit;
1829         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1830
1831         /* update local VFTA copy */
1832         shadow_vfta->vfta[vid_idx] = vfta;
1833
1834         return 0;
1835 }
1836
1837 static void
1838 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1839 {
1840         if (on)
1841                 ixgbe_vlan_hw_strip_enable(dev, queue);
1842         else
1843                 ixgbe_vlan_hw_strip_disable(dev, queue);
1844 }
1845
1846 static int
1847 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1848                     enum rte_vlan_type vlan_type,
1849                     uint16_t tpid)
1850 {
1851         struct ixgbe_hw *hw =
1852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         int ret = 0;
1854         uint32_t reg;
1855         uint32_t qinq;
1856
1857         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1858         qinq &= IXGBE_DMATXCTL_GDV;
1859
1860         switch (vlan_type) {
1861         case ETH_VLAN_TYPE_INNER:
1862                 if (qinq) {
1863                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1864                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1865                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1866                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1868                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1869                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1870                 } else {
1871                         ret = -ENOTSUP;
1872                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1873                                     " by single VLAN");
1874                 }
1875                 break;
1876         case ETH_VLAN_TYPE_OUTER:
1877                 if (qinq) {
1878                         /* Only the high 16-bits is valid */
1879                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1880                                         IXGBE_EXVET_VET_EXT_SHIFT);
1881                 } else {
1882                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1889                 }
1890
1891                 break;
1892         default:
1893                 ret = -EINVAL;
1894                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1895                 break;
1896         }
1897
1898         return ret;
1899 }
1900
1901 void
1902 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1903 {
1904         struct ixgbe_hw *hw =
1905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1906         uint32_t vlnctrl;
1907
1908         PMD_INIT_FUNC_TRACE();
1909
1910         /* Filter Table Disable */
1911         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1913
1914         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1915 }
1916
1917 void
1918 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct ixgbe_vfta *shadow_vfta =
1923                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1924         uint32_t vlnctrl;
1925         uint16_t i;
1926
1927         PMD_INIT_FUNC_TRACE();
1928
1929         /* Filter Table Enable */
1930         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1932         vlnctrl |= IXGBE_VLNCTRL_VFE;
1933
1934         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1935
1936         /* write whatever is in local vfta copy */
1937         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1938                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1939 }
1940
1941 static void
1942 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1943 {
1944         struct ixgbe_hwstrip *hwstrip =
1945                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1946         struct ixgbe_rx_queue *rxq;
1947
1948         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1949                 return;
1950
1951         if (on)
1952                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1953         else
1954                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1955
1956         if (queue >= dev->data->nb_rx_queues)
1957                 return;
1958
1959         rxq = dev->data->rx_queues[queue];
1960
1961         if (on)
1962                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1963         else
1964                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1965 }
1966
1967 static void
1968 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1969 {
1970         struct ixgbe_hw *hw =
1971                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972         uint32_t ctrl;
1973
1974         PMD_INIT_FUNC_TRACE();
1975
1976         if (hw->mac.type == ixgbe_mac_82598EB) {
1977                 /* No queue level support */
1978                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1979                 return;
1980         }
1981
1982         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1983         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1984         ctrl &= ~IXGBE_RXDCTL_VME;
1985         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1986
1987         /* record those setting for HW strip per queue */
1988         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1989 }
1990
1991 static void
1992 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1993 {
1994         struct ixgbe_hw *hw =
1995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996         uint32_t ctrl;
1997
1998         PMD_INIT_FUNC_TRACE();
1999
2000         if (hw->mac.type == ixgbe_mac_82598EB) {
2001                 /* No queue level supported */
2002                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2003                 return;
2004         }
2005
2006         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2007         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2008         ctrl |= IXGBE_RXDCTL_VME;
2009         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2010
2011         /* record those setting for HW strip per queue */
2012         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2013 }
2014
2015 void
2016 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2017 {
2018         struct ixgbe_hw *hw =
2019                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2020         uint32_t ctrl;
2021         uint16_t i;
2022         struct ixgbe_rx_queue *rxq;
2023
2024         PMD_INIT_FUNC_TRACE();
2025
2026         if (hw->mac.type == ixgbe_mac_82598EB) {
2027                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2028                 ctrl &= ~IXGBE_VLNCTRL_VME;
2029                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2030         } else {
2031                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2032                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2033                         rxq = dev->data->rx_queues[i];
2034                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2035                         ctrl &= ~IXGBE_RXDCTL_VME;
2036                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2037
2038                         /* record those setting for HW strip per queue */
2039                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2040                 }
2041         }
2042 }
2043
2044 void
2045 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2046 {
2047         struct ixgbe_hw *hw =
2048                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2049         uint32_t ctrl;
2050         uint16_t i;
2051         struct ixgbe_rx_queue *rxq;
2052
2053         PMD_INIT_FUNC_TRACE();
2054
2055         if (hw->mac.type == ixgbe_mac_82598EB) {
2056                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2057                 ctrl |= IXGBE_VLNCTRL_VME;
2058                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2059         } else {
2060                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2061                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2062                         rxq = dev->data->rx_queues[i];
2063                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2064                         ctrl |= IXGBE_RXDCTL_VME;
2065                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2066
2067                         /* record those setting for HW strip per queue */
2068                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2069                 }
2070         }
2071 }
2072
2073 static void
2074 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2075 {
2076         struct ixgbe_hw *hw =
2077                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078         uint32_t ctrl;
2079
2080         PMD_INIT_FUNC_TRACE();
2081
2082         /* DMATXCTRL: Geric Double VLAN Disable */
2083         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2084         ctrl &= ~IXGBE_DMATXCTL_GDV;
2085         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2086
2087         /* CTRL_EXT: Global Double VLAN Disable */
2088         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2089         ctrl &= ~IXGBE_EXTENDED_VLAN;
2090         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2091
2092 }
2093
2094 static void
2095 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2096 {
2097         struct ixgbe_hw *hw =
2098                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         uint32_t ctrl;
2100
2101         PMD_INIT_FUNC_TRACE();
2102
2103         /* DMATXCTRL: Geric Double VLAN Enable */
2104         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2105         ctrl |= IXGBE_DMATXCTL_GDV;
2106         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2107
2108         /* CTRL_EXT: Global Double VLAN Enable */
2109         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2110         ctrl |= IXGBE_EXTENDED_VLAN;
2111         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2112
2113         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2114         if (hw->mac.type == ixgbe_mac_X550 ||
2115             hw->mac.type == ixgbe_mac_X550EM_x ||
2116             hw->mac.type == ixgbe_mac_X550EM_a) {
2117                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2118                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2119                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2120         }
2121
2122         /*
2123          * VET EXT field in the EXVET register = 0x8100 by default
2124          * So no need to change. Same to VT field of DMATXCTL register
2125          */
2126 }
2127
2128 static void
2129 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2130 {
2131         if (mask & ETH_VLAN_STRIP_MASK) {
2132                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2133                         ixgbe_vlan_hw_strip_enable_all(dev);
2134                 else
2135                         ixgbe_vlan_hw_strip_disable_all(dev);
2136         }
2137
2138         if (mask & ETH_VLAN_FILTER_MASK) {
2139                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2140                         ixgbe_vlan_hw_filter_enable(dev);
2141                 else
2142                         ixgbe_vlan_hw_filter_disable(dev);
2143         }
2144
2145         if (mask & ETH_VLAN_EXTEND_MASK) {
2146                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2147                         ixgbe_vlan_hw_extend_enable(dev);
2148                 else
2149                         ixgbe_vlan_hw_extend_disable(dev);
2150         }
2151 }
2152
2153 static void
2154 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2155 {
2156         struct ixgbe_hw *hw =
2157                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2159         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2160
2161         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2162         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2163 }
2164
2165 static int
2166 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2167 {
2168         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2169
2170         switch (nb_rx_q) {
2171         case 1:
2172         case 2:
2173                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2174                 break;
2175         case 4:
2176                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2177                 break;
2178         default:
2179                 return -EINVAL;
2180         }
2181
2182         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2183         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2184
2185         return 0;
2186 }
2187
2188 static int
2189 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2190 {
2191         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2194         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2195
2196         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2197                 /* check multi-queue mode */
2198                 switch (dev_conf->rxmode.mq_mode) {
2199                 case ETH_MQ_RX_VMDQ_DCB:
2200                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2201                         break;
2202                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2203                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2204                         PMD_INIT_LOG(ERR, "SRIOV active,"
2205                                         " unsupported mq_mode rx %d.",
2206                                         dev_conf->rxmode.mq_mode);
2207                         return -EINVAL;
2208                 case ETH_MQ_RX_RSS:
2209                 case ETH_MQ_RX_VMDQ_RSS:
2210                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2211                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2212                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2213                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2214                                                 " invalid queue number"
2215                                                 " for VMDQ RSS, allowed"
2216                                                 " value are 1, 2 or 4.");
2217                                         return -EINVAL;
2218                                 }
2219                         break;
2220                 case ETH_MQ_RX_VMDQ_ONLY:
2221                 case ETH_MQ_RX_NONE:
2222                         /* if nothing mq mode configure, use default scheme */
2223                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2224                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2225                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2226                         break;
2227                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2228                         /* SRIOV only works in VMDq enable mode */
2229                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2230                                         " wrong mq_mode rx %d.",
2231                                         dev_conf->rxmode.mq_mode);
2232                         return -EINVAL;
2233                 }
2234
2235                 switch (dev_conf->txmode.mq_mode) {
2236                 case ETH_MQ_TX_VMDQ_DCB:
2237                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2238                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2239                         break;
2240                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2241                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2242                         break;
2243                 }
2244
2245                 /* check valid queue number */
2246                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2247                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2248                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2249                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2250                                         " must be less than or equal to %d.",
2251                                         nb_rx_q, nb_tx_q,
2252                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2253                         return -EINVAL;
2254                 }
2255         } else {
2256                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2257                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2258                                           " not supported.");
2259                         return -EINVAL;
2260                 }
2261                 /* check configuration for vmdb+dcb mode */
2262                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2263                         const struct rte_eth_vmdq_dcb_conf *conf;
2264
2265                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2266                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2267                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2268                                 return -EINVAL;
2269                         }
2270                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2271                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2272                                conf->nb_queue_pools == ETH_32_POOLS)) {
2273                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2274                                                 " nb_queue_pools must be %d or %d.",
2275                                                 ETH_16_POOLS, ETH_32_POOLS);
2276                                 return -EINVAL;
2277                         }
2278                 }
2279                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2280                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2281
2282                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2283                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2284                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2285                                 return -EINVAL;
2286                         }
2287                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2288                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2289                                conf->nb_queue_pools == ETH_32_POOLS)) {
2290                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2291                                                 " nb_queue_pools != %d and"
2292                                                 " nb_queue_pools != %d.",
2293                                                 ETH_16_POOLS, ETH_32_POOLS);
2294                                 return -EINVAL;
2295                         }
2296                 }
2297
2298                 /* For DCB mode check our configuration before we go further */
2299                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2300                         const struct rte_eth_dcb_rx_conf *conf;
2301
2302                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2303                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2304                                                  IXGBE_DCB_NB_QUEUES);
2305                                 return -EINVAL;
2306                         }
2307                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2308                         if (!(conf->nb_tcs == ETH_4_TCS ||
2309                                conf->nb_tcs == ETH_8_TCS)) {
2310                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2311                                                 " and nb_tcs != %d.",
2312                                                 ETH_4_TCS, ETH_8_TCS);
2313                                 return -EINVAL;
2314                         }
2315                 }
2316
2317                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2318                         const struct rte_eth_dcb_tx_conf *conf;
2319
2320                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2321                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2322                                                  IXGBE_DCB_NB_QUEUES);
2323                                 return -EINVAL;
2324                         }
2325                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2326                         if (!(conf->nb_tcs == ETH_4_TCS ||
2327                                conf->nb_tcs == ETH_8_TCS)) {
2328                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2329                                                 " and nb_tcs != %d.",
2330                                                 ETH_4_TCS, ETH_8_TCS);
2331                                 return -EINVAL;
2332                         }
2333                 }
2334
2335                 /*
2336                  * When DCB/VT is off, maximum number of queues changes,
2337                  * except for 82598EB, which remains constant.
2338                  */
2339                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2340                                 hw->mac.type != ixgbe_mac_82598EB) {
2341                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2342                                 PMD_INIT_LOG(ERR,
2343                                              "Neither VT nor DCB are enabled, "
2344                                              "nb_tx_q > %d.",
2345                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2346                                 return -EINVAL;
2347                         }
2348                 }
2349         }
2350         return 0;
2351 }
2352
2353 static int
2354 ixgbe_dev_configure(struct rte_eth_dev *dev)
2355 {
2356         struct ixgbe_interrupt *intr =
2357                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2358         struct ixgbe_adapter *adapter =
2359                 (struct ixgbe_adapter *)dev->data->dev_private;
2360         int ret;
2361
2362         PMD_INIT_FUNC_TRACE();
2363         /* multipe queue mode checking */
2364         ret  = ixgbe_check_mq_mode(dev);
2365         if (ret != 0) {
2366                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2367                             ret);
2368                 return ret;
2369         }
2370
2371         /* set flag to update link status after init */
2372         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2373
2374         /*
2375          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2376          * allocation or vector Rx preconditions we will reset it.
2377          */
2378         adapter->rx_bulk_alloc_allowed = true;
2379         adapter->rx_vec_allowed = true;
2380
2381         return 0;
2382 }
2383
2384 static void
2385 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2386 {
2387         struct ixgbe_hw *hw =
2388                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389         struct ixgbe_interrupt *intr =
2390                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2391         uint32_t gpie;
2392
2393         /* only set up it on X550EM_X */
2394         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2395                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2396                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2397                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2398                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2399                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2400         }
2401 }
2402
2403 int
2404 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2405                         uint16_t tx_rate, uint64_t q_msk)
2406 {
2407         struct ixgbe_hw *hw;
2408         struct ixgbe_vf_info *vfinfo;
2409         struct rte_eth_link link;
2410         uint8_t  nb_q_per_pool;
2411         uint32_t queue_stride;
2412         uint32_t queue_idx, idx = 0, vf_idx;
2413         uint32_t queue_end;
2414         uint16_t total_rate = 0;
2415         struct rte_pci_device *pci_dev;
2416
2417         pci_dev = IXGBE_DEV_TO_PCI(dev);
2418         rte_eth_link_get_nowait(dev->data->port_id, &link);
2419
2420         if (vf >= pci_dev->max_vfs)
2421                 return -EINVAL;
2422
2423         if (tx_rate > link.link_speed)
2424                 return -EINVAL;
2425
2426         if (q_msk == 0)
2427                 return 0;
2428
2429         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2431         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2432         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2433         queue_idx = vf * queue_stride;
2434         queue_end = queue_idx + nb_q_per_pool - 1;
2435         if (queue_end >= hw->mac.max_tx_queues)
2436                 return -EINVAL;
2437
2438         if (vfinfo) {
2439                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2440                         if (vf_idx == vf)
2441                                 continue;
2442                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2443                                 idx++)
2444                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2445                 }
2446         } else {
2447                 return -EINVAL;
2448         }
2449
2450         /* Store tx_rate for this vf. */
2451         for (idx = 0; idx < nb_q_per_pool; idx++) {
2452                 if (((uint64_t)0x1 << idx) & q_msk) {
2453                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2454                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2455                         total_rate += tx_rate;
2456                 }
2457         }
2458
2459         if (total_rate > dev->data->dev_link.link_speed) {
2460                 /* Reset stored TX rate of the VF if it causes exceed
2461                  * link speed.
2462                  */
2463                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2464                 return -EINVAL;
2465         }
2466
2467         /* Set RTTBCNRC of each queue/pool for vf X  */
2468         for (; queue_idx <= queue_end; queue_idx++) {
2469                 if (0x1 & q_msk)
2470                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2471                 q_msk = q_msk >> 1;
2472         }
2473
2474         return 0;
2475 }
2476
2477 /*
2478  * Configure device link speed and setup link.
2479  * It returns 0 on success.
2480  */
2481 static int
2482 ixgbe_dev_start(struct rte_eth_dev *dev)
2483 {
2484         struct ixgbe_hw *hw =
2485                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486         struct ixgbe_vf_info *vfinfo =
2487                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2488         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2489         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2490         uint32_t intr_vector = 0;
2491         int err, link_up = 0, negotiate = 0;
2492         uint32_t speed = 0;
2493         int mask = 0;
2494         int status;
2495         uint16_t vf, idx;
2496         uint32_t *link_speeds;
2497
2498         PMD_INIT_FUNC_TRACE();
2499
2500         /* IXGBE devices don't support:
2501         *    - half duplex (checked afterwards for valid speeds)
2502         *    - fixed speed: TODO implement
2503         */
2504         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2505                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2506                              dev->data->port_id);
2507                 return -EINVAL;
2508         }
2509
2510         /* disable uio/vfio intr/eventfd mapping */
2511         rte_intr_disable(intr_handle);
2512
2513         /* stop adapter */
2514         hw->adapter_stopped = 0;
2515         ixgbe_stop_adapter(hw);
2516
2517         /* reinitialize adapter
2518          * this calls reset and start
2519          */
2520         status = ixgbe_pf_reset_hw(hw);
2521         if (status != 0)
2522                 return -1;
2523         hw->mac.ops.start_hw(hw);
2524         hw->mac.get_link_status = true;
2525
2526         /* configure PF module if SRIOV enabled */
2527         ixgbe_pf_host_configure(dev);
2528
2529         ixgbe_dev_phy_intr_setup(dev);
2530
2531         /* check and configure queue intr-vector mapping */
2532         if ((rte_intr_cap_multiple(intr_handle) ||
2533              !RTE_ETH_DEV_SRIOV(dev).active) &&
2534             dev->data->dev_conf.intr_conf.rxq != 0) {
2535                 intr_vector = dev->data->nb_rx_queues;
2536                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2537                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2538                                         IXGBE_MAX_INTR_QUEUE_NUM);
2539                         return -ENOTSUP;
2540                 }
2541                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2542                         return -1;
2543         }
2544
2545         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2546                 intr_handle->intr_vec =
2547                         rte_zmalloc("intr_vec",
2548                                     dev->data->nb_rx_queues * sizeof(int), 0);
2549                 if (intr_handle->intr_vec == NULL) {
2550                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2551                                      " intr_vec", dev->data->nb_rx_queues);
2552                         return -ENOMEM;
2553                 }
2554         }
2555
2556         /* confiugre msix for sleep until rx interrupt */
2557         ixgbe_configure_msix(dev);
2558
2559         /* initialize transmission unit */
2560         ixgbe_dev_tx_init(dev);
2561
2562         /* This can fail when allocating mbufs for descriptor rings */
2563         err = ixgbe_dev_rx_init(dev);
2564         if (err) {
2565                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2566                 goto error;
2567         }
2568
2569     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2570                 ETH_VLAN_EXTEND_MASK;
2571         ixgbe_vlan_offload_set(dev, mask);
2572
2573         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2574                 /* Enable vlan filtering for VMDq */
2575                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2576         }
2577
2578         /* Configure DCB hw */
2579         ixgbe_configure_dcb(dev);
2580
2581         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2582                 err = ixgbe_fdir_configure(dev);
2583                 if (err)
2584                         goto error;
2585         }
2586
2587         /* Restore vf rate limit */
2588         if (vfinfo != NULL) {
2589                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2590                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2591                                 if (vfinfo[vf].tx_rate[idx] != 0)
2592                                         ixgbe_set_vf_rate_limit(
2593                                                 dev, vf,
2594                                                 vfinfo[vf].tx_rate[idx],
2595                                                 1 << idx);
2596         }
2597
2598         ixgbe_restore_statistics_mapping(dev);
2599
2600         err = ixgbe_dev_rxtx_start(dev);
2601         if (err < 0) {
2602                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2603                 goto error;
2604         }
2605
2606         /* Skip link setup if loopback mode is enabled for 82599. */
2607         if (hw->mac.type == ixgbe_mac_82599EB &&
2608                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2609                 goto skip_link_setup;
2610
2611         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2612                 err = hw->mac.ops.setup_sfp(hw);
2613                 if (err)
2614                         goto error;
2615         }
2616
2617         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2618                 /* Turn on the copper */
2619                 ixgbe_set_phy_power(hw, true);
2620         } else {
2621                 /* Turn on the laser */
2622                 ixgbe_enable_tx_laser(hw);
2623         }
2624
2625         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2626         if (err)
2627                 goto error;
2628         dev->data->dev_link.link_status = link_up;
2629
2630         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2631         if (err)
2632                 goto error;
2633
2634         link_speeds = &dev->data->dev_conf.link_speeds;
2635         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2636                         ETH_LINK_SPEED_10G)) {
2637                 PMD_INIT_LOG(ERR, "Invalid link setting");
2638                 goto error;
2639         }
2640
2641         speed = 0x0;
2642         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2643                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2644                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2645                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2646         } else {
2647                 if (*link_speeds & ETH_LINK_SPEED_10G)
2648                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2649                 if (*link_speeds & ETH_LINK_SPEED_1G)
2650                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2651                 if (*link_speeds & ETH_LINK_SPEED_100M)
2652                         speed |= IXGBE_LINK_SPEED_100_FULL;
2653         }
2654
2655         err = ixgbe_setup_link(hw, speed, link_up);
2656         if (err)
2657                 goto error;
2658
2659 skip_link_setup:
2660
2661         if (rte_intr_allow_others(intr_handle)) {
2662                 /* check if lsc interrupt is enabled */
2663                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2664                         ixgbe_dev_lsc_interrupt_setup(dev);
2665                 ixgbe_dev_macsec_interrupt_setup(dev);
2666         } else {
2667                 rte_intr_callback_unregister(intr_handle,
2668                                              ixgbe_dev_interrupt_handler, dev);
2669                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2670                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2671                                      " no intr multiplex");
2672         }
2673
2674         /* check if rxq interrupt is enabled */
2675         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2676             rte_intr_dp_is_en(intr_handle))
2677                 ixgbe_dev_rxq_interrupt_setup(dev);
2678
2679         /* enable uio/vfio intr/eventfd mapping */
2680         rte_intr_enable(intr_handle);
2681
2682         /* resume enabled intr since hw reset */
2683         ixgbe_enable_intr(dev);
2684         ixgbe_l2_tunnel_conf(dev);
2685         ixgbe_filter_restore(dev);
2686
2687         return 0;
2688
2689 error:
2690         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2691         ixgbe_dev_clear_queues(dev);
2692         return -EIO;
2693 }
2694
2695 /*
2696  * Stop device: disable rx and tx functions to allow for reconfiguring.
2697  */
2698 static void
2699 ixgbe_dev_stop(struct rte_eth_dev *dev)
2700 {
2701         struct rte_eth_link link;
2702         struct ixgbe_hw *hw =
2703                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704         struct ixgbe_vf_info *vfinfo =
2705                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2706         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2707         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2708         int vf;
2709
2710         PMD_INIT_FUNC_TRACE();
2711
2712         /* disable interrupts */
2713         ixgbe_disable_intr(hw);
2714
2715         /* reset the NIC */
2716         ixgbe_pf_reset_hw(hw);
2717         hw->adapter_stopped = 0;
2718
2719         /* stop adapter */
2720         ixgbe_stop_adapter(hw);
2721
2722         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2723                 vfinfo[vf].clear_to_send = false;
2724
2725         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2726                 /* Turn off the copper */
2727                 ixgbe_set_phy_power(hw, false);
2728         } else {
2729                 /* Turn off the laser */
2730                 ixgbe_disable_tx_laser(hw);
2731         }
2732
2733         ixgbe_dev_clear_queues(dev);
2734
2735         /* Clear stored conf */
2736         dev->data->scattered_rx = 0;
2737         dev->data->lro = 0;
2738
2739         /* Clear recorded link status */
2740         memset(&link, 0, sizeof(link));
2741         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2742
2743         if (!rte_intr_allow_others(intr_handle))
2744                 /* resume to the default handler */
2745                 rte_intr_callback_register(intr_handle,
2746                                            ixgbe_dev_interrupt_handler,
2747                                            (void *)dev);
2748
2749         /* Clean datapath event and queue/vec mapping */
2750         rte_intr_efd_disable(intr_handle);
2751         if (intr_handle->intr_vec != NULL) {
2752                 rte_free(intr_handle->intr_vec);
2753                 intr_handle->intr_vec = NULL;
2754         }
2755 }
2756
2757 /*
2758  * Set device link up: enable tx.
2759  */
2760 static int
2761 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2762 {
2763         struct ixgbe_hw *hw =
2764                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765         if (hw->mac.type == ixgbe_mac_82599EB) {
2766 #ifdef RTE_NIC_BYPASS
2767                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2768                         /* Not suported in bypass mode */
2769                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2770                                      "by device id 0x%x", hw->device_id);
2771                         return -ENOTSUP;
2772                 }
2773 #endif
2774         }
2775
2776         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2777                 /* Turn on the copper */
2778                 ixgbe_set_phy_power(hw, true);
2779         } else {
2780                 /* Turn on the laser */
2781                 ixgbe_enable_tx_laser(hw);
2782         }
2783
2784         return 0;
2785 }
2786
2787 /*
2788  * Set device link down: disable tx.
2789  */
2790 static int
2791 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2792 {
2793         struct ixgbe_hw *hw =
2794                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795         if (hw->mac.type == ixgbe_mac_82599EB) {
2796 #ifdef RTE_NIC_BYPASS
2797                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2798                         /* Not suported in bypass mode */
2799                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2800                                      "by device id 0x%x", hw->device_id);
2801                         return -ENOTSUP;
2802                 }
2803 #endif
2804         }
2805
2806         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2807                 /* Turn off the copper */
2808                 ixgbe_set_phy_power(hw, false);
2809         } else {
2810                 /* Turn off the laser */
2811                 ixgbe_disable_tx_laser(hw);
2812         }
2813
2814         return 0;
2815 }
2816
2817 /*
2818  * Reest and stop device.
2819  */
2820 static void
2821 ixgbe_dev_close(struct rte_eth_dev *dev)
2822 {
2823         struct ixgbe_hw *hw =
2824                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2825
2826         PMD_INIT_FUNC_TRACE();
2827
2828         ixgbe_pf_reset_hw(hw);
2829
2830         ixgbe_dev_stop(dev);
2831         hw->adapter_stopped = 1;
2832
2833         ixgbe_dev_free_queues(dev);
2834
2835         ixgbe_disable_pcie_master(hw);
2836
2837         /* reprogram the RAR[0] in case user changed it. */
2838         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2839 }
2840
2841 static void
2842 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2843                            struct ixgbe_hw_stats *hw_stats,
2844                            struct ixgbe_macsec_stats *macsec_stats,
2845                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2846                            uint64_t *total_qprc, uint64_t *total_qprdc)
2847 {
2848         uint32_t bprc, lxon, lxoff, total;
2849         uint32_t delta_gprc = 0;
2850         unsigned i;
2851         /* Workaround for RX byte count not including CRC bytes when CRC
2852          * strip is enabled. CRC bytes are removed from counters when crc_strip
2853          * is disabled.
2854          */
2855         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2856                         IXGBE_HLREG0_RXCRCSTRP);
2857
2858         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2859         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2860         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2861         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2862
2863         for (i = 0; i < 8; i++) {
2864                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2865
2866                 /* global total per queue */
2867                 hw_stats->mpc[i] += mp;
2868                 /* Running comprehensive total for stats display */
2869                 *total_missed_rx += hw_stats->mpc[i];
2870                 if (hw->mac.type == ixgbe_mac_82598EB) {
2871                         hw_stats->rnbc[i] +=
2872                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2873                         hw_stats->pxonrxc[i] +=
2874                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2875                         hw_stats->pxoffrxc[i] +=
2876                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2877                 } else {
2878                         hw_stats->pxonrxc[i] +=
2879                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2880                         hw_stats->pxoffrxc[i] +=
2881                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2882                         hw_stats->pxon2offc[i] +=
2883                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2884                 }
2885                 hw_stats->pxontxc[i] +=
2886                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2887                 hw_stats->pxofftxc[i] +=
2888                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2889         }
2890         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2891                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2892                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2893                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2894
2895                 delta_gprc += delta_qprc;
2896
2897                 hw_stats->qprc[i] += delta_qprc;
2898                 hw_stats->qptc[i] += delta_qptc;
2899
2900                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2901                 hw_stats->qbrc[i] +=
2902                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2903                 if (crc_strip == 0)
2904                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2905
2906                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2907                 hw_stats->qbtc[i] +=
2908                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2909
2910                 hw_stats->qprdc[i] += delta_qprdc;
2911                 *total_qprdc += hw_stats->qprdc[i];
2912
2913                 *total_qprc += hw_stats->qprc[i];
2914                 *total_qbrc += hw_stats->qbrc[i];
2915         }
2916         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2917         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2918         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2919
2920         /*
2921          * An errata states that gprc actually counts good + missed packets:
2922          * Workaround to set gprc to summated queue packet receives
2923          */
2924         hw_stats->gprc = *total_qprc;
2925
2926         if (hw->mac.type != ixgbe_mac_82598EB) {
2927                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2928                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2929                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2930                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2931                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2932                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2933                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2934                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2935         } else {
2936                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2937                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2938                 /* 82598 only has a counter in the high register */
2939                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2940                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2941                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2942         }
2943         uint64_t old_tpr = hw_stats->tpr;
2944
2945         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2946         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2947
2948         if (crc_strip == 0)
2949                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2950
2951         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2952         hw_stats->gptc += delta_gptc;
2953         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2954         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2955
2956         /*
2957          * Workaround: mprc hardware is incorrectly counting
2958          * broadcasts, so for now we subtract those.
2959          */
2960         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2961         hw_stats->bprc += bprc;
2962         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2963         if (hw->mac.type == ixgbe_mac_82598EB)
2964                 hw_stats->mprc -= bprc;
2965
2966         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2967         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2968         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2969         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2970         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2971         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2972
2973         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2974         hw_stats->lxontxc += lxon;
2975         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2976         hw_stats->lxofftxc += lxoff;
2977         total = lxon + lxoff;
2978
2979         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2980         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2981         hw_stats->gptc -= total;
2982         hw_stats->mptc -= total;
2983         hw_stats->ptc64 -= total;
2984         hw_stats->gotc -= total * ETHER_MIN_LEN;
2985
2986         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2987         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2988         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2989         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2990         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2991         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2992         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2993         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2994         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2995         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2996         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2997         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2998         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2999         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3000         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3001         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3002         /* Only read FCOE on 82599 */
3003         if (hw->mac.type != ixgbe_mac_82598EB) {
3004                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3005                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3006                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3007                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3008                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3009         }
3010
3011         /* Flow Director Stats registers */
3012         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3013         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3014
3015         /* MACsec Stats registers */
3016         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3017         macsec_stats->out_pkts_encrypted +=
3018                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3019         macsec_stats->out_pkts_protected +=
3020                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3021         macsec_stats->out_octets_encrypted +=
3022                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3023         macsec_stats->out_octets_protected +=
3024                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3025         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3026         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3027         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3028         macsec_stats->in_pkts_unknownsci +=
3029                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3030         macsec_stats->in_octets_decrypted +=
3031                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3032         macsec_stats->in_octets_validated +=
3033                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3034         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3035         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3036         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3037         for (i = 0; i < 2; i++) {
3038                 macsec_stats->in_pkts_ok +=
3039                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3040                 macsec_stats->in_pkts_invalid +=
3041                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3042                 macsec_stats->in_pkts_notvalid +=
3043                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3044         }
3045         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3046         macsec_stats->in_pkts_notusingsa +=
3047                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3048 }
3049
3050 /*
3051  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3052  */
3053 static void
3054 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3055 {
3056         struct ixgbe_hw *hw =
3057                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3058         struct ixgbe_hw_stats *hw_stats =
3059                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3060         struct ixgbe_macsec_stats *macsec_stats =
3061                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3062                                 dev->data->dev_private);
3063         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3064         unsigned i;
3065
3066         total_missed_rx = 0;
3067         total_qbrc = 0;
3068         total_qprc = 0;
3069         total_qprdc = 0;
3070
3071         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3072                         &total_qbrc, &total_qprc, &total_qprdc);
3073
3074         if (stats == NULL)
3075                 return;
3076
3077         /* Fill out the rte_eth_stats statistics structure */
3078         stats->ipackets = total_qprc;
3079         stats->ibytes = total_qbrc;
3080         stats->opackets = hw_stats->gptc;
3081         stats->obytes = hw_stats->gotc;
3082
3083         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3084                 stats->q_ipackets[i] = hw_stats->qprc[i];
3085                 stats->q_opackets[i] = hw_stats->qptc[i];
3086                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3087                 stats->q_obytes[i] = hw_stats->qbtc[i];
3088                 stats->q_errors[i] = hw_stats->qprdc[i];
3089         }
3090
3091         /* Rx Errors */
3092         stats->imissed  = total_missed_rx;
3093         stats->ierrors  = hw_stats->crcerrs +
3094                           hw_stats->mspdc +
3095                           hw_stats->rlec +
3096                           hw_stats->ruc +
3097                           hw_stats->roc +
3098                           hw_stats->illerrc +
3099                           hw_stats->errbc +
3100                           hw_stats->rfc +
3101                           hw_stats->fccrc +
3102                           hw_stats->fclast;
3103
3104         /* Tx Errors */
3105         stats->oerrors  = 0;
3106 }
3107
3108 static void
3109 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3110 {
3111         struct ixgbe_hw_stats *stats =
3112                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3113
3114         /* HW registers are cleared on read */
3115         ixgbe_dev_stats_get(dev, NULL);
3116
3117         /* Reset software totals */
3118         memset(stats, 0, sizeof(*stats));
3119 }
3120
3121 /* This function calculates the number of xstats based on the current config */
3122 static unsigned
3123 ixgbe_xstats_calc_num(void) {
3124         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3125                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3126                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3127 }
3128
3129 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3130         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3131 {
3132         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3133         unsigned stat, i, count;
3134
3135         if (xstats_names != NULL) {
3136                 count = 0;
3137
3138                 /* Note: limit >= cnt_stats checked upstream
3139                  * in rte_eth_xstats_names()
3140                  */
3141
3142                 /* Extended stats from ixgbe_hw_stats */
3143                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3144                         snprintf(xstats_names[count].name,
3145                                 sizeof(xstats_names[count].name),
3146                                 "%s",
3147                                 rte_ixgbe_stats_strings[i].name);
3148                         count++;
3149                 }
3150
3151                 /* MACsec Stats */
3152                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3153                         snprintf(xstats_names[count].name,
3154                                 sizeof(xstats_names[count].name),
3155                                 "%s",
3156                                 rte_ixgbe_macsec_strings[i].name);
3157                         count++;
3158                 }
3159
3160                 /* RX Priority Stats */
3161                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3162                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3163                                 snprintf(xstats_names[count].name,
3164                                         sizeof(xstats_names[count].name),
3165                                         "rx_priority%u_%s", i,
3166                                         rte_ixgbe_rxq_strings[stat].name);
3167                                 count++;
3168                         }
3169                 }
3170
3171                 /* TX Priority Stats */
3172                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3173                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3174                                 snprintf(xstats_names[count].name,
3175                                         sizeof(xstats_names[count].name),
3176                                         "tx_priority%u_%s", i,
3177                                         rte_ixgbe_txq_strings[stat].name);
3178                                 count++;
3179                         }
3180                 }
3181         }
3182         return cnt_stats;
3183 }
3184
3185 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3186         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3187 {
3188         unsigned i;
3189
3190         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3191                 return -ENOMEM;
3192
3193         if (xstats_names != NULL)
3194                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3195                         snprintf(xstats_names[i].name,
3196                                 sizeof(xstats_names[i].name),
3197                                 "%s", rte_ixgbevf_stats_strings[i].name);
3198         return IXGBEVF_NB_XSTATS;
3199 }
3200
3201 static int
3202 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3203                                          unsigned n)
3204 {
3205         struct ixgbe_hw *hw =
3206                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3207         struct ixgbe_hw_stats *hw_stats =
3208                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3209         struct ixgbe_macsec_stats *macsec_stats =
3210                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3211                                 dev->data->dev_private);
3212         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3213         unsigned i, stat, count = 0;
3214
3215         count = ixgbe_xstats_calc_num();
3216
3217         if (n < count)
3218                 return count;
3219
3220         total_missed_rx = 0;
3221         total_qbrc = 0;
3222         total_qprc = 0;
3223         total_qprdc = 0;
3224
3225         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3226                         &total_qbrc, &total_qprc, &total_qprdc);
3227
3228         /* If this is a reset xstats is NULL, and we have cleared the
3229          * registers by reading them.
3230          */
3231         if (!xstats)
3232                 return 0;
3233
3234         /* Extended stats from ixgbe_hw_stats */
3235         count = 0;
3236         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3237                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3238                                 rte_ixgbe_stats_strings[i].offset);
3239                 xstats[count].id = count;
3240                 count++;
3241         }
3242
3243         /* MACsec Stats */
3244         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3245                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3246                                 rte_ixgbe_macsec_strings[i].offset);
3247                 xstats[count].id = count;
3248                 count++;
3249         }
3250
3251         /* RX Priority Stats */
3252         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3253                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3254                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3255                                         rte_ixgbe_rxq_strings[stat].offset +
3256                                         (sizeof(uint64_t) * i));
3257                         xstats[count].id = count;
3258                         count++;
3259                 }
3260         }
3261
3262         /* TX Priority Stats */
3263         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3264                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3265                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3266                                         rte_ixgbe_txq_strings[stat].offset +
3267                                         (sizeof(uint64_t) * i));
3268                         xstats[count].id = count;
3269                         count++;
3270                 }
3271         }
3272         return count;
3273 }
3274
3275 static void
3276 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3277 {
3278         struct ixgbe_hw_stats *stats =
3279                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3280         struct ixgbe_macsec_stats *macsec_stats =
3281                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3282                                 dev->data->dev_private);
3283
3284         unsigned count = ixgbe_xstats_calc_num();
3285
3286         /* HW registers are cleared on read */
3287         ixgbe_dev_xstats_get(dev, NULL, count);
3288
3289         /* Reset software totals */
3290         memset(stats, 0, sizeof(*stats));
3291         memset(macsec_stats, 0, sizeof(*macsec_stats));
3292 }
3293
3294 static void
3295 ixgbevf_update_stats(struct rte_eth_dev *dev)
3296 {
3297         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3298         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3299                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3300
3301         /* Good Rx packet, include VF loopback */
3302         UPDATE_VF_STAT(IXGBE_VFGPRC,
3303             hw_stats->last_vfgprc, hw_stats->vfgprc);
3304
3305         /* Good Rx octets, include VF loopback */
3306         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3307             hw_stats->last_vfgorc, hw_stats->vfgorc);
3308
3309         /* Good Tx packet, include VF loopback */
3310         UPDATE_VF_STAT(IXGBE_VFGPTC,
3311             hw_stats->last_vfgptc, hw_stats->vfgptc);
3312
3313         /* Good Tx octets, include VF loopback */
3314         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3315             hw_stats->last_vfgotc, hw_stats->vfgotc);
3316
3317         /* Rx Multicst Packet */
3318         UPDATE_VF_STAT(IXGBE_VFMPRC,
3319             hw_stats->last_vfmprc, hw_stats->vfmprc);
3320 }
3321
3322 static int
3323 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3324                        unsigned n)
3325 {
3326         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3327                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3328         unsigned i;
3329
3330         if (n < IXGBEVF_NB_XSTATS)
3331                 return IXGBEVF_NB_XSTATS;
3332
3333         ixgbevf_update_stats(dev);
3334
3335         if (!xstats)
3336                 return 0;
3337
3338         /* Extended stats */
3339         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3340                 xstats[i].id = i;
3341                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3342                         rte_ixgbevf_stats_strings[i].offset);
3343         }
3344
3345         return IXGBEVF_NB_XSTATS;
3346 }
3347
3348 static void
3349 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3350 {
3351         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3352                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3353
3354         ixgbevf_update_stats(dev);
3355
3356         if (stats == NULL)
3357                 return;
3358
3359         stats->ipackets = hw_stats->vfgprc;
3360         stats->ibytes = hw_stats->vfgorc;
3361         stats->opackets = hw_stats->vfgptc;
3362         stats->obytes = hw_stats->vfgotc;
3363 }
3364
3365 static void
3366 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3367 {
3368         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3369                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3370
3371         /* Sync HW register to the last stats */
3372         ixgbevf_dev_stats_get(dev, NULL);
3373
3374         /* reset HW current stats*/
3375         hw_stats->vfgprc = 0;
3376         hw_stats->vfgorc = 0;
3377         hw_stats->vfgptc = 0;
3378         hw_stats->vfgotc = 0;
3379 }
3380
3381 static int
3382 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3383 {
3384         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3385         u16 eeprom_verh, eeprom_verl;
3386         u32 etrack_id;
3387         int ret;
3388
3389         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3390         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3391
3392         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3393         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3394
3395         ret += 1; /* add the size of '\0' */
3396         if (fw_size < (u32)ret)
3397                 return ret;
3398         else
3399                 return 0;
3400 }
3401
3402 static void
3403 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3404 {
3405         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3406         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3407         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3408
3409         dev_info->pci_dev = pci_dev;
3410         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3411         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3412         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3413                 /*
3414                  * When DCB/VT is off, maximum number of queues changes,
3415                  * except for 82598EB, which remains constant.
3416                  */
3417                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3418                                 hw->mac.type != ixgbe_mac_82598EB)
3419                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3420         }
3421         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3422         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3423         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3424         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3425         dev_info->max_vfs = pci_dev->max_vfs;
3426         if (hw->mac.type == ixgbe_mac_82598EB)
3427                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3428         else
3429                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3430         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3431         dev_info->rx_offload_capa =
3432                 DEV_RX_OFFLOAD_VLAN_STRIP |
3433                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3434                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3435                 DEV_RX_OFFLOAD_TCP_CKSUM;
3436
3437         /*
3438          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3439          * mode.
3440          */
3441         if ((hw->mac.type == ixgbe_mac_82599EB ||
3442              hw->mac.type == ixgbe_mac_X540) &&
3443             !RTE_ETH_DEV_SRIOV(dev).active)
3444                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3445
3446         if (hw->mac.type == ixgbe_mac_82599EB ||
3447             hw->mac.type == ixgbe_mac_X540)
3448                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3449
3450         if (hw->mac.type == ixgbe_mac_X550 ||
3451             hw->mac.type == ixgbe_mac_X550EM_x ||
3452             hw->mac.type == ixgbe_mac_X550EM_a)
3453                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3454
3455         dev_info->tx_offload_capa =
3456                 DEV_TX_OFFLOAD_VLAN_INSERT |
3457                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3458                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3459                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3460                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3461                 DEV_TX_OFFLOAD_TCP_TSO;
3462
3463         if (hw->mac.type == ixgbe_mac_82599EB ||
3464             hw->mac.type == ixgbe_mac_X540)
3465                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3466
3467         if (hw->mac.type == ixgbe_mac_X550 ||
3468             hw->mac.type == ixgbe_mac_X550EM_x ||
3469             hw->mac.type == ixgbe_mac_X550EM_a)
3470                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3471
3472         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3473                 .rx_thresh = {
3474                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3475                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3476                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3477                 },
3478                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3479                 .rx_drop_en = 0,
3480         };
3481
3482         dev_info->default_txconf = (struct rte_eth_txconf) {
3483                 .tx_thresh = {
3484                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3485                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3486                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3487                 },
3488                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3489                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3490                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3491                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3492         };
3493
3494         dev_info->rx_desc_lim = rx_desc_lim;
3495         dev_info->tx_desc_lim = tx_desc_lim;
3496
3497         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3498         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3499         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3500
3501         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3502         if (hw->mac.type == ixgbe_mac_X540 ||
3503             hw->mac.type == ixgbe_mac_X540_vf ||
3504             hw->mac.type == ixgbe_mac_X550 ||
3505             hw->mac.type == ixgbe_mac_X550_vf) {
3506                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3507         }
3508 }
3509
3510 static const uint32_t *
3511 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3512 {
3513         static const uint32_t ptypes[] = {
3514                 /* For non-vec functions,
3515                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3516                  * for vec functions,
3517                  * refers to _recv_raw_pkts_vec().
3518                  */
3519                 RTE_PTYPE_L2_ETHER,
3520                 RTE_PTYPE_L3_IPV4,
3521                 RTE_PTYPE_L3_IPV4_EXT,
3522                 RTE_PTYPE_L3_IPV6,
3523                 RTE_PTYPE_L3_IPV6_EXT,
3524                 RTE_PTYPE_L4_SCTP,
3525                 RTE_PTYPE_L4_TCP,
3526                 RTE_PTYPE_L4_UDP,
3527                 RTE_PTYPE_TUNNEL_IP,
3528                 RTE_PTYPE_INNER_L3_IPV6,
3529                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3530                 RTE_PTYPE_INNER_L4_TCP,
3531                 RTE_PTYPE_INNER_L4_UDP,
3532                 RTE_PTYPE_UNKNOWN
3533         };
3534
3535         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3536             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3537             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3538             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3539                 return ptypes;
3540         return NULL;
3541 }
3542
3543 static void
3544 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3545                      struct rte_eth_dev_info *dev_info)
3546 {
3547         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3548         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549
3550         dev_info->pci_dev = pci_dev;
3551         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3552         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3553         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3554         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3555         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3556         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3557         dev_info->max_vfs = pci_dev->max_vfs;
3558         if (hw->mac.type == ixgbe_mac_82598EB)
3559                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3560         else
3561                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3562         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3563                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3564                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3565                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3566         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3567                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3568                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3569                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3570                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3571                                 DEV_TX_OFFLOAD_TCP_TSO;
3572
3573         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3574                 .rx_thresh = {
3575                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3576                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3577                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3578                 },
3579                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3580                 .rx_drop_en = 0,
3581         };
3582
3583         dev_info->default_txconf = (struct rte_eth_txconf) {
3584                 .tx_thresh = {
3585                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3586                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3587                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3588                 },
3589                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3590                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3591                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3592                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3593         };
3594
3595         dev_info->rx_desc_lim = rx_desc_lim;
3596         dev_info->tx_desc_lim = tx_desc_lim;
3597 }
3598
3599 /* return 0 means link status changed, -1 means not changed */
3600 static int
3601 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3602 {
3603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3604         struct rte_eth_link link, old;
3605         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3606         int link_up;
3607         int diag;
3608
3609         link.link_status = ETH_LINK_DOWN;
3610         link.link_speed = 0;
3611         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3612         memset(&old, 0, sizeof(old));
3613         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3614
3615         hw->mac.get_link_status = true;
3616
3617         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3618         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3619                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3620         else
3621                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3622
3623         if (diag != 0) {
3624                 link.link_speed = ETH_SPEED_NUM_100M;
3625                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3626                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3627                 if (link.link_status == old.link_status)
3628                         return -1;
3629                 return 0;
3630         }
3631
3632         if (link_up == 0) {
3633                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3634                 if (link.link_status == old.link_status)
3635                         return -1;
3636                 return 0;
3637         }
3638         link.link_status = ETH_LINK_UP;
3639         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3640
3641         switch (link_speed) {
3642         default:
3643         case IXGBE_LINK_SPEED_UNKNOWN:
3644                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3645                 link.link_speed = ETH_SPEED_NUM_100M;
3646                 break;
3647
3648         case IXGBE_LINK_SPEED_100_FULL:
3649                 link.link_speed = ETH_SPEED_NUM_100M;
3650                 break;
3651
3652         case IXGBE_LINK_SPEED_1GB_FULL:
3653                 link.link_speed = ETH_SPEED_NUM_1G;
3654                 break;
3655
3656         case IXGBE_LINK_SPEED_10GB_FULL:
3657                 link.link_speed = ETH_SPEED_NUM_10G;
3658                 break;
3659         }
3660         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3661
3662         if (link.link_status == old.link_status)
3663                 return -1;
3664
3665         return 0;
3666 }
3667
3668 static void
3669 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3670 {
3671         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3672         uint32_t fctrl;
3673
3674         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3675         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3676         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3677 }
3678
3679 static void
3680 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3681 {
3682         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3683         uint32_t fctrl;
3684
3685         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3686         fctrl &= (~IXGBE_FCTRL_UPE);
3687         if (dev->data->all_multicast == 1)
3688                 fctrl |= IXGBE_FCTRL_MPE;
3689         else
3690                 fctrl &= (~IXGBE_FCTRL_MPE);
3691         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3692 }
3693
3694 static void
3695 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3696 {
3697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698         uint32_t fctrl;
3699
3700         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3701         fctrl |= IXGBE_FCTRL_MPE;
3702         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3703 }
3704
3705 static void
3706 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3707 {
3708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709         uint32_t fctrl;
3710
3711         if (dev->data->promiscuous == 1)
3712                 return; /* must remain in all_multicast mode */
3713
3714         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3715         fctrl &= (~IXGBE_FCTRL_MPE);
3716         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3717 }
3718
3719 /**
3720  * It clears the interrupt causes and enables the interrupt.
3721  * It will be called once only during nic initialized.
3722  *
3723  * @param dev
3724  *  Pointer to struct rte_eth_dev.
3725  *
3726  * @return
3727  *  - On success, zero.
3728  *  - On failure, a negative value.
3729  */
3730 static int
3731 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3732 {
3733         struct ixgbe_interrupt *intr =
3734                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3735
3736         ixgbe_dev_link_status_print(dev);
3737         intr->mask |= IXGBE_EICR_LSC;
3738
3739         return 0;
3740 }
3741
3742 /**
3743  * It clears the interrupt causes and enables the interrupt.
3744  * It will be called once only during nic initialized.
3745  *
3746  * @param dev
3747  *  Pointer to struct rte_eth_dev.
3748  *
3749  * @return
3750  *  - On success, zero.
3751  *  - On failure, a negative value.
3752  */
3753 static int
3754 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3755 {
3756         struct ixgbe_interrupt *intr =
3757                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3758
3759         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3760
3761         return 0;
3762 }
3763
3764 /**
3765  * It clears the interrupt causes and enables the interrupt.
3766  * It will be called once only during nic initialized.
3767  *
3768  * @param dev
3769  *  Pointer to struct rte_eth_dev.
3770  *
3771  * @return
3772  *  - On success, zero.
3773  *  - On failure, a negative value.
3774  */
3775 static int
3776 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3777 {
3778         struct ixgbe_interrupt *intr =
3779                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3780
3781         intr->mask |= IXGBE_EICR_LINKSEC;
3782
3783         return 0;
3784 }
3785
3786 /*
3787  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3788  *
3789  * @param dev
3790  *  Pointer to struct rte_eth_dev.
3791  *
3792  * @return
3793  *  - On success, zero.
3794  *  - On failure, a negative value.
3795  */
3796 static int
3797 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3798 {
3799         uint32_t eicr;
3800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3801         struct ixgbe_interrupt *intr =
3802                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3803
3804         /* clear all cause mask */
3805         ixgbe_disable_intr(hw);
3806
3807         /* read-on-clear nic registers here */
3808         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3809         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3810
3811         intr->flags = 0;
3812
3813         /* set flag for async link update */
3814         if (eicr & IXGBE_EICR_LSC)
3815                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3816
3817         if (eicr & IXGBE_EICR_MAILBOX)
3818                 intr->flags |= IXGBE_FLAG_MAILBOX;
3819
3820         if (eicr & IXGBE_EICR_LINKSEC)
3821                 intr->flags |= IXGBE_FLAG_MACSEC;
3822
3823         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3824             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3825             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3826                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3827
3828         return 0;
3829 }
3830
3831 /**
3832  * It gets and then prints the link status.
3833  *
3834  * @param dev
3835  *  Pointer to struct rte_eth_dev.
3836  *
3837  * @return
3838  *  - On success, zero.
3839  *  - On failure, a negative value.
3840  */
3841 static void
3842 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3843 {
3844         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3845         struct rte_eth_link link;
3846
3847         memset(&link, 0, sizeof(link));
3848         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3849         if (link.link_status) {
3850                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3851                                         (int)(dev->data->port_id),
3852                                         (unsigned)link.link_speed,
3853                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3854                                         "full-duplex" : "half-duplex");
3855         } else {
3856                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3857                                 (int)(dev->data->port_id));
3858         }
3859         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3860                                 pci_dev->addr.domain,
3861                                 pci_dev->addr.bus,
3862                                 pci_dev->addr.devid,
3863                                 pci_dev->addr.function);
3864 }
3865
3866 /*
3867  * It executes link_update after knowing an interrupt occurred.
3868  *
3869  * @param dev
3870  *  Pointer to struct rte_eth_dev.
3871  *
3872  * @return
3873  *  - On success, zero.
3874  *  - On failure, a negative value.
3875  */
3876 static int
3877 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3878                            struct rte_intr_handle *intr_handle)
3879 {
3880         struct ixgbe_interrupt *intr =
3881                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3882         int64_t timeout;
3883         struct rte_eth_link link;
3884         struct ixgbe_hw *hw =
3885                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3886
3887         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3888
3889         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3890                 ixgbe_pf_mbx_process(dev);
3891                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3892         }
3893
3894         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3895                 ixgbe_handle_lasi(hw);
3896                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3897         }
3898
3899         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3900                 /* get the link status before link update, for predicting later */
3901                 memset(&link, 0, sizeof(link));
3902                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3903
3904                 ixgbe_dev_link_update(dev, 0);
3905
3906                 /* likely to up */
3907                 if (!link.link_status)
3908                         /* handle it 1 sec later, wait it being stable */
3909                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3910                 /* likely to down */
3911                 else
3912                         /* handle it 4 sec later, wait it being stable */
3913                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3914
3915                 ixgbe_dev_link_status_print(dev);
3916                 intr->mask_original = intr->mask;
3917                 /* only disable lsc interrupt */
3918                 intr->mask &= ~IXGBE_EIMS_LSC;
3919                 if (rte_eal_alarm_set(timeout * 1000,
3920                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3921                         PMD_DRV_LOG(ERR, "Error setting alarm");
3922                 else
3923                         intr->mask = intr->mask_original;
3924         }
3925
3926         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3927         ixgbe_enable_intr(dev);
3928         rte_intr_enable(intr_handle);
3929
3930         return 0;
3931 }
3932
3933 /**
3934  * Interrupt handler which shall be registered for alarm callback for delayed
3935  * handling specific interrupt to wait for the stable nic state. As the
3936  * NIC interrupt state is not stable for ixgbe after link is just down,
3937  * it needs to wait 4 seconds to get the stable status.
3938  *
3939  * @param handle
3940  *  Pointer to interrupt handle.
3941  * @param param
3942  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3943  *
3944  * @return
3945  *  void
3946  */
3947 static void
3948 ixgbe_dev_interrupt_delayed_handler(void *param)
3949 {
3950         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3951         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3952         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3953         struct ixgbe_interrupt *intr =
3954                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3955         struct ixgbe_hw *hw =
3956                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3957         uint32_t eicr;
3958
3959         ixgbe_disable_intr(hw);
3960
3961         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3962         if (eicr & IXGBE_EICR_MAILBOX)
3963                 ixgbe_pf_mbx_process(dev);
3964
3965         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3966                 ixgbe_handle_lasi(hw);
3967                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3968         }
3969
3970         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3971                 ixgbe_dev_link_update(dev, 0);
3972                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3973                 ixgbe_dev_link_status_print(dev);
3974                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3975         }
3976
3977         if (intr->flags & IXGBE_FLAG_MACSEC) {
3978                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3979                                               NULL);
3980                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3981         }
3982
3983         /* restore original mask */
3984         intr->mask = intr->mask_original;
3985         intr->mask_original = 0;
3986
3987         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3988         ixgbe_enable_intr(dev);
3989         rte_intr_enable(intr_handle);
3990 }
3991
3992 /**
3993  * Interrupt handler triggered by NIC  for handling
3994  * specific interrupt.
3995  *
3996  * @param handle
3997  *  Pointer to interrupt handle.
3998  * @param param
3999  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4000  *
4001  * @return
4002  *  void
4003  */
4004 static void
4005 ixgbe_dev_interrupt_handler(void *param)
4006 {
4007         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4008
4009         ixgbe_dev_interrupt_get_status(dev);
4010         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4011 }
4012
4013 static int
4014 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4015 {
4016         struct ixgbe_hw *hw;
4017
4018         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4019         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4020 }
4021
4022 static int
4023 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4024 {
4025         struct ixgbe_hw *hw;
4026
4027         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4028         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4029 }
4030
4031 static int
4032 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4033 {
4034         struct ixgbe_hw *hw;
4035         uint32_t mflcn_reg;
4036         uint32_t fccfg_reg;
4037         int rx_pause;
4038         int tx_pause;
4039
4040         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4041
4042         fc_conf->pause_time = hw->fc.pause_time;
4043         fc_conf->high_water = hw->fc.high_water[0];
4044         fc_conf->low_water = hw->fc.low_water[0];
4045         fc_conf->send_xon = hw->fc.send_xon;
4046         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4047
4048         /*
4049          * Return rx_pause status according to actual setting of
4050          * MFLCN register.
4051          */
4052         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4053         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4054                 rx_pause = 1;
4055         else
4056                 rx_pause = 0;
4057
4058         /*
4059          * Return tx_pause status according to actual setting of
4060          * FCCFG register.
4061          */
4062         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4063         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4064                 tx_pause = 1;
4065         else
4066                 tx_pause = 0;
4067
4068         if (rx_pause && tx_pause)
4069                 fc_conf->mode = RTE_FC_FULL;
4070         else if (rx_pause)
4071                 fc_conf->mode = RTE_FC_RX_PAUSE;
4072         else if (tx_pause)
4073                 fc_conf->mode = RTE_FC_TX_PAUSE;
4074         else
4075                 fc_conf->mode = RTE_FC_NONE;
4076
4077         return 0;
4078 }
4079
4080 static int
4081 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4082 {
4083         struct ixgbe_hw *hw;
4084         int err;
4085         uint32_t rx_buf_size;
4086         uint32_t max_high_water;
4087         uint32_t mflcn;
4088         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4089                 ixgbe_fc_none,
4090                 ixgbe_fc_rx_pause,
4091                 ixgbe_fc_tx_pause,
4092                 ixgbe_fc_full
4093         };
4094
4095         PMD_INIT_FUNC_TRACE();
4096
4097         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4098         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4099         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4100
4101         /*
4102          * At least reserve one Ethernet frame for watermark
4103          * high_water/low_water in kilo bytes for ixgbe
4104          */
4105         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4106         if ((fc_conf->high_water > max_high_water) ||
4107                 (fc_conf->high_water < fc_conf->low_water)) {
4108                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4109                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4110                 return -EINVAL;
4111         }
4112
4113         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4114         hw->fc.pause_time     = fc_conf->pause_time;
4115         hw->fc.high_water[0]  = fc_conf->high_water;
4116         hw->fc.low_water[0]   = fc_conf->low_water;
4117         hw->fc.send_xon       = fc_conf->send_xon;
4118         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4119
4120         err = ixgbe_fc_enable(hw);
4121
4122         /* Not negotiated is not an error case */
4123         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4124
4125                 /* check if we want to forward MAC frames - driver doesn't have native
4126                  * capability to do that, so we'll write the registers ourselves */
4127
4128                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4129
4130                 /* set or clear MFLCN.PMCF bit depending on configuration */
4131                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4132                         mflcn |= IXGBE_MFLCN_PMCF;
4133                 else
4134                         mflcn &= ~IXGBE_MFLCN_PMCF;
4135
4136                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4137                 IXGBE_WRITE_FLUSH(hw);
4138
4139                 return 0;
4140         }
4141
4142         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4143         return -EIO;
4144 }
4145
4146 /**
4147  *  ixgbe_pfc_enable_generic - Enable flow control
4148  *  @hw: pointer to hardware structure
4149  *  @tc_num: traffic class number
4150  *  Enable flow control according to the current settings.
4151  */
4152 static int
4153 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4154 {
4155         int ret_val = 0;
4156         uint32_t mflcn_reg, fccfg_reg;
4157         uint32_t reg;
4158         uint32_t fcrtl, fcrth;
4159         uint8_t i;
4160         uint8_t nb_rx_en;
4161
4162         /* Validate the water mark configuration */
4163         if (!hw->fc.pause_time) {
4164                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4165                 goto out;
4166         }
4167
4168         /* Low water mark of zero causes XOFF floods */
4169         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4170                  /* High/Low water can not be 0 */
4171                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4172                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4173                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4174                         goto out;
4175                 }
4176
4177                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4178                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4179                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4180                         goto out;
4181                 }
4182         }
4183         /* Negotiate the fc mode to use */
4184         ixgbe_fc_autoneg(hw);
4185
4186         /* Disable any previous flow control settings */
4187         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4188         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4189
4190         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4191         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4192
4193         switch (hw->fc.current_mode) {
4194         case ixgbe_fc_none:
4195                 /*
4196                  * If the count of enabled RX Priority Flow control >1,
4197                  * and the TX pause can not be disabled
4198                  */
4199                 nb_rx_en = 0;
4200                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4201                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4202                         if (reg & IXGBE_FCRTH_FCEN)
4203                                 nb_rx_en++;
4204                 }
4205                 if (nb_rx_en > 1)
4206                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4207                 break;
4208         case ixgbe_fc_rx_pause:
4209                 /*
4210                  * Rx Flow control is enabled and Tx Flow control is
4211                  * disabled by software override. Since there really
4212                  * isn't a way to advertise that we are capable of RX
4213                  * Pause ONLY, we will advertise that we support both
4214                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4215                  * disable the adapter's ability to send PAUSE frames.
4216                  */
4217                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4218                 /*
4219                  * If the count of enabled RX Priority Flow control >1,
4220                  * and the TX pause can not be disabled
4221                  */
4222                 nb_rx_en = 0;
4223                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4224                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4225                         if (reg & IXGBE_FCRTH_FCEN)
4226                                 nb_rx_en++;
4227                 }
4228                 if (nb_rx_en > 1)
4229                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4230                 break;
4231         case ixgbe_fc_tx_pause:
4232                 /*
4233                  * Tx Flow control is enabled, and Rx Flow control is
4234                  * disabled by software override.
4235                  */
4236                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4237                 break;
4238         case ixgbe_fc_full:
4239                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4240                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4241                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4242                 break;
4243         default:
4244                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4245                 ret_val = IXGBE_ERR_CONFIG;
4246                 goto out;
4247         }
4248
4249         /* Set 802.3x based flow control settings. */
4250         mflcn_reg |= IXGBE_MFLCN_DPF;
4251         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4252         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4253
4254         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4255         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4256                 hw->fc.high_water[tc_num]) {
4257                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4258                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4259                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4260         } else {
4261                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4262                 /*
4263                  * In order to prevent Tx hangs when the internal Tx
4264                  * switch is enabled we must set the high water mark
4265                  * to the maximum FCRTH value.  This allows the Tx
4266                  * switch to function even under heavy Rx workloads.
4267                  */
4268                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4269         }
4270         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4271
4272         /* Configure pause time (2 TCs per register) */
4273         reg = hw->fc.pause_time * 0x00010001;
4274         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4275                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4276
4277         /* Configure flow control refresh threshold value */
4278         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4279
4280 out:
4281         return ret_val;
4282 }
4283
4284 static int
4285 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4286 {
4287         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4288         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4289
4290         if (hw->mac.type != ixgbe_mac_82598EB) {
4291                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4292         }
4293         return ret_val;
4294 }
4295
4296 static int
4297 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4298 {
4299         int err;
4300         uint32_t rx_buf_size;
4301         uint32_t max_high_water;
4302         uint8_t tc_num;
4303         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4304         struct ixgbe_hw *hw =
4305                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4306         struct ixgbe_dcb_config *dcb_config =
4307                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4308
4309         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4310                 ixgbe_fc_none,
4311                 ixgbe_fc_rx_pause,
4312                 ixgbe_fc_tx_pause,
4313                 ixgbe_fc_full
4314         };
4315
4316         PMD_INIT_FUNC_TRACE();
4317
4318         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4319         tc_num = map[pfc_conf->priority];
4320         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4321         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4322         /*
4323          * At least reserve one Ethernet frame for watermark
4324          * high_water/low_water in kilo bytes for ixgbe
4325          */
4326         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4327         if ((pfc_conf->fc.high_water > max_high_water) ||
4328             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4329                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4330                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4331                 return -EINVAL;
4332         }
4333
4334         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4335         hw->fc.pause_time = pfc_conf->fc.pause_time;
4336         hw->fc.send_xon = pfc_conf->fc.send_xon;
4337         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4338         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4339
4340         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4341
4342         /* Not negotiated is not an error case */
4343         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4344                 return 0;
4345
4346         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4347         return -EIO;
4348 }
4349
4350 static int
4351 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4352                           struct rte_eth_rss_reta_entry64 *reta_conf,
4353                           uint16_t reta_size)
4354 {
4355         uint16_t i, sp_reta_size;
4356         uint8_t j, mask;
4357         uint32_t reta, r;
4358         uint16_t idx, shift;
4359         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360         uint32_t reta_reg;
4361
4362         PMD_INIT_FUNC_TRACE();
4363
4364         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4365                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4366                         "NIC.");
4367                 return -ENOTSUP;
4368         }
4369
4370         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4371         if (reta_size != sp_reta_size) {
4372                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4373                         "(%d) doesn't match the number hardware can supported "
4374                         "(%d)", reta_size, sp_reta_size);
4375                 return -EINVAL;
4376         }
4377
4378         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4379                 idx = i / RTE_RETA_GROUP_SIZE;
4380                 shift = i % RTE_RETA_GROUP_SIZE;
4381                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4382                                                 IXGBE_4_BIT_MASK);
4383                 if (!mask)
4384                         continue;
4385                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4386                 if (mask == IXGBE_4_BIT_MASK)
4387                         r = 0;
4388                 else
4389                         r = IXGBE_READ_REG(hw, reta_reg);
4390                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4391                         if (mask & (0x1 << j))
4392                                 reta |= reta_conf[idx].reta[shift + j] <<
4393                                                         (CHAR_BIT * j);
4394                         else
4395                                 reta |= r & (IXGBE_8_BIT_MASK <<
4396                                                 (CHAR_BIT * j));
4397                 }
4398                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4399         }
4400
4401         return 0;
4402 }
4403
4404 static int
4405 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4406                          struct rte_eth_rss_reta_entry64 *reta_conf,
4407                          uint16_t reta_size)
4408 {
4409         uint16_t i, sp_reta_size;
4410         uint8_t j, mask;
4411         uint32_t reta;
4412         uint16_t idx, shift;
4413         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4414         uint32_t reta_reg;
4415
4416         PMD_INIT_FUNC_TRACE();
4417         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4418         if (reta_size != sp_reta_size) {
4419                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4420                         "(%d) doesn't match the number hardware can supported "
4421                         "(%d)", reta_size, sp_reta_size);
4422                 return -EINVAL;
4423         }
4424
4425         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4426                 idx = i / RTE_RETA_GROUP_SIZE;
4427                 shift = i % RTE_RETA_GROUP_SIZE;
4428                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4429                                                 IXGBE_4_BIT_MASK);
4430                 if (!mask)
4431                         continue;
4432
4433                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4434                 reta = IXGBE_READ_REG(hw, reta_reg);
4435                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4436                         if (mask & (0x1 << j))
4437                                 reta_conf[idx].reta[shift + j] =
4438                                         ((reta >> (CHAR_BIT * j)) &
4439                                                 IXGBE_8_BIT_MASK);
4440                 }
4441         }
4442
4443         return 0;
4444 }
4445
4446 static void
4447 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4448                                 uint32_t index, uint32_t pool)
4449 {
4450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4451         uint32_t enable_addr = 1;
4452
4453         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4454 }
4455
4456 static void
4457 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4458 {
4459         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4460
4461         ixgbe_clear_rar(hw, index);
4462 }
4463
4464 static void
4465 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4466 {
4467         ixgbe_remove_rar(dev, 0);
4468
4469         ixgbe_add_rar(dev, addr, 0, 0);
4470 }
4471
4472 static bool
4473 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4474 {
4475         if (strcmp(dev->data->drv_name, drv->driver.name))
4476                 return false;
4477
4478         return true;
4479 }
4480
4481 bool
4482 is_ixgbe_supported(struct rte_eth_dev *dev)
4483 {
4484         return is_device_supported(dev, &rte_ixgbe_pmd);
4485 }
4486
4487 static int
4488 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4489 {
4490         uint32_t hlreg0;
4491         uint32_t maxfrs;
4492         struct ixgbe_hw *hw;
4493         struct rte_eth_dev_info dev_info;
4494         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4495
4496         ixgbe_dev_info_get(dev, &dev_info);
4497
4498         /* check that mtu is within the allowed range */
4499         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4500                 return -EINVAL;
4501
4502         /* refuse mtu that requires the support of scattered packets when this
4503          * feature has not been enabled before.
4504          */
4505         if (!dev->data->scattered_rx &&
4506             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4507              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4508                 return -EINVAL;
4509
4510         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4511         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4512
4513         /* switch to jumbo mode if needed */
4514         if (frame_size > ETHER_MAX_LEN) {
4515                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4516                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4517         } else {
4518                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4519                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4520         }
4521         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4522
4523         /* update max frame size */
4524         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4525
4526         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4527         maxfrs &= 0x0000FFFF;
4528         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4529         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4530
4531         return 0;
4532 }
4533
4534 /*
4535  * Virtual Function operations
4536  */
4537 static void
4538 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4539 {
4540         PMD_INIT_FUNC_TRACE();
4541
4542         /* Clear interrupt mask to stop from interrupts being generated */
4543         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4544
4545         IXGBE_WRITE_FLUSH(hw);
4546 }
4547
4548 static void
4549 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4550 {
4551         PMD_INIT_FUNC_TRACE();
4552
4553         /* VF enable interrupt autoclean */
4554         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4555         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4556         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4557
4558         IXGBE_WRITE_FLUSH(hw);
4559 }
4560
4561 static int
4562 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4563 {
4564         struct rte_eth_conf *conf = &dev->data->dev_conf;
4565         struct ixgbe_adapter *adapter =
4566                         (struct ixgbe_adapter *)dev->data->dev_private;
4567
4568         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4569                      dev->data->port_id);
4570
4571         /*
4572          * VF has no ability to enable/disable HW CRC
4573          * Keep the persistent behavior the same as Host PF
4574          */
4575 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4576         if (!conf->rxmode.hw_strip_crc) {
4577                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4578                 conf->rxmode.hw_strip_crc = 1;
4579         }
4580 #else
4581         if (conf->rxmode.hw_strip_crc) {
4582                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4583                 conf->rxmode.hw_strip_crc = 0;
4584         }
4585 #endif
4586
4587         /*
4588          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4589          * allocation or vector Rx preconditions we will reset it.
4590          */
4591         adapter->rx_bulk_alloc_allowed = true;
4592         adapter->rx_vec_allowed = true;
4593
4594         return 0;
4595 }
4596
4597 static int
4598 ixgbevf_dev_start(struct rte_eth_dev *dev)
4599 {
4600         struct ixgbe_hw *hw =
4601                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4602         uint32_t intr_vector = 0;
4603         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4604         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4605
4606         int err, mask = 0;
4607
4608         PMD_INIT_FUNC_TRACE();
4609
4610         hw->mac.ops.reset_hw(hw);
4611         hw->mac.get_link_status = true;
4612
4613         /* negotiate mailbox API version to use with the PF. */
4614         ixgbevf_negotiate_api(hw);
4615
4616         ixgbevf_dev_tx_init(dev);
4617
4618         /* This can fail when allocating mbufs for descriptor rings */
4619         err = ixgbevf_dev_rx_init(dev);
4620         if (err) {
4621                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4622                 ixgbe_dev_clear_queues(dev);
4623                 return err;
4624         }
4625
4626         /* Set vfta */
4627         ixgbevf_set_vfta_all(dev, 1);
4628
4629         /* Set HW strip */
4630         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4631                 ETH_VLAN_EXTEND_MASK;
4632         ixgbevf_vlan_offload_set(dev, mask);
4633
4634         ixgbevf_dev_rxtx_start(dev);
4635
4636         /* check and configure queue intr-vector mapping */
4637         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4638                 intr_vector = dev->data->nb_rx_queues;
4639                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4640                         return -1;
4641         }
4642
4643         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4644                 intr_handle->intr_vec =
4645                         rte_zmalloc("intr_vec",
4646                                     dev->data->nb_rx_queues * sizeof(int), 0);
4647                 if (intr_handle->intr_vec == NULL) {
4648                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4649                                      " intr_vec", dev->data->nb_rx_queues);
4650                         return -ENOMEM;
4651                 }
4652         }
4653         ixgbevf_configure_msix(dev);
4654
4655         rte_intr_enable(intr_handle);
4656
4657         /* Re-enable interrupt for VF */
4658         ixgbevf_intr_enable(hw);
4659
4660         return 0;
4661 }
4662
4663 static void
4664 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4665 {
4666         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4667         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4668         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4669
4670         PMD_INIT_FUNC_TRACE();
4671
4672         ixgbevf_intr_disable(hw);
4673
4674         hw->adapter_stopped = 1;
4675         ixgbe_stop_adapter(hw);
4676
4677         /*
4678           * Clear what we set, but we still keep shadow_vfta to
4679           * restore after device starts
4680           */
4681         ixgbevf_set_vfta_all(dev, 0);
4682
4683         /* Clear stored conf */
4684         dev->data->scattered_rx = 0;
4685
4686         ixgbe_dev_clear_queues(dev);
4687
4688         /* Clean datapath event and queue/vec mapping */
4689         rte_intr_efd_disable(intr_handle);
4690         if (intr_handle->intr_vec != NULL) {
4691                 rte_free(intr_handle->intr_vec);
4692                 intr_handle->intr_vec = NULL;
4693         }
4694 }
4695
4696 static void
4697 ixgbevf_dev_close(struct rte_eth_dev *dev)
4698 {
4699         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700
4701         PMD_INIT_FUNC_TRACE();
4702
4703         ixgbe_reset_hw(hw);
4704
4705         ixgbevf_dev_stop(dev);
4706
4707         ixgbe_dev_free_queues(dev);
4708
4709         /**
4710          * Remove the VF MAC address ro ensure
4711          * that the VF traffic goes to the PF
4712          * after stop, close and detach of the VF
4713          **/
4714         ixgbevf_remove_mac_addr(dev, 0);
4715 }
4716
4717 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4718 {
4719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4720         struct ixgbe_vfta *shadow_vfta =
4721                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4722         int i = 0, j = 0, vfta = 0, mask = 1;
4723
4724         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4725                 vfta = shadow_vfta->vfta[i];
4726                 if (vfta) {
4727                         mask = 1;
4728                         for (j = 0; j < 32; j++) {
4729                                 if (vfta & mask)
4730                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4731                                                        on, false);
4732                                 mask <<= 1;
4733                         }
4734                 }
4735         }
4736
4737 }
4738
4739 static int
4740 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4741 {
4742         struct ixgbe_hw *hw =
4743                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744         struct ixgbe_vfta *shadow_vfta =
4745                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4746         uint32_t vid_idx = 0;
4747         uint32_t vid_bit = 0;
4748         int ret = 0;
4749
4750         PMD_INIT_FUNC_TRACE();
4751
4752         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4753         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4754         if (ret) {
4755                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4756                 return ret;
4757         }
4758         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4759         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4760
4761         /* Save what we set and retore it after device reset */
4762         if (on)
4763                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4764         else
4765                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4766
4767         return 0;
4768 }
4769
4770 static void
4771 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4772 {
4773         struct ixgbe_hw *hw =
4774                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4775         uint32_t ctrl;
4776
4777         PMD_INIT_FUNC_TRACE();
4778
4779         if (queue >= hw->mac.max_rx_queues)
4780                 return;
4781
4782         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4783         if (on)
4784                 ctrl |= IXGBE_RXDCTL_VME;
4785         else
4786                 ctrl &= ~IXGBE_RXDCTL_VME;
4787         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4788
4789         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4790 }
4791
4792 static void
4793 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4794 {
4795         struct ixgbe_hw *hw =
4796                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4797         uint16_t i;
4798         int on = 0;
4799
4800         /* VF function only support hw strip feature, others are not support */
4801         if (mask & ETH_VLAN_STRIP_MASK) {
4802                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4803
4804                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4805                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4806         }
4807 }
4808
4809 int
4810 ixgbe_vt_check(struct ixgbe_hw *hw)
4811 {
4812         uint32_t reg_val;
4813
4814         /* if Virtualization Technology is enabled */
4815         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4816         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4817                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4818                 return -1;
4819         }
4820
4821         return 0;
4822 }
4823
4824 static uint32_t
4825 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4826 {
4827         uint32_t vector = 0;
4828
4829         switch (hw->mac.mc_filter_type) {
4830         case 0:   /* use bits [47:36] of the address */
4831                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4832                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4833                 break;
4834         case 1:   /* use bits [46:35] of the address */
4835                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4836                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4837                 break;
4838         case 2:   /* use bits [45:34] of the address */
4839                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4840                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4841                 break;
4842         case 3:   /* use bits [43:32] of the address */
4843                 vector = ((uc_addr->addr_bytes[4]) |
4844                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4845                 break;
4846         default:  /* Invalid mc_filter_type */
4847                 break;
4848         }
4849
4850         /* vector can only be 12-bits or boundary will be exceeded */
4851         vector &= 0xFFF;
4852         return vector;
4853 }
4854
4855 static int
4856 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4857                         uint8_t on)
4858 {
4859         uint32_t vector;
4860         uint32_t uta_idx;
4861         uint32_t reg_val;
4862         uint32_t uta_shift;
4863         uint32_t rc;
4864         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4865         const uint32_t ixgbe_uta_bit_shift = 5;
4866         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4867         const uint32_t bit1 = 0x1;
4868
4869         struct ixgbe_hw *hw =
4870                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4871         struct ixgbe_uta_info *uta_info =
4872                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4873
4874         /* The UTA table only exists on 82599 hardware and newer */
4875         if (hw->mac.type < ixgbe_mac_82599EB)
4876                 return -ENOTSUP;
4877
4878         vector = ixgbe_uta_vector(hw, mac_addr);
4879         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4880         uta_shift = vector & ixgbe_uta_bit_mask;
4881
4882         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4883         if (rc == on)
4884                 return 0;
4885
4886         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4887         if (on) {
4888                 uta_info->uta_in_use++;
4889                 reg_val |= (bit1 << uta_shift);
4890                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4891         } else {
4892                 uta_info->uta_in_use--;
4893                 reg_val &= ~(bit1 << uta_shift);
4894                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4895         }
4896
4897         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4898
4899         if (uta_info->uta_in_use > 0)
4900                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4901                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4902         else
4903                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4904
4905         return 0;
4906 }
4907
4908 static int
4909 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4910 {
4911         int i;
4912         struct ixgbe_hw *hw =
4913                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4914         struct ixgbe_uta_info *uta_info =
4915                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4916
4917         /* The UTA table only exists on 82599 hardware and newer */
4918         if (hw->mac.type < ixgbe_mac_82599EB)
4919                 return -ENOTSUP;
4920
4921         if (on) {
4922                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4923                         uta_info->uta_shadow[i] = ~0;
4924                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4925                 }
4926         } else {
4927                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4928                         uta_info->uta_shadow[i] = 0;
4929                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4930                 }
4931         }
4932         return 0;
4933
4934 }
4935
4936 uint32_t
4937 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4938 {
4939         uint32_t new_val = orig_val;
4940
4941         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4942                 new_val |= IXGBE_VMOLR_AUPE;
4943         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4944                 new_val |= IXGBE_VMOLR_ROMPE;
4945         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4946                 new_val |= IXGBE_VMOLR_ROPE;
4947         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4948                 new_val |= IXGBE_VMOLR_BAM;
4949         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4950                 new_val |= IXGBE_VMOLR_MPE;
4951
4952         return new_val;
4953 }
4954
4955 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4956 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4957 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4958 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4959 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4960         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4961         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4962
4963 static int
4964 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4965                       struct rte_eth_mirror_conf *mirror_conf,
4966                       uint8_t rule_id, uint8_t on)
4967 {
4968         uint32_t mr_ctl, vlvf;
4969         uint32_t mp_lsb = 0;
4970         uint32_t mv_msb = 0;
4971         uint32_t mv_lsb = 0;
4972         uint32_t mp_msb = 0;
4973         uint8_t i = 0;
4974         int reg_index = 0;
4975         uint64_t vlan_mask = 0;
4976
4977         const uint8_t pool_mask_offset = 32;
4978         const uint8_t vlan_mask_offset = 32;
4979         const uint8_t dst_pool_offset = 8;
4980         const uint8_t rule_mr_offset  = 4;
4981         const uint8_t mirror_rule_mask = 0x0F;
4982
4983         struct ixgbe_mirror_info *mr_info =
4984                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4985         struct ixgbe_hw *hw =
4986                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4987         uint8_t mirror_type = 0;
4988
4989         if (ixgbe_vt_check(hw) < 0)
4990                 return -ENOTSUP;
4991
4992         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4993                 return -EINVAL;
4994
4995         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4996                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4997                             mirror_conf->rule_type);
4998                 return -EINVAL;
4999         }
5000
5001         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5002                 mirror_type |= IXGBE_MRCTL_VLME;
5003                 /* Check if vlan id is valid and find conresponding VLAN ID
5004                  * index in VLVF
5005                  */
5006                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5007                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5008                                 /* search vlan id related pool vlan filter
5009                                  * index
5010                                  */
5011                                 reg_index = ixgbe_find_vlvf_slot(
5012                                                 hw,
5013                                                 mirror_conf->vlan.vlan_id[i],
5014                                                 false);
5015                                 if (reg_index < 0)
5016                                         return -EINVAL;
5017                                 vlvf = IXGBE_READ_REG(hw,
5018                                                       IXGBE_VLVF(reg_index));
5019                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5020                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5021                                       mirror_conf->vlan.vlan_id[i]))
5022                                         vlan_mask |= (1ULL << reg_index);
5023                                 else
5024                                         return -EINVAL;
5025                         }
5026                 }
5027
5028                 if (on) {
5029                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5030                         mv_msb = vlan_mask >> vlan_mask_offset;
5031
5032                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5033                                                 mirror_conf->vlan.vlan_mask;
5034                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5035                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5036                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5037                                                 mirror_conf->vlan.vlan_id[i];
5038                         }
5039                 } else {
5040                         mv_lsb = 0;
5041                         mv_msb = 0;
5042                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5043                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5044                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5045                 }
5046         }
5047
5048         /**
5049          * if enable pool mirror, write related pool mask register,if disable
5050          * pool mirror, clear PFMRVM register
5051          */
5052         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5053                 mirror_type |= IXGBE_MRCTL_VPME;
5054                 if (on) {
5055                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5056                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5057                         mr_info->mr_conf[rule_id].pool_mask =
5058                                         mirror_conf->pool_mask;
5059
5060                 } else {
5061                         mp_lsb = 0;
5062                         mp_msb = 0;
5063                         mr_info->mr_conf[rule_id].pool_mask = 0;
5064                 }
5065         }
5066         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5067                 mirror_type |= IXGBE_MRCTL_UPME;
5068         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5069                 mirror_type |= IXGBE_MRCTL_DPME;
5070
5071         /* read  mirror control register and recalculate it */
5072         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5073
5074         if (on) {
5075                 mr_ctl |= mirror_type;
5076                 mr_ctl &= mirror_rule_mask;
5077                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5078         } else {
5079                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5080         }
5081
5082         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5083         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5084
5085         /* write mirrror control  register */
5086         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5087
5088         /* write pool mirrror control  register */
5089         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5090                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5091                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5092                                 mp_msb);
5093         }
5094         /* write VLAN mirrror control  register */
5095         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5096                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5097                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5098                                 mv_msb);
5099         }
5100
5101         return 0;
5102 }
5103
5104 static int
5105 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5106 {
5107         int mr_ctl = 0;
5108         uint32_t lsb_val = 0;
5109         uint32_t msb_val = 0;
5110         const uint8_t rule_mr_offset = 4;
5111
5112         struct ixgbe_hw *hw =
5113                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5114         struct ixgbe_mirror_info *mr_info =
5115                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5116
5117         if (ixgbe_vt_check(hw) < 0)
5118                 return -ENOTSUP;
5119
5120         memset(&mr_info->mr_conf[rule_id], 0,
5121                sizeof(struct rte_eth_mirror_conf));
5122
5123         /* clear PFVMCTL register */
5124         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5125
5126         /* clear pool mask register */
5127         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5128         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5129
5130         /* clear vlan mask register */
5131         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5132         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5133
5134         return 0;
5135 }
5136
5137 static int
5138 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5139 {
5140         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5141         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5142         uint32_t mask;
5143         struct ixgbe_hw *hw =
5144                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5145
5146         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5147         mask |= (1 << IXGBE_MISC_VEC_ID);
5148         RTE_SET_USED(queue_id);
5149         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5150
5151         rte_intr_enable(intr_handle);
5152
5153         return 0;
5154 }
5155
5156 static int
5157 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5158 {
5159         uint32_t mask;
5160         struct ixgbe_hw *hw =
5161                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5162
5163         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5164         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5165         RTE_SET_USED(queue_id);
5166         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5167
5168         return 0;
5169 }
5170
5171 static int
5172 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5173 {
5174         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5175         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5176         uint32_t mask;
5177         struct ixgbe_hw *hw =
5178                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5179         struct ixgbe_interrupt *intr =
5180                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5181
5182         if (queue_id < 16) {
5183                 ixgbe_disable_intr(hw);
5184                 intr->mask |= (1 << queue_id);
5185                 ixgbe_enable_intr(dev);
5186         } else if (queue_id < 32) {
5187                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5188                 mask &= (1 << queue_id);
5189                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5190         } else if (queue_id < 64) {
5191                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5192                 mask &= (1 << (queue_id - 32));
5193                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5194         }
5195         rte_intr_enable(intr_handle);
5196
5197         return 0;
5198 }
5199
5200 static int
5201 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5202 {
5203         uint32_t mask;
5204         struct ixgbe_hw *hw =
5205                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5206         struct ixgbe_interrupt *intr =
5207                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5208
5209         if (queue_id < 16) {
5210                 ixgbe_disable_intr(hw);
5211                 intr->mask &= ~(1 << queue_id);
5212                 ixgbe_enable_intr(dev);
5213         } else if (queue_id < 32) {
5214                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5215                 mask &= ~(1 << queue_id);
5216                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5217         } else if (queue_id < 64) {
5218                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5219                 mask &= ~(1 << (queue_id - 32));
5220                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5221         }
5222
5223         return 0;
5224 }
5225
5226 static void
5227 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5228                      uint8_t queue, uint8_t msix_vector)
5229 {
5230         uint32_t tmp, idx;
5231
5232         if (direction == -1) {
5233                 /* other causes */
5234                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5235                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5236                 tmp &= ~0xFF;
5237                 tmp |= msix_vector;
5238                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5239         } else {
5240                 /* rx or tx cause */
5241                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5242                 idx = ((16 * (queue & 1)) + (8 * direction));
5243                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5244                 tmp &= ~(0xFF << idx);
5245                 tmp |= (msix_vector << idx);
5246                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5247         }
5248 }
5249
5250 /**
5251  * set the IVAR registers, mapping interrupt causes to vectors
5252  * @param hw
5253  *  pointer to ixgbe_hw struct
5254  * @direction
5255  *  0 for Rx, 1 for Tx, -1 for other causes
5256  * @queue
5257  *  queue to map the corresponding interrupt to
5258  * @msix_vector
5259  *  the vector to map to the corresponding queue
5260  */
5261 static void
5262 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5263                    uint8_t queue, uint8_t msix_vector)
5264 {
5265         uint32_t tmp, idx;
5266
5267         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5268         if (hw->mac.type == ixgbe_mac_82598EB) {
5269                 if (direction == -1)
5270                         direction = 0;
5271                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5272                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5273                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5274                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5275                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5276         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5277                         (hw->mac.type == ixgbe_mac_X540)) {
5278                 if (direction == -1) {
5279                         /* other causes */
5280                         idx = ((queue & 1) * 8);
5281                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5282                         tmp &= ~(0xFF << idx);
5283                         tmp |= (msix_vector << idx);
5284                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5285                 } else {
5286                         /* rx or tx causes */
5287                         idx = ((16 * (queue & 1)) + (8 * direction));
5288                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5289                         tmp &= ~(0xFF << idx);
5290                         tmp |= (msix_vector << idx);
5291                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5292                 }
5293         }
5294 }
5295
5296 static void
5297 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5298 {
5299         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5300         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5301         struct ixgbe_hw *hw =
5302                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303         uint32_t q_idx;
5304         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5305
5306         /* Configure VF other cause ivar */
5307         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5308
5309         /* won't configure msix register if no mapping is done
5310          * between intr vector and event fd.
5311          */
5312         if (!rte_intr_dp_is_en(intr_handle))
5313                 return;
5314
5315         /* Configure all RX queues of VF */
5316         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5317                 /* Force all queue use vector 0,
5318                  * as IXGBE_VF_MAXMSIVECOTR = 1
5319                  */
5320                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5321                 intr_handle->intr_vec[q_idx] = vector_idx;
5322         }
5323 }
5324
5325 /**
5326  * Sets up the hardware to properly generate MSI-X interrupts
5327  * @hw
5328  *  board private structure
5329  */
5330 static void
5331 ixgbe_configure_msix(struct rte_eth_dev *dev)
5332 {
5333         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5334         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5335         struct ixgbe_hw *hw =
5336                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5337         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5338         uint32_t vec = IXGBE_MISC_VEC_ID;
5339         uint32_t mask;
5340         uint32_t gpie;
5341
5342         /* won't configure msix register if no mapping is done
5343          * between intr vector and event fd
5344          */
5345         if (!rte_intr_dp_is_en(intr_handle))
5346                 return;
5347
5348         if (rte_intr_allow_others(intr_handle))
5349                 vec = base = IXGBE_RX_VEC_START;
5350
5351         /* setup GPIE for MSI-x mode */
5352         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5353         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5354                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5355         /* auto clearing and auto setting corresponding bits in EIMS
5356          * when MSI-X interrupt is triggered
5357          */
5358         if (hw->mac.type == ixgbe_mac_82598EB) {
5359                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5360         } else {
5361                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5362                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5363         }
5364         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5365
5366         /* Populate the IVAR table and set the ITR values to the
5367          * corresponding register.
5368          */
5369         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5370              queue_id++) {
5371                 /* by default, 1:1 mapping */
5372                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5373                 intr_handle->intr_vec[queue_id] = vec;
5374                 if (vec < base + intr_handle->nb_efd - 1)
5375                         vec++;
5376         }
5377
5378         switch (hw->mac.type) {
5379         case ixgbe_mac_82598EB:
5380                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5381                                    IXGBE_MISC_VEC_ID);
5382                 break;
5383         case ixgbe_mac_82599EB:
5384         case ixgbe_mac_X540:
5385                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5386                 break;
5387         default:
5388                 break;
5389         }
5390         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5391                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5392
5393         /* set up to autoclear timer, and the vectors */
5394         mask = IXGBE_EIMS_ENABLE_MASK;
5395         mask &= ~(IXGBE_EIMS_OTHER |
5396                   IXGBE_EIMS_MAILBOX |
5397                   IXGBE_EIMS_LSC);
5398
5399         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5400 }
5401
5402 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5403         uint16_t queue_idx, uint16_t tx_rate)
5404 {
5405         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5406         uint32_t rf_dec, rf_int;
5407         uint32_t bcnrc_val;
5408         uint16_t link_speed = dev->data->dev_link.link_speed;
5409
5410         if (queue_idx >= hw->mac.max_tx_queues)
5411                 return -EINVAL;
5412
5413         if (tx_rate != 0) {
5414                 /* Calculate the rate factor values to set */
5415                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5416                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5417                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5418
5419                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5420                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5421                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5422                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5423         } else {
5424                 bcnrc_val = 0;
5425         }
5426
5427         /*
5428          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5429          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5430          * set as 0x4.
5431          */
5432         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5433                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5434                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5435                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5436                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5437         else
5438                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5439                         IXGBE_MMW_SIZE_DEFAULT);
5440
5441         /* Set RTTBCNRC of queue X */
5442         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5443         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5444         IXGBE_WRITE_FLUSH(hw);
5445
5446         return 0;
5447 }
5448
5449 static void
5450 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5451                      __attribute__((unused)) uint32_t index,
5452                      __attribute__((unused)) uint32_t pool)
5453 {
5454         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5455         int diag;
5456
5457         /*
5458          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5459          * operation. Trap this case to avoid exhausting the [very limited]
5460          * set of PF resources used to store VF MAC addresses.
5461          */
5462         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5463                 return;
5464         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5465         if (diag == 0)
5466                 return;
5467         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5468 }
5469
5470 static void
5471 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5472 {
5473         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5474         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5475         struct ether_addr *mac_addr;
5476         uint32_t i;
5477         int diag;
5478
5479         /*
5480          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5481          * not support the deletion of a given MAC address.
5482          * Instead, it imposes to delete all MAC addresses, then to add again
5483          * all MAC addresses with the exception of the one to be deleted.
5484          */
5485         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5486
5487         /*
5488          * Add again all MAC addresses, with the exception of the deleted one
5489          * and of the permanent MAC address.
5490          */
5491         for (i = 0, mac_addr = dev->data->mac_addrs;
5492              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5493                 /* Skip the deleted MAC address */
5494                 if (i == index)
5495                         continue;
5496                 /* Skip NULL MAC addresses */
5497                 if (is_zero_ether_addr(mac_addr))
5498                         continue;
5499                 /* Skip the permanent MAC address */
5500                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5501                         continue;
5502                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5503                 if (diag != 0)
5504                         PMD_DRV_LOG(ERR,
5505                                     "Adding again MAC address "
5506                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5507                                     "diag=%d",
5508                                     mac_addr->addr_bytes[0],
5509                                     mac_addr->addr_bytes[1],
5510                                     mac_addr->addr_bytes[2],
5511                                     mac_addr->addr_bytes[3],
5512                                     mac_addr->addr_bytes[4],
5513                                     mac_addr->addr_bytes[5],
5514                                     diag);
5515         }
5516 }
5517
5518 static void
5519 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5520 {
5521         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5522
5523         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5524 }
5525
5526 int
5527 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5528                         struct rte_eth_syn_filter *filter,
5529                         bool add)
5530 {
5531         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5532         struct ixgbe_filter_info *filter_info =
5533                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5534         uint32_t syn_info;
5535         uint32_t synqf;
5536
5537         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5538                 return -EINVAL;
5539
5540         syn_info = filter_info->syn_info;
5541
5542         if (add) {
5543                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5544                         return -EINVAL;
5545                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5546                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5547
5548                 if (filter->hig_pri)
5549                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5550                 else
5551                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5552         } else {
5553                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5554                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5555                         return -ENOENT;
5556                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5557         }
5558
5559         filter_info->syn_info = synqf;
5560         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5561         IXGBE_WRITE_FLUSH(hw);
5562         return 0;
5563 }
5564
5565 static int
5566 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5567                         struct rte_eth_syn_filter *filter)
5568 {
5569         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5570         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5571
5572         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5573                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5574                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5575                 return 0;
5576         }
5577         return -ENOENT;
5578 }
5579
5580 static int
5581 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5582                         enum rte_filter_op filter_op,
5583                         void *arg)
5584 {
5585         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5586         int ret;
5587
5588         MAC_TYPE_FILTER_SUP(hw->mac.type);
5589
5590         if (filter_op == RTE_ETH_FILTER_NOP)
5591                 return 0;
5592
5593         if (arg == NULL) {
5594                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5595                             filter_op);
5596                 return -EINVAL;
5597         }
5598
5599         switch (filter_op) {
5600         case RTE_ETH_FILTER_ADD:
5601                 ret = ixgbe_syn_filter_set(dev,
5602                                 (struct rte_eth_syn_filter *)arg,
5603                                 TRUE);
5604                 break;
5605         case RTE_ETH_FILTER_DELETE:
5606                 ret = ixgbe_syn_filter_set(dev,
5607                                 (struct rte_eth_syn_filter *)arg,
5608                                 FALSE);
5609                 break;
5610         case RTE_ETH_FILTER_GET:
5611                 ret = ixgbe_syn_filter_get(dev,
5612                                 (struct rte_eth_syn_filter *)arg);
5613                 break;
5614         default:
5615                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5616                 ret = -EINVAL;
5617                 break;
5618         }
5619
5620         return ret;
5621 }
5622
5623
5624 static inline enum ixgbe_5tuple_protocol
5625 convert_protocol_type(uint8_t protocol_value)
5626 {
5627         if (protocol_value == IPPROTO_TCP)
5628                 return IXGBE_FILTER_PROTOCOL_TCP;
5629         else if (protocol_value == IPPROTO_UDP)
5630                 return IXGBE_FILTER_PROTOCOL_UDP;
5631         else if (protocol_value == IPPROTO_SCTP)
5632                 return IXGBE_FILTER_PROTOCOL_SCTP;
5633         else
5634                 return IXGBE_FILTER_PROTOCOL_NONE;
5635 }
5636
5637 /* inject a 5-tuple filter to HW */
5638 static inline void
5639 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5640                            struct ixgbe_5tuple_filter *filter)
5641 {
5642         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5643         int i;
5644         uint32_t ftqf, sdpqf;
5645         uint32_t l34timir = 0;
5646         uint8_t mask = 0xff;
5647
5648         i = filter->index;
5649
5650         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5651                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5652         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5653
5654         ftqf = (uint32_t)(filter->filter_info.proto &
5655                 IXGBE_FTQF_PROTOCOL_MASK);
5656         ftqf |= (uint32_t)((filter->filter_info.priority &
5657                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5658         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5659                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5660         if (filter->filter_info.dst_ip_mask == 0)
5661                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5662         if (filter->filter_info.src_port_mask == 0)
5663                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5664         if (filter->filter_info.dst_port_mask == 0)
5665                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5666         if (filter->filter_info.proto_mask == 0)
5667                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5668         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5669         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5670         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5671
5672         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5673         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5674         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5675         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5676
5677         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5678         l34timir |= (uint32_t)(filter->queue <<
5679                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5680         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5681 }
5682
5683 /*
5684  * add a 5tuple filter
5685  *
5686  * @param
5687  * dev: Pointer to struct rte_eth_dev.
5688  * index: the index the filter allocates.
5689  * filter: ponter to the filter that will be added.
5690  * rx_queue: the queue id the filter assigned to.
5691  *
5692  * @return
5693  *    - On success, zero.
5694  *    - On failure, a negative value.
5695  */
5696 static int
5697 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5698                         struct ixgbe_5tuple_filter *filter)
5699 {
5700         struct ixgbe_filter_info *filter_info =
5701                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5702         int i, idx, shift;
5703
5704         /*
5705          * look for an unused 5tuple filter index,
5706          * and insert the filter to list.
5707          */
5708         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5709                 idx = i / (sizeof(uint32_t) * NBBY);
5710                 shift = i % (sizeof(uint32_t) * NBBY);
5711                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5712                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5713                         filter->index = i;
5714                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5715                                           filter,
5716                                           entries);
5717                         break;
5718                 }
5719         }
5720         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5721                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5722                 return -ENOSYS;
5723         }
5724
5725         ixgbe_inject_5tuple_filter(dev, filter);
5726
5727         return 0;
5728 }
5729
5730 /*
5731  * remove a 5tuple filter
5732  *
5733  * @param
5734  * dev: Pointer to struct rte_eth_dev.
5735  * filter: the pointer of the filter will be removed.
5736  */
5737 static void
5738 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5739                         struct ixgbe_5tuple_filter *filter)
5740 {
5741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5742         struct ixgbe_filter_info *filter_info =
5743                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5744         uint16_t index = filter->index;
5745
5746         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5747                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5748         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5749         rte_free(filter);
5750
5751         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5752         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5753         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5754         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5755         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5756 }
5757
5758 static int
5759 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5760 {
5761         struct ixgbe_hw *hw;
5762         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5763
5764         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5765
5766         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5767                 return -EINVAL;
5768
5769         /* refuse mtu that requires the support of scattered packets when this
5770          * feature has not been enabled before.
5771          */
5772         if (!dev->data->scattered_rx &&
5773             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5774              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5775                 return -EINVAL;
5776
5777         /*
5778          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5779          * request of the version 2.0 of the mailbox API.
5780          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5781          * of the mailbox API.
5782          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5783          * prior to 3.11.33 which contains the following change:
5784          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5785          */
5786         ixgbevf_rlpml_set_vf(hw, max_frame);
5787
5788         /* update max frame size */
5789         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5790         return 0;
5791 }
5792
5793 static inline struct ixgbe_5tuple_filter *
5794 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5795                         struct ixgbe_5tuple_filter_info *key)
5796 {
5797         struct ixgbe_5tuple_filter *it;
5798
5799         TAILQ_FOREACH(it, filter_list, entries) {
5800                 if (memcmp(key, &it->filter_info,
5801                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5802                         return it;
5803                 }
5804         }
5805         return NULL;
5806 }
5807
5808 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5809 static inline int
5810 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5811                         struct ixgbe_5tuple_filter_info *filter_info)
5812 {
5813         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5814                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5815                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5816                 return -EINVAL;
5817
5818         switch (filter->dst_ip_mask) {
5819         case UINT32_MAX:
5820                 filter_info->dst_ip_mask = 0;
5821                 filter_info->dst_ip = filter->dst_ip;
5822                 break;
5823         case 0:
5824                 filter_info->dst_ip_mask = 1;
5825                 break;
5826         default:
5827                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5828                 return -EINVAL;
5829         }
5830
5831         switch (filter->src_ip_mask) {
5832         case UINT32_MAX:
5833                 filter_info->src_ip_mask = 0;
5834                 filter_info->src_ip = filter->src_ip;
5835                 break;
5836         case 0:
5837                 filter_info->src_ip_mask = 1;
5838                 break;
5839         default:
5840                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5841                 return -EINVAL;
5842         }
5843
5844         switch (filter->dst_port_mask) {
5845         case UINT16_MAX:
5846                 filter_info->dst_port_mask = 0;
5847                 filter_info->dst_port = filter->dst_port;
5848                 break;
5849         case 0:
5850                 filter_info->dst_port_mask = 1;
5851                 break;
5852         default:
5853                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5854                 return -EINVAL;
5855         }
5856
5857         switch (filter->src_port_mask) {
5858         case UINT16_MAX:
5859                 filter_info->src_port_mask = 0;
5860                 filter_info->src_port = filter->src_port;
5861                 break;
5862         case 0:
5863                 filter_info->src_port_mask = 1;
5864                 break;
5865         default:
5866                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5867                 return -EINVAL;
5868         }
5869
5870         switch (filter->proto_mask) {
5871         case UINT8_MAX:
5872                 filter_info->proto_mask = 0;
5873                 filter_info->proto =
5874                         convert_protocol_type(filter->proto);
5875                 break;
5876         case 0:
5877                 filter_info->proto_mask = 1;
5878                 break;
5879         default:
5880                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5881                 return -EINVAL;
5882         }
5883
5884         filter_info->priority = (uint8_t)filter->priority;
5885         return 0;
5886 }
5887
5888 /*
5889  * add or delete a ntuple filter
5890  *
5891  * @param
5892  * dev: Pointer to struct rte_eth_dev.
5893  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5894  * add: if true, add filter, if false, remove filter
5895  *
5896  * @return
5897  *    - On success, zero.
5898  *    - On failure, a negative value.
5899  */
5900 int
5901 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5902                         struct rte_eth_ntuple_filter *ntuple_filter,
5903                         bool add)
5904 {
5905         struct ixgbe_filter_info *filter_info =
5906                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5907         struct ixgbe_5tuple_filter_info filter_5tuple;
5908         struct ixgbe_5tuple_filter *filter;
5909         int ret;
5910
5911         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5912                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5913                 return -EINVAL;
5914         }
5915
5916         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5917         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5918         if (ret < 0)
5919                 return ret;
5920
5921         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5922                                          &filter_5tuple);
5923         if (filter != NULL && add) {
5924                 PMD_DRV_LOG(ERR, "filter exists.");
5925                 return -EEXIST;
5926         }
5927         if (filter == NULL && !add) {
5928                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5929                 return -ENOENT;
5930         }
5931
5932         if (add) {
5933                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5934                                 sizeof(struct ixgbe_5tuple_filter), 0);
5935                 if (filter == NULL)
5936                         return -ENOMEM;
5937                 (void)rte_memcpy(&filter->filter_info,
5938                                  &filter_5tuple,
5939                                  sizeof(struct ixgbe_5tuple_filter_info));
5940                 filter->queue = ntuple_filter->queue;
5941                 ret = ixgbe_add_5tuple_filter(dev, filter);
5942                 if (ret < 0) {
5943                         rte_free(filter);
5944                         return ret;
5945                 }
5946         } else
5947                 ixgbe_remove_5tuple_filter(dev, filter);
5948
5949         return 0;
5950 }
5951
5952 /*
5953  * get a ntuple filter
5954  *
5955  * @param
5956  * dev: Pointer to struct rte_eth_dev.
5957  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5958  *
5959  * @return
5960  *    - On success, zero.
5961  *    - On failure, a negative value.
5962  */
5963 static int
5964 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5965                         struct rte_eth_ntuple_filter *ntuple_filter)
5966 {
5967         struct ixgbe_filter_info *filter_info =
5968                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5969         struct ixgbe_5tuple_filter_info filter_5tuple;
5970         struct ixgbe_5tuple_filter *filter;
5971         int ret;
5972
5973         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5974                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5975                 return -EINVAL;
5976         }
5977
5978         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5979         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5980         if (ret < 0)
5981                 return ret;
5982
5983         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5984                                          &filter_5tuple);
5985         if (filter == NULL) {
5986                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5987                 return -ENOENT;
5988         }
5989         ntuple_filter->queue = filter->queue;
5990         return 0;
5991 }
5992
5993 /*
5994  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5995  * @dev: pointer to rte_eth_dev structure
5996  * @filter_op:operation will be taken.
5997  * @arg: a pointer to specific structure corresponding to the filter_op
5998  *
5999  * @return
6000  *    - On success, zero.
6001  *    - On failure, a negative value.
6002  */
6003 static int
6004 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6005                                 enum rte_filter_op filter_op,
6006                                 void *arg)
6007 {
6008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6009         int ret;
6010
6011         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6012
6013         if (filter_op == RTE_ETH_FILTER_NOP)
6014                 return 0;
6015
6016         if (arg == NULL) {
6017                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6018                             filter_op);
6019                 return -EINVAL;
6020         }
6021
6022         switch (filter_op) {
6023         case RTE_ETH_FILTER_ADD:
6024                 ret = ixgbe_add_del_ntuple_filter(dev,
6025                         (struct rte_eth_ntuple_filter *)arg,
6026                         TRUE);
6027                 break;
6028         case RTE_ETH_FILTER_DELETE:
6029                 ret = ixgbe_add_del_ntuple_filter(dev,
6030                         (struct rte_eth_ntuple_filter *)arg,
6031                         FALSE);
6032                 break;
6033         case RTE_ETH_FILTER_GET:
6034                 ret = ixgbe_get_ntuple_filter(dev,
6035                         (struct rte_eth_ntuple_filter *)arg);
6036                 break;
6037         default:
6038                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6039                 ret = -EINVAL;
6040                 break;
6041         }
6042         return ret;
6043 }
6044
6045 int
6046 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6047                         struct rte_eth_ethertype_filter *filter,
6048                         bool add)
6049 {
6050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6051         struct ixgbe_filter_info *filter_info =
6052                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6053         uint32_t etqf = 0;
6054         uint32_t etqs = 0;
6055         int ret;
6056         struct ixgbe_ethertype_filter ethertype_filter;
6057
6058         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6059                 return -EINVAL;
6060
6061         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6062                 filter->ether_type == ETHER_TYPE_IPv6) {
6063                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6064                         " ethertype filter.", filter->ether_type);
6065                 return -EINVAL;
6066         }
6067
6068         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6069                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6070                 return -EINVAL;
6071         }
6072         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6073                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6074                 return -EINVAL;
6075         }
6076
6077         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6078         if (ret >= 0 && add) {
6079                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6080                             filter->ether_type);
6081                 return -EEXIST;
6082         }
6083         if (ret < 0 && !add) {
6084                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6085                             filter->ether_type);
6086                 return -ENOENT;
6087         }
6088
6089         if (add) {
6090                 etqf = IXGBE_ETQF_FILTER_EN;
6091                 etqf |= (uint32_t)filter->ether_type;
6092                 etqs |= (uint32_t)((filter->queue <<
6093                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6094                                     IXGBE_ETQS_RX_QUEUE);
6095                 etqs |= IXGBE_ETQS_QUEUE_EN;
6096
6097                 ethertype_filter.ethertype = filter->ether_type;
6098                 ethertype_filter.etqf = etqf;
6099                 ethertype_filter.etqs = etqs;
6100                 ethertype_filter.conf = FALSE;
6101                 ret = ixgbe_ethertype_filter_insert(filter_info,
6102                                                     &ethertype_filter);
6103                 if (ret < 0) {
6104                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6105                         return -ENOSPC;
6106                 }
6107         } else {
6108                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6109                 if (ret < 0)
6110                         return -ENOSYS;
6111         }
6112         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6113         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6114         IXGBE_WRITE_FLUSH(hw);
6115
6116         return 0;
6117 }
6118
6119 static int
6120 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6121                         struct rte_eth_ethertype_filter *filter)
6122 {
6123         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6124         struct ixgbe_filter_info *filter_info =
6125                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6126         uint32_t etqf, etqs;
6127         int ret;
6128
6129         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6130         if (ret < 0) {
6131                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6132                             filter->ether_type);
6133                 return -ENOENT;
6134         }
6135
6136         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6137         if (etqf & IXGBE_ETQF_FILTER_EN) {
6138                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6139                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6140                 filter->flags = 0;
6141                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6142                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6143                 return 0;
6144         }
6145         return -ENOENT;
6146 }
6147
6148 /*
6149  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6150  * @dev: pointer to rte_eth_dev structure
6151  * @filter_op:operation will be taken.
6152  * @arg: a pointer to specific structure corresponding to the filter_op
6153  */
6154 static int
6155 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6156                                 enum rte_filter_op filter_op,
6157                                 void *arg)
6158 {
6159         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6160         int ret;
6161
6162         MAC_TYPE_FILTER_SUP(hw->mac.type);
6163
6164         if (filter_op == RTE_ETH_FILTER_NOP)
6165                 return 0;
6166
6167         if (arg == NULL) {
6168                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6169                             filter_op);
6170                 return -EINVAL;
6171         }
6172
6173         switch (filter_op) {
6174         case RTE_ETH_FILTER_ADD:
6175                 ret = ixgbe_add_del_ethertype_filter(dev,
6176                         (struct rte_eth_ethertype_filter *)arg,
6177                         TRUE);
6178                 break;
6179         case RTE_ETH_FILTER_DELETE:
6180                 ret = ixgbe_add_del_ethertype_filter(dev,
6181                         (struct rte_eth_ethertype_filter *)arg,
6182                         FALSE);
6183                 break;
6184         case RTE_ETH_FILTER_GET:
6185                 ret = ixgbe_get_ethertype_filter(dev,
6186                         (struct rte_eth_ethertype_filter *)arg);
6187                 break;
6188         default:
6189                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6190                 ret = -EINVAL;
6191                 break;
6192         }
6193         return ret;
6194 }
6195
6196 static int
6197 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6198                      enum rte_filter_type filter_type,
6199                      enum rte_filter_op filter_op,
6200                      void *arg)
6201 {
6202         int ret = 0;
6203
6204         switch (filter_type) {
6205         case RTE_ETH_FILTER_NTUPLE:
6206                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6207                 break;
6208         case RTE_ETH_FILTER_ETHERTYPE:
6209                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6210                 break;
6211         case RTE_ETH_FILTER_SYN:
6212                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6213                 break;
6214         case RTE_ETH_FILTER_FDIR:
6215                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6216                 break;
6217         case RTE_ETH_FILTER_L2_TUNNEL:
6218                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6219                 break;
6220         case RTE_ETH_FILTER_GENERIC:
6221                 if (filter_op != RTE_ETH_FILTER_GET)
6222                         return -EINVAL;
6223                 *(const void **)arg = &ixgbe_flow_ops;
6224                 break;
6225         default:
6226                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6227                                                         filter_type);
6228                 ret = -EINVAL;
6229                 break;
6230         }
6231
6232         return ret;
6233 }
6234
6235 static u8 *
6236 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6237                         u8 **mc_addr_ptr, u32 *vmdq)
6238 {
6239         u8 *mc_addr;
6240
6241         *vmdq = 0;
6242         mc_addr = *mc_addr_ptr;
6243         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6244         return mc_addr;
6245 }
6246
6247 static int
6248 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6249                           struct ether_addr *mc_addr_set,
6250                           uint32_t nb_mc_addr)
6251 {
6252         struct ixgbe_hw *hw;
6253         u8 *mc_addr_list;
6254
6255         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6256         mc_addr_list = (u8 *)mc_addr_set;
6257         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6258                                          ixgbe_dev_addr_list_itr, TRUE);
6259 }
6260
6261 static uint64_t
6262 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6263 {
6264         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6265         uint64_t systime_cycles;
6266
6267         switch (hw->mac.type) {
6268         case ixgbe_mac_X550:
6269         case ixgbe_mac_X550EM_x:
6270         case ixgbe_mac_X550EM_a:
6271                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6272                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6273                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6274                                 * NSEC_PER_SEC;
6275                 break;
6276         default:
6277                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6278                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6279                                 << 32;
6280         }
6281
6282         return systime_cycles;
6283 }
6284
6285 static uint64_t
6286 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6287 {
6288         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6289         uint64_t rx_tstamp_cycles;
6290
6291         switch (hw->mac.type) {
6292         case ixgbe_mac_X550:
6293         case ixgbe_mac_X550EM_x:
6294         case ixgbe_mac_X550EM_a:
6295                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6296                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6297                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6298                                 * NSEC_PER_SEC;
6299                 break;
6300         default:
6301                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6302                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6303                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6304                                 << 32;
6305         }
6306
6307         return rx_tstamp_cycles;
6308 }
6309
6310 static uint64_t
6311 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6312 {
6313         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6314         uint64_t tx_tstamp_cycles;
6315
6316         switch (hw->mac.type) {
6317         case ixgbe_mac_X550:
6318         case ixgbe_mac_X550EM_x:
6319         case ixgbe_mac_X550EM_a:
6320                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6321                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6322                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6323                                 * NSEC_PER_SEC;
6324                 break;
6325         default:
6326                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6327                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6328                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6329                                 << 32;
6330         }
6331
6332         return tx_tstamp_cycles;
6333 }
6334
6335 static void
6336 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6337 {
6338         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6339         struct ixgbe_adapter *adapter =
6340                 (struct ixgbe_adapter *)dev->data->dev_private;
6341         struct rte_eth_link link;
6342         uint32_t incval = 0;
6343         uint32_t shift = 0;
6344
6345         /* Get current link speed. */
6346         memset(&link, 0, sizeof(link));
6347         ixgbe_dev_link_update(dev, 1);
6348         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6349
6350         switch (link.link_speed) {
6351         case ETH_SPEED_NUM_100M:
6352                 incval = IXGBE_INCVAL_100;
6353                 shift = IXGBE_INCVAL_SHIFT_100;
6354                 break;
6355         case ETH_SPEED_NUM_1G:
6356                 incval = IXGBE_INCVAL_1GB;
6357                 shift = IXGBE_INCVAL_SHIFT_1GB;
6358                 break;
6359         case ETH_SPEED_NUM_10G:
6360         default:
6361                 incval = IXGBE_INCVAL_10GB;
6362                 shift = IXGBE_INCVAL_SHIFT_10GB;
6363                 break;
6364         }
6365
6366         switch (hw->mac.type) {
6367         case ixgbe_mac_X550:
6368         case ixgbe_mac_X550EM_x:
6369         case ixgbe_mac_X550EM_a:
6370                 /* Independent of link speed. */
6371                 incval = 1;
6372                 /* Cycles read will be interpreted as ns. */
6373                 shift = 0;
6374                 /* Fall-through */
6375         case ixgbe_mac_X540:
6376                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6377                 break;
6378         case ixgbe_mac_82599EB:
6379                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6380                 shift -= IXGBE_INCVAL_SHIFT_82599;
6381                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6382                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6383                 break;
6384         default:
6385                 /* Not supported. */
6386                 return;
6387         }
6388
6389         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6390         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6391         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6392
6393         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6394         adapter->systime_tc.cc_shift = shift;
6395         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6396
6397         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6398         adapter->rx_tstamp_tc.cc_shift = shift;
6399         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6400
6401         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6402         adapter->tx_tstamp_tc.cc_shift = shift;
6403         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6404 }
6405
6406 static int
6407 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6408 {
6409         struct ixgbe_adapter *adapter =
6410                         (struct ixgbe_adapter *)dev->data->dev_private;
6411
6412         adapter->systime_tc.nsec += delta;
6413         adapter->rx_tstamp_tc.nsec += delta;
6414         adapter->tx_tstamp_tc.nsec += delta;
6415
6416         return 0;
6417 }
6418
6419 static int
6420 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6421 {
6422         uint64_t ns;
6423         struct ixgbe_adapter *adapter =
6424                         (struct ixgbe_adapter *)dev->data->dev_private;
6425
6426         ns = rte_timespec_to_ns(ts);
6427         /* Set the timecounters to a new value. */
6428         adapter->systime_tc.nsec = ns;
6429         adapter->rx_tstamp_tc.nsec = ns;
6430         adapter->tx_tstamp_tc.nsec = ns;
6431
6432         return 0;
6433 }
6434
6435 static int
6436 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6437 {
6438         uint64_t ns, systime_cycles;
6439         struct ixgbe_adapter *adapter =
6440                         (struct ixgbe_adapter *)dev->data->dev_private;
6441
6442         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6443         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6444         *ts = rte_ns_to_timespec(ns);
6445
6446         return 0;
6447 }
6448
6449 static int
6450 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6451 {
6452         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6453         uint32_t tsync_ctl;
6454         uint32_t tsauxc;
6455
6456         /* Stop the timesync system time. */
6457         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6458         /* Reset the timesync system time value. */
6459         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6460         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6461
6462         /* Enable system time for platforms where it isn't on by default. */
6463         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6464         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6465         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6466
6467         ixgbe_start_timecounters(dev);
6468
6469         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6470         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6471                         (ETHER_TYPE_1588 |
6472                          IXGBE_ETQF_FILTER_EN |
6473                          IXGBE_ETQF_1588));
6474
6475         /* Enable timestamping of received PTP packets. */
6476         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6477         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6478         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6479
6480         /* Enable timestamping of transmitted PTP packets. */
6481         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6482         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6483         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6484
6485         IXGBE_WRITE_FLUSH(hw);
6486
6487         return 0;
6488 }
6489
6490 static int
6491 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6492 {
6493         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6494         uint32_t tsync_ctl;
6495
6496         /* Disable timestamping of transmitted PTP packets. */
6497         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6498         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6499         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6500
6501         /* Disable timestamping of received PTP packets. */
6502         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6503         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6504         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6505
6506         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6507         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6508
6509         /* Stop incrementating the System Time registers. */
6510         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6511
6512         return 0;
6513 }
6514
6515 static int
6516 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6517                                  struct timespec *timestamp,
6518                                  uint32_t flags __rte_unused)
6519 {
6520         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6521         struct ixgbe_adapter *adapter =
6522                 (struct ixgbe_adapter *)dev->data->dev_private;
6523         uint32_t tsync_rxctl;
6524         uint64_t rx_tstamp_cycles;
6525         uint64_t ns;
6526
6527         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6528         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6529                 return -EINVAL;
6530
6531         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6532         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6533         *timestamp = rte_ns_to_timespec(ns);
6534
6535         return  0;
6536 }
6537
6538 static int
6539 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6540                                  struct timespec *timestamp)
6541 {
6542         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6543         struct ixgbe_adapter *adapter =
6544                 (struct ixgbe_adapter *)dev->data->dev_private;
6545         uint32_t tsync_txctl;
6546         uint64_t tx_tstamp_cycles;
6547         uint64_t ns;
6548
6549         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6550         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6551                 return -EINVAL;
6552
6553         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6554         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6555         *timestamp = rte_ns_to_timespec(ns);
6556
6557         return 0;
6558 }
6559
6560 static int
6561 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6562 {
6563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6564         int count = 0;
6565         int g_ind = 0;
6566         const struct reg_info *reg_group;
6567         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6568                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6569
6570         while ((reg_group = reg_set[g_ind++]))
6571                 count += ixgbe_regs_group_count(reg_group);
6572
6573         return count;
6574 }
6575
6576 static int
6577 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6578 {
6579         int count = 0;
6580         int g_ind = 0;
6581         const struct reg_info *reg_group;
6582
6583         while ((reg_group = ixgbevf_regs[g_ind++]))
6584                 count += ixgbe_regs_group_count(reg_group);
6585
6586         return count;
6587 }
6588
6589 static int
6590 ixgbe_get_regs(struct rte_eth_dev *dev,
6591               struct rte_dev_reg_info *regs)
6592 {
6593         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6594         uint32_t *data = regs->data;
6595         int g_ind = 0;
6596         int count = 0;
6597         const struct reg_info *reg_group;
6598         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6599                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6600
6601         if (data == NULL) {
6602                 regs->length = ixgbe_get_reg_length(dev);
6603                 regs->width = sizeof(uint32_t);
6604                 return 0;
6605         }
6606
6607         /* Support only full register dump */
6608         if ((regs->length == 0) ||
6609             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6610                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6611                         hw->device_id;
6612                 while ((reg_group = reg_set[g_ind++]))
6613                         count += ixgbe_read_regs_group(dev, &data[count],
6614                                 reg_group);
6615                 return 0;
6616         }
6617
6618         return -ENOTSUP;
6619 }
6620
6621 static int
6622 ixgbevf_get_regs(struct rte_eth_dev *dev,
6623                 struct rte_dev_reg_info *regs)
6624 {
6625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6626         uint32_t *data = regs->data;
6627         int g_ind = 0;
6628         int count = 0;
6629         const struct reg_info *reg_group;
6630
6631         if (data == NULL) {
6632                 regs->length = ixgbevf_get_reg_length(dev);
6633                 regs->width = sizeof(uint32_t);
6634                 return 0;
6635         }
6636
6637         /* Support only full register dump */
6638         if ((regs->length == 0) ||
6639             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6640                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6641                         hw->device_id;
6642                 while ((reg_group = ixgbevf_regs[g_ind++]))
6643                         count += ixgbe_read_regs_group(dev, &data[count],
6644                                                       reg_group);
6645                 return 0;
6646         }
6647
6648         return -ENOTSUP;
6649 }
6650
6651 static int
6652 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6653 {
6654         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6655
6656         /* Return unit is byte count */
6657         return hw->eeprom.word_size * 2;
6658 }
6659
6660 static int
6661 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6662                 struct rte_dev_eeprom_info *in_eeprom)
6663 {
6664         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6665         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6666         uint16_t *data = in_eeprom->data;
6667         int first, length;
6668
6669         first = in_eeprom->offset >> 1;
6670         length = in_eeprom->length >> 1;
6671         if ((first > hw->eeprom.word_size) ||
6672             ((first + length) > hw->eeprom.word_size))
6673                 return -EINVAL;
6674
6675         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6676
6677         return eeprom->ops.read_buffer(hw, first, length, data);
6678 }
6679
6680 static int
6681 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6682                 struct rte_dev_eeprom_info *in_eeprom)
6683 {
6684         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6685         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6686         uint16_t *data = in_eeprom->data;
6687         int first, length;
6688
6689         first = in_eeprom->offset >> 1;
6690         length = in_eeprom->length >> 1;
6691         if ((first > hw->eeprom.word_size) ||
6692             ((first + length) > hw->eeprom.word_size))
6693                 return -EINVAL;
6694
6695         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6696
6697         return eeprom->ops.write_buffer(hw,  first, length, data);
6698 }
6699
6700 uint16_t
6701 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6702         switch (mac_type) {
6703         case ixgbe_mac_X550:
6704         case ixgbe_mac_X550EM_x:
6705         case ixgbe_mac_X550EM_a:
6706                 return ETH_RSS_RETA_SIZE_512;
6707         case ixgbe_mac_X550_vf:
6708         case ixgbe_mac_X550EM_x_vf:
6709         case ixgbe_mac_X550EM_a_vf:
6710                 return ETH_RSS_RETA_SIZE_64;
6711         default:
6712                 return ETH_RSS_RETA_SIZE_128;
6713         }
6714 }
6715
6716 uint32_t
6717 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6718         switch (mac_type) {
6719         case ixgbe_mac_X550:
6720         case ixgbe_mac_X550EM_x:
6721         case ixgbe_mac_X550EM_a:
6722                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6723                         return IXGBE_RETA(reta_idx >> 2);
6724                 else
6725                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6726         case ixgbe_mac_X550_vf:
6727         case ixgbe_mac_X550EM_x_vf:
6728         case ixgbe_mac_X550EM_a_vf:
6729                 return IXGBE_VFRETA(reta_idx >> 2);
6730         default:
6731                 return IXGBE_RETA(reta_idx >> 2);
6732         }
6733 }
6734
6735 uint32_t
6736 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6737         switch (mac_type) {
6738         case ixgbe_mac_X550_vf:
6739         case ixgbe_mac_X550EM_x_vf:
6740         case ixgbe_mac_X550EM_a_vf:
6741                 return IXGBE_VFMRQC;
6742         default:
6743                 return IXGBE_MRQC;
6744         }
6745 }
6746
6747 uint32_t
6748 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6749         switch (mac_type) {
6750         case ixgbe_mac_X550_vf:
6751         case ixgbe_mac_X550EM_x_vf:
6752         case ixgbe_mac_X550EM_a_vf:
6753                 return IXGBE_VFRSSRK(i);
6754         default:
6755                 return IXGBE_RSSRK(i);
6756         }
6757 }
6758
6759 bool
6760 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6761         switch (mac_type) {
6762         case ixgbe_mac_82599_vf:
6763         case ixgbe_mac_X540_vf:
6764                 return 0;
6765         default:
6766                 return 1;
6767         }
6768 }
6769
6770 static int
6771 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6772                         struct rte_eth_dcb_info *dcb_info)
6773 {
6774         struct ixgbe_dcb_config *dcb_config =
6775                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6776         struct ixgbe_dcb_tc_config *tc;
6777         uint8_t i, j;
6778
6779         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6780                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6781         else
6782                 dcb_info->nb_tcs = 1;
6783
6784         if (dcb_config->vt_mode) { /* vt is enabled*/
6785                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6786                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6787                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6788                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6789                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6790                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6791                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6792                                                 i * dcb_info->nb_tcs + j;
6793                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6794                                 dcb_info->tc_queue.tc_txq[i][j].base =
6795                                                 i * dcb_info->nb_tcs + j;
6796                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6797                         }
6798                 }
6799         } else { /* vt is disabled*/
6800                 struct rte_eth_dcb_rx_conf *rx_conf =
6801                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6802                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6803                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6804                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6805                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6806                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6807                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6808                         }
6809                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6810                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6811                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6812                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6813                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6814                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6815                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6816                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6817                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6818                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6819                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6820                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6821                         }
6822                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6823                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6824                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6825                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6826                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6827                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6828                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6829                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6830                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6831                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6832                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6833                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6834                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6835                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6836                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6837                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6838                 }
6839         }
6840         for (i = 0; i < dcb_info->nb_tcs; i++) {
6841                 tc = &dcb_config->tc_config[i];
6842                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6843         }
6844         return 0;
6845 }
6846
6847 /* Update e-tag ether type */
6848 static int
6849 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6850                             uint16_t ether_type)
6851 {
6852         uint32_t etag_etype;
6853
6854         if (hw->mac.type != ixgbe_mac_X550 &&
6855             hw->mac.type != ixgbe_mac_X550EM_x &&
6856             hw->mac.type != ixgbe_mac_X550EM_a) {
6857                 return -ENOTSUP;
6858         }
6859
6860         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6861         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6862         etag_etype |= ether_type;
6863         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6864         IXGBE_WRITE_FLUSH(hw);
6865
6866         return 0;
6867 }
6868
6869 /* Config l2 tunnel ether type */
6870 static int
6871 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6872                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6873 {
6874         int ret = 0;
6875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6876         struct ixgbe_l2_tn_info *l2_tn_info =
6877                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
6878
6879         if (l2_tunnel == NULL)
6880                 return -EINVAL;
6881
6882         switch (l2_tunnel->l2_tunnel_type) {
6883         case RTE_L2_TUNNEL_TYPE_E_TAG:
6884                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
6885                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6886                 break;
6887         default:
6888                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6889                 ret = -EINVAL;
6890                 break;
6891         }
6892
6893         return ret;
6894 }
6895
6896 /* Enable e-tag tunnel */
6897 static int
6898 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6899 {
6900         uint32_t etag_etype;
6901
6902         if (hw->mac.type != ixgbe_mac_X550 &&
6903             hw->mac.type != ixgbe_mac_X550EM_x &&
6904             hw->mac.type != ixgbe_mac_X550EM_a) {
6905                 return -ENOTSUP;
6906         }
6907
6908         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6909         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6910         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6911         IXGBE_WRITE_FLUSH(hw);
6912
6913         return 0;
6914 }
6915
6916 /* Enable l2 tunnel */
6917 static int
6918 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6919                            enum rte_eth_tunnel_type l2_tunnel_type)
6920 {
6921         int ret = 0;
6922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6923         struct ixgbe_l2_tn_info *l2_tn_info =
6924                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
6925
6926         switch (l2_tunnel_type) {
6927         case RTE_L2_TUNNEL_TYPE_E_TAG:
6928                 l2_tn_info->e_tag_en = TRUE;
6929                 ret = ixgbe_e_tag_enable(hw);
6930                 break;
6931         default:
6932                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6933                 ret = -EINVAL;
6934                 break;
6935         }
6936
6937         return ret;
6938 }
6939
6940 /* Disable e-tag tunnel */
6941 static int
6942 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6943 {
6944         uint32_t etag_etype;
6945
6946         if (hw->mac.type != ixgbe_mac_X550 &&
6947             hw->mac.type != ixgbe_mac_X550EM_x &&
6948             hw->mac.type != ixgbe_mac_X550EM_a) {
6949                 return -ENOTSUP;
6950         }
6951
6952         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6953         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6954         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6955         IXGBE_WRITE_FLUSH(hw);
6956
6957         return 0;
6958 }
6959
6960 /* Disable l2 tunnel */
6961 static int
6962 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6963                             enum rte_eth_tunnel_type l2_tunnel_type)
6964 {
6965         int ret = 0;
6966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6967         struct ixgbe_l2_tn_info *l2_tn_info =
6968                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
6969
6970         switch (l2_tunnel_type) {
6971         case RTE_L2_TUNNEL_TYPE_E_TAG:
6972                 l2_tn_info->e_tag_en = FALSE;
6973                 ret = ixgbe_e_tag_disable(hw);
6974                 break;
6975         default:
6976                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6977                 ret = -EINVAL;
6978                 break;
6979         }
6980
6981         return ret;
6982 }
6983
6984 static int
6985 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6986                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6987 {
6988         int ret = 0;
6989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6990         uint32_t i, rar_entries;
6991         uint32_t rar_low, rar_high;
6992
6993         if (hw->mac.type != ixgbe_mac_X550 &&
6994             hw->mac.type != ixgbe_mac_X550EM_x &&
6995             hw->mac.type != ixgbe_mac_X550EM_a) {
6996                 return -ENOTSUP;
6997         }
6998
6999         rar_entries = ixgbe_get_num_rx_addrs(hw);
7000
7001         for (i = 1; i < rar_entries; i++) {
7002                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7003                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7004                 if ((rar_high & IXGBE_RAH_AV) &&
7005                     (rar_high & IXGBE_RAH_ADTYPE) &&
7006                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7007                      l2_tunnel->tunnel_id)) {
7008                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7009                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7010
7011                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7012
7013                         return ret;
7014                 }
7015         }
7016
7017         return ret;
7018 }
7019
7020 static int
7021 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7022                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7023 {
7024         int ret = 0;
7025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7026         uint32_t i, rar_entries;
7027         uint32_t rar_low, rar_high;
7028
7029         if (hw->mac.type != ixgbe_mac_X550 &&
7030             hw->mac.type != ixgbe_mac_X550EM_x &&
7031             hw->mac.type != ixgbe_mac_X550EM_a) {
7032                 return -ENOTSUP;
7033         }
7034
7035         /* One entry for one tunnel. Try to remove potential existing entry. */
7036         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7037
7038         rar_entries = ixgbe_get_num_rx_addrs(hw);
7039
7040         for (i = 1; i < rar_entries; i++) {
7041                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7042                 if (rar_high & IXGBE_RAH_AV) {
7043                         continue;
7044                 } else {
7045                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7046                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7047                         rar_low = l2_tunnel->tunnel_id;
7048
7049                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7050                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7051
7052                         return ret;
7053                 }
7054         }
7055
7056         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7057                      " Please remove a rule before adding a new one.");
7058         return -EINVAL;
7059 }
7060
7061 static inline struct ixgbe_l2_tn_filter *
7062 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7063                           struct ixgbe_l2_tn_key *key)
7064 {
7065         int ret;
7066
7067         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7068         if (ret < 0)
7069                 return NULL;
7070
7071         return l2_tn_info->hash_map[ret];
7072 }
7073
7074 static inline int
7075 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7076                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7077 {
7078         int ret;
7079
7080         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7081                                &l2_tn_filter->key);
7082
7083         if (ret < 0) {
7084                 PMD_DRV_LOG(ERR,
7085                             "Failed to insert L2 tunnel filter"
7086                             " to hash table %d!",
7087                             ret);
7088                 return ret;
7089         }
7090
7091         l2_tn_info->hash_map[ret] = l2_tn_filter;
7092
7093         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7094
7095         return 0;
7096 }
7097
7098 static inline int
7099 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7100                           struct ixgbe_l2_tn_key *key)
7101 {
7102         int ret;
7103         struct ixgbe_l2_tn_filter *l2_tn_filter;
7104
7105         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7106
7107         if (ret < 0) {
7108                 PMD_DRV_LOG(ERR,
7109                             "No such L2 tunnel filter to delete %d!",
7110                             ret);
7111                 return ret;
7112         }
7113
7114         l2_tn_filter = l2_tn_info->hash_map[ret];
7115         l2_tn_info->hash_map[ret] = NULL;
7116
7117         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7118         rte_free(l2_tn_filter);
7119
7120         return 0;
7121 }
7122
7123 /* Add l2 tunnel filter */
7124 int
7125 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7126                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7127                                bool restore)
7128 {
7129         int ret;
7130         struct ixgbe_l2_tn_info *l2_tn_info =
7131                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7132         struct ixgbe_l2_tn_key key;
7133         struct ixgbe_l2_tn_filter *node;
7134
7135         if (!restore) {
7136                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7137                 key.tn_id = l2_tunnel->tunnel_id;
7138
7139                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7140
7141                 if (node) {
7142                         PMD_DRV_LOG(ERR,
7143                                     "The L2 tunnel filter already exists!");
7144                         return -EINVAL;
7145                 }
7146
7147                 node = rte_zmalloc("ixgbe_l2_tn",
7148                                    sizeof(struct ixgbe_l2_tn_filter),
7149                                    0);
7150                 if (!node)
7151                         return -ENOMEM;
7152
7153                 (void)rte_memcpy(&node->key,
7154                                  &key,
7155                                  sizeof(struct ixgbe_l2_tn_key));
7156                 node->pool = l2_tunnel->pool;
7157                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7158                 if (ret < 0) {
7159                         rte_free(node);
7160                         return ret;
7161                 }
7162         }
7163
7164         switch (l2_tunnel->l2_tunnel_type) {
7165         case RTE_L2_TUNNEL_TYPE_E_TAG:
7166                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7167                 break;
7168         default:
7169                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7170                 ret = -EINVAL;
7171                 break;
7172         }
7173
7174         if ((!restore) && (ret < 0))
7175                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7176
7177         return ret;
7178 }
7179
7180 /* Delete l2 tunnel filter */
7181 int
7182 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7183                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7184 {
7185         int ret;
7186         struct ixgbe_l2_tn_info *l2_tn_info =
7187                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7188         struct ixgbe_l2_tn_key key;
7189
7190         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7191         key.tn_id = l2_tunnel->tunnel_id;
7192         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7193         if (ret < 0)
7194                 return ret;
7195
7196         switch (l2_tunnel->l2_tunnel_type) {
7197         case RTE_L2_TUNNEL_TYPE_E_TAG:
7198                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7199                 break;
7200         default:
7201                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7202                 ret = -EINVAL;
7203                 break;
7204         }
7205
7206         return ret;
7207 }
7208
7209 /**
7210  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7211  * @dev: pointer to rte_eth_dev structure
7212  * @filter_op:operation will be taken.
7213  * @arg: a pointer to specific structure corresponding to the filter_op
7214  */
7215 static int
7216 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7217                                   enum rte_filter_op filter_op,
7218                                   void *arg)
7219 {
7220         int ret;
7221
7222         if (filter_op == RTE_ETH_FILTER_NOP)
7223                 return 0;
7224
7225         if (arg == NULL) {
7226                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7227                             filter_op);
7228                 return -EINVAL;
7229         }
7230
7231         switch (filter_op) {
7232         case RTE_ETH_FILTER_ADD:
7233                 ret = ixgbe_dev_l2_tunnel_filter_add
7234                         (dev,
7235                          (struct rte_eth_l2_tunnel_conf *)arg,
7236                          FALSE);
7237                 break;
7238         case RTE_ETH_FILTER_DELETE:
7239                 ret = ixgbe_dev_l2_tunnel_filter_del
7240                         (dev,
7241                          (struct rte_eth_l2_tunnel_conf *)arg);
7242                 break;
7243         default:
7244                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7245                 ret = -EINVAL;
7246                 break;
7247         }
7248         return ret;
7249 }
7250
7251 static int
7252 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7253 {
7254         int ret = 0;
7255         uint32_t ctrl;
7256         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7257
7258         if (hw->mac.type != ixgbe_mac_X550 &&
7259             hw->mac.type != ixgbe_mac_X550EM_x &&
7260             hw->mac.type != ixgbe_mac_X550EM_a) {
7261                 return -ENOTSUP;
7262         }
7263
7264         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7265         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7266         if (en)
7267                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7268         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7269
7270         return ret;
7271 }
7272
7273 /* Enable l2 tunnel forwarding */
7274 static int
7275 ixgbe_dev_l2_tunnel_forwarding_enable
7276         (struct rte_eth_dev *dev,
7277          enum rte_eth_tunnel_type l2_tunnel_type)
7278 {
7279         struct ixgbe_l2_tn_info *l2_tn_info =
7280                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7281         int ret = 0;
7282
7283         switch (l2_tunnel_type) {
7284         case RTE_L2_TUNNEL_TYPE_E_TAG:
7285                 l2_tn_info->e_tag_fwd_en = TRUE;
7286                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7287                 break;
7288         default:
7289                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7290                 ret = -EINVAL;
7291                 break;
7292         }
7293
7294         return ret;
7295 }
7296
7297 /* Disable l2 tunnel forwarding */
7298 static int
7299 ixgbe_dev_l2_tunnel_forwarding_disable
7300         (struct rte_eth_dev *dev,
7301          enum rte_eth_tunnel_type l2_tunnel_type)
7302 {
7303         struct ixgbe_l2_tn_info *l2_tn_info =
7304                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7305         int ret = 0;
7306
7307         switch (l2_tunnel_type) {
7308         case RTE_L2_TUNNEL_TYPE_E_TAG:
7309                 l2_tn_info->e_tag_fwd_en = FALSE;
7310                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7311                 break;
7312         default:
7313                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7314                 ret = -EINVAL;
7315                 break;
7316         }
7317
7318         return ret;
7319 }
7320
7321 static int
7322 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7323                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7324                              bool en)
7325 {
7326         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7327         int ret = 0;
7328         uint32_t vmtir, vmvir;
7329         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7330
7331         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7332                 PMD_DRV_LOG(ERR,
7333                             "VF id %u should be less than %u",
7334                             l2_tunnel->vf_id,
7335                             pci_dev->max_vfs);
7336                 return -EINVAL;
7337         }
7338
7339         if (hw->mac.type != ixgbe_mac_X550 &&
7340             hw->mac.type != ixgbe_mac_X550EM_x &&
7341             hw->mac.type != ixgbe_mac_X550EM_a) {
7342                 return -ENOTSUP;
7343         }
7344
7345         if (en)
7346                 vmtir = l2_tunnel->tunnel_id;
7347         else
7348                 vmtir = 0;
7349
7350         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7351
7352         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7353         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7354         if (en)
7355                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7356         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7357
7358         return ret;
7359 }
7360
7361 /* Enable l2 tunnel tag insertion */
7362 static int
7363 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7364                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7365 {
7366         int ret = 0;
7367
7368         switch (l2_tunnel->l2_tunnel_type) {
7369         case RTE_L2_TUNNEL_TYPE_E_TAG:
7370                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7371                 break;
7372         default:
7373                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7374                 ret = -EINVAL;
7375                 break;
7376         }
7377
7378         return ret;
7379 }
7380
7381 /* Disable l2 tunnel tag insertion */
7382 static int
7383 ixgbe_dev_l2_tunnel_insertion_disable
7384         (struct rte_eth_dev *dev,
7385          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7386 {
7387         int ret = 0;
7388
7389         switch (l2_tunnel->l2_tunnel_type) {
7390         case RTE_L2_TUNNEL_TYPE_E_TAG:
7391                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7392                 break;
7393         default:
7394                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7395                 ret = -EINVAL;
7396                 break;
7397         }
7398
7399         return ret;
7400 }
7401
7402 static int
7403 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7404                              bool en)
7405 {
7406         int ret = 0;
7407         uint32_t qde;
7408         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7409
7410         if (hw->mac.type != ixgbe_mac_X550 &&
7411             hw->mac.type != ixgbe_mac_X550EM_x &&
7412             hw->mac.type != ixgbe_mac_X550EM_a) {
7413                 return -ENOTSUP;
7414         }
7415
7416         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7417         if (en)
7418                 qde |= IXGBE_QDE_STRIP_TAG;
7419         else
7420                 qde &= ~IXGBE_QDE_STRIP_TAG;
7421         qde &= ~IXGBE_QDE_READ;
7422         qde |= IXGBE_QDE_WRITE;
7423         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7424
7425         return ret;
7426 }
7427
7428 /* Enable l2 tunnel tag stripping */
7429 static int
7430 ixgbe_dev_l2_tunnel_stripping_enable
7431         (struct rte_eth_dev *dev,
7432          enum rte_eth_tunnel_type l2_tunnel_type)
7433 {
7434         int ret = 0;
7435
7436         switch (l2_tunnel_type) {
7437         case RTE_L2_TUNNEL_TYPE_E_TAG:
7438                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7439                 break;
7440         default:
7441                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7442                 ret = -EINVAL;
7443                 break;
7444         }
7445
7446         return ret;
7447 }
7448
7449 /* Disable l2 tunnel tag stripping */
7450 static int
7451 ixgbe_dev_l2_tunnel_stripping_disable
7452         (struct rte_eth_dev *dev,
7453          enum rte_eth_tunnel_type l2_tunnel_type)
7454 {
7455         int ret = 0;
7456
7457         switch (l2_tunnel_type) {
7458         case RTE_L2_TUNNEL_TYPE_E_TAG:
7459                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7460                 break;
7461         default:
7462                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7463                 ret = -EINVAL;
7464                 break;
7465         }
7466
7467         return ret;
7468 }
7469
7470 /* Enable/disable l2 tunnel offload functions */
7471 static int
7472 ixgbe_dev_l2_tunnel_offload_set
7473         (struct rte_eth_dev *dev,
7474          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7475          uint32_t mask,
7476          uint8_t en)
7477 {
7478         int ret = 0;
7479
7480         if (l2_tunnel == NULL)
7481                 return -EINVAL;
7482
7483         ret = -EINVAL;
7484         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7485                 if (en)
7486                         ret = ixgbe_dev_l2_tunnel_enable(
7487                                 dev,
7488                                 l2_tunnel->l2_tunnel_type);
7489                 else
7490                         ret = ixgbe_dev_l2_tunnel_disable(
7491                                 dev,
7492                                 l2_tunnel->l2_tunnel_type);
7493         }
7494
7495         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7496                 if (en)
7497                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7498                                 dev,
7499                                 l2_tunnel);
7500                 else
7501                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7502                                 dev,
7503                                 l2_tunnel);
7504         }
7505
7506         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7507                 if (en)
7508                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7509                                 dev,
7510                                 l2_tunnel->l2_tunnel_type);
7511                 else
7512                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7513                                 dev,
7514                                 l2_tunnel->l2_tunnel_type);
7515         }
7516
7517         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7518                 if (en)
7519                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7520                                 dev,
7521                                 l2_tunnel->l2_tunnel_type);
7522                 else
7523                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7524                                 dev,
7525                                 l2_tunnel->l2_tunnel_type);
7526         }
7527
7528         return ret;
7529 }
7530
7531 static int
7532 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7533                         uint16_t port)
7534 {
7535         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7536         IXGBE_WRITE_FLUSH(hw);
7537
7538         return 0;
7539 }
7540
7541 /* There's only one register for VxLAN UDP port.
7542  * So, we cannot add several ports. Will update it.
7543  */
7544 static int
7545 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7546                      uint16_t port)
7547 {
7548         if (port == 0) {
7549                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7550                 return -EINVAL;
7551         }
7552
7553         return ixgbe_update_vxlan_port(hw, port);
7554 }
7555
7556 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7557  * UDP port, it must have a value.
7558  * So, will reset it to the original value 0.
7559  */
7560 static int
7561 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7562                      uint16_t port)
7563 {
7564         uint16_t cur_port;
7565
7566         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7567
7568         if (cur_port != port) {
7569                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7570                 return -EINVAL;
7571         }
7572
7573         return ixgbe_update_vxlan_port(hw, 0);
7574 }
7575
7576 /* Add UDP tunneling port */
7577 static int
7578 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7579                               struct rte_eth_udp_tunnel *udp_tunnel)
7580 {
7581         int ret = 0;
7582         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7583
7584         if (hw->mac.type != ixgbe_mac_X550 &&
7585             hw->mac.type != ixgbe_mac_X550EM_x &&
7586             hw->mac.type != ixgbe_mac_X550EM_a) {
7587                 return -ENOTSUP;
7588         }
7589
7590         if (udp_tunnel == NULL)
7591                 return -EINVAL;
7592
7593         switch (udp_tunnel->prot_type) {
7594         case RTE_TUNNEL_TYPE_VXLAN:
7595                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7596                 break;
7597
7598         case RTE_TUNNEL_TYPE_GENEVE:
7599         case RTE_TUNNEL_TYPE_TEREDO:
7600                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7601                 ret = -EINVAL;
7602                 break;
7603
7604         default:
7605                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7606                 ret = -EINVAL;
7607                 break;
7608         }
7609
7610         return ret;
7611 }
7612
7613 /* Remove UDP tunneling port */
7614 static int
7615 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7616                               struct rte_eth_udp_tunnel *udp_tunnel)
7617 {
7618         int ret = 0;
7619         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7620
7621         if (hw->mac.type != ixgbe_mac_X550 &&
7622             hw->mac.type != ixgbe_mac_X550EM_x &&
7623             hw->mac.type != ixgbe_mac_X550EM_a) {
7624                 return -ENOTSUP;
7625         }
7626
7627         if (udp_tunnel == NULL)
7628                 return -EINVAL;
7629
7630         switch (udp_tunnel->prot_type) {
7631         case RTE_TUNNEL_TYPE_VXLAN:
7632                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7633                 break;
7634         case RTE_TUNNEL_TYPE_GENEVE:
7635         case RTE_TUNNEL_TYPE_TEREDO:
7636                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7637                 ret = -EINVAL;
7638                 break;
7639         default:
7640                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7641                 ret = -EINVAL;
7642                 break;
7643         }
7644
7645         return ret;
7646 }
7647
7648 static void
7649 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7650 {
7651         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7652
7653         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7654 }
7655
7656 static void
7657 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7658 {
7659         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7660
7661         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7662 }
7663
7664 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7665 {
7666         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7667         u32 in_msg = 0;
7668
7669         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7670                 return;
7671
7672         /* PF reset VF event */
7673         if (in_msg == IXGBE_PF_CONTROL_MSG)
7674                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7675 }
7676
7677 static int
7678 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7679 {
7680         uint32_t eicr;
7681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7682         struct ixgbe_interrupt *intr =
7683                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7684         ixgbevf_intr_disable(hw);
7685
7686         /* read-on-clear nic registers here */
7687         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7688         intr->flags = 0;
7689
7690         /* only one misc vector supported - mailbox */
7691         eicr &= IXGBE_VTEICR_MASK;
7692         if (eicr == IXGBE_MISC_VEC_ID)
7693                 intr->flags |= IXGBE_FLAG_MAILBOX;
7694
7695         return 0;
7696 }
7697
7698 static int
7699 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7700 {
7701         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7702         struct ixgbe_interrupt *intr =
7703                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7704
7705         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7706                 ixgbevf_mbx_process(dev);
7707                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7708         }
7709
7710         ixgbevf_intr_enable(hw);
7711
7712         return 0;
7713 }
7714
7715 static void
7716 ixgbevf_dev_interrupt_handler(void *param)
7717 {
7718         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7719
7720         ixgbevf_dev_interrupt_get_status(dev);
7721         ixgbevf_dev_interrupt_action(dev);
7722 }
7723
7724 /**
7725  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7726  *  @hw: pointer to hardware structure
7727  *
7728  *  Stops the transmit data path and waits for the HW to internally empty
7729  *  the Tx security block
7730  **/
7731 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7732 {
7733 #define IXGBE_MAX_SECTX_POLL 40
7734
7735         int i;
7736         int sectxreg;
7737
7738         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7739         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7740         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7741         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7742                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7743                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7744                         break;
7745                 /* Use interrupt-safe sleep just in case */
7746                 usec_delay(1000);
7747         }
7748
7749         /* For informational purposes only */
7750         if (i >= IXGBE_MAX_SECTX_POLL)
7751                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7752                          "path fully disabled.  Continuing with init.");
7753
7754         return IXGBE_SUCCESS;
7755 }
7756
7757 /**
7758  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7759  *  @hw: pointer to hardware structure
7760  *
7761  *  Enables the transmit data path.
7762  **/
7763 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7764 {
7765         uint32_t sectxreg;
7766
7767         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7768         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7769         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7770         IXGBE_WRITE_FLUSH(hw);
7771
7772         return IXGBE_SUCCESS;
7773 }
7774
7775 /* restore n-tuple filter */
7776 static inline void
7777 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7778 {
7779         struct ixgbe_filter_info *filter_info =
7780                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7781         struct ixgbe_5tuple_filter *node;
7782
7783         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
7784                 ixgbe_inject_5tuple_filter(dev, node);
7785         }
7786 }
7787
7788 /* restore ethernet type filter */
7789 static inline void
7790 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
7791 {
7792         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7793         struct ixgbe_filter_info *filter_info =
7794                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7795         int i;
7796
7797         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
7798                 if (filter_info->ethertype_mask & (1 << i)) {
7799                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
7800                                         filter_info->ethertype_filters[i].etqf);
7801                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
7802                                         filter_info->ethertype_filters[i].etqs);
7803                         IXGBE_WRITE_FLUSH(hw);
7804                 }
7805         }
7806 }
7807
7808 /* restore SYN filter */
7809 static inline void
7810 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
7811 {
7812         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7813         struct ixgbe_filter_info *filter_info =
7814                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7815         uint32_t synqf;
7816
7817         synqf = filter_info->syn_info;
7818
7819         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
7820                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
7821                 IXGBE_WRITE_FLUSH(hw);
7822         }
7823 }
7824
7825 /* restore L2 tunnel filter */
7826 static inline void
7827 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
7828 {
7829         struct ixgbe_l2_tn_info *l2_tn_info =
7830                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7831         struct ixgbe_l2_tn_filter *node;
7832         struct rte_eth_l2_tunnel_conf l2_tn_conf;
7833
7834         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
7835                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
7836                 l2_tn_conf.tunnel_id      = node->key.tn_id;
7837                 l2_tn_conf.pool           = node->pool;
7838                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
7839         }
7840 }
7841
7842 static int
7843 ixgbe_filter_restore(struct rte_eth_dev *dev)
7844 {
7845         ixgbe_ntuple_filter_restore(dev);
7846         ixgbe_ethertype_filter_restore(dev);
7847         ixgbe_syn_filter_restore(dev);
7848         ixgbe_fdir_filter_restore(dev);
7849         ixgbe_l2_tn_filter_restore(dev);
7850
7851         return 0;
7852 }
7853
7854 static void
7855 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
7856 {
7857         struct ixgbe_l2_tn_info *l2_tn_info =
7858                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7860
7861         if (l2_tn_info->e_tag_en)
7862                 (void)ixgbe_e_tag_enable(hw);
7863
7864         if (l2_tn_info->e_tag_fwd_en)
7865                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
7866
7867         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
7868 }
7869
7870 /* remove all the n-tuple filters */
7871 void
7872 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
7873 {
7874         struct ixgbe_filter_info *filter_info =
7875                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7876         struct ixgbe_5tuple_filter *p_5tuple;
7877
7878         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
7879                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
7880 }
7881
7882 /* remove all the ether type filters */
7883 void
7884 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
7885 {
7886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7887         struct ixgbe_filter_info *filter_info =
7888                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7889         int i;
7890
7891         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
7892                 if (filter_info->ethertype_mask & (1 << i) &&
7893                     !filter_info->ethertype_filters[i].conf) {
7894                         (void)ixgbe_ethertype_filter_remove(filter_info,
7895                                                             (uint8_t)i);
7896                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
7897                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
7898                         IXGBE_WRITE_FLUSH(hw);
7899                 }
7900         }
7901 }
7902
7903 /* remove the SYN filter */
7904 void
7905 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
7906 {
7907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7908         struct ixgbe_filter_info *filter_info =
7909                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7910
7911         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
7912                 filter_info->syn_info = 0;
7913
7914                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
7915                 IXGBE_WRITE_FLUSH(hw);
7916         }
7917 }
7918
7919 /* remove all the L2 tunnel filters */
7920 int
7921 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
7922 {
7923         struct ixgbe_l2_tn_info *l2_tn_info =
7924                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7925         struct ixgbe_l2_tn_filter *l2_tn_filter;
7926         struct rte_eth_l2_tunnel_conf l2_tn_conf;
7927         int ret = 0;
7928
7929         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
7930                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
7931                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
7932                 l2_tn_conf.pool           = l2_tn_filter->pool;
7933                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
7934                 if (ret < 0)
7935                         return ret;
7936         }
7937
7938         return 0;
7939 }
7940
7941 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
7942 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7943 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
7944 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
7945 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
7946 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");