drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 #include "rte_pmd_ixgbe.h"
  77
  78 /*
  79  * High threshold controlling when to start sending XOFF frames. Must be at
  80  * least 8 bytes less than receive packet buffer size. This value is in units
  81  * of 1024 bytes.
  82  */
  83 #define IXGBE_FC_HI    0x80
  84
  85 /*
  86  * Low threshold controlling when to start sending XON frames. This value is
  87  * in units of 1024 bytes.
  88  */
  89 #define IXGBE_FC_LO    0x40
  90
  91 /* Default minimum inter-interrupt interval for EITR configuration */
  92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  93
  94 /* Timer value included in XOFF frames. */
  95 #define IXGBE_FC_PAUSE 0x680
  96
  97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  98 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  99 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 100
 101 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 102 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 103 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 104
 105 /*
 106  *  Default values for RX/TX configuration
 107  */
 108 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 109 #define IXGBE_DEFAULT_RX_PTHRESH      8
 110 #define IXGBE_DEFAULT_RX_HTHRESH      8
 111 #define IXGBE_DEFAULT_RX_WTHRESH      0
 112
 113 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 114 #define IXGBE_DEFAULT_TX_PTHRESH      32
 115 #define IXGBE_DEFAULT_TX_HTHRESH      0
 116 #define IXGBE_DEFAULT_TX_WTHRESH      0
 117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 118
 119 /* Bit shift and mask */
 120 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 121 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 122 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 123 #define IXGBE_8_BIT_MASK   UINT8_MAX
 124
 125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 126
 127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 128
 129 #define IXGBE_HKEY_MAX_INDEX 10
 130
 131 /* Additional timesync values. */
 132 #define NSEC_PER_SEC             1000000000L
 133 #define IXGBE_INCVAL_10GB        0x66666666
 134 #define IXGBE_INCVAL_1GB         0x40000000
 135 #define IXGBE_INCVAL_100         0x50000000
 136 #define IXGBE_INCVAL_SHIFT_10GB  28
 137 #define IXGBE_INCVAL_SHIFT_1GB   24
 138 #define IXGBE_INCVAL_SHIFT_100   21
 139 #define IXGBE_INCVAL_SHIFT_82599 7
 140 #define IXGBE_INCPER_SHIFT_82599 24
 141
 142 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 143
 144 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 146 #define DEFAULT_ETAG_ETYPE                     0x893f
 147 #define IXGBE_ETAG_ETYPE                       0x00005084
 148 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 149 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 150 #define IXGBE_RAH_ADTYPE                       0x40000000
 151 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 152 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 155 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 156 #define IXGBE_VTEICR_MASK                      0x07
 157
 158 enum ixgbevf_xcast_modes {
 159         IXGBEVF_XCAST_MODE_NONE = 0,
 160         IXGBEVF_XCAST_MODE_MULTI,
 161         IXGBEVF_XCAST_MODE_ALLMULTI,
 162 };
 163
 164 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 165 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 166
 167 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 168 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 169 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 170 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 171 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 172 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 173 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 174 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 175 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 177 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 178 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 179 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 180 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 182 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 183 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 184 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 185                                 int wait_to_complete);
 186 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 187                                 struct rte_eth_stats *stats);
 188 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_xstat *xstats, unsigned n);
 190 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 191                                   struct rte_eth_xstat *xstats, unsigned n);
 192 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 193 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 195         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 196 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 198 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 199                                              uint16_t queue_id,
 200                                              uint8_t stat_idx,
 201                                              uint8_t is_rx);
 202 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 203                                  size_t fw_size);
 204 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_dev_info *dev_info);
 206 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 207 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 208                                  struct rte_eth_dev_info *dev_info);
 209 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 210
 211 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 212                 uint16_t vlan_id, int on);
 213 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 214                                enum rte_vlan_type vlan_type,
 215                                uint16_t tpid_id);
 216 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 217                 uint16_t queue, bool on);
 218 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 219                 int on);
 220 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 221 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 222 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 223 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 224 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 225
 226 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 228 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 229                                struct rte_eth_fc_conf *fc_conf);
 230 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 233                 struct rte_eth_pfc_conf *pfc_conf);
 234 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 235                         struct rte_eth_rss_reta_entry64 *reta_conf,
 236                         uint16_t reta_size);
 237 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 238                         struct rte_eth_rss_reta_entry64 *reta_conf,
 239                         uint16_t reta_size);
 240 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 241 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 242 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 246                                       struct rte_intr_handle *handle);
 247 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 248                 void *param);
 249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 250 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 251                 uint32_t index, uint32_t pool);
 252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 254                                            struct ether_addr *mac_addr);
 255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 256 static int is_ixgbe_pmd(const char *driver_name);
 257
 258 /* For Virtual Function support */
 259 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 260 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 261 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 262 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 265 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 266 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 267 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 268                 struct rte_eth_stats *stats);
 269 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 270 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 271                 uint16_t vlan_id, int on);
 272 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 273                 uint16_t queue, int on);
 274 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 275 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 276 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                             uint16_t queue_id);
 278 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                              uint16_t queue_id);
 280 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                  uint8_t queue, uint8_t msix_vector);
 282 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 283 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 284 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 285
 286 /* For Eth VMDQ APIs support */
 287 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 288                 ether_addr * mac_addr, uint8_t on);
 289 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 291                 struct rte_eth_mirror_conf *mirror_conf,
 292                 uint8_t rule_id, uint8_t on);
 293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 294                 uint8_t rule_id);
 295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 296                                           uint16_t queue_id);
 297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 298                                            uint16_t queue_id);
 299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 300                                uint8_t queue, uint8_t msix_vector);
 301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 302
 303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 304                 uint16_t queue_idx, uint16_t tx_rate);
 305
 306 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 307                                  struct ether_addr *mac_addr,
 308                                  uint32_t index, uint32_t pool);
 309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 311                                              struct ether_addr *mac_addr);
 312 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 313                         struct rte_eth_syn_filter *filter,
 314                         bool add);
 315 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 316                         struct rte_eth_syn_filter *filter);
 317 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 318                         enum rte_filter_op filter_op,
 319                         void *arg);
 320 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 323                         struct ixgbe_5tuple_filter *filter);
 324 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ntuple_filter *filter,
 326                         bool add);
 327 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 328                                 enum rte_filter_op filter_op,
 329                                 void *arg);
 330 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 331                         struct rte_eth_ntuple_filter *filter);
 332 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 333                         struct rte_eth_ethertype_filter *filter,
 334                         bool add);
 335 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 336                                 enum rte_filter_op filter_op,
 337                                 void *arg);
 338 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 339                         struct rte_eth_ethertype_filter *filter);
 340 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 341                      enum rte_filter_type filter_type,
 342                      enum rte_filter_op filter_op,
 343                      void *arg);
 344 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 345
 346 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 347                                       struct ether_addr *mc_addr_set,
 348                                       uint32_t nb_mc_addr);
 349 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 350                                    struct rte_eth_dcb_info *dcb_info);
 351
 352 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 353 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 354                             struct rte_dev_reg_info *regs);
 355 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 356 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 357                                 struct rte_dev_eeprom_info *eeprom);
 358 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 359                                 struct rte_dev_eeprom_info *eeprom);
 360
 361 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 362 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 363                                 struct rte_dev_reg_info *regs);
 364
 365 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 366 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 367 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 368                                             struct timespec *timestamp,
 369                                             uint32_t flags);
 370 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 371                                             struct timespec *timestamp);
 372 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 373 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 374                                    struct timespec *timestamp);
 375 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 376                                    const struct timespec *timestamp);
 377 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 378                                           void *param);
 379
 380 static int ixgbe_dev_l2_tunnel_eth_type_conf
 381         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 382 static int ixgbe_dev_l2_tunnel_offload_set
 383         (struct rte_eth_dev *dev,
 384          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 385          uint32_t mask,
 386          uint8_t en);
 387 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 388                                              enum rte_filter_op filter_op,
 389                                              void *arg);
 390
 391 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 392                                          struct rte_eth_udp_tunnel *udp_tunnel);
 393 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 394                                          struct rte_eth_udp_tunnel *udp_tunnel);
 395 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 396 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 397
 398 /*
 399  * Define VF Stats MACRO for Non "cleared on read" register
 400  */
 401 #define UPDATE_VF_STAT(reg, last, cur)                          \
 402 {                                                               \
 403         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 404         cur += (latest - last) & UINT_MAX;                      \
 405         last = latest;                                          \
 406 }
 407
 408 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 409 {                                                                \
 410         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 411         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 412         u64 latest = ((new_msb << 32) | new_lsb);                \
 413         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 414         last = latest;                                           \
 415 }
 416
 417 #define IXGBE_SET_HWSTRIP(h, q) do {\
 418                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 419                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 420                 (h)->bitmap[idx] |= 1 << bit;\
 421         } while (0)
 422
 423 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 424                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 425                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 426                 (h)->bitmap[idx] &= ~(1 << bit);\
 427         } while (0)
 428
 429 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 430                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 431                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 432                 (r) = (h)->bitmap[idx] >> bit & 1;\
 433         } while (0)
 434
 435 /*
 436  * The set of PCI devices this driver supports
 437  */
 438 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 492 #ifdef RTE_NIC_BYPASS
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 494 #endif
 495         { .vendor_id = 0, /* sentinel */ },
 496 };
 497
 498 /*
 499  * The set of PCI devices this driver supports (for 82599 VF)
 500  */
 501 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 508         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 509         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 510         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 511         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 512         { .vendor_id = 0, /* sentinel */ },
 513 };
 514
 515 static const struct rte_eth_desc_lim rx_desc_lim = {
 516         .nb_max = IXGBE_MAX_RING_DESC,
 517         .nb_min = IXGBE_MIN_RING_DESC,
 518         .nb_align = IXGBE_RXD_ALIGN,
 519 };
 520
 521 static const struct rte_eth_desc_lim tx_desc_lim = {
 522         .nb_max = IXGBE_MAX_RING_DESC,
 523         .nb_min = IXGBE_MIN_RING_DESC,
 524         .nb_align = IXGBE_TXD_ALIGN,
 525         .nb_seg_max = IXGBE_TX_MAX_SEG,
 526         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 527 };
 528
 529 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 530         .dev_configure        = ixgbe_dev_configure,
 531         .dev_start            = ixgbe_dev_start,
 532         .dev_stop             = ixgbe_dev_stop,
 533         .dev_set_link_up    = ixgbe_dev_set_link_up,
 534         .dev_set_link_down  = ixgbe_dev_set_link_down,
 535         .dev_close            = ixgbe_dev_close,
 536         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 537         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 538         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 539         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 540         .link_update          = ixgbe_dev_link_update,
 541         .stats_get            = ixgbe_dev_stats_get,
 542         .xstats_get           = ixgbe_dev_xstats_get,
 543         .stats_reset          = ixgbe_dev_stats_reset,
 544         .xstats_reset         = ixgbe_dev_xstats_reset,
 545         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 546         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 547         .fw_version_get       = ixgbe_fw_version_get,
 548         .dev_infos_get        = ixgbe_dev_info_get,
 549         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 550         .mtu_set              = ixgbe_dev_mtu_set,
 551         .vlan_filter_set      = ixgbe_vlan_filter_set,
 552         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 553         .vlan_offload_set     = ixgbe_vlan_offload_set,
 554         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 555         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 556         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 557         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 558         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 559         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 560         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 561         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 562         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 563         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 564         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 565         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 566         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 567         .dev_led_on           = ixgbe_dev_led_on,
 568         .dev_led_off          = ixgbe_dev_led_off,
 569         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 570         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 571         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 572         .mac_addr_add         = ixgbe_add_rar,
 573         .mac_addr_remove      = ixgbe_remove_rar,
 574         .mac_addr_set         = ixgbe_set_default_mac_addr,
 575         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 576         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 577         .mirror_rule_set      = ixgbe_mirror_rule_set,
 578         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 579         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 580         .reta_update          = ixgbe_dev_rss_reta_update,
 581         .reta_query           = ixgbe_dev_rss_reta_query,
 582 #ifdef RTE_NIC_BYPASS
 583         .bypass_init          = ixgbe_bypass_init,
 584         .bypass_state_set     = ixgbe_bypass_state_store,
 585         .bypass_state_show    = ixgbe_bypass_state_show,
 586         .bypass_event_set     = ixgbe_bypass_event_store,
 587         .bypass_event_show    = ixgbe_bypass_event_show,
 588         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 589         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 590         .bypass_ver_show      = ixgbe_bypass_ver_show,
 591         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 592 #endif /* RTE_NIC_BYPASS */
 593         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 594         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 595         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 596         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 597         .rxq_info_get         = ixgbe_rxq_info_get,
 598         .txq_info_get         = ixgbe_txq_info_get,
 599         .timesync_enable      = ixgbe_timesync_enable,
 600         .timesync_disable     = ixgbe_timesync_disable,
 601         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 602         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 603         .get_reg              = ixgbe_get_regs,
 604         .get_eeprom_length    = ixgbe_get_eeprom_length,
 605         .get_eeprom           = ixgbe_get_eeprom,
 606         .set_eeprom           = ixgbe_set_eeprom,
 607         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 608         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 609         .timesync_read_time   = ixgbe_timesync_read_time,
 610         .timesync_write_time  = ixgbe_timesync_write_time,
 611         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 612         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 613         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 614         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 615 };
 616
 617 /*
 618  * dev_ops for virtual function, bare necessities for basic vf
 619  * operation have been implemented
 620  */
 621 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 622         .dev_configure        = ixgbevf_dev_configure,
 623         .dev_start            = ixgbevf_dev_start,
 624         .dev_stop             = ixgbevf_dev_stop,
 625         .link_update          = ixgbe_dev_link_update,
 626         .stats_get            = ixgbevf_dev_stats_get,
 627         .xstats_get           = ixgbevf_dev_xstats_get,
 628         .stats_reset          = ixgbevf_dev_stats_reset,
 629         .xstats_reset         = ixgbevf_dev_stats_reset,
 630         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 631         .dev_close            = ixgbevf_dev_close,
 632         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 633         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 634         .dev_infos_get        = ixgbevf_dev_info_get,
 635         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 636         .mtu_set              = ixgbevf_dev_set_mtu,
 637         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 638         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 639         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 640         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 641         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 642         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 643         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 644         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 645         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 646         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 647         .mac_addr_add         = ixgbevf_add_mac_addr,
 648         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 649         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 650         .rxq_info_get         = ixgbe_rxq_info_get,
 651         .txq_info_get         = ixgbe_txq_info_get,
 652         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 653         .get_reg              = ixgbevf_get_regs,
 654         .reta_update          = ixgbe_dev_rss_reta_update,
 655         .reta_query           = ixgbe_dev_rss_reta_query,
 656         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 657         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 658 };
 659
 660 /* store statistics names and its offset in stats structure */
 661 struct rte_ixgbe_xstats_name_off {
 662         char name[RTE_ETH_XSTATS_NAME_SIZE];
 663         unsigned offset;
 664 };
 665
 666 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 667         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 668         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 669         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 670         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 671         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 672         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 673         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 674         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 675         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 676         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 677         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 678         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 679         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 680         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 681         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 682                 prc1023)},
 683         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 684                 prc1522)},
 685         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 686         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 687         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 688         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 689         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 690         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 691         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 692         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 693         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 694         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 695         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 696         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 697         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 698         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 699         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 700         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 701         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 702                 ptc1023)},
 703         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 704                 ptc1522)},
 705         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 706         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 707         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 708         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 709
 710         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirustat_add)},
 712         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirustat_remove)},
 714         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 715                 fdirfstat_fadd)},
 716         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 717                 fdirfstat_fremove)},
 718         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 719                 fdirmatch)},
 720         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 721                 fdirmiss)},
 722
 723         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 724         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 725         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 726                 fclast)},
 727         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 728         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 729         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 730         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 731         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 732                 fcoe_noddp)},
 733         {"rx_fcoe_no_direct_data_placement_ext_buff",
 734                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 735
 736         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxontxc)},
 738         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxonrxc)},
 740         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxofftxc)},
 742         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 743                 lxoffrxc)},
 744         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 745 };
 746
 747 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 748                            sizeof(rte_ixgbe_stats_strings[0]))
 749
 750 /* MACsec statistics */
 751 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 752         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 753                 out_pkts_untagged)},
 754         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 755                 out_pkts_encrypted)},
 756         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 757                 out_pkts_protected)},
 758         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 759                 out_octets_encrypted)},
 760         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 761                 out_octets_protected)},
 762         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_untagged)},
 764         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_badtag)},
 766         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_nosci)},
 768         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_unknownsci)},
 770         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 771                 in_octets_decrypted)},
 772         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 773                 in_octets_validated)},
 774         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_unchecked)},
 776         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_delayed)},
 778         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_late)},
 780         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_ok)},
 782         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 783                 in_pkts_invalid)},
 784         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 785                 in_pkts_notvalid)},
 786         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 787                 in_pkts_unusedsa)},
 788         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 789                 in_pkts_notusingsa)},
 790 };
 791
 792 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 793                            sizeof(rte_ixgbe_macsec_strings[0]))
 794
 795 /* Per-queue statistics */
 796 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 797         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 798         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 799         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 800         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 801 };
 802
 803 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 804                            sizeof(rte_ixgbe_rxq_strings[0]))
 805 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 806
 807 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 808         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 809         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 810         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 811                 pxon2offc)},
 812 };
 813
 814 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 815                            sizeof(rte_ixgbe_txq_strings[0]))
 816 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 817
 818 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 819         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 820 };
 821
 822 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 823                 sizeof(rte_ixgbevf_stats_strings[0]))
 824
 825 /**
 826  * Atomically reads the link status information from global
 827  * structure rte_eth_dev.
 828  *
 829  * @param dev
 830  *   - Pointer to the structure rte_eth_dev to read from.
 831  *   - Pointer to the buffer to be saved with the link status.
 832  *
 833  * @return
 834  *   - On success, zero.
 835  *   - On failure, negative value.
 836  */
 837 static inline int
 838 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 839                                 struct rte_eth_link *link)
 840 {
 841         struct rte_eth_link *dst = link;
 842         struct rte_eth_link *src = &(dev->data->dev_link);
 843
 844         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 845                                         *(uint64_t *)src) == 0)
 846                 return -1;
 847
 848         return 0;
 849 }
 850
 851 /**
 852  * Atomically writes the link status information into global
 853  * structure rte_eth_dev.
 854  *
 855  * @param dev
 856  *   - Pointer to the structure rte_eth_dev to read from.
 857  *   - Pointer to the buffer to be saved with the link status.
 858  *
 859  * @return
 860  *   - On success, zero.
 861  *   - On failure, negative value.
 862  */
 863 static inline int
 864 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 865                                 struct rte_eth_link *link)
 866 {
 867         struct rte_eth_link *dst = &(dev->data->dev_link);
 868         struct rte_eth_link *src = link;
 869
 870         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 871                                         *(uint64_t *)src) == 0)
 872                 return -1;
 873
 874         return 0;
 875 }
 876
 877 /*
 878  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 879  */
 880 static inline int
 881 ixgbe_is_sfp(struct ixgbe_hw *hw)
 882 {
 883         switch (hw->phy.type) {
 884         case ixgbe_phy_sfp_avago:
 885         case ixgbe_phy_sfp_ftl:
 886         case ixgbe_phy_sfp_intel:
 887         case ixgbe_phy_sfp_unknown:
 888         case ixgbe_phy_sfp_passive_tyco:
 889         case ixgbe_phy_sfp_passive_unknown:
 890                 return 1;
 891         default:
 892                 return 0;
 893         }
 894 }
 895
 896 static inline int32_t
 897 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 898 {
 899         uint32_t ctrl_ext;
 900         int32_t status;
 901
 902         status = ixgbe_reset_hw(hw);
 903
 904         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 905         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 906         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 907         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 908         IXGBE_WRITE_FLUSH(hw);
 909
 910         return status;
 911 }
 912
 913 static inline void
 914 ixgbe_enable_intr(struct rte_eth_dev *dev)
 915 {
 916         struct ixgbe_interrupt *intr =
 917                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 918         struct ixgbe_hw *hw =
 919                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 920
 921         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 922         IXGBE_WRITE_FLUSH(hw);
 923 }
 924
 925 /*
 926  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 927  */
 928 static void
 929 ixgbe_disable_intr(struct ixgbe_hw *hw)
 930 {
 931         PMD_INIT_FUNC_TRACE();
 932
 933         if (hw->mac.type == ixgbe_mac_82598EB) {
 934                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 935         } else {
 936                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 937                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 938                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 939         }
 940         IXGBE_WRITE_FLUSH(hw);
 941 }
 942
 943 /*
 944  * This function resets queue statistics mapping registers.
 945  * From Niantic datasheet, Initialization of Statistics section:
 946  * "...if software requires the queue counters, the RQSMR and TQSM registers
 947  * must be re-programmed following a device reset.
 948  */
 949 static void
 950 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 951 {
 952         uint32_t i;
 953
 954         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 956                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 957         }
 958 }
 959
 960
 961 static int
 962 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 963                                   uint16_t queue_id,
 964                                   uint8_t stat_idx,
 965                                   uint8_t is_rx)
 966 {
 967 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 968 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 969 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 970
 971         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 972         struct ixgbe_stat_mapping_registers *stat_mappings =
 973                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 974         uint32_t qsmr_mask = 0;
 975         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 976         uint32_t q_map;
 977         uint8_t n, offset;
 978
 979         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 980                 (hw->mac.type != ixgbe_mac_X540) &&
 981                 (hw->mac.type != ixgbe_mac_X550) &&
 982                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 983                 (hw->mac.type != ixgbe_mac_X550EM_a))
 984                 return -ENOSYS;
 985
 986         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 987                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 988                      queue_id, stat_idx);
 989
 990         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 991         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 992                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 993                 return -EIO;
 994         }
 995         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 996
 997         /* Now clear any previous stat_idx set */
 998         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 999         if (!is_rx)
1000                 stat_mappings->tqsm[n] &= ~clearing_mask;
1001         else
1002                 stat_mappings->rqsmr[n] &= ~clearing_mask;
1003
1004         q_map = (uint32_t)stat_idx;
1005         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1006         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1007         if (!is_rx)
1008                 stat_mappings->tqsm[n] |= qsmr_mask;
1009         else
1010                 stat_mappings->rqsmr[n] |= qsmr_mask;
1011
1012         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1013                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1014                      queue_id, stat_idx);
1015         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1016                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1017
1018         /* Now write the mapping in the appropriate register */
1019         if (is_rx) {
1020                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1021                              stat_mappings->rqsmr[n], n);
1022                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1023         } else {
1024                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1025                              stat_mappings->tqsm[n], n);
1026                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1027         }
1028         return 0;
1029 }
1030
1031 static void
1032 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1033 {
1034         struct ixgbe_stat_mapping_registers *stat_mappings =
1035                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         int i;
1038
1039         /* write whatever was in stat mapping table to the NIC */
1040         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1041                 /* rx */
1042                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1043
1044                 /* tx */
1045                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1046         }
1047 }
1048
1049 static void
1050 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1051 {
1052         uint8_t i;
1053         struct ixgbe_dcb_tc_config *tc;
1054         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1055
1056         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1057         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1058         for (i = 0; i < dcb_max_tc; i++) {
1059                 tc = &dcb_config->tc_config[i];
1060                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1061                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1062                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1063                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1064                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1065                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1066                 tc->pfc = ixgbe_dcb_pfc_disabled;
1067         }
1068
1069         /* Initialize default user to priority mapping, UPx->TC0 */
1070         tc = &dcb_config->tc_config[0];
1071         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1072         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1073         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1074                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1075                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1076         }
1077         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1078         dcb_config->pfc_mode_enable = false;
1079         dcb_config->vt_mode = true;
1080         dcb_config->round_robin_enable = false;
1081         /* support all DCB capabilities in 82599 */
1082         dcb_config->support.capabilities = 0xFF;
1083
1084         /*we only support 4 Tcs for X540, X550 */
1085         if (hw->mac.type == ixgbe_mac_X540 ||
1086                 hw->mac.type == ixgbe_mac_X550 ||
1087                 hw->mac.type == ixgbe_mac_X550EM_x ||
1088                 hw->mac.type == ixgbe_mac_X550EM_a) {
1089                 dcb_config->num_tcs.pg_tcs = 4;
1090                 dcb_config->num_tcs.pfc_tcs = 4;
1091         }
1092 }
1093
1094 /*
1095  * Ensure that all locks are released before first NVM or PHY access
1096  */
1097 static void
1098 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1099 {
1100         uint16_t mask;
1101
1102         /*
1103          * Phy lock should not fail in this early stage. If this is the case,
1104          * it is due to an improper exit of the application.
1105          * So force the release of the faulty lock. Release of common lock
1106          * is done automatically by swfw_sync function.
1107          */
1108         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1109         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1111         }
1112         ixgbe_release_swfw_semaphore(hw, mask);
1113
1114         /*
1115          * These ones are more tricky since they are common to all ports; but
1116          * swfw_sync retries last long enough (1s) to be almost sure that if
1117          * lock can not be taken it is due to an improper lock of the
1118          * semaphore.
1119          */
1120         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1121         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1122                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1123         }
1124         ixgbe_release_swfw_semaphore(hw, mask);
1125 }
1126
1127 /*
1128  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1129  * It returns 0 on success.
1130  */
1131 static int
1132 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1133 {
1134         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1135         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1136         struct ixgbe_hw *hw =
1137                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1138         struct ixgbe_vfta *shadow_vfta =
1139                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1140         struct ixgbe_hwstrip *hwstrip =
1141                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1142         struct ixgbe_dcb_config *dcb_config =
1143                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1144         struct ixgbe_filter_info *filter_info =
1145                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1146         uint32_t ctrl_ext;
1147         uint16_t csum;
1148         int diag, i;
1149
1150         PMD_INIT_FUNC_TRACE();
1151
1152         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1153         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1154         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1155         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1156
1157         /*
1158          * For secondary processes, we don't initialise any further as primary
1159          * has already done this work. Only check we don't need a different
1160          * RX and TX function.
1161          */
1162         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1163                 struct ixgbe_tx_queue *txq;
1164                 /* TX queue function in primary, set by last queue initialized
1165                  * Tx queue may not initialized by primary process
1166                  */
1167                 if (eth_dev->data->tx_queues) {
1168                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1169                         ixgbe_set_tx_function(eth_dev, txq);
1170                 } else {
1171                         /* Use default TX function if we get here */
1172                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1173                                      "Using default TX function.");
1174                 }
1175
1176                 ixgbe_set_rx_function(eth_dev);
1177
1178                 return 0;
1179         }
1180
1181         rte_eth_copy_pci_info(eth_dev, pci_dev);
1182         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1183
1184         /* Vendor and Device ID need to be set before init of shared code */
1185         hw->device_id = pci_dev->id.device_id;
1186         hw->vendor_id = pci_dev->id.vendor_id;
1187         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1188         hw->allow_unsupported_sfp = 1;
1189
1190         /* Initialize the shared code (base driver) */
1191 #ifdef RTE_NIC_BYPASS
1192         diag = ixgbe_bypass_init_shared_code(hw);
1193 #else
1194         diag = ixgbe_init_shared_code(hw);
1195 #endif /* RTE_NIC_BYPASS */
1196
1197         if (diag != IXGBE_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1199                 return -EIO;
1200         }
1201
1202         /* pick up the PCI bus settings for reporting later */
1203         ixgbe_get_bus_info(hw);
1204
1205         /* Unlock any pending hardware semaphore */
1206         ixgbe_swfw_lock_reset(hw);
1207
1208         /* Initialize DCB configuration*/
1209         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1210         ixgbe_dcb_init(hw, dcb_config);
1211         /* Get Hardware Flow Control setting */
1212         hw->fc.requested_mode = ixgbe_fc_full;
1213         hw->fc.current_mode = ixgbe_fc_full;
1214         hw->fc.pause_time = IXGBE_FC_PAUSE;
1215         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1216                 hw->fc.low_water[i] = IXGBE_FC_LO;
1217                 hw->fc.high_water[i] = IXGBE_FC_HI;
1218         }
1219         hw->fc.send_xon = 1;
1220
1221         /* Make sure we have a good EEPROM before we read from it */
1222         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1223         if (diag != IXGBE_SUCCESS) {
1224                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1225                 return -EIO;
1226         }
1227
1228 #ifdef RTE_NIC_BYPASS
1229         diag = ixgbe_bypass_init_hw(hw);
1230 #else
1231         diag = ixgbe_init_hw(hw);
1232 #endif /* RTE_NIC_BYPASS */
1233
1234         /*
1235          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1236          * is called too soon after the kernel driver unbinding/binding occurs.
1237          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1238          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1239          * also called. See ixgbe_identify_phy_82599(). The reason for the
1240          * failure is not known, and only occuts when virtualisation features
1241          * are disabled in the bios. A delay of 100ms  was found to be enough by
1242          * trial-and-error, and is doubled to be safe.
1243          */
1244         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1245                 rte_delay_ms(200);
1246                 diag = ixgbe_init_hw(hw);
1247         }
1248
1249         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1250                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1251                              "LOM.  Please be aware there may be issues associated "
1252                              "with your hardware.");
1253                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1254                              "please contact your Intel or hardware representative "
1255                              "who provided you with this hardware.");
1256         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1257                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1258         if (diag) {
1259                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1260                 return -EIO;
1261         }
1262
1263         /* Reset the hw statistics */
1264         ixgbe_dev_stats_reset(eth_dev);
1265
1266         /* disable interrupt */
1267         ixgbe_disable_intr(hw);
1268
1269         /* reset mappings for queue statistics hw counters*/
1270         ixgbe_reset_qstat_mappings(hw);
1271
1272         /* Allocate memory for storing MAC addresses */
1273         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1274                                                hw->mac.num_rar_entries, 0);
1275         if (eth_dev->data->mac_addrs == NULL) {
1276                 PMD_INIT_LOG(ERR,
1277                              "Failed to allocate %u bytes needed to store "
1278                              "MAC addresses",
1279                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1280                 return -ENOMEM;
1281         }
1282         /* Copy the permanent MAC address */
1283         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1284                         &eth_dev->data->mac_addrs[0]);
1285
1286         /* Allocate memory for storing hash filter MAC addresses */
1287         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1288                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1289         if (eth_dev->data->hash_mac_addrs == NULL) {
1290                 PMD_INIT_LOG(ERR,
1291                              "Failed to allocate %d bytes needed to store MAC addresses",
1292                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1293                 return -ENOMEM;
1294         }
1295
1296         /* initialize the vfta */
1297         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1298
1299         /* initialize the hw strip bitmap*/
1300         memset(hwstrip, 0, sizeof(*hwstrip));
1301
1302         /* initialize PF if max_vfs not zero */
1303         ixgbe_pf_host_init(eth_dev);
1304
1305         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1306         /* let hardware know driver is loaded */
1307         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1308         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1309         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1310         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1311         IXGBE_WRITE_FLUSH(hw);
1312
1313         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1314                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1315                              (int) hw->mac.type, (int) hw->phy.type,
1316                              (int) hw->phy.sfp_type);
1317         else
1318                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1319                              (int) hw->mac.type, (int) hw->phy.type);
1320
1321         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1322                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1323                      pci_dev->id.device_id);
1324
1325         rte_intr_callback_register(intr_handle,
1326                                    ixgbe_dev_interrupt_handler, eth_dev);
1327
1328         /* enable uio/vfio intr/eventfd mapping */
1329         rte_intr_enable(intr_handle);
1330
1331         /* enable support intr */
1332         ixgbe_enable_intr(eth_dev);
1333
1334         /* initialize filter info */
1335         memset(filter_info, 0,
1336                sizeof(struct ixgbe_filter_info));
1337
1338         /* initialize 5tuple filter list */
1339         TAILQ_INIT(&filter_info->fivetuple_list);
1340
1341         /* initialize flow director filter list & hash */
1342         ixgbe_fdir_filter_init(eth_dev);
1343
1344         /* initialize l2 tunnel filter list & hash */
1345         ixgbe_l2_tn_filter_init(eth_dev);
1346         return 0;
1347 }
1348
1349 static int
1350 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1351 {
1352         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1353         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1354         struct ixgbe_hw *hw;
1355
1356         PMD_INIT_FUNC_TRACE();
1357
1358         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1359                 return -EPERM;
1360
1361         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1362
1363         if (hw->adapter_stopped == 0)
1364                 ixgbe_dev_close(eth_dev);
1365
1366         eth_dev->dev_ops = NULL;
1367         eth_dev->rx_pkt_burst = NULL;
1368         eth_dev->tx_pkt_burst = NULL;
1369
1370         /* Unlock any pending hardware semaphore */
1371         ixgbe_swfw_lock_reset(hw);
1372
1373         /* disable uio intr before callback unregister */
1374         rte_intr_disable(intr_handle);
1375         rte_intr_callback_unregister(intr_handle,
1376                                      ixgbe_dev_interrupt_handler, eth_dev);
1377
1378         /* uninitialize PF if max_vfs not zero */
1379         ixgbe_pf_host_uninit(eth_dev);
1380
1381         rte_free(eth_dev->data->mac_addrs);
1382         eth_dev->data->mac_addrs = NULL;
1383
1384         rte_free(eth_dev->data->hash_mac_addrs);
1385         eth_dev->data->hash_mac_addrs = NULL;
1386
1387         /* remove all the fdir filters & hash */
1388         ixgbe_fdir_filter_uninit(eth_dev);
1389
1390         /* remove all the L2 tunnel filters & hash */
1391         ixgbe_l2_tn_filter_uninit(eth_dev);
1392
1393         /* Remove all ntuple filters of the device */
1394         ixgbe_ntuple_filter_uninit(eth_dev);
1395
1396         return 0;
1397 }
1398
1399 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1400 {
1401         struct ixgbe_filter_info *filter_info =
1402                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1403         struct ixgbe_5tuple_filter *p_5tuple;
1404
1405         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1406                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1407                              p_5tuple,
1408                              entries);
1409                 rte_free(p_5tuple);
1410         }
1411         memset(filter_info->fivetuple_mask, 0,
1412                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1413
1414         return 0;
1415 }
1416
1417 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1418 {
1419         struct ixgbe_hw_fdir_info *fdir_info =
1420                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1421         struct ixgbe_fdir_filter *fdir_filter;
1422
1423                 if (fdir_info->hash_map)
1424                 rte_free(fdir_info->hash_map);
1425         if (fdir_info->hash_handle)
1426                 rte_hash_free(fdir_info->hash_handle);
1427
1428         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1429                 TAILQ_REMOVE(&fdir_info->fdir_list,
1430                              fdir_filter,
1431                              entries);
1432                 rte_free(fdir_filter);
1433         }
1434
1435         return 0;
1436 }
1437
1438 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1439 {
1440         struct ixgbe_l2_tn_info *l2_tn_info =
1441                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1442         struct ixgbe_l2_tn_filter *l2_tn_filter;
1443
1444         if (l2_tn_info->hash_map)
1445                 rte_free(l2_tn_info->hash_map);
1446         if (l2_tn_info->hash_handle)
1447                 rte_hash_free(l2_tn_info->hash_handle);
1448
1449         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1450                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1451                              l2_tn_filter,
1452                              entries);
1453                 rte_free(l2_tn_filter);
1454         }
1455
1456         return 0;
1457 }
1458
1459 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1460 {
1461         struct ixgbe_hw_fdir_info *fdir_info =
1462                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1463         char fdir_hash_name[RTE_HASH_NAMESIZE];
1464         struct rte_hash_parameters fdir_hash_params = {
1465                 .name = fdir_hash_name,
1466                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1467                 .key_len = sizeof(union ixgbe_atr_input),
1468                 .hash_func = rte_hash_crc,
1469                 .hash_func_init_val = 0,
1470                 .socket_id = rte_socket_id(),
1471         };
1472
1473         TAILQ_INIT(&fdir_info->fdir_list);
1474         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1475                  "fdir_%s", eth_dev->data->name);
1476         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1477         if (!fdir_info->hash_handle) {
1478                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1479                 return -EINVAL;
1480         }
1481         fdir_info->hash_map = rte_zmalloc("ixgbe",
1482                                           sizeof(struct ixgbe_fdir_filter *) *
1483                                           IXGBE_MAX_FDIR_FILTER_NUM,
1484                                           0);
1485         if (!fdir_info->hash_map) {
1486                 PMD_INIT_LOG(ERR,
1487                              "Failed to allocate memory for fdir hash map!");
1488                 return -ENOMEM;
1489         }
1490         return 0;
1491 }
1492
1493 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1494 {
1495         struct ixgbe_l2_tn_info *l2_tn_info =
1496                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1497         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1498         struct rte_hash_parameters l2_tn_hash_params = {
1499                 .name = l2_tn_hash_name,
1500                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1501                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1502                 .hash_func = rte_hash_crc,
1503                 .hash_func_init_val = 0,
1504                 .socket_id = rte_socket_id(),
1505         };
1506
1507         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1508         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1509                  "l2_tn_%s", eth_dev->data->name);
1510         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1511         if (!l2_tn_info->hash_handle) {
1512                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1513                 return -EINVAL;
1514         }
1515         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1516                                    sizeof(struct ixgbe_l2_tn_filter *) *
1517                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1518                                    0);
1519         if (!l2_tn_info->hash_map) {
1520                 PMD_INIT_LOG(ERR,
1521                         "Failed to allocate memory for L2 TN hash map!");
1522                 return -ENOMEM;
1523         }
1524         l2_tn_info->e_tag_en = FALSE;
1525         l2_tn_info->e_tag_fwd_en = FALSE;
1526         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1527
1528         return 0;
1529 }
1530 /*
1531  * Negotiate mailbox API version with the PF.
1532  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1533  * Then we try to negotiate starting with the most recent one.
1534  * If all negotiation attempts fail, then we will proceed with
1535  * the default one (ixgbe_mbox_api_10).
1536  */
1537 static void
1538 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1539 {
1540         int32_t i;
1541
1542         /* start with highest supported, proceed down */
1543         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1544                 ixgbe_mbox_api_12,
1545                 ixgbe_mbox_api_11,
1546                 ixgbe_mbox_api_10,
1547         };
1548
1549         for (i = 0;
1550                         i != RTE_DIM(sup_ver) &&
1551                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1552                         i++)
1553                 ;
1554 }
1555
1556 static void
1557 generate_random_mac_addr(struct ether_addr *mac_addr)
1558 {
1559         uint64_t random;
1560
1561         /* Set Organizationally Unique Identifier (OUI) prefix. */
1562         mac_addr->addr_bytes[0] = 0x00;
1563         mac_addr->addr_bytes[1] = 0x09;
1564         mac_addr->addr_bytes[2] = 0xC0;
1565         /* Force indication of locally assigned MAC address. */
1566         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1567         /* Generate the last 3 bytes of the MAC address with a random number. */
1568         random = rte_rand();
1569         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1570 }
1571
1572 /*
1573  * Virtual Function device init
1574  */
1575 static int
1576 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1577 {
1578         int diag;
1579         uint32_t tc, tcs;
1580         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1581         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1582         struct ixgbe_hw *hw =
1583                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1584         struct ixgbe_vfta *shadow_vfta =
1585                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1586         struct ixgbe_hwstrip *hwstrip =
1587                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1588         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1589
1590         PMD_INIT_FUNC_TRACE();
1591
1592         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1593         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1594         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1595
1596         /* for secondary processes, we don't initialise any further as primary
1597          * has already done this work. Only check we don't need a different
1598          * RX function
1599          */
1600         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1601                 struct ixgbe_tx_queue *txq;
1602                 /* TX queue function in primary, set by last queue initialized
1603                  * Tx queue may not initialized by primary process
1604                  */
1605                 if (eth_dev->data->tx_queues) {
1606                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1607                         ixgbe_set_tx_function(eth_dev, txq);
1608                 } else {
1609                         /* Use default TX function if we get here */
1610                         PMD_INIT_LOG(NOTICE,
1611                                      "No TX queues configured yet. Using default TX function.");
1612                 }
1613
1614                 ixgbe_set_rx_function(eth_dev);
1615
1616                 return 0;
1617         }
1618
1619         rte_eth_copy_pci_info(eth_dev, pci_dev);
1620         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1621
1622         hw->device_id = pci_dev->id.device_id;
1623         hw->vendor_id = pci_dev->id.vendor_id;
1624         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1625
1626         /* initialize the vfta */
1627         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1628
1629         /* initialize the hw strip bitmap*/
1630         memset(hwstrip, 0, sizeof(*hwstrip));
1631
1632         /* Initialize the shared code (base driver) */
1633         diag = ixgbe_init_shared_code(hw);
1634         if (diag != IXGBE_SUCCESS) {
1635                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1636                 return -EIO;
1637         }
1638
1639         /* init_mailbox_params */
1640         hw->mbx.ops.init_params(hw);
1641
1642         /* Reset the hw statistics */
1643         ixgbevf_dev_stats_reset(eth_dev);
1644
1645         /* Disable the interrupts for VF */
1646         ixgbevf_intr_disable(hw);
1647
1648         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1649         diag = hw->mac.ops.reset_hw(hw);
1650
1651         /*
1652          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1653          * the underlying PF driver has not assigned a MAC address to the VF.
1654          * In this case, assign a random MAC address.
1655          */
1656         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1657                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1658                 return diag;
1659         }
1660
1661         /* negotiate mailbox API version to use with the PF. */
1662         ixgbevf_negotiate_api(hw);
1663
1664         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1665         ixgbevf_get_queues(hw, &tcs, &tc);
1666
1667         /* Allocate memory for storing MAC addresses */
1668         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1669                                                hw->mac.num_rar_entries, 0);
1670         if (eth_dev->data->mac_addrs == NULL) {
1671                 PMD_INIT_LOG(ERR,
1672                              "Failed to allocate %u bytes needed to store "
1673                              "MAC addresses",
1674                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1675                 return -ENOMEM;
1676         }
1677
1678         /* Generate a random MAC address, if none was assigned by PF. */
1679         if (is_zero_ether_addr(perm_addr)) {
1680                 generate_random_mac_addr(perm_addr);
1681                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1682                 if (diag) {
1683                         rte_free(eth_dev->data->mac_addrs);
1684                         eth_dev->data->mac_addrs = NULL;
1685                         return diag;
1686                 }
1687                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1688                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1689                              "%02x:%02x:%02x:%02x:%02x:%02x",
1690                              perm_addr->addr_bytes[0],
1691                              perm_addr->addr_bytes[1],
1692                              perm_addr->addr_bytes[2],
1693                              perm_addr->addr_bytes[3],
1694                              perm_addr->addr_bytes[4],
1695                              perm_addr->addr_bytes[5]);
1696         }
1697
1698         /* Copy the permanent MAC address */
1699         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1700
1701         /* reset the hardware with the new settings */
1702         diag = hw->mac.ops.start_hw(hw);
1703         switch (diag) {
1704         case  0:
1705                 break;
1706
1707         default:
1708                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1709                 return -EIO;
1710         }
1711
1712         rte_intr_callback_register(intr_handle,
1713                                    ixgbevf_dev_interrupt_handler, eth_dev);
1714         rte_intr_enable(intr_handle);
1715         ixgbevf_intr_enable(hw);
1716
1717         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1718                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1719                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1720
1721         return 0;
1722 }
1723
1724 /* Virtual Function device uninit */
1725
1726 static int
1727 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1728 {
1729         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1730         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1731         struct ixgbe_hw *hw;
1732
1733         PMD_INIT_FUNC_TRACE();
1734
1735         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1736                 return -EPERM;
1737
1738         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1739
1740         if (hw->adapter_stopped == 0)
1741                 ixgbevf_dev_close(eth_dev);
1742
1743         eth_dev->dev_ops = NULL;
1744         eth_dev->rx_pkt_burst = NULL;
1745         eth_dev->tx_pkt_burst = NULL;
1746
1747         /* Disable the interrupts for VF */
1748         ixgbevf_intr_disable(hw);
1749
1750         rte_free(eth_dev->data->mac_addrs);
1751         eth_dev->data->mac_addrs = NULL;
1752
1753         rte_intr_disable(intr_handle);
1754         rte_intr_callback_unregister(intr_handle,
1755                                      ixgbevf_dev_interrupt_handler, eth_dev);
1756
1757         return 0;
1758 }
1759
1760 static struct eth_driver rte_ixgbe_pmd = {
1761         .pci_drv = {
1762                 .id_table = pci_id_ixgbe_map,
1763                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1764                 .probe = rte_eth_dev_pci_probe,
1765                 .remove = rte_eth_dev_pci_remove,
1766         },
1767         .eth_dev_init = eth_ixgbe_dev_init,
1768         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1769         .dev_private_size = sizeof(struct ixgbe_adapter),
1770 };
1771
1772 /*
1773  * virtual function driver struct
1774  */
1775 static struct eth_driver rte_ixgbevf_pmd = {
1776         .pci_drv = {
1777                 .id_table = pci_id_ixgbevf_map,
1778                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1779                 .probe = rte_eth_dev_pci_probe,
1780                 .remove = rte_eth_dev_pci_remove,
1781         },
1782         .eth_dev_init = eth_ixgbevf_dev_init,
1783         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1784         .dev_private_size = sizeof(struct ixgbe_adapter),
1785 };
1786
1787 static int
1788 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1789 {
1790         struct ixgbe_hw *hw =
1791                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1792         struct ixgbe_vfta *shadow_vfta =
1793                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1794         uint32_t vfta;
1795         uint32_t vid_idx;
1796         uint32_t vid_bit;
1797
1798         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1799         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1800         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1801         if (on)
1802                 vfta |= vid_bit;
1803         else
1804                 vfta &= ~vid_bit;
1805         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1806
1807         /* update local VFTA copy */
1808         shadow_vfta->vfta[vid_idx] = vfta;
1809
1810         return 0;
1811 }
1812
1813 static void
1814 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1815 {
1816         if (on)
1817                 ixgbe_vlan_hw_strip_enable(dev, queue);
1818         else
1819                 ixgbe_vlan_hw_strip_disable(dev, queue);
1820 }
1821
1822 static int
1823 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1824                     enum rte_vlan_type vlan_type,
1825                     uint16_t tpid)
1826 {
1827         struct ixgbe_hw *hw =
1828                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829         int ret = 0;
1830         uint32_t reg;
1831         uint32_t qinq;
1832
1833         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1834         qinq &= IXGBE_DMATXCTL_GDV;
1835
1836         switch (vlan_type) {
1837         case ETH_VLAN_TYPE_INNER:
1838                 if (qinq) {
1839                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1840                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1841                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1842                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1843                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1844                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1845                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1846                 } else {
1847                         ret = -ENOTSUP;
1848                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1849                                     " by single VLAN");
1850                 }
1851                 break;
1852         case ETH_VLAN_TYPE_OUTER:
1853                 if (qinq) {
1854                         /* Only the high 16-bits is valid */
1855                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1856                                         IXGBE_EXVET_VET_EXT_SHIFT);
1857                 } else {
1858                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1859                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1860                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1861                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1862                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1863                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1864                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1865                 }
1866
1867                 break;
1868         default:
1869                 ret = -EINVAL;
1870                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1871                 break;
1872         }
1873
1874         return ret;
1875 }
1876
1877 void
1878 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1879 {
1880         struct ixgbe_hw *hw =
1881                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882         uint32_t vlnctrl;
1883
1884         PMD_INIT_FUNC_TRACE();
1885
1886         /* Filter Table Disable */
1887         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1888         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1889
1890         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1891 }
1892
1893 void
1894 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1895 {
1896         struct ixgbe_hw *hw =
1897                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898         struct ixgbe_vfta *shadow_vfta =
1899                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1900         uint32_t vlnctrl;
1901         uint16_t i;
1902
1903         PMD_INIT_FUNC_TRACE();
1904
1905         /* Filter Table Enable */
1906         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1907         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1908         vlnctrl |= IXGBE_VLNCTRL_VFE;
1909
1910         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1911
1912         /* write whatever is in local vfta copy */
1913         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1914                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1915 }
1916
1917 static void
1918 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1919 {
1920         struct ixgbe_hwstrip *hwstrip =
1921                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1922         struct ixgbe_rx_queue *rxq;
1923
1924         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1925                 return;
1926
1927         if (on)
1928                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1929         else
1930                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1931
1932         if (queue >= dev->data->nb_rx_queues)
1933                 return;
1934
1935         rxq = dev->data->rx_queues[queue];
1936
1937         if (on)
1938                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1939         else
1940                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1941 }
1942
1943 static void
1944 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1945 {
1946         struct ixgbe_hw *hw =
1947                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948         uint32_t ctrl;
1949
1950         PMD_INIT_FUNC_TRACE();
1951
1952         if (hw->mac.type == ixgbe_mac_82598EB) {
1953                 /* No queue level support */
1954                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1955                 return;
1956         }
1957
1958         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1959         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1960         ctrl &= ~IXGBE_RXDCTL_VME;
1961         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1962
1963         /* record those setting for HW strip per queue */
1964         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1965 }
1966
1967 static void
1968 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1969 {
1970         struct ixgbe_hw *hw =
1971                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972         uint32_t ctrl;
1973
1974         PMD_INIT_FUNC_TRACE();
1975
1976         if (hw->mac.type == ixgbe_mac_82598EB) {
1977                 /* No queue level supported */
1978                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1979                 return;
1980         }
1981
1982         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1983         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1984         ctrl |= IXGBE_RXDCTL_VME;
1985         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1986
1987         /* record those setting for HW strip per queue */
1988         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1989 }
1990
1991 void
1992 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1993 {
1994         struct ixgbe_hw *hw =
1995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996         uint32_t ctrl;
1997         uint16_t i;
1998         struct ixgbe_rx_queue *rxq;
1999
2000         PMD_INIT_FUNC_TRACE();
2001
2002         if (hw->mac.type == ixgbe_mac_82598EB) {
2003                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2004                 ctrl &= ~IXGBE_VLNCTRL_VME;
2005                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2006         } else {
2007                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2008                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2009                         rxq = dev->data->rx_queues[i];
2010                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2011                         ctrl &= ~IXGBE_RXDCTL_VME;
2012                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2013
2014                         /* record those setting for HW strip per queue */
2015                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2016                 }
2017         }
2018 }
2019
2020 void
2021 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2022 {
2023         struct ixgbe_hw *hw =
2024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         uint32_t ctrl;
2026         uint16_t i;
2027         struct ixgbe_rx_queue *rxq;
2028
2029         PMD_INIT_FUNC_TRACE();
2030
2031         if (hw->mac.type == ixgbe_mac_82598EB) {
2032                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2033                 ctrl |= IXGBE_VLNCTRL_VME;
2034                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2035         } else {
2036                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2037                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2038                         rxq = dev->data->rx_queues[i];
2039                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2040                         ctrl |= IXGBE_RXDCTL_VME;
2041                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2042
2043                         /* record those setting for HW strip per queue */
2044                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2045                 }
2046         }
2047 }
2048
2049 static void
2050 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2051 {
2052         struct ixgbe_hw *hw =
2053                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054         uint32_t ctrl;
2055
2056         PMD_INIT_FUNC_TRACE();
2057
2058         /* DMATXCTRL: Geric Double VLAN Disable */
2059         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2060         ctrl &= ~IXGBE_DMATXCTL_GDV;
2061         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2062
2063         /* CTRL_EXT: Global Double VLAN Disable */
2064         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2065         ctrl &= ~IXGBE_EXTENDED_VLAN;
2066         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2067
2068 }
2069
2070 static void
2071 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2072 {
2073         struct ixgbe_hw *hw =
2074                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075         uint32_t ctrl;
2076
2077         PMD_INIT_FUNC_TRACE();
2078
2079         /* DMATXCTRL: Geric Double VLAN Enable */
2080         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2081         ctrl |= IXGBE_DMATXCTL_GDV;
2082         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2083
2084         /* CTRL_EXT: Global Double VLAN Enable */
2085         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2086         ctrl |= IXGBE_EXTENDED_VLAN;
2087         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2088
2089         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2090         if (hw->mac.type == ixgbe_mac_X550 ||
2091             hw->mac.type == ixgbe_mac_X550EM_x ||
2092             hw->mac.type == ixgbe_mac_X550EM_a) {
2093                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2094                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2095                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2096         }
2097
2098         /*
2099          * VET EXT field in the EXVET register = 0x8100 by default
2100          * So no need to change. Same to VT field of DMATXCTL register
2101          */
2102 }
2103
2104 static void
2105 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2106 {
2107         if (mask & ETH_VLAN_STRIP_MASK) {
2108                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2109                         ixgbe_vlan_hw_strip_enable_all(dev);
2110                 else
2111                         ixgbe_vlan_hw_strip_disable_all(dev);
2112         }
2113
2114         if (mask & ETH_VLAN_FILTER_MASK) {
2115                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2116                         ixgbe_vlan_hw_filter_enable(dev);
2117                 else
2118                         ixgbe_vlan_hw_filter_disable(dev);
2119         }
2120
2121         if (mask & ETH_VLAN_EXTEND_MASK) {
2122                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2123                         ixgbe_vlan_hw_extend_enable(dev);
2124                 else
2125                         ixgbe_vlan_hw_extend_disable(dev);
2126         }
2127 }
2128
2129 static void
2130 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2131 {
2132         struct ixgbe_hw *hw =
2133                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2135         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2136
2137         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2138         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2139 }
2140
2141 static int
2142 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2143 {
2144         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2145
2146         switch (nb_rx_q) {
2147         case 1:
2148         case 2:
2149                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2150                 break;
2151         case 4:
2152                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2153                 break;
2154         default:
2155                 return -EINVAL;
2156         }
2157
2158         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2159         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2160
2161         return 0;
2162 }
2163
2164 static int
2165 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2166 {
2167         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2170         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2171
2172         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2173                 /* check multi-queue mode */
2174                 switch (dev_conf->rxmode.mq_mode) {
2175                 case ETH_MQ_RX_VMDQ_DCB:
2176                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2177                         break;
2178                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2179                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2180                         PMD_INIT_LOG(ERR, "SRIOV active,"
2181                                         " unsupported mq_mode rx %d.",
2182                                         dev_conf->rxmode.mq_mode);
2183                         return -EINVAL;
2184                 case ETH_MQ_RX_RSS:
2185                 case ETH_MQ_RX_VMDQ_RSS:
2186                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2187                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2188                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2189                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2190                                                 " invalid queue number"
2191                                                 " for VMDQ RSS, allowed"
2192                                                 " value are 1, 2 or 4.");
2193                                         return -EINVAL;
2194                                 }
2195                         break;
2196                 case ETH_MQ_RX_VMDQ_ONLY:
2197                 case ETH_MQ_RX_NONE:
2198                         /* if nothing mq mode configure, use default scheme */
2199                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2200                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2201                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2202                         break;
2203                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2204                         /* SRIOV only works in VMDq enable mode */
2205                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2206                                         " wrong mq_mode rx %d.",
2207                                         dev_conf->rxmode.mq_mode);
2208                         return -EINVAL;
2209                 }
2210
2211                 switch (dev_conf->txmode.mq_mode) {
2212                 case ETH_MQ_TX_VMDQ_DCB:
2213                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2214                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2215                         break;
2216                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2217                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2218                         break;
2219                 }
2220
2221                 /* check valid queue number */
2222                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2223                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2224                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2225                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2226                                         " must be less than or equal to %d.",
2227                                         nb_rx_q, nb_tx_q,
2228                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2229                         return -EINVAL;
2230                 }
2231         } else {
2232                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2233                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2234                                           " not supported.");
2235                         return -EINVAL;
2236                 }
2237                 /* check configuration for vmdb+dcb mode */
2238                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2239                         const struct rte_eth_vmdq_dcb_conf *conf;
2240
2241                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2242                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2243                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2244                                 return -EINVAL;
2245                         }
2246                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2247                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2248                                conf->nb_queue_pools == ETH_32_POOLS)) {
2249                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2250                                                 " nb_queue_pools must be %d or %d.",
2251                                                 ETH_16_POOLS, ETH_32_POOLS);
2252                                 return -EINVAL;
2253                         }
2254                 }
2255                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2256                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2257
2258                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2259                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2260                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2261                                 return -EINVAL;
2262                         }
2263                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2264                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2265                                conf->nb_queue_pools == ETH_32_POOLS)) {
2266                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2267                                                 " nb_queue_pools != %d and"
2268                                                 " nb_queue_pools != %d.",
2269                                                 ETH_16_POOLS, ETH_32_POOLS);
2270                                 return -EINVAL;
2271                         }
2272                 }
2273
2274                 /* For DCB mode check our configuration before we go further */
2275                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2276                         const struct rte_eth_dcb_rx_conf *conf;
2277
2278                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2279                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2280                                                  IXGBE_DCB_NB_QUEUES);
2281                                 return -EINVAL;
2282                         }
2283                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2284                         if (!(conf->nb_tcs == ETH_4_TCS ||
2285                                conf->nb_tcs == ETH_8_TCS)) {
2286                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2287                                                 " and nb_tcs != %d.",
2288                                                 ETH_4_TCS, ETH_8_TCS);
2289                                 return -EINVAL;
2290                         }
2291                 }
2292
2293                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2294                         const struct rte_eth_dcb_tx_conf *conf;
2295
2296                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2297                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2298                                                  IXGBE_DCB_NB_QUEUES);
2299                                 return -EINVAL;
2300                         }
2301                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2302                         if (!(conf->nb_tcs == ETH_4_TCS ||
2303                                conf->nb_tcs == ETH_8_TCS)) {
2304                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2305                                                 " and nb_tcs != %d.",
2306                                                 ETH_4_TCS, ETH_8_TCS);
2307                                 return -EINVAL;
2308                         }
2309                 }
2310
2311                 /*
2312                  * When DCB/VT is off, maximum number of queues changes,
2313                  * except for 82598EB, which remains constant.
2314                  */
2315                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2316                                 hw->mac.type != ixgbe_mac_82598EB) {
2317                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2318                                 PMD_INIT_LOG(ERR,
2319                                              "Neither VT nor DCB are enabled, "
2320                                              "nb_tx_q > %d.",
2321                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2322                                 return -EINVAL;
2323                         }
2324                 }
2325         }
2326         return 0;
2327 }
2328
2329 static int
2330 ixgbe_dev_configure(struct rte_eth_dev *dev)
2331 {
2332         struct ixgbe_interrupt *intr =
2333                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2334         struct ixgbe_adapter *adapter =
2335                 (struct ixgbe_adapter *)dev->data->dev_private;
2336         int ret;
2337
2338         PMD_INIT_FUNC_TRACE();
2339         /* multipe queue mode checking */
2340         ret  = ixgbe_check_mq_mode(dev);
2341         if (ret != 0) {
2342                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2343                             ret);
2344                 return ret;
2345         }
2346
2347         /* set flag to update link status after init */
2348         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2349
2350         /*
2351          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2352          * allocation or vector Rx preconditions we will reset it.
2353          */
2354         adapter->rx_bulk_alloc_allowed = true;
2355         adapter->rx_vec_allowed = true;
2356
2357         return 0;
2358 }
2359
2360 static void
2361 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2362 {
2363         struct ixgbe_hw *hw =
2364                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2365         struct ixgbe_interrupt *intr =
2366                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2367         uint32_t gpie;
2368
2369         /* only set up it on X550EM_X */
2370         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2371                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2372                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2373                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2374                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2375                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2376         }
2377 }
2378
2379 /*
2380  * Configure device link speed and setup link.
2381  * It returns 0 on success.
2382  */
2383 static int
2384 ixgbe_dev_start(struct rte_eth_dev *dev)
2385 {
2386         struct ixgbe_hw *hw =
2387                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         struct ixgbe_vf_info *vfinfo =
2389                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2390         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2391         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2392         uint32_t intr_vector = 0;
2393         int err, link_up = 0, negotiate = 0;
2394         uint32_t speed = 0;
2395         int mask = 0;
2396         int status;
2397         uint16_t vf, idx;
2398         uint32_t *link_speeds;
2399
2400         PMD_INIT_FUNC_TRACE();
2401
2402         /* IXGBE devices don't support:
2403         *    - half duplex (checked afterwards for valid speeds)
2404         *    - fixed speed: TODO implement
2405         */
2406         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2407                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2408                              dev->data->port_id);
2409                 return -EINVAL;
2410         }
2411
2412         /* disable uio/vfio intr/eventfd mapping */
2413         rte_intr_disable(intr_handle);
2414
2415         /* stop adapter */
2416         hw->adapter_stopped = 0;
2417         ixgbe_stop_adapter(hw);
2418
2419         /* reinitialize adapter
2420          * this calls reset and start
2421          */
2422         status = ixgbe_pf_reset_hw(hw);
2423         if (status != 0)
2424                 return -1;
2425         hw->mac.ops.start_hw(hw);
2426         hw->mac.get_link_status = true;
2427
2428         /* configure PF module if SRIOV enabled */
2429         ixgbe_pf_host_configure(dev);
2430
2431         ixgbe_dev_phy_intr_setup(dev);
2432
2433         /* check and configure queue intr-vector mapping */
2434         if ((rte_intr_cap_multiple(intr_handle) ||
2435              !RTE_ETH_DEV_SRIOV(dev).active) &&
2436             dev->data->dev_conf.intr_conf.rxq != 0) {
2437                 intr_vector = dev->data->nb_rx_queues;
2438                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2439                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2440                                         IXGBE_MAX_INTR_QUEUE_NUM);
2441                         return -ENOTSUP;
2442                 }
2443                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2444                         return -1;
2445         }
2446
2447         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2448                 intr_handle->intr_vec =
2449                         rte_zmalloc("intr_vec",
2450                                     dev->data->nb_rx_queues * sizeof(int), 0);
2451                 if (intr_handle->intr_vec == NULL) {
2452                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2453                                      " intr_vec\n", dev->data->nb_rx_queues);
2454                         return -ENOMEM;
2455                 }
2456         }
2457
2458         /* confiugre msix for sleep until rx interrupt */
2459         ixgbe_configure_msix(dev);
2460
2461         /* initialize transmission unit */
2462         ixgbe_dev_tx_init(dev);
2463
2464         /* This can fail when allocating mbufs for descriptor rings */
2465         err = ixgbe_dev_rx_init(dev);
2466         if (err) {
2467                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2468                 goto error;
2469         }
2470
2471     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2472                 ETH_VLAN_EXTEND_MASK;
2473         ixgbe_vlan_offload_set(dev, mask);
2474
2475         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2476                 /* Enable vlan filtering for VMDq */
2477                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2478         }
2479
2480         /* Configure DCB hw */
2481         ixgbe_configure_dcb(dev);
2482
2483         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2484                 err = ixgbe_fdir_configure(dev);
2485                 if (err)
2486                         goto error;
2487         }
2488
2489         /* Restore vf rate limit */
2490         if (vfinfo != NULL) {
2491                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2492                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2493                                 if (vfinfo[vf].tx_rate[idx] != 0)
2494                                         rte_pmd_ixgbe_set_vf_rate_limit(
2495                                                 dev->data->port_id, vf,
2496                                                 vfinfo[vf].tx_rate[idx],
2497                                                 1 << idx);
2498         }
2499
2500         ixgbe_restore_statistics_mapping(dev);
2501
2502         err = ixgbe_dev_rxtx_start(dev);
2503         if (err < 0) {
2504                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2505                 goto error;
2506         }
2507
2508         /* Skip link setup if loopback mode is enabled for 82599. */
2509         if (hw->mac.type == ixgbe_mac_82599EB &&
2510                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2511                 goto skip_link_setup;
2512
2513         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2514                 err = hw->mac.ops.setup_sfp(hw);
2515                 if (err)
2516                         goto error;
2517         }
2518
2519         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2520                 /* Turn on the copper */
2521                 ixgbe_set_phy_power(hw, true);
2522         } else {
2523                 /* Turn on the laser */
2524                 ixgbe_enable_tx_laser(hw);
2525         }
2526
2527         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2528         if (err)
2529                 goto error;
2530         dev->data->dev_link.link_status = link_up;
2531
2532         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2533         if (err)
2534                 goto error;
2535
2536         link_speeds = &dev->data->dev_conf.link_speeds;
2537         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2538                         ETH_LINK_SPEED_10G)) {
2539                 PMD_INIT_LOG(ERR, "Invalid link setting");
2540                 goto error;
2541         }
2542
2543         speed = 0x0;
2544         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2545                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2546                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2547                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2548         } else {
2549                 if (*link_speeds & ETH_LINK_SPEED_10G)
2550                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2551                 if (*link_speeds & ETH_LINK_SPEED_1G)
2552                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2553                 if (*link_speeds & ETH_LINK_SPEED_100M)
2554                         speed |= IXGBE_LINK_SPEED_100_FULL;
2555         }
2556
2557         err = ixgbe_setup_link(hw, speed, link_up);
2558         if (err)
2559                 goto error;
2560
2561 skip_link_setup:
2562
2563         if (rte_intr_allow_others(intr_handle)) {
2564                 /* check if lsc interrupt is enabled */
2565                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2566                         ixgbe_dev_lsc_interrupt_setup(dev);
2567                 ixgbe_dev_macsec_interrupt_setup(dev);
2568         } else {
2569                 rte_intr_callback_unregister(intr_handle,
2570                                              ixgbe_dev_interrupt_handler, dev);
2571                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2572                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2573                                      " no intr multiplex\n");
2574         }
2575
2576         /* check if rxq interrupt is enabled */
2577         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2578             rte_intr_dp_is_en(intr_handle))
2579                 ixgbe_dev_rxq_interrupt_setup(dev);
2580
2581         /* enable uio/vfio intr/eventfd mapping */
2582         rte_intr_enable(intr_handle);
2583
2584         /* resume enabled intr since hw reset */
2585         ixgbe_enable_intr(dev);
2586         ixgbe_l2_tunnel_conf(dev);
2587         ixgbe_filter_restore(dev);
2588
2589         return 0;
2590
2591 error:
2592         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2593         ixgbe_dev_clear_queues(dev);
2594         return -EIO;
2595 }
2596
2597 /*
2598  * Stop device: disable rx and tx functions to allow for reconfiguring.
2599  */
2600 static void
2601 ixgbe_dev_stop(struct rte_eth_dev *dev)
2602 {
2603         struct rte_eth_link link;
2604         struct ixgbe_hw *hw =
2605                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2606         struct ixgbe_vf_info *vfinfo =
2607                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2608         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2609         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2610         int vf;
2611
2612         PMD_INIT_FUNC_TRACE();
2613
2614         /* disable interrupts */
2615         ixgbe_disable_intr(hw);
2616
2617         /* reset the NIC */
2618         ixgbe_pf_reset_hw(hw);
2619         hw->adapter_stopped = 0;
2620
2621         /* stop adapter */
2622         ixgbe_stop_adapter(hw);
2623
2624         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2625                 vfinfo[vf].clear_to_send = false;
2626
2627         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2628                 /* Turn off the copper */
2629                 ixgbe_set_phy_power(hw, false);
2630         } else {
2631                 /* Turn off the laser */
2632                 ixgbe_disable_tx_laser(hw);
2633         }
2634
2635         ixgbe_dev_clear_queues(dev);
2636
2637         /* Clear stored conf */
2638         dev->data->scattered_rx = 0;
2639         dev->data->lro = 0;
2640
2641         /* Clear recorded link status */
2642         memset(&link, 0, sizeof(link));
2643         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2644
2645         if (!rte_intr_allow_others(intr_handle))
2646                 /* resume to the default handler */
2647                 rte_intr_callback_register(intr_handle,
2648                                            ixgbe_dev_interrupt_handler,
2649                                            (void *)dev);
2650
2651         /* Clean datapath event and queue/vec mapping */
2652         rte_intr_efd_disable(intr_handle);
2653         if (intr_handle->intr_vec != NULL) {
2654                 rte_free(intr_handle->intr_vec);
2655                 intr_handle->intr_vec = NULL;
2656         }
2657 }
2658
2659 /*
2660  * Set device link up: enable tx.
2661  */
2662 static int
2663 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2664 {
2665         struct ixgbe_hw *hw =
2666                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2667         if (hw->mac.type == ixgbe_mac_82599EB) {
2668 #ifdef RTE_NIC_BYPASS
2669                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2670                         /* Not suported in bypass mode */
2671                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2672                                      "by device id 0x%x", hw->device_id);
2673                         return -ENOTSUP;
2674                 }
2675 #endif
2676         }
2677
2678         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2679                 /* Turn on the copper */
2680                 ixgbe_set_phy_power(hw, true);
2681         } else {
2682                 /* Turn on the laser */
2683                 ixgbe_enable_tx_laser(hw);
2684         }
2685
2686         return 0;
2687 }
2688
2689 /*
2690  * Set device link down: disable tx.
2691  */
2692 static int
2693 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2694 {
2695         struct ixgbe_hw *hw =
2696                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2697         if (hw->mac.type == ixgbe_mac_82599EB) {
2698 #ifdef RTE_NIC_BYPASS
2699                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2700                         /* Not suported in bypass mode */
2701                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2702                                      "by device id 0x%x", hw->device_id);
2703                         return -ENOTSUP;
2704                 }
2705 #endif
2706         }
2707
2708         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2709                 /* Turn off the copper */
2710                 ixgbe_set_phy_power(hw, false);
2711         } else {
2712                 /* Turn off the laser */
2713                 ixgbe_disable_tx_laser(hw);
2714         }
2715
2716         return 0;
2717 }
2718
2719 /*
2720  * Reest and stop device.
2721  */
2722 static void
2723 ixgbe_dev_close(struct rte_eth_dev *dev)
2724 {
2725         struct ixgbe_hw *hw =
2726                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2727
2728         PMD_INIT_FUNC_TRACE();
2729
2730         ixgbe_pf_reset_hw(hw);
2731
2732         ixgbe_dev_stop(dev);
2733         hw->adapter_stopped = 1;
2734
2735         ixgbe_dev_free_queues(dev);
2736
2737         ixgbe_disable_pcie_master(hw);
2738
2739         /* reprogram the RAR[0] in case user changed it. */
2740         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2741 }
2742
2743 static void
2744 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2745                            struct ixgbe_hw_stats *hw_stats,
2746                            struct ixgbe_macsec_stats *macsec_stats,
2747                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2748                            uint64_t *total_qprc, uint64_t *total_qprdc)
2749 {
2750         uint32_t bprc, lxon, lxoff, total;
2751         uint32_t delta_gprc = 0;
2752         unsigned i;
2753         /* Workaround for RX byte count not including CRC bytes when CRC
2754          * strip is enabled. CRC bytes are removed from counters when crc_strip
2755          * is disabled.
2756          */
2757         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2758                         IXGBE_HLREG0_RXCRCSTRP);
2759
2760         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2761         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2762         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2763         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2764
2765         for (i = 0; i < 8; i++) {
2766                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2767
2768                 /* global total per queue */
2769                 hw_stats->mpc[i] += mp;
2770                 /* Running comprehensive total for stats display */
2771                 *total_missed_rx += hw_stats->mpc[i];
2772                 if (hw->mac.type == ixgbe_mac_82598EB) {
2773                         hw_stats->rnbc[i] +=
2774                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2775                         hw_stats->pxonrxc[i] +=
2776                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2777                         hw_stats->pxoffrxc[i] +=
2778                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2779                 } else {
2780                         hw_stats->pxonrxc[i] +=
2781                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2782                         hw_stats->pxoffrxc[i] +=
2783                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2784                         hw_stats->pxon2offc[i] +=
2785                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2786                 }
2787                 hw_stats->pxontxc[i] +=
2788                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2789                 hw_stats->pxofftxc[i] +=
2790                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2791         }
2792         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2793                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2794                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2795                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2796
2797                 delta_gprc += delta_qprc;
2798
2799                 hw_stats->qprc[i] += delta_qprc;
2800                 hw_stats->qptc[i] += delta_qptc;
2801
2802                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2803                 hw_stats->qbrc[i] +=
2804                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2805                 if (crc_strip == 0)
2806                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2807
2808                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2809                 hw_stats->qbtc[i] +=
2810                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2811
2812                 hw_stats->qprdc[i] += delta_qprdc;
2813                 *total_qprdc += hw_stats->qprdc[i];
2814
2815                 *total_qprc += hw_stats->qprc[i];
2816                 *total_qbrc += hw_stats->qbrc[i];
2817         }
2818         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2819         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2820         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2821
2822         /*
2823          * An errata states that gprc actually counts good + missed packets:
2824          * Workaround to set gprc to summated queue packet receives
2825          */
2826         hw_stats->gprc = *total_qprc;
2827
2828         if (hw->mac.type != ixgbe_mac_82598EB) {
2829                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2830                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2831                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2832                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2833                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2834                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2835                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2836                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2837         } else {
2838                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2839                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2840                 /* 82598 only has a counter in the high register */
2841                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2842                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2843                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2844         }
2845         uint64_t old_tpr = hw_stats->tpr;
2846
2847         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2848         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2849
2850         if (crc_strip == 0)
2851                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2852
2853         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2854         hw_stats->gptc += delta_gptc;
2855         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2856         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2857
2858         /*
2859          * Workaround: mprc hardware is incorrectly counting
2860          * broadcasts, so for now we subtract those.
2861          */
2862         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2863         hw_stats->bprc += bprc;
2864         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2865         if (hw->mac.type == ixgbe_mac_82598EB)
2866                 hw_stats->mprc -= bprc;
2867
2868         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2869         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2870         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2871         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2872         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2873         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2874
2875         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2876         hw_stats->lxontxc += lxon;
2877         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2878         hw_stats->lxofftxc += lxoff;
2879         total = lxon + lxoff;
2880
2881         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2882         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2883         hw_stats->gptc -= total;
2884         hw_stats->mptc -= total;
2885         hw_stats->ptc64 -= total;
2886         hw_stats->gotc -= total * ETHER_MIN_LEN;
2887
2888         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2889         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2890         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2891         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2892         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2893         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2894         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2895         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2896         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2897         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2898         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2899         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2900         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2901         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2902         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2903         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2904         /* Only read FCOE on 82599 */
2905         if (hw->mac.type != ixgbe_mac_82598EB) {
2906                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2907                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2908                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2909                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2910                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2911         }
2912
2913         /* Flow Director Stats registers */
2914         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2915         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2916
2917         /* MACsec Stats registers */
2918         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2919         macsec_stats->out_pkts_encrypted +=
2920                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2921         macsec_stats->out_pkts_protected +=
2922                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2923         macsec_stats->out_octets_encrypted +=
2924                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2925         macsec_stats->out_octets_protected +=
2926                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2927         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2928         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2929         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2930         macsec_stats->in_pkts_unknownsci +=
2931                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2932         macsec_stats->in_octets_decrypted +=
2933                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2934         macsec_stats->in_octets_validated +=
2935                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2936         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2937         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2938         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2939         for (i = 0; i < 2; i++) {
2940                 macsec_stats->in_pkts_ok +=
2941                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2942                 macsec_stats->in_pkts_invalid +=
2943                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2944                 macsec_stats->in_pkts_notvalid +=
2945                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2946         }
2947         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2948         macsec_stats->in_pkts_notusingsa +=
2949                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2950 }
2951
2952 /*
2953  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2954  */
2955 static void
2956 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2957 {
2958         struct ixgbe_hw *hw =
2959                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960         struct ixgbe_hw_stats *hw_stats =
2961                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2962         struct ixgbe_macsec_stats *macsec_stats =
2963                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2964                                 dev->data->dev_private);
2965         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2966         unsigned i;
2967
2968         total_missed_rx = 0;
2969         total_qbrc = 0;
2970         total_qprc = 0;
2971         total_qprdc = 0;
2972
2973         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2974                         &total_qbrc, &total_qprc, &total_qprdc);
2975
2976         if (stats == NULL)
2977                 return;
2978
2979         /* Fill out the rte_eth_stats statistics structure */
2980         stats->ipackets = total_qprc;
2981         stats->ibytes = total_qbrc;
2982         stats->opackets = hw_stats->gptc;
2983         stats->obytes = hw_stats->gotc;
2984
2985         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2986                 stats->q_ipackets[i] = hw_stats->qprc[i];
2987                 stats->q_opackets[i] = hw_stats->qptc[i];
2988                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2989                 stats->q_obytes[i] = hw_stats->qbtc[i];
2990                 stats->q_errors[i] = hw_stats->qprdc[i];
2991         }
2992
2993         /* Rx Errors */
2994         stats->imissed  = total_missed_rx;
2995         stats->ierrors  = hw_stats->crcerrs +
2996                           hw_stats->mspdc +
2997                           hw_stats->rlec +
2998                           hw_stats->ruc +
2999                           hw_stats->roc +
3000                           hw_stats->illerrc +
3001                           hw_stats->errbc +
3002                           hw_stats->rfc +
3003                           hw_stats->fccrc +
3004                           hw_stats->fclast;
3005
3006         /* Tx Errors */
3007         stats->oerrors  = 0;
3008 }
3009
3010 static void
3011 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3012 {
3013         struct ixgbe_hw_stats *stats =
3014                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3015
3016         /* HW registers are cleared on read */
3017         ixgbe_dev_stats_get(dev, NULL);
3018
3019         /* Reset software totals */
3020         memset(stats, 0, sizeof(*stats));
3021 }
3022
3023 /* This function calculates the number of xstats based on the current config */
3024 static unsigned
3025 ixgbe_xstats_calc_num(void) {
3026         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3027                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3028                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3029 }
3030
3031 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3032         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3033 {
3034         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3035         unsigned stat, i, count;
3036
3037         if (xstats_names != NULL) {
3038                 count = 0;
3039
3040                 /* Note: limit >= cnt_stats checked upstream
3041                  * in rte_eth_xstats_names()
3042                  */
3043
3044                 /* Extended stats from ixgbe_hw_stats */
3045                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3046                         snprintf(xstats_names[count].name,
3047                                 sizeof(xstats_names[count].name),
3048                                 "%s",
3049                                 rte_ixgbe_stats_strings[i].name);
3050                         count++;
3051                 }
3052
3053                 /* MACsec Stats */
3054                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3055                         snprintf(xstats_names[count].name,
3056                                 sizeof(xstats_names[count].name),
3057                                 "%s",
3058                                 rte_ixgbe_macsec_strings[i].name);
3059                         count++;
3060                 }
3061
3062                 /* RX Priority Stats */
3063                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3064                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3065                                 snprintf(xstats_names[count].name,
3066                                         sizeof(xstats_names[count].name),
3067                                         "rx_priority%u_%s", i,
3068                                         rte_ixgbe_rxq_strings[stat].name);
3069                                 count++;
3070                         }
3071                 }
3072
3073                 /* TX Priority Stats */
3074                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3075                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3076                                 snprintf(xstats_names[count].name,
3077                                         sizeof(xstats_names[count].name),
3078                                         "tx_priority%u_%s", i,
3079                                         rte_ixgbe_txq_strings[stat].name);
3080                                 count++;
3081                         }
3082                 }
3083         }
3084         return cnt_stats;
3085 }
3086
3087 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3088         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3089 {
3090         unsigned i;
3091
3092         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3093                 return -ENOMEM;
3094
3095         if (xstats_names != NULL)
3096                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3097                         snprintf(xstats_names[i].name,
3098                                 sizeof(xstats_names[i].name),
3099                                 "%s", rte_ixgbevf_stats_strings[i].name);
3100         return IXGBEVF_NB_XSTATS;
3101 }
3102
3103 static int
3104 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3105                                          unsigned n)
3106 {
3107         struct ixgbe_hw *hw =
3108                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3109         struct ixgbe_hw_stats *hw_stats =
3110                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3111         struct ixgbe_macsec_stats *macsec_stats =
3112                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3113                                 dev->data->dev_private);
3114         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3115         unsigned i, stat, count = 0;
3116
3117         count = ixgbe_xstats_calc_num();
3118
3119         if (n < count)
3120                 return count;
3121
3122         total_missed_rx = 0;
3123         total_qbrc = 0;
3124         total_qprc = 0;
3125         total_qprdc = 0;
3126
3127         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3128                         &total_qbrc, &total_qprc, &total_qprdc);
3129
3130         /* If this is a reset xstats is NULL, and we have cleared the
3131          * registers by reading them.
3132          */
3133         if (!xstats)
3134                 return 0;
3135
3136         /* Extended stats from ixgbe_hw_stats */
3137         count = 0;
3138         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3139                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3140                                 rte_ixgbe_stats_strings[i].offset);
3141                 xstats[count].id = count;
3142                 count++;
3143         }
3144
3145         /* MACsec Stats */
3146         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3147                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3148                                 rte_ixgbe_macsec_strings[i].offset);
3149                 xstats[count].id = count;
3150                 count++;
3151         }
3152
3153         /* RX Priority Stats */
3154         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3155                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3156                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3157                                         rte_ixgbe_rxq_strings[stat].offset +
3158                                         (sizeof(uint64_t) * i));
3159                         xstats[count].id = count;
3160                         count++;
3161                 }
3162         }
3163
3164         /* TX Priority Stats */
3165         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3166                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3167                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3168                                         rte_ixgbe_txq_strings[stat].offset +
3169                                         (sizeof(uint64_t) * i));
3170                         xstats[count].id = count;
3171                         count++;
3172                 }
3173         }
3174         return count;
3175 }
3176
3177 static void
3178 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3179 {
3180         struct ixgbe_hw_stats *stats =
3181                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3182         struct ixgbe_macsec_stats *macsec_stats =
3183                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3184                                 dev->data->dev_private);
3185
3186         unsigned count = ixgbe_xstats_calc_num();
3187
3188         /* HW registers are cleared on read */
3189         ixgbe_dev_xstats_get(dev, NULL, count);
3190
3191         /* Reset software totals */
3192         memset(stats, 0, sizeof(*stats));
3193         memset(macsec_stats, 0, sizeof(*macsec_stats));
3194 }
3195
3196 static void
3197 ixgbevf_update_stats(struct rte_eth_dev *dev)
3198 {
3199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3200         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3201                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3202
3203         /* Good Rx packet, include VF loopback */
3204         UPDATE_VF_STAT(IXGBE_VFGPRC,
3205             hw_stats->last_vfgprc, hw_stats->vfgprc);
3206
3207         /* Good Rx octets, include VF loopback */
3208         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3209             hw_stats->last_vfgorc, hw_stats->vfgorc);
3210
3211         /* Good Tx packet, include VF loopback */
3212         UPDATE_VF_STAT(IXGBE_VFGPTC,
3213             hw_stats->last_vfgptc, hw_stats->vfgptc);
3214
3215         /* Good Tx octets, include VF loopback */
3216         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3217             hw_stats->last_vfgotc, hw_stats->vfgotc);
3218
3219         /* Rx Multicst Packet */
3220         UPDATE_VF_STAT(IXGBE_VFMPRC,
3221             hw_stats->last_vfmprc, hw_stats->vfmprc);
3222 }
3223
3224 static int
3225 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3226                        unsigned n)
3227 {
3228         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3229                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3230         unsigned i;
3231
3232         if (n < IXGBEVF_NB_XSTATS)
3233                 return IXGBEVF_NB_XSTATS;
3234
3235         ixgbevf_update_stats(dev);
3236
3237         if (!xstats)
3238                 return 0;
3239
3240         /* Extended stats */
3241         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3242                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3243                         rte_ixgbevf_stats_strings[i].offset);
3244         }
3245
3246         return IXGBEVF_NB_XSTATS;
3247 }
3248
3249 static void
3250 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3251 {
3252         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3253                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3254
3255         ixgbevf_update_stats(dev);
3256
3257         if (stats == NULL)
3258                 return;
3259
3260         stats->ipackets = hw_stats->vfgprc;
3261         stats->ibytes = hw_stats->vfgorc;
3262         stats->opackets = hw_stats->vfgptc;
3263         stats->obytes = hw_stats->vfgotc;
3264 }
3265
3266 static void
3267 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3268 {
3269         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3270                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3271
3272         /* Sync HW register to the last stats */
3273         ixgbevf_dev_stats_get(dev, NULL);
3274
3275         /* reset HW current stats*/
3276         hw_stats->vfgprc = 0;
3277         hw_stats->vfgorc = 0;
3278         hw_stats->vfgptc = 0;
3279         hw_stats->vfgotc = 0;
3280 }
3281
3282 static int
3283 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3284 {
3285         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3286         u16 eeprom_verh, eeprom_verl;
3287         u32 etrack_id;
3288         int ret;
3289
3290         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3291         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3292
3293         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3294         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3295
3296         ret += 1; /* add the size of '\0' */
3297         if (fw_size < (u32)ret)
3298                 return ret;
3299         else
3300                 return 0;
3301 }
3302
3303 static void
3304 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3305 {
3306         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3307         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3308         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3309
3310         dev_info->pci_dev = pci_dev;
3311         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3312         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3313         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3314                 /*
3315                  * When DCB/VT is off, maximum number of queues changes,
3316                  * except for 82598EB, which remains constant.
3317                  */
3318                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3319                                 hw->mac.type != ixgbe_mac_82598EB)
3320                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3321         }
3322         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3323         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3324         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3325         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3326         dev_info->max_vfs = pci_dev->max_vfs;
3327         if (hw->mac.type == ixgbe_mac_82598EB)
3328                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3329         else
3330                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3331         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3332         dev_info->rx_offload_capa =
3333                 DEV_RX_OFFLOAD_VLAN_STRIP |
3334                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3335                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3336                 DEV_RX_OFFLOAD_TCP_CKSUM;
3337
3338         /*
3339          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3340          * mode.
3341          */
3342         if ((hw->mac.type == ixgbe_mac_82599EB ||
3343              hw->mac.type == ixgbe_mac_X540) &&
3344             !RTE_ETH_DEV_SRIOV(dev).active)
3345                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3346
3347         if (hw->mac.type == ixgbe_mac_82599EB ||
3348             hw->mac.type == ixgbe_mac_X540)
3349                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3350
3351         if (hw->mac.type == ixgbe_mac_X550 ||
3352             hw->mac.type == ixgbe_mac_X550EM_x ||
3353             hw->mac.type == ixgbe_mac_X550EM_a)
3354                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3355
3356         dev_info->tx_offload_capa =
3357                 DEV_TX_OFFLOAD_VLAN_INSERT |
3358                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3359                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3360                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3361                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3362                 DEV_TX_OFFLOAD_TCP_TSO;
3363
3364         if (hw->mac.type == ixgbe_mac_82599EB ||
3365             hw->mac.type == ixgbe_mac_X540)
3366                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3367
3368         if (hw->mac.type == ixgbe_mac_X550 ||
3369             hw->mac.type == ixgbe_mac_X550EM_x ||
3370             hw->mac.type == ixgbe_mac_X550EM_a)
3371                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3372
3373         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3374                 .rx_thresh = {
3375                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3376                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3377                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3378                 },
3379                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3380                 .rx_drop_en = 0,
3381         };
3382
3383         dev_info->default_txconf = (struct rte_eth_txconf) {
3384                 .tx_thresh = {
3385                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3386                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3387                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3388                 },
3389                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3390                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3391                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3392                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3393         };
3394
3395         dev_info->rx_desc_lim = rx_desc_lim;
3396         dev_info->tx_desc_lim = tx_desc_lim;
3397
3398         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3399         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3400         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3401
3402         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3403         if (hw->mac.type == ixgbe_mac_X540 ||
3404             hw->mac.type == ixgbe_mac_X540_vf ||
3405             hw->mac.type == ixgbe_mac_X550 ||
3406             hw->mac.type == ixgbe_mac_X550_vf) {
3407                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3408         }
3409 }
3410
3411 static const uint32_t *
3412 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3413 {
3414         static const uint32_t ptypes[] = {
3415                 /* For non-vec functions,
3416                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3417                  * for vec functions,
3418                  * refers to _recv_raw_pkts_vec().
3419                  */
3420                 RTE_PTYPE_L2_ETHER,
3421                 RTE_PTYPE_L3_IPV4,
3422                 RTE_PTYPE_L3_IPV4_EXT,
3423                 RTE_PTYPE_L3_IPV6,
3424                 RTE_PTYPE_L3_IPV6_EXT,
3425                 RTE_PTYPE_L4_SCTP,
3426                 RTE_PTYPE_L4_TCP,
3427                 RTE_PTYPE_L4_UDP,
3428                 RTE_PTYPE_TUNNEL_IP,
3429                 RTE_PTYPE_INNER_L3_IPV6,
3430                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3431                 RTE_PTYPE_INNER_L4_TCP,
3432                 RTE_PTYPE_INNER_L4_UDP,
3433                 RTE_PTYPE_UNKNOWN
3434         };
3435
3436         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3437             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3438             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3439             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3440                 return ptypes;
3441         return NULL;
3442 }
3443
3444 static void
3445 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3446                      struct rte_eth_dev_info *dev_info)
3447 {
3448         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3449         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3450
3451         dev_info->pci_dev = pci_dev;
3452         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3453         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3454         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3455         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3456         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3457         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3458         dev_info->max_vfs = pci_dev->max_vfs;
3459         if (hw->mac.type == ixgbe_mac_82598EB)
3460                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3461         else
3462                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3463         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3464                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3465                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3466                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3467         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3468                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3469                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3470                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3471                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3472                                 DEV_TX_OFFLOAD_TCP_TSO;
3473
3474         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3475                 .rx_thresh = {
3476                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3477                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3478                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3479                 },
3480                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3481                 .rx_drop_en = 0,
3482         };
3483
3484         dev_info->default_txconf = (struct rte_eth_txconf) {
3485                 .tx_thresh = {
3486                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3487                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3488                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3489                 },
3490                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3491                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3492                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3493                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3494         };
3495
3496         dev_info->rx_desc_lim = rx_desc_lim;
3497         dev_info->tx_desc_lim = tx_desc_lim;
3498 }
3499
3500 /* return 0 means link status changed, -1 means not changed */
3501 static int
3502 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3503 {
3504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3505         struct rte_eth_link link, old;
3506         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3507         int link_up;
3508         int diag;
3509
3510         link.link_status = ETH_LINK_DOWN;
3511         link.link_speed = 0;
3512         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3513         memset(&old, 0, sizeof(old));
3514         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3515
3516         hw->mac.get_link_status = true;
3517
3518         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3519         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3520                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3521         else
3522                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3523
3524         if (diag != 0) {
3525                 link.link_speed = ETH_SPEED_NUM_100M;
3526                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3527                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3528                 if (link.link_status == old.link_status)
3529                         return -1;
3530                 return 0;
3531         }
3532
3533         if (link_up == 0) {
3534                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3535                 if (link.link_status == old.link_status)
3536                         return -1;
3537                 return 0;
3538         }
3539         link.link_status = ETH_LINK_UP;
3540         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3541
3542         switch (link_speed) {
3543         default:
3544         case IXGBE_LINK_SPEED_UNKNOWN:
3545                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3546                 link.link_speed = ETH_SPEED_NUM_100M;
3547                 break;
3548
3549         case IXGBE_LINK_SPEED_100_FULL:
3550                 link.link_speed = ETH_SPEED_NUM_100M;
3551                 break;
3552
3553         case IXGBE_LINK_SPEED_1GB_FULL:
3554                 link.link_speed = ETH_SPEED_NUM_1G;
3555                 break;
3556
3557         case IXGBE_LINK_SPEED_10GB_FULL:
3558                 link.link_speed = ETH_SPEED_NUM_10G;
3559                 break;
3560         }
3561         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3562
3563         if (link.link_status == old.link_status)
3564                 return -1;
3565
3566         return 0;
3567 }
3568
3569 static void
3570 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3571 {
3572         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3573         uint32_t fctrl;
3574
3575         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3576         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3577         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3578 }
3579
3580 static void
3581 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3582 {
3583         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3584         uint32_t fctrl;
3585
3586         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3587         fctrl &= (~IXGBE_FCTRL_UPE);
3588         if (dev->data->all_multicast == 1)
3589                 fctrl |= IXGBE_FCTRL_MPE;
3590         else
3591                 fctrl &= (~IXGBE_FCTRL_MPE);
3592         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3593 }
3594
3595 static void
3596 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3597 {
3598         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3599         uint32_t fctrl;
3600
3601         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3602         fctrl |= IXGBE_FCTRL_MPE;
3603         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3604 }
3605
3606 static void
3607 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3608 {
3609         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3610         uint32_t fctrl;
3611
3612         if (dev->data->promiscuous == 1)
3613                 return; /* must remain in all_multicast mode */
3614
3615         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3616         fctrl &= (~IXGBE_FCTRL_MPE);
3617         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3618 }
3619
3620 /**
3621  * It clears the interrupt causes and enables the interrupt.
3622  * It will be called once only during nic initialized.
3623  *
3624  * @param dev
3625  *  Pointer to struct rte_eth_dev.
3626  *
3627  * @return
3628  *  - On success, zero.
3629  *  - On failure, a negative value.
3630  */
3631 static int
3632 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3633 {
3634         struct ixgbe_interrupt *intr =
3635                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3636
3637         ixgbe_dev_link_status_print(dev);
3638         intr->mask |= IXGBE_EICR_LSC;
3639
3640         return 0;
3641 }
3642
3643 /**
3644  * It clears the interrupt causes and enables the interrupt.
3645  * It will be called once only during nic initialized.
3646  *
3647  * @param dev
3648  *  Pointer to struct rte_eth_dev.
3649  *
3650  * @return
3651  *  - On success, zero.
3652  *  - On failure, a negative value.
3653  */
3654 static int
3655 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3656 {
3657         struct ixgbe_interrupt *intr =
3658                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3659
3660         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3661
3662         return 0;
3663 }
3664
3665 /**
3666  * It clears the interrupt causes and enables the interrupt.
3667  * It will be called once only during nic initialized.
3668  *
3669  * @param dev
3670  *  Pointer to struct rte_eth_dev.
3671  *
3672  * @return
3673  *  - On success, zero.
3674  *  - On failure, a negative value.
3675  */
3676 static int
3677 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3678 {
3679         struct ixgbe_interrupt *intr =
3680                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3681
3682         intr->mask |= IXGBE_EICR_LINKSEC;
3683
3684         return 0;
3685 }
3686
3687 /*
3688  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3689  *
3690  * @param dev
3691  *  Pointer to struct rte_eth_dev.
3692  *
3693  * @return
3694  *  - On success, zero.
3695  *  - On failure, a negative value.
3696  */
3697 static int
3698 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3699 {
3700         uint32_t eicr;
3701         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3702         struct ixgbe_interrupt *intr =
3703                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3704
3705         /* clear all cause mask */
3706         ixgbe_disable_intr(hw);
3707
3708         /* read-on-clear nic registers here */
3709         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3710         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3711
3712         intr->flags = 0;
3713
3714         /* set flag for async link update */
3715         if (eicr & IXGBE_EICR_LSC)
3716                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3717
3718         if (eicr & IXGBE_EICR_MAILBOX)
3719                 intr->flags |= IXGBE_FLAG_MAILBOX;
3720
3721         if (eicr & IXGBE_EICR_LINKSEC)
3722                 intr->flags |= IXGBE_FLAG_MACSEC;
3723
3724         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3725             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3726             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3727                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3728
3729         return 0;
3730 }
3731
3732 /**
3733  * It gets and then prints the link status.
3734  *
3735  * @param dev
3736  *  Pointer to struct rte_eth_dev.
3737  *
3738  * @return
3739  *  - On success, zero.
3740  *  - On failure, a negative value.
3741  */
3742 static void
3743 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3744 {
3745         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3746         struct rte_eth_link link;
3747
3748         memset(&link, 0, sizeof(link));
3749         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3750         if (link.link_status) {
3751                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3752                                         (int)(dev->data->port_id),
3753                                         (unsigned)link.link_speed,
3754                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3755                                         "full-duplex" : "half-duplex");
3756         } else {
3757                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3758                                 (int)(dev->data->port_id));
3759         }
3760         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3761                                 pci_dev->addr.domain,
3762                                 pci_dev->addr.bus,
3763                                 pci_dev->addr.devid,
3764                                 pci_dev->addr.function);
3765 }
3766
3767 /*
3768  * It executes link_update after knowing an interrupt occurred.
3769  *
3770  * @param dev
3771  *  Pointer to struct rte_eth_dev.
3772  *
3773  * @return
3774  *  - On success, zero.
3775  *  - On failure, a negative value.
3776  */
3777 static int
3778 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3779                            struct rte_intr_handle *intr_handle)
3780 {
3781         struct ixgbe_interrupt *intr =
3782                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3783         int64_t timeout;
3784         struct rte_eth_link link;
3785         int intr_enable_delay = false;
3786         struct ixgbe_hw *hw =
3787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3788
3789         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3790
3791         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3792                 ixgbe_pf_mbx_process(dev);
3793                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3794         }
3795
3796         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3797                 ixgbe_handle_lasi(hw);
3798                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3799         }
3800
3801         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3802                 /* get the link status before link update, for predicting later */
3803                 memset(&link, 0, sizeof(link));
3804                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3805
3806                 ixgbe_dev_link_update(dev, 0);
3807
3808                 /* likely to up */
3809                 if (!link.link_status)
3810                         /* handle it 1 sec later, wait it being stable */
3811                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3812                 /* likely to down */
3813                 else
3814                         /* handle it 4 sec later, wait it being stable */
3815                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3816
3817                 ixgbe_dev_link_status_print(dev);
3818
3819                 intr_enable_delay = true;
3820         }
3821
3822         if (intr_enable_delay) {
3823                 if (rte_eal_alarm_set(timeout * 1000,
3824                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3825                         PMD_DRV_LOG(ERR, "Error setting alarm");
3826         } else {
3827                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3828                 ixgbe_enable_intr(dev);
3829                 rte_intr_enable(intr_handle);
3830         }
3831
3832
3833         return 0;
3834 }
3835
3836 /**
3837  * Interrupt handler which shall be registered for alarm callback for delayed
3838  * handling specific interrupt to wait for the stable nic state. As the
3839  * NIC interrupt state is not stable for ixgbe after link is just down,
3840  * it needs to wait 4 seconds to get the stable status.
3841  *
3842  * @param handle
3843  *  Pointer to interrupt handle.
3844  * @param param
3845  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3846  *
3847  * @return
3848  *  void
3849  */
3850 static void
3851 ixgbe_dev_interrupt_delayed_handler(void *param)
3852 {
3853         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3854         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3855         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3856         struct ixgbe_interrupt *intr =
3857                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3858         struct ixgbe_hw *hw =
3859                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3860         uint32_t eicr;
3861
3862         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3863         if (eicr & IXGBE_EICR_MAILBOX)
3864                 ixgbe_pf_mbx_process(dev);
3865
3866         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3867                 ixgbe_handle_lasi(hw);
3868                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3869         }
3870
3871         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3872                 ixgbe_dev_link_update(dev, 0);
3873                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3874                 ixgbe_dev_link_status_print(dev);
3875                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3876         }
3877
3878         if (intr->flags & IXGBE_FLAG_MACSEC) {
3879                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3880                                               NULL);
3881                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3882         }
3883
3884         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3885         ixgbe_enable_intr(dev);
3886         rte_intr_enable(intr_handle);
3887 }
3888
3889 /**
3890  * Interrupt handler triggered by NIC  for handling
3891  * specific interrupt.
3892  *
3893  * @param handle
3894  *  Pointer to interrupt handle.
3895  * @param param
3896  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3897  *
3898  * @return
3899  *  void
3900  */
3901 static void
3902 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3903                             void *param)
3904 {
3905         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3906
3907         ixgbe_dev_interrupt_get_status(dev);
3908         ixgbe_dev_interrupt_action(dev, handle);
3909 }
3910
3911 static int
3912 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3913 {
3914         struct ixgbe_hw *hw;
3915
3916         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3918 }
3919
3920 static int
3921 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3922 {
3923         struct ixgbe_hw *hw;
3924
3925         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3926         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3927 }
3928
3929 static int
3930 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3931 {
3932         struct ixgbe_hw *hw;
3933         uint32_t mflcn_reg;
3934         uint32_t fccfg_reg;
3935         int rx_pause;
3936         int tx_pause;
3937
3938         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939
3940         fc_conf->pause_time = hw->fc.pause_time;
3941         fc_conf->high_water = hw->fc.high_water[0];
3942         fc_conf->low_water = hw->fc.low_water[0];
3943         fc_conf->send_xon = hw->fc.send_xon;
3944         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3945
3946         /*
3947          * Return rx_pause status according to actual setting of
3948          * MFLCN register.
3949          */
3950         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3951         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3952                 rx_pause = 1;
3953         else
3954                 rx_pause = 0;
3955
3956         /*
3957          * Return tx_pause status according to actual setting of
3958          * FCCFG register.
3959          */
3960         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3961         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3962                 tx_pause = 1;
3963         else
3964                 tx_pause = 0;
3965
3966         if (rx_pause && tx_pause)
3967                 fc_conf->mode = RTE_FC_FULL;
3968         else if (rx_pause)
3969                 fc_conf->mode = RTE_FC_RX_PAUSE;
3970         else if (tx_pause)
3971                 fc_conf->mode = RTE_FC_TX_PAUSE;
3972         else
3973                 fc_conf->mode = RTE_FC_NONE;
3974
3975         return 0;
3976 }
3977
3978 static int
3979 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3980 {
3981         struct ixgbe_hw *hw;
3982         int err;
3983         uint32_t rx_buf_size;
3984         uint32_t max_high_water;
3985         uint32_t mflcn;
3986         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3987                 ixgbe_fc_none,
3988                 ixgbe_fc_rx_pause,
3989                 ixgbe_fc_tx_pause,
3990                 ixgbe_fc_full
3991         };
3992
3993         PMD_INIT_FUNC_TRACE();
3994
3995         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3996         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3997         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3998
3999         /*
4000          * At least reserve one Ethernet frame for watermark
4001          * high_water/low_water in kilo bytes for ixgbe
4002          */
4003         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4004         if ((fc_conf->high_water > max_high_water) ||
4005                 (fc_conf->high_water < fc_conf->low_water)) {
4006                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4007                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4008                 return -EINVAL;
4009         }
4010
4011         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4012         hw->fc.pause_time     = fc_conf->pause_time;
4013         hw->fc.high_water[0]  = fc_conf->high_water;
4014         hw->fc.low_water[0]   = fc_conf->low_water;
4015         hw->fc.send_xon       = fc_conf->send_xon;
4016         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4017
4018         err = ixgbe_fc_enable(hw);
4019
4020         /* Not negotiated is not an error case */
4021         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4022
4023                 /* check if we want to forward MAC frames - driver doesn't have native
4024                  * capability to do that, so we'll write the registers ourselves */
4025
4026                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4027
4028                 /* set or clear MFLCN.PMCF bit depending on configuration */
4029                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4030                         mflcn |= IXGBE_MFLCN_PMCF;
4031                 else
4032                         mflcn &= ~IXGBE_MFLCN_PMCF;
4033
4034                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4035                 IXGBE_WRITE_FLUSH(hw);
4036
4037                 return 0;
4038         }
4039
4040         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4041         return -EIO;
4042 }
4043
4044 /**
4045  *  ixgbe_pfc_enable_generic - Enable flow control
4046  *  @hw: pointer to hardware structure
4047  *  @tc_num: traffic class number
4048  *  Enable flow control according to the current settings.
4049  */
4050 static int
4051 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4052 {
4053         int ret_val = 0;
4054         uint32_t mflcn_reg, fccfg_reg;
4055         uint32_t reg;
4056         uint32_t fcrtl, fcrth;
4057         uint8_t i;
4058         uint8_t nb_rx_en;
4059
4060         /* Validate the water mark configuration */
4061         if (!hw->fc.pause_time) {
4062                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4063                 goto out;
4064         }
4065
4066         /* Low water mark of zero causes XOFF floods */
4067         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4068                  /* High/Low water can not be 0 */
4069                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4070                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4071                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4072                         goto out;
4073                 }
4074
4075                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4076                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4077                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4078                         goto out;
4079                 }
4080         }
4081         /* Negotiate the fc mode to use */
4082         ixgbe_fc_autoneg(hw);
4083
4084         /* Disable any previous flow control settings */
4085         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4086         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4087
4088         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4089         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4090
4091         switch (hw->fc.current_mode) {
4092         case ixgbe_fc_none:
4093                 /*
4094                  * If the count of enabled RX Priority Flow control >1,
4095                  * and the TX pause can not be disabled
4096                  */
4097                 nb_rx_en = 0;
4098                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4099                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4100                         if (reg & IXGBE_FCRTH_FCEN)
4101                                 nb_rx_en++;
4102                 }
4103                 if (nb_rx_en > 1)
4104                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4105                 break;
4106         case ixgbe_fc_rx_pause:
4107                 /*
4108                  * Rx Flow control is enabled and Tx Flow control is
4109                  * disabled by software override. Since there really
4110                  * isn't a way to advertise that we are capable of RX
4111                  * Pause ONLY, we will advertise that we support both
4112                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4113                  * disable the adapter's ability to send PAUSE frames.
4114                  */
4115                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4116                 /*
4117                  * If the count of enabled RX Priority Flow control >1,
4118                  * and the TX pause can not be disabled
4119                  */
4120                 nb_rx_en = 0;
4121                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4122                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4123                         if (reg & IXGBE_FCRTH_FCEN)
4124                                 nb_rx_en++;
4125                 }
4126                 if (nb_rx_en > 1)
4127                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4128                 break;
4129         case ixgbe_fc_tx_pause:
4130                 /*
4131                  * Tx Flow control is enabled, and Rx Flow control is
4132                  * disabled by software override.
4133                  */
4134                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4135                 break;
4136         case ixgbe_fc_full:
4137                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4138                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4139                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4140                 break;
4141         default:
4142                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4143                 ret_val = IXGBE_ERR_CONFIG;
4144                 goto out;
4145         }
4146
4147         /* Set 802.3x based flow control settings. */
4148         mflcn_reg |= IXGBE_MFLCN_DPF;
4149         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4150         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4151
4152         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4153         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4154                 hw->fc.high_water[tc_num]) {
4155                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4156                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4157                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4158         } else {
4159                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4160                 /*
4161                  * In order to prevent Tx hangs when the internal Tx
4162                  * switch is enabled we must set the high water mark
4163                  * to the maximum FCRTH value.  This allows the Tx
4164                  * switch to function even under heavy Rx workloads.
4165                  */
4166                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4167         }
4168         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4169
4170         /* Configure pause time (2 TCs per register) */
4171         reg = hw->fc.pause_time * 0x00010001;
4172         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4173                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4174
4175         /* Configure flow control refresh threshold value */
4176         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4177
4178 out:
4179         return ret_val;
4180 }
4181
4182 static int
4183 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4184 {
4185         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4186         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4187
4188         if (hw->mac.type != ixgbe_mac_82598EB) {
4189                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4190         }
4191         return ret_val;
4192 }
4193
4194 static int
4195 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4196 {
4197         int err;
4198         uint32_t rx_buf_size;
4199         uint32_t max_high_water;
4200         uint8_t tc_num;
4201         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4202         struct ixgbe_hw *hw =
4203                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4204         struct ixgbe_dcb_config *dcb_config =
4205                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4206
4207         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4208                 ixgbe_fc_none,
4209                 ixgbe_fc_rx_pause,
4210                 ixgbe_fc_tx_pause,
4211                 ixgbe_fc_full
4212         };
4213
4214         PMD_INIT_FUNC_TRACE();
4215
4216         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4217         tc_num = map[pfc_conf->priority];
4218         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4219         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4220         /*
4221          * At least reserve one Ethernet frame for watermark
4222          * high_water/low_water in kilo bytes for ixgbe
4223          */
4224         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4225         if ((pfc_conf->fc.high_water > max_high_water) ||
4226             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4227                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4228                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4229                 return -EINVAL;
4230         }
4231
4232         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4233         hw->fc.pause_time = pfc_conf->fc.pause_time;
4234         hw->fc.send_xon = pfc_conf->fc.send_xon;
4235         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4236         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4237
4238         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4239
4240         /* Not negotiated is not an error case */
4241         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4242                 return 0;
4243
4244         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4245         return -EIO;
4246 }
4247
4248 static int
4249 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4250                           struct rte_eth_rss_reta_entry64 *reta_conf,
4251                           uint16_t reta_size)
4252 {
4253         uint16_t i, sp_reta_size;
4254         uint8_t j, mask;
4255         uint32_t reta, r;
4256         uint16_t idx, shift;
4257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4258         uint32_t reta_reg;
4259
4260         PMD_INIT_FUNC_TRACE();
4261
4262         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4263                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4264                         "NIC.");
4265                 return -ENOTSUP;
4266         }
4267
4268         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4269         if (reta_size != sp_reta_size) {
4270                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4271                         "(%d) doesn't match the number hardware can supported "
4272                         "(%d)\n", reta_size, sp_reta_size);
4273                 return -EINVAL;
4274         }
4275
4276         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4277                 idx = i / RTE_RETA_GROUP_SIZE;
4278                 shift = i % RTE_RETA_GROUP_SIZE;
4279                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4280                                                 IXGBE_4_BIT_MASK);
4281                 if (!mask)
4282                         continue;
4283                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4284                 if (mask == IXGBE_4_BIT_MASK)
4285                         r = 0;
4286                 else
4287                         r = IXGBE_READ_REG(hw, reta_reg);
4288                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4289                         if (mask & (0x1 << j))
4290                                 reta |= reta_conf[idx].reta[shift + j] <<
4291                                                         (CHAR_BIT * j);
4292                         else
4293                                 reta |= r & (IXGBE_8_BIT_MASK <<
4294                                                 (CHAR_BIT * j));
4295                 }
4296                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4297         }
4298
4299         return 0;
4300 }
4301
4302 static int
4303 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4304                          struct rte_eth_rss_reta_entry64 *reta_conf,
4305                          uint16_t reta_size)
4306 {
4307         uint16_t i, sp_reta_size;
4308         uint8_t j, mask;
4309         uint32_t reta;
4310         uint16_t idx, shift;
4311         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4312         uint32_t reta_reg;
4313
4314         PMD_INIT_FUNC_TRACE();
4315         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4316         if (reta_size != sp_reta_size) {
4317                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4318                         "(%d) doesn't match the number hardware can supported "
4319                         "(%d)\n", reta_size, sp_reta_size);
4320                 return -EINVAL;
4321         }
4322
4323         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4324                 idx = i / RTE_RETA_GROUP_SIZE;
4325                 shift = i % RTE_RETA_GROUP_SIZE;
4326                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4327                                                 IXGBE_4_BIT_MASK);
4328                 if (!mask)
4329                         continue;
4330
4331                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4332                 reta = IXGBE_READ_REG(hw, reta_reg);
4333                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4334                         if (mask & (0x1 << j))
4335                                 reta_conf[idx].reta[shift + j] =
4336                                         ((reta >> (CHAR_BIT * j)) &
4337                                                 IXGBE_8_BIT_MASK);
4338                 }
4339         }
4340
4341         return 0;
4342 }
4343
4344 static void
4345 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4346                                 uint32_t index, uint32_t pool)
4347 {
4348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4349         uint32_t enable_addr = 1;
4350
4351         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4352 }
4353
4354 static void
4355 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4356 {
4357         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358
4359         ixgbe_clear_rar(hw, index);
4360 }
4361
4362 static void
4363 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4364 {
4365         ixgbe_remove_rar(dev, 0);
4366
4367         ixgbe_add_rar(dev, addr, 0, 0);
4368 }
4369
4370 static int
4371 is_ixgbe_pmd(const char *driver_name)
4372 {
4373         if (!strstr(driver_name, "ixgbe"))
4374                 return -ENOTSUP;
4375
4376         if (strstr(driver_name, "ixgbe_vf"))
4377                 return -ENOTSUP;
4378
4379         return 0;
4380 }
4381
4382 int
4383 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4384                 struct ether_addr *mac_addr)
4385 {
4386         struct ixgbe_hw *hw;
4387         struct ixgbe_vf_info *vfinfo;
4388         int rar_entry;
4389         uint8_t *new_mac = (uint8_t *)(mac_addr);
4390         struct rte_eth_dev *dev;
4391         struct rte_eth_dev_info dev_info;
4392
4393         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4394
4395         dev = &rte_eth_devices[port];
4396         rte_eth_dev_info_get(port, &dev_info);
4397
4398         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4399                 return -ENOTSUP;
4400
4401         if (vf >= dev_info.max_vfs)
4402                 return -EINVAL;
4403
4404         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4405         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4406         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4407
4408         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4409                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4410                                 ETHER_ADDR_LEN);
4411                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4412                                 IXGBE_RAH_AV);
4413         }
4414         return -EINVAL;
4415 }
4416
4417 static int
4418 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4419 {
4420         uint32_t hlreg0;
4421         uint32_t maxfrs;
4422         struct ixgbe_hw *hw;
4423         struct rte_eth_dev_info dev_info;
4424         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4425
4426         ixgbe_dev_info_get(dev, &dev_info);
4427
4428         /* check that mtu is within the allowed range */
4429         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4430                 return -EINVAL;
4431
4432         /* refuse mtu that requires the support of scattered packets when this
4433          * feature has not been enabled before.
4434          */
4435         if (!dev->data->scattered_rx &&
4436             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4437              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4438                 return -EINVAL;
4439
4440         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4441         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4442
4443         /* switch to jumbo mode if needed */
4444         if (frame_size > ETHER_MAX_LEN) {
4445                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4446                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4447         } else {
4448                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4449                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4450         }
4451         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4452
4453         /* update max frame size */
4454         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4455
4456         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4457         maxfrs &= 0x0000FFFF;
4458         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4459         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4460
4461         return 0;
4462 }
4463
4464 /*
4465  * Virtual Function operations
4466  */
4467 static void
4468 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4469 {
4470         PMD_INIT_FUNC_TRACE();
4471
4472         /* Clear interrupt mask to stop from interrupts being generated */
4473         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4474
4475         IXGBE_WRITE_FLUSH(hw);
4476 }
4477
4478 static void
4479 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4480 {
4481         PMD_INIT_FUNC_TRACE();
4482
4483         /* VF enable interrupt autoclean */
4484         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4485         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4486         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4487
4488         IXGBE_WRITE_FLUSH(hw);
4489 }
4490
4491 static int
4492 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4493 {
4494         struct rte_eth_conf *conf = &dev->data->dev_conf;
4495         struct ixgbe_adapter *adapter =
4496                         (struct ixgbe_adapter *)dev->data->dev_private;
4497
4498         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4499                      dev->data->port_id);
4500
4501         /*
4502          * VF has no ability to enable/disable HW CRC
4503          * Keep the persistent behavior the same as Host PF
4504          */
4505 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4506         if (!conf->rxmode.hw_strip_crc) {
4507                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4508                 conf->rxmode.hw_strip_crc = 1;
4509         }
4510 #else
4511         if (conf->rxmode.hw_strip_crc) {
4512                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4513                 conf->rxmode.hw_strip_crc = 0;
4514         }
4515 #endif
4516
4517         /*
4518          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4519          * allocation or vector Rx preconditions we will reset it.
4520          */
4521         adapter->rx_bulk_alloc_allowed = true;
4522         adapter->rx_vec_allowed = true;
4523
4524         return 0;
4525 }
4526
4527 static int
4528 ixgbevf_dev_start(struct rte_eth_dev *dev)
4529 {
4530         struct ixgbe_hw *hw =
4531                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4532         uint32_t intr_vector = 0;
4533         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4534         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4535
4536         int err, mask = 0;
4537
4538         PMD_INIT_FUNC_TRACE();
4539
4540         hw->mac.ops.reset_hw(hw);
4541         hw->mac.get_link_status = true;
4542
4543         /* negotiate mailbox API version to use with the PF. */
4544         ixgbevf_negotiate_api(hw);
4545
4546         ixgbevf_dev_tx_init(dev);
4547
4548         /* This can fail when allocating mbufs for descriptor rings */
4549         err = ixgbevf_dev_rx_init(dev);
4550         if (err) {
4551                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4552                 ixgbe_dev_clear_queues(dev);
4553                 return err;
4554         }
4555
4556         /* Set vfta */
4557         ixgbevf_set_vfta_all(dev, 1);
4558
4559         /* Set HW strip */
4560         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4561                 ETH_VLAN_EXTEND_MASK;
4562         ixgbevf_vlan_offload_set(dev, mask);
4563
4564         ixgbevf_dev_rxtx_start(dev);
4565
4566         /* check and configure queue intr-vector mapping */
4567         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4568                 intr_vector = dev->data->nb_rx_queues;
4569                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4570                         return -1;
4571         }
4572
4573         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4574                 intr_handle->intr_vec =
4575                         rte_zmalloc("intr_vec",
4576                                     dev->data->nb_rx_queues * sizeof(int), 0);
4577                 if (intr_handle->intr_vec == NULL) {
4578                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4579                                      " intr_vec\n", dev->data->nb_rx_queues);
4580                         return -ENOMEM;
4581                 }
4582         }
4583         ixgbevf_configure_msix(dev);
4584
4585         rte_intr_enable(intr_handle);
4586
4587         /* Re-enable interrupt for VF */
4588         ixgbevf_intr_enable(hw);
4589
4590         return 0;
4591 }
4592
4593 static void
4594 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4595 {
4596         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4597         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4598         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4599
4600         PMD_INIT_FUNC_TRACE();
4601
4602         ixgbevf_intr_disable(hw);
4603
4604         hw->adapter_stopped = 1;
4605         ixgbe_stop_adapter(hw);
4606
4607         /*
4608           * Clear what we set, but we still keep shadow_vfta to
4609           * restore after device starts
4610           */
4611         ixgbevf_set_vfta_all(dev, 0);
4612
4613         /* Clear stored conf */
4614         dev->data->scattered_rx = 0;
4615
4616         ixgbe_dev_clear_queues(dev);
4617
4618         /* Clean datapath event and queue/vec mapping */
4619         rte_intr_efd_disable(intr_handle);
4620         if (intr_handle->intr_vec != NULL) {
4621                 rte_free(intr_handle->intr_vec);
4622                 intr_handle->intr_vec = NULL;
4623         }
4624 }
4625
4626 static void
4627 ixgbevf_dev_close(struct rte_eth_dev *dev)
4628 {
4629         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4630
4631         PMD_INIT_FUNC_TRACE();
4632
4633         ixgbe_reset_hw(hw);
4634
4635         ixgbevf_dev_stop(dev);
4636
4637         ixgbe_dev_free_queues(dev);
4638
4639         /**
4640          * Remove the VF MAC address ro ensure
4641          * that the VF traffic goes to the PF
4642          * after stop, close and detach of the VF
4643          **/
4644         ixgbevf_remove_mac_addr(dev, 0);
4645 }
4646
4647 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4648 {
4649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4650         struct ixgbe_vfta *shadow_vfta =
4651                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4652         int i = 0, j = 0, vfta = 0, mask = 1;
4653
4654         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4655                 vfta = shadow_vfta->vfta[i];
4656                 if (vfta) {
4657                         mask = 1;
4658                         for (j = 0; j < 32; j++) {
4659                                 if (vfta & mask)
4660                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4661                                                        on, false);
4662                                 mask <<= 1;
4663                         }
4664                 }
4665         }
4666
4667 }
4668
4669 static int
4670 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4671 {
4672         struct ixgbe_hw *hw =
4673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4674         struct ixgbe_vfta *shadow_vfta =
4675                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4676         uint32_t vid_idx = 0;
4677         uint32_t vid_bit = 0;
4678         int ret = 0;
4679
4680         PMD_INIT_FUNC_TRACE();
4681
4682         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4683         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4684         if (ret) {
4685                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4686                 return ret;
4687         }
4688         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4689         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4690
4691         /* Save what we set and retore it after device reset */
4692         if (on)
4693                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4694         else
4695                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4696
4697         return 0;
4698 }
4699
4700 static void
4701 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4702 {
4703         struct ixgbe_hw *hw =
4704                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4705         uint32_t ctrl;
4706
4707         PMD_INIT_FUNC_TRACE();
4708
4709         if (queue >= hw->mac.max_rx_queues)
4710                 return;
4711
4712         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4713         if (on)
4714                 ctrl |= IXGBE_RXDCTL_VME;
4715         else
4716                 ctrl &= ~IXGBE_RXDCTL_VME;
4717         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4718
4719         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4720 }
4721
4722 static void
4723 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4724 {
4725         struct ixgbe_hw *hw =
4726                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4727         uint16_t i;
4728         int on = 0;
4729
4730         /* VF function only support hw strip feature, others are not support */
4731         if (mask & ETH_VLAN_STRIP_MASK) {
4732                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4733
4734                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4735                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4736         }
4737 }
4738
4739 static int
4740 ixgbe_vt_check(struct ixgbe_hw *hw)
4741 {
4742         uint32_t reg_val;
4743
4744         /* if Virtualization Technology is enabled */
4745         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4746         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4747                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4748                 return -1;
4749         }
4750
4751         return 0;
4752 }
4753
4754 static uint32_t
4755 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4756 {
4757         uint32_t vector = 0;
4758
4759         switch (hw->mac.mc_filter_type) {
4760         case 0:   /* use bits [47:36] of the address */
4761                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4762                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4763                 break;
4764         case 1:   /* use bits [46:35] of the address */
4765                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4766                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4767                 break;
4768         case 2:   /* use bits [45:34] of the address */
4769                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4770                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4771                 break;
4772         case 3:   /* use bits [43:32] of the address */
4773                 vector = ((uc_addr->addr_bytes[4]) |
4774                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4775                 break;
4776         default:  /* Invalid mc_filter_type */
4777                 break;
4778         }
4779
4780         /* vector can only be 12-bits or boundary will be exceeded */
4781         vector &= 0xFFF;
4782         return vector;
4783 }
4784
4785 static int
4786 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4787                         uint8_t on)
4788 {
4789         uint32_t vector;
4790         uint32_t uta_idx;
4791         uint32_t reg_val;
4792         uint32_t uta_shift;
4793         uint32_t rc;
4794         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4795         const uint32_t ixgbe_uta_bit_shift = 5;
4796         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4797         const uint32_t bit1 = 0x1;
4798
4799         struct ixgbe_hw *hw =
4800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4801         struct ixgbe_uta_info *uta_info =
4802                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4803
4804         /* The UTA table only exists on 82599 hardware and newer */
4805         if (hw->mac.type < ixgbe_mac_82599EB)
4806                 return -ENOTSUP;
4807
4808         vector = ixgbe_uta_vector(hw, mac_addr);
4809         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4810         uta_shift = vector & ixgbe_uta_bit_mask;
4811
4812         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4813         if (rc == on)
4814                 return 0;
4815
4816         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4817         if (on) {
4818                 uta_info->uta_in_use++;
4819                 reg_val |= (bit1 << uta_shift);
4820                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4821         } else {
4822                 uta_info->uta_in_use--;
4823                 reg_val &= ~(bit1 << uta_shift);
4824                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4825         }
4826
4827         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4828
4829         if (uta_info->uta_in_use > 0)
4830                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4831                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4832         else
4833                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4834
4835         return 0;
4836 }
4837
4838 static int
4839 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4840 {
4841         int i;
4842         struct ixgbe_hw *hw =
4843                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4844         struct ixgbe_uta_info *uta_info =
4845                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4846
4847         /* The UTA table only exists on 82599 hardware and newer */
4848         if (hw->mac.type < ixgbe_mac_82599EB)
4849                 return -ENOTSUP;
4850
4851         if (on) {
4852                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4853                         uta_info->uta_shadow[i] = ~0;
4854                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4855                 }
4856         } else {
4857                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4858                         uta_info->uta_shadow[i] = 0;
4859                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4860                 }
4861         }
4862         return 0;
4863
4864 }
4865
4866 uint32_t
4867 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4868 {
4869         uint32_t new_val = orig_val;
4870
4871         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4872                 new_val |= IXGBE_VMOLR_AUPE;
4873         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4874                 new_val |= IXGBE_VMOLR_ROMPE;
4875         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4876                 new_val |= IXGBE_VMOLR_ROPE;
4877         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4878                 new_val |= IXGBE_VMOLR_BAM;
4879         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4880                 new_val |= IXGBE_VMOLR_MPE;
4881
4882         return new_val;
4883 }
4884
4885
4886 int
4887 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4888 {
4889         struct ixgbe_hw *hw;
4890         struct ixgbe_mac_info *mac;
4891         struct rte_eth_dev *dev;
4892         struct rte_eth_dev_info dev_info;
4893
4894         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4895
4896         dev = &rte_eth_devices[port];
4897         rte_eth_dev_info_get(port, &dev_info);
4898
4899         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4900                 return -ENOTSUP;
4901
4902         if (vf >= dev_info.max_vfs)
4903                 return -EINVAL;
4904
4905         if (on > 1)
4906                 return -EINVAL;
4907
4908         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4909         mac = &hw->mac;
4910
4911         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4912
4913         return 0;
4914 }
4915
4916 int
4917 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4918 {
4919         struct ixgbe_hw *hw;
4920         struct ixgbe_mac_info *mac;
4921         struct rte_eth_dev *dev;
4922         struct rte_eth_dev_info dev_info;
4923
4924         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4925
4926         dev = &rte_eth_devices[port];
4927         rte_eth_dev_info_get(port, &dev_info);
4928
4929         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4930                 return -ENOTSUP;
4931
4932         if (vf >= dev_info.max_vfs)
4933                 return -EINVAL;
4934
4935         if (on > 1)
4936                 return -EINVAL;
4937
4938         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939         mac = &hw->mac;
4940         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4941
4942         return 0;
4943 }
4944
4945 int
4946 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4947 {
4948         struct ixgbe_hw *hw;
4949         uint32_t ctrl;
4950         struct rte_eth_dev *dev;
4951         struct rte_eth_dev_info dev_info;
4952
4953         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4954
4955         dev = &rte_eth_devices[port];
4956         rte_eth_dev_info_get(port, &dev_info);
4957
4958         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4959                 return -ENOTSUP;
4960
4961         if (vf >= dev_info.max_vfs)
4962                 return -EINVAL;
4963
4964         if (vlan_id > ETHER_MAX_VLAN_ID)
4965                 return -EINVAL;
4966
4967         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4968         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4969         if (vlan_id) {
4970                 ctrl = vlan_id;
4971                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4972         } else {
4973                 ctrl = 0;
4974         }
4975
4976         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4977
4978         return 0;
4979 }
4980
4981 int
4982 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4983 {
4984         struct ixgbe_hw *hw;
4985         uint32_t ctrl;
4986         struct rte_eth_dev *dev;
4987         struct rte_eth_dev_info dev_info;
4988
4989         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4990
4991         dev = &rte_eth_devices[port];
4992         rte_eth_dev_info_get(port, &dev_info);
4993
4994         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4995                 return -ENOTSUP;
4996
4997         if (on > 1)
4998                 return -EINVAL;
4999
5000         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5001         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5002         /* enable or disable VMDQ loopback */
5003         if (on)
5004                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5005         else
5006                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5007
5008         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5009
5010         return 0;
5011 }
5012
5013 int
5014 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5015 {
5016         struct ixgbe_hw *hw;
5017         uint32_t reg_value;
5018         int i;
5019         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5020         struct rte_eth_dev *dev;
5021         struct rte_eth_dev_info dev_info;
5022
5023         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5024
5025         dev = &rte_eth_devices[port];
5026         rte_eth_dev_info_get(port, &dev_info);
5027
5028         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5029                 return -ENOTSUP;
5030
5031         if (on > 1)
5032                 return -EINVAL;
5033
5034         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5035         for (i = 0; i <= num_queues; i++) {
5036                 reg_value = IXGBE_QDE_WRITE |
5037                                 (i << IXGBE_QDE_IDX_SHIFT) |
5038                                 (on & IXGBE_QDE_ENABLE);
5039                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5040         }
5041
5042         return 0;
5043 }
5044
5045 int
5046 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5047 {
5048         struct ixgbe_hw *hw;
5049         uint32_t reg_value;
5050         struct rte_eth_dev *dev;
5051         struct rte_eth_dev_info dev_info;
5052
5053         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5054
5055         dev = &rte_eth_devices[port];
5056         rte_eth_dev_info_get(port, &dev_info);
5057
5058         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5059                 return -ENOTSUP;
5060
5061         /* only support VF's 0 to 63 */
5062         if ((vf >= dev_info.max_vfs) || (vf > 63))
5063                 return -EINVAL;
5064
5065         if (on > 1)
5066                 return -EINVAL;
5067
5068         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5070         if (on)
5071                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5072         else
5073                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5074
5075         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5076
5077         return 0;
5078 }
5079
5080 int
5081 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5082 {
5083         struct rte_eth_dev *dev;
5084         struct rte_eth_dev_info dev_info;
5085         uint16_t queues_per_pool;
5086         uint32_t q;
5087
5088         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5089
5090         dev = &rte_eth_devices[port];
5091         rte_eth_dev_info_get(port, &dev_info);
5092
5093         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5094                 return -ENOTSUP;
5095
5096         if (vf >= dev_info.max_vfs)
5097                 return -EINVAL;
5098
5099         if (on > 1)
5100                 return -EINVAL;
5101
5102         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5103
5104         /* The PF has 128 queue pairs and in SRIOV configuration
5105          * those queues will be assigned to VF's, so RXDCTL
5106          * registers will be dealing with queues which will be
5107          * assigned to VF's.
5108          * Let's say we have SRIOV configured with 31 VF's then the
5109          * first 124 queues 0-123 will be allocated to VF's and only
5110          * the last 4 queues 123-127 will be assigned to the PF.
5111          */
5112
5113         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5114
5115         for (q = 0; q < queues_per_pool; q++)
5116                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5117                                 q + vf * queues_per_pool, on);
5118         return 0;
5119 }
5120
5121 int
5122 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5123 {
5124         int val = 0;
5125         struct rte_eth_dev *dev;
5126         struct rte_eth_dev_info dev_info;
5127         struct ixgbe_hw *hw;
5128         uint32_t vmolr;
5129
5130         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5131
5132         dev = &rte_eth_devices[port];
5133         rte_eth_dev_info_get(port, &dev_info);
5134
5135         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5136                 return -ENOTSUP;
5137
5138         if (vf >= dev_info.max_vfs)
5139                 return -EINVAL;
5140
5141         if (on > 1)
5142                 return -EINVAL;
5143
5144         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5145         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5146
5147         if (hw->mac.type == ixgbe_mac_82598EB) {
5148                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5149                              " on 82599 hardware and newer");
5150                 return -ENOTSUP;
5151         }
5152         if (ixgbe_vt_check(hw) < 0)
5153                 return -ENOTSUP;
5154
5155         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5156
5157         if (on)
5158                 vmolr |= val;
5159         else
5160                 vmolr &= ~val;
5161
5162         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5163
5164         return 0;
5165 }
5166
5167 int
5168 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5169 {
5170         struct rte_eth_dev *dev;
5171         struct rte_eth_dev_info dev_info;
5172         uint32_t reg, addr;
5173         uint32_t val;
5174         const uint8_t bit1 = 0x1;
5175         struct ixgbe_hw *hw;
5176
5177         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5178
5179         dev = &rte_eth_devices[port];
5180         rte_eth_dev_info_get(port, &dev_info);
5181
5182         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5183                 return -ENOTSUP;
5184
5185         if (vf >= dev_info.max_vfs)
5186                 return -EINVAL;
5187
5188         if (on > 1)
5189                 return -EINVAL;
5190
5191         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5192
5193         if (ixgbe_vt_check(hw) < 0)
5194                 return -ENOTSUP;
5195
5196         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5197         if (vf >= 32) {
5198                 addr = IXGBE_VFRE(1);
5199                 val = bit1 << (vf - 32);
5200         } else {
5201                 addr = IXGBE_VFRE(0);
5202                 val = bit1 << vf;
5203         }
5204
5205         reg = IXGBE_READ_REG(hw, addr);
5206
5207         if (on)
5208                 reg |= val;
5209         else
5210                 reg &= ~val;
5211
5212         IXGBE_WRITE_REG(hw, addr, reg);
5213
5214         return 0;
5215 }
5216
5217 int
5218 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5219 {
5220         struct rte_eth_dev *dev;
5221         struct rte_eth_dev_info dev_info;
5222         uint32_t reg, addr;
5223         uint32_t val;
5224         const uint8_t bit1 = 0x1;
5225
5226         struct ixgbe_hw *hw;
5227
5228         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5229
5230         dev = &rte_eth_devices[port];
5231         rte_eth_dev_info_get(port, &dev_info);
5232
5233         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5234                 return -ENOTSUP;
5235
5236         if (vf >= dev_info.max_vfs)
5237                 return -EINVAL;
5238
5239         if (on > 1)
5240                 return -EINVAL;
5241
5242         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5243         if (ixgbe_vt_check(hw) < 0)
5244                 return -ENOTSUP;
5245
5246         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5247         if (vf >= 32) {
5248                 addr = IXGBE_VFTE(1);
5249                 val = bit1 << (vf - 32);
5250         } else {
5251                 addr = IXGBE_VFTE(0);
5252                 val = bit1 << vf;
5253         }
5254
5255         reg = IXGBE_READ_REG(hw, addr);
5256
5257         if (on)
5258                 reg |= val;
5259         else
5260                 reg &= ~val;
5261
5262         IXGBE_WRITE_REG(hw, addr, reg);
5263
5264         return 0;
5265 }
5266
5267 int
5268 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5269                         uint64_t vf_mask, uint8_t vlan_on)
5270 {
5271         struct rte_eth_dev *dev;
5272         struct rte_eth_dev_info dev_info;
5273         int ret = 0;
5274         uint16_t vf_idx;
5275         struct ixgbe_hw *hw;
5276
5277         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5278
5279         dev = &rte_eth_devices[port];
5280         rte_eth_dev_info_get(port, &dev_info);
5281
5282         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5283                 return -ENOTSUP;
5284
5285         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5286                 return -EINVAL;
5287
5288         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5289         if (ixgbe_vt_check(hw) < 0)
5290                 return -ENOTSUP;
5291
5292         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5293                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5294                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5295                                                    vlan_on, false);
5296                         if (ret < 0)
5297                                 return ret;
5298                 }
5299         }
5300
5301         return ret;
5302 }
5303
5304 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5305         uint16_t tx_rate, uint64_t q_msk)
5306 {
5307         struct rte_eth_dev *dev;
5308         struct rte_eth_dev_info dev_info;
5309         struct ixgbe_hw *hw;
5310         struct ixgbe_vf_info *vfinfo;
5311         struct rte_eth_link link;
5312         uint8_t  nb_q_per_pool;
5313         uint32_t queue_stride;
5314         uint32_t queue_idx, idx = 0, vf_idx;
5315         uint32_t queue_end;
5316         uint16_t total_rate = 0;
5317         struct rte_pci_device *pci_dev;
5318
5319         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5320
5321         dev = &rte_eth_devices[port];
5322         rte_eth_dev_info_get(port, &dev_info);
5323         rte_eth_link_get_nowait(port, &link);
5324
5325         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5326                 return -ENOTSUP;
5327
5328         if (vf >= dev_info.max_vfs)
5329                 return -EINVAL;
5330
5331         if (tx_rate > link.link_speed)
5332                 return -EINVAL;
5333
5334         if (q_msk == 0)
5335                 return 0;
5336
5337         pci_dev = IXGBE_DEV_TO_PCI(dev);
5338         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5339         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5340         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5341         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5342         queue_idx = vf * queue_stride;
5343         queue_end = queue_idx + nb_q_per_pool - 1;
5344         if (queue_end >= hw->mac.max_tx_queues)
5345                 return -EINVAL;
5346
5347         if (vfinfo) {
5348                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5349                         if (vf_idx == vf)
5350                                 continue;
5351                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5352                                 idx++)
5353                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5354                 }
5355         } else {
5356                 return -EINVAL;
5357         }
5358
5359         /* Store tx_rate for this vf. */
5360         for (idx = 0; idx < nb_q_per_pool; idx++) {
5361                 if (((uint64_t)0x1 << idx) & q_msk) {
5362                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5363                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5364                         total_rate += tx_rate;
5365                 }
5366         }
5367
5368         if (total_rate > dev->data->dev_link.link_speed) {
5369                 /* Reset stored TX rate of the VF if it causes exceed
5370                  * link speed.
5371                  */
5372                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5373                 return -EINVAL;
5374         }
5375
5376         /* Set RTTBCNRC of each queue/pool for vf X  */
5377         for (; queue_idx <= queue_end; queue_idx++) {
5378                 if (0x1 & q_msk)
5379                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5380                 q_msk = q_msk >> 1;
5381         }
5382
5383         return 0;
5384 }
5385
5386 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5387 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5388 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5389 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5390 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5391         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5392         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5393
5394 static int
5395 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5396                         struct rte_eth_mirror_conf *mirror_conf,
5397                         uint8_t rule_id, uint8_t on)
5398 {
5399         uint32_t mr_ctl, vlvf;
5400         uint32_t mp_lsb = 0;
5401         uint32_t mv_msb = 0;
5402         uint32_t mv_lsb = 0;
5403         uint32_t mp_msb = 0;
5404         uint8_t i = 0;
5405         int reg_index = 0;
5406         uint64_t vlan_mask = 0;
5407
5408         const uint8_t pool_mask_offset = 32;
5409         const uint8_t vlan_mask_offset = 32;
5410         const uint8_t dst_pool_offset = 8;
5411         const uint8_t rule_mr_offset  = 4;
5412         const uint8_t mirror_rule_mask = 0x0F;
5413
5414         struct ixgbe_mirror_info *mr_info =
5415                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5416         struct ixgbe_hw *hw =
5417                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5418         uint8_t mirror_type = 0;
5419
5420         if (ixgbe_vt_check(hw) < 0)
5421                 return -ENOTSUP;
5422
5423         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5424                 return -EINVAL;
5425
5426         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5427                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5428                         mirror_conf->rule_type);
5429                 return -EINVAL;
5430         }
5431
5432         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5433                 mirror_type |= IXGBE_MRCTL_VLME;
5434                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5435                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5436                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5437                                 /* search vlan id related pool vlan filter index */
5438                                 reg_index = ixgbe_find_vlvf_slot(hw,
5439                                                  mirror_conf->vlan.vlan_id[i],
5440                                                  false);
5441                                 if (reg_index < 0)
5442                                         return -EINVAL;
5443                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5444                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5445                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5446                                       mirror_conf->vlan.vlan_id[i]))
5447                                         vlan_mask |= (1ULL << reg_index);
5448                                 else
5449                                         return -EINVAL;
5450                         }
5451                 }
5452
5453                 if (on) {
5454                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5455                         mv_msb = vlan_mask >> vlan_mask_offset;
5456
5457                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5458                                                 mirror_conf->vlan.vlan_mask;
5459                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5460                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5461                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5462                                                 mirror_conf->vlan.vlan_id[i];
5463                         }
5464                 } else {
5465                         mv_lsb = 0;
5466                         mv_msb = 0;
5467                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5468                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5469                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5470                 }
5471         }
5472
5473         /*
5474          * if enable pool mirror, write related pool mask register,if disable
5475          * pool mirror, clear PFMRVM register
5476          */
5477         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5478                 mirror_type |= IXGBE_MRCTL_VPME;
5479                 if (on) {
5480                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5481                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5482                         mr_info->mr_conf[rule_id].pool_mask =
5483                                         mirror_conf->pool_mask;
5484
5485                 } else {
5486                         mp_lsb = 0;
5487                         mp_msb = 0;
5488                         mr_info->mr_conf[rule_id].pool_mask = 0;
5489                 }
5490         }
5491         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5492                 mirror_type |= IXGBE_MRCTL_UPME;
5493         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5494                 mirror_type |= IXGBE_MRCTL_DPME;
5495
5496         /* read  mirror control register and recalculate it */
5497         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5498
5499         if (on) {
5500                 mr_ctl |= mirror_type;
5501                 mr_ctl &= mirror_rule_mask;
5502                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5503         } else
5504                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5505
5506         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5507         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5508
5509         /* write mirrror control  register */
5510         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5511
5512         /* write pool mirrror control  register */
5513         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5514                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5515                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5516                                 mp_msb);
5517         }
5518         /* write VLAN mirrror control  register */
5519         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5520                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5521                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5522                                 mv_msb);
5523         }
5524
5525         return 0;
5526 }
5527
5528 static int
5529 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5530 {
5531         int mr_ctl = 0;
5532         uint32_t lsb_val = 0;
5533         uint32_t msb_val = 0;
5534         const uint8_t rule_mr_offset = 4;
5535
5536         struct ixgbe_hw *hw =
5537                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5538         struct ixgbe_mirror_info *mr_info =
5539                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5540
5541         if (ixgbe_vt_check(hw) < 0)
5542                 return -ENOTSUP;
5543
5544         memset(&mr_info->mr_conf[rule_id], 0,
5545                 sizeof(struct rte_eth_mirror_conf));
5546
5547         /* clear PFVMCTL register */
5548         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5549
5550         /* clear pool mask register */
5551         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5552         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5553
5554         /* clear vlan mask register */
5555         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5556         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5557
5558         return 0;
5559 }
5560
5561 static int
5562 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5563 {
5564         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5565         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5566         uint32_t mask;
5567         struct ixgbe_hw *hw =
5568                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5569
5570         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5571         mask |= (1 << IXGBE_MISC_VEC_ID);
5572         RTE_SET_USED(queue_id);
5573         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5574
5575         rte_intr_enable(intr_handle);
5576
5577         return 0;
5578 }
5579
5580 static int
5581 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5582 {
5583         uint32_t mask;
5584         struct ixgbe_hw *hw =
5585                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5586
5587         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5588         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5589         RTE_SET_USED(queue_id);
5590         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5591
5592         return 0;
5593 }
5594
5595 static int
5596 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5597 {
5598         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5599         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5600         uint32_t mask;
5601         struct ixgbe_hw *hw =
5602                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5603         struct ixgbe_interrupt *intr =
5604                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5605
5606         if (queue_id < 16) {
5607                 ixgbe_disable_intr(hw);
5608                 intr->mask |= (1 << queue_id);
5609                 ixgbe_enable_intr(dev);
5610         } else if (queue_id < 32) {
5611                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5612                 mask &= (1 << queue_id);
5613                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5614         } else if (queue_id < 64) {
5615                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5616                 mask &= (1 << (queue_id - 32));
5617                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5618         }
5619         rte_intr_enable(intr_handle);
5620
5621         return 0;
5622 }
5623
5624 static int
5625 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5626 {
5627         uint32_t mask;
5628         struct ixgbe_hw *hw =
5629                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5630         struct ixgbe_interrupt *intr =
5631                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5632
5633         if (queue_id < 16) {
5634                 ixgbe_disable_intr(hw);
5635                 intr->mask &= ~(1 << queue_id);
5636                 ixgbe_enable_intr(dev);
5637         } else if (queue_id < 32) {
5638                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5639                 mask &= ~(1 << queue_id);
5640                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5641         } else if (queue_id < 64) {
5642                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5643                 mask &= ~(1 << (queue_id - 32));
5644                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5645         }
5646
5647         return 0;
5648 }
5649
5650 static void
5651 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5652                      uint8_t queue, uint8_t msix_vector)
5653 {
5654         uint32_t tmp, idx;
5655
5656         if (direction == -1) {
5657                 /* other causes */
5658                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5659                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5660                 tmp &= ~0xFF;
5661                 tmp |= msix_vector;
5662                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5663         } else {
5664                 /* rx or tx cause */
5665                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5666                 idx = ((16 * (queue & 1)) + (8 * direction));
5667                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5668                 tmp &= ~(0xFF << idx);
5669                 tmp |= (msix_vector << idx);
5670                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5671         }
5672 }
5673
5674 /**
5675  * set the IVAR registers, mapping interrupt causes to vectors
5676  * @param hw
5677  *  pointer to ixgbe_hw struct
5678  * @direction
5679  *  0 for Rx, 1 for Tx, -1 for other causes
5680  * @queue
5681  *  queue to map the corresponding interrupt to
5682  * @msix_vector
5683  *  the vector to map to the corresponding queue
5684  */
5685 static void
5686 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5687                    uint8_t queue, uint8_t msix_vector)
5688 {
5689         uint32_t tmp, idx;
5690
5691         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5692         if (hw->mac.type == ixgbe_mac_82598EB) {
5693                 if (direction == -1)
5694                         direction = 0;
5695                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5696                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5697                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5698                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5699                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5700         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5701                         (hw->mac.type == ixgbe_mac_X540)) {
5702                 if (direction == -1) {
5703                         /* other causes */
5704                         idx = ((queue & 1) * 8);
5705                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5706                         tmp &= ~(0xFF << idx);
5707                         tmp |= (msix_vector << idx);
5708                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5709                 } else {
5710                         /* rx or tx causes */
5711                         idx = ((16 * (queue & 1)) + (8 * direction));
5712                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5713                         tmp &= ~(0xFF << idx);
5714                         tmp |= (msix_vector << idx);
5715                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5716                 }
5717         }
5718 }
5719
5720 static void
5721 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5722 {
5723         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5724         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5725         struct ixgbe_hw *hw =
5726                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5727         uint32_t q_idx;
5728         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5729
5730         /* Configure VF other cause ivar */
5731         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5732
5733         /* won't configure msix register if no mapping is done
5734          * between intr vector and event fd.
5735          */
5736         if (!rte_intr_dp_is_en(intr_handle))
5737                 return;
5738
5739         /* Configure all RX queues of VF */
5740         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5741                 /* Force all queue use vector 0,
5742                  * as IXGBE_VF_MAXMSIVECOTR = 1
5743                  */
5744                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5745                 intr_handle->intr_vec[q_idx] = vector_idx;
5746         }
5747 }
5748
5749 /**
5750  * Sets up the hardware to properly generate MSI-X interrupts
5751  * @hw
5752  *  board private structure
5753  */
5754 static void
5755 ixgbe_configure_msix(struct rte_eth_dev *dev)
5756 {
5757         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5758         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5759         struct ixgbe_hw *hw =
5760                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5761         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5762         uint32_t vec = IXGBE_MISC_VEC_ID;
5763         uint32_t mask;
5764         uint32_t gpie;
5765
5766         /* won't configure msix register if no mapping is done
5767          * between intr vector and event fd
5768          */
5769         if (!rte_intr_dp_is_en(intr_handle))
5770                 return;
5771
5772         if (rte_intr_allow_others(intr_handle))
5773                 vec = base = IXGBE_RX_VEC_START;
5774
5775         /* setup GPIE for MSI-x mode */
5776         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5777         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5778                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5779         /* auto clearing and auto setting corresponding bits in EIMS
5780          * when MSI-X interrupt is triggered
5781          */
5782         if (hw->mac.type == ixgbe_mac_82598EB) {
5783                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5784         } else {
5785                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5786                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5787         }
5788         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5789
5790         /* Populate the IVAR table and set the ITR values to the
5791          * corresponding register.
5792          */
5793         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5794              queue_id++) {
5795                 /* by default, 1:1 mapping */
5796                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5797                 intr_handle->intr_vec[queue_id] = vec;
5798                 if (vec < base + intr_handle->nb_efd - 1)
5799                         vec++;
5800         }
5801
5802         switch (hw->mac.type) {
5803         case ixgbe_mac_82598EB:
5804                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5805                                    IXGBE_MISC_VEC_ID);
5806                 break;
5807         case ixgbe_mac_82599EB:
5808         case ixgbe_mac_X540:
5809                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5810                 break;
5811         default:
5812                 break;
5813         }
5814         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5815                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5816
5817         /* set up to autoclear timer, and the vectors */
5818         mask = IXGBE_EIMS_ENABLE_MASK;
5819         mask &= ~(IXGBE_EIMS_OTHER |
5820                   IXGBE_EIMS_MAILBOX |
5821                   IXGBE_EIMS_LSC);
5822
5823         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5824 }
5825
5826 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5827         uint16_t queue_idx, uint16_t tx_rate)
5828 {
5829         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5830         uint32_t rf_dec, rf_int;
5831         uint32_t bcnrc_val;
5832         uint16_t link_speed = dev->data->dev_link.link_speed;
5833
5834         if (queue_idx >= hw->mac.max_tx_queues)
5835                 return -EINVAL;
5836
5837         if (tx_rate != 0) {
5838                 /* Calculate the rate factor values to set */
5839                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5840                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5841                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5842
5843                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5844                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5845                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5846                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5847         } else {
5848                 bcnrc_val = 0;
5849         }
5850
5851         /*
5852          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5853          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5854          * set as 0x4.
5855          */
5856         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5857                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5858                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5859                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5860                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5861         else
5862                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5863                         IXGBE_MMW_SIZE_DEFAULT);
5864
5865         /* Set RTTBCNRC of queue X */
5866         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5867         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5868         IXGBE_WRITE_FLUSH(hw);
5869
5870         return 0;
5871 }
5872
5873 static void
5874 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5875                      __attribute__((unused)) uint32_t index,
5876                      __attribute__((unused)) uint32_t pool)
5877 {
5878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5879         int diag;
5880
5881         /*
5882          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5883          * operation. Trap this case to avoid exhausting the [very limited]
5884          * set of PF resources used to store VF MAC addresses.
5885          */
5886         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5887                 return;
5888         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5889         if (diag == 0)
5890                 return;
5891         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5892 }
5893
5894 static void
5895 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5896 {
5897         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5898         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5899         struct ether_addr *mac_addr;
5900         uint32_t i;
5901         int diag;
5902
5903         /*
5904          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5905          * not support the deletion of a given MAC address.
5906          * Instead, it imposes to delete all MAC addresses, then to add again
5907          * all MAC addresses with the exception of the one to be deleted.
5908          */
5909         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5910
5911         /*
5912          * Add again all MAC addresses, with the exception of the deleted one
5913          * and of the permanent MAC address.
5914          */
5915         for (i = 0, mac_addr = dev->data->mac_addrs;
5916              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5917                 /* Skip the deleted MAC address */
5918                 if (i == index)
5919                         continue;
5920                 /* Skip NULL MAC addresses */
5921                 if (is_zero_ether_addr(mac_addr))
5922                         continue;
5923                 /* Skip the permanent MAC address */
5924                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5925                         continue;
5926                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5927                 if (diag != 0)
5928                         PMD_DRV_LOG(ERR,
5929                                     "Adding again MAC address "
5930                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5931                                     "diag=%d",
5932                                     mac_addr->addr_bytes[0],
5933                                     mac_addr->addr_bytes[1],
5934                                     mac_addr->addr_bytes[2],
5935                                     mac_addr->addr_bytes[3],
5936                                     mac_addr->addr_bytes[4],
5937                                     mac_addr->addr_bytes[5],
5938                                     diag);
5939         }
5940 }
5941
5942 static void
5943 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5944 {
5945         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5946
5947         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5948 }
5949
5950 #define MAC_TYPE_FILTER_SUP(type)    do {\
5951         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5952                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5953                 (type) != ixgbe_mac_X550EM_a)\
5954                 return -ENOTSUP;\
5955 } while (0)
5956
5957 static int
5958 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5959                         struct rte_eth_syn_filter *filter,
5960                         bool add)
5961 {
5962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5963         struct ixgbe_filter_info *filter_info =
5964                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5965         uint32_t syn_info;
5966         uint32_t synqf;
5967
5968         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5969                 return -EINVAL;
5970
5971         syn_info = filter_info->syn_info;
5972
5973         if (add) {
5974                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5975                         return -EINVAL;
5976                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5977                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5978
5979                 if (filter->hig_pri)
5980                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5981                 else
5982                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5983         } else {
5984                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5985                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5986                         return -ENOENT;
5987                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5988         }
5989
5990         filter_info->syn_info = synqf;
5991         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5992         IXGBE_WRITE_FLUSH(hw);
5993         return 0;
5994 }
5995
5996 static int
5997 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5998                         struct rte_eth_syn_filter *filter)
5999 {
6000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6001         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6002
6003         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6004                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6005                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6006                 return 0;
6007         }
6008         return -ENOENT;
6009 }
6010
6011 static int
6012 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6013                         enum rte_filter_op filter_op,
6014                         void *arg)
6015 {
6016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6017         int ret;
6018
6019         MAC_TYPE_FILTER_SUP(hw->mac.type);
6020
6021         if (filter_op == RTE_ETH_FILTER_NOP)
6022                 return 0;
6023
6024         if (arg == NULL) {
6025                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6026                             filter_op);
6027                 return -EINVAL;
6028         }
6029
6030         switch (filter_op) {
6031         case RTE_ETH_FILTER_ADD:
6032                 ret = ixgbe_syn_filter_set(dev,
6033                                 (struct rte_eth_syn_filter *)arg,
6034                                 TRUE);
6035                 break;
6036         case RTE_ETH_FILTER_DELETE:
6037                 ret = ixgbe_syn_filter_set(dev,
6038                                 (struct rte_eth_syn_filter *)arg,
6039                                 FALSE);
6040                 break;
6041         case RTE_ETH_FILTER_GET:
6042                 ret = ixgbe_syn_filter_get(dev,
6043                                 (struct rte_eth_syn_filter *)arg);
6044                 break;
6045         default:
6046                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6047                 ret = -EINVAL;
6048                 break;
6049         }
6050
6051         return ret;
6052 }
6053
6054
6055 static inline enum ixgbe_5tuple_protocol
6056 convert_protocol_type(uint8_t protocol_value)
6057 {
6058         if (protocol_value == IPPROTO_TCP)
6059                 return IXGBE_FILTER_PROTOCOL_TCP;
6060         else if (protocol_value == IPPROTO_UDP)
6061                 return IXGBE_FILTER_PROTOCOL_UDP;
6062         else if (protocol_value == IPPROTO_SCTP)
6063                 return IXGBE_FILTER_PROTOCOL_SCTP;
6064         else
6065                 return IXGBE_FILTER_PROTOCOL_NONE;
6066 }
6067
6068 /* inject a 5-tuple filter to HW */
6069 static inline void
6070 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6071                            struct ixgbe_5tuple_filter *filter)
6072 {
6073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6074         int i;
6075         uint32_t ftqf, sdpqf;
6076         uint32_t l34timir = 0;
6077         uint8_t mask = 0xff;
6078
6079         i = filter->index;
6080
6081         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6082                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6083         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6084
6085         ftqf = (uint32_t)(filter->filter_info.proto &
6086                 IXGBE_FTQF_PROTOCOL_MASK);
6087         ftqf |= (uint32_t)((filter->filter_info.priority &
6088                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6089         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6090                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6091         if (filter->filter_info.dst_ip_mask == 0)
6092                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6093         if (filter->filter_info.src_port_mask == 0)
6094                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6095         if (filter->filter_info.dst_port_mask == 0)
6096                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6097         if (filter->filter_info.proto_mask == 0)
6098                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6099         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6100         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6101         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6102
6103         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6104         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6105         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6106         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6107
6108         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6109         l34timir |= (uint32_t)(filter->queue <<
6110                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6111         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6112 }
6113
6114 /*
6115  * add a 5tuple filter
6116  *
6117  * @param
6118  * dev: Pointer to struct rte_eth_dev.
6119  * index: the index the filter allocates.
6120  * filter: ponter to the filter that will be added.
6121  * rx_queue: the queue id the filter assigned to.
6122  *
6123  * @return
6124  *    - On success, zero.
6125  *    - On failure, a negative value.
6126  */
6127 static int
6128 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6129                         struct ixgbe_5tuple_filter *filter)
6130 {
6131         struct ixgbe_filter_info *filter_info =
6132                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6133         int i, idx, shift;
6134
6135         /*
6136          * look for an unused 5tuple filter index,
6137          * and insert the filter to list.
6138          */
6139         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6140                 idx = i / (sizeof(uint32_t) * NBBY);
6141                 shift = i % (sizeof(uint32_t) * NBBY);
6142                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6143                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6144                         filter->index = i;
6145                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6146                                           filter,
6147                                           entries);
6148                         break;
6149                 }
6150         }
6151         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6152                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6153                 return -ENOSYS;
6154         }
6155
6156         ixgbe_inject_5tuple_filter(dev, filter);
6157
6158         return 0;
6159 }
6160
6161 /*
6162  * remove a 5tuple filter
6163  *
6164  * @param
6165  * dev: Pointer to struct rte_eth_dev.
6166  * filter: the pointer of the filter will be removed.
6167  */
6168 static void
6169 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6170                         struct ixgbe_5tuple_filter *filter)
6171 {
6172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6173         struct ixgbe_filter_info *filter_info =
6174                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6175         uint16_t index = filter->index;
6176
6177         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6178                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6179         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6180         rte_free(filter);
6181
6182         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6183         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6184         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6185         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6186         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6187 }
6188
6189 static int
6190 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6191 {
6192         struct ixgbe_hw *hw;
6193         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6194
6195         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6196
6197         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6198                 return -EINVAL;
6199
6200         /* refuse mtu that requires the support of scattered packets when this
6201          * feature has not been enabled before.
6202          */
6203         if (!dev->data->scattered_rx &&
6204             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6205              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6206                 return -EINVAL;
6207
6208         /*
6209          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6210          * request of the version 2.0 of the mailbox API.
6211          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6212          * of the mailbox API.
6213          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6214          * prior to 3.11.33 which contains the following change:
6215          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6216          */
6217         ixgbevf_rlpml_set_vf(hw, max_frame);
6218
6219         /* update max frame size */
6220         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6221         return 0;
6222 }
6223
6224 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
6225         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6226                 return -ENOTSUP;\
6227 } while (0)
6228
6229 static inline struct ixgbe_5tuple_filter *
6230 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6231                         struct ixgbe_5tuple_filter_info *key)
6232 {
6233         struct ixgbe_5tuple_filter *it;
6234
6235         TAILQ_FOREACH(it, filter_list, entries) {
6236                 if (memcmp(key, &it->filter_info,
6237                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6238                         return it;
6239                 }
6240         }
6241         return NULL;
6242 }
6243
6244 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6245 static inline int
6246 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6247                         struct ixgbe_5tuple_filter_info *filter_info)
6248 {
6249         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6250                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6251                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6252                 return -EINVAL;
6253
6254         switch (filter->dst_ip_mask) {
6255         case UINT32_MAX:
6256                 filter_info->dst_ip_mask = 0;
6257                 filter_info->dst_ip = filter->dst_ip;
6258                 break;
6259         case 0:
6260                 filter_info->dst_ip_mask = 1;
6261                 break;
6262         default:
6263                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6264                 return -EINVAL;
6265         }
6266
6267         switch (filter->src_ip_mask) {
6268         case UINT32_MAX:
6269                 filter_info->src_ip_mask = 0;
6270                 filter_info->src_ip = filter->src_ip;
6271                 break;
6272         case 0:
6273                 filter_info->src_ip_mask = 1;
6274                 break;
6275         default:
6276                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6277                 return -EINVAL;
6278         }
6279
6280         switch (filter->dst_port_mask) {
6281         case UINT16_MAX:
6282                 filter_info->dst_port_mask = 0;
6283                 filter_info->dst_port = filter->dst_port;
6284                 break;
6285         case 0:
6286                 filter_info->dst_port_mask = 1;
6287                 break;
6288         default:
6289                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6290                 return -EINVAL;
6291         }
6292
6293         switch (filter->src_port_mask) {
6294         case UINT16_MAX:
6295                 filter_info->src_port_mask = 0;
6296                 filter_info->src_port = filter->src_port;
6297                 break;
6298         case 0:
6299                 filter_info->src_port_mask = 1;
6300                 break;
6301         default:
6302                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6303                 return -EINVAL;
6304         }
6305
6306         switch (filter->proto_mask) {
6307         case UINT8_MAX:
6308                 filter_info->proto_mask = 0;
6309                 filter_info->proto =
6310                         convert_protocol_type(filter->proto);
6311                 break;
6312         case 0:
6313                 filter_info->proto_mask = 1;
6314                 break;
6315         default:
6316                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6317                 return -EINVAL;
6318         }
6319
6320         filter_info->priority = (uint8_t)filter->priority;
6321         return 0;
6322 }
6323
6324 /*
6325  * add or delete a ntuple filter
6326  *
6327  * @param
6328  * dev: Pointer to struct rte_eth_dev.
6329  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6330  * add: if true, add filter, if false, remove filter
6331  *
6332  * @return
6333  *    - On success, zero.
6334  *    - On failure, a negative value.
6335  */
6336 static int
6337 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6338                         struct rte_eth_ntuple_filter *ntuple_filter,
6339                         bool add)
6340 {
6341         struct ixgbe_filter_info *filter_info =
6342                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6343         struct ixgbe_5tuple_filter_info filter_5tuple;
6344         struct ixgbe_5tuple_filter *filter;
6345         int ret;
6346
6347         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6348                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6349                 return -EINVAL;
6350         }
6351
6352         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6353         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6354         if (ret < 0)
6355                 return ret;
6356
6357         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6358                                          &filter_5tuple);
6359         if (filter != NULL && add) {
6360                 PMD_DRV_LOG(ERR, "filter exists.");
6361                 return -EEXIST;
6362         }
6363         if (filter == NULL && !add) {
6364                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6365                 return -ENOENT;
6366         }
6367
6368         if (add) {
6369                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6370                                 sizeof(struct ixgbe_5tuple_filter), 0);
6371                 if (filter == NULL)
6372                         return -ENOMEM;
6373                 (void)rte_memcpy(&filter->filter_info,
6374                                  &filter_5tuple,
6375                                  sizeof(struct ixgbe_5tuple_filter_info));
6376                 filter->queue = ntuple_filter->queue;
6377                 ret = ixgbe_add_5tuple_filter(dev, filter);
6378                 if (ret < 0) {
6379                         rte_free(filter);
6380                         return ret;
6381                 }
6382         } else
6383                 ixgbe_remove_5tuple_filter(dev, filter);
6384
6385         return 0;
6386 }
6387
6388 /*
6389  * get a ntuple filter
6390  *
6391  * @param
6392  * dev: Pointer to struct rte_eth_dev.
6393  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6394  *
6395  * @return
6396  *    - On success, zero.
6397  *    - On failure, a negative value.
6398  */
6399 static int
6400 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6401                         struct rte_eth_ntuple_filter *ntuple_filter)
6402 {
6403         struct ixgbe_filter_info *filter_info =
6404                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6405         struct ixgbe_5tuple_filter_info filter_5tuple;
6406         struct ixgbe_5tuple_filter *filter;
6407         int ret;
6408
6409         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6410                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6411                 return -EINVAL;
6412         }
6413
6414         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6415         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6416         if (ret < 0)
6417                 return ret;
6418
6419         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6420                                          &filter_5tuple);
6421         if (filter == NULL) {
6422                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6423                 return -ENOENT;
6424         }
6425         ntuple_filter->queue = filter->queue;
6426         return 0;
6427 }
6428
6429 /*
6430  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6431  * @dev: pointer to rte_eth_dev structure
6432  * @filter_op:operation will be taken.
6433  * @arg: a pointer to specific structure corresponding to the filter_op
6434  *
6435  * @return
6436  *    - On success, zero.
6437  *    - On failure, a negative value.
6438  */
6439 static int
6440 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6441                                 enum rte_filter_op filter_op,
6442                                 void *arg)
6443 {
6444         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6445         int ret;
6446
6447         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6448
6449         if (filter_op == RTE_ETH_FILTER_NOP)
6450                 return 0;
6451
6452         if (arg == NULL) {
6453                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6454                             filter_op);
6455                 return -EINVAL;
6456         }
6457
6458         switch (filter_op) {
6459         case RTE_ETH_FILTER_ADD:
6460                 ret = ixgbe_add_del_ntuple_filter(dev,
6461                         (struct rte_eth_ntuple_filter *)arg,
6462                         TRUE);
6463                 break;
6464         case RTE_ETH_FILTER_DELETE:
6465                 ret = ixgbe_add_del_ntuple_filter(dev,
6466                         (struct rte_eth_ntuple_filter *)arg,
6467                         FALSE);
6468                 break;
6469         case RTE_ETH_FILTER_GET:
6470                 ret = ixgbe_get_ntuple_filter(dev,
6471                         (struct rte_eth_ntuple_filter *)arg);
6472                 break;
6473         default:
6474                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6475                 ret = -EINVAL;
6476                 break;
6477         }
6478         return ret;
6479 }
6480
6481 static int
6482 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6483                         struct rte_eth_ethertype_filter *filter,
6484                         bool add)
6485 {
6486         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6487         struct ixgbe_filter_info *filter_info =
6488                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6489         uint32_t etqf = 0;
6490         uint32_t etqs = 0;
6491         int ret;
6492         struct ixgbe_ethertype_filter ethertype_filter;
6493
6494         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6495                 return -EINVAL;
6496
6497         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6498                 filter->ether_type == ETHER_TYPE_IPv6) {
6499                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6500                         " ethertype filter.", filter->ether_type);
6501                 return -EINVAL;
6502         }
6503
6504         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6505                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6506                 return -EINVAL;
6507         }
6508         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6509                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6510                 return -EINVAL;
6511         }
6512
6513         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6514         if (ret >= 0 && add) {
6515                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6516                             filter->ether_type);
6517                 return -EEXIST;
6518         }
6519         if (ret < 0 && !add) {
6520                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6521                             filter->ether_type);
6522                 return -ENOENT;
6523         }
6524
6525         if (add) {
6526                 etqf = IXGBE_ETQF_FILTER_EN;
6527                 etqf |= (uint32_t)filter->ether_type;
6528                 etqs |= (uint32_t)((filter->queue <<
6529                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6530                                     IXGBE_ETQS_RX_QUEUE);
6531                 etqs |= IXGBE_ETQS_QUEUE_EN;
6532
6533                 ethertype_filter.ethertype = filter->ether_type;
6534                 ethertype_filter.etqf = etqf;
6535                 ethertype_filter.etqs = etqs;
6536                 ret = ixgbe_ethertype_filter_insert(filter_info,
6537                                                     &ethertype_filter);
6538                 if (ret < 0) {
6539                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6540                         return -ENOSPC;
6541                 }
6542         } else {
6543                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6544                 if (ret < 0)
6545                         return -ENOSYS;
6546         }
6547         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6548         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6549         IXGBE_WRITE_FLUSH(hw);
6550
6551         return 0;
6552 }
6553
6554 static int
6555 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6556                         struct rte_eth_ethertype_filter *filter)
6557 {
6558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6559         struct ixgbe_filter_info *filter_info =
6560                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6561         uint32_t etqf, etqs;
6562         int ret;
6563
6564         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6565         if (ret < 0) {
6566                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6567                             filter->ether_type);
6568                 return -ENOENT;
6569         }
6570
6571         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6572         if (etqf & IXGBE_ETQF_FILTER_EN) {
6573                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6574                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6575                 filter->flags = 0;
6576                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6577                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6578                 return 0;
6579         }
6580         return -ENOENT;
6581 }
6582
6583 /*
6584  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6585  * @dev: pointer to rte_eth_dev structure
6586  * @filter_op:operation will be taken.
6587  * @arg: a pointer to specific structure corresponding to the filter_op
6588  */
6589 static int
6590 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6591                                 enum rte_filter_op filter_op,
6592                                 void *arg)
6593 {
6594         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6595         int ret;
6596
6597         MAC_TYPE_FILTER_SUP(hw->mac.type);
6598
6599         if (filter_op == RTE_ETH_FILTER_NOP)
6600                 return 0;
6601
6602         if (arg == NULL) {
6603                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6604                             filter_op);
6605                 return -EINVAL;
6606         }
6607
6608         switch (filter_op) {
6609         case RTE_ETH_FILTER_ADD:
6610                 ret = ixgbe_add_del_ethertype_filter(dev,
6611                         (struct rte_eth_ethertype_filter *)arg,
6612                         TRUE);
6613                 break;
6614         case RTE_ETH_FILTER_DELETE:
6615                 ret = ixgbe_add_del_ethertype_filter(dev,
6616                         (struct rte_eth_ethertype_filter *)arg,
6617                         FALSE);
6618                 break;
6619         case RTE_ETH_FILTER_GET:
6620                 ret = ixgbe_get_ethertype_filter(dev,
6621                         (struct rte_eth_ethertype_filter *)arg);
6622                 break;
6623         default:
6624                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6625                 ret = -EINVAL;
6626                 break;
6627         }
6628         return ret;
6629 }
6630
6631 static int
6632 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6633                      enum rte_filter_type filter_type,
6634                      enum rte_filter_op filter_op,
6635                      void *arg)
6636 {
6637         int ret = -EINVAL;
6638
6639         switch (filter_type) {
6640         case RTE_ETH_FILTER_NTUPLE:
6641                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6642                 break;
6643         case RTE_ETH_FILTER_ETHERTYPE:
6644                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6645                 break;
6646         case RTE_ETH_FILTER_SYN:
6647                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6648                 break;
6649         case RTE_ETH_FILTER_FDIR:
6650                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6651                 break;
6652         case RTE_ETH_FILTER_L2_TUNNEL:
6653                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6654                 break;
6655         default:
6656                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6657                                                         filter_type);
6658                 break;
6659         }
6660
6661         return ret;
6662 }
6663
6664 static u8 *
6665 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6666                         u8 **mc_addr_ptr, u32 *vmdq)
6667 {
6668         u8 *mc_addr;
6669
6670         *vmdq = 0;
6671         mc_addr = *mc_addr_ptr;
6672         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6673         return mc_addr;
6674 }
6675
6676 static int
6677 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6678                           struct ether_addr *mc_addr_set,
6679                           uint32_t nb_mc_addr)
6680 {
6681         struct ixgbe_hw *hw;
6682         u8 *mc_addr_list;
6683
6684         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6685         mc_addr_list = (u8 *)mc_addr_set;
6686         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6687                                          ixgbe_dev_addr_list_itr, TRUE);
6688 }
6689
6690 static uint64_t
6691 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6692 {
6693         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6694         uint64_t systime_cycles;
6695
6696         switch (hw->mac.type) {
6697         case ixgbe_mac_X550:
6698         case ixgbe_mac_X550EM_x:
6699         case ixgbe_mac_X550EM_a:
6700                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6701                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6702                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6703                                 * NSEC_PER_SEC;
6704                 break;
6705         default:
6706                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6707                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6708                                 << 32;
6709         }
6710
6711         return systime_cycles;
6712 }
6713
6714 static uint64_t
6715 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6716 {
6717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6718         uint64_t rx_tstamp_cycles;
6719
6720         switch (hw->mac.type) {
6721         case ixgbe_mac_X550:
6722         case ixgbe_mac_X550EM_x:
6723         case ixgbe_mac_X550EM_a:
6724                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6725                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6726                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6727                                 * NSEC_PER_SEC;
6728                 break;
6729         default:
6730                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6731                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6732                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6733                                 << 32;
6734         }
6735
6736         return rx_tstamp_cycles;
6737 }
6738
6739 static uint64_t
6740 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6741 {
6742         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6743         uint64_t tx_tstamp_cycles;
6744
6745         switch (hw->mac.type) {
6746         case ixgbe_mac_X550:
6747         case ixgbe_mac_X550EM_x:
6748         case ixgbe_mac_X550EM_a:
6749                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6750                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6751                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6752                                 * NSEC_PER_SEC;
6753                 break;
6754         default:
6755                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6756                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6757                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6758                                 << 32;
6759         }
6760
6761         return tx_tstamp_cycles;
6762 }
6763
6764 static void
6765 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6766 {
6767         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6768         struct ixgbe_adapter *adapter =
6769                 (struct ixgbe_adapter *)dev->data->dev_private;
6770         struct rte_eth_link link;
6771         uint32_t incval = 0;
6772         uint32_t shift = 0;
6773
6774         /* Get current link speed. */
6775         memset(&link, 0, sizeof(link));
6776         ixgbe_dev_link_update(dev, 1);
6777         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6778
6779         switch (link.link_speed) {
6780         case ETH_SPEED_NUM_100M:
6781                 incval = IXGBE_INCVAL_100;
6782                 shift = IXGBE_INCVAL_SHIFT_100;
6783                 break;
6784         case ETH_SPEED_NUM_1G:
6785                 incval = IXGBE_INCVAL_1GB;
6786                 shift = IXGBE_INCVAL_SHIFT_1GB;
6787                 break;
6788         case ETH_SPEED_NUM_10G:
6789         default:
6790                 incval = IXGBE_INCVAL_10GB;
6791                 shift = IXGBE_INCVAL_SHIFT_10GB;
6792                 break;
6793         }
6794
6795         switch (hw->mac.type) {
6796         case ixgbe_mac_X550:
6797         case ixgbe_mac_X550EM_x:
6798         case ixgbe_mac_X550EM_a:
6799                 /* Independent of link speed. */
6800                 incval = 1;
6801                 /* Cycles read will be interpreted as ns. */
6802                 shift = 0;
6803                 /* Fall-through */
6804         case ixgbe_mac_X540:
6805                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6806                 break;
6807         case ixgbe_mac_82599EB:
6808                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6809                 shift -= IXGBE_INCVAL_SHIFT_82599;
6810                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6811                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6812                 break;
6813         default:
6814                 /* Not supported. */
6815                 return;
6816         }
6817
6818         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6819         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6820         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6821
6822         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6823         adapter->systime_tc.cc_shift = shift;
6824         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6825
6826         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6827         adapter->rx_tstamp_tc.cc_shift = shift;
6828         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6829
6830         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6831         adapter->tx_tstamp_tc.cc_shift = shift;
6832         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6833 }
6834
6835 static int
6836 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6837 {
6838         struct ixgbe_adapter *adapter =
6839                         (struct ixgbe_adapter *)dev->data->dev_private;
6840
6841         adapter->systime_tc.nsec += delta;
6842         adapter->rx_tstamp_tc.nsec += delta;
6843         adapter->tx_tstamp_tc.nsec += delta;
6844
6845         return 0;
6846 }
6847
6848 static int
6849 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6850 {
6851         uint64_t ns;
6852         struct ixgbe_adapter *adapter =
6853                         (struct ixgbe_adapter *)dev->data->dev_private;
6854
6855         ns = rte_timespec_to_ns(ts);
6856         /* Set the timecounters to a new value. */
6857         adapter->systime_tc.nsec = ns;
6858         adapter->rx_tstamp_tc.nsec = ns;
6859         adapter->tx_tstamp_tc.nsec = ns;
6860
6861         return 0;
6862 }
6863
6864 static int
6865 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6866 {
6867         uint64_t ns, systime_cycles;
6868         struct ixgbe_adapter *adapter =
6869                         (struct ixgbe_adapter *)dev->data->dev_private;
6870
6871         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6872         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6873         *ts = rte_ns_to_timespec(ns);
6874
6875         return 0;
6876 }
6877
6878 static int
6879 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6880 {
6881         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6882         uint32_t tsync_ctl;
6883         uint32_t tsauxc;
6884
6885         /* Stop the timesync system time. */
6886         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6887         /* Reset the timesync system time value. */
6888         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6889         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6890
6891         /* Enable system time for platforms where it isn't on by default. */
6892         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6893         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6894         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6895
6896         ixgbe_start_timecounters(dev);
6897
6898         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6899         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6900                         (ETHER_TYPE_1588 |
6901                          IXGBE_ETQF_FILTER_EN |
6902                          IXGBE_ETQF_1588));
6903
6904         /* Enable timestamping of received PTP packets. */
6905         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6906         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6907         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6908
6909         /* Enable timestamping of transmitted PTP packets. */
6910         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6911         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6912         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6913
6914         IXGBE_WRITE_FLUSH(hw);
6915
6916         return 0;
6917 }
6918
6919 static int
6920 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6921 {
6922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6923         uint32_t tsync_ctl;
6924
6925         /* Disable timestamping of transmitted PTP packets. */
6926         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6927         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6928         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6929
6930         /* Disable timestamping of received PTP packets. */
6931         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6932         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6933         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6934
6935         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6936         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6937
6938         /* Stop incrementating the System Time registers. */
6939         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6940
6941         return 0;
6942 }
6943
6944 static int
6945 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6946                                  struct timespec *timestamp,
6947                                  uint32_t flags __rte_unused)
6948 {
6949         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6950         struct ixgbe_adapter *adapter =
6951                 (struct ixgbe_adapter *)dev->data->dev_private;
6952         uint32_t tsync_rxctl;
6953         uint64_t rx_tstamp_cycles;
6954         uint64_t ns;
6955
6956         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6957         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6958                 return -EINVAL;
6959
6960         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6961         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6962         *timestamp = rte_ns_to_timespec(ns);
6963
6964         return  0;
6965 }
6966
6967 static int
6968 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6969                                  struct timespec *timestamp)
6970 {
6971         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6972         struct ixgbe_adapter *adapter =
6973                 (struct ixgbe_adapter *)dev->data->dev_private;
6974         uint32_t tsync_txctl;
6975         uint64_t tx_tstamp_cycles;
6976         uint64_t ns;
6977
6978         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6979         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6980                 return -EINVAL;
6981
6982         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6983         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6984         *timestamp = rte_ns_to_timespec(ns);
6985
6986         return 0;
6987 }
6988
6989 static int
6990 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6991 {
6992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6993         int count = 0;
6994         int g_ind = 0;
6995         const struct reg_info *reg_group;
6996         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6997                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6998
6999         while ((reg_group = reg_set[g_ind++]))
7000                 count += ixgbe_regs_group_count(reg_group);
7001
7002         return count;
7003 }
7004
7005 static int
7006 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7007 {
7008         int count = 0;
7009         int g_ind = 0;
7010         const struct reg_info *reg_group;
7011
7012         while ((reg_group = ixgbevf_regs[g_ind++]))
7013                 count += ixgbe_regs_group_count(reg_group);
7014
7015         return count;
7016 }
7017
7018 static int
7019 ixgbe_get_regs(struct rte_eth_dev *dev,
7020               struct rte_dev_reg_info *regs)
7021 {
7022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7023         uint32_t *data = regs->data;
7024         int g_ind = 0;
7025         int count = 0;
7026         const struct reg_info *reg_group;
7027         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7028                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7029
7030         if (data == NULL) {
7031                 regs->length = ixgbe_get_reg_length(dev);
7032                 regs->width = sizeof(uint32_t);
7033                 return 0;
7034         }
7035
7036         /* Support only full register dump */
7037         if ((regs->length == 0) ||
7038             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7039                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7040                         hw->device_id;
7041                 while ((reg_group = reg_set[g_ind++]))
7042                         count += ixgbe_read_regs_group(dev, &data[count],
7043                                 reg_group);
7044                 return 0;
7045         }
7046
7047         return -ENOTSUP;
7048 }
7049
7050 static int
7051 ixgbevf_get_regs(struct rte_eth_dev *dev,
7052                 struct rte_dev_reg_info *regs)
7053 {
7054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7055         uint32_t *data = regs->data;
7056         int g_ind = 0;
7057         int count = 0;
7058         const struct reg_info *reg_group;
7059
7060         if (data == NULL) {
7061                 regs->length = ixgbevf_get_reg_length(dev);
7062                 regs->width = sizeof(uint32_t);
7063                 return 0;
7064         }
7065
7066         /* Support only full register dump */
7067         if ((regs->length == 0) ||
7068             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7069                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7070                         hw->device_id;
7071                 while ((reg_group = ixgbevf_regs[g_ind++]))
7072                         count += ixgbe_read_regs_group(dev, &data[count],
7073                                                       reg_group);
7074                 return 0;
7075         }
7076
7077         return -ENOTSUP;
7078 }
7079
7080 static int
7081 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7082 {
7083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7084
7085         /* Return unit is byte count */
7086         return hw->eeprom.word_size * 2;
7087 }
7088
7089 static int
7090 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7091                 struct rte_dev_eeprom_info *in_eeprom)
7092 {
7093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7094         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7095         uint16_t *data = in_eeprom->data;
7096         int first, length;
7097
7098         first = in_eeprom->offset >> 1;
7099         length = in_eeprom->length >> 1;
7100         if ((first > hw->eeprom.word_size) ||
7101             ((first + length) > hw->eeprom.word_size))
7102                 return -EINVAL;
7103
7104         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7105
7106         return eeprom->ops.read_buffer(hw, first, length, data);
7107 }
7108
7109 static int
7110 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7111                 struct rte_dev_eeprom_info *in_eeprom)
7112 {
7113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7114         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7115         uint16_t *data = in_eeprom->data;
7116         int first, length;
7117
7118         first = in_eeprom->offset >> 1;
7119         length = in_eeprom->length >> 1;
7120         if ((first > hw->eeprom.word_size) ||
7121             ((first + length) > hw->eeprom.word_size))
7122                 return -EINVAL;
7123
7124         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7125
7126         return eeprom->ops.write_buffer(hw,  first, length, data);
7127 }
7128
7129 uint16_t
7130 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7131         switch (mac_type) {
7132         case ixgbe_mac_X550:
7133         case ixgbe_mac_X550EM_x:
7134         case ixgbe_mac_X550EM_a:
7135                 return ETH_RSS_RETA_SIZE_512;
7136         case ixgbe_mac_X550_vf:
7137         case ixgbe_mac_X550EM_x_vf:
7138         case ixgbe_mac_X550EM_a_vf:
7139                 return ETH_RSS_RETA_SIZE_64;
7140         default:
7141                 return ETH_RSS_RETA_SIZE_128;
7142         }
7143 }
7144
7145 uint32_t
7146 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7147         switch (mac_type) {
7148         case ixgbe_mac_X550:
7149         case ixgbe_mac_X550EM_x:
7150         case ixgbe_mac_X550EM_a:
7151                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7152                         return IXGBE_RETA(reta_idx >> 2);
7153                 else
7154                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7155         case ixgbe_mac_X550_vf:
7156         case ixgbe_mac_X550EM_x_vf:
7157         case ixgbe_mac_X550EM_a_vf:
7158                 return IXGBE_VFRETA(reta_idx >> 2);
7159         default:
7160                 return IXGBE_RETA(reta_idx >> 2);
7161         }
7162 }
7163
7164 uint32_t
7165 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7166         switch (mac_type) {
7167         case ixgbe_mac_X550_vf:
7168         case ixgbe_mac_X550EM_x_vf:
7169         case ixgbe_mac_X550EM_a_vf:
7170                 return IXGBE_VFMRQC;
7171         default:
7172                 return IXGBE_MRQC;
7173         }
7174 }
7175
7176 uint32_t
7177 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7178         switch (mac_type) {
7179         case ixgbe_mac_X550_vf:
7180         case ixgbe_mac_X550EM_x_vf:
7181         case ixgbe_mac_X550EM_a_vf:
7182                 return IXGBE_VFRSSRK(i);
7183         default:
7184                 return IXGBE_RSSRK(i);
7185         }
7186 }
7187
7188 bool
7189 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7190         switch (mac_type) {
7191         case ixgbe_mac_82599_vf:
7192         case ixgbe_mac_X540_vf:
7193                 return 0;
7194         default:
7195                 return 1;
7196         }
7197 }
7198
7199 static int
7200 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7201                         struct rte_eth_dcb_info *dcb_info)
7202 {
7203         struct ixgbe_dcb_config *dcb_config =
7204                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7205         struct ixgbe_dcb_tc_config *tc;
7206         uint8_t i, j;
7207
7208         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7209                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7210         else
7211                 dcb_info->nb_tcs = 1;
7212
7213         if (dcb_config->vt_mode) { /* vt is enabled*/
7214                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7215                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7216                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7217                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7218                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7219                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7220                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7221                                                 i * dcb_info->nb_tcs + j;
7222                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7223                                 dcb_info->tc_queue.tc_txq[i][j].base =
7224                                                 i * dcb_info->nb_tcs + j;
7225                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7226                         }
7227                 }
7228         } else { /* vt is disabled*/
7229                 struct rte_eth_dcb_rx_conf *rx_conf =
7230                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7231                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7232                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7233                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7234                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7235                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7236                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7237                         }
7238                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7239                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7240                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7241                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7242                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7243                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7244                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7245                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7246                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7247                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7248                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7249                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7250                         }
7251                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7252                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7253                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7254                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7255                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7256                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7257                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7258                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7259                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7260                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7261                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7262                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7263                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7264                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7265                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7266                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7267                 }
7268         }
7269         for (i = 0; i < dcb_info->nb_tcs; i++) {
7270                 tc = &dcb_config->tc_config[i];
7271                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7272         }
7273         return 0;
7274 }
7275
7276 /* Update e-tag ether type */
7277 static int
7278 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7279                             uint16_t ether_type)
7280 {
7281         uint32_t etag_etype;
7282
7283         if (hw->mac.type != ixgbe_mac_X550 &&
7284             hw->mac.type != ixgbe_mac_X550EM_x &&
7285             hw->mac.type != ixgbe_mac_X550EM_a) {
7286                 return -ENOTSUP;
7287         }
7288
7289         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7290         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7291         etag_etype |= ether_type;
7292         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7293         IXGBE_WRITE_FLUSH(hw);
7294
7295         return 0;
7296 }
7297
7298 /* Config l2 tunnel ether type */
7299 static int
7300 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7301                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7302 {
7303         int ret = 0;
7304         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7305         struct ixgbe_l2_tn_info *l2_tn_info =
7306                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7307
7308         if (l2_tunnel == NULL)
7309                 return -EINVAL;
7310
7311         switch (l2_tunnel->l2_tunnel_type) {
7312         case RTE_L2_TUNNEL_TYPE_E_TAG:
7313                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7314                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7315                 break;
7316         default:
7317                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7318                 ret = -EINVAL;
7319                 break;
7320         }
7321
7322         return ret;
7323 }
7324
7325 /* Enable e-tag tunnel */
7326 static int
7327 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7328 {
7329         uint32_t etag_etype;
7330
7331         if (hw->mac.type != ixgbe_mac_X550 &&
7332             hw->mac.type != ixgbe_mac_X550EM_x &&
7333             hw->mac.type != ixgbe_mac_X550EM_a) {
7334                 return -ENOTSUP;
7335         }
7336
7337         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7338         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7339         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7340         IXGBE_WRITE_FLUSH(hw);
7341
7342         return 0;
7343 }
7344
7345 /* Enable l2 tunnel */
7346 static int
7347 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7348                            enum rte_eth_tunnel_type l2_tunnel_type)
7349 {
7350         int ret = 0;
7351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7352         struct ixgbe_l2_tn_info *l2_tn_info =
7353                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7354
7355         switch (l2_tunnel_type) {
7356         case RTE_L2_TUNNEL_TYPE_E_TAG:
7357                 l2_tn_info->e_tag_en = TRUE;
7358                 ret = ixgbe_e_tag_enable(hw);
7359                 break;
7360         default:
7361                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7362                 ret = -EINVAL;
7363                 break;
7364         }
7365
7366         return ret;
7367 }
7368
7369 /* Disable e-tag tunnel */
7370 static int
7371 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7372 {
7373         uint32_t etag_etype;
7374
7375         if (hw->mac.type != ixgbe_mac_X550 &&
7376             hw->mac.type != ixgbe_mac_X550EM_x &&
7377             hw->mac.type != ixgbe_mac_X550EM_a) {
7378                 return -ENOTSUP;
7379         }
7380
7381         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7382         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7383         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7384         IXGBE_WRITE_FLUSH(hw);
7385
7386         return 0;
7387 }
7388
7389 /* Disable l2 tunnel */
7390 static int
7391 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7392                             enum rte_eth_tunnel_type l2_tunnel_type)
7393 {
7394         int ret = 0;
7395         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7396         struct ixgbe_l2_tn_info *l2_tn_info =
7397                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7398
7399         switch (l2_tunnel_type) {
7400         case RTE_L2_TUNNEL_TYPE_E_TAG:
7401                 l2_tn_info->e_tag_en = FALSE;
7402                 ret = ixgbe_e_tag_disable(hw);
7403                 break;
7404         default:
7405                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7406                 ret = -EINVAL;
7407                 break;
7408         }
7409
7410         return ret;
7411 }
7412
7413 static int
7414 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7415                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7416 {
7417         int ret = 0;
7418         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7419         uint32_t i, rar_entries;
7420         uint32_t rar_low, rar_high;
7421
7422         if (hw->mac.type != ixgbe_mac_X550 &&
7423             hw->mac.type != ixgbe_mac_X550EM_x &&
7424             hw->mac.type != ixgbe_mac_X550EM_a) {
7425                 return -ENOTSUP;
7426         }
7427
7428         rar_entries = ixgbe_get_num_rx_addrs(hw);
7429
7430         for (i = 1; i < rar_entries; i++) {
7431                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7432                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7433                 if ((rar_high & IXGBE_RAH_AV) &&
7434                     (rar_high & IXGBE_RAH_ADTYPE) &&
7435                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7436                      l2_tunnel->tunnel_id)) {
7437                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7438                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7439
7440                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7441
7442                         return ret;
7443                 }
7444         }
7445
7446         return ret;
7447 }
7448
7449 static int
7450 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7451                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7452 {
7453         int ret = 0;
7454         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7455         uint32_t i, rar_entries;
7456         uint32_t rar_low, rar_high;
7457
7458         if (hw->mac.type != ixgbe_mac_X550 &&
7459             hw->mac.type != ixgbe_mac_X550EM_x &&
7460             hw->mac.type != ixgbe_mac_X550EM_a) {
7461                 return -ENOTSUP;
7462         }
7463
7464         /* One entry for one tunnel. Try to remove potential existing entry. */
7465         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7466
7467         rar_entries = ixgbe_get_num_rx_addrs(hw);
7468
7469         for (i = 1; i < rar_entries; i++) {
7470                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7471                 if (rar_high & IXGBE_RAH_AV) {
7472                         continue;
7473                 } else {
7474                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7475                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7476                         rar_low = l2_tunnel->tunnel_id;
7477
7478                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7479                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7480
7481                         return ret;
7482                 }
7483         }
7484
7485         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7486                      " Please remove a rule before adding a new one.");
7487         return -EINVAL;
7488 }
7489
7490 static inline struct ixgbe_l2_tn_filter *
7491 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7492                           struct ixgbe_l2_tn_key *key)
7493 {
7494         int ret;
7495
7496         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7497         if (ret < 0)
7498                 return NULL;
7499
7500         return l2_tn_info->hash_map[ret];
7501 }
7502
7503 static inline int
7504 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7505                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7506 {
7507         int ret;
7508
7509         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7510                                &l2_tn_filter->key);
7511
7512         if (ret < 0) {
7513                 PMD_DRV_LOG(ERR,
7514                             "Failed to insert L2 tunnel filter"
7515                             " to hash table %d!",
7516                             ret);
7517                 return ret;
7518         }
7519
7520         l2_tn_info->hash_map[ret] = l2_tn_filter;
7521
7522         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7523
7524         return 0;
7525 }
7526
7527 static inline int
7528 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7529                           struct ixgbe_l2_tn_key *key)
7530 {
7531         int ret;
7532         struct ixgbe_l2_tn_filter *l2_tn_filter;
7533
7534         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7535
7536         if (ret < 0) {
7537                 PMD_DRV_LOG(ERR,
7538                             "No such L2 tunnel filter to delete %d!",
7539                             ret);
7540                 return ret;
7541         }
7542
7543         l2_tn_filter = l2_tn_info->hash_map[ret];
7544         l2_tn_info->hash_map[ret] = NULL;
7545
7546         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7547         rte_free(l2_tn_filter);
7548
7549         return 0;
7550 }
7551
7552 /* Add l2 tunnel filter */
7553 static int
7554 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7555                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7556                                bool restore)
7557 {
7558         int ret;
7559         struct ixgbe_l2_tn_info *l2_tn_info =
7560                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7561         struct ixgbe_l2_tn_key key;
7562         struct ixgbe_l2_tn_filter *node;
7563
7564         if (!restore) {
7565                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7566                 key.tn_id = l2_tunnel->tunnel_id;
7567
7568                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7569
7570                 if (node) {
7571                         PMD_DRV_LOG(ERR,
7572                                     "The L2 tunnel filter already exists!");
7573                         return -EINVAL;
7574                 }
7575
7576                 node = rte_zmalloc("ixgbe_l2_tn",
7577                                    sizeof(struct ixgbe_l2_tn_filter),
7578                                    0);
7579                 if (!node)
7580                         return -ENOMEM;
7581
7582                 (void)rte_memcpy(&node->key,
7583                                  &key,
7584                                  sizeof(struct ixgbe_l2_tn_key));
7585                 node->pool = l2_tunnel->pool;
7586                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7587                 if (ret < 0) {
7588                         rte_free(node);
7589                         return ret;
7590                 }
7591         }
7592
7593         switch (l2_tunnel->l2_tunnel_type) {
7594         case RTE_L2_TUNNEL_TYPE_E_TAG:
7595                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7596                 break;
7597         default:
7598                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7599                 ret = -EINVAL;
7600                 break;
7601         }
7602
7603         if ((!restore) && (ret < 0))
7604                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7605
7606         return ret;
7607 }
7608
7609 /* Delete l2 tunnel filter */
7610 static int
7611 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7612                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7613 {
7614         int ret;
7615         struct ixgbe_l2_tn_info *l2_tn_info =
7616                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7617         struct ixgbe_l2_tn_key key;
7618
7619         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7620         key.tn_id = l2_tunnel->tunnel_id;
7621         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7622         if (ret < 0)
7623                 return ret;
7624
7625         switch (l2_tunnel->l2_tunnel_type) {
7626         case RTE_L2_TUNNEL_TYPE_E_TAG:
7627                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7628                 break;
7629         default:
7630                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7631                 ret = -EINVAL;
7632                 break;
7633         }
7634
7635         return ret;
7636 }
7637
7638 /**
7639  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7640  * @dev: pointer to rte_eth_dev structure
7641  * @filter_op:operation will be taken.
7642  * @arg: a pointer to specific structure corresponding to the filter_op
7643  */
7644 static int
7645 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7646                                   enum rte_filter_op filter_op,
7647                                   void *arg)
7648 {
7649         int ret;
7650
7651         if (filter_op == RTE_ETH_FILTER_NOP)
7652                 return 0;
7653
7654         if (arg == NULL) {
7655                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7656                             filter_op);
7657                 return -EINVAL;
7658         }
7659
7660         switch (filter_op) {
7661         case RTE_ETH_FILTER_ADD:
7662                 ret = ixgbe_dev_l2_tunnel_filter_add
7663                         (dev,
7664                          (struct rte_eth_l2_tunnel_conf *)arg,
7665                          FALSE);
7666                 break;
7667         case RTE_ETH_FILTER_DELETE:
7668                 ret = ixgbe_dev_l2_tunnel_filter_del
7669                         (dev,
7670                          (struct rte_eth_l2_tunnel_conf *)arg);
7671                 break;
7672         default:
7673                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7674                 ret = -EINVAL;
7675                 break;
7676         }
7677         return ret;
7678 }
7679
7680 static int
7681 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7682 {
7683         int ret = 0;
7684         uint32_t ctrl;
7685         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7686
7687         if (hw->mac.type != ixgbe_mac_X550 &&
7688             hw->mac.type != ixgbe_mac_X550EM_x &&
7689             hw->mac.type != ixgbe_mac_X550EM_a) {
7690                 return -ENOTSUP;
7691         }
7692
7693         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7694         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7695         if (en)
7696                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7697         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7698
7699         return ret;
7700 }
7701
7702 /* Enable l2 tunnel forwarding */
7703 static int
7704 ixgbe_dev_l2_tunnel_forwarding_enable
7705         (struct rte_eth_dev *dev,
7706          enum rte_eth_tunnel_type l2_tunnel_type)
7707 {
7708         struct ixgbe_l2_tn_info *l2_tn_info =
7709                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7710         int ret = 0;
7711
7712         switch (l2_tunnel_type) {
7713         case RTE_L2_TUNNEL_TYPE_E_TAG:
7714                 l2_tn_info->e_tag_fwd_en = TRUE;
7715                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7716                 break;
7717         default:
7718                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7719                 ret = -EINVAL;
7720                 break;
7721         }
7722
7723         return ret;
7724 }
7725
7726 /* Disable l2 tunnel forwarding */
7727 static int
7728 ixgbe_dev_l2_tunnel_forwarding_disable
7729         (struct rte_eth_dev *dev,
7730          enum rte_eth_tunnel_type l2_tunnel_type)
7731 {
7732         struct ixgbe_l2_tn_info *l2_tn_info =
7733                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7734         int ret = 0;
7735
7736         switch (l2_tunnel_type) {
7737         case RTE_L2_TUNNEL_TYPE_E_TAG:
7738                 l2_tn_info->e_tag_fwd_en = FALSE;
7739                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7740                 break;
7741         default:
7742                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7743                 ret = -EINVAL;
7744                 break;
7745         }
7746
7747         return ret;
7748 }
7749
7750 static int
7751 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7752                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7753                              bool en)
7754 {
7755         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7756         int ret = 0;
7757         uint32_t vmtir, vmvir;
7758         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7759
7760         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7761                 PMD_DRV_LOG(ERR,
7762                             "VF id %u should be less than %u",
7763                             l2_tunnel->vf_id,
7764                             pci_dev->max_vfs);
7765                 return -EINVAL;
7766         }
7767
7768         if (hw->mac.type != ixgbe_mac_X550 &&
7769             hw->mac.type != ixgbe_mac_X550EM_x &&
7770             hw->mac.type != ixgbe_mac_X550EM_a) {
7771                 return -ENOTSUP;
7772         }
7773
7774         if (en)
7775                 vmtir = l2_tunnel->tunnel_id;
7776         else
7777                 vmtir = 0;
7778
7779         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7780
7781         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7782         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7783         if (en)
7784                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7785         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7786
7787         return ret;
7788 }
7789
7790 /* Enable l2 tunnel tag insertion */
7791 static int
7792 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7793                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7794 {
7795         int ret = 0;
7796
7797         switch (l2_tunnel->l2_tunnel_type) {
7798         case RTE_L2_TUNNEL_TYPE_E_TAG:
7799                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7800                 break;
7801         default:
7802                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7803                 ret = -EINVAL;
7804                 break;
7805         }
7806
7807         return ret;
7808 }
7809
7810 /* Disable l2 tunnel tag insertion */
7811 static int
7812 ixgbe_dev_l2_tunnel_insertion_disable
7813         (struct rte_eth_dev *dev,
7814          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7815 {
7816         int ret = 0;
7817
7818         switch (l2_tunnel->l2_tunnel_type) {
7819         case RTE_L2_TUNNEL_TYPE_E_TAG:
7820                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7821                 break;
7822         default:
7823                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7824                 ret = -EINVAL;
7825                 break;
7826         }
7827
7828         return ret;
7829 }
7830
7831 static int
7832 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7833                              bool en)
7834 {
7835         int ret = 0;
7836         uint32_t qde;
7837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7838
7839         if (hw->mac.type != ixgbe_mac_X550 &&
7840             hw->mac.type != ixgbe_mac_X550EM_x &&
7841             hw->mac.type != ixgbe_mac_X550EM_a) {
7842                 return -ENOTSUP;
7843         }
7844
7845         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7846         if (en)
7847                 qde |= IXGBE_QDE_STRIP_TAG;
7848         else
7849                 qde &= ~IXGBE_QDE_STRIP_TAG;
7850         qde &= ~IXGBE_QDE_READ;
7851         qde |= IXGBE_QDE_WRITE;
7852         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7853
7854         return ret;
7855 }
7856
7857 /* Enable l2 tunnel tag stripping */
7858 static int
7859 ixgbe_dev_l2_tunnel_stripping_enable
7860         (struct rte_eth_dev *dev,
7861          enum rte_eth_tunnel_type l2_tunnel_type)
7862 {
7863         int ret = 0;
7864
7865         switch (l2_tunnel_type) {
7866         case RTE_L2_TUNNEL_TYPE_E_TAG:
7867                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7868                 break;
7869         default:
7870                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7871                 ret = -EINVAL;
7872                 break;
7873         }
7874
7875         return ret;
7876 }
7877
7878 /* Disable l2 tunnel tag stripping */
7879 static int
7880 ixgbe_dev_l2_tunnel_stripping_disable
7881         (struct rte_eth_dev *dev,
7882          enum rte_eth_tunnel_type l2_tunnel_type)
7883 {
7884         int ret = 0;
7885
7886         switch (l2_tunnel_type) {
7887         case RTE_L2_TUNNEL_TYPE_E_TAG:
7888                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7889                 break;
7890         default:
7891                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7892                 ret = -EINVAL;
7893                 break;
7894         }
7895
7896         return ret;
7897 }
7898
7899 /* Enable/disable l2 tunnel offload functions */
7900 static int
7901 ixgbe_dev_l2_tunnel_offload_set
7902         (struct rte_eth_dev *dev,
7903          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7904          uint32_t mask,
7905          uint8_t en)
7906 {
7907         int ret = 0;
7908
7909         if (l2_tunnel == NULL)
7910                 return -EINVAL;
7911
7912         ret = -EINVAL;
7913         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7914                 if (en)
7915                         ret = ixgbe_dev_l2_tunnel_enable(
7916                                 dev,
7917                                 l2_tunnel->l2_tunnel_type);
7918                 else
7919                         ret = ixgbe_dev_l2_tunnel_disable(
7920                                 dev,
7921                                 l2_tunnel->l2_tunnel_type);
7922         }
7923
7924         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7925                 if (en)
7926                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7927                                 dev,
7928                                 l2_tunnel);
7929                 else
7930                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7931                                 dev,
7932                                 l2_tunnel);
7933         }
7934
7935         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7936                 if (en)
7937                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7938                                 dev,
7939                                 l2_tunnel->l2_tunnel_type);
7940                 else
7941                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7942                                 dev,
7943                                 l2_tunnel->l2_tunnel_type);
7944         }
7945
7946         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7947                 if (en)
7948                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7949                                 dev,
7950                                 l2_tunnel->l2_tunnel_type);
7951                 else
7952                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7953                                 dev,
7954                                 l2_tunnel->l2_tunnel_type);
7955         }
7956
7957         return ret;
7958 }
7959
7960 static int
7961 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7962                         uint16_t port)
7963 {
7964         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7965         IXGBE_WRITE_FLUSH(hw);
7966
7967         return 0;
7968 }
7969
7970 /* There's only one register for VxLAN UDP port.
7971  * So, we cannot add several ports. Will update it.
7972  */
7973 static int
7974 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7975                      uint16_t port)
7976 {
7977         if (port == 0) {
7978                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7979                 return -EINVAL;
7980         }
7981
7982         return ixgbe_update_vxlan_port(hw, port);
7983 }
7984
7985 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7986  * UDP port, it must have a value.
7987  * So, will reset it to the original value 0.
7988  */
7989 static int
7990 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7991                      uint16_t port)
7992 {
7993         uint16_t cur_port;
7994
7995         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7996
7997         if (cur_port != port) {
7998                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7999                 return -EINVAL;
8000         }
8001
8002         return ixgbe_update_vxlan_port(hw, 0);
8003 }
8004
8005 /* Add UDP tunneling port */
8006 static int
8007 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8008                               struct rte_eth_udp_tunnel *udp_tunnel)
8009 {
8010         int ret = 0;
8011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8012
8013         if (hw->mac.type != ixgbe_mac_X550 &&
8014             hw->mac.type != ixgbe_mac_X550EM_x &&
8015             hw->mac.type != ixgbe_mac_X550EM_a) {
8016                 return -ENOTSUP;
8017         }
8018
8019         if (udp_tunnel == NULL)
8020                 return -EINVAL;
8021
8022         switch (udp_tunnel->prot_type) {
8023         case RTE_TUNNEL_TYPE_VXLAN:
8024                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8025                 break;
8026
8027         case RTE_TUNNEL_TYPE_GENEVE:
8028         case RTE_TUNNEL_TYPE_TEREDO:
8029                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8030                 ret = -EINVAL;
8031                 break;
8032
8033         default:
8034                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8035                 ret = -EINVAL;
8036                 break;
8037         }
8038
8039         return ret;
8040 }
8041
8042 /* Remove UDP tunneling port */
8043 static int
8044 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8045                               struct rte_eth_udp_tunnel *udp_tunnel)
8046 {
8047         int ret = 0;
8048         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8049
8050         if (hw->mac.type != ixgbe_mac_X550 &&
8051             hw->mac.type != ixgbe_mac_X550EM_x &&
8052             hw->mac.type != ixgbe_mac_X550EM_a) {
8053                 return -ENOTSUP;
8054         }
8055
8056         if (udp_tunnel == NULL)
8057                 return -EINVAL;
8058
8059         switch (udp_tunnel->prot_type) {
8060         case RTE_TUNNEL_TYPE_VXLAN:
8061                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8062                 break;
8063         case RTE_TUNNEL_TYPE_GENEVE:
8064         case RTE_TUNNEL_TYPE_TEREDO:
8065                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8066                 ret = -EINVAL;
8067                 break;
8068         default:
8069                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8070                 ret = -EINVAL;
8071                 break;
8072         }
8073
8074         return ret;
8075 }
8076
8077 static void
8078 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8079 {
8080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8081
8082         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8083 }
8084
8085 static void
8086 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8087 {
8088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8089
8090         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8091 }
8092
8093 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8094 {
8095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8096         u32 in_msg = 0;
8097
8098         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8099                 return;
8100
8101         /* PF reset VF event */
8102         if (in_msg == IXGBE_PF_CONTROL_MSG)
8103                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8104 }
8105
8106 static int
8107 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8108 {
8109         uint32_t eicr;
8110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8111         struct ixgbe_interrupt *intr =
8112                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8113         ixgbevf_intr_disable(hw);
8114
8115         /* read-on-clear nic registers here */
8116         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8117         intr->flags = 0;
8118
8119         /* only one misc vector supported - mailbox */
8120         eicr &= IXGBE_VTEICR_MASK;
8121         if (eicr == IXGBE_MISC_VEC_ID)
8122                 intr->flags |= IXGBE_FLAG_MAILBOX;
8123
8124         return 0;
8125 }
8126
8127 static int
8128 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8129 {
8130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8131         struct ixgbe_interrupt *intr =
8132                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8133
8134         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8135                 ixgbevf_mbx_process(dev);
8136                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8137         }
8138
8139         ixgbevf_intr_enable(hw);
8140
8141         return 0;
8142 }
8143
8144 static void
8145 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8146                               void *param)
8147 {
8148         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8149
8150         ixgbevf_dev_interrupt_get_status(dev);
8151         ixgbevf_dev_interrupt_action(dev);
8152 }
8153
8154 /**
8155  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8156  *  @hw: pointer to hardware structure
8157  *
8158  *  Stops the transmit data path and waits for the HW to internally empty
8159  *  the Tx security block
8160  **/
8161 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8162 {
8163 #define IXGBE_MAX_SECTX_POLL 40
8164
8165         int i;
8166         int sectxreg;
8167
8168         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8169         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8170         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8171         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8172                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8173                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8174                         break;
8175                 /* Use interrupt-safe sleep just in case */
8176                 usec_delay(1000);
8177         }
8178
8179         /* For informational purposes only */
8180         if (i >= IXGBE_MAX_SECTX_POLL)
8181                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8182                          "path fully disabled.  Continuing with init.\n");
8183
8184         return IXGBE_SUCCESS;
8185 }
8186
8187 /**
8188  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8189  *  @hw: pointer to hardware structure
8190  *
8191  *  Enables the transmit data path.
8192  **/
8193 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8194 {
8195         uint32_t sectxreg;
8196
8197         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8198         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8199         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8200         IXGBE_WRITE_FLUSH(hw);
8201
8202         return IXGBE_SUCCESS;
8203 }
8204
8205 int
8206 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8207 {
8208         struct ixgbe_hw *hw;
8209         struct rte_eth_dev *dev;
8210         uint32_t ctrl;
8211
8212         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8213
8214         dev = &rte_eth_devices[port];
8215         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8216
8217         /* Stop the data paths */
8218         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8219                 return -ENOTSUP;
8220         /*
8221          * Workaround:
8222          * As no ixgbe_disable_sec_rx_path equivalent is
8223          * implemented for tx in the base code, and we are
8224          * not allowed to modify the base code in DPDK, so
8225          * just call the hand-written one directly for now.
8226          * The hardware support has been checked by
8227          * ixgbe_disable_sec_rx_path().
8228          */
8229         ixgbe_disable_sec_tx_path_generic(hw);
8230
8231         /* Enable Ethernet CRC (required by MACsec offload) */
8232         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8233         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8234         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8235
8236         /* Enable the TX and RX crypto engines */
8237         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8238         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8239         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8240
8241         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8242         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8243         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8244
8245         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8246         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8247         ctrl |= 0x3;
8248         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8249
8250         /* Enable SA lookup */
8251         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8252         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8253         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8254                      IXGBE_LSECTXCTRL_AUTH;
8255         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8256         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8257         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8258         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8259
8260         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8261         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8262         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8263         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8264         if (rp)
8265                 ctrl |= IXGBE_LSECRXCTRL_RP;
8266         else
8267                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8268         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8269
8270         /* Start the data paths */
8271         ixgbe_enable_sec_rx_path(hw);
8272         /*
8273          * Workaround:
8274          * As no ixgbe_enable_sec_rx_path equivalent is
8275          * implemented for tx in the base code, and we are
8276          * not allowed to modify the base code in DPDK, so
8277          * just call the hand-written one directly for now.
8278          */
8279         ixgbe_enable_sec_tx_path_generic(hw);
8280
8281         return 0;
8282 }
8283
8284 int
8285 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8286 {
8287         struct ixgbe_hw *hw;
8288         struct rte_eth_dev *dev;
8289         uint32_t ctrl;
8290
8291         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8292
8293         dev = &rte_eth_devices[port];
8294         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8295
8296         /* Stop the data paths */
8297         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8298                 return -ENOTSUP;
8299         /*
8300          * Workaround:
8301          * As no ixgbe_disable_sec_rx_path equivalent is
8302          * implemented for tx in the base code, and we are
8303          * not allowed to modify the base code in DPDK, so
8304          * just call the hand-written one directly for now.
8305          * The hardware support has been checked by
8306          * ixgbe_disable_sec_rx_path().
8307          */
8308         ixgbe_disable_sec_tx_path_generic(hw);
8309
8310         /* Disable the TX and RX crypto engines */
8311         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8312         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8313         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8314
8315         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8316         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8317         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8318
8319         /* Disable SA lookup */
8320         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8321         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8322         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8323         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8324
8325         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8326         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8327         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8328         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8329
8330         /* Start the data paths */
8331         ixgbe_enable_sec_rx_path(hw);
8332         /*
8333          * Workaround:
8334          * As no ixgbe_enable_sec_rx_path equivalent is
8335          * implemented for tx in the base code, and we are
8336          * not allowed to modify the base code in DPDK, so
8337          * just call the hand-written one directly for now.
8338          */
8339         ixgbe_enable_sec_tx_path_generic(hw);
8340
8341         return 0;
8342 }
8343
8344 int
8345 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8346 {
8347         struct ixgbe_hw *hw;
8348         struct rte_eth_dev *dev;
8349         uint32_t ctrl;
8350
8351         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8352
8353         dev = &rte_eth_devices[port];
8354         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8355
8356         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8357         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8358
8359         ctrl = mac[4] | (mac[5] << 8);
8360         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8361
8362         return 0;
8363 }
8364
8365 int
8366 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8367 {
8368         struct ixgbe_hw *hw;
8369         struct rte_eth_dev *dev;
8370         uint32_t ctrl;
8371
8372         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8373
8374         dev = &rte_eth_devices[port];
8375         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8376
8377         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8378         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8379
8380         pi = rte_cpu_to_be_16(pi);
8381         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8382         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8383
8384         return 0;
8385 }
8386
8387 int
8388 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8389                                  uint32_t pn, uint8_t *key)
8390 {
8391         struct ixgbe_hw *hw;
8392         struct rte_eth_dev *dev;
8393         uint32_t ctrl, i;
8394
8395         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8396
8397         dev = &rte_eth_devices[port];
8398         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8399
8400         if (idx != 0 && idx != 1)
8401                 return -EINVAL;
8402
8403         if (an >= 4)
8404                 return -EINVAL;
8405
8406         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8407
8408         /* Set the PN and key */
8409         pn = rte_cpu_to_be_32(pn);
8410         if (idx == 0) {
8411                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8412
8413                 for (i = 0; i < 4; i++) {
8414                         ctrl = (key[i * 4 + 0] <<  0) |
8415                                (key[i * 4 + 1] <<  8) |
8416                                (key[i * 4 + 2] << 16) |
8417                                (key[i * 4 + 3] << 24);
8418                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8419                 }
8420         } else {
8421                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8422
8423                 for (i = 0; i < 4; i++) {
8424                         ctrl = (key[i * 4 + 0] <<  0) |
8425                                (key[i * 4 + 1] <<  8) |
8426                                (key[i * 4 + 2] << 16) |
8427                                (key[i * 4 + 3] << 24);
8428                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8429                 }
8430         }
8431
8432         /* Set AN and select the SA */
8433         ctrl = (an << idx * 2) | (idx << 4);
8434         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8435
8436         return 0;
8437 }
8438
8439 int
8440 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8441                                  uint32_t pn, uint8_t *key)
8442 {
8443         struct ixgbe_hw *hw;
8444         struct rte_eth_dev *dev;
8445         uint32_t ctrl, i;
8446
8447         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8448
8449         dev = &rte_eth_devices[port];
8450         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8451
8452         if (idx != 0 && idx != 1)
8453                 return -EINVAL;
8454
8455         if (an >= 4)
8456                 return -EINVAL;
8457
8458         /* Set the PN */
8459         pn = rte_cpu_to_be_32(pn);
8460         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8461
8462         /* Set the key */
8463         for (i = 0; i < 4; i++) {
8464                 ctrl = (key[i * 4 + 0] <<  0) |
8465                        (key[i * 4 + 1] <<  8) |
8466                        (key[i * 4 + 2] << 16) |
8467                        (key[i * 4 + 3] << 24);
8468                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8469         }
8470
8471         /* Set the AN and validate the SA */
8472         ctrl = an | (1 << 2);
8473         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8474
8475         return 0;
8476 }
8477
8478 /* restore n-tuple filter */
8479 static inline void
8480 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8481 {
8482         struct ixgbe_filter_info *filter_info =
8483                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8484         struct ixgbe_5tuple_filter *node;
8485
8486         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8487                 ixgbe_inject_5tuple_filter(dev, node);
8488         }
8489 }
8490
8491 /* restore ethernet type filter */
8492 static inline void
8493 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8494 {
8495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8496         struct ixgbe_filter_info *filter_info =
8497                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8498         int i;
8499
8500         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8501                 if (filter_info->ethertype_mask & (1 << i)) {
8502                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8503                                         filter_info->ethertype_filters[i].etqf);
8504                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8505                                         filter_info->ethertype_filters[i].etqs);
8506                         IXGBE_WRITE_FLUSH(hw);
8507                 }
8508         }
8509 }
8510
8511 /* restore SYN filter */
8512 static inline void
8513 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8514 {
8515         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8516         struct ixgbe_filter_info *filter_info =
8517                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8518         uint32_t synqf;
8519
8520         synqf = filter_info->syn_info;
8521
8522         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8523                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8524                 IXGBE_WRITE_FLUSH(hw);
8525         }
8526 }
8527
8528 /* restore L2 tunnel filter */
8529 static inline void
8530 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8531 {
8532         struct ixgbe_l2_tn_info *l2_tn_info =
8533                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8534         struct ixgbe_l2_tn_filter *node;
8535         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8536
8537         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8538                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8539                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8540                 l2_tn_conf.pool           = node->pool;
8541                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8542         }
8543 }
8544
8545 static int
8546 ixgbe_filter_restore(struct rte_eth_dev *dev)
8547 {
8548         ixgbe_ntuple_filter_restore(dev);
8549         ixgbe_ethertype_filter_restore(dev);
8550         ixgbe_syn_filter_restore(dev);
8551         ixgbe_fdir_filter_restore(dev);
8552         ixgbe_l2_tn_filter_restore(dev);
8553
8554         return 0;
8555 }
8556
8557 static void
8558 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8559 {
8560         struct ixgbe_l2_tn_info *l2_tn_info =
8561                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8562         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8563
8564         if (l2_tn_info->e_tag_en)
8565                 (void)ixgbe_e_tag_enable(hw);
8566
8567         if (l2_tn_info->e_tag_fwd_en)
8568                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8569
8570         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8571 }
8572
8573 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8574 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8575 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8576 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8577 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8578 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");