drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 #define IXGBE_HKEY_MAX_INDEX 10
 104
 105 /* Additional timesync values. */
 106 #define NSEC_PER_SEC             1000000000L
 107 #define IXGBE_INCVAL_10GB        0x66666666
 108 #define IXGBE_INCVAL_1GB         0x40000000
 109 #define IXGBE_INCVAL_100         0x50000000
 110 #define IXGBE_INCVAL_SHIFT_10GB  28
 111 #define IXGBE_INCVAL_SHIFT_1GB   24
 112 #define IXGBE_INCVAL_SHIFT_100   21
 113 #define IXGBE_INCVAL_SHIFT_82599 7
 114 #define IXGBE_INCPER_SHIFT_82599 24
 115
 116 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 117
 118 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 119 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 120 #define DEFAULT_ETAG_ETYPE                     0x893f
 121 #define IXGBE_ETAG_ETYPE                       0x00005084
 122 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 123 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 124 #define IXGBE_RAH_ADTYPE                       0x40000000
 125 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 126 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 127 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 128 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 129 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 130 #define IXGBE_VTEICR_MASK                      0x07
 131
 132 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 133 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 134
 135 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 136 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 154                                 int wait_to_complete);
 155 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *stats);
 157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstat *xstats, unsigned n);
 159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 160                                   struct rte_eth_xstat *xstats, unsigned n);
 161 static int
 162 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 163                 uint64_t *values, unsigned int n);
 164 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         unsigned int size);
 169 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 171 static int ixgbe_dev_xstats_get_names_by_id(
 172         struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names,
 174         const uint64_t *ids,
 175         unsigned int limit);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 181                                  size_t fw_size);
 182 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 183                                struct rte_eth_dev_info *dev_info);
 184 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 185 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 186                                  struct rte_eth_dev_info *dev_info);
 187 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 188
 189 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 190                 uint16_t vlan_id, int on);
 191 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 192                                enum rte_vlan_type vlan_type,
 193                                uint16_t tpid_id);
 194 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 195                 uint16_t queue, bool on);
 196 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 197                 int on);
 198 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 200 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 201 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 202 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 203
 204 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 205 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 206 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 209                                struct rte_eth_fc_conf *fc_conf);
 210 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 211                 struct rte_eth_pfc_conf *pfc_conf);
 212 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 220 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 224                                       struct rte_intr_handle *handle);
 225 static void ixgbe_dev_interrupt_handler(void *param);
 226 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 227 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 228                          uint32_t index, uint32_t pool);
 229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 230 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 231                                            struct ether_addr *mac_addr);
 232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 233 static bool is_device_supported(struct rte_eth_dev *dev,
 234                                 struct rte_pci_driver *drv);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 242                                    int wait_to_complete);
 243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 247 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 249                 struct rte_eth_stats *stats);
 250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 252                 uint16_t vlan_id, int on);
 253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                 uint16_t queue, int on);
 255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 258                                             uint16_t queue_id);
 259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 260                                              uint16_t queue_id);
 261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 262                                  uint8_t queue, uint8_t msix_vector);
 263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 266
 267 /* For Eth VMDQ APIs support */
 268 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 269                 ether_addr * mac_addr, uint8_t on);
 270 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 271 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 272                 struct rte_eth_mirror_conf *mirror_conf,
 273                 uint8_t rule_id, uint8_t on);
 274 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 275                 uint8_t rule_id);
 276 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                           uint16_t queue_id);
 278 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                            uint16_t queue_id);
 280 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                uint8_t queue, uint8_t msix_vector);
 282 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 283
 284 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                 struct ether_addr *mac_addr,
 286                                 uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter);
 292 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 293                         enum rte_filter_op filter_op,
 294                         void *arg);
 295 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 298                         struct ixgbe_5tuple_filter *filter);
 299 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 300                                 enum rte_filter_op filter_op,
 301                                 void *arg);
 302 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter);
 304 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 305                                 enum rte_filter_op filter_op,
 306                                 void *arg);
 307 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 308                         struct rte_eth_ethertype_filter *filter);
 309 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 310                      enum rte_filter_type filter_type,
 311                      enum rte_filter_op filter_op,
 312                      void *arg);
 313 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 314
 315 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 316                                       struct ether_addr *mc_addr_set,
 317                                       uint32_t nb_mc_addr);
 318 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 319                                    struct rte_eth_dcb_info *dcb_info);
 320
 321 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 323                             struct rte_dev_reg_info *regs);
 324 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 325 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 328                                 struct rte_dev_eeprom_info *eeprom);
 329
 330 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 331 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 332                                 struct rte_dev_reg_info *regs);
 333
 334 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 335 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 337                                             struct timespec *timestamp,
 338                                             uint32_t flags);
 339 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp);
 341 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 342 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 343                                    struct timespec *timestamp);
 344 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 345                                    const struct timespec *timestamp);
 346 static void ixgbevf_dev_interrupt_handler(void *param);
 347
 348 static int ixgbe_dev_l2_tunnel_eth_type_conf
 349         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 350 static int ixgbe_dev_l2_tunnel_offload_set
 351         (struct rte_eth_dev *dev,
 352          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 353          uint32_t mask,
 354          uint8_t en);
 355 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 356                                              enum rte_filter_op filter_op,
 357                                              void *arg);
 358
 359 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 360                                          struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 364 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 365
 366 /*
 367  * Define VF Stats MACRO for Non "cleared on read" register
 368  */
 369 #define UPDATE_VF_STAT(reg, last, cur)                          \
 370 {                                                               \
 371         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 372         cur += (latest - last) & UINT_MAX;                      \
 373         last = latest;                                          \
 374 }
 375
 376 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 377 {                                                                \
 378         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 379         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 380         u64 latest = ((new_msb << 32) | new_lsb);                \
 381         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 382         last = latest;                                           \
 383 }
 384
 385 #define IXGBE_SET_HWSTRIP(h, q) do {\
 386                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 387                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 388                 (h)->bitmap[idx] |= 1 << bit;\
 389         } while (0)
 390
 391 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 392                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] &= ~(1 << bit);\
 395         } while (0)
 396
 397 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 398                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 400                 (r) = (h)->bitmap[idx] >> bit & 1;\
 401         } while (0)
 402
 403 int ixgbe_logtype_init;
 404 int ixgbe_logtype_driver;
 405
 406 /*
 407  * The set of PCI devices this driver supports
 408  */
 409 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 458 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 460 #endif
 461         { .vendor_id = 0, /* sentinel */ },
 462 };
 463
 464 /*
 465  * The set of PCI devices this driver supports (for 82599 VF)
 466  */
 467 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct rte_eth_desc_lim rx_desc_lim = {
 482         .nb_max = IXGBE_MAX_RING_DESC,
 483         .nb_min = IXGBE_MIN_RING_DESC,
 484         .nb_align = IXGBE_RXD_ALIGN,
 485 };
 486
 487 static const struct rte_eth_desc_lim tx_desc_lim = {
 488         .nb_max = IXGBE_MAX_RING_DESC,
 489         .nb_min = IXGBE_MIN_RING_DESC,
 490         .nb_align = IXGBE_TXD_ALIGN,
 491         .nb_seg_max = IXGBE_TX_MAX_SEG,
 492         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 493 };
 494
 495 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 496         .dev_configure        = ixgbe_dev_configure,
 497         .dev_start            = ixgbe_dev_start,
 498         .dev_stop             = ixgbe_dev_stop,
 499         .dev_set_link_up    = ixgbe_dev_set_link_up,
 500         .dev_set_link_down  = ixgbe_dev_set_link_down,
 501         .dev_close            = ixgbe_dev_close,
 502         .dev_reset            = ixgbe_dev_reset,
 503         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 504         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 505         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 506         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 507         .link_update          = ixgbe_dev_link_update,
 508         .stats_get            = ixgbe_dev_stats_get,
 509         .xstats_get           = ixgbe_dev_xstats_get,
 510         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 511         .stats_reset          = ixgbe_dev_stats_reset,
 512         .xstats_reset         = ixgbe_dev_xstats_reset,
 513         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 514         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 515         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 516         .fw_version_get       = ixgbe_fw_version_get,
 517         .dev_infos_get        = ixgbe_dev_info_get,
 518         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 519         .mtu_set              = ixgbe_dev_mtu_set,
 520         .vlan_filter_set      = ixgbe_vlan_filter_set,
 521         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 522         .vlan_offload_set     = ixgbe_vlan_offload_set,
 523         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 524         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 525         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 526         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 527         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 528         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 529         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 530         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 531         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 532         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 533         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 534         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 535         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 536         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 537         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 538         .dev_led_on           = ixgbe_dev_led_on,
 539         .dev_led_off          = ixgbe_dev_led_off,
 540         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 541         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 542         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 543         .mac_addr_add         = ixgbe_add_rar,
 544         .mac_addr_remove      = ixgbe_remove_rar,
 545         .mac_addr_set         = ixgbe_set_default_mac_addr,
 546         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 547         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 548         .mirror_rule_set      = ixgbe_mirror_rule_set,
 549         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 550         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 551         .reta_update          = ixgbe_dev_rss_reta_update,
 552         .reta_query           = ixgbe_dev_rss_reta_query,
 553         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 554         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 555         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 556         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 557         .rxq_info_get         = ixgbe_rxq_info_get,
 558         .txq_info_get         = ixgbe_txq_info_get,
 559         .timesync_enable      = ixgbe_timesync_enable,
 560         .timesync_disable     = ixgbe_timesync_disable,
 561         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 562         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 563         .get_reg              = ixgbe_get_regs,
 564         .get_eeprom_length    = ixgbe_get_eeprom_length,
 565         .get_eeprom           = ixgbe_get_eeprom,
 566         .set_eeprom           = ixgbe_set_eeprom,
 567         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 568         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 569         .timesync_read_time   = ixgbe_timesync_read_time,
 570         .timesync_write_time  = ixgbe_timesync_write_time,
 571         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 572         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 573         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 574         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 575         .tm_ops_get           = ixgbe_tm_ops_get,
 576 };
 577
 578 /*
 579  * dev_ops for virtual function, bare necessities for basic vf
 580  * operation have been implemented
 581  */
 582 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 583         .dev_configure        = ixgbevf_dev_configure,
 584         .dev_start            = ixgbevf_dev_start,
 585         .dev_stop             = ixgbevf_dev_stop,
 586         .link_update          = ixgbevf_dev_link_update,
 587         .stats_get            = ixgbevf_dev_stats_get,
 588         .xstats_get           = ixgbevf_dev_xstats_get,
 589         .stats_reset          = ixgbevf_dev_stats_reset,
 590         .xstats_reset         = ixgbevf_dev_stats_reset,
 591         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 592         .dev_close            = ixgbevf_dev_close,
 593         .dev_reset            = ixgbevf_dev_reset,
 594         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 595         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 596         .dev_infos_get        = ixgbevf_dev_info_get,
 597         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 598         .mtu_set              = ixgbevf_dev_set_mtu,
 599         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 600         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 601         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 602         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 603         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 604         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 605         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 606         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 607         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 608         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 609         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 610         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 611         .mac_addr_add         = ixgbevf_add_mac_addr,
 612         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 613         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 614         .rxq_info_get         = ixgbe_rxq_info_get,
 615         .txq_info_get         = ixgbe_txq_info_get,
 616         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 617         .get_reg              = ixgbevf_get_regs,
 618         .reta_update          = ixgbe_dev_rss_reta_update,
 619         .reta_query           = ixgbe_dev_rss_reta_query,
 620         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 621         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 622 };
 623
 624 /* store statistics names and its offset in stats structure */
 625 struct rte_ixgbe_xstats_name_off {
 626         char name[RTE_ETH_XSTATS_NAME_SIZE];
 627         unsigned offset;
 628 };
 629
 630 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 631         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 632         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 633         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 634         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 635         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 636         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 637         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 638         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 639         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 640         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 641         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 642         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 643         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 644         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 645         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 646                 prc1023)},
 647         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 648                 prc1522)},
 649         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 650         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 651         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 652         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 653         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 654         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 655         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 656         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 657         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 658         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 659         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 660         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 661         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 662         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 663         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 664         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 665         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 666                 ptc1023)},
 667         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 668                 ptc1522)},
 669         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 670         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 671         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 672         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 673
 674         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 675                 fdirustat_add)},
 676         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 677                 fdirustat_remove)},
 678         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 679                 fdirfstat_fadd)},
 680         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 681                 fdirfstat_fremove)},
 682         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 683                 fdirmatch)},
 684         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 685                 fdirmiss)},
 686
 687         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 688         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 689         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 690                 fclast)},
 691         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 692         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 693         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 694         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 695         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 696                 fcoe_noddp)},
 697         {"rx_fcoe_no_direct_data_placement_ext_buff",
 698                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 699
 700         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 701                 lxontxc)},
 702         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 703                 lxonrxc)},
 704         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxofftxc)},
 706         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxoffrxc)},
 708         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 709 };
 710
 711 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 712                            sizeof(rte_ixgbe_stats_strings[0]))
 713
 714 /* MACsec statistics */
 715 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 716         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 717                 out_pkts_untagged)},
 718         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 719                 out_pkts_encrypted)},
 720         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_protected)},
 722         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_octets_encrypted)},
 724         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_octets_protected)},
 726         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_untagged)},
 728         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_badtag)},
 730         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_nosci)},
 732         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_unknownsci)},
 734         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 735                 in_octets_decrypted)},
 736         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 737                 in_octets_validated)},
 738         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_unchecked)},
 740         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_delayed)},
 742         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_late)},
 744         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_ok)},
 746         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_invalid)},
 748         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_notvalid)},
 750         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_unusedsa)},
 752         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notusingsa)},
 754 };
 755
 756 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 757                            sizeof(rte_ixgbe_macsec_strings[0]))
 758
 759 /* Per-queue statistics */
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 761         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 762         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 763         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 764         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 765 };
 766
 767 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 768                            sizeof(rte_ixgbe_rxq_strings[0]))
 769 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 772         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 773         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 774         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 775                 pxon2offc)},
 776 };
 777
 778 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 779                            sizeof(rte_ixgbe_txq_strings[0]))
 780 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 781
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 783         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 784 };
 785
 786 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 787                 sizeof(rte_ixgbevf_stats_strings[0]))
 788
 789 /*
 790  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 791  */
 792 static inline int
 793 ixgbe_is_sfp(struct ixgbe_hw *hw)
 794 {
 795         switch (hw->phy.type) {
 796         case ixgbe_phy_sfp_avago:
 797         case ixgbe_phy_sfp_ftl:
 798         case ixgbe_phy_sfp_intel:
 799         case ixgbe_phy_sfp_unknown:
 800         case ixgbe_phy_sfp_passive_tyco:
 801         case ixgbe_phy_sfp_passive_unknown:
 802                 return 1;
 803         default:
 804                 return 0;
 805         }
 806 }
 807
 808 static inline int32_t
 809 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 810 {
 811         uint32_t ctrl_ext;
 812         int32_t status;
 813
 814         status = ixgbe_reset_hw(hw);
 815
 816         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 817         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 818         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 819         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 820         IXGBE_WRITE_FLUSH(hw);
 821
 822         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 823                 status = IXGBE_SUCCESS;
 824         return status;
 825 }
 826
 827 static inline void
 828 ixgbe_enable_intr(struct rte_eth_dev *dev)
 829 {
 830         struct ixgbe_interrupt *intr =
 831                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 832         struct ixgbe_hw *hw =
 833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 834
 835         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 836         IXGBE_WRITE_FLUSH(hw);
 837 }
 838
 839 /*
 840  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 841  */
 842 static void
 843 ixgbe_disable_intr(struct ixgbe_hw *hw)
 844 {
 845         PMD_INIT_FUNC_TRACE();
 846
 847         if (hw->mac.type == ixgbe_mac_82598EB) {
 848                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 849         } else {
 850                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 853         }
 854         IXGBE_WRITE_FLUSH(hw);
 855 }
 856
 857 /*
 858  * This function resets queue statistics mapping registers.
 859  * From Niantic datasheet, Initialization of Statistics section:
 860  * "...if software requires the queue counters, the RQSMR and TQSM registers
 861  * must be re-programmed following a device reset.
 862  */
 863 static void
 864 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 865 {
 866         uint32_t i;
 867
 868         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 869                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 870                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 871         }
 872 }
 873
 874
 875 static int
 876 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 877                                   uint16_t queue_id,
 878                                   uint8_t stat_idx,
 879                                   uint8_t is_rx)
 880 {
 881 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 882 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 883 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 884
 885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 886         struct ixgbe_stat_mapping_registers *stat_mappings =
 887                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 888         uint32_t qsmr_mask = 0;
 889         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 890         uint32_t q_map;
 891         uint8_t n, offset;
 892
 893         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 894                 (hw->mac.type != ixgbe_mac_X540) &&
 895                 (hw->mac.type != ixgbe_mac_X550) &&
 896                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 897                 (hw->mac.type != ixgbe_mac_X550EM_a))
 898                 return -ENOSYS;
 899
 900         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 901                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 902                      queue_id, stat_idx);
 903
 904         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 905         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 906                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 907                 return -EIO;
 908         }
 909         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 910
 911         /* Now clear any previous stat_idx set */
 912         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 913         if (!is_rx)
 914                 stat_mappings->tqsm[n] &= ~clearing_mask;
 915         else
 916                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 917
 918         q_map = (uint32_t)stat_idx;
 919         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 920         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 921         if (!is_rx)
 922                 stat_mappings->tqsm[n] |= qsmr_mask;
 923         else
 924                 stat_mappings->rqsmr[n] |= qsmr_mask;
 925
 926         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 927                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 928                      queue_id, stat_idx);
 929         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 930                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 931
 932         /* Now write the mapping in the appropriate register */
 933         if (is_rx) {
 934                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 935                              stat_mappings->rqsmr[n], n);
 936                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 937         } else {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 939                              stat_mappings->tqsm[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 941         }
 942         return 0;
 943 }
 944
 945 static void
 946 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 947 {
 948         struct ixgbe_stat_mapping_registers *stat_mappings =
 949                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951         int i;
 952
 953         /* write whatever was in stat mapping table to the NIC */
 954         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 /* rx */
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 957
 958                 /* tx */
 959                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 960         }
 961 }
 962
 963 static void
 964 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 965 {
 966         uint8_t i;
 967         struct ixgbe_dcb_tc_config *tc;
 968         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 969
 970         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 971         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 972         for (i = 0; i < dcb_max_tc; i++) {
 973                 tc = &dcb_config->tc_config[i];
 974                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 975                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 976                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 977                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 978                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 979                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 980                 tc->pfc = ixgbe_dcb_pfc_disabled;
 981         }
 982
 983         /* Initialize default user to priority mapping, UPx->TC0 */
 984         tc = &dcb_config->tc_config[0];
 985         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 986         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 987         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 988                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 989                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 990         }
 991         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 992         dcb_config->pfc_mode_enable = false;
 993         dcb_config->vt_mode = true;
 994         dcb_config->round_robin_enable = false;
 995         /* support all DCB capabilities in 82599 */
 996         dcb_config->support.capabilities = 0xFF;
 997
 998         /*we only support 4 Tcs for X540, X550 */
 999         if (hw->mac.type == ixgbe_mac_X540 ||
1000                 hw->mac.type == ixgbe_mac_X550 ||
1001                 hw->mac.type == ixgbe_mac_X550EM_x ||
1002                 hw->mac.type == ixgbe_mac_X550EM_a) {
1003                 dcb_config->num_tcs.pg_tcs = 4;
1004                 dcb_config->num_tcs.pfc_tcs = 4;
1005         }
1006 }
1007
1008 /*
1009  * Ensure that all locks are released before first NVM or PHY access
1010  */
1011 static void
1012 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1013 {
1014         uint16_t mask;
1015
1016         /*
1017          * Phy lock should not fail in this early stage. If this is the case,
1018          * it is due to an improper exit of the application.
1019          * So force the release of the faulty lock. Release of common lock
1020          * is done automatically by swfw_sync function.
1021          */
1022         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1023         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1024                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1025         }
1026         ixgbe_release_swfw_semaphore(hw, mask);
1027
1028         /*
1029          * These ones are more tricky since they are common to all ports; but
1030          * swfw_sync retries last long enough (1s) to be almost sure that if
1031          * lock can not be taken it is due to an improper lock of the
1032          * semaphore.
1033          */
1034         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1035         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1037         }
1038         ixgbe_release_swfw_semaphore(hw, mask);
1039 }
1040
1041 /*
1042  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1043  * It returns 0 on success.
1044  */
1045 static int
1046 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1047 {
1048         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1049         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1050         struct ixgbe_hw *hw =
1051                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1052         struct ixgbe_vfta *shadow_vfta =
1053                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1054         struct ixgbe_hwstrip *hwstrip =
1055                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1056         struct ixgbe_dcb_config *dcb_config =
1057                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1058         struct ixgbe_filter_info *filter_info =
1059                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1060         struct ixgbe_bw_conf *bw_conf =
1061                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1062         uint32_t ctrl_ext;
1063         uint16_t csum;
1064         int diag, i;
1065
1066         PMD_INIT_FUNC_TRACE();
1067
1068         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1069         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1070         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1071         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1072
1073         /*
1074          * For secondary processes, we don't initialise any further as primary
1075          * has already done this work. Only check we don't need a different
1076          * RX and TX function.
1077          */
1078         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1079                 struct ixgbe_tx_queue *txq;
1080                 /* TX queue function in primary, set by last queue initialized
1081                  * Tx queue may not initialized by primary process
1082                  */
1083                 if (eth_dev->data->tx_queues) {
1084                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1085                         ixgbe_set_tx_function(eth_dev, txq);
1086                 } else {
1087                         /* Use default TX function if we get here */
1088                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1089                                      "Using default TX function.");
1090                 }
1091
1092                 ixgbe_set_rx_function(eth_dev);
1093
1094                 return 0;
1095         }
1096
1097         rte_eth_copy_pci_info(eth_dev, pci_dev);
1098
1099         /* Vendor and Device ID need to be set before init of shared code */
1100         hw->device_id = pci_dev->id.device_id;
1101         hw->vendor_id = pci_dev->id.vendor_id;
1102         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1103         hw->allow_unsupported_sfp = 1;
1104
1105         /* Initialize the shared code (base driver) */
1106 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1107         diag = ixgbe_bypass_init_shared_code(hw);
1108 #else
1109         diag = ixgbe_init_shared_code(hw);
1110 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1111
1112         if (diag != IXGBE_SUCCESS) {
1113                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1114                 return -EIO;
1115         }
1116
1117         /* pick up the PCI bus settings for reporting later */
1118         ixgbe_get_bus_info(hw);
1119
1120         /* Unlock any pending hardware semaphore */
1121         ixgbe_swfw_lock_reset(hw);
1122
1123 #ifdef RTE_LIBRTE_SECURITY
1124         /* Initialize security_ctx only for primary process*/
1125         if (ixgbe_ipsec_ctx_create(eth_dev))
1126                 return -ENOMEM;
1127 #endif
1128
1129         /* Initialize DCB configuration*/
1130         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1131         ixgbe_dcb_init(hw, dcb_config);
1132         /* Get Hardware Flow Control setting */
1133         hw->fc.requested_mode = ixgbe_fc_full;
1134         hw->fc.current_mode = ixgbe_fc_full;
1135         hw->fc.pause_time = IXGBE_FC_PAUSE;
1136         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1137                 hw->fc.low_water[i] = IXGBE_FC_LO;
1138                 hw->fc.high_water[i] = IXGBE_FC_HI;
1139         }
1140         hw->fc.send_xon = 1;
1141
1142         /* Make sure we have a good EEPROM before we read from it */
1143         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1144         if (diag != IXGBE_SUCCESS) {
1145                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1146                 return -EIO;
1147         }
1148
1149 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1150         diag = ixgbe_bypass_init_hw(hw);
1151 #else
1152         diag = ixgbe_init_hw(hw);
1153 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1154
1155         /*
1156          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1157          * is called too soon after the kernel driver unbinding/binding occurs.
1158          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1159          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1160          * also called. See ixgbe_identify_phy_82599(). The reason for the
1161          * failure is not known, and only occuts when virtualisation features
1162          * are disabled in the bios. A delay of 100ms  was found to be enough by
1163          * trial-and-error, and is doubled to be safe.
1164          */
1165         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1166                 rte_delay_ms(200);
1167                 diag = ixgbe_init_hw(hw);
1168         }
1169
1170         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1171                 diag = IXGBE_SUCCESS;
1172
1173         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1174                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1175                              "LOM.  Please be aware there may be issues associated "
1176                              "with your hardware.");
1177                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1178                              "please contact your Intel or hardware representative "
1179                              "who provided you with this hardware.");
1180         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1181                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1182         if (diag) {
1183                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1184                 return -EIO;
1185         }
1186
1187         /* Reset the hw statistics */
1188         ixgbe_dev_stats_reset(eth_dev);
1189
1190         /* disable interrupt */
1191         ixgbe_disable_intr(hw);
1192
1193         /* reset mappings for queue statistics hw counters*/
1194         ixgbe_reset_qstat_mappings(hw);
1195
1196         /* Allocate memory for storing MAC addresses */
1197         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1198                                                hw->mac.num_rar_entries, 0);
1199         if (eth_dev->data->mac_addrs == NULL) {
1200                 PMD_INIT_LOG(ERR,
1201                              "Failed to allocate %u bytes needed to store "
1202                              "MAC addresses",
1203                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1204                 return -ENOMEM;
1205         }
1206         /* Copy the permanent MAC address */
1207         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1208                         &eth_dev->data->mac_addrs[0]);
1209
1210         /* Allocate memory for storing hash filter MAC addresses */
1211         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1212                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1213         if (eth_dev->data->hash_mac_addrs == NULL) {
1214                 PMD_INIT_LOG(ERR,
1215                              "Failed to allocate %d bytes needed to store MAC addresses",
1216                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1217                 return -ENOMEM;
1218         }
1219
1220         /* initialize the vfta */
1221         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1222
1223         /* initialize the hw strip bitmap*/
1224         memset(hwstrip, 0, sizeof(*hwstrip));
1225
1226         /* initialize PF if max_vfs not zero */
1227         ixgbe_pf_host_init(eth_dev);
1228
1229         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1230         /* let hardware know driver is loaded */
1231         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1232         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1233         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1234         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1235         IXGBE_WRITE_FLUSH(hw);
1236
1237         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1238                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1239                              (int) hw->mac.type, (int) hw->phy.type,
1240                              (int) hw->phy.sfp_type);
1241         else
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type);
1244
1245         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1246                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1247                      pci_dev->id.device_id);
1248
1249         rte_intr_callback_register(intr_handle,
1250                                    ixgbe_dev_interrupt_handler, eth_dev);
1251
1252         /* enable uio/vfio intr/eventfd mapping */
1253         rte_intr_enable(intr_handle);
1254
1255         /* enable support intr */
1256         ixgbe_enable_intr(eth_dev);
1257
1258         /* initialize filter info */
1259         memset(filter_info, 0,
1260                sizeof(struct ixgbe_filter_info));
1261
1262         /* initialize 5tuple filter list */
1263         TAILQ_INIT(&filter_info->fivetuple_list);
1264
1265         /* initialize flow director filter list & hash */
1266         ixgbe_fdir_filter_init(eth_dev);
1267
1268         /* initialize l2 tunnel filter list & hash */
1269         ixgbe_l2_tn_filter_init(eth_dev);
1270
1271         /* initialize flow filter lists */
1272         ixgbe_filterlist_init();
1273
1274         /* initialize bandwidth configuration info */
1275         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1276
1277         /* initialize Traffic Manager configuration */
1278         ixgbe_tm_conf_init(eth_dev);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1285 {
1286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1287         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288         struct ixgbe_hw *hw;
1289         int retries = 0;
1290         int ret;
1291
1292         PMD_INIT_FUNC_TRACE();
1293
1294         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1295                 return -EPERM;
1296
1297         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1298
1299         if (hw->adapter_stopped == 0)
1300                 ixgbe_dev_close(eth_dev);
1301
1302         eth_dev->dev_ops = NULL;
1303         eth_dev->rx_pkt_burst = NULL;
1304         eth_dev->tx_pkt_burst = NULL;
1305
1306         /* Unlock any pending hardware semaphore */
1307         ixgbe_swfw_lock_reset(hw);
1308
1309         /* disable uio intr before callback unregister */
1310         rte_intr_disable(intr_handle);
1311
1312         do {
1313                 ret = rte_intr_callback_unregister(intr_handle,
1314                                 ixgbe_dev_interrupt_handler, eth_dev);
1315                 if (ret >= 0) {
1316                         break;
1317                 } else if (ret != -EAGAIN) {
1318                         PMD_INIT_LOG(ERR,
1319                                 "intr callback unregister failed: %d",
1320                                 ret);
1321                         return ret;
1322                 }
1323                 rte_delay_ms(100);
1324         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1325
1326         /* uninitialize PF if max_vfs not zero */
1327         ixgbe_pf_host_uninit(eth_dev);
1328
1329         rte_free(eth_dev->data->mac_addrs);
1330         eth_dev->data->mac_addrs = NULL;
1331
1332         rte_free(eth_dev->data->hash_mac_addrs);
1333         eth_dev->data->hash_mac_addrs = NULL;
1334
1335         /* remove all the fdir filters & hash */
1336         ixgbe_fdir_filter_uninit(eth_dev);
1337
1338         /* remove all the L2 tunnel filters & hash */
1339         ixgbe_l2_tn_filter_uninit(eth_dev);
1340
1341         /* Remove all ntuple filters of the device */
1342         ixgbe_ntuple_filter_uninit(eth_dev);
1343
1344         /* clear all the filters list */
1345         ixgbe_filterlist_flush();
1346
1347         /* Remove all Traffic Manager configuration */
1348         ixgbe_tm_conf_uninit(eth_dev);
1349
1350 #ifdef RTE_LIBRTE_SECURITY
1351         rte_free(eth_dev->security_ctx);
1352 #endif
1353
1354         return 0;
1355 }
1356
1357 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct ixgbe_filter_info *filter_info =
1360                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1361         struct ixgbe_5tuple_filter *p_5tuple;
1362
1363         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1364                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1365                              p_5tuple,
1366                              entries);
1367                 rte_free(p_5tuple);
1368         }
1369         memset(filter_info->fivetuple_mask, 0,
1370                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1371
1372         return 0;
1373 }
1374
1375 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1376 {
1377         struct ixgbe_hw_fdir_info *fdir_info =
1378                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1379         struct ixgbe_fdir_filter *fdir_filter;
1380
1381                 if (fdir_info->hash_map)
1382                 rte_free(fdir_info->hash_map);
1383         if (fdir_info->hash_handle)
1384                 rte_hash_free(fdir_info->hash_handle);
1385
1386         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1387                 TAILQ_REMOVE(&fdir_info->fdir_list,
1388                              fdir_filter,
1389                              entries);
1390                 rte_free(fdir_filter);
1391         }
1392
1393         return 0;
1394 }
1395
1396 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1397 {
1398         struct ixgbe_l2_tn_info *l2_tn_info =
1399                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1400         struct ixgbe_l2_tn_filter *l2_tn_filter;
1401
1402         if (l2_tn_info->hash_map)
1403                 rte_free(l2_tn_info->hash_map);
1404         if (l2_tn_info->hash_handle)
1405                 rte_hash_free(l2_tn_info->hash_handle);
1406
1407         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1408                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1409                              l2_tn_filter,
1410                              entries);
1411                 rte_free(l2_tn_filter);
1412         }
1413
1414         return 0;
1415 }
1416
1417 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1418 {
1419         struct ixgbe_hw_fdir_info *fdir_info =
1420                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1421         char fdir_hash_name[RTE_HASH_NAMESIZE];
1422         struct rte_hash_parameters fdir_hash_params = {
1423                 .name = fdir_hash_name,
1424                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1425                 .key_len = sizeof(union ixgbe_atr_input),
1426                 .hash_func = rte_hash_crc,
1427                 .hash_func_init_val = 0,
1428                 .socket_id = rte_socket_id(),
1429         };
1430
1431         TAILQ_INIT(&fdir_info->fdir_list);
1432         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1433                  "fdir_%s", eth_dev->device->name);
1434         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1435         if (!fdir_info->hash_handle) {
1436                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1437                 return -EINVAL;
1438         }
1439         fdir_info->hash_map = rte_zmalloc("ixgbe",
1440                                           sizeof(struct ixgbe_fdir_filter *) *
1441                                           IXGBE_MAX_FDIR_FILTER_NUM,
1442                                           0);
1443         if (!fdir_info->hash_map) {
1444                 PMD_INIT_LOG(ERR,
1445                              "Failed to allocate memory for fdir hash map!");
1446                 return -ENOMEM;
1447         }
1448         fdir_info->mask_added = FALSE;
1449
1450         return 0;
1451 }
1452
1453 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1454 {
1455         struct ixgbe_l2_tn_info *l2_tn_info =
1456                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1457         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1458         struct rte_hash_parameters l2_tn_hash_params = {
1459                 .name = l2_tn_hash_name,
1460                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1461                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1462                 .hash_func = rte_hash_crc,
1463                 .hash_func_init_val = 0,
1464                 .socket_id = rte_socket_id(),
1465         };
1466
1467         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1468         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1469                  "l2_tn_%s", eth_dev->device->name);
1470         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1471         if (!l2_tn_info->hash_handle) {
1472                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1473                 return -EINVAL;
1474         }
1475         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1476                                    sizeof(struct ixgbe_l2_tn_filter *) *
1477                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1478                                    0);
1479         if (!l2_tn_info->hash_map) {
1480                 PMD_INIT_LOG(ERR,
1481                         "Failed to allocate memory for L2 TN hash map!");
1482                 return -ENOMEM;
1483         }
1484         l2_tn_info->e_tag_en = FALSE;
1485         l2_tn_info->e_tag_fwd_en = FALSE;
1486         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1487
1488         return 0;
1489 }
1490 /*
1491  * Negotiate mailbox API version with the PF.
1492  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1493  * Then we try to negotiate starting with the most recent one.
1494  * If all negotiation attempts fail, then we will proceed with
1495  * the default one (ixgbe_mbox_api_10).
1496  */
1497 static void
1498 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1499 {
1500         int32_t i;
1501
1502         /* start with highest supported, proceed down */
1503         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1504                 ixgbe_mbox_api_12,
1505                 ixgbe_mbox_api_11,
1506                 ixgbe_mbox_api_10,
1507         };
1508
1509         for (i = 0;
1510                         i != RTE_DIM(sup_ver) &&
1511                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1512                         i++)
1513                 ;
1514 }
1515
1516 static void
1517 generate_random_mac_addr(struct ether_addr *mac_addr)
1518 {
1519         uint64_t random;
1520
1521         /* Set Organizationally Unique Identifier (OUI) prefix. */
1522         mac_addr->addr_bytes[0] = 0x00;
1523         mac_addr->addr_bytes[1] = 0x09;
1524         mac_addr->addr_bytes[2] = 0xC0;
1525         /* Force indication of locally assigned MAC address. */
1526         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1527         /* Generate the last 3 bytes of the MAC address with a random number. */
1528         random = rte_rand();
1529         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1530 }
1531
1532 /*
1533  * Virtual Function device init
1534  */
1535 static int
1536 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1537 {
1538         int diag;
1539         uint32_t tc, tcs;
1540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542         struct ixgbe_hw *hw =
1543                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1544         struct ixgbe_vfta *shadow_vfta =
1545                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1546         struct ixgbe_hwstrip *hwstrip =
1547                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1548         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1549
1550         PMD_INIT_FUNC_TRACE();
1551
1552         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1553         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1554         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1555
1556         /* for secondary processes, we don't initialise any further as primary
1557          * has already done this work. Only check we don't need a different
1558          * RX function
1559          */
1560         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1561                 struct ixgbe_tx_queue *txq;
1562                 /* TX queue function in primary, set by last queue initialized
1563                  * Tx queue may not initialized by primary process
1564                  */
1565                 if (eth_dev->data->tx_queues) {
1566                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1567                         ixgbe_set_tx_function(eth_dev, txq);
1568                 } else {
1569                         /* Use default TX function if we get here */
1570                         PMD_INIT_LOG(NOTICE,
1571                                      "No TX queues configured yet. Using default TX function.");
1572                 }
1573
1574                 ixgbe_set_rx_function(eth_dev);
1575
1576                 return 0;
1577         }
1578
1579         rte_eth_copy_pci_info(eth_dev, pci_dev);
1580
1581         hw->device_id = pci_dev->id.device_id;
1582         hw->vendor_id = pci_dev->id.vendor_id;
1583         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1584
1585         /* initialize the vfta */
1586         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1587
1588         /* initialize the hw strip bitmap*/
1589         memset(hwstrip, 0, sizeof(*hwstrip));
1590
1591         /* Initialize the shared code (base driver) */
1592         diag = ixgbe_init_shared_code(hw);
1593         if (diag != IXGBE_SUCCESS) {
1594                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1595                 return -EIO;
1596         }
1597
1598         /* init_mailbox_params */
1599         hw->mbx.ops.init_params(hw);
1600
1601         /* Reset the hw statistics */
1602         ixgbevf_dev_stats_reset(eth_dev);
1603
1604         /* Disable the interrupts for VF */
1605         ixgbevf_intr_disable(hw);
1606
1607         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1608         diag = hw->mac.ops.reset_hw(hw);
1609
1610         /*
1611          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1612          * the underlying PF driver has not assigned a MAC address to the VF.
1613          * In this case, assign a random MAC address.
1614          */
1615         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1616                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1617                 return diag;
1618         }
1619
1620         /* negotiate mailbox API version to use with the PF. */
1621         ixgbevf_negotiate_api(hw);
1622
1623         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1624         ixgbevf_get_queues(hw, &tcs, &tc);
1625
1626         /* Allocate memory for storing MAC addresses */
1627         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1628                                                hw->mac.num_rar_entries, 0);
1629         if (eth_dev->data->mac_addrs == NULL) {
1630                 PMD_INIT_LOG(ERR,
1631                              "Failed to allocate %u bytes needed to store "
1632                              "MAC addresses",
1633                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1634                 return -ENOMEM;
1635         }
1636
1637         /* Generate a random MAC address, if none was assigned by PF. */
1638         if (is_zero_ether_addr(perm_addr)) {
1639                 generate_random_mac_addr(perm_addr);
1640                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1641                 if (diag) {
1642                         rte_free(eth_dev->data->mac_addrs);
1643                         eth_dev->data->mac_addrs = NULL;
1644                         return diag;
1645                 }
1646                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1647                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1648                              "%02x:%02x:%02x:%02x:%02x:%02x",
1649                              perm_addr->addr_bytes[0],
1650                              perm_addr->addr_bytes[1],
1651                              perm_addr->addr_bytes[2],
1652                              perm_addr->addr_bytes[3],
1653                              perm_addr->addr_bytes[4],
1654                              perm_addr->addr_bytes[5]);
1655         }
1656
1657         /* Copy the permanent MAC address */
1658         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1659
1660         /* reset the hardware with the new settings */
1661         diag = hw->mac.ops.start_hw(hw);
1662         switch (diag) {
1663         case  0:
1664                 break;
1665
1666         default:
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return -EIO;
1669         }
1670
1671         rte_intr_callback_register(intr_handle,
1672                                    ixgbevf_dev_interrupt_handler, eth_dev);
1673         rte_intr_enable(intr_handle);
1674         ixgbevf_intr_enable(hw);
1675
1676         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1677                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1678                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1679
1680         return 0;
1681 }
1682
1683 /* Virtual Function device uninit */
1684
1685 static int
1686 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1687 {
1688         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1689         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690         struct ixgbe_hw *hw;
1691
1692         PMD_INIT_FUNC_TRACE();
1693
1694         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1695                 return -EPERM;
1696
1697         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1698
1699         if (hw->adapter_stopped == 0)
1700                 ixgbevf_dev_close(eth_dev);
1701
1702         eth_dev->dev_ops = NULL;
1703         eth_dev->rx_pkt_burst = NULL;
1704         eth_dev->tx_pkt_burst = NULL;
1705
1706         /* Disable the interrupts for VF */
1707         ixgbevf_intr_disable(hw);
1708
1709         rte_free(eth_dev->data->mac_addrs);
1710         eth_dev->data->mac_addrs = NULL;
1711
1712         rte_intr_disable(intr_handle);
1713         rte_intr_callback_unregister(intr_handle,
1714                                      ixgbevf_dev_interrupt_handler, eth_dev);
1715
1716         return 0;
1717 }
1718
1719 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1720         struct rte_pci_device *pci_dev)
1721 {
1722         return rte_eth_dev_pci_generic_probe(pci_dev,
1723                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1724 }
1725
1726 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1727 {
1728         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1729 }
1730
1731 static struct rte_pci_driver rte_ixgbe_pmd = {
1732         .id_table = pci_id_ixgbe_map,
1733         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1734                      RTE_PCI_DRV_IOVA_AS_VA,
1735         .probe = eth_ixgbe_pci_probe,
1736         .remove = eth_ixgbe_pci_remove,
1737 };
1738
1739 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1740         struct rte_pci_device *pci_dev)
1741 {
1742         return rte_eth_dev_pci_generic_probe(pci_dev,
1743                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1744 }
1745
1746 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1747 {
1748         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1749 }
1750
1751 /*
1752  * virtual function driver struct
1753  */
1754 static struct rte_pci_driver rte_ixgbevf_pmd = {
1755         .id_table = pci_id_ixgbevf_map,
1756         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1757         .probe = eth_ixgbevf_pci_probe,
1758         .remove = eth_ixgbevf_pci_remove,
1759 };
1760
1761 static int
1762 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1763 {
1764         struct ixgbe_hw *hw =
1765                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1766         struct ixgbe_vfta *shadow_vfta =
1767                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1768         uint32_t vfta;
1769         uint32_t vid_idx;
1770         uint32_t vid_bit;
1771
1772         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1773         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1774         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1775         if (on)
1776                 vfta |= vid_bit;
1777         else
1778                 vfta &= ~vid_bit;
1779         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1780
1781         /* update local VFTA copy */
1782         shadow_vfta->vfta[vid_idx] = vfta;
1783
1784         return 0;
1785 }
1786
1787 static void
1788 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1789 {
1790         if (on)
1791                 ixgbe_vlan_hw_strip_enable(dev, queue);
1792         else
1793                 ixgbe_vlan_hw_strip_disable(dev, queue);
1794 }
1795
1796 static int
1797 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1798                     enum rte_vlan_type vlan_type,
1799                     uint16_t tpid)
1800 {
1801         struct ixgbe_hw *hw =
1802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803         int ret = 0;
1804         uint32_t reg;
1805         uint32_t qinq;
1806
1807         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1808         qinq &= IXGBE_DMATXCTL_GDV;
1809
1810         switch (vlan_type) {
1811         case ETH_VLAN_TYPE_INNER:
1812                 if (qinq) {
1813                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1814                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1815                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1816                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1817                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1818                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1819                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1820                 } else {
1821                         ret = -ENOTSUP;
1822                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1823                                     " by single VLAN");
1824                 }
1825                 break;
1826         case ETH_VLAN_TYPE_OUTER:
1827                 if (qinq) {
1828                         /* Only the high 16-bits is valid */
1829                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1830                                         IXGBE_EXVET_VET_EXT_SHIFT);
1831                 } else {
1832                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1833                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1834                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1835                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1836                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1837                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1838                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1839                 }
1840
1841                 break;
1842         default:
1843                 ret = -EINVAL;
1844                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1845                 break;
1846         }
1847
1848         return ret;
1849 }
1850
1851 void
1852 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1853 {
1854         struct ixgbe_hw *hw =
1855                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856         uint32_t vlnctrl;
1857
1858         PMD_INIT_FUNC_TRACE();
1859
1860         /* Filter Table Disable */
1861         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1862         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1863
1864         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1865 }
1866
1867 void
1868 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         struct ixgbe_vfta *shadow_vfta =
1873                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1874         uint32_t vlnctrl;
1875         uint16_t i;
1876
1877         PMD_INIT_FUNC_TRACE();
1878
1879         /* Filter Table Enable */
1880         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1881         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1882         vlnctrl |= IXGBE_VLNCTRL_VFE;
1883
1884         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1885
1886         /* write whatever is in local vfta copy */
1887         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1888                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1889 }
1890
1891 static void
1892 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1893 {
1894         struct ixgbe_hwstrip *hwstrip =
1895                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1896         struct ixgbe_rx_queue *rxq;
1897
1898         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1899                 return;
1900
1901         if (on)
1902                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1903         else
1904                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1905
1906         if (queue >= dev->data->nb_rx_queues)
1907                 return;
1908
1909         rxq = dev->data->rx_queues[queue];
1910
1911         if (on)
1912                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1913         else
1914                 rxq->vlan_flags = PKT_RX_VLAN;
1915 }
1916
1917 static void
1918 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint32_t ctrl;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         if (hw->mac.type == ixgbe_mac_82598EB) {
1927                 /* No queue level support */
1928                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1929                 return;
1930         }
1931
1932         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1933         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1934         ctrl &= ~IXGBE_RXDCTL_VME;
1935         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1936
1937         /* record those setting for HW strip per queue */
1938         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1939 }
1940
1941 static void
1942 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1943 {
1944         struct ixgbe_hw *hw =
1945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946         uint32_t ctrl;
1947
1948         PMD_INIT_FUNC_TRACE();
1949
1950         if (hw->mac.type == ixgbe_mac_82598EB) {
1951                 /* No queue level supported */
1952                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1953                 return;
1954         }
1955
1956         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1957         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1958         ctrl |= IXGBE_RXDCTL_VME;
1959         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1960
1961         /* record those setting for HW strip per queue */
1962         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1963 }
1964
1965 static void
1966 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1967 {
1968         struct ixgbe_hw *hw =
1969                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970         uint32_t ctrl;
1971
1972         PMD_INIT_FUNC_TRACE();
1973
1974         /* DMATXCTRL: Geric Double VLAN Disable */
1975         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1976         ctrl &= ~IXGBE_DMATXCTL_GDV;
1977         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1978
1979         /* CTRL_EXT: Global Double VLAN Disable */
1980         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1981         ctrl &= ~IXGBE_EXTENDED_VLAN;
1982         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1983
1984 }
1985
1986 static void
1987 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1988 {
1989         struct ixgbe_hw *hw =
1990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         uint32_t ctrl;
1992
1993         PMD_INIT_FUNC_TRACE();
1994
1995         /* DMATXCTRL: Geric Double VLAN Enable */
1996         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1997         ctrl |= IXGBE_DMATXCTL_GDV;
1998         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1999
2000         /* CTRL_EXT: Global Double VLAN Enable */
2001         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2002         ctrl |= IXGBE_EXTENDED_VLAN;
2003         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2004
2005         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2006         if (hw->mac.type == ixgbe_mac_X550 ||
2007             hw->mac.type == ixgbe_mac_X550EM_x ||
2008             hw->mac.type == ixgbe_mac_X550EM_a) {
2009                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2010                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2011                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2012         }
2013
2014         /*
2015          * VET EXT field in the EXVET register = 0x8100 by default
2016          * So no need to change. Same to VT field of DMATXCTL register
2017          */
2018 }
2019
2020 void
2021 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2022 {
2023         struct ixgbe_hw *hw =
2024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2026         uint32_t ctrl;
2027         uint16_t i;
2028         struct ixgbe_rx_queue *rxq;
2029         bool on;
2030
2031         PMD_INIT_FUNC_TRACE();
2032
2033         if (hw->mac.type == ixgbe_mac_82598EB) {
2034                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2035                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2036                         ctrl |= IXGBE_VLNCTRL_VME;
2037                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2038                 } else {
2039                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2040                         ctrl &= ~IXGBE_VLNCTRL_VME;
2041                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2042                 }
2043         } else {
2044                 /*
2045                  * Other 10G NIC, the VLAN strip can be setup
2046                  * per queue in RXDCTL
2047                  */
2048                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2049                         rxq = dev->data->rx_queues[i];
2050                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2051                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2052                                 ctrl |= IXGBE_RXDCTL_VME;
2053                                 on = TRUE;
2054                         } else {
2055                                 ctrl &= ~IXGBE_RXDCTL_VME;
2056                                 on = FALSE;
2057                         }
2058                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2059
2060                         /* record those setting for HW strip per queue */
2061                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2062                 }
2063         }
2064 }
2065
2066 static int
2067 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2068 {
2069         struct rte_eth_rxmode *rxmode;
2070         rxmode = &dev->data->dev_conf.rxmode;
2071
2072         if (mask & ETH_VLAN_STRIP_MASK) {
2073                 ixgbe_vlan_hw_strip_config(dev);
2074         }
2075
2076         if (mask & ETH_VLAN_FILTER_MASK) {
2077                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2078                         ixgbe_vlan_hw_filter_enable(dev);
2079                 else
2080                         ixgbe_vlan_hw_filter_disable(dev);
2081         }
2082
2083         if (mask & ETH_VLAN_EXTEND_MASK) {
2084                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2085                         ixgbe_vlan_hw_extend_enable(dev);
2086                 else
2087                         ixgbe_vlan_hw_extend_disable(dev);
2088         }
2089
2090         return 0;
2091 }
2092
2093 static void
2094 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2095 {
2096         struct ixgbe_hw *hw =
2097                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2099         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2100
2101         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2102         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2103 }
2104
2105 static int
2106 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2107 {
2108         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2109
2110         switch (nb_rx_q) {
2111         case 1:
2112         case 2:
2113                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2114                 break;
2115         case 4:
2116                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2117                 break;
2118         default:
2119                 return -EINVAL;
2120         }
2121
2122         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2123                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2124         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2125                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2126         return 0;
2127 }
2128
2129 static int
2130 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2131 {
2132         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2135         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2136
2137         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2138                 /* check multi-queue mode */
2139                 switch (dev_conf->rxmode.mq_mode) {
2140                 case ETH_MQ_RX_VMDQ_DCB:
2141                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2142                         break;
2143                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2144                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2145                         PMD_INIT_LOG(ERR, "SRIOV active,"
2146                                         " unsupported mq_mode rx %d.",
2147                                         dev_conf->rxmode.mq_mode);
2148                         return -EINVAL;
2149                 case ETH_MQ_RX_RSS:
2150                 case ETH_MQ_RX_VMDQ_RSS:
2151                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2152                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2153                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2154                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2155                                                 " invalid queue number"
2156                                                 " for VMDQ RSS, allowed"
2157                                                 " value are 1, 2 or 4.");
2158                                         return -EINVAL;
2159                                 }
2160                         break;
2161                 case ETH_MQ_RX_VMDQ_ONLY:
2162                 case ETH_MQ_RX_NONE:
2163                         /* if nothing mq mode configure, use default scheme */
2164                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2165                         break;
2166                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2167                         /* SRIOV only works in VMDq enable mode */
2168                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2169                                         " wrong mq_mode rx %d.",
2170                                         dev_conf->rxmode.mq_mode);
2171                         return -EINVAL;
2172                 }
2173
2174                 switch (dev_conf->txmode.mq_mode) {
2175                 case ETH_MQ_TX_VMDQ_DCB:
2176                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2177                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2178                         break;
2179                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2180                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2181                         break;
2182                 }
2183
2184                 /* check valid queue number */
2185                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2186                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2187                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2188                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2189                                         " must be less than or equal to %d.",
2190                                         nb_rx_q, nb_tx_q,
2191                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2192                         return -EINVAL;
2193                 }
2194         } else {
2195                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2196                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2197                                           " not supported.");
2198                         return -EINVAL;
2199                 }
2200                 /* check configuration for vmdb+dcb mode */
2201                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2202                         const struct rte_eth_vmdq_dcb_conf *conf;
2203
2204                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2205                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2206                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2207                                 return -EINVAL;
2208                         }
2209                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2210                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2211                                conf->nb_queue_pools == ETH_32_POOLS)) {
2212                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2213                                                 " nb_queue_pools must be %d or %d.",
2214                                                 ETH_16_POOLS, ETH_32_POOLS);
2215                                 return -EINVAL;
2216                         }
2217                 }
2218                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2219                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2220
2221                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2222                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2223                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2224                                 return -EINVAL;
2225                         }
2226                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2227                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2228                                conf->nb_queue_pools == ETH_32_POOLS)) {
2229                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2230                                                 " nb_queue_pools != %d and"
2231                                                 " nb_queue_pools != %d.",
2232                                                 ETH_16_POOLS, ETH_32_POOLS);
2233                                 return -EINVAL;
2234                         }
2235                 }
2236
2237                 /* For DCB mode check our configuration before we go further */
2238                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2239                         const struct rte_eth_dcb_rx_conf *conf;
2240
2241                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2242                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2243                                                  IXGBE_DCB_NB_QUEUES);
2244                                 return -EINVAL;
2245                         }
2246                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2247                         if (!(conf->nb_tcs == ETH_4_TCS ||
2248                                conf->nb_tcs == ETH_8_TCS)) {
2249                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2250                                                 " and nb_tcs != %d.",
2251                                                 ETH_4_TCS, ETH_8_TCS);
2252                                 return -EINVAL;
2253                         }
2254                 }
2255
2256                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2257                         const struct rte_eth_dcb_tx_conf *conf;
2258
2259                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2260                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2261                                                  IXGBE_DCB_NB_QUEUES);
2262                                 return -EINVAL;
2263                         }
2264                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2265                         if (!(conf->nb_tcs == ETH_4_TCS ||
2266                                conf->nb_tcs == ETH_8_TCS)) {
2267                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2268                                                 " and nb_tcs != %d.",
2269                                                 ETH_4_TCS, ETH_8_TCS);
2270                                 return -EINVAL;
2271                         }
2272                 }
2273
2274                 /*
2275                  * When DCB/VT is off, maximum number of queues changes,
2276                  * except for 82598EB, which remains constant.
2277                  */
2278                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2279                                 hw->mac.type != ixgbe_mac_82598EB) {
2280                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2281                                 PMD_INIT_LOG(ERR,
2282                                              "Neither VT nor DCB are enabled, "
2283                                              "nb_tx_q > %d.",
2284                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2285                                 return -EINVAL;
2286                         }
2287                 }
2288         }
2289         return 0;
2290 }
2291
2292 static int
2293 ixgbe_dev_configure(struct rte_eth_dev *dev)
2294 {
2295         struct ixgbe_interrupt *intr =
2296                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2297         struct ixgbe_adapter *adapter =
2298                 (struct ixgbe_adapter *)dev->data->dev_private;
2299         struct rte_eth_dev_info dev_info;
2300         uint64_t rx_offloads;
2301         uint64_t tx_offloads;
2302         int ret;
2303
2304         PMD_INIT_FUNC_TRACE();
2305         /* multipe queue mode checking */
2306         ret  = ixgbe_check_mq_mode(dev);
2307         if (ret != 0) {
2308                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2309                             ret);
2310                 return ret;
2311         }
2312
2313         ixgbe_dev_info_get(dev, &dev_info);
2314         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2315         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2316                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2317                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2318                             rx_offloads, dev_info.rx_offload_capa);
2319                 return -ENOTSUP;
2320         }
2321         tx_offloads = dev->data->dev_conf.txmode.offloads;
2322         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2323                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2324                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2325                             tx_offloads, dev_info.tx_offload_capa);
2326                 return -ENOTSUP;
2327         }
2328
2329         /* set flag to update link status after init */
2330         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2331
2332         /*
2333          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2334          * allocation or vector Rx preconditions we will reset it.
2335          */
2336         adapter->rx_bulk_alloc_allowed = true;
2337         adapter->rx_vec_allowed = true;
2338
2339         return 0;
2340 }
2341
2342 static void
2343 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2344 {
2345         struct ixgbe_hw *hw =
2346                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         struct ixgbe_interrupt *intr =
2348                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2349         uint32_t gpie;
2350
2351         /* only set up it on X550EM_X */
2352         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2353                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2354                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2355                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2356                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2357                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2358         }
2359 }
2360
2361 int
2362 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2363                         uint16_t tx_rate, uint64_t q_msk)
2364 {
2365         struct ixgbe_hw *hw;
2366         struct ixgbe_vf_info *vfinfo;
2367         struct rte_eth_link link;
2368         uint8_t  nb_q_per_pool;
2369         uint32_t queue_stride;
2370         uint32_t queue_idx, idx = 0, vf_idx;
2371         uint32_t queue_end;
2372         uint16_t total_rate = 0;
2373         struct rte_pci_device *pci_dev;
2374
2375         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2376         rte_eth_link_get_nowait(dev->data->port_id, &link);
2377
2378         if (vf >= pci_dev->max_vfs)
2379                 return -EINVAL;
2380
2381         if (tx_rate > link.link_speed)
2382                 return -EINVAL;
2383
2384         if (q_msk == 0)
2385                 return 0;
2386
2387         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2389         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2390         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2391         queue_idx = vf * queue_stride;
2392         queue_end = queue_idx + nb_q_per_pool - 1;
2393         if (queue_end >= hw->mac.max_tx_queues)
2394                 return -EINVAL;
2395
2396         if (vfinfo) {
2397                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2398                         if (vf_idx == vf)
2399                                 continue;
2400                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2401                                 idx++)
2402                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2403                 }
2404         } else {
2405                 return -EINVAL;
2406         }
2407
2408         /* Store tx_rate for this vf. */
2409         for (idx = 0; idx < nb_q_per_pool; idx++) {
2410                 if (((uint64_t)0x1 << idx) & q_msk) {
2411                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2412                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2413                         total_rate += tx_rate;
2414                 }
2415         }
2416
2417         if (total_rate > dev->data->dev_link.link_speed) {
2418                 /* Reset stored TX rate of the VF if it causes exceed
2419                  * link speed.
2420                  */
2421                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2422                 return -EINVAL;
2423         }
2424
2425         /* Set RTTBCNRC of each queue/pool for vf X  */
2426         for (; queue_idx <= queue_end; queue_idx++) {
2427                 if (0x1 & q_msk)
2428                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2429                 q_msk = q_msk >> 1;
2430         }
2431
2432         return 0;
2433 }
2434
2435 /*
2436  * Configure device link speed and setup link.
2437  * It returns 0 on success.
2438  */
2439 static int
2440 ixgbe_dev_start(struct rte_eth_dev *dev)
2441 {
2442         struct ixgbe_hw *hw =
2443                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444         struct ixgbe_vf_info *vfinfo =
2445                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2446         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2447         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2448         uint32_t intr_vector = 0;
2449         int err, link_up = 0, negotiate = 0;
2450         uint32_t speed = 0;
2451         int mask = 0;
2452         int status;
2453         uint16_t vf, idx;
2454         uint32_t *link_speeds;
2455         struct ixgbe_tm_conf *tm_conf =
2456                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2457
2458         PMD_INIT_FUNC_TRACE();
2459
2460         /* IXGBE devices don't support:
2461         *    - half duplex (checked afterwards for valid speeds)
2462         *    - fixed speed: TODO implement
2463         */
2464         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2465                 PMD_INIT_LOG(ERR,
2466                 "Invalid link_speeds for port %u, fix speed not supported",
2467                                 dev->data->port_id);
2468                 return -EINVAL;
2469         }
2470
2471         /* disable uio/vfio intr/eventfd mapping */
2472         rte_intr_disable(intr_handle);
2473
2474         /* stop adapter */
2475         hw->adapter_stopped = 0;
2476         ixgbe_stop_adapter(hw);
2477
2478         /* reinitialize adapter
2479          * this calls reset and start
2480          */
2481         status = ixgbe_pf_reset_hw(hw);
2482         if (status != 0)
2483                 return -1;
2484         hw->mac.ops.start_hw(hw);
2485         hw->mac.get_link_status = true;
2486
2487         /* configure PF module if SRIOV enabled */
2488         ixgbe_pf_host_configure(dev);
2489
2490         ixgbe_dev_phy_intr_setup(dev);
2491
2492         /* check and configure queue intr-vector mapping */
2493         if ((rte_intr_cap_multiple(intr_handle) ||
2494              !RTE_ETH_DEV_SRIOV(dev).active) &&
2495             dev->data->dev_conf.intr_conf.rxq != 0) {
2496                 intr_vector = dev->data->nb_rx_queues;
2497                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2498                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2499                                         IXGBE_MAX_INTR_QUEUE_NUM);
2500                         return -ENOTSUP;
2501                 }
2502                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2503                         return -1;
2504         }
2505
2506         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2507                 intr_handle->intr_vec =
2508                         rte_zmalloc("intr_vec",
2509                                     dev->data->nb_rx_queues * sizeof(int), 0);
2510                 if (intr_handle->intr_vec == NULL) {
2511                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2512                                      " intr_vec", dev->data->nb_rx_queues);
2513                         return -ENOMEM;
2514                 }
2515         }
2516
2517         /* confiugre msix for sleep until rx interrupt */
2518         ixgbe_configure_msix(dev);
2519
2520         /* initialize transmission unit */
2521         ixgbe_dev_tx_init(dev);
2522
2523         /* This can fail when allocating mbufs for descriptor rings */
2524         err = ixgbe_dev_rx_init(dev);
2525         if (err) {
2526                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2527                 goto error;
2528         }
2529
2530         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2531                 ETH_VLAN_EXTEND_MASK;
2532         err = ixgbe_vlan_offload_set(dev, mask);
2533         if (err) {
2534                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2535                 goto error;
2536         }
2537
2538         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2539                 /* Enable vlan filtering for VMDq */
2540                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2541         }
2542
2543         /* Configure DCB hw */
2544         ixgbe_configure_dcb(dev);
2545
2546         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2547                 err = ixgbe_fdir_configure(dev);
2548                 if (err)
2549                         goto error;
2550         }
2551
2552         /* Restore vf rate limit */
2553         if (vfinfo != NULL) {
2554                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2555                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2556                                 if (vfinfo[vf].tx_rate[idx] != 0)
2557                                         ixgbe_set_vf_rate_limit(
2558                                                 dev, vf,
2559                                                 vfinfo[vf].tx_rate[idx],
2560                                                 1 << idx);
2561         }
2562
2563         ixgbe_restore_statistics_mapping(dev);
2564
2565         err = ixgbe_dev_rxtx_start(dev);
2566         if (err < 0) {
2567                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2568                 goto error;
2569         }
2570
2571         /* Skip link setup if loopback mode is enabled for 82599. */
2572         if (hw->mac.type == ixgbe_mac_82599EB &&
2573                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2574                 goto skip_link_setup;
2575
2576         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2577                 err = hw->mac.ops.setup_sfp(hw);
2578                 if (err)
2579                         goto error;
2580         }
2581
2582         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2583                 /* Turn on the copper */
2584                 ixgbe_set_phy_power(hw, true);
2585         } else {
2586                 /* Turn on the laser */
2587                 ixgbe_enable_tx_laser(hw);
2588         }
2589
2590         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2591         if (err)
2592                 goto error;
2593         dev->data->dev_link.link_status = link_up;
2594
2595         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2596         if (err)
2597                 goto error;
2598
2599         link_speeds = &dev->data->dev_conf.link_speeds;
2600         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2601                         ETH_LINK_SPEED_10G)) {
2602                 PMD_INIT_LOG(ERR, "Invalid link setting");
2603                 goto error;
2604         }
2605
2606         speed = 0x0;
2607         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2608                 switch (hw->mac.type) {
2609                 case ixgbe_mac_82598EB:
2610                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2611                         break;
2612                 case ixgbe_mac_82599EB:
2613                 case ixgbe_mac_X540:
2614                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2615                         break;
2616                 case ixgbe_mac_X550:
2617                 case ixgbe_mac_X550EM_x:
2618                 case ixgbe_mac_X550EM_a:
2619                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2620                         break;
2621                 default:
2622                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2623                 }
2624         } else {
2625                 if (*link_speeds & ETH_LINK_SPEED_10G)
2626                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2627                 if (*link_speeds & ETH_LINK_SPEED_1G)
2628                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2629                 if (*link_speeds & ETH_LINK_SPEED_100M)
2630                         speed |= IXGBE_LINK_SPEED_100_FULL;
2631         }
2632
2633         err = ixgbe_setup_link(hw, speed, link_up);
2634         if (err)
2635                 goto error;
2636
2637         ixgbe_dev_link_update(dev, 0);
2638
2639 skip_link_setup:
2640
2641         if (rte_intr_allow_others(intr_handle)) {
2642                 /* check if lsc interrupt is enabled */
2643                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2644                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2645                 else
2646                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2647                 ixgbe_dev_macsec_interrupt_setup(dev);
2648         } else {
2649                 rte_intr_callback_unregister(intr_handle,
2650                                              ixgbe_dev_interrupt_handler, dev);
2651                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2652                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2653                                      " no intr multiplex");
2654         }
2655
2656         /* check if rxq interrupt is enabled */
2657         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2658             rte_intr_dp_is_en(intr_handle))
2659                 ixgbe_dev_rxq_interrupt_setup(dev);
2660
2661         /* enable uio/vfio intr/eventfd mapping */
2662         rte_intr_enable(intr_handle);
2663
2664         /* resume enabled intr since hw reset */
2665         ixgbe_enable_intr(dev);
2666         ixgbe_l2_tunnel_conf(dev);
2667         ixgbe_filter_restore(dev);
2668
2669         if (tm_conf->root && !tm_conf->committed)
2670                 PMD_DRV_LOG(WARNING,
2671                             "please call hierarchy_commit() "
2672                             "before starting the port");
2673
2674         return 0;
2675
2676 error:
2677         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2678         ixgbe_dev_clear_queues(dev);
2679         return -EIO;
2680 }
2681
2682 /*
2683  * Stop device: disable rx and tx functions to allow for reconfiguring.
2684  */
2685 static void
2686 ixgbe_dev_stop(struct rte_eth_dev *dev)
2687 {
2688         struct rte_eth_link link;
2689         struct ixgbe_hw *hw =
2690                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2691         struct ixgbe_vf_info *vfinfo =
2692                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2693         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2694         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2695         int vf;
2696         struct ixgbe_tm_conf *tm_conf =
2697                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2698
2699         PMD_INIT_FUNC_TRACE();
2700
2701         /* disable interrupts */
2702         ixgbe_disable_intr(hw);
2703
2704         /* reset the NIC */
2705         ixgbe_pf_reset_hw(hw);
2706         hw->adapter_stopped = 0;
2707
2708         /* stop adapter */
2709         ixgbe_stop_adapter(hw);
2710
2711         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2712                 vfinfo[vf].clear_to_send = false;
2713
2714         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2715                 /* Turn off the copper */
2716                 ixgbe_set_phy_power(hw, false);
2717         } else {
2718                 /* Turn off the laser */
2719                 ixgbe_disable_tx_laser(hw);
2720         }
2721
2722         ixgbe_dev_clear_queues(dev);
2723
2724         /* Clear stored conf */
2725         dev->data->scattered_rx = 0;
2726         dev->data->lro = 0;
2727
2728         /* Clear recorded link status */
2729         memset(&link, 0, sizeof(link));
2730         rte_eth_linkstatus_set(dev, &link);
2731
2732         if (!rte_intr_allow_others(intr_handle))
2733                 /* resume to the default handler */
2734                 rte_intr_callback_register(intr_handle,
2735                                            ixgbe_dev_interrupt_handler,
2736                                            (void *)dev);
2737
2738         /* Clean datapath event and queue/vec mapping */
2739         rte_intr_efd_disable(intr_handle);
2740         if (intr_handle->intr_vec != NULL) {
2741                 rte_free(intr_handle->intr_vec);
2742                 intr_handle->intr_vec = NULL;
2743         }
2744
2745         /* reset hierarchy commit */
2746         tm_conf->committed = false;
2747 }
2748
2749 /*
2750  * Set device link up: enable tx.
2751  */
2752 static int
2753 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2754 {
2755         struct ixgbe_hw *hw =
2756                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757         if (hw->mac.type == ixgbe_mac_82599EB) {
2758 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2759                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2760                         /* Not suported in bypass mode */
2761                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2762                                      "by device id 0x%x", hw->device_id);
2763                         return -ENOTSUP;
2764                 }
2765 #endif
2766         }
2767
2768         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2769                 /* Turn on the copper */
2770                 ixgbe_set_phy_power(hw, true);
2771         } else {
2772                 /* Turn on the laser */
2773                 ixgbe_enable_tx_laser(hw);
2774         }
2775
2776         return 0;
2777 }
2778
2779 /*
2780  * Set device link down: disable tx.
2781  */
2782 static int
2783 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2784 {
2785         struct ixgbe_hw *hw =
2786                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2787         if (hw->mac.type == ixgbe_mac_82599EB) {
2788 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2789                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2790                         /* Not suported in bypass mode */
2791                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2792                                      "by device id 0x%x", hw->device_id);
2793                         return -ENOTSUP;
2794                 }
2795 #endif
2796         }
2797
2798         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2799                 /* Turn off the copper */
2800                 ixgbe_set_phy_power(hw, false);
2801         } else {
2802                 /* Turn off the laser */
2803                 ixgbe_disable_tx_laser(hw);
2804         }
2805
2806         return 0;
2807 }
2808
2809 /*
2810  * Reset and stop device.
2811  */
2812 static void
2813 ixgbe_dev_close(struct rte_eth_dev *dev)
2814 {
2815         struct ixgbe_hw *hw =
2816                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817
2818         PMD_INIT_FUNC_TRACE();
2819
2820         ixgbe_pf_reset_hw(hw);
2821
2822         ixgbe_dev_stop(dev);
2823         hw->adapter_stopped = 1;
2824
2825         ixgbe_dev_free_queues(dev);
2826
2827         ixgbe_disable_pcie_master(hw);
2828
2829         /* reprogram the RAR[0] in case user changed it. */
2830         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2831 }
2832
2833 /*
2834  * Reset PF device.
2835  */
2836 static int
2837 ixgbe_dev_reset(struct rte_eth_dev *dev)
2838 {
2839         int ret;
2840
2841         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2842          * its VF to make them align with it. The detailed notification
2843          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2844          * To avoid unexpected behavior in VF, currently reset of PF with
2845          * SR-IOV activation is not supported. It might be supported later.
2846          */
2847         if (dev->data->sriov.active)
2848                 return -ENOTSUP;
2849
2850         ret = eth_ixgbe_dev_uninit(dev);
2851         if (ret)
2852                 return ret;
2853
2854         ret = eth_ixgbe_dev_init(dev);
2855
2856         return ret;
2857 }
2858
2859 static void
2860 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2861                            struct ixgbe_hw_stats *hw_stats,
2862                            struct ixgbe_macsec_stats *macsec_stats,
2863                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2864                            uint64_t *total_qprc, uint64_t *total_qprdc)
2865 {
2866         uint32_t bprc, lxon, lxoff, total;
2867         uint32_t delta_gprc = 0;
2868         unsigned i;
2869         /* Workaround for RX byte count not including CRC bytes when CRC
2870          * strip is enabled. CRC bytes are removed from counters when crc_strip
2871          * is disabled.
2872          */
2873         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2874                         IXGBE_HLREG0_RXCRCSTRP);
2875
2876         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2877         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2878         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2879         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2880
2881         for (i = 0; i < 8; i++) {
2882                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2883
2884                 /* global total per queue */
2885                 hw_stats->mpc[i] += mp;
2886                 /* Running comprehensive total for stats display */
2887                 *total_missed_rx += hw_stats->mpc[i];
2888                 if (hw->mac.type == ixgbe_mac_82598EB) {
2889                         hw_stats->rnbc[i] +=
2890                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2891                         hw_stats->pxonrxc[i] +=
2892                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2893                         hw_stats->pxoffrxc[i] +=
2894                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2895                 } else {
2896                         hw_stats->pxonrxc[i] +=
2897                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2898                         hw_stats->pxoffrxc[i] +=
2899                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2900                         hw_stats->pxon2offc[i] +=
2901                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2902                 }
2903                 hw_stats->pxontxc[i] +=
2904                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2905                 hw_stats->pxofftxc[i] +=
2906                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2907         }
2908         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2909                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2910                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2911                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2912
2913                 delta_gprc += delta_qprc;
2914
2915                 hw_stats->qprc[i] += delta_qprc;
2916                 hw_stats->qptc[i] += delta_qptc;
2917
2918                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2919                 hw_stats->qbrc[i] +=
2920                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2921                 if (crc_strip == 0)
2922                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2923
2924                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2925                 hw_stats->qbtc[i] +=
2926                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2927
2928                 hw_stats->qprdc[i] += delta_qprdc;
2929                 *total_qprdc += hw_stats->qprdc[i];
2930
2931                 *total_qprc += hw_stats->qprc[i];
2932                 *total_qbrc += hw_stats->qbrc[i];
2933         }
2934         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2935         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2936         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2937
2938         /*
2939          * An errata states that gprc actually counts good + missed packets:
2940          * Workaround to set gprc to summated queue packet receives
2941          */
2942         hw_stats->gprc = *total_qprc;
2943
2944         if (hw->mac.type != ixgbe_mac_82598EB) {
2945                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2946                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2947                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2948                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2949                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2950                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2951                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2952                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2953         } else {
2954                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2955                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2956                 /* 82598 only has a counter in the high register */
2957                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2958                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2959                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2960         }
2961         uint64_t old_tpr = hw_stats->tpr;
2962
2963         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2964         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2965
2966         if (crc_strip == 0)
2967                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2968
2969         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2970         hw_stats->gptc += delta_gptc;
2971         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2972         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2973
2974         /*
2975          * Workaround: mprc hardware is incorrectly counting
2976          * broadcasts, so for now we subtract those.
2977          */
2978         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2979         hw_stats->bprc += bprc;
2980         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2981         if (hw->mac.type == ixgbe_mac_82598EB)
2982                 hw_stats->mprc -= bprc;
2983
2984         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2985         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2986         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2987         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2988         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2989         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2990
2991         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2992         hw_stats->lxontxc += lxon;
2993         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2994         hw_stats->lxofftxc += lxoff;
2995         total = lxon + lxoff;
2996
2997         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2998         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2999         hw_stats->gptc -= total;
3000         hw_stats->mptc -= total;
3001         hw_stats->ptc64 -= total;
3002         hw_stats->gotc -= total * ETHER_MIN_LEN;
3003
3004         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3005         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3006         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3007         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3008         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3009         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3010         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3011         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3012         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3013         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3014         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3015         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3016         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3017         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3018         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3019         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3020         /* Only read FCOE on 82599 */
3021         if (hw->mac.type != ixgbe_mac_82598EB) {
3022                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3023                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3024                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3025                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3026                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3027         }
3028
3029         /* Flow Director Stats registers */
3030         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3031         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3032
3033         /* MACsec Stats registers */
3034         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3035         macsec_stats->out_pkts_encrypted +=
3036                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3037         macsec_stats->out_pkts_protected +=
3038                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3039         macsec_stats->out_octets_encrypted +=
3040                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3041         macsec_stats->out_octets_protected +=
3042                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3043         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3044         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3045         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3046         macsec_stats->in_pkts_unknownsci +=
3047                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3048         macsec_stats->in_octets_decrypted +=
3049                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3050         macsec_stats->in_octets_validated +=
3051                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3052         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3053         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3054         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3055         for (i = 0; i < 2; i++) {
3056                 macsec_stats->in_pkts_ok +=
3057                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3058                 macsec_stats->in_pkts_invalid +=
3059                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3060                 macsec_stats->in_pkts_notvalid +=
3061                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3062         }
3063         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3064         macsec_stats->in_pkts_notusingsa +=
3065                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3066 }
3067
3068 /*
3069  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3070  */
3071 static int
3072 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3073 {
3074         struct ixgbe_hw *hw =
3075                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076         struct ixgbe_hw_stats *hw_stats =
3077                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3078         struct ixgbe_macsec_stats *macsec_stats =
3079                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3080                                 dev->data->dev_private);
3081         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3082         unsigned i;
3083
3084         total_missed_rx = 0;
3085         total_qbrc = 0;
3086         total_qprc = 0;
3087         total_qprdc = 0;
3088
3089         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3090                         &total_qbrc, &total_qprc, &total_qprdc);
3091
3092         if (stats == NULL)
3093                 return -EINVAL;
3094
3095         /* Fill out the rte_eth_stats statistics structure */
3096         stats->ipackets = total_qprc;
3097         stats->ibytes = total_qbrc;
3098         stats->opackets = hw_stats->gptc;
3099         stats->obytes = hw_stats->gotc;
3100
3101         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3102                 stats->q_ipackets[i] = hw_stats->qprc[i];
3103                 stats->q_opackets[i] = hw_stats->qptc[i];
3104                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3105                 stats->q_obytes[i] = hw_stats->qbtc[i];
3106                 stats->q_errors[i] = hw_stats->qprdc[i];
3107         }
3108
3109         /* Rx Errors */
3110         stats->imissed  = total_missed_rx;
3111         stats->ierrors  = hw_stats->crcerrs +
3112                           hw_stats->mspdc +
3113                           hw_stats->rlec +
3114                           hw_stats->ruc +
3115                           hw_stats->roc +
3116                           hw_stats->illerrc +
3117                           hw_stats->errbc +
3118                           hw_stats->rfc +
3119                           hw_stats->fccrc +
3120                           hw_stats->fclast;
3121
3122         /* Tx Errors */
3123         stats->oerrors  = 0;
3124         return 0;
3125 }
3126
3127 static void
3128 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3129 {
3130         struct ixgbe_hw_stats *stats =
3131                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3132
3133         /* HW registers are cleared on read */
3134         ixgbe_dev_stats_get(dev, NULL);
3135
3136         /* Reset software totals */
3137         memset(stats, 0, sizeof(*stats));
3138 }
3139
3140 /* This function calculates the number of xstats based on the current config */
3141 static unsigned
3142 ixgbe_xstats_calc_num(void) {
3143         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3144                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3145                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3146 }
3147
3148 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3149         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3150 {
3151         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3152         unsigned stat, i, count;
3153
3154         if (xstats_names != NULL) {
3155                 count = 0;
3156
3157                 /* Note: limit >= cnt_stats checked upstream
3158                  * in rte_eth_xstats_names()
3159                  */
3160
3161                 /* Extended stats from ixgbe_hw_stats */
3162                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3163                         snprintf(xstats_names[count].name,
3164                                 sizeof(xstats_names[count].name),
3165                                 "%s",
3166                                 rte_ixgbe_stats_strings[i].name);
3167                         count++;
3168                 }
3169
3170                 /* MACsec Stats */
3171                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3172                         snprintf(xstats_names[count].name,
3173                                 sizeof(xstats_names[count].name),
3174                                 "%s",
3175                                 rte_ixgbe_macsec_strings[i].name);
3176                         count++;
3177                 }
3178
3179                 /* RX Priority Stats */
3180                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3181                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3182                                 snprintf(xstats_names[count].name,
3183                                         sizeof(xstats_names[count].name),
3184                                         "rx_priority%u_%s", i,
3185                                         rte_ixgbe_rxq_strings[stat].name);
3186                                 count++;
3187                         }
3188                 }
3189
3190                 /* TX Priority Stats */
3191                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3192                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3193                                 snprintf(xstats_names[count].name,
3194                                         sizeof(xstats_names[count].name),
3195                                         "tx_priority%u_%s", i,
3196                                         rte_ixgbe_txq_strings[stat].name);
3197                                 count++;
3198                         }
3199                 }
3200         }
3201         return cnt_stats;
3202 }
3203
3204 static int ixgbe_dev_xstats_get_names_by_id(
3205         struct rte_eth_dev *dev,
3206         struct rte_eth_xstat_name *xstats_names,
3207         const uint64_t *ids,
3208         unsigned int limit)
3209 {
3210         if (!ids) {
3211                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3212                 unsigned int stat, i, count;
3213
3214                 if (xstats_names != NULL) {
3215                         count = 0;
3216
3217                         /* Note: limit >= cnt_stats checked upstream
3218                          * in rte_eth_xstats_names()
3219                          */
3220
3221                         /* Extended stats from ixgbe_hw_stats */
3222                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3223                                 snprintf(xstats_names[count].name,
3224                                         sizeof(xstats_names[count].name),
3225                                         "%s",
3226                                         rte_ixgbe_stats_strings[i].name);
3227                                 count++;
3228                         }
3229
3230                         /* MACsec Stats */
3231                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3232                                 snprintf(xstats_names[count].name,
3233                                         sizeof(xstats_names[count].name),
3234                                         "%s",
3235                                         rte_ixgbe_macsec_strings[i].name);
3236                                 count++;
3237                         }
3238
3239                         /* RX Priority Stats */
3240                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3241                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3242                                         snprintf(xstats_names[count].name,
3243                                             sizeof(xstats_names[count].name),
3244                                             "rx_priority%u_%s", i,
3245                                             rte_ixgbe_rxq_strings[stat].name);
3246                                         count++;
3247                                 }
3248                         }
3249
3250                         /* TX Priority Stats */
3251                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3252                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3253                                         snprintf(xstats_names[count].name,
3254                                             sizeof(xstats_names[count].name),
3255                                             "tx_priority%u_%s", i,
3256                                             rte_ixgbe_txq_strings[stat].name);
3257                                         count++;
3258                                 }
3259                         }
3260                 }
3261                 return cnt_stats;
3262         }
3263
3264         uint16_t i;
3265         uint16_t size = ixgbe_xstats_calc_num();
3266         struct rte_eth_xstat_name xstats_names_copy[size];
3267
3268         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3269                         size);
3270
3271         for (i = 0; i < limit; i++) {
3272                 if (ids[i] >= size) {
3273                         PMD_INIT_LOG(ERR, "id value isn't valid");
3274                         return -1;
3275                 }
3276                 strcpy(xstats_names[i].name,
3277                                 xstats_names_copy[ids[i]].name);
3278         }
3279         return limit;
3280 }
3281
3282 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3283         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3284 {
3285         unsigned i;
3286
3287         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3288                 return -ENOMEM;
3289
3290         if (xstats_names != NULL)
3291                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3292                         snprintf(xstats_names[i].name,
3293                                 sizeof(xstats_names[i].name),
3294                                 "%s", rte_ixgbevf_stats_strings[i].name);
3295         return IXGBEVF_NB_XSTATS;
3296 }
3297
3298 static int
3299 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3300                                          unsigned n)
3301 {
3302         struct ixgbe_hw *hw =
3303                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3304         struct ixgbe_hw_stats *hw_stats =
3305                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3306         struct ixgbe_macsec_stats *macsec_stats =
3307                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3308                                 dev->data->dev_private);
3309         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3310         unsigned i, stat, count = 0;
3311
3312         count = ixgbe_xstats_calc_num();
3313
3314         if (n < count)
3315                 return count;
3316
3317         total_missed_rx = 0;
3318         total_qbrc = 0;
3319         total_qprc = 0;
3320         total_qprdc = 0;
3321
3322         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3323                         &total_qbrc, &total_qprc, &total_qprdc);
3324
3325         /* If this is a reset xstats is NULL, and we have cleared the
3326          * registers by reading them.
3327          */
3328         if (!xstats)
3329                 return 0;
3330
3331         /* Extended stats from ixgbe_hw_stats */
3332         count = 0;
3333         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3334                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3335                                 rte_ixgbe_stats_strings[i].offset);
3336                 xstats[count].id = count;
3337                 count++;
3338         }
3339
3340         /* MACsec Stats */
3341         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3342                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3343                                 rte_ixgbe_macsec_strings[i].offset);
3344                 xstats[count].id = count;
3345                 count++;
3346         }
3347
3348         /* RX Priority Stats */
3349         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3350                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3351                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3352                                         rte_ixgbe_rxq_strings[stat].offset +
3353                                         (sizeof(uint64_t) * i));
3354                         xstats[count].id = count;
3355                         count++;
3356                 }
3357         }
3358
3359         /* TX Priority Stats */
3360         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3361                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3362                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3363                                         rte_ixgbe_txq_strings[stat].offset +
3364                                         (sizeof(uint64_t) * i));
3365                         xstats[count].id = count;
3366                         count++;
3367                 }
3368         }
3369         return count;
3370 }
3371
3372 static int
3373 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3374                 uint64_t *values, unsigned int n)
3375 {
3376         if (!ids) {
3377                 struct ixgbe_hw *hw =
3378                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3379                 struct ixgbe_hw_stats *hw_stats =
3380                                 IXGBE_DEV_PRIVATE_TO_STATS(
3381                                                 dev->data->dev_private);
3382                 struct ixgbe_macsec_stats *macsec_stats =
3383                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3384                                         dev->data->dev_private);
3385                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3386                 unsigned int i, stat, count = 0;
3387
3388                 count = ixgbe_xstats_calc_num();
3389
3390                 if (!ids && n < count)
3391                         return count;
3392
3393                 total_missed_rx = 0;
3394                 total_qbrc = 0;
3395                 total_qprc = 0;
3396                 total_qprdc = 0;
3397
3398                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3399                                 &total_missed_rx, &total_qbrc, &total_qprc,
3400                                 &total_qprdc);
3401
3402                 /* If this is a reset xstats is NULL, and we have cleared the
3403                  * registers by reading them.
3404                  */
3405                 if (!ids && !values)
3406                         return 0;
3407
3408                 /* Extended stats from ixgbe_hw_stats */
3409                 count = 0;
3410                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3411                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3412                                         rte_ixgbe_stats_strings[i].offset);
3413                         count++;
3414                 }
3415
3416                 /* MACsec Stats */
3417                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3418                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3419                                         rte_ixgbe_macsec_strings[i].offset);
3420                         count++;
3421                 }
3422
3423                 /* RX Priority Stats */
3424                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3425                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3426                                 values[count] =
3427                                         *(uint64_t *)(((char *)hw_stats) +
3428                                         rte_ixgbe_rxq_strings[stat].offset +
3429                                         (sizeof(uint64_t) * i));
3430                                 count++;
3431                         }
3432                 }
3433
3434                 /* TX Priority Stats */
3435                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3436                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3437                                 values[count] =
3438                                         *(uint64_t *)(((char *)hw_stats) +
3439                                         rte_ixgbe_txq_strings[stat].offset +
3440                                         (sizeof(uint64_t) * i));
3441                                 count++;
3442                         }
3443                 }
3444                 return count;
3445         }
3446
3447         uint16_t i;
3448         uint16_t size = ixgbe_xstats_calc_num();
3449         uint64_t values_copy[size];
3450
3451         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3452
3453         for (i = 0; i < n; i++) {
3454                 if (ids[i] >= size) {
3455                         PMD_INIT_LOG(ERR, "id value isn't valid");
3456                         return -1;
3457                 }
3458                 values[i] = values_copy[ids[i]];
3459         }
3460         return n;
3461 }
3462
3463 static void
3464 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3465 {
3466         struct ixgbe_hw_stats *stats =
3467                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3468         struct ixgbe_macsec_stats *macsec_stats =
3469                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3470                                 dev->data->dev_private);
3471
3472         unsigned count = ixgbe_xstats_calc_num();
3473
3474         /* HW registers are cleared on read */
3475         ixgbe_dev_xstats_get(dev, NULL, count);
3476
3477         /* Reset software totals */
3478         memset(stats, 0, sizeof(*stats));
3479         memset(macsec_stats, 0, sizeof(*macsec_stats));
3480 }
3481
3482 static void
3483 ixgbevf_update_stats(struct rte_eth_dev *dev)
3484 {
3485         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3487                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3488
3489         /* Good Rx packet, include VF loopback */
3490         UPDATE_VF_STAT(IXGBE_VFGPRC,
3491             hw_stats->last_vfgprc, hw_stats->vfgprc);
3492
3493         /* Good Rx octets, include VF loopback */
3494         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3495             hw_stats->last_vfgorc, hw_stats->vfgorc);
3496
3497         /* Good Tx packet, include VF loopback */
3498         UPDATE_VF_STAT(IXGBE_VFGPTC,
3499             hw_stats->last_vfgptc, hw_stats->vfgptc);
3500
3501         /* Good Tx octets, include VF loopback */
3502         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3503             hw_stats->last_vfgotc, hw_stats->vfgotc);
3504
3505         /* Rx Multicst Packet */
3506         UPDATE_VF_STAT(IXGBE_VFMPRC,
3507             hw_stats->last_vfmprc, hw_stats->vfmprc);
3508 }
3509
3510 static int
3511 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3512                        unsigned n)
3513 {
3514         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3515                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3516         unsigned i;
3517
3518         if (n < IXGBEVF_NB_XSTATS)
3519                 return IXGBEVF_NB_XSTATS;
3520
3521         ixgbevf_update_stats(dev);
3522
3523         if (!xstats)
3524                 return 0;
3525
3526         /* Extended stats */
3527         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3528                 xstats[i].id = i;
3529                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3530                         rte_ixgbevf_stats_strings[i].offset);
3531         }
3532
3533         return IXGBEVF_NB_XSTATS;
3534 }
3535
3536 static int
3537 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3538 {
3539         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3540                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3541
3542         ixgbevf_update_stats(dev);
3543
3544         if (stats == NULL)
3545                 return -EINVAL;
3546
3547         stats->ipackets = hw_stats->vfgprc;
3548         stats->ibytes = hw_stats->vfgorc;
3549         stats->opackets = hw_stats->vfgptc;
3550         stats->obytes = hw_stats->vfgotc;
3551         return 0;
3552 }
3553
3554 static void
3555 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3556 {
3557         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3558                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3559
3560         /* Sync HW register to the last stats */
3561         ixgbevf_dev_stats_get(dev, NULL);
3562
3563         /* reset HW current stats*/
3564         hw_stats->vfgprc = 0;
3565         hw_stats->vfgorc = 0;
3566         hw_stats->vfgptc = 0;
3567         hw_stats->vfgotc = 0;
3568 }
3569
3570 static int
3571 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3572 {
3573         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3574         u16 eeprom_verh, eeprom_verl;
3575         u32 etrack_id;
3576         int ret;
3577
3578         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3579         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3580
3581         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3582         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3583
3584         ret += 1; /* add the size of '\0' */
3585         if (fw_size < (u32)ret)
3586                 return ret;
3587         else
3588                 return 0;
3589 }
3590
3591 static void
3592 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3593 {
3594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3596         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3597
3598         dev_info->pci_dev = pci_dev;
3599         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3600         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3601         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3602                 /*
3603                  * When DCB/VT is off, maximum number of queues changes,
3604                  * except for 82598EB, which remains constant.
3605                  */
3606                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3607                                 hw->mac.type != ixgbe_mac_82598EB)
3608                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3609         }
3610         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3611         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3612         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3613         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3614         dev_info->max_vfs = pci_dev->max_vfs;
3615         if (hw->mac.type == ixgbe_mac_82598EB)
3616                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3617         else
3618                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3619         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3620         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3621         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3622                                      dev_info->rx_queue_offload_capa);
3623         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3624         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3625
3626         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3627                 .rx_thresh = {
3628                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3629                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3630                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3631                 },
3632                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3633                 .rx_drop_en = 0,
3634                 .offloads = 0,
3635         };
3636
3637         dev_info->default_txconf = (struct rte_eth_txconf) {
3638                 .tx_thresh = {
3639                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3640                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3641                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3642                 },
3643                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3644                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3645                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3646                              ETH_TXQ_FLAGS_NOOFFLOADS |
3647                              ETH_TXQ_FLAGS_IGNORE,
3648                 .offloads = 0,
3649         };
3650
3651         dev_info->rx_desc_lim = rx_desc_lim;
3652         dev_info->tx_desc_lim = tx_desc_lim;
3653
3654         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3655         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3656         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3657
3658         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3659         if (hw->mac.type == ixgbe_mac_X540 ||
3660             hw->mac.type == ixgbe_mac_X540_vf ||
3661             hw->mac.type == ixgbe_mac_X550 ||
3662             hw->mac.type == ixgbe_mac_X550_vf) {
3663                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3664         }
3665         if (hw->mac.type == ixgbe_mac_X550) {
3666                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3667                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3668         }
3669 }
3670
3671 static const uint32_t *
3672 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3673 {
3674         static const uint32_t ptypes[] = {
3675                 /* For non-vec functions,
3676                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3677                  * for vec functions,
3678                  * refers to _recv_raw_pkts_vec().
3679                  */
3680                 RTE_PTYPE_L2_ETHER,
3681                 RTE_PTYPE_L3_IPV4,
3682                 RTE_PTYPE_L3_IPV4_EXT,
3683                 RTE_PTYPE_L3_IPV6,
3684                 RTE_PTYPE_L3_IPV6_EXT,
3685                 RTE_PTYPE_L4_SCTP,
3686                 RTE_PTYPE_L4_TCP,
3687                 RTE_PTYPE_L4_UDP,
3688                 RTE_PTYPE_TUNNEL_IP,
3689                 RTE_PTYPE_INNER_L3_IPV6,
3690                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3691                 RTE_PTYPE_INNER_L4_TCP,
3692                 RTE_PTYPE_INNER_L4_UDP,
3693                 RTE_PTYPE_UNKNOWN
3694         };
3695
3696         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3697             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3698             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3699             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3700                 return ptypes;
3701
3702 #if defined(RTE_ARCH_X86)
3703         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3704             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3705                 return ptypes;
3706 #endif
3707         return NULL;
3708 }
3709
3710 static void
3711 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3712                      struct rte_eth_dev_info *dev_info)
3713 {
3714         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3715         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716
3717         dev_info->pci_dev = pci_dev;
3718         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3719         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3720         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3721         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3722         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3723         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3724         dev_info->max_vfs = pci_dev->max_vfs;
3725         if (hw->mac.type == ixgbe_mac_82598EB)
3726                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3727         else
3728                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3729         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3730         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3731                                      dev_info->rx_queue_offload_capa);
3732         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3733         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3734
3735         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3736                 .rx_thresh = {
3737                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3738                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3739                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3740                 },
3741                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3742                 .rx_drop_en = 0,
3743                 .offloads = 0,
3744         };
3745
3746         dev_info->default_txconf = (struct rte_eth_txconf) {
3747                 .tx_thresh = {
3748                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3749                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3750                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3751                 },
3752                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3753                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3754                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3755                              ETH_TXQ_FLAGS_NOOFFLOADS |
3756                              ETH_TXQ_FLAGS_IGNORE,
3757                 .offloads = 0,
3758         };
3759
3760         dev_info->rx_desc_lim = rx_desc_lim;
3761         dev_info->tx_desc_lim = tx_desc_lim;
3762 }
3763
3764 static int
3765 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3766                    int *link_up, int wait_to_complete)
3767 {
3768         /**
3769          * for a quick link status checking, wait_to_compelet == 0,
3770          * skip PF link status checking
3771          */
3772         bool no_pflink_check = wait_to_complete == 0;
3773         struct ixgbe_mbx_info *mbx = &hw->mbx;
3774         struct ixgbe_mac_info *mac = &hw->mac;
3775         uint32_t links_reg, in_msg;
3776         int ret_val = 0;
3777
3778         /* If we were hit with a reset drop the link */
3779         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3780                 mac->get_link_status = true;
3781
3782         if (!mac->get_link_status)
3783                 goto out;
3784
3785         /* if link status is down no point in checking to see if pf is up */
3786         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3787         if (!(links_reg & IXGBE_LINKS_UP))
3788                 goto out;
3789
3790         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3791          * before the link status is correct
3792          */
3793         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3794                 int i;
3795
3796                 for (i = 0; i < 5; i++) {
3797                         rte_delay_us(100);
3798                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3799
3800                         if (!(links_reg & IXGBE_LINKS_UP))
3801                                 goto out;
3802                 }
3803         }
3804
3805         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3806         case IXGBE_LINKS_SPEED_10G_82599:
3807                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3808                 if (hw->mac.type >= ixgbe_mac_X550) {
3809                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3810                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3811                 }
3812                 break;
3813         case IXGBE_LINKS_SPEED_1G_82599:
3814                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3815                 break;
3816         case IXGBE_LINKS_SPEED_100_82599:
3817                 *speed = IXGBE_LINK_SPEED_100_FULL;
3818                 if (hw->mac.type == ixgbe_mac_X550) {
3819                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3820                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3821                 }
3822                 break;
3823         case IXGBE_LINKS_SPEED_10_X550EM_A:
3824                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3825                 /* Since Reserved in older MAC's */
3826                 if (hw->mac.type >= ixgbe_mac_X550)
3827                         *speed = IXGBE_LINK_SPEED_10_FULL;
3828                 break;
3829         default:
3830                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3831         }
3832
3833         if (no_pflink_check) {
3834                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3835                         mac->get_link_status = true;
3836                 else
3837                         mac->get_link_status = false;
3838
3839                 goto out;
3840         }
3841         /* if the read failed it could just be a mailbox collision, best wait
3842          * until we are called again and don't report an error
3843          */
3844         if (mbx->ops.read(hw, &in_msg, 1, 0))
3845                 goto out;
3846
3847         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3848                 /* msg is not CTS and is NACK we must have lost CTS status */
3849                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3850                         ret_val = -1;
3851                 goto out;
3852         }
3853
3854         /* the pf is talking, if we timed out in the past we reinit */
3855         if (!mbx->timeout) {
3856                 ret_val = -1;
3857                 goto out;
3858         }
3859
3860         /* if we passed all the tests above then the link is up and we no
3861          * longer need to check for link
3862          */
3863         mac->get_link_status = false;
3864
3865 out:
3866         *link_up = !mac->get_link_status;
3867         return ret_val;
3868 }
3869
3870 /* return 0 means link status changed, -1 means not changed */
3871 static int
3872 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3873                             int wait_to_complete, int vf)
3874 {
3875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3876         struct rte_eth_link link;
3877         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3878         struct ixgbe_interrupt *intr =
3879                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3880         int link_up;
3881         int diag;
3882         u32 speed = 0;
3883         int wait = 1;
3884         bool autoneg = false;
3885
3886         memset(&link, 0, sizeof(link));
3887         link.link_status = ETH_LINK_DOWN;
3888         link.link_speed = 0;
3889         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3890         link.link_autoneg = ETH_LINK_AUTONEG;
3891
3892         hw->mac.get_link_status = true;
3893
3894         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3895                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3896                 speed = hw->phy.autoneg_advertised;
3897                 if (!speed)
3898                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3899                 ixgbe_setup_link(hw, speed, true);
3900         }
3901
3902         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3903         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3904                 wait = 0;
3905
3906         if (vf)
3907                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3908         else
3909                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3910
3911         if (diag != 0) {
3912                 link.link_speed = ETH_SPEED_NUM_100M;
3913                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3914                 return rte_eth_linkstatus_set(dev, &link);
3915         }
3916
3917         if (link_up == 0) {
3918                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3919                 return rte_eth_linkstatus_set(dev, &link);
3920         }
3921
3922         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3923         link.link_status = ETH_LINK_UP;
3924         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3925
3926         switch (link_speed) {
3927         default:
3928         case IXGBE_LINK_SPEED_UNKNOWN:
3929                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3930                 link.link_speed = ETH_SPEED_NUM_100M;
3931                 break;
3932
3933         case IXGBE_LINK_SPEED_100_FULL:
3934                 link.link_speed = ETH_SPEED_NUM_100M;
3935                 break;
3936
3937         case IXGBE_LINK_SPEED_1GB_FULL:
3938                 link.link_speed = ETH_SPEED_NUM_1G;
3939                 break;
3940
3941         case IXGBE_LINK_SPEED_2_5GB_FULL:
3942                 link.link_speed = ETH_SPEED_NUM_2_5G;
3943                 break;
3944
3945         case IXGBE_LINK_SPEED_5GB_FULL:
3946                 link.link_speed = ETH_SPEED_NUM_5G;
3947                 break;
3948
3949         case IXGBE_LINK_SPEED_10GB_FULL:
3950                 link.link_speed = ETH_SPEED_NUM_10G;
3951                 break;
3952         }
3953
3954         return rte_eth_linkstatus_set(dev, &link);
3955 }
3956
3957 static int
3958 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3959 {
3960         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3961 }
3962
3963 static int
3964 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3965 {
3966         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3967 }
3968
3969 static void
3970 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3971 {
3972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3973         uint32_t fctrl;
3974
3975         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3976         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3977         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3978 }
3979
3980 static void
3981 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3982 {
3983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3984         uint32_t fctrl;
3985
3986         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3987         fctrl &= (~IXGBE_FCTRL_UPE);
3988         if (dev->data->all_multicast == 1)
3989                 fctrl |= IXGBE_FCTRL_MPE;
3990         else
3991                 fctrl &= (~IXGBE_FCTRL_MPE);
3992         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3993 }
3994
3995 static void
3996 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3997 {
3998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3999         uint32_t fctrl;
4000
4001         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4002         fctrl |= IXGBE_FCTRL_MPE;
4003         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4004 }
4005
4006 static void
4007 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4008 {
4009         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4010         uint32_t fctrl;
4011
4012         if (dev->data->promiscuous == 1)
4013                 return; /* must remain in all_multicast mode */
4014
4015         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4016         fctrl &= (~IXGBE_FCTRL_MPE);
4017         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4018 }
4019
4020 /**
4021  * It clears the interrupt causes and enables the interrupt.
4022  * It will be called once only during nic initialized.
4023  *
4024  * @param dev
4025  *  Pointer to struct rte_eth_dev.
4026  * @param on
4027  *  Enable or Disable.
4028  *
4029  * @return
4030  *  - On success, zero.
4031  *  - On failure, a negative value.
4032  */
4033 static int
4034 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4035 {
4036         struct ixgbe_interrupt *intr =
4037                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4038
4039         ixgbe_dev_link_status_print(dev);
4040         if (on)
4041                 intr->mask |= IXGBE_EICR_LSC;
4042         else
4043                 intr->mask &= ~IXGBE_EICR_LSC;
4044
4045         return 0;
4046 }
4047
4048 /**
4049  * It clears the interrupt causes and enables the interrupt.
4050  * It will be called once only during nic initialized.
4051  *
4052  * @param dev
4053  *  Pointer to struct rte_eth_dev.
4054  *
4055  * @return
4056  *  - On success, zero.
4057  *  - On failure, a negative value.
4058  */
4059 static int
4060 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4061 {
4062         struct ixgbe_interrupt *intr =
4063                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4064
4065         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4066
4067         return 0;
4068 }
4069
4070 /**
4071  * It clears the interrupt causes and enables the interrupt.
4072  * It will be called once only during nic initialized.
4073  *
4074  * @param dev
4075  *  Pointer to struct rte_eth_dev.
4076  *
4077  * @return
4078  *  - On success, zero.
4079  *  - On failure, a negative value.
4080  */
4081 static int
4082 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4083 {
4084         struct ixgbe_interrupt *intr =
4085                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4086
4087         intr->mask |= IXGBE_EICR_LINKSEC;
4088
4089         return 0;
4090 }
4091
4092 /*
4093  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4094  *
4095  * @param dev
4096  *  Pointer to struct rte_eth_dev.
4097  *
4098  * @return
4099  *  - On success, zero.
4100  *  - On failure, a negative value.
4101  */
4102 static int
4103 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4104 {
4105         uint32_t eicr;
4106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4107         struct ixgbe_interrupt *intr =
4108                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4109
4110         /* clear all cause mask */
4111         ixgbe_disable_intr(hw);
4112
4113         /* read-on-clear nic registers here */
4114         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4115         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4116
4117         intr->flags = 0;
4118
4119         /* set flag for async link update */
4120         if (eicr & IXGBE_EICR_LSC)
4121                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4122
4123         if (eicr & IXGBE_EICR_MAILBOX)
4124                 intr->flags |= IXGBE_FLAG_MAILBOX;
4125
4126         if (eicr & IXGBE_EICR_LINKSEC)
4127                 intr->flags |= IXGBE_FLAG_MACSEC;
4128
4129         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4130             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4131             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4132                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4133
4134         return 0;
4135 }
4136
4137 /**
4138  * It gets and then prints the link status.
4139  *
4140  * @param dev
4141  *  Pointer to struct rte_eth_dev.
4142  *
4143  * @return
4144  *  - On success, zero.
4145  *  - On failure, a negative value.
4146  */
4147 static void
4148 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4149 {
4150         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4151         struct rte_eth_link link;
4152
4153         rte_eth_linkstatus_get(dev, &link);
4154
4155         if (link.link_status) {
4156                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4157                                         (int)(dev->data->port_id),
4158                                         (unsigned)link.link_speed,
4159                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4160                                         "full-duplex" : "half-duplex");
4161         } else {
4162                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4163                                 (int)(dev->data->port_id));
4164         }
4165         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4166                                 pci_dev->addr.domain,
4167                                 pci_dev->addr.bus,
4168                                 pci_dev->addr.devid,
4169                                 pci_dev->addr.function);
4170 }
4171
4172 /*
4173  * It executes link_update after knowing an interrupt occurred.
4174  *
4175  * @param dev
4176  *  Pointer to struct rte_eth_dev.
4177  *
4178  * @return
4179  *  - On success, zero.
4180  *  - On failure, a negative value.
4181  */
4182 static int
4183 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4184                            struct rte_intr_handle *intr_handle)
4185 {
4186         struct ixgbe_interrupt *intr =
4187                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4188         int64_t timeout;
4189         struct ixgbe_hw *hw =
4190                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4191
4192         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4193
4194         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4195                 ixgbe_pf_mbx_process(dev);
4196                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4197         }
4198
4199         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4200                 ixgbe_handle_lasi(hw);
4201                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4202         }
4203
4204         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4205                 struct rte_eth_link link;
4206
4207                 /* get the link status before link update, for predicting later */
4208                 rte_eth_linkstatus_get(dev, &link);
4209
4210                 ixgbe_dev_link_update(dev, 0);
4211
4212                 /* likely to up */
4213                 if (!link.link_status)
4214                         /* handle it 1 sec later, wait it being stable */
4215                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4216                 /* likely to down */
4217                 else
4218                         /* handle it 4 sec later, wait it being stable */
4219                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4220
4221                 ixgbe_dev_link_status_print(dev);
4222                 if (rte_eal_alarm_set(timeout * 1000,
4223                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4224                         PMD_DRV_LOG(ERR, "Error setting alarm");
4225                 else {
4226                         /* remember original mask */
4227                         intr->mask_original = intr->mask;
4228                         /* only disable lsc interrupt */
4229                         intr->mask &= ~IXGBE_EIMS_LSC;
4230                 }
4231         }
4232
4233         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4234         ixgbe_enable_intr(dev);
4235         rte_intr_enable(intr_handle);
4236
4237         return 0;
4238 }
4239
4240 /**
4241  * Interrupt handler which shall be registered for alarm callback for delayed
4242  * handling specific interrupt to wait for the stable nic state. As the
4243  * NIC interrupt state is not stable for ixgbe after link is just down,
4244  * it needs to wait 4 seconds to get the stable status.
4245  *
4246  * @param handle
4247  *  Pointer to interrupt handle.
4248  * @param param
4249  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4250  *
4251  * @return
4252  *  void
4253  */
4254 static void
4255 ixgbe_dev_interrupt_delayed_handler(void *param)
4256 {
4257         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4258         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4259         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4260         struct ixgbe_interrupt *intr =
4261                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4262         struct ixgbe_hw *hw =
4263                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4264         uint32_t eicr;
4265
4266         ixgbe_disable_intr(hw);
4267
4268         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4269         if (eicr & IXGBE_EICR_MAILBOX)
4270                 ixgbe_pf_mbx_process(dev);
4271
4272         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4273                 ixgbe_handle_lasi(hw);
4274                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4275         }
4276
4277         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4278                 ixgbe_dev_link_update(dev, 0);
4279                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4280                 ixgbe_dev_link_status_print(dev);
4281                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4282                                               NULL);
4283         }
4284
4285         if (intr->flags & IXGBE_FLAG_MACSEC) {
4286                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4287                                               NULL);
4288                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4289         }
4290
4291         /* restore original mask */
4292         intr->mask = intr->mask_original;
4293         intr->mask_original = 0;
4294
4295         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4296         ixgbe_enable_intr(dev);
4297         rte_intr_enable(intr_handle);
4298 }
4299
4300 /**
4301  * Interrupt handler triggered by NIC  for handling
4302  * specific interrupt.
4303  *
4304  * @param handle
4305  *  Pointer to interrupt handle.
4306  * @param param
4307  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4308  *
4309  * @return
4310  *  void
4311  */
4312 static void
4313 ixgbe_dev_interrupt_handler(void *param)
4314 {
4315         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4316
4317         ixgbe_dev_interrupt_get_status(dev);
4318         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4319 }
4320
4321 static int
4322 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4323 {
4324         struct ixgbe_hw *hw;
4325
4326         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4327         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4328 }
4329
4330 static int
4331 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4332 {
4333         struct ixgbe_hw *hw;
4334
4335         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4336         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4337 }
4338
4339 static int
4340 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4341 {
4342         struct ixgbe_hw *hw;
4343         uint32_t mflcn_reg;
4344         uint32_t fccfg_reg;
4345         int rx_pause;
4346         int tx_pause;
4347
4348         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4349
4350         fc_conf->pause_time = hw->fc.pause_time;
4351         fc_conf->high_water = hw->fc.high_water[0];
4352         fc_conf->low_water = hw->fc.low_water[0];
4353         fc_conf->send_xon = hw->fc.send_xon;
4354         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4355
4356         /*
4357          * Return rx_pause status according to actual setting of
4358          * MFLCN register.
4359          */
4360         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4361         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4362                 rx_pause = 1;
4363         else
4364                 rx_pause = 0;
4365
4366         /*
4367          * Return tx_pause status according to actual setting of
4368          * FCCFG register.
4369          */
4370         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4371         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4372                 tx_pause = 1;
4373         else
4374                 tx_pause = 0;
4375
4376         if (rx_pause && tx_pause)
4377                 fc_conf->mode = RTE_FC_FULL;
4378         else if (rx_pause)
4379                 fc_conf->mode = RTE_FC_RX_PAUSE;
4380         else if (tx_pause)
4381                 fc_conf->mode = RTE_FC_TX_PAUSE;
4382         else
4383                 fc_conf->mode = RTE_FC_NONE;
4384
4385         return 0;
4386 }
4387
4388 static int
4389 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4390 {
4391         struct ixgbe_hw *hw;
4392         int err;
4393         uint32_t rx_buf_size;
4394         uint32_t max_high_water;
4395         uint32_t mflcn;
4396         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4397                 ixgbe_fc_none,
4398                 ixgbe_fc_rx_pause,
4399                 ixgbe_fc_tx_pause,
4400                 ixgbe_fc_full
4401         };
4402
4403         PMD_INIT_FUNC_TRACE();
4404
4405         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4406         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4407         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4408
4409         /*
4410          * At least reserve one Ethernet frame for watermark
4411          * high_water/low_water in kilo bytes for ixgbe
4412          */
4413         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4414         if ((fc_conf->high_water > max_high_water) ||
4415                 (fc_conf->high_water < fc_conf->low_water)) {
4416                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4417                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4418                 return -EINVAL;
4419         }
4420
4421         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4422         hw->fc.pause_time     = fc_conf->pause_time;
4423         hw->fc.high_water[0]  = fc_conf->high_water;
4424         hw->fc.low_water[0]   = fc_conf->low_water;
4425         hw->fc.send_xon       = fc_conf->send_xon;
4426         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4427
4428         err = ixgbe_fc_enable(hw);
4429
4430         /* Not negotiated is not an error case */
4431         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4432
4433                 /* check if we want to forward MAC frames - driver doesn't have native
4434                  * capability to do that, so we'll write the registers ourselves */
4435
4436                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4437
4438                 /* set or clear MFLCN.PMCF bit depending on configuration */
4439                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4440                         mflcn |= IXGBE_MFLCN_PMCF;
4441                 else
4442                         mflcn &= ~IXGBE_MFLCN_PMCF;
4443
4444                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4445                 IXGBE_WRITE_FLUSH(hw);
4446
4447                 return 0;
4448         }
4449
4450         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4451         return -EIO;
4452 }
4453
4454 /**
4455  *  ixgbe_pfc_enable_generic - Enable flow control
4456  *  @hw: pointer to hardware structure
4457  *  @tc_num: traffic class number
4458  *  Enable flow control according to the current settings.
4459  */
4460 static int
4461 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4462 {
4463         int ret_val = 0;
4464         uint32_t mflcn_reg, fccfg_reg;
4465         uint32_t reg;
4466         uint32_t fcrtl, fcrth;
4467         uint8_t i;
4468         uint8_t nb_rx_en;
4469
4470         /* Validate the water mark configuration */
4471         if (!hw->fc.pause_time) {
4472                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4473                 goto out;
4474         }
4475
4476         /* Low water mark of zero causes XOFF floods */
4477         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4478                  /* High/Low water can not be 0 */
4479                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4480                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4481                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4482                         goto out;
4483                 }
4484
4485                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4486                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4487                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4488                         goto out;
4489                 }
4490         }
4491         /* Negotiate the fc mode to use */
4492         ixgbe_fc_autoneg(hw);
4493
4494         /* Disable any previous flow control settings */
4495         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4496         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4497
4498         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4499         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4500
4501         switch (hw->fc.current_mode) {
4502         case ixgbe_fc_none:
4503                 /*
4504                  * If the count of enabled RX Priority Flow control >1,
4505                  * and the TX pause can not be disabled
4506                  */
4507                 nb_rx_en = 0;
4508                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4509                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4510                         if (reg & IXGBE_FCRTH_FCEN)
4511                                 nb_rx_en++;
4512                 }
4513                 if (nb_rx_en > 1)
4514                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4515                 break;
4516         case ixgbe_fc_rx_pause:
4517                 /*
4518                  * Rx Flow control is enabled and Tx Flow control is
4519                  * disabled by software override. Since there really
4520                  * isn't a way to advertise that we are capable of RX
4521                  * Pause ONLY, we will advertise that we support both
4522                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4523                  * disable the adapter's ability to send PAUSE frames.
4524                  */
4525                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4526                 /*
4527                  * If the count of enabled RX Priority Flow control >1,
4528                  * and the TX pause can not be disabled
4529                  */
4530                 nb_rx_en = 0;
4531                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4532                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4533                         if (reg & IXGBE_FCRTH_FCEN)
4534                                 nb_rx_en++;
4535                 }
4536                 if (nb_rx_en > 1)
4537                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4538                 break;
4539         case ixgbe_fc_tx_pause:
4540                 /*
4541                  * Tx Flow control is enabled, and Rx Flow control is
4542                  * disabled by software override.
4543                  */
4544                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4545                 break;
4546         case ixgbe_fc_full:
4547                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4548                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4549                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4550                 break;
4551         default:
4552                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4553                 ret_val = IXGBE_ERR_CONFIG;
4554                 goto out;
4555         }
4556
4557         /* Set 802.3x based flow control settings. */
4558         mflcn_reg |= IXGBE_MFLCN_DPF;
4559         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4560         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4561
4562         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4563         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4564                 hw->fc.high_water[tc_num]) {
4565                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4566                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4567                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4568         } else {
4569                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4570                 /*
4571                  * In order to prevent Tx hangs when the internal Tx
4572                  * switch is enabled we must set the high water mark
4573                  * to the maximum FCRTH value.  This allows the Tx
4574                  * switch to function even under heavy Rx workloads.
4575                  */
4576                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4577         }
4578         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4579
4580         /* Configure pause time (2 TCs per register) */
4581         reg = hw->fc.pause_time * 0x00010001;
4582         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4583                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4584
4585         /* Configure flow control refresh threshold value */
4586         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4587
4588 out:
4589         return ret_val;
4590 }
4591
4592 static int
4593 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4594 {
4595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4596         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4597
4598         if (hw->mac.type != ixgbe_mac_82598EB) {
4599                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4600         }
4601         return ret_val;
4602 }
4603
4604 static int
4605 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4606 {
4607         int err;
4608         uint32_t rx_buf_size;
4609         uint32_t max_high_water;
4610         uint8_t tc_num;
4611         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4612         struct ixgbe_hw *hw =
4613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4614         struct ixgbe_dcb_config *dcb_config =
4615                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4616
4617         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4618                 ixgbe_fc_none,
4619                 ixgbe_fc_rx_pause,
4620                 ixgbe_fc_tx_pause,
4621                 ixgbe_fc_full
4622         };
4623
4624         PMD_INIT_FUNC_TRACE();
4625
4626         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4627         tc_num = map[pfc_conf->priority];
4628         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4629         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4630         /*
4631          * At least reserve one Ethernet frame for watermark
4632          * high_water/low_water in kilo bytes for ixgbe
4633          */
4634         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4635         if ((pfc_conf->fc.high_water > max_high_water) ||
4636             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4637                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4638                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4639                 return -EINVAL;
4640         }
4641
4642         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4643         hw->fc.pause_time = pfc_conf->fc.pause_time;
4644         hw->fc.send_xon = pfc_conf->fc.send_xon;
4645         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4646         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4647
4648         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4649
4650         /* Not negotiated is not an error case */
4651         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4652                 return 0;
4653
4654         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4655         return -EIO;
4656 }
4657
4658 static int
4659 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4660                           struct rte_eth_rss_reta_entry64 *reta_conf,
4661                           uint16_t reta_size)
4662 {
4663         uint16_t i, sp_reta_size;
4664         uint8_t j, mask;
4665         uint32_t reta, r;
4666         uint16_t idx, shift;
4667         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4668         uint32_t reta_reg;
4669
4670         PMD_INIT_FUNC_TRACE();
4671
4672         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4673                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4674                         "NIC.");
4675                 return -ENOTSUP;
4676         }
4677
4678         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4679         if (reta_size != sp_reta_size) {
4680                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4681                         "(%d) doesn't match the number hardware can supported "
4682                         "(%d)", reta_size, sp_reta_size);
4683                 return -EINVAL;
4684         }
4685
4686         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4687                 idx = i / RTE_RETA_GROUP_SIZE;
4688                 shift = i % RTE_RETA_GROUP_SIZE;
4689                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4690                                                 IXGBE_4_BIT_MASK);
4691                 if (!mask)
4692                         continue;
4693                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4694                 if (mask == IXGBE_4_BIT_MASK)
4695                         r = 0;
4696                 else
4697                         r = IXGBE_READ_REG(hw, reta_reg);
4698                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4699                         if (mask & (0x1 << j))
4700                                 reta |= reta_conf[idx].reta[shift + j] <<
4701                                                         (CHAR_BIT * j);
4702                         else
4703                                 reta |= r & (IXGBE_8_BIT_MASK <<
4704                                                 (CHAR_BIT * j));
4705                 }
4706                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4707         }
4708
4709         return 0;
4710 }
4711
4712 static int
4713 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4714                          struct rte_eth_rss_reta_entry64 *reta_conf,
4715                          uint16_t reta_size)
4716 {
4717         uint16_t i, sp_reta_size;
4718         uint8_t j, mask;
4719         uint32_t reta;
4720         uint16_t idx, shift;
4721         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4722         uint32_t reta_reg;
4723
4724         PMD_INIT_FUNC_TRACE();
4725         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4726         if (reta_size != sp_reta_size) {
4727                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4728                         "(%d) doesn't match the number hardware can supported "
4729                         "(%d)", reta_size, sp_reta_size);
4730                 return -EINVAL;
4731         }
4732
4733         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4734                 idx = i / RTE_RETA_GROUP_SIZE;
4735                 shift = i % RTE_RETA_GROUP_SIZE;
4736                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4737                                                 IXGBE_4_BIT_MASK);
4738                 if (!mask)
4739                         continue;
4740
4741                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4742                 reta = IXGBE_READ_REG(hw, reta_reg);
4743                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4744                         if (mask & (0x1 << j))
4745                                 reta_conf[idx].reta[shift + j] =
4746                                         ((reta >> (CHAR_BIT * j)) &
4747                                                 IXGBE_8_BIT_MASK);
4748                 }
4749         }
4750
4751         return 0;
4752 }
4753
4754 static int
4755 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4756                                 uint32_t index, uint32_t pool)
4757 {
4758         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4759         uint32_t enable_addr = 1;
4760
4761         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4762                              pool, enable_addr);
4763 }
4764
4765 static void
4766 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4767 {
4768         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4769
4770         ixgbe_clear_rar(hw, index);
4771 }
4772
4773 static void
4774 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4775 {
4776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4777
4778         ixgbe_remove_rar(dev, 0);
4779
4780         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4781 }
4782
4783 static bool
4784 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4785 {
4786         if (strcmp(dev->device->driver->name, drv->driver.name))
4787                 return false;
4788
4789         return true;
4790 }
4791
4792 bool
4793 is_ixgbe_supported(struct rte_eth_dev *dev)
4794 {
4795         return is_device_supported(dev, &rte_ixgbe_pmd);
4796 }
4797
4798 static int
4799 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4800 {
4801         uint32_t hlreg0;
4802         uint32_t maxfrs;
4803         struct ixgbe_hw *hw;
4804         struct rte_eth_dev_info dev_info;
4805         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4806         struct rte_eth_dev_data *dev_data = dev->data;
4807
4808         ixgbe_dev_info_get(dev, &dev_info);
4809
4810         /* check that mtu is within the allowed range */
4811         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4812                 return -EINVAL;
4813
4814         /* If device is started, refuse mtu that requires the support of
4815          * scattered packets when this feature has not been enabled before.
4816          */
4817         if (dev_data->dev_started && !dev_data->scattered_rx &&
4818             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4819              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4820                 PMD_INIT_LOG(ERR, "Stop port first.");
4821                 return -EINVAL;
4822         }
4823
4824         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4825         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4826
4827         /* switch to jumbo mode if needed */
4828         if (frame_size > ETHER_MAX_LEN) {
4829                 dev->data->dev_conf.rxmode.offloads |=
4830                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4831                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4832         } else {
4833                 dev->data->dev_conf.rxmode.offloads &=
4834                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4835                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4836         }
4837         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4838
4839         /* update max frame size */
4840         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4841
4842         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4843         maxfrs &= 0x0000FFFF;
4844         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4845         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4846
4847         return 0;
4848 }
4849
4850 /*
4851  * Virtual Function operations
4852  */
4853 static void
4854 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4855 {
4856         PMD_INIT_FUNC_TRACE();
4857
4858         /* Clear interrupt mask to stop from interrupts being generated */
4859         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4860
4861         IXGBE_WRITE_FLUSH(hw);
4862 }
4863
4864 static void
4865 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4866 {
4867         PMD_INIT_FUNC_TRACE();
4868
4869         /* VF enable interrupt autoclean */
4870         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4871         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4872         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4873
4874         IXGBE_WRITE_FLUSH(hw);
4875 }
4876
4877 static int
4878 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4879 {
4880         struct rte_eth_conf *conf = &dev->data->dev_conf;
4881         struct ixgbe_adapter *adapter =
4882                         (struct ixgbe_adapter *)dev->data->dev_private;
4883         struct rte_eth_dev_info dev_info;
4884         uint64_t rx_offloads;
4885         uint64_t tx_offloads;
4886
4887         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4888                      dev->data->port_id);
4889
4890         ixgbevf_dev_info_get(dev, &dev_info);
4891         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4892         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4893                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4894                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4895                             rx_offloads, dev_info.rx_offload_capa);
4896                 return -ENOTSUP;
4897         }
4898         tx_offloads = dev->data->dev_conf.txmode.offloads;
4899         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4900                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4901                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4902                             tx_offloads, dev_info.tx_offload_capa);
4903                 return -ENOTSUP;
4904         }
4905
4906         /*
4907          * VF has no ability to enable/disable HW CRC
4908          * Keep the persistent behavior the same as Host PF
4909          */
4910 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4911         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4912                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4913                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4914         }
4915 #else
4916         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4917                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4918                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4919         }
4920 #endif
4921
4922         /*
4923          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4924          * allocation or vector Rx preconditions we will reset it.
4925          */
4926         adapter->rx_bulk_alloc_allowed = true;
4927         adapter->rx_vec_allowed = true;
4928
4929         return 0;
4930 }
4931
4932 static int
4933 ixgbevf_dev_start(struct rte_eth_dev *dev)
4934 {
4935         struct ixgbe_hw *hw =
4936                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4937         uint32_t intr_vector = 0;
4938         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4939         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4940
4941         int err, mask = 0;
4942
4943         PMD_INIT_FUNC_TRACE();
4944
4945         err = hw->mac.ops.reset_hw(hw);
4946         if (err) {
4947                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4948                 return err;
4949         }
4950         hw->mac.get_link_status = true;
4951
4952         /* negotiate mailbox API version to use with the PF. */
4953         ixgbevf_negotiate_api(hw);
4954
4955         ixgbevf_dev_tx_init(dev);
4956
4957         /* This can fail when allocating mbufs for descriptor rings */
4958         err = ixgbevf_dev_rx_init(dev);
4959         if (err) {
4960                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4961                 ixgbe_dev_clear_queues(dev);
4962                 return err;
4963         }
4964
4965         /* Set vfta */
4966         ixgbevf_set_vfta_all(dev, 1);
4967
4968         /* Set HW strip */
4969         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4970                 ETH_VLAN_EXTEND_MASK;
4971         err = ixgbevf_vlan_offload_set(dev, mask);
4972         if (err) {
4973                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4974                 ixgbe_dev_clear_queues(dev);
4975                 return err;
4976         }
4977
4978         ixgbevf_dev_rxtx_start(dev);
4979
4980         ixgbevf_dev_link_update(dev, 0);
4981
4982         /* check and configure queue intr-vector mapping */
4983         if (rte_intr_cap_multiple(intr_handle) &&
4984             dev->data->dev_conf.intr_conf.rxq) {
4985                 /* According to datasheet, only vector 0/1/2 can be used,
4986                  * now only one vector is used for Rx queue
4987                  */
4988                 intr_vector = 1;
4989                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4990                         return -1;
4991         }
4992
4993         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4994                 intr_handle->intr_vec =
4995                         rte_zmalloc("intr_vec",
4996                                     dev->data->nb_rx_queues * sizeof(int), 0);
4997                 if (intr_handle->intr_vec == NULL) {
4998                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4999                                      " intr_vec", dev->data->nb_rx_queues);
5000                         return -ENOMEM;
5001                 }
5002         }
5003         ixgbevf_configure_msix(dev);
5004
5005         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5006          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5007          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5008          * is not cleared, it will fail when following rte_intr_enable( ) tries
5009          * to map Rx queue interrupt to other VFIO vectors.
5010          * So clear uio/vfio intr/evevnfd first to avoid failure.
5011          */
5012         rte_intr_disable(intr_handle);
5013
5014         rte_intr_enable(intr_handle);
5015
5016         /* Re-enable interrupt for VF */
5017         ixgbevf_intr_enable(hw);
5018
5019         return 0;
5020 }
5021
5022 static void
5023 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5024 {
5025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5026         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5027         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5028
5029         PMD_INIT_FUNC_TRACE();
5030
5031         ixgbevf_intr_disable(hw);
5032
5033         hw->adapter_stopped = 1;
5034         ixgbe_stop_adapter(hw);
5035
5036         /*
5037           * Clear what we set, but we still keep shadow_vfta to
5038           * restore after device starts
5039           */
5040         ixgbevf_set_vfta_all(dev, 0);
5041
5042         /* Clear stored conf */
5043         dev->data->scattered_rx = 0;
5044
5045         ixgbe_dev_clear_queues(dev);
5046
5047         /* Clean datapath event and queue/vec mapping */
5048         rte_intr_efd_disable(intr_handle);
5049         if (intr_handle->intr_vec != NULL) {
5050                 rte_free(intr_handle->intr_vec);
5051                 intr_handle->intr_vec = NULL;
5052         }
5053 }
5054
5055 static void
5056 ixgbevf_dev_close(struct rte_eth_dev *dev)
5057 {
5058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5059
5060         PMD_INIT_FUNC_TRACE();
5061
5062         ixgbe_reset_hw(hw);
5063
5064         ixgbevf_dev_stop(dev);
5065
5066         ixgbe_dev_free_queues(dev);
5067
5068         /**
5069          * Remove the VF MAC address ro ensure
5070          * that the VF traffic goes to the PF
5071          * after stop, close and detach of the VF
5072          **/
5073         ixgbevf_remove_mac_addr(dev, 0);
5074 }
5075
5076 /*
5077  * Reset VF device
5078  */
5079 static int
5080 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5081 {
5082         int ret;
5083
5084         ret = eth_ixgbevf_dev_uninit(dev);
5085         if (ret)
5086                 return ret;
5087
5088         ret = eth_ixgbevf_dev_init(dev);
5089
5090         return ret;
5091 }
5092
5093 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5094 {
5095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5096         struct ixgbe_vfta *shadow_vfta =
5097                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5098         int i = 0, j = 0, vfta = 0, mask = 1;
5099
5100         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5101                 vfta = shadow_vfta->vfta[i];
5102                 if (vfta) {
5103                         mask = 1;
5104                         for (j = 0; j < 32; j++) {
5105                                 if (vfta & mask)
5106                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5107                                                        on, false);
5108                                 mask <<= 1;
5109                         }
5110                 }
5111         }
5112
5113 }
5114
5115 static int
5116 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5117 {
5118         struct ixgbe_hw *hw =
5119                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5120         struct ixgbe_vfta *shadow_vfta =
5121                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5122         uint32_t vid_idx = 0;
5123         uint32_t vid_bit = 0;
5124         int ret = 0;
5125
5126         PMD_INIT_FUNC_TRACE();
5127
5128         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5129         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5130         if (ret) {
5131                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5132                 return ret;
5133         }
5134         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5135         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5136
5137         /* Save what we set and retore it after device reset */
5138         if (on)
5139                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5140         else
5141                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5142
5143         return 0;
5144 }
5145
5146 static void
5147 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5148 {
5149         struct ixgbe_hw *hw =
5150                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5151         uint32_t ctrl;
5152
5153         PMD_INIT_FUNC_TRACE();
5154
5155         if (queue >= hw->mac.max_rx_queues)
5156                 return;
5157
5158         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5159         if (on)
5160                 ctrl |= IXGBE_RXDCTL_VME;
5161         else
5162                 ctrl &= ~IXGBE_RXDCTL_VME;
5163         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5164
5165         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5166 }
5167
5168 static int
5169 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5170 {
5171         struct ixgbe_hw *hw =
5172                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5173         struct ixgbe_rx_queue *rxq;
5174         uint16_t i;
5175         int on = 0;
5176
5177         /* VF function only support hw strip feature, others are not support */
5178         if (mask & ETH_VLAN_STRIP_MASK) {
5179                 for (i = 0; i < hw->mac.max_rx_queues; i++) {
5180                         rxq = dev->data->rx_queues[i];
5181                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5182                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5183                 }
5184         }
5185
5186         return 0;
5187 }
5188
5189 int
5190 ixgbe_vt_check(struct ixgbe_hw *hw)
5191 {
5192         uint32_t reg_val;
5193
5194         /* if Virtualization Technology is enabled */
5195         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5196         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5197                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5198                 return -1;
5199         }
5200
5201         return 0;
5202 }
5203
5204 static uint32_t
5205 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5206 {
5207         uint32_t vector = 0;
5208
5209         switch (hw->mac.mc_filter_type) {
5210         case 0:   /* use bits [47:36] of the address */
5211                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5212                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5213                 break;
5214         case 1:   /* use bits [46:35] of the address */
5215                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5216                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5217                 break;
5218         case 2:   /* use bits [45:34] of the address */
5219                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5220                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5221                 break;
5222         case 3:   /* use bits [43:32] of the address */
5223                 vector = ((uc_addr->addr_bytes[4]) |
5224                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5225                 break;
5226         default:  /* Invalid mc_filter_type */
5227                 break;
5228         }
5229
5230         /* vector can only be 12-bits or boundary will be exceeded */
5231         vector &= 0xFFF;
5232         return vector;
5233 }
5234
5235 static int
5236 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5237                         uint8_t on)
5238 {
5239         uint32_t vector;
5240         uint32_t uta_idx;
5241         uint32_t reg_val;
5242         uint32_t uta_shift;
5243         uint32_t rc;
5244         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5245         const uint32_t ixgbe_uta_bit_shift = 5;
5246         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5247         const uint32_t bit1 = 0x1;
5248
5249         struct ixgbe_hw *hw =
5250                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5251         struct ixgbe_uta_info *uta_info =
5252                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5253
5254         /* The UTA table only exists on 82599 hardware and newer */
5255         if (hw->mac.type < ixgbe_mac_82599EB)
5256                 return -ENOTSUP;
5257
5258         vector = ixgbe_uta_vector(hw, mac_addr);
5259         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5260         uta_shift = vector & ixgbe_uta_bit_mask;
5261
5262         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5263         if (rc == on)
5264                 return 0;
5265
5266         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5267         if (on) {
5268                 uta_info->uta_in_use++;
5269                 reg_val |= (bit1 << uta_shift);
5270                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5271         } else {
5272                 uta_info->uta_in_use--;
5273                 reg_val &= ~(bit1 << uta_shift);
5274                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5275         }
5276
5277         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5278
5279         if (uta_info->uta_in_use > 0)
5280                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5281                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5282         else
5283                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5284
5285         return 0;
5286 }
5287
5288 static int
5289 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5290 {
5291         int i;
5292         struct ixgbe_hw *hw =
5293                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5294         struct ixgbe_uta_info *uta_info =
5295                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5296
5297         /* The UTA table only exists on 82599 hardware and newer */
5298         if (hw->mac.type < ixgbe_mac_82599EB)
5299                 return -ENOTSUP;
5300
5301         if (on) {
5302                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5303                         uta_info->uta_shadow[i] = ~0;
5304                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5305                 }
5306         } else {
5307                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5308                         uta_info->uta_shadow[i] = 0;
5309                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5310                 }
5311         }
5312         return 0;
5313
5314 }
5315
5316 uint32_t
5317 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5318 {
5319         uint32_t new_val = orig_val;
5320
5321         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5322                 new_val |= IXGBE_VMOLR_AUPE;
5323         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5324                 new_val |= IXGBE_VMOLR_ROMPE;
5325         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5326                 new_val |= IXGBE_VMOLR_ROPE;
5327         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5328                 new_val |= IXGBE_VMOLR_BAM;
5329         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5330                 new_val |= IXGBE_VMOLR_MPE;
5331
5332         return new_val;
5333 }
5334
5335 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5336 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5337 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5338 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5339 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5340         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5341         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5342
5343 static int
5344 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5345                       struct rte_eth_mirror_conf *mirror_conf,
5346                       uint8_t rule_id, uint8_t on)
5347 {
5348         uint32_t mr_ctl, vlvf;
5349         uint32_t mp_lsb = 0;
5350         uint32_t mv_msb = 0;
5351         uint32_t mv_lsb = 0;
5352         uint32_t mp_msb = 0;
5353         uint8_t i = 0;
5354         int reg_index = 0;
5355         uint64_t vlan_mask = 0;
5356
5357         const uint8_t pool_mask_offset = 32;
5358         const uint8_t vlan_mask_offset = 32;
5359         const uint8_t dst_pool_offset = 8;
5360         const uint8_t rule_mr_offset  = 4;
5361         const uint8_t mirror_rule_mask = 0x0F;
5362
5363         struct ixgbe_mirror_info *mr_info =
5364                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5365         struct ixgbe_hw *hw =
5366                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5367         uint8_t mirror_type = 0;
5368
5369         if (ixgbe_vt_check(hw) < 0)
5370                 return -ENOTSUP;
5371
5372         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5373                 return -EINVAL;
5374
5375         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5376                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5377                             mirror_conf->rule_type);
5378                 return -EINVAL;
5379         }
5380
5381         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5382                 mirror_type |= IXGBE_MRCTL_VLME;
5383                 /* Check if vlan id is valid and find conresponding VLAN ID
5384                  * index in VLVF
5385                  */
5386                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5387                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5388                                 /* search vlan id related pool vlan filter
5389                                  * index
5390                                  */
5391                                 reg_index = ixgbe_find_vlvf_slot(
5392                                                 hw,
5393                                                 mirror_conf->vlan.vlan_id[i],
5394                                                 false);
5395                                 if (reg_index < 0)
5396                                         return -EINVAL;
5397                                 vlvf = IXGBE_READ_REG(hw,
5398                                                       IXGBE_VLVF(reg_index));
5399                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5400                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5401                                       mirror_conf->vlan.vlan_id[i]))
5402                                         vlan_mask |= (1ULL << reg_index);
5403                                 else
5404                                         return -EINVAL;
5405                         }
5406                 }
5407
5408                 if (on) {
5409                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5410                         mv_msb = vlan_mask >> vlan_mask_offset;
5411
5412                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5413                                                 mirror_conf->vlan.vlan_mask;
5414                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5415                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5416                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5417                                                 mirror_conf->vlan.vlan_id[i];
5418                         }
5419                 } else {
5420                         mv_lsb = 0;
5421                         mv_msb = 0;
5422                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5423                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5424                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5425                 }
5426         }
5427
5428         /**
5429          * if enable pool mirror, write related pool mask register,if disable
5430          * pool mirror, clear PFMRVM register
5431          */
5432         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5433                 mirror_type |= IXGBE_MRCTL_VPME;
5434                 if (on) {
5435                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5436                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5437                         mr_info->mr_conf[rule_id].pool_mask =
5438                                         mirror_conf->pool_mask;
5439
5440                 } else {
5441                         mp_lsb = 0;
5442                         mp_msb = 0;
5443                         mr_info->mr_conf[rule_id].pool_mask = 0;
5444                 }
5445         }
5446         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5447                 mirror_type |= IXGBE_MRCTL_UPME;
5448         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5449                 mirror_type |= IXGBE_MRCTL_DPME;
5450
5451         /* read  mirror control register and recalculate it */
5452         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5453
5454         if (on) {
5455                 mr_ctl |= mirror_type;
5456                 mr_ctl &= mirror_rule_mask;
5457                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5458         } else {
5459                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5460         }
5461
5462         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5463         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5464
5465         /* write mirrror control  register */
5466         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5467
5468         /* write pool mirrror control  register */
5469         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5470                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5471                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5472                                 mp_msb);
5473         }
5474         /* write VLAN mirrror control  register */
5475         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5476                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5477                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5478                                 mv_msb);
5479         }
5480
5481         return 0;
5482 }
5483
5484 static int
5485 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5486 {
5487         int mr_ctl = 0;
5488         uint32_t lsb_val = 0;
5489         uint32_t msb_val = 0;
5490         const uint8_t rule_mr_offset = 4;
5491
5492         struct ixgbe_hw *hw =
5493                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5494         struct ixgbe_mirror_info *mr_info =
5495                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5496
5497         if (ixgbe_vt_check(hw) < 0)
5498                 return -ENOTSUP;
5499
5500         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5501                 return -EINVAL;
5502
5503         memset(&mr_info->mr_conf[rule_id], 0,
5504                sizeof(struct rte_eth_mirror_conf));
5505
5506         /* clear PFVMCTL register */
5507         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5508
5509         /* clear pool mask register */
5510         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5511         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5512
5513         /* clear vlan mask register */
5514         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5515         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5516
5517         return 0;
5518 }
5519
5520 static int
5521 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5522 {
5523         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5524         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5525         uint32_t mask;
5526         struct ixgbe_hw *hw =
5527                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5528         uint32_t vec = IXGBE_MISC_VEC_ID;
5529
5530         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5531         if (rte_intr_allow_others(intr_handle))
5532                 vec = IXGBE_RX_VEC_START;
5533         mask |= (1 << vec);
5534         RTE_SET_USED(queue_id);
5535         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5536
5537         rte_intr_enable(intr_handle);
5538
5539         return 0;
5540 }
5541
5542 static int
5543 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5544 {
5545         uint32_t mask;
5546         struct ixgbe_hw *hw =
5547                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5548         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5549         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5550         uint32_t vec = IXGBE_MISC_VEC_ID;
5551
5552         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5553         if (rte_intr_allow_others(intr_handle))
5554                 vec = IXGBE_RX_VEC_START;
5555         mask &= ~(1 << vec);
5556         RTE_SET_USED(queue_id);
5557         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5558
5559         return 0;
5560 }
5561
5562 static int
5563 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5564 {
5565         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5566         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5567         uint32_t mask;
5568         struct ixgbe_hw *hw =
5569                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5570         struct ixgbe_interrupt *intr =
5571                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5572
5573         if (queue_id < 16) {
5574                 ixgbe_disable_intr(hw);
5575                 intr->mask |= (1 << queue_id);
5576                 ixgbe_enable_intr(dev);
5577         } else if (queue_id < 32) {
5578                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5579                 mask &= (1 << queue_id);
5580                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5581         } else if (queue_id < 64) {
5582                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5583                 mask &= (1 << (queue_id - 32));
5584                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5585         }
5586         rte_intr_enable(intr_handle);
5587
5588         return 0;
5589 }
5590
5591 static int
5592 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5593 {
5594         uint32_t mask;
5595         struct ixgbe_hw *hw =
5596                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5597         struct ixgbe_interrupt *intr =
5598                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5599
5600         if (queue_id < 16) {
5601                 ixgbe_disable_intr(hw);
5602                 intr->mask &= ~(1 << queue_id);
5603                 ixgbe_enable_intr(dev);
5604         } else if (queue_id < 32) {
5605                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5606                 mask &= ~(1 << queue_id);
5607                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5608         } else if (queue_id < 64) {
5609                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5610                 mask &= ~(1 << (queue_id - 32));
5611                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5612         }
5613
5614         return 0;
5615 }
5616
5617 static void
5618 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5619                      uint8_t queue, uint8_t msix_vector)
5620 {
5621         uint32_t tmp, idx;
5622
5623         if (direction == -1) {
5624                 /* other causes */
5625                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5626                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5627                 tmp &= ~0xFF;
5628                 tmp |= msix_vector;
5629                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5630         } else {
5631                 /* rx or tx cause */
5632                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5633                 idx = ((16 * (queue & 1)) + (8 * direction));
5634                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5635                 tmp &= ~(0xFF << idx);
5636                 tmp |= (msix_vector << idx);
5637                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5638         }
5639 }
5640
5641 /**
5642  * set the IVAR registers, mapping interrupt causes to vectors
5643  * @param hw
5644  *  pointer to ixgbe_hw struct
5645  * @direction
5646  *  0 for Rx, 1 for Tx, -1 for other causes
5647  * @queue
5648  *  queue to map the corresponding interrupt to
5649  * @msix_vector
5650  *  the vector to map to the corresponding queue
5651  */
5652 static void
5653 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5654                    uint8_t queue, uint8_t msix_vector)
5655 {
5656         uint32_t tmp, idx;
5657
5658         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5659         if (hw->mac.type == ixgbe_mac_82598EB) {
5660                 if (direction == -1)
5661                         direction = 0;
5662                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5663                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5664                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5665                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5666                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5667         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5668                         (hw->mac.type == ixgbe_mac_X540) ||
5669                         (hw->mac.type == ixgbe_mac_X550)) {
5670                 if (direction == -1) {
5671                         /* other causes */
5672                         idx = ((queue & 1) * 8);
5673                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5674                         tmp &= ~(0xFF << idx);
5675                         tmp |= (msix_vector << idx);
5676                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5677                 } else {
5678                         /* rx or tx causes */
5679                         idx = ((16 * (queue & 1)) + (8 * direction));
5680                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5681                         tmp &= ~(0xFF << idx);
5682                         tmp |= (msix_vector << idx);
5683                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5684                 }
5685         }
5686 }
5687
5688 static void
5689 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5690 {
5691         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5692         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5693         struct ixgbe_hw *hw =
5694                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5695         uint32_t q_idx;
5696         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5697         uint32_t base = IXGBE_MISC_VEC_ID;
5698
5699         /* Configure VF other cause ivar */
5700         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5701
5702         /* won't configure msix register if no mapping is done
5703          * between intr vector and event fd.
5704          */
5705         if (!rte_intr_dp_is_en(intr_handle))
5706                 return;
5707
5708         if (rte_intr_allow_others(intr_handle)) {
5709                 base = IXGBE_RX_VEC_START;
5710                 vector_idx = IXGBE_RX_VEC_START;
5711         }
5712
5713         /* Configure all RX queues of VF */
5714         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5715                 /* Force all queue use vector 0,
5716                  * as IXGBE_VF_MAXMSIVECOTR = 1
5717                  */
5718                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5719                 intr_handle->intr_vec[q_idx] = vector_idx;
5720                 if (vector_idx < base + intr_handle->nb_efd - 1)
5721                         vector_idx++;
5722         }
5723 }
5724
5725 /**
5726  * Sets up the hardware to properly generate MSI-X interrupts
5727  * @hw
5728  *  board private structure
5729  */
5730 static void
5731 ixgbe_configure_msix(struct rte_eth_dev *dev)
5732 {
5733         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5734         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5735         struct ixgbe_hw *hw =
5736                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5737         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5738         uint32_t vec = IXGBE_MISC_VEC_ID;
5739         uint32_t mask;
5740         uint32_t gpie;
5741
5742         /* won't configure msix register if no mapping is done
5743          * between intr vector and event fd
5744          */
5745         if (!rte_intr_dp_is_en(intr_handle))
5746                 return;
5747
5748         if (rte_intr_allow_others(intr_handle))
5749                 vec = base = IXGBE_RX_VEC_START;
5750
5751         /* setup GPIE for MSI-x mode */
5752         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5753         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5754                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5755         /* auto clearing and auto setting corresponding bits in EIMS
5756          * when MSI-X interrupt is triggered
5757          */
5758         if (hw->mac.type == ixgbe_mac_82598EB) {
5759                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5760         } else {
5761                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5762                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5763         }
5764         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5765
5766         /* Populate the IVAR table and set the ITR values to the
5767          * corresponding register.
5768          */
5769         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5770              queue_id++) {
5771                 /* by default, 1:1 mapping */
5772                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5773                 intr_handle->intr_vec[queue_id] = vec;
5774                 if (vec < base + intr_handle->nb_efd - 1)
5775                         vec++;
5776         }
5777
5778         switch (hw->mac.type) {
5779         case ixgbe_mac_82598EB:
5780                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5781                                    IXGBE_MISC_VEC_ID);
5782                 break;
5783         case ixgbe_mac_82599EB:
5784         case ixgbe_mac_X540:
5785         case ixgbe_mac_X550:
5786                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5787                 break;
5788         default:
5789                 break;
5790         }
5791         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5792                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5793
5794         /* set up to autoclear timer, and the vectors */
5795         mask = IXGBE_EIMS_ENABLE_MASK;
5796         mask &= ~(IXGBE_EIMS_OTHER |
5797                   IXGBE_EIMS_MAILBOX |
5798                   IXGBE_EIMS_LSC);
5799
5800         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5801 }
5802
5803 int
5804 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5805                            uint16_t queue_idx, uint16_t tx_rate)
5806 {
5807         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5808         struct rte_eth_rxmode *rxmode;
5809         uint32_t rf_dec, rf_int;
5810         uint32_t bcnrc_val;
5811         uint16_t link_speed = dev->data->dev_link.link_speed;
5812
5813         if (queue_idx >= hw->mac.max_tx_queues)
5814                 return -EINVAL;
5815
5816         if (tx_rate != 0) {
5817                 /* Calculate the rate factor values to set */
5818                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5819                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5820                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5821
5822                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5823                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5824                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5825                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5826         } else {
5827                 bcnrc_val = 0;
5828         }
5829
5830         rxmode = &dev->data->dev_conf.rxmode;
5831         /*
5832          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5833          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5834          * set as 0x4.
5835          */
5836         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5837             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5838                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5839                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5840         else
5841                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5842                         IXGBE_MMW_SIZE_DEFAULT);
5843
5844         /* Set RTTBCNRC of queue X */
5845         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5846         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5847         IXGBE_WRITE_FLUSH(hw);
5848
5849         return 0;
5850 }
5851
5852 static int
5853 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5854                      __attribute__((unused)) uint32_t index,
5855                      __attribute__((unused)) uint32_t pool)
5856 {
5857         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5858         int diag;
5859
5860         /*
5861          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5862          * operation. Trap this case to avoid exhausting the [very limited]
5863          * set of PF resources used to store VF MAC addresses.
5864          */
5865         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5866                 return -1;
5867         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5868         if (diag != 0)
5869                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5870                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5871                             mac_addr->addr_bytes[0],
5872                             mac_addr->addr_bytes[1],
5873                             mac_addr->addr_bytes[2],
5874                             mac_addr->addr_bytes[3],
5875                             mac_addr->addr_bytes[4],
5876                             mac_addr->addr_bytes[5],
5877                             diag);
5878         return diag;
5879 }
5880
5881 static void
5882 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5883 {
5884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5885         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5886         struct ether_addr *mac_addr;
5887         uint32_t i;
5888         int diag;
5889
5890         /*
5891          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5892          * not support the deletion of a given MAC address.
5893          * Instead, it imposes to delete all MAC addresses, then to add again
5894          * all MAC addresses with the exception of the one to be deleted.
5895          */
5896         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5897
5898         /*
5899          * Add again all MAC addresses, with the exception of the deleted one
5900          * and of the permanent MAC address.
5901          */
5902         for (i = 0, mac_addr = dev->data->mac_addrs;
5903              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5904                 /* Skip the deleted MAC address */
5905                 if (i == index)
5906                         continue;
5907                 /* Skip NULL MAC addresses */
5908                 if (is_zero_ether_addr(mac_addr))
5909                         continue;
5910                 /* Skip the permanent MAC address */
5911                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5912                         continue;
5913                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5914                 if (diag != 0)
5915                         PMD_DRV_LOG(ERR,
5916                                     "Adding again MAC address "
5917                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5918                                     "diag=%d",
5919                                     mac_addr->addr_bytes[0],
5920                                     mac_addr->addr_bytes[1],
5921                                     mac_addr->addr_bytes[2],
5922                                     mac_addr->addr_bytes[3],
5923                                     mac_addr->addr_bytes[4],
5924                                     mac_addr->addr_bytes[5],
5925                                     diag);
5926         }
5927 }
5928
5929 static void
5930 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5931 {
5932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5933
5934         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5935 }
5936
5937 int
5938 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5939                         struct rte_eth_syn_filter *filter,
5940                         bool add)
5941 {
5942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5943         struct ixgbe_filter_info *filter_info =
5944                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5945         uint32_t syn_info;
5946         uint32_t synqf;
5947
5948         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5949                 return -EINVAL;
5950
5951         syn_info = filter_info->syn_info;
5952
5953         if (add) {
5954                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5955                         return -EINVAL;
5956                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5957                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5958
5959                 if (filter->hig_pri)
5960                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5961                 else
5962                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5963         } else {
5964                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5965                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5966                         return -ENOENT;
5967                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5968         }
5969
5970         filter_info->syn_info = synqf;
5971         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5972         IXGBE_WRITE_FLUSH(hw);
5973         return 0;
5974 }
5975
5976 static int
5977 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5978                         struct rte_eth_syn_filter *filter)
5979 {
5980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5981         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5982
5983         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5984                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5985                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5986                 return 0;
5987         }
5988         return -ENOENT;
5989 }
5990
5991 static int
5992 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5993                         enum rte_filter_op filter_op,
5994                         void *arg)
5995 {
5996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5997         int ret;
5998
5999         MAC_TYPE_FILTER_SUP(hw->mac.type);
6000
6001         if (filter_op == RTE_ETH_FILTER_NOP)
6002                 return 0;
6003
6004         if (arg == NULL) {
6005                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6006                             filter_op);
6007                 return -EINVAL;
6008         }
6009
6010         switch (filter_op) {
6011         case RTE_ETH_FILTER_ADD:
6012                 ret = ixgbe_syn_filter_set(dev,
6013                                 (struct rte_eth_syn_filter *)arg,
6014                                 TRUE);
6015                 break;
6016         case RTE_ETH_FILTER_DELETE:
6017                 ret = ixgbe_syn_filter_set(dev,
6018                                 (struct rte_eth_syn_filter *)arg,
6019                                 FALSE);
6020                 break;
6021         case RTE_ETH_FILTER_GET:
6022                 ret = ixgbe_syn_filter_get(dev,
6023                                 (struct rte_eth_syn_filter *)arg);
6024                 break;
6025         default:
6026                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6027                 ret = -EINVAL;
6028                 break;
6029         }
6030
6031         return ret;
6032 }
6033
6034
6035 static inline enum ixgbe_5tuple_protocol
6036 convert_protocol_type(uint8_t protocol_value)
6037 {
6038         if (protocol_value == IPPROTO_TCP)
6039                 return IXGBE_FILTER_PROTOCOL_TCP;
6040         else if (protocol_value == IPPROTO_UDP)
6041                 return IXGBE_FILTER_PROTOCOL_UDP;
6042         else if (protocol_value == IPPROTO_SCTP)
6043                 return IXGBE_FILTER_PROTOCOL_SCTP;
6044         else
6045                 return IXGBE_FILTER_PROTOCOL_NONE;
6046 }
6047
6048 /* inject a 5-tuple filter to HW */
6049 static inline void
6050 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6051                            struct ixgbe_5tuple_filter *filter)
6052 {
6053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6054         int i;
6055         uint32_t ftqf, sdpqf;
6056         uint32_t l34timir = 0;
6057         uint8_t mask = 0xff;
6058
6059         i = filter->index;
6060
6061         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6062                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6063         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6064
6065         ftqf = (uint32_t)(filter->filter_info.proto &
6066                 IXGBE_FTQF_PROTOCOL_MASK);
6067         ftqf |= (uint32_t)((filter->filter_info.priority &
6068                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6069         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6070                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6071         if (filter->filter_info.dst_ip_mask == 0)
6072                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6073         if (filter->filter_info.src_port_mask == 0)
6074                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6075         if (filter->filter_info.dst_port_mask == 0)
6076                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6077         if (filter->filter_info.proto_mask == 0)
6078                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6079         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6080         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6081         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6082
6083         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6084         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6085         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6086         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6087
6088         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6089         l34timir |= (uint32_t)(filter->queue <<
6090                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6091         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6092 }
6093
6094 /*
6095  * add a 5tuple filter
6096  *
6097  * @param
6098  * dev: Pointer to struct rte_eth_dev.
6099  * index: the index the filter allocates.
6100  * filter: ponter to the filter that will be added.
6101  * rx_queue: the queue id the filter assigned to.
6102  *
6103  * @return
6104  *    - On success, zero.
6105  *    - On failure, a negative value.
6106  */
6107 static int
6108 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6109                         struct ixgbe_5tuple_filter *filter)
6110 {
6111         struct ixgbe_filter_info *filter_info =
6112                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6113         int i, idx, shift;
6114
6115         /*
6116          * look for an unused 5tuple filter index,
6117          * and insert the filter to list.
6118          */
6119         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6120                 idx = i / (sizeof(uint32_t) * NBBY);
6121                 shift = i % (sizeof(uint32_t) * NBBY);
6122                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6123                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6124                         filter->index = i;
6125                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6126                                           filter,
6127                                           entries);
6128                         break;
6129                 }
6130         }
6131         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6132                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6133                 return -ENOSYS;
6134         }
6135
6136         ixgbe_inject_5tuple_filter(dev, filter);
6137
6138         return 0;
6139 }
6140
6141 /*
6142  * remove a 5tuple filter
6143  *
6144  * @param
6145  * dev: Pointer to struct rte_eth_dev.
6146  * filter: the pointer of the filter will be removed.
6147  */
6148 static void
6149 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6150                         struct ixgbe_5tuple_filter *filter)
6151 {
6152         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6153         struct ixgbe_filter_info *filter_info =
6154                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6155         uint16_t index = filter->index;
6156
6157         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6158                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6159         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6160         rte_free(filter);
6161
6162         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6163         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6164         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6165         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6166         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6167 }
6168
6169 static int
6170 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6171 {
6172         struct ixgbe_hw *hw;
6173         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6174         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6175
6176         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6177
6178         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6179                 return -EINVAL;
6180
6181         /* refuse mtu that requires the support of scattered packets when this
6182          * feature has not been enabled before.
6183          */
6184         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6185             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6186              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6187                 return -EINVAL;
6188
6189         /*
6190          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6191          * request of the version 2.0 of the mailbox API.
6192          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6193          * of the mailbox API.
6194          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6195          * prior to 3.11.33 which contains the following change:
6196          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6197          */
6198         ixgbevf_rlpml_set_vf(hw, max_frame);
6199
6200         /* update max frame size */
6201         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6202         return 0;
6203 }
6204
6205 static inline struct ixgbe_5tuple_filter *
6206 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6207                         struct ixgbe_5tuple_filter_info *key)
6208 {
6209         struct ixgbe_5tuple_filter *it;
6210
6211         TAILQ_FOREACH(it, filter_list, entries) {
6212                 if (memcmp(key, &it->filter_info,
6213                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6214                         return it;
6215                 }
6216         }
6217         return NULL;
6218 }
6219
6220 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6221 static inline int
6222 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6223                         struct ixgbe_5tuple_filter_info *filter_info)
6224 {
6225         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6226                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6227                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6228                 return -EINVAL;
6229
6230         switch (filter->dst_ip_mask) {
6231         case UINT32_MAX:
6232                 filter_info->dst_ip_mask = 0;
6233                 filter_info->dst_ip = filter->dst_ip;
6234                 break;
6235         case 0:
6236                 filter_info->dst_ip_mask = 1;
6237                 break;
6238         default:
6239                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6240                 return -EINVAL;
6241         }
6242
6243         switch (filter->src_ip_mask) {
6244         case UINT32_MAX:
6245                 filter_info->src_ip_mask = 0;
6246                 filter_info->src_ip = filter->src_ip;
6247                 break;
6248         case 0:
6249                 filter_info->src_ip_mask = 1;
6250                 break;
6251         default:
6252                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6253                 return -EINVAL;
6254         }
6255
6256         switch (filter->dst_port_mask) {
6257         case UINT16_MAX:
6258                 filter_info->dst_port_mask = 0;
6259                 filter_info->dst_port = filter->dst_port;
6260                 break;
6261         case 0:
6262                 filter_info->dst_port_mask = 1;
6263                 break;
6264         default:
6265                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6266                 return -EINVAL;
6267         }
6268
6269         switch (filter->src_port_mask) {
6270         case UINT16_MAX:
6271                 filter_info->src_port_mask = 0;
6272                 filter_info->src_port = filter->src_port;
6273                 break;
6274         case 0:
6275                 filter_info->src_port_mask = 1;
6276                 break;
6277         default:
6278                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6279                 return -EINVAL;
6280         }
6281
6282         switch (filter->proto_mask) {
6283         case UINT8_MAX:
6284                 filter_info->proto_mask = 0;
6285                 filter_info->proto =
6286                         convert_protocol_type(filter->proto);
6287                 break;
6288         case 0:
6289                 filter_info->proto_mask = 1;
6290                 break;
6291         default:
6292                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6293                 return -EINVAL;
6294         }
6295
6296         filter_info->priority = (uint8_t)filter->priority;
6297         return 0;
6298 }
6299
6300 /*
6301  * add or delete a ntuple filter
6302  *
6303  * @param
6304  * dev: Pointer to struct rte_eth_dev.
6305  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6306  * add: if true, add filter, if false, remove filter
6307  *
6308  * @return
6309  *    - On success, zero.
6310  *    - On failure, a negative value.
6311  */
6312 int
6313 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6314                         struct rte_eth_ntuple_filter *ntuple_filter,
6315                         bool add)
6316 {
6317         struct ixgbe_filter_info *filter_info =
6318                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6319         struct ixgbe_5tuple_filter_info filter_5tuple;
6320         struct ixgbe_5tuple_filter *filter;
6321         int ret;
6322
6323         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6324                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6325                 return -EINVAL;
6326         }
6327
6328         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6329         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6330         if (ret < 0)
6331                 return ret;
6332
6333         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6334                                          &filter_5tuple);
6335         if (filter != NULL && add) {
6336                 PMD_DRV_LOG(ERR, "filter exists.");
6337                 return -EEXIST;
6338         }
6339         if (filter == NULL && !add) {
6340                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6341                 return -ENOENT;
6342         }
6343
6344         if (add) {
6345                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6346                                 sizeof(struct ixgbe_5tuple_filter), 0);
6347                 if (filter == NULL)
6348                         return -ENOMEM;
6349                 rte_memcpy(&filter->filter_info,
6350                                  &filter_5tuple,
6351                                  sizeof(struct ixgbe_5tuple_filter_info));
6352                 filter->queue = ntuple_filter->queue;
6353                 ret = ixgbe_add_5tuple_filter(dev, filter);
6354                 if (ret < 0) {
6355                         rte_free(filter);
6356                         return ret;
6357                 }
6358         } else
6359                 ixgbe_remove_5tuple_filter(dev, filter);
6360
6361         return 0;
6362 }
6363
6364 /*
6365  * get a ntuple filter
6366  *
6367  * @param
6368  * dev: Pointer to struct rte_eth_dev.
6369  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6370  *
6371  * @return
6372  *    - On success, zero.
6373  *    - On failure, a negative value.
6374  */
6375 static int
6376 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6377                         struct rte_eth_ntuple_filter *ntuple_filter)
6378 {
6379         struct ixgbe_filter_info *filter_info =
6380                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6381         struct ixgbe_5tuple_filter_info filter_5tuple;
6382         struct ixgbe_5tuple_filter *filter;
6383         int ret;
6384
6385         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6386                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6387                 return -EINVAL;
6388         }
6389
6390         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6391         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6392         if (ret < 0)
6393                 return ret;
6394
6395         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6396                                          &filter_5tuple);
6397         if (filter == NULL) {
6398                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6399                 return -ENOENT;
6400         }
6401         ntuple_filter->queue = filter->queue;
6402         return 0;
6403 }
6404
6405 /*
6406  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6407  * @dev: pointer to rte_eth_dev structure
6408  * @filter_op:operation will be taken.
6409  * @arg: a pointer to specific structure corresponding to the filter_op
6410  *
6411  * @return
6412  *    - On success, zero.
6413  *    - On failure, a negative value.
6414  */
6415 static int
6416 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6417                                 enum rte_filter_op filter_op,
6418                                 void *arg)
6419 {
6420         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6421         int ret;
6422
6423         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6424
6425         if (filter_op == RTE_ETH_FILTER_NOP)
6426                 return 0;
6427
6428         if (arg == NULL) {
6429                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6430                             filter_op);
6431                 return -EINVAL;
6432         }
6433
6434         switch (filter_op) {
6435         case RTE_ETH_FILTER_ADD:
6436                 ret = ixgbe_add_del_ntuple_filter(dev,
6437                         (struct rte_eth_ntuple_filter *)arg,
6438                         TRUE);
6439                 break;
6440         case RTE_ETH_FILTER_DELETE:
6441                 ret = ixgbe_add_del_ntuple_filter(dev,
6442                         (struct rte_eth_ntuple_filter *)arg,
6443                         FALSE);
6444                 break;
6445         case RTE_ETH_FILTER_GET:
6446                 ret = ixgbe_get_ntuple_filter(dev,
6447                         (struct rte_eth_ntuple_filter *)arg);
6448                 break;
6449         default:
6450                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6451                 ret = -EINVAL;
6452                 break;
6453         }
6454         return ret;
6455 }
6456
6457 int
6458 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6459                         struct rte_eth_ethertype_filter *filter,
6460                         bool add)
6461 {
6462         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6463         struct ixgbe_filter_info *filter_info =
6464                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6465         uint32_t etqf = 0;
6466         uint32_t etqs = 0;
6467         int ret;
6468         struct ixgbe_ethertype_filter ethertype_filter;
6469
6470         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6471                 return -EINVAL;
6472
6473         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6474                 filter->ether_type == ETHER_TYPE_IPv6) {
6475                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6476                         " ethertype filter.", filter->ether_type);
6477                 return -EINVAL;
6478         }
6479
6480         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6481                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6482                 return -EINVAL;
6483         }
6484         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6485                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6486                 return -EINVAL;
6487         }
6488
6489         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6490         if (ret >= 0 && add) {
6491                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6492                             filter->ether_type);
6493                 return -EEXIST;
6494         }
6495         if (ret < 0 && !add) {
6496                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6497                             filter->ether_type);
6498                 return -ENOENT;
6499         }
6500
6501         if (add) {
6502                 etqf = IXGBE_ETQF_FILTER_EN;
6503                 etqf |= (uint32_t)filter->ether_type;
6504                 etqs |= (uint32_t)((filter->queue <<
6505                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6506                                     IXGBE_ETQS_RX_QUEUE);
6507                 etqs |= IXGBE_ETQS_QUEUE_EN;
6508
6509                 ethertype_filter.ethertype = filter->ether_type;
6510                 ethertype_filter.etqf = etqf;
6511                 ethertype_filter.etqs = etqs;
6512                 ethertype_filter.conf = FALSE;
6513                 ret = ixgbe_ethertype_filter_insert(filter_info,
6514                                                     &ethertype_filter);
6515                 if (ret < 0) {
6516                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6517                         return -ENOSPC;
6518                 }
6519         } else {
6520                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6521                 if (ret < 0)
6522                         return -ENOSYS;
6523         }
6524         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6525         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6526         IXGBE_WRITE_FLUSH(hw);
6527
6528         return 0;
6529 }
6530
6531 static int
6532 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6533                         struct rte_eth_ethertype_filter *filter)
6534 {
6535         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6536         struct ixgbe_filter_info *filter_info =
6537                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6538         uint32_t etqf, etqs;
6539         int ret;
6540
6541         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6542         if (ret < 0) {
6543                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6544                             filter->ether_type);
6545                 return -ENOENT;
6546         }
6547
6548         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6549         if (etqf & IXGBE_ETQF_FILTER_EN) {
6550                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6551                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6552                 filter->flags = 0;
6553                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6554                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6555                 return 0;
6556         }
6557         return -ENOENT;
6558 }
6559
6560 /*
6561  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6562  * @dev: pointer to rte_eth_dev structure
6563  * @filter_op:operation will be taken.
6564  * @arg: a pointer to specific structure corresponding to the filter_op
6565  */
6566 static int
6567 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6568                                 enum rte_filter_op filter_op,
6569                                 void *arg)
6570 {
6571         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6572         int ret;
6573
6574         MAC_TYPE_FILTER_SUP(hw->mac.type);
6575
6576         if (filter_op == RTE_ETH_FILTER_NOP)
6577                 return 0;
6578
6579         if (arg == NULL) {
6580                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6581                             filter_op);
6582                 return -EINVAL;
6583         }
6584
6585         switch (filter_op) {
6586         case RTE_ETH_FILTER_ADD:
6587                 ret = ixgbe_add_del_ethertype_filter(dev,
6588                         (struct rte_eth_ethertype_filter *)arg,
6589                         TRUE);
6590                 break;
6591         case RTE_ETH_FILTER_DELETE:
6592                 ret = ixgbe_add_del_ethertype_filter(dev,
6593                         (struct rte_eth_ethertype_filter *)arg,
6594                         FALSE);
6595                 break;
6596         case RTE_ETH_FILTER_GET:
6597                 ret = ixgbe_get_ethertype_filter(dev,
6598                         (struct rte_eth_ethertype_filter *)arg);
6599                 break;
6600         default:
6601                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6602                 ret = -EINVAL;
6603                 break;
6604         }
6605         return ret;
6606 }
6607
6608 static int
6609 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6610                      enum rte_filter_type filter_type,
6611                      enum rte_filter_op filter_op,
6612                      void *arg)
6613 {
6614         int ret = 0;
6615
6616         switch (filter_type) {
6617         case RTE_ETH_FILTER_NTUPLE:
6618                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6619                 break;
6620         case RTE_ETH_FILTER_ETHERTYPE:
6621                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6622                 break;
6623         case RTE_ETH_FILTER_SYN:
6624                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6625                 break;
6626         case RTE_ETH_FILTER_FDIR:
6627                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6628                 break;
6629         case RTE_ETH_FILTER_L2_TUNNEL:
6630                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6631                 break;
6632         case RTE_ETH_FILTER_GENERIC:
6633                 if (filter_op != RTE_ETH_FILTER_GET)
6634                         return -EINVAL;
6635                 *(const void **)arg = &ixgbe_flow_ops;
6636                 break;
6637         default:
6638                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6639                                                         filter_type);
6640                 ret = -EINVAL;
6641                 break;
6642         }
6643
6644         return ret;
6645 }
6646
6647 static u8 *
6648 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6649                         u8 **mc_addr_ptr, u32 *vmdq)
6650 {
6651         u8 *mc_addr;
6652
6653         *vmdq = 0;
6654         mc_addr = *mc_addr_ptr;
6655         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6656         return mc_addr;
6657 }
6658
6659 static int
6660 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6661                           struct ether_addr *mc_addr_set,
6662                           uint32_t nb_mc_addr)
6663 {
6664         struct ixgbe_hw *hw;
6665         u8 *mc_addr_list;
6666
6667         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6668         mc_addr_list = (u8 *)mc_addr_set;
6669         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6670                                          ixgbe_dev_addr_list_itr, TRUE);
6671 }
6672
6673 static uint64_t
6674 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6675 {
6676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6677         uint64_t systime_cycles;
6678
6679         switch (hw->mac.type) {
6680         case ixgbe_mac_X550:
6681         case ixgbe_mac_X550EM_x:
6682         case ixgbe_mac_X550EM_a:
6683                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6684                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6685                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6686                                 * NSEC_PER_SEC;
6687                 break;
6688         default:
6689                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6690                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6691                                 << 32;
6692         }
6693
6694         return systime_cycles;
6695 }
6696
6697 static uint64_t
6698 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6699 {
6700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6701         uint64_t rx_tstamp_cycles;
6702
6703         switch (hw->mac.type) {
6704         case ixgbe_mac_X550:
6705         case ixgbe_mac_X550EM_x:
6706         case ixgbe_mac_X550EM_a:
6707                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6708                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6709                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6710                                 * NSEC_PER_SEC;
6711                 break;
6712         default:
6713                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6714                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6715                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6716                                 << 32;
6717         }
6718
6719         return rx_tstamp_cycles;
6720 }
6721
6722 static uint64_t
6723 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6724 {
6725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6726         uint64_t tx_tstamp_cycles;
6727
6728         switch (hw->mac.type) {
6729         case ixgbe_mac_X550:
6730         case ixgbe_mac_X550EM_x:
6731         case ixgbe_mac_X550EM_a:
6732                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6733                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6734                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6735                                 * NSEC_PER_SEC;
6736                 break;
6737         default:
6738                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6739                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6740                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6741                                 << 32;
6742         }
6743
6744         return tx_tstamp_cycles;
6745 }
6746
6747 static void
6748 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6749 {
6750         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6751         struct ixgbe_adapter *adapter =
6752                 (struct ixgbe_adapter *)dev->data->dev_private;
6753         struct rte_eth_link link;
6754         uint32_t incval = 0;
6755         uint32_t shift = 0;
6756
6757         /* Get current link speed. */
6758         ixgbe_dev_link_update(dev, 1);
6759         rte_eth_linkstatus_get(dev, &link);
6760
6761         switch (link.link_speed) {
6762         case ETH_SPEED_NUM_100M:
6763                 incval = IXGBE_INCVAL_100;
6764                 shift = IXGBE_INCVAL_SHIFT_100;
6765                 break;
6766         case ETH_SPEED_NUM_1G:
6767                 incval = IXGBE_INCVAL_1GB;
6768                 shift = IXGBE_INCVAL_SHIFT_1GB;
6769                 break;
6770         case ETH_SPEED_NUM_10G:
6771         default:
6772                 incval = IXGBE_INCVAL_10GB;
6773                 shift = IXGBE_INCVAL_SHIFT_10GB;
6774                 break;
6775         }
6776
6777         switch (hw->mac.type) {
6778         case ixgbe_mac_X550:
6779         case ixgbe_mac_X550EM_x:
6780         case ixgbe_mac_X550EM_a:
6781                 /* Independent of link speed. */
6782                 incval = 1;
6783                 /* Cycles read will be interpreted as ns. */
6784                 shift = 0;
6785                 /* Fall-through */
6786         case ixgbe_mac_X540:
6787                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6788                 break;
6789         case ixgbe_mac_82599EB:
6790                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6791                 shift -= IXGBE_INCVAL_SHIFT_82599;
6792                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6793                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6794                 break;
6795         default:
6796                 /* Not supported. */
6797                 return;
6798         }
6799
6800         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6801         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6802         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6803
6804         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6805         adapter->systime_tc.cc_shift = shift;
6806         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6807
6808         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6809         adapter->rx_tstamp_tc.cc_shift = shift;
6810         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6811
6812         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6813         adapter->tx_tstamp_tc.cc_shift = shift;
6814         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6815 }
6816
6817 static int
6818 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6819 {
6820         struct ixgbe_adapter *adapter =
6821                         (struct ixgbe_adapter *)dev->data->dev_private;
6822
6823         adapter->systime_tc.nsec += delta;
6824         adapter->rx_tstamp_tc.nsec += delta;
6825         adapter->tx_tstamp_tc.nsec += delta;
6826
6827         return 0;
6828 }
6829
6830 static int
6831 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6832 {
6833         uint64_t ns;
6834         struct ixgbe_adapter *adapter =
6835                         (struct ixgbe_adapter *)dev->data->dev_private;
6836
6837         ns = rte_timespec_to_ns(ts);
6838         /* Set the timecounters to a new value. */
6839         adapter->systime_tc.nsec = ns;
6840         adapter->rx_tstamp_tc.nsec = ns;
6841         adapter->tx_tstamp_tc.nsec = ns;
6842
6843         return 0;
6844 }
6845
6846 static int
6847 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6848 {
6849         uint64_t ns, systime_cycles;
6850         struct ixgbe_adapter *adapter =
6851                         (struct ixgbe_adapter *)dev->data->dev_private;
6852
6853         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6854         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6855         *ts = rte_ns_to_timespec(ns);
6856
6857         return 0;
6858 }
6859
6860 static int
6861 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6862 {
6863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6864         uint32_t tsync_ctl;
6865         uint32_t tsauxc;
6866
6867         /* Stop the timesync system time. */
6868         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6869         /* Reset the timesync system time value. */
6870         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6871         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6872
6873         /* Enable system time for platforms where it isn't on by default. */
6874         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6875         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6876         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6877
6878         ixgbe_start_timecounters(dev);
6879
6880         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6881         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6882                         (ETHER_TYPE_1588 |
6883                          IXGBE_ETQF_FILTER_EN |
6884                          IXGBE_ETQF_1588));
6885
6886         /* Enable timestamping of received PTP packets. */
6887         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6888         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6889         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6890
6891         /* Enable timestamping of transmitted PTP packets. */
6892         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6893         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6894         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6895
6896         IXGBE_WRITE_FLUSH(hw);
6897
6898         return 0;
6899 }
6900
6901 static int
6902 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6903 {
6904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6905         uint32_t tsync_ctl;
6906
6907         /* Disable timestamping of transmitted PTP packets. */
6908         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6909         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6910         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6911
6912         /* Disable timestamping of received PTP packets. */
6913         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6914         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6915         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6916
6917         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6918         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6919
6920         /* Stop incrementating the System Time registers. */
6921         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6922
6923         return 0;
6924 }
6925
6926 static int
6927 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6928                                  struct timespec *timestamp,
6929                                  uint32_t flags __rte_unused)
6930 {
6931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6932         struct ixgbe_adapter *adapter =
6933                 (struct ixgbe_adapter *)dev->data->dev_private;
6934         uint32_t tsync_rxctl;
6935         uint64_t rx_tstamp_cycles;
6936         uint64_t ns;
6937
6938         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6939         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6940                 return -EINVAL;
6941
6942         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6943         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6944         *timestamp = rte_ns_to_timespec(ns);
6945
6946         return  0;
6947 }
6948
6949 static int
6950 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6951                                  struct timespec *timestamp)
6952 {
6953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6954         struct ixgbe_adapter *adapter =
6955                 (struct ixgbe_adapter *)dev->data->dev_private;
6956         uint32_t tsync_txctl;
6957         uint64_t tx_tstamp_cycles;
6958         uint64_t ns;
6959
6960         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6961         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6962                 return -EINVAL;
6963
6964         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6965         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6966         *timestamp = rte_ns_to_timespec(ns);
6967
6968         return 0;
6969 }
6970
6971 static int
6972 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6973 {
6974         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6975         int count = 0;
6976         int g_ind = 0;
6977         const struct reg_info *reg_group;
6978         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6979                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6980
6981         while ((reg_group = reg_set[g_ind++]))
6982                 count += ixgbe_regs_group_count(reg_group);
6983
6984         return count;
6985 }
6986
6987 static int
6988 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6989 {
6990         int count = 0;
6991         int g_ind = 0;
6992         const struct reg_info *reg_group;
6993
6994         while ((reg_group = ixgbevf_regs[g_ind++]))
6995                 count += ixgbe_regs_group_count(reg_group);
6996
6997         return count;
6998 }
6999
7000 static int
7001 ixgbe_get_regs(struct rte_eth_dev *dev,
7002               struct rte_dev_reg_info *regs)
7003 {
7004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7005         uint32_t *data = regs->data;
7006         int g_ind = 0;
7007         int count = 0;
7008         const struct reg_info *reg_group;
7009         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7010                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7011
7012         if (data == NULL) {
7013                 regs->length = ixgbe_get_reg_length(dev);
7014                 regs->width = sizeof(uint32_t);
7015                 return 0;
7016         }
7017
7018         /* Support only full register dump */
7019         if ((regs->length == 0) ||
7020             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7021                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7022                         hw->device_id;
7023                 while ((reg_group = reg_set[g_ind++]))
7024                         count += ixgbe_read_regs_group(dev, &data[count],
7025                                 reg_group);
7026                 return 0;
7027         }
7028
7029         return -ENOTSUP;
7030 }
7031
7032 static int
7033 ixgbevf_get_regs(struct rte_eth_dev *dev,
7034                 struct rte_dev_reg_info *regs)
7035 {
7036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7037         uint32_t *data = regs->data;
7038         int g_ind = 0;
7039         int count = 0;
7040         const struct reg_info *reg_group;
7041
7042         if (data == NULL) {
7043                 regs->length = ixgbevf_get_reg_length(dev);
7044                 regs->width = sizeof(uint32_t);
7045                 return 0;
7046         }
7047
7048         /* Support only full register dump */
7049         if ((regs->length == 0) ||
7050             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7051                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7052                         hw->device_id;
7053                 while ((reg_group = ixgbevf_regs[g_ind++]))
7054                         count += ixgbe_read_regs_group(dev, &data[count],
7055                                                       reg_group);
7056                 return 0;
7057         }
7058
7059         return -ENOTSUP;
7060 }
7061
7062 static int
7063 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7064 {
7065         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7066
7067         /* Return unit is byte count */
7068         return hw->eeprom.word_size * 2;
7069 }
7070
7071 static int
7072 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7073                 struct rte_dev_eeprom_info *in_eeprom)
7074 {
7075         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7076         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7077         uint16_t *data = in_eeprom->data;
7078         int first, length;
7079
7080         first = in_eeprom->offset >> 1;
7081         length = in_eeprom->length >> 1;
7082         if ((first > hw->eeprom.word_size) ||
7083             ((first + length) > hw->eeprom.word_size))
7084                 return -EINVAL;
7085
7086         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7087
7088         return eeprom->ops.read_buffer(hw, first, length, data);
7089 }
7090
7091 static int
7092 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7093                 struct rte_dev_eeprom_info *in_eeprom)
7094 {
7095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7096         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7097         uint16_t *data = in_eeprom->data;
7098         int first, length;
7099
7100         first = in_eeprom->offset >> 1;
7101         length = in_eeprom->length >> 1;
7102         if ((first > hw->eeprom.word_size) ||
7103             ((first + length) > hw->eeprom.word_size))
7104                 return -EINVAL;
7105
7106         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7107
7108         return eeprom->ops.write_buffer(hw,  first, length, data);
7109 }
7110
7111 uint16_t
7112 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7113         switch (mac_type) {
7114         case ixgbe_mac_X550:
7115         case ixgbe_mac_X550EM_x:
7116         case ixgbe_mac_X550EM_a:
7117                 return ETH_RSS_RETA_SIZE_512;
7118         case ixgbe_mac_X550_vf:
7119         case ixgbe_mac_X550EM_x_vf:
7120         case ixgbe_mac_X550EM_a_vf:
7121                 return ETH_RSS_RETA_SIZE_64;
7122         default:
7123                 return ETH_RSS_RETA_SIZE_128;
7124         }
7125 }
7126
7127 uint32_t
7128 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7129         switch (mac_type) {
7130         case ixgbe_mac_X550:
7131         case ixgbe_mac_X550EM_x:
7132         case ixgbe_mac_X550EM_a:
7133                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7134                         return IXGBE_RETA(reta_idx >> 2);
7135                 else
7136                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7137         case ixgbe_mac_X550_vf:
7138         case ixgbe_mac_X550EM_x_vf:
7139         case ixgbe_mac_X550EM_a_vf:
7140                 return IXGBE_VFRETA(reta_idx >> 2);
7141         default:
7142                 return IXGBE_RETA(reta_idx >> 2);
7143         }
7144 }
7145
7146 uint32_t
7147 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7148         switch (mac_type) {
7149         case ixgbe_mac_X550_vf:
7150         case ixgbe_mac_X550EM_x_vf:
7151         case ixgbe_mac_X550EM_a_vf:
7152                 return IXGBE_VFMRQC;
7153         default:
7154                 return IXGBE_MRQC;
7155         }
7156 }
7157
7158 uint32_t
7159 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7160         switch (mac_type) {
7161         case ixgbe_mac_X550_vf:
7162         case ixgbe_mac_X550EM_x_vf:
7163         case ixgbe_mac_X550EM_a_vf:
7164                 return IXGBE_VFRSSRK(i);
7165         default:
7166                 return IXGBE_RSSRK(i);
7167         }
7168 }
7169
7170 bool
7171 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7172         switch (mac_type) {
7173         case ixgbe_mac_82599_vf:
7174         case ixgbe_mac_X540_vf:
7175                 return 0;
7176         default:
7177                 return 1;
7178         }
7179 }
7180
7181 static int
7182 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7183                         struct rte_eth_dcb_info *dcb_info)
7184 {
7185         struct ixgbe_dcb_config *dcb_config =
7186                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7187         struct ixgbe_dcb_tc_config *tc;
7188         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7189         uint8_t nb_tcs;
7190         uint8_t i, j;
7191
7192         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7193                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7194         else
7195                 dcb_info->nb_tcs = 1;
7196
7197         tc_queue = &dcb_info->tc_queue;
7198         nb_tcs = dcb_info->nb_tcs;
7199
7200         if (dcb_config->vt_mode) { /* vt is enabled*/
7201                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7202                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7203                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7204                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7205                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7206                         for (j = 0; j < nb_tcs; j++) {
7207                                 tc_queue->tc_rxq[0][j].base = j;
7208                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7209                                 tc_queue->tc_txq[0][j].base = j;
7210                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7211                         }
7212                 } else {
7213                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7214                                 for (j = 0; j < nb_tcs; j++) {
7215                                         tc_queue->tc_rxq[i][j].base =
7216                                                 i * nb_tcs + j;
7217                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7218                                         tc_queue->tc_txq[i][j].base =
7219                                                 i * nb_tcs + j;
7220                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7221                                 }
7222                         }
7223                 }
7224         } else { /* vt is disabled*/
7225                 struct rte_eth_dcb_rx_conf *rx_conf =
7226                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7227                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7228                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7229                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7230                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7231                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7232                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7233                         }
7234                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7235                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7236                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7237                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7238                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7239                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7240                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7241                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7242                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7243                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7244                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7245                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7246                         }
7247                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7248                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7249                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7250                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7251                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7252                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7253                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7254                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7255                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7256                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7257                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7258                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7259                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7260                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7261                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7262                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7263                 }
7264         }
7265         for (i = 0; i < dcb_info->nb_tcs; i++) {
7266                 tc = &dcb_config->tc_config[i];
7267                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7268         }
7269         return 0;
7270 }
7271
7272 /* Update e-tag ether type */
7273 static int
7274 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7275                             uint16_t ether_type)
7276 {
7277         uint32_t etag_etype;
7278
7279         if (hw->mac.type != ixgbe_mac_X550 &&
7280             hw->mac.type != ixgbe_mac_X550EM_x &&
7281             hw->mac.type != ixgbe_mac_X550EM_a) {
7282                 return -ENOTSUP;
7283         }
7284
7285         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7286         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7287         etag_etype |= ether_type;
7288         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7289         IXGBE_WRITE_FLUSH(hw);
7290
7291         return 0;
7292 }
7293
7294 /* Config l2 tunnel ether type */
7295 static int
7296 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7297                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7298 {
7299         int ret = 0;
7300         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7301         struct ixgbe_l2_tn_info *l2_tn_info =
7302                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7303
7304         if (l2_tunnel == NULL)
7305                 return -EINVAL;
7306
7307         switch (l2_tunnel->l2_tunnel_type) {
7308         case RTE_L2_TUNNEL_TYPE_E_TAG:
7309                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7310                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7311                 break;
7312         default:
7313                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7314                 ret = -EINVAL;
7315                 break;
7316         }
7317
7318         return ret;
7319 }
7320
7321 /* Enable e-tag tunnel */
7322 static int
7323 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7324 {
7325         uint32_t etag_etype;
7326
7327         if (hw->mac.type != ixgbe_mac_X550 &&
7328             hw->mac.type != ixgbe_mac_X550EM_x &&
7329             hw->mac.type != ixgbe_mac_X550EM_a) {
7330                 return -ENOTSUP;
7331         }
7332
7333         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7334         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7335         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7336         IXGBE_WRITE_FLUSH(hw);
7337
7338         return 0;
7339 }
7340
7341 /* Enable l2 tunnel */
7342 static int
7343 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7344                            enum rte_eth_tunnel_type l2_tunnel_type)
7345 {
7346         int ret = 0;
7347         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7348         struct ixgbe_l2_tn_info *l2_tn_info =
7349                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7350
7351         switch (l2_tunnel_type) {
7352         case RTE_L2_TUNNEL_TYPE_E_TAG:
7353                 l2_tn_info->e_tag_en = TRUE;
7354                 ret = ixgbe_e_tag_enable(hw);
7355                 break;
7356         default:
7357                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7358                 ret = -EINVAL;
7359                 break;
7360         }
7361
7362         return ret;
7363 }
7364
7365 /* Disable e-tag tunnel */
7366 static int
7367 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7368 {
7369         uint32_t etag_etype;
7370
7371         if (hw->mac.type != ixgbe_mac_X550 &&
7372             hw->mac.type != ixgbe_mac_X550EM_x &&
7373             hw->mac.type != ixgbe_mac_X550EM_a) {
7374                 return -ENOTSUP;
7375         }
7376
7377         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7378         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7379         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7380         IXGBE_WRITE_FLUSH(hw);
7381
7382         return 0;
7383 }
7384
7385 /* Disable l2 tunnel */
7386 static int
7387 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7388                             enum rte_eth_tunnel_type l2_tunnel_type)
7389 {
7390         int ret = 0;
7391         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7392         struct ixgbe_l2_tn_info *l2_tn_info =
7393                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7394
7395         switch (l2_tunnel_type) {
7396         case RTE_L2_TUNNEL_TYPE_E_TAG:
7397                 l2_tn_info->e_tag_en = FALSE;
7398                 ret = ixgbe_e_tag_disable(hw);
7399                 break;
7400         default:
7401                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7402                 ret = -EINVAL;
7403                 break;
7404         }
7405
7406         return ret;
7407 }
7408
7409 static int
7410 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7411                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7412 {
7413         int ret = 0;
7414         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7415         uint32_t i, rar_entries;
7416         uint32_t rar_low, rar_high;
7417
7418         if (hw->mac.type != ixgbe_mac_X550 &&
7419             hw->mac.type != ixgbe_mac_X550EM_x &&
7420             hw->mac.type != ixgbe_mac_X550EM_a) {
7421                 return -ENOTSUP;
7422         }
7423
7424         rar_entries = ixgbe_get_num_rx_addrs(hw);
7425
7426         for (i = 1; i < rar_entries; i++) {
7427                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7428                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7429                 if ((rar_high & IXGBE_RAH_AV) &&
7430                     (rar_high & IXGBE_RAH_ADTYPE) &&
7431                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7432                      l2_tunnel->tunnel_id)) {
7433                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7434                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7435
7436                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7437
7438                         return ret;
7439                 }
7440         }
7441
7442         return ret;
7443 }
7444
7445 static int
7446 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7447                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7448 {
7449         int ret = 0;
7450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7451         uint32_t i, rar_entries;
7452         uint32_t rar_low, rar_high;
7453
7454         if (hw->mac.type != ixgbe_mac_X550 &&
7455             hw->mac.type != ixgbe_mac_X550EM_x &&
7456             hw->mac.type != ixgbe_mac_X550EM_a) {
7457                 return -ENOTSUP;
7458         }
7459
7460         /* One entry for one tunnel. Try to remove potential existing entry. */
7461         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7462
7463         rar_entries = ixgbe_get_num_rx_addrs(hw);
7464
7465         for (i = 1; i < rar_entries; i++) {
7466                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7467                 if (rar_high & IXGBE_RAH_AV) {
7468                         continue;
7469                 } else {
7470                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7471                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7472                         rar_low = l2_tunnel->tunnel_id;
7473
7474                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7475                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7476
7477                         return ret;
7478                 }
7479         }
7480
7481         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7482                      " Please remove a rule before adding a new one.");
7483         return -EINVAL;
7484 }
7485
7486 static inline struct ixgbe_l2_tn_filter *
7487 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7488                           struct ixgbe_l2_tn_key *key)
7489 {
7490         int ret;
7491
7492         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7493         if (ret < 0)
7494                 return NULL;
7495
7496         return l2_tn_info->hash_map[ret];
7497 }
7498
7499 static inline int
7500 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7501                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7502 {
7503         int ret;
7504
7505         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7506                                &l2_tn_filter->key);
7507
7508         if (ret < 0) {
7509                 PMD_DRV_LOG(ERR,
7510                             "Failed to insert L2 tunnel filter"
7511                             " to hash table %d!",
7512                             ret);
7513                 return ret;
7514         }
7515
7516         l2_tn_info->hash_map[ret] = l2_tn_filter;
7517
7518         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7519
7520         return 0;
7521 }
7522
7523 static inline int
7524 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7525                           struct ixgbe_l2_tn_key *key)
7526 {
7527         int ret;
7528         struct ixgbe_l2_tn_filter *l2_tn_filter;
7529
7530         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7531
7532         if (ret < 0) {
7533                 PMD_DRV_LOG(ERR,
7534                             "No such L2 tunnel filter to delete %d!",
7535                             ret);
7536                 return ret;
7537         }
7538
7539         l2_tn_filter = l2_tn_info->hash_map[ret];
7540         l2_tn_info->hash_map[ret] = NULL;
7541
7542         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7543         rte_free(l2_tn_filter);
7544
7545         return 0;
7546 }
7547
7548 /* Add l2 tunnel filter */
7549 int
7550 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7551                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7552                                bool restore)
7553 {
7554         int ret;
7555         struct ixgbe_l2_tn_info *l2_tn_info =
7556                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7557         struct ixgbe_l2_tn_key key;
7558         struct ixgbe_l2_tn_filter *node;
7559
7560         if (!restore) {
7561                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7562                 key.tn_id = l2_tunnel->tunnel_id;
7563
7564                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7565
7566                 if (node) {
7567                         PMD_DRV_LOG(ERR,
7568                                     "The L2 tunnel filter already exists!");
7569                         return -EINVAL;
7570                 }
7571
7572                 node = rte_zmalloc("ixgbe_l2_tn",
7573                                    sizeof(struct ixgbe_l2_tn_filter),
7574                                    0);
7575                 if (!node)
7576                         return -ENOMEM;
7577
7578                 rte_memcpy(&node->key,
7579                                  &key,
7580                                  sizeof(struct ixgbe_l2_tn_key));
7581                 node->pool = l2_tunnel->pool;
7582                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7583                 if (ret < 0) {
7584                         rte_free(node);
7585                         return ret;
7586                 }
7587         }
7588
7589         switch (l2_tunnel->l2_tunnel_type) {
7590         case RTE_L2_TUNNEL_TYPE_E_TAG:
7591                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7592                 break;
7593         default:
7594                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7595                 ret = -EINVAL;
7596                 break;
7597         }
7598
7599         if ((!restore) && (ret < 0))
7600                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7601
7602         return ret;
7603 }
7604
7605 /* Delete l2 tunnel filter */
7606 int
7607 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7608                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7609 {
7610         int ret;
7611         struct ixgbe_l2_tn_info *l2_tn_info =
7612                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7613         struct ixgbe_l2_tn_key key;
7614
7615         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7616         key.tn_id = l2_tunnel->tunnel_id;
7617         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7618         if (ret < 0)
7619                 return ret;
7620
7621         switch (l2_tunnel->l2_tunnel_type) {
7622         case RTE_L2_TUNNEL_TYPE_E_TAG:
7623                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7624                 break;
7625         default:
7626                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7627                 ret = -EINVAL;
7628                 break;
7629         }
7630
7631         return ret;
7632 }
7633
7634 /**
7635  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7636  * @dev: pointer to rte_eth_dev structure
7637  * @filter_op:operation will be taken.
7638  * @arg: a pointer to specific structure corresponding to the filter_op
7639  */
7640 static int
7641 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7642                                   enum rte_filter_op filter_op,
7643                                   void *arg)
7644 {
7645         int ret;
7646
7647         if (filter_op == RTE_ETH_FILTER_NOP)
7648                 return 0;
7649
7650         if (arg == NULL) {
7651                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7652                             filter_op);
7653                 return -EINVAL;
7654         }
7655
7656         switch (filter_op) {
7657         case RTE_ETH_FILTER_ADD:
7658                 ret = ixgbe_dev_l2_tunnel_filter_add
7659                         (dev,
7660                          (struct rte_eth_l2_tunnel_conf *)arg,
7661                          FALSE);
7662                 break;
7663         case RTE_ETH_FILTER_DELETE:
7664                 ret = ixgbe_dev_l2_tunnel_filter_del
7665                         (dev,
7666                          (struct rte_eth_l2_tunnel_conf *)arg);
7667                 break;
7668         default:
7669                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7670                 ret = -EINVAL;
7671                 break;
7672         }
7673         return ret;
7674 }
7675
7676 static int
7677 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7678 {
7679         int ret = 0;
7680         uint32_t ctrl;
7681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7682
7683         if (hw->mac.type != ixgbe_mac_X550 &&
7684             hw->mac.type != ixgbe_mac_X550EM_x &&
7685             hw->mac.type != ixgbe_mac_X550EM_a) {
7686                 return -ENOTSUP;
7687         }
7688
7689         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7690         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7691         if (en)
7692                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7693         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7694
7695         return ret;
7696 }
7697
7698 /* Enable l2 tunnel forwarding */
7699 static int
7700 ixgbe_dev_l2_tunnel_forwarding_enable
7701         (struct rte_eth_dev *dev,
7702          enum rte_eth_tunnel_type l2_tunnel_type)
7703 {
7704         struct ixgbe_l2_tn_info *l2_tn_info =
7705                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7706         int ret = 0;
7707
7708         switch (l2_tunnel_type) {
7709         case RTE_L2_TUNNEL_TYPE_E_TAG:
7710                 l2_tn_info->e_tag_fwd_en = TRUE;
7711                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7712                 break;
7713         default:
7714                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7715                 ret = -EINVAL;
7716                 break;
7717         }
7718
7719         return ret;
7720 }
7721
7722 /* Disable l2 tunnel forwarding */
7723 static int
7724 ixgbe_dev_l2_tunnel_forwarding_disable
7725         (struct rte_eth_dev *dev,
7726          enum rte_eth_tunnel_type l2_tunnel_type)
7727 {
7728         struct ixgbe_l2_tn_info *l2_tn_info =
7729                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7730         int ret = 0;
7731
7732         switch (l2_tunnel_type) {
7733         case RTE_L2_TUNNEL_TYPE_E_TAG:
7734                 l2_tn_info->e_tag_fwd_en = FALSE;
7735                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7736                 break;
7737         default:
7738                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7739                 ret = -EINVAL;
7740                 break;
7741         }
7742
7743         return ret;
7744 }
7745
7746 static int
7747 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7748                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7749                              bool en)
7750 {
7751         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7752         int ret = 0;
7753         uint32_t vmtir, vmvir;
7754         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7755
7756         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7757                 PMD_DRV_LOG(ERR,
7758                             "VF id %u should be less than %u",
7759                             l2_tunnel->vf_id,
7760                             pci_dev->max_vfs);
7761                 return -EINVAL;
7762         }
7763
7764         if (hw->mac.type != ixgbe_mac_X550 &&
7765             hw->mac.type != ixgbe_mac_X550EM_x &&
7766             hw->mac.type != ixgbe_mac_X550EM_a) {
7767                 return -ENOTSUP;
7768         }
7769
7770         if (en)
7771                 vmtir = l2_tunnel->tunnel_id;
7772         else
7773                 vmtir = 0;
7774
7775         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7776
7777         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7778         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7779         if (en)
7780                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7781         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7782
7783         return ret;
7784 }
7785
7786 /* Enable l2 tunnel tag insertion */
7787 static int
7788 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7789                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7790 {
7791         int ret = 0;
7792
7793         switch (l2_tunnel->l2_tunnel_type) {
7794         case RTE_L2_TUNNEL_TYPE_E_TAG:
7795                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7796                 break;
7797         default:
7798                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7799                 ret = -EINVAL;
7800                 break;
7801         }
7802
7803         return ret;
7804 }
7805
7806 /* Disable l2 tunnel tag insertion */
7807 static int
7808 ixgbe_dev_l2_tunnel_insertion_disable
7809         (struct rte_eth_dev *dev,
7810          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7811 {
7812         int ret = 0;
7813
7814         switch (l2_tunnel->l2_tunnel_type) {
7815         case RTE_L2_TUNNEL_TYPE_E_TAG:
7816                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7817                 break;
7818         default:
7819                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7820                 ret = -EINVAL;
7821                 break;
7822         }
7823
7824         return ret;
7825 }
7826
7827 static int
7828 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7829                              bool en)
7830 {
7831         int ret = 0;
7832         uint32_t qde;
7833         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7834
7835         if (hw->mac.type != ixgbe_mac_X550 &&
7836             hw->mac.type != ixgbe_mac_X550EM_x &&
7837             hw->mac.type != ixgbe_mac_X550EM_a) {
7838                 return -ENOTSUP;
7839         }
7840
7841         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7842         if (en)
7843                 qde |= IXGBE_QDE_STRIP_TAG;
7844         else
7845                 qde &= ~IXGBE_QDE_STRIP_TAG;
7846         qde &= ~IXGBE_QDE_READ;
7847         qde |= IXGBE_QDE_WRITE;
7848         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7849
7850         return ret;
7851 }
7852
7853 /* Enable l2 tunnel tag stripping */
7854 static int
7855 ixgbe_dev_l2_tunnel_stripping_enable
7856         (struct rte_eth_dev *dev,
7857          enum rte_eth_tunnel_type l2_tunnel_type)
7858 {
7859         int ret = 0;
7860
7861         switch (l2_tunnel_type) {
7862         case RTE_L2_TUNNEL_TYPE_E_TAG:
7863                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7864                 break;
7865         default:
7866                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7867                 ret = -EINVAL;
7868                 break;
7869         }
7870
7871         return ret;
7872 }
7873
7874 /* Disable l2 tunnel tag stripping */
7875 static int
7876 ixgbe_dev_l2_tunnel_stripping_disable
7877         (struct rte_eth_dev *dev,
7878          enum rte_eth_tunnel_type l2_tunnel_type)
7879 {
7880         int ret = 0;
7881
7882         switch (l2_tunnel_type) {
7883         case RTE_L2_TUNNEL_TYPE_E_TAG:
7884                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7885                 break;
7886         default:
7887                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7888                 ret = -EINVAL;
7889                 break;
7890         }
7891
7892         return ret;
7893 }
7894
7895 /* Enable/disable l2 tunnel offload functions */
7896 static int
7897 ixgbe_dev_l2_tunnel_offload_set
7898         (struct rte_eth_dev *dev,
7899          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7900          uint32_t mask,
7901          uint8_t en)
7902 {
7903         int ret = 0;
7904
7905         if (l2_tunnel == NULL)
7906                 return -EINVAL;
7907
7908         ret = -EINVAL;
7909         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7910                 if (en)
7911                         ret = ixgbe_dev_l2_tunnel_enable(
7912                                 dev,
7913                                 l2_tunnel->l2_tunnel_type);
7914                 else
7915                         ret = ixgbe_dev_l2_tunnel_disable(
7916                                 dev,
7917                                 l2_tunnel->l2_tunnel_type);
7918         }
7919
7920         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7921                 if (en)
7922                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7923                                 dev,
7924                                 l2_tunnel);
7925                 else
7926                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7927                                 dev,
7928                                 l2_tunnel);
7929         }
7930
7931         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7932                 if (en)
7933                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7934                                 dev,
7935                                 l2_tunnel->l2_tunnel_type);
7936                 else
7937                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7938                                 dev,
7939                                 l2_tunnel->l2_tunnel_type);
7940         }
7941
7942         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7943                 if (en)
7944                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7945                                 dev,
7946                                 l2_tunnel->l2_tunnel_type);
7947                 else
7948                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7949                                 dev,
7950                                 l2_tunnel->l2_tunnel_type);
7951         }
7952
7953         return ret;
7954 }
7955
7956 static int
7957 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7958                         uint16_t port)
7959 {
7960         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7961         IXGBE_WRITE_FLUSH(hw);
7962
7963         return 0;
7964 }
7965
7966 /* There's only one register for VxLAN UDP port.
7967  * So, we cannot add several ports. Will update it.
7968  */
7969 static int
7970 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7971                      uint16_t port)
7972 {
7973         if (port == 0) {
7974                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7975                 return -EINVAL;
7976         }
7977
7978         return ixgbe_update_vxlan_port(hw, port);
7979 }
7980
7981 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7982  * UDP port, it must have a value.
7983  * So, will reset it to the original value 0.
7984  */
7985 static int
7986 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7987                      uint16_t port)
7988 {
7989         uint16_t cur_port;
7990
7991         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7992
7993         if (cur_port != port) {
7994                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7995                 return -EINVAL;
7996         }
7997
7998         return ixgbe_update_vxlan_port(hw, 0);
7999 }
8000
8001 /* Add UDP tunneling port */
8002 static int
8003 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8004                               struct rte_eth_udp_tunnel *udp_tunnel)
8005 {
8006         int ret = 0;
8007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8008
8009         if (hw->mac.type != ixgbe_mac_X550 &&
8010             hw->mac.type != ixgbe_mac_X550EM_x &&
8011             hw->mac.type != ixgbe_mac_X550EM_a) {
8012                 return -ENOTSUP;
8013         }
8014
8015         if (udp_tunnel == NULL)
8016                 return -EINVAL;
8017
8018         switch (udp_tunnel->prot_type) {
8019         case RTE_TUNNEL_TYPE_VXLAN:
8020                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8021                 break;
8022
8023         case RTE_TUNNEL_TYPE_GENEVE:
8024         case RTE_TUNNEL_TYPE_TEREDO:
8025                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8026                 ret = -EINVAL;
8027                 break;
8028
8029         default:
8030                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8031                 ret = -EINVAL;
8032                 break;
8033         }
8034
8035         return ret;
8036 }
8037
8038 /* Remove UDP tunneling port */
8039 static int
8040 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8041                               struct rte_eth_udp_tunnel *udp_tunnel)
8042 {
8043         int ret = 0;
8044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8045
8046         if (hw->mac.type != ixgbe_mac_X550 &&
8047             hw->mac.type != ixgbe_mac_X550EM_x &&
8048             hw->mac.type != ixgbe_mac_X550EM_a) {
8049                 return -ENOTSUP;
8050         }
8051
8052         if (udp_tunnel == NULL)
8053                 return -EINVAL;
8054
8055         switch (udp_tunnel->prot_type) {
8056         case RTE_TUNNEL_TYPE_VXLAN:
8057                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8058                 break;
8059         case RTE_TUNNEL_TYPE_GENEVE:
8060         case RTE_TUNNEL_TYPE_TEREDO:
8061                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8062                 ret = -EINVAL;
8063                 break;
8064         default:
8065                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8066                 ret = -EINVAL;
8067                 break;
8068         }
8069
8070         return ret;
8071 }
8072
8073 static void
8074 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8075 {
8076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8077
8078         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8079 }
8080
8081 static void
8082 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8083 {
8084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8085
8086         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8087 }
8088
8089 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8090 {
8091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8092         u32 in_msg = 0;
8093
8094         /* peek the message first */
8095         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8096
8097         /* PF reset VF event */
8098         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8099                 /* dummy mbx read to ack pf */
8100                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8101                         return;
8102                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8103                                               NULL);
8104         }
8105 }
8106
8107 static int
8108 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8109 {
8110         uint32_t eicr;
8111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8112         struct ixgbe_interrupt *intr =
8113                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8114         ixgbevf_intr_disable(hw);
8115
8116         /* read-on-clear nic registers here */
8117         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8118         intr->flags = 0;
8119
8120         /* only one misc vector supported - mailbox */
8121         eicr &= IXGBE_VTEICR_MASK;
8122         if (eicr == IXGBE_MISC_VEC_ID)
8123                 intr->flags |= IXGBE_FLAG_MAILBOX;
8124
8125         return 0;
8126 }
8127
8128 static int
8129 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8130 {
8131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8132         struct ixgbe_interrupt *intr =
8133                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8134
8135         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8136                 ixgbevf_mbx_process(dev);
8137                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8138         }
8139
8140         ixgbevf_intr_enable(hw);
8141
8142         return 0;
8143 }
8144
8145 static void
8146 ixgbevf_dev_interrupt_handler(void *param)
8147 {
8148         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8149
8150         ixgbevf_dev_interrupt_get_status(dev);
8151         ixgbevf_dev_interrupt_action(dev);
8152 }
8153
8154 /**
8155  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8156  *  @hw: pointer to hardware structure
8157  *
8158  *  Stops the transmit data path and waits for the HW to internally empty
8159  *  the Tx security block
8160  **/
8161 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8162 {
8163 #define IXGBE_MAX_SECTX_POLL 40
8164
8165         int i;
8166         int sectxreg;
8167
8168         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8169         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8170         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8171         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8172                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8173                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8174                         break;
8175                 /* Use interrupt-safe sleep just in case */
8176                 usec_delay(1000);
8177         }
8178
8179         /* For informational purposes only */
8180         if (i >= IXGBE_MAX_SECTX_POLL)
8181                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8182                          "path fully disabled.  Continuing with init.");
8183
8184         return IXGBE_SUCCESS;
8185 }
8186
8187 /**
8188  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8189  *  @hw: pointer to hardware structure
8190  *
8191  *  Enables the transmit data path.
8192  **/
8193 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8194 {
8195         uint32_t sectxreg;
8196
8197         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8198         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8199         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8200         IXGBE_WRITE_FLUSH(hw);
8201
8202         return IXGBE_SUCCESS;
8203 }
8204
8205 /* restore n-tuple filter */
8206 static inline void
8207 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8208 {
8209         struct ixgbe_filter_info *filter_info =
8210                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8211         struct ixgbe_5tuple_filter *node;
8212
8213         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8214                 ixgbe_inject_5tuple_filter(dev, node);
8215         }
8216 }
8217
8218 /* restore ethernet type filter */
8219 static inline void
8220 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8221 {
8222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8223         struct ixgbe_filter_info *filter_info =
8224                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8225         int i;
8226
8227         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8228                 if (filter_info->ethertype_mask & (1 << i)) {
8229                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8230                                         filter_info->ethertype_filters[i].etqf);
8231                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8232                                         filter_info->ethertype_filters[i].etqs);
8233                         IXGBE_WRITE_FLUSH(hw);
8234                 }
8235         }
8236 }
8237
8238 /* restore SYN filter */
8239 static inline void
8240 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8241 {
8242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8243         struct ixgbe_filter_info *filter_info =
8244                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8245         uint32_t synqf;
8246
8247         synqf = filter_info->syn_info;
8248
8249         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8250                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8251                 IXGBE_WRITE_FLUSH(hw);
8252         }
8253 }
8254
8255 /* restore L2 tunnel filter */
8256 static inline void
8257 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8258 {
8259         struct ixgbe_l2_tn_info *l2_tn_info =
8260                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8261         struct ixgbe_l2_tn_filter *node;
8262         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8263
8264         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8265                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8266                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8267                 l2_tn_conf.pool           = node->pool;
8268                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8269         }
8270 }
8271
8272 /* restore rss filter */
8273 static inline void
8274 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8275 {
8276         struct ixgbe_filter_info *filter_info =
8277                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8278
8279         if (filter_info->rss_info.num)
8280                 ixgbe_config_rss_filter(dev,
8281                         &filter_info->rss_info, TRUE);
8282 }
8283
8284 static int
8285 ixgbe_filter_restore(struct rte_eth_dev *dev)
8286 {
8287         ixgbe_ntuple_filter_restore(dev);
8288         ixgbe_ethertype_filter_restore(dev);
8289         ixgbe_syn_filter_restore(dev);
8290         ixgbe_fdir_filter_restore(dev);
8291         ixgbe_l2_tn_filter_restore(dev);
8292         ixgbe_rss_filter_restore(dev);
8293
8294         return 0;
8295 }
8296
8297 static void
8298 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8299 {
8300         struct ixgbe_l2_tn_info *l2_tn_info =
8301                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8302         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8303
8304         if (l2_tn_info->e_tag_en)
8305                 (void)ixgbe_e_tag_enable(hw);
8306
8307         if (l2_tn_info->e_tag_fwd_en)
8308                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8309
8310         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8311 }
8312
8313 /* remove all the n-tuple filters */
8314 void
8315 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8316 {
8317         struct ixgbe_filter_info *filter_info =
8318                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8319         struct ixgbe_5tuple_filter *p_5tuple;
8320
8321         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8322                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8323 }
8324
8325 /* remove all the ether type filters */
8326 void
8327 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8328 {
8329         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8330         struct ixgbe_filter_info *filter_info =
8331                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8332         int i;
8333
8334         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8335                 if (filter_info->ethertype_mask & (1 << i) &&
8336                     !filter_info->ethertype_filters[i].conf) {
8337                         (void)ixgbe_ethertype_filter_remove(filter_info,
8338                                                             (uint8_t)i);
8339                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8340                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8341                         IXGBE_WRITE_FLUSH(hw);
8342                 }
8343         }
8344 }
8345
8346 /* remove the SYN filter */
8347 void
8348 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8349 {
8350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8351         struct ixgbe_filter_info *filter_info =
8352                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8353
8354         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8355                 filter_info->syn_info = 0;
8356
8357                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8358                 IXGBE_WRITE_FLUSH(hw);
8359         }
8360 }
8361
8362 /* remove all the L2 tunnel filters */
8363 int
8364 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8365 {
8366         struct ixgbe_l2_tn_info *l2_tn_info =
8367                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8368         struct ixgbe_l2_tn_filter *l2_tn_filter;
8369         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8370         int ret = 0;
8371
8372         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8373                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8374                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8375                 l2_tn_conf.pool           = l2_tn_filter->pool;
8376                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8377                 if (ret < 0)
8378                         return ret;
8379         }
8380
8381         return 0;
8382 }
8383
8384 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8385 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8386 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8387 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8388 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8389 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8390
8391 RTE_INIT(ixgbe_init_log);
8392 static void
8393 ixgbe_init_log(void)
8394 {
8395         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8396         if (ixgbe_logtype_init >= 0)
8397                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8398         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8399         if (ixgbe_logtype_driver >= 0)
8400                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8401 }