drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 #include "rte_pmd_ixgbe.h"
  77
  78 /*
  79  * High threshold controlling when to start sending XOFF frames. Must be at
  80  * least 8 bytes less than receive packet buffer size. This value is in units
  81  * of 1024 bytes.
  82  */
  83 #define IXGBE_FC_HI    0x80
  84
  85 /*
  86  * Low threshold controlling when to start sending XON frames. This value is
  87  * in units of 1024 bytes.
  88  */
  89 #define IXGBE_FC_LO    0x40
  90
  91 /* Default minimum inter-interrupt interval for EITR configuration */
  92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  93
  94 /* Timer value included in XOFF frames. */
  95 #define IXGBE_FC_PAUSE 0x680
  96
  97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  98 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  99 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 100
 101 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 102 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 103 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 104
 105 /*
 106  *  Default values for RX/TX configuration
 107  */
 108 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 109 #define IXGBE_DEFAULT_RX_PTHRESH      8
 110 #define IXGBE_DEFAULT_RX_HTHRESH      8
 111 #define IXGBE_DEFAULT_RX_WTHRESH      0
 112
 113 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 114 #define IXGBE_DEFAULT_TX_PTHRESH      32
 115 #define IXGBE_DEFAULT_TX_HTHRESH      0
 116 #define IXGBE_DEFAULT_TX_WTHRESH      0
 117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 118
 119 /* Bit shift and mask */
 120 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 121 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 122 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 123 #define IXGBE_8_BIT_MASK   UINT8_MAX
 124
 125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 126
 127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 128
 129 #define IXGBE_HKEY_MAX_INDEX 10
 130
 131 /* Additional timesync values. */
 132 #define NSEC_PER_SEC             1000000000L
 133 #define IXGBE_INCVAL_10GB        0x66666666
 134 #define IXGBE_INCVAL_1GB         0x40000000
 135 #define IXGBE_INCVAL_100         0x50000000
 136 #define IXGBE_INCVAL_SHIFT_10GB  28
 137 #define IXGBE_INCVAL_SHIFT_1GB   24
 138 #define IXGBE_INCVAL_SHIFT_100   21
 139 #define IXGBE_INCVAL_SHIFT_82599 7
 140 #define IXGBE_INCPER_SHIFT_82599 24
 141
 142 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 143
 144 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 146 #define DEFAULT_ETAG_ETYPE                     0x893f
 147 #define IXGBE_ETAG_ETYPE                       0x00005084
 148 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 149 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 150 #define IXGBE_RAH_ADTYPE                       0x40000000
 151 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 152 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 155 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 156 #define IXGBE_VTEICR_MASK                      0x07
 157
 158 enum ixgbevf_xcast_modes {
 159         IXGBEVF_XCAST_MODE_NONE = 0,
 160         IXGBEVF_XCAST_MODE_MULTI,
 161         IXGBEVF_XCAST_MODE_ALLMULTI,
 162 };
 163
 164 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 165 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 166
 167 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 168 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 169 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 170 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 171 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 172 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 173 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 174 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 175 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 177 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 178 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 179 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 180 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 182 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 183 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 184 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 185                                 int wait_to_complete);
 186 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 187                                 struct rte_eth_stats *stats);
 188 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_xstat *xstats, unsigned n);
 190 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 191                                   struct rte_eth_xstat *xstats, unsigned n);
 192 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 193 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 195         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 196 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 198 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 199                                              uint16_t queue_id,
 200                                              uint8_t stat_idx,
 201                                              uint8_t is_rx);
 202 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 203                                  size_t fw_size);
 204 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_dev_info *dev_info);
 206 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 207 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 208                                  struct rte_eth_dev_info *dev_info);
 209 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 210
 211 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 212                 uint16_t vlan_id, int on);
 213 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 214                                enum rte_vlan_type vlan_type,
 215                                uint16_t tpid_id);
 216 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 217                 uint16_t queue, bool on);
 218 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 219                 int on);
 220 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 221 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 222 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 223 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 224 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 225
 226 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 228 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 229                                struct rte_eth_fc_conf *fc_conf);
 230 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 233                 struct rte_eth_pfc_conf *pfc_conf);
 234 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 235                         struct rte_eth_rss_reta_entry64 *reta_conf,
 236                         uint16_t reta_size);
 237 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 238                         struct rte_eth_rss_reta_entry64 *reta_conf,
 239                         uint16_t reta_size);
 240 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 241 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 242 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 246                                       struct rte_intr_handle *handle);
 247 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 248                 void *param);
 249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 250 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 251                 uint32_t index, uint32_t pool);
 252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 254                                            struct ether_addr *mac_addr);
 255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 256 static int is_ixgbe_pmd(const char *driver_name);
 257
 258 /* For Virtual Function support */
 259 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 260 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 261 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 262 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 265 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 266 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 267 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 268                 struct rte_eth_stats *stats);
 269 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 270 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 271                 uint16_t vlan_id, int on);
 272 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 273                 uint16_t queue, int on);
 274 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 275 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 276 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                             uint16_t queue_id);
 278 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                              uint16_t queue_id);
 280 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                  uint8_t queue, uint8_t msix_vector);
 282 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 283 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 284 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 285
 286 /* For Eth VMDQ APIs support */
 287 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 288                 ether_addr * mac_addr, uint8_t on);
 289 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 291                 struct rte_eth_mirror_conf *mirror_conf,
 292                 uint8_t rule_id, uint8_t on);
 293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 294                 uint8_t rule_id);
 295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 296                                           uint16_t queue_id);
 297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 298                                            uint16_t queue_id);
 299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 300                                uint8_t queue, uint8_t msix_vector);
 301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 302
 303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 304                 uint16_t queue_idx, uint16_t tx_rate);
 305
 306 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 307                                  struct ether_addr *mac_addr,
 308                                  uint32_t index, uint32_t pool);
 309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 311                                              struct ether_addr *mac_addr);
 312 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 313                         struct rte_eth_syn_filter *filter,
 314                         bool add);
 315 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 316                         struct rte_eth_syn_filter *filter);
 317 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 318                         enum rte_filter_op filter_op,
 319                         void *arg);
 320 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 323                         struct ixgbe_5tuple_filter *filter);
 324 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ntuple_filter *filter,
 326                         bool add);
 327 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 328                                 enum rte_filter_op filter_op,
 329                                 void *arg);
 330 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 331                         struct rte_eth_ntuple_filter *filter);
 332 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 333                         struct rte_eth_ethertype_filter *filter,
 334                         bool add);
 335 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 336                                 enum rte_filter_op filter_op,
 337                                 void *arg);
 338 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 339                         struct rte_eth_ethertype_filter *filter);
 340 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 341                      enum rte_filter_type filter_type,
 342                      enum rte_filter_op filter_op,
 343                      void *arg);
 344 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 345
 346 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 347                                       struct ether_addr *mc_addr_set,
 348                                       uint32_t nb_mc_addr);
 349 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 350                                    struct rte_eth_dcb_info *dcb_info);
 351
 352 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 353 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 354                             struct rte_dev_reg_info *regs);
 355 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 356 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 357                                 struct rte_dev_eeprom_info *eeprom);
 358 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 359                                 struct rte_dev_eeprom_info *eeprom);
 360
 361 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 362 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 363                                 struct rte_dev_reg_info *regs);
 364
 365 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 366 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 367 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 368                                             struct timespec *timestamp,
 369                                             uint32_t flags);
 370 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 371                                             struct timespec *timestamp);
 372 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 373 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 374                                    struct timespec *timestamp);
 375 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 376                                    const struct timespec *timestamp);
 377 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 378                                           void *param);
 379
 380 static int ixgbe_dev_l2_tunnel_eth_type_conf
 381         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 382 static int ixgbe_dev_l2_tunnel_offload_set
 383         (struct rte_eth_dev *dev,
 384          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 385          uint32_t mask,
 386          uint8_t en);
 387 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 388                                              enum rte_filter_op filter_op,
 389                                              void *arg);
 390
 391 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 392                                          struct rte_eth_udp_tunnel *udp_tunnel);
 393 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 394                                          struct rte_eth_udp_tunnel *udp_tunnel);
 395 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 396
 397 /*
 398  * Define VF Stats MACRO for Non "cleared on read" register
 399  */
 400 #define UPDATE_VF_STAT(reg, last, cur)                          \
 401 {                                                               \
 402         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 403         cur += (latest - last) & UINT_MAX;                      \
 404         last = latest;                                          \
 405 }
 406
 407 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 408 {                                                                \
 409         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 410         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 411         u64 latest = ((new_msb << 32) | new_lsb);                \
 412         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 413         last = latest;                                           \
 414 }
 415
 416 #define IXGBE_SET_HWSTRIP(h, q) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (h)->bitmap[idx] |= 1 << bit;\
 420         } while (0)
 421
 422 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 423                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 424                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 425                 (h)->bitmap[idx] &= ~(1 << bit);\
 426         } while (0)
 427
 428 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 429                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 430                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 431                 (r) = (h)->bitmap[idx] >> bit & 1;\
 432         } while (0)
 433
 434 /*
 435  * The set of PCI devices this driver supports
 436  */
 437 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 491 #ifdef RTE_NIC_BYPASS
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 493 #endif
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 /*
 498  * The set of PCI devices this driver supports (for 82599 VF)
 499  */
 500 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 508         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 509         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 510         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 511         { .vendor_id = 0, /* sentinel */ },
 512 };
 513
 514 static const struct rte_eth_desc_lim rx_desc_lim = {
 515         .nb_max = IXGBE_MAX_RING_DESC,
 516         .nb_min = IXGBE_MIN_RING_DESC,
 517         .nb_align = IXGBE_RXD_ALIGN,
 518 };
 519
 520 static const struct rte_eth_desc_lim tx_desc_lim = {
 521         .nb_max = IXGBE_MAX_RING_DESC,
 522         .nb_min = IXGBE_MIN_RING_DESC,
 523         .nb_align = IXGBE_TXD_ALIGN,
 524         .nb_seg_max = IXGBE_TX_MAX_SEG,
 525         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 526 };
 527
 528 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 529         .dev_configure        = ixgbe_dev_configure,
 530         .dev_start            = ixgbe_dev_start,
 531         .dev_stop             = ixgbe_dev_stop,
 532         .dev_set_link_up    = ixgbe_dev_set_link_up,
 533         .dev_set_link_down  = ixgbe_dev_set_link_down,
 534         .dev_close            = ixgbe_dev_close,
 535         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 536         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 537         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 538         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 539         .link_update          = ixgbe_dev_link_update,
 540         .stats_get            = ixgbe_dev_stats_get,
 541         .xstats_get           = ixgbe_dev_xstats_get,
 542         .stats_reset          = ixgbe_dev_stats_reset,
 543         .xstats_reset         = ixgbe_dev_xstats_reset,
 544         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 545         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 546         .fw_version_get       = ixgbe_fw_version_get,
 547         .dev_infos_get        = ixgbe_dev_info_get,
 548         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 549         .mtu_set              = ixgbe_dev_mtu_set,
 550         .vlan_filter_set      = ixgbe_vlan_filter_set,
 551         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 552         .vlan_offload_set     = ixgbe_vlan_offload_set,
 553         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 554         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 555         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 556         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 557         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 558         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 559         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 560         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 561         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 562         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 563         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 564         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 565         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 566         .dev_led_on           = ixgbe_dev_led_on,
 567         .dev_led_off          = ixgbe_dev_led_off,
 568         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 569         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 570         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 571         .mac_addr_add         = ixgbe_add_rar,
 572         .mac_addr_remove      = ixgbe_remove_rar,
 573         .mac_addr_set         = ixgbe_set_default_mac_addr,
 574         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 575         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 576         .mirror_rule_set      = ixgbe_mirror_rule_set,
 577         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 578         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 579         .reta_update          = ixgbe_dev_rss_reta_update,
 580         .reta_query           = ixgbe_dev_rss_reta_query,
 581 #ifdef RTE_NIC_BYPASS
 582         .bypass_init          = ixgbe_bypass_init,
 583         .bypass_state_set     = ixgbe_bypass_state_store,
 584         .bypass_state_show    = ixgbe_bypass_state_show,
 585         .bypass_event_set     = ixgbe_bypass_event_store,
 586         .bypass_event_show    = ixgbe_bypass_event_show,
 587         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 588         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 589         .bypass_ver_show      = ixgbe_bypass_ver_show,
 590         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 591 #endif /* RTE_NIC_BYPASS */
 592         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 593         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 594         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 595         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 596         .rxq_info_get         = ixgbe_rxq_info_get,
 597         .txq_info_get         = ixgbe_txq_info_get,
 598         .timesync_enable      = ixgbe_timesync_enable,
 599         .timesync_disable     = ixgbe_timesync_disable,
 600         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 601         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 602         .get_reg              = ixgbe_get_regs,
 603         .get_eeprom_length    = ixgbe_get_eeprom_length,
 604         .get_eeprom           = ixgbe_get_eeprom,
 605         .set_eeprom           = ixgbe_set_eeprom,
 606         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 607         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 608         .timesync_read_time   = ixgbe_timesync_read_time,
 609         .timesync_write_time  = ixgbe_timesync_write_time,
 610         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 611         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 612         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 613         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 614 };
 615
 616 /*
 617  * dev_ops for virtual function, bare necessities for basic vf
 618  * operation have been implemented
 619  */
 620 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 621         .dev_configure        = ixgbevf_dev_configure,
 622         .dev_start            = ixgbevf_dev_start,
 623         .dev_stop             = ixgbevf_dev_stop,
 624         .link_update          = ixgbe_dev_link_update,
 625         .stats_get            = ixgbevf_dev_stats_get,
 626         .xstats_get           = ixgbevf_dev_xstats_get,
 627         .stats_reset          = ixgbevf_dev_stats_reset,
 628         .xstats_reset         = ixgbevf_dev_stats_reset,
 629         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 630         .dev_close            = ixgbevf_dev_close,
 631         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 632         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 633         .dev_infos_get        = ixgbevf_dev_info_get,
 634         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 635         .mtu_set              = ixgbevf_dev_set_mtu,
 636         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 637         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 638         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 639         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 640         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 641         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 642         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 643         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 644         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 645         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 646         .mac_addr_add         = ixgbevf_add_mac_addr,
 647         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 648         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 649         .rxq_info_get         = ixgbe_rxq_info_get,
 650         .txq_info_get         = ixgbe_txq_info_get,
 651         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 652         .get_reg              = ixgbevf_get_regs,
 653         .reta_update          = ixgbe_dev_rss_reta_update,
 654         .reta_query           = ixgbe_dev_rss_reta_query,
 655         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 656         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 657 };
 658
 659 /* store statistics names and its offset in stats structure */
 660 struct rte_ixgbe_xstats_name_off {
 661         char name[RTE_ETH_XSTATS_NAME_SIZE];
 662         unsigned offset;
 663 };
 664
 665 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 666         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 667         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 668         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 669         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 670         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 671         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 672         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 673         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 674         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 675         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 676         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 677         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 678         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 679         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 680         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 681                 prc1023)},
 682         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 683                 prc1522)},
 684         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 685         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 686         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 687         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 688         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 689         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 690         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 691         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 692         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 693         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 694         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 695         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 696         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 697         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 698         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 699         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 700         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 701                 ptc1023)},
 702         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 703                 ptc1522)},
 704         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 705         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 706         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 707         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 708
 709         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 710                 fdirustat_add)},
 711         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 712                 fdirustat_remove)},
 713         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 714                 fdirfstat_fadd)},
 715         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 716                 fdirfstat_fremove)},
 717         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 718                 fdirmatch)},
 719         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 720                 fdirmiss)},
 721
 722         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 723         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 724         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 725                 fclast)},
 726         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 727         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 728         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 729         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 730         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 731                 fcoe_noddp)},
 732         {"rx_fcoe_no_direct_data_placement_ext_buff",
 733                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 734
 735         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 736                 lxontxc)},
 737         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 738                 lxonrxc)},
 739         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 740                 lxofftxc)},
 741         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 742                 lxoffrxc)},
 743         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 744 };
 745
 746 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 747                            sizeof(rte_ixgbe_stats_strings[0]))
 748
 749 /* MACsec statistics */
 750 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 751         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 752                 out_pkts_untagged)},
 753         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 754                 out_pkts_encrypted)},
 755         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 756                 out_pkts_protected)},
 757         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 758                 out_octets_encrypted)},
 759         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 760                 out_octets_protected)},
 761         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_untagged)},
 763         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_badtag)},
 765         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_nosci)},
 767         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_unknownsci)},
 769         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 770                 in_octets_decrypted)},
 771         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 772                 in_octets_validated)},
 773         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_unchecked)},
 775         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_delayed)},
 777         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_late)},
 779         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_ok)},
 781         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 782                 in_pkts_invalid)},
 783         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 784                 in_pkts_notvalid)},
 785         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 786                 in_pkts_unusedsa)},
 787         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 788                 in_pkts_notusingsa)},
 789 };
 790
 791 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 792                            sizeof(rte_ixgbe_macsec_strings[0]))
 793
 794 /* Per-queue statistics */
 795 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 796         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 797         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 798         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 799         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 800 };
 801
 802 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 803                            sizeof(rte_ixgbe_rxq_strings[0]))
 804 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 805
 806 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 807         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 808         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 809         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 810                 pxon2offc)},
 811 };
 812
 813 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 814                            sizeof(rte_ixgbe_txq_strings[0]))
 815 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 816
 817 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 818         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 819 };
 820
 821 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 822                 sizeof(rte_ixgbevf_stats_strings[0]))
 823
 824 /**
 825  * Atomically reads the link status information from global
 826  * structure rte_eth_dev.
 827  *
 828  * @param dev
 829  *   - Pointer to the structure rte_eth_dev to read from.
 830  *   - Pointer to the buffer to be saved with the link status.
 831  *
 832  * @return
 833  *   - On success, zero.
 834  *   - On failure, negative value.
 835  */
 836 static inline int
 837 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 838                                 struct rte_eth_link *link)
 839 {
 840         struct rte_eth_link *dst = link;
 841         struct rte_eth_link *src = &(dev->data->dev_link);
 842
 843         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 844                                         *(uint64_t *)src) == 0)
 845                 return -1;
 846
 847         return 0;
 848 }
 849
 850 /**
 851  * Atomically writes the link status information into global
 852  * structure rte_eth_dev.
 853  *
 854  * @param dev
 855  *   - Pointer to the structure rte_eth_dev to read from.
 856  *   - Pointer to the buffer to be saved with the link status.
 857  *
 858  * @return
 859  *   - On success, zero.
 860  *   - On failure, negative value.
 861  */
 862 static inline int
 863 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 864                                 struct rte_eth_link *link)
 865 {
 866         struct rte_eth_link *dst = &(dev->data->dev_link);
 867         struct rte_eth_link *src = link;
 868
 869         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 870                                         *(uint64_t *)src) == 0)
 871                 return -1;
 872
 873         return 0;
 874 }
 875
 876 /*
 877  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 878  */
 879 static inline int
 880 ixgbe_is_sfp(struct ixgbe_hw *hw)
 881 {
 882         switch (hw->phy.type) {
 883         case ixgbe_phy_sfp_avago:
 884         case ixgbe_phy_sfp_ftl:
 885         case ixgbe_phy_sfp_intel:
 886         case ixgbe_phy_sfp_unknown:
 887         case ixgbe_phy_sfp_passive_tyco:
 888         case ixgbe_phy_sfp_passive_unknown:
 889                 return 1;
 890         default:
 891                 return 0;
 892         }
 893 }
 894
 895 static inline int32_t
 896 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 897 {
 898         uint32_t ctrl_ext;
 899         int32_t status;
 900
 901         status = ixgbe_reset_hw(hw);
 902
 903         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 904         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 905         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 906         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 907         IXGBE_WRITE_FLUSH(hw);
 908
 909         return status;
 910 }
 911
 912 static inline void
 913 ixgbe_enable_intr(struct rte_eth_dev *dev)
 914 {
 915         struct ixgbe_interrupt *intr =
 916                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 917         struct ixgbe_hw *hw =
 918                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 919
 920         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 921         IXGBE_WRITE_FLUSH(hw);
 922 }
 923
 924 /*
 925  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 926  */
 927 static void
 928 ixgbe_disable_intr(struct ixgbe_hw *hw)
 929 {
 930         PMD_INIT_FUNC_TRACE();
 931
 932         if (hw->mac.type == ixgbe_mac_82598EB) {
 933                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 934         } else {
 935                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 936                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 937                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 938         }
 939         IXGBE_WRITE_FLUSH(hw);
 940 }
 941
 942 /*
 943  * This function resets queue statistics mapping registers.
 944  * From Niantic datasheet, Initialization of Statistics section:
 945  * "...if software requires the queue counters, the RQSMR and TQSM registers
 946  * must be re-programmed following a device reset.
 947  */
 948 static void
 949 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 950 {
 951         uint32_t i;
 952
 953         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 954                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 955                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 956         }
 957 }
 958
 959
 960 static int
 961 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 962                                   uint16_t queue_id,
 963                                   uint8_t stat_idx,
 964                                   uint8_t is_rx)
 965 {
 966 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 967 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 968 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 969
 970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 971         struct ixgbe_stat_mapping_registers *stat_mappings =
 972                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 973         uint32_t qsmr_mask = 0;
 974         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 975         uint32_t q_map;
 976         uint8_t n, offset;
 977
 978         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 979                 (hw->mac.type != ixgbe_mac_X540) &&
 980                 (hw->mac.type != ixgbe_mac_X550) &&
 981                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 982                 (hw->mac.type != ixgbe_mac_X550EM_a))
 983                 return -ENOSYS;
 984
 985         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 986                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 987                      queue_id, stat_idx);
 988
 989         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 990         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 991                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 992                 return -EIO;
 993         }
 994         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 995
 996         /* Now clear any previous stat_idx set */
 997         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 998         if (!is_rx)
 999                 stat_mappings->tqsm[n] &= ~clearing_mask;
1000         else
1001                 stat_mappings->rqsmr[n] &= ~clearing_mask;
1002
1003         q_map = (uint32_t)stat_idx;
1004         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1005         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1006         if (!is_rx)
1007                 stat_mappings->tqsm[n] |= qsmr_mask;
1008         else
1009                 stat_mappings->rqsmr[n] |= qsmr_mask;
1010
1011         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1012                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1013                      queue_id, stat_idx);
1014         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1015                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1016
1017         /* Now write the mapping in the appropriate register */
1018         if (is_rx) {
1019                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1020                              stat_mappings->rqsmr[n], n);
1021                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1022         } else {
1023                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1024                              stat_mappings->tqsm[n], n);
1025                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1026         }
1027         return 0;
1028 }
1029
1030 static void
1031 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1032 {
1033         struct ixgbe_stat_mapping_registers *stat_mappings =
1034                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036         int i;
1037
1038         /* write whatever was in stat mapping table to the NIC */
1039         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1040                 /* rx */
1041                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1042
1043                 /* tx */
1044                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1045         }
1046 }
1047
1048 static void
1049 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1050 {
1051         uint8_t i;
1052         struct ixgbe_dcb_tc_config *tc;
1053         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1054
1055         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1056         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1057         for (i = 0; i < dcb_max_tc; i++) {
1058                 tc = &dcb_config->tc_config[i];
1059                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1060                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1061                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1062                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1063                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1064                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1065                 tc->pfc = ixgbe_dcb_pfc_disabled;
1066         }
1067
1068         /* Initialize default user to priority mapping, UPx->TC0 */
1069         tc = &dcb_config->tc_config[0];
1070         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1071         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1072         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1073                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1074                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1075         }
1076         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1077         dcb_config->pfc_mode_enable = false;
1078         dcb_config->vt_mode = true;
1079         dcb_config->round_robin_enable = false;
1080         /* support all DCB capabilities in 82599 */
1081         dcb_config->support.capabilities = 0xFF;
1082
1083         /*we only support 4 Tcs for X540, X550 */
1084         if (hw->mac.type == ixgbe_mac_X540 ||
1085                 hw->mac.type == ixgbe_mac_X550 ||
1086                 hw->mac.type == ixgbe_mac_X550EM_x ||
1087                 hw->mac.type == ixgbe_mac_X550EM_a) {
1088                 dcb_config->num_tcs.pg_tcs = 4;
1089                 dcb_config->num_tcs.pfc_tcs = 4;
1090         }
1091 }
1092
1093 /*
1094  * Ensure that all locks are released before first NVM or PHY access
1095  */
1096 static void
1097 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1098 {
1099         uint16_t mask;
1100
1101         /*
1102          * Phy lock should not fail in this early stage. If this is the case,
1103          * it is due to an improper exit of the application.
1104          * So force the release of the faulty lock. Release of common lock
1105          * is done automatically by swfw_sync function.
1106          */
1107         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1108         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1109                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1110         }
1111         ixgbe_release_swfw_semaphore(hw, mask);
1112
1113         /*
1114          * These ones are more tricky since they are common to all ports; but
1115          * swfw_sync retries last long enough (1s) to be almost sure that if
1116          * lock can not be taken it is due to an improper lock of the
1117          * semaphore.
1118          */
1119         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1120         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1121                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1122         }
1123         ixgbe_release_swfw_semaphore(hw, mask);
1124 }
1125
1126 /*
1127  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1128  * It returns 0 on success.
1129  */
1130 static int
1131 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1132 {
1133         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1134         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1135         struct ixgbe_hw *hw =
1136                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1137         struct ixgbe_vfta *shadow_vfta =
1138                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1139         struct ixgbe_hwstrip *hwstrip =
1140                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1141         struct ixgbe_dcb_config *dcb_config =
1142                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1143         struct ixgbe_filter_info *filter_info =
1144                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1145         uint32_t ctrl_ext;
1146         uint16_t csum;
1147         int diag, i;
1148
1149         PMD_INIT_FUNC_TRACE();
1150
1151         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1152         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1153         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1154         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1155
1156         /*
1157          * For secondary processes, we don't initialise any further as primary
1158          * has already done this work. Only check we don't need a different
1159          * RX and TX function.
1160          */
1161         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1162                 struct ixgbe_tx_queue *txq;
1163                 /* TX queue function in primary, set by last queue initialized
1164                  * Tx queue may not initialized by primary process
1165                  */
1166                 if (eth_dev->data->tx_queues) {
1167                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1168                         ixgbe_set_tx_function(eth_dev, txq);
1169                 } else {
1170                         /* Use default TX function if we get here */
1171                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1172                                      "Using default TX function.");
1173                 }
1174
1175                 ixgbe_set_rx_function(eth_dev);
1176
1177                 return 0;
1178         }
1179
1180         rte_eth_copy_pci_info(eth_dev, pci_dev);
1181         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1182
1183         /* Vendor and Device ID need to be set before init of shared code */
1184         hw->device_id = pci_dev->id.device_id;
1185         hw->vendor_id = pci_dev->id.vendor_id;
1186         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1187         hw->allow_unsupported_sfp = 1;
1188
1189         /* Initialize the shared code (base driver) */
1190 #ifdef RTE_NIC_BYPASS
1191         diag = ixgbe_bypass_init_shared_code(hw);
1192 #else
1193         diag = ixgbe_init_shared_code(hw);
1194 #endif /* RTE_NIC_BYPASS */
1195
1196         if (diag != IXGBE_SUCCESS) {
1197                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1198                 return -EIO;
1199         }
1200
1201         /* pick up the PCI bus settings for reporting later */
1202         ixgbe_get_bus_info(hw);
1203
1204         /* Unlock any pending hardware semaphore */
1205         ixgbe_swfw_lock_reset(hw);
1206
1207         /* Initialize DCB configuration*/
1208         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1209         ixgbe_dcb_init(hw, dcb_config);
1210         /* Get Hardware Flow Control setting */
1211         hw->fc.requested_mode = ixgbe_fc_full;
1212         hw->fc.current_mode = ixgbe_fc_full;
1213         hw->fc.pause_time = IXGBE_FC_PAUSE;
1214         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1215                 hw->fc.low_water[i] = IXGBE_FC_LO;
1216                 hw->fc.high_water[i] = IXGBE_FC_HI;
1217         }
1218         hw->fc.send_xon = 1;
1219
1220         /* Make sure we have a good EEPROM before we read from it */
1221         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1222         if (diag != IXGBE_SUCCESS) {
1223                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1224                 return -EIO;
1225         }
1226
1227 #ifdef RTE_NIC_BYPASS
1228         diag = ixgbe_bypass_init_hw(hw);
1229 #else
1230         diag = ixgbe_init_hw(hw);
1231 #endif /* RTE_NIC_BYPASS */
1232
1233         /*
1234          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1235          * is called too soon after the kernel driver unbinding/binding occurs.
1236          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1237          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1238          * also called. See ixgbe_identify_phy_82599(). The reason for the
1239          * failure is not known, and only occuts when virtualisation features
1240          * are disabled in the bios. A delay of 100ms  was found to be enough by
1241          * trial-and-error, and is doubled to be safe.
1242          */
1243         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1244                 rte_delay_ms(200);
1245                 diag = ixgbe_init_hw(hw);
1246         }
1247
1248         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1249                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1250                              "LOM.  Please be aware there may be issues associated "
1251                              "with your hardware.");
1252                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1253                              "please contact your Intel or hardware representative "
1254                              "who provided you with this hardware.");
1255         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1256                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1257         if (diag) {
1258                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1259                 return -EIO;
1260         }
1261
1262         /* Reset the hw statistics */
1263         ixgbe_dev_stats_reset(eth_dev);
1264
1265         /* disable interrupt */
1266         ixgbe_disable_intr(hw);
1267
1268         /* reset mappings for queue statistics hw counters*/
1269         ixgbe_reset_qstat_mappings(hw);
1270
1271         /* Allocate memory for storing MAC addresses */
1272         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1273                                                hw->mac.num_rar_entries, 0);
1274         if (eth_dev->data->mac_addrs == NULL) {
1275                 PMD_INIT_LOG(ERR,
1276                              "Failed to allocate %u bytes needed to store "
1277                              "MAC addresses",
1278                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1279                 return -ENOMEM;
1280         }
1281         /* Copy the permanent MAC address */
1282         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1283                         &eth_dev->data->mac_addrs[0]);
1284
1285         /* Allocate memory for storing hash filter MAC addresses */
1286         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1287                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1288         if (eth_dev->data->hash_mac_addrs == NULL) {
1289                 PMD_INIT_LOG(ERR,
1290                              "Failed to allocate %d bytes needed to store MAC addresses",
1291                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1292                 return -ENOMEM;
1293         }
1294
1295         /* initialize the vfta */
1296         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1297
1298         /* initialize the hw strip bitmap*/
1299         memset(hwstrip, 0, sizeof(*hwstrip));
1300
1301         /* initialize PF if max_vfs not zero */
1302         ixgbe_pf_host_init(eth_dev);
1303
1304         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1305         /* let hardware know driver is loaded */
1306         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1307         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1308         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1309         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1310         IXGBE_WRITE_FLUSH(hw);
1311
1312         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1313                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1314                              (int) hw->mac.type, (int) hw->phy.type,
1315                              (int) hw->phy.sfp_type);
1316         else
1317                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1318                              (int) hw->mac.type, (int) hw->phy.type);
1319
1320         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1321                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1322                      pci_dev->id.device_id);
1323
1324         rte_intr_callback_register(intr_handle,
1325                                    ixgbe_dev_interrupt_handler, eth_dev);
1326
1327         /* enable uio/vfio intr/eventfd mapping */
1328         rte_intr_enable(intr_handle);
1329
1330         /* enable support intr */
1331         ixgbe_enable_intr(eth_dev);
1332
1333         /* initialize filter info */
1334         memset(filter_info, 0,
1335                sizeof(struct ixgbe_filter_info));
1336
1337         /* initialize 5tuple filter list */
1338         TAILQ_INIT(&filter_info->fivetuple_list);
1339
1340         /* initialize flow director filter list & hash */
1341         ixgbe_fdir_filter_init(eth_dev);
1342
1343         /* initialize l2 tunnel filter list & hash */
1344         ixgbe_l2_tn_filter_init(eth_dev);
1345         return 0;
1346 }
1347
1348 static int
1349 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1350 {
1351         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1352         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1353         struct ixgbe_hw *hw;
1354
1355         PMD_INIT_FUNC_TRACE();
1356
1357         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1358                 return -EPERM;
1359
1360         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1361
1362         if (hw->adapter_stopped == 0)
1363                 ixgbe_dev_close(eth_dev);
1364
1365         eth_dev->dev_ops = NULL;
1366         eth_dev->rx_pkt_burst = NULL;
1367         eth_dev->tx_pkt_burst = NULL;
1368
1369         /* Unlock any pending hardware semaphore */
1370         ixgbe_swfw_lock_reset(hw);
1371
1372         /* disable uio intr before callback unregister */
1373         rte_intr_disable(intr_handle);
1374         rte_intr_callback_unregister(intr_handle,
1375                                      ixgbe_dev_interrupt_handler, eth_dev);
1376
1377         /* uninitialize PF if max_vfs not zero */
1378         ixgbe_pf_host_uninit(eth_dev);
1379
1380         rte_free(eth_dev->data->mac_addrs);
1381         eth_dev->data->mac_addrs = NULL;
1382
1383         rte_free(eth_dev->data->hash_mac_addrs);
1384         eth_dev->data->hash_mac_addrs = NULL;
1385
1386         /* remove all the fdir filters & hash */
1387         ixgbe_fdir_filter_uninit(eth_dev);
1388
1389         /* remove all the L2 tunnel filters & hash */
1390         ixgbe_l2_tn_filter_uninit(eth_dev);
1391
1392         /* Remove all ntuple filters of the device */
1393         ixgbe_ntuple_filter_uninit(eth_dev);
1394
1395         return 0;
1396 }
1397
1398 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1399 {
1400         struct ixgbe_filter_info *filter_info =
1401                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1402         struct ixgbe_5tuple_filter *p_5tuple;
1403
1404         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1405                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1406                              p_5tuple,
1407                              entries);
1408                 rte_free(p_5tuple);
1409         }
1410         memset(filter_info->fivetuple_mask, 0,
1411                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1412
1413         return 0;
1414 }
1415
1416 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1417 {
1418         struct ixgbe_hw_fdir_info *fdir_info =
1419                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1420         struct ixgbe_fdir_filter *fdir_filter;
1421
1422                 if (fdir_info->hash_map)
1423                 rte_free(fdir_info->hash_map);
1424         if (fdir_info->hash_handle)
1425                 rte_hash_free(fdir_info->hash_handle);
1426
1427         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1428                 TAILQ_REMOVE(&fdir_info->fdir_list,
1429                              fdir_filter,
1430                              entries);
1431                 rte_free(fdir_filter);
1432         }
1433
1434         return 0;
1435 }
1436
1437 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1438 {
1439         struct ixgbe_l2_tn_info *l2_tn_info =
1440                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1441         struct ixgbe_l2_tn_filter *l2_tn_filter;
1442
1443         if (l2_tn_info->hash_map)
1444                 rte_free(l2_tn_info->hash_map);
1445         if (l2_tn_info->hash_handle)
1446                 rte_hash_free(l2_tn_info->hash_handle);
1447
1448         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1449                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1450                              l2_tn_filter,
1451                              entries);
1452                 rte_free(l2_tn_filter);
1453         }
1454
1455         return 0;
1456 }
1457
1458 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1459 {
1460         struct ixgbe_hw_fdir_info *fdir_info =
1461                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1462         char fdir_hash_name[RTE_HASH_NAMESIZE];
1463         struct rte_hash_parameters fdir_hash_params = {
1464                 .name = fdir_hash_name,
1465                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1466                 .key_len = sizeof(union ixgbe_atr_input),
1467                 .hash_func = rte_hash_crc,
1468                 .hash_func_init_val = 0,
1469                 .socket_id = rte_socket_id(),
1470         };
1471
1472         TAILQ_INIT(&fdir_info->fdir_list);
1473         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1474                  "fdir_%s", eth_dev->data->name);
1475         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1476         if (!fdir_info->hash_handle) {
1477                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1478                 return -EINVAL;
1479         }
1480         fdir_info->hash_map = rte_zmalloc("ixgbe",
1481                                           sizeof(struct ixgbe_fdir_filter *) *
1482                                           IXGBE_MAX_FDIR_FILTER_NUM,
1483                                           0);
1484         if (!fdir_info->hash_map) {
1485                 PMD_INIT_LOG(ERR,
1486                              "Failed to allocate memory for fdir hash map!");
1487                 return -ENOMEM;
1488         }
1489         return 0;
1490 }
1491
1492 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1493 {
1494         struct ixgbe_l2_tn_info *l2_tn_info =
1495                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1496         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1497         struct rte_hash_parameters l2_tn_hash_params = {
1498                 .name = l2_tn_hash_name,
1499                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1500                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1501                 .hash_func = rte_hash_crc,
1502                 .hash_func_init_val = 0,
1503                 .socket_id = rte_socket_id(),
1504         };
1505
1506         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1507         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1508                  "l2_tn_%s", eth_dev->data->name);
1509         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1510         if (!l2_tn_info->hash_handle) {
1511                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1512                 return -EINVAL;
1513         }
1514         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1515                                    sizeof(struct ixgbe_l2_tn_filter *) *
1516                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1517                                    0);
1518         if (!l2_tn_info->hash_map) {
1519                 PMD_INIT_LOG(ERR,
1520                         "Failed to allocate memory for L2 TN hash map!");
1521                 return -ENOMEM;
1522         }
1523
1524         return 0;
1525 }
1526 /*
1527  * Negotiate mailbox API version with the PF.
1528  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1529  * Then we try to negotiate starting with the most recent one.
1530  * If all negotiation attempts fail, then we will proceed with
1531  * the default one (ixgbe_mbox_api_10).
1532  */
1533 static void
1534 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1535 {
1536         int32_t i;
1537
1538         /* start with highest supported, proceed down */
1539         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1540                 ixgbe_mbox_api_12,
1541                 ixgbe_mbox_api_11,
1542                 ixgbe_mbox_api_10,
1543         };
1544
1545         for (i = 0;
1546                         i != RTE_DIM(sup_ver) &&
1547                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1548                         i++)
1549                 ;
1550 }
1551
1552 static void
1553 generate_random_mac_addr(struct ether_addr *mac_addr)
1554 {
1555         uint64_t random;
1556
1557         /* Set Organizationally Unique Identifier (OUI) prefix. */
1558         mac_addr->addr_bytes[0] = 0x00;
1559         mac_addr->addr_bytes[1] = 0x09;
1560         mac_addr->addr_bytes[2] = 0xC0;
1561         /* Force indication of locally assigned MAC address. */
1562         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1563         /* Generate the last 3 bytes of the MAC address with a random number. */
1564         random = rte_rand();
1565         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1566 }
1567
1568 /*
1569  * Virtual Function device init
1570  */
1571 static int
1572 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1573 {
1574         int diag;
1575         uint32_t tc, tcs;
1576         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1577         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1578         struct ixgbe_hw *hw =
1579                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1580         struct ixgbe_vfta *shadow_vfta =
1581                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1582         struct ixgbe_hwstrip *hwstrip =
1583                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1584         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1585
1586         PMD_INIT_FUNC_TRACE();
1587
1588         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1589         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1590         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1591
1592         /* for secondary processes, we don't initialise any further as primary
1593          * has already done this work. Only check we don't need a different
1594          * RX function
1595          */
1596         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1597                 struct ixgbe_tx_queue *txq;
1598                 /* TX queue function in primary, set by last queue initialized
1599                  * Tx queue may not initialized by primary process
1600                  */
1601                 if (eth_dev->data->tx_queues) {
1602                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1603                         ixgbe_set_tx_function(eth_dev, txq);
1604                 } else {
1605                         /* Use default TX function if we get here */
1606                         PMD_INIT_LOG(NOTICE,
1607                                      "No TX queues configured yet. Using default TX function.");
1608                 }
1609
1610                 ixgbe_set_rx_function(eth_dev);
1611
1612                 return 0;
1613         }
1614
1615         rte_eth_copy_pci_info(eth_dev, pci_dev);
1616         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1617
1618         hw->device_id = pci_dev->id.device_id;
1619         hw->vendor_id = pci_dev->id.vendor_id;
1620         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1621
1622         /* initialize the vfta */
1623         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1624
1625         /* initialize the hw strip bitmap*/
1626         memset(hwstrip, 0, sizeof(*hwstrip));
1627
1628         /* Initialize the shared code (base driver) */
1629         diag = ixgbe_init_shared_code(hw);
1630         if (diag != IXGBE_SUCCESS) {
1631                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1632                 return -EIO;
1633         }
1634
1635         /* init_mailbox_params */
1636         hw->mbx.ops.init_params(hw);
1637
1638         /* Reset the hw statistics */
1639         ixgbevf_dev_stats_reset(eth_dev);
1640
1641         /* Disable the interrupts for VF */
1642         ixgbevf_intr_disable(hw);
1643
1644         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1645         diag = hw->mac.ops.reset_hw(hw);
1646
1647         /*
1648          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1649          * the underlying PF driver has not assigned a MAC address to the VF.
1650          * In this case, assign a random MAC address.
1651          */
1652         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1653                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1654                 return diag;
1655         }
1656
1657         /* negotiate mailbox API version to use with the PF. */
1658         ixgbevf_negotiate_api(hw);
1659
1660         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1661         ixgbevf_get_queues(hw, &tcs, &tc);
1662
1663         /* Allocate memory for storing MAC addresses */
1664         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1665                                                hw->mac.num_rar_entries, 0);
1666         if (eth_dev->data->mac_addrs == NULL) {
1667                 PMD_INIT_LOG(ERR,
1668                              "Failed to allocate %u bytes needed to store "
1669                              "MAC addresses",
1670                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1671                 return -ENOMEM;
1672         }
1673
1674         /* Generate a random MAC address, if none was assigned by PF. */
1675         if (is_zero_ether_addr(perm_addr)) {
1676                 generate_random_mac_addr(perm_addr);
1677                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1678                 if (diag) {
1679                         rte_free(eth_dev->data->mac_addrs);
1680                         eth_dev->data->mac_addrs = NULL;
1681                         return diag;
1682                 }
1683                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1684                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1685                              "%02x:%02x:%02x:%02x:%02x:%02x",
1686                              perm_addr->addr_bytes[0],
1687                              perm_addr->addr_bytes[1],
1688                              perm_addr->addr_bytes[2],
1689                              perm_addr->addr_bytes[3],
1690                              perm_addr->addr_bytes[4],
1691                              perm_addr->addr_bytes[5]);
1692         }
1693
1694         /* Copy the permanent MAC address */
1695         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1696
1697         /* reset the hardware with the new settings */
1698         diag = hw->mac.ops.start_hw(hw);
1699         switch (diag) {
1700         case  0:
1701                 break;
1702
1703         default:
1704                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1705                 return -EIO;
1706         }
1707
1708         rte_intr_callback_register(intr_handle,
1709                                    ixgbevf_dev_interrupt_handler, eth_dev);
1710         rte_intr_enable(intr_handle);
1711         ixgbevf_intr_enable(hw);
1712
1713         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1714                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1715                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1716
1717         return 0;
1718 }
1719
1720 /* Virtual Function device uninit */
1721
1722 static int
1723 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1724 {
1725         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1726         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1727         struct ixgbe_hw *hw;
1728
1729         PMD_INIT_FUNC_TRACE();
1730
1731         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1732                 return -EPERM;
1733
1734         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1735
1736         if (hw->adapter_stopped == 0)
1737                 ixgbevf_dev_close(eth_dev);
1738
1739         eth_dev->dev_ops = NULL;
1740         eth_dev->rx_pkt_burst = NULL;
1741         eth_dev->tx_pkt_burst = NULL;
1742
1743         /* Disable the interrupts for VF */
1744         ixgbevf_intr_disable(hw);
1745
1746         rte_free(eth_dev->data->mac_addrs);
1747         eth_dev->data->mac_addrs = NULL;
1748
1749         rte_intr_disable(intr_handle);
1750         rte_intr_callback_unregister(intr_handle,
1751                                      ixgbevf_dev_interrupt_handler, eth_dev);
1752
1753         return 0;
1754 }
1755
1756 static struct eth_driver rte_ixgbe_pmd = {
1757         .pci_drv = {
1758                 .id_table = pci_id_ixgbe_map,
1759                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1760                 .probe = rte_eth_dev_pci_probe,
1761                 .remove = rte_eth_dev_pci_remove,
1762         },
1763         .eth_dev_init = eth_ixgbe_dev_init,
1764         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1765         .dev_private_size = sizeof(struct ixgbe_adapter),
1766 };
1767
1768 /*
1769  * virtual function driver struct
1770  */
1771 static struct eth_driver rte_ixgbevf_pmd = {
1772         .pci_drv = {
1773                 .id_table = pci_id_ixgbevf_map,
1774                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1775                 .probe = rte_eth_dev_pci_probe,
1776                 .remove = rte_eth_dev_pci_remove,
1777         },
1778         .eth_dev_init = eth_ixgbevf_dev_init,
1779         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1780         .dev_private_size = sizeof(struct ixgbe_adapter),
1781 };
1782
1783 static int
1784 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1785 {
1786         struct ixgbe_hw *hw =
1787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1788         struct ixgbe_vfta *shadow_vfta =
1789                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1790         uint32_t vfta;
1791         uint32_t vid_idx;
1792         uint32_t vid_bit;
1793
1794         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1795         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1796         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1797         if (on)
1798                 vfta |= vid_bit;
1799         else
1800                 vfta &= ~vid_bit;
1801         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1802
1803         /* update local VFTA copy */
1804         shadow_vfta->vfta[vid_idx] = vfta;
1805
1806         return 0;
1807 }
1808
1809 static void
1810 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1811 {
1812         if (on)
1813                 ixgbe_vlan_hw_strip_enable(dev, queue);
1814         else
1815                 ixgbe_vlan_hw_strip_disable(dev, queue);
1816 }
1817
1818 static int
1819 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1820                     enum rte_vlan_type vlan_type,
1821                     uint16_t tpid)
1822 {
1823         struct ixgbe_hw *hw =
1824                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825         int ret = 0;
1826         uint32_t reg;
1827         uint32_t qinq;
1828
1829         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1830         qinq &= IXGBE_DMATXCTL_GDV;
1831
1832         switch (vlan_type) {
1833         case ETH_VLAN_TYPE_INNER:
1834                 if (qinq) {
1835                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1836                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1837                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1838                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1839                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1840                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1841                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1842                 } else {
1843                         ret = -ENOTSUP;
1844                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1845                                     " by single VLAN");
1846                 }
1847                 break;
1848         case ETH_VLAN_TYPE_OUTER:
1849                 if (qinq) {
1850                         /* Only the high 16-bits is valid */
1851                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1852                                         IXGBE_EXVET_VET_EXT_SHIFT);
1853                 } else {
1854                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1855                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1856                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1857                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1858                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1859                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1860                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1861                 }
1862
1863                 break;
1864         default:
1865                 ret = -EINVAL;
1866                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1867                 break;
1868         }
1869
1870         return ret;
1871 }
1872
1873 void
1874 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1875 {
1876         struct ixgbe_hw *hw =
1877                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1878         uint32_t vlnctrl;
1879
1880         PMD_INIT_FUNC_TRACE();
1881
1882         /* Filter Table Disable */
1883         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1884         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1885
1886         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1887 }
1888
1889 void
1890 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1891 {
1892         struct ixgbe_hw *hw =
1893                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1894         struct ixgbe_vfta *shadow_vfta =
1895                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1896         uint32_t vlnctrl;
1897         uint16_t i;
1898
1899         PMD_INIT_FUNC_TRACE();
1900
1901         /* Filter Table Enable */
1902         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1903         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1904         vlnctrl |= IXGBE_VLNCTRL_VFE;
1905
1906         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1907
1908         /* write whatever is in local vfta copy */
1909         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1910                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1911 }
1912
1913 static void
1914 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1915 {
1916         struct ixgbe_hwstrip *hwstrip =
1917                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1918         struct ixgbe_rx_queue *rxq;
1919
1920         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1921                 return;
1922
1923         if (on)
1924                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1925         else
1926                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1927
1928         if (queue >= dev->data->nb_rx_queues)
1929                 return;
1930
1931         rxq = dev->data->rx_queues[queue];
1932
1933         if (on)
1934                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1935         else
1936                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1937 }
1938
1939 static void
1940 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1941 {
1942         struct ixgbe_hw *hw =
1943                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1944         uint32_t ctrl;
1945
1946         PMD_INIT_FUNC_TRACE();
1947
1948         if (hw->mac.type == ixgbe_mac_82598EB) {
1949                 /* No queue level support */
1950                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1951                 return;
1952         }
1953
1954         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1955         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1956         ctrl &= ~IXGBE_RXDCTL_VME;
1957         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1958
1959         /* record those setting for HW strip per queue */
1960         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1961 }
1962
1963 static void
1964 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1965 {
1966         struct ixgbe_hw *hw =
1967                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1968         uint32_t ctrl;
1969
1970         PMD_INIT_FUNC_TRACE();
1971
1972         if (hw->mac.type == ixgbe_mac_82598EB) {
1973                 /* No queue level supported */
1974                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1975                 return;
1976         }
1977
1978         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1979         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1980         ctrl |= IXGBE_RXDCTL_VME;
1981         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1982
1983         /* record those setting for HW strip per queue */
1984         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1985 }
1986
1987 void
1988 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1989 {
1990         struct ixgbe_hw *hw =
1991                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1992         uint32_t ctrl;
1993         uint16_t i;
1994         struct ixgbe_rx_queue *rxq;
1995
1996         PMD_INIT_FUNC_TRACE();
1997
1998         if (hw->mac.type == ixgbe_mac_82598EB) {
1999                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2000                 ctrl &= ~IXGBE_VLNCTRL_VME;
2001                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2002         } else {
2003                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2004                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2005                         rxq = dev->data->rx_queues[i];
2006                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2007                         ctrl &= ~IXGBE_RXDCTL_VME;
2008                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2009
2010                         /* record those setting for HW strip per queue */
2011                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2012                 }
2013         }
2014 }
2015
2016 void
2017 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2018 {
2019         struct ixgbe_hw *hw =
2020                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2021         uint32_t ctrl;
2022         uint16_t i;
2023         struct ixgbe_rx_queue *rxq;
2024
2025         PMD_INIT_FUNC_TRACE();
2026
2027         if (hw->mac.type == ixgbe_mac_82598EB) {
2028                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2029                 ctrl |= IXGBE_VLNCTRL_VME;
2030                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2031         } else {
2032                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2033                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2034                         rxq = dev->data->rx_queues[i];
2035                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2036                         ctrl |= IXGBE_RXDCTL_VME;
2037                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2038
2039                         /* record those setting for HW strip per queue */
2040                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2041                 }
2042         }
2043 }
2044
2045 static void
2046 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2047 {
2048         struct ixgbe_hw *hw =
2049                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050         uint32_t ctrl;
2051
2052         PMD_INIT_FUNC_TRACE();
2053
2054         /* DMATXCTRL: Geric Double VLAN Disable */
2055         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2056         ctrl &= ~IXGBE_DMATXCTL_GDV;
2057         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2058
2059         /* CTRL_EXT: Global Double VLAN Disable */
2060         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2061         ctrl &= ~IXGBE_EXTENDED_VLAN;
2062         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2063
2064 }
2065
2066 static void
2067 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2068 {
2069         struct ixgbe_hw *hw =
2070                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2071         uint32_t ctrl;
2072
2073         PMD_INIT_FUNC_TRACE();
2074
2075         /* DMATXCTRL: Geric Double VLAN Enable */
2076         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2077         ctrl |= IXGBE_DMATXCTL_GDV;
2078         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2079
2080         /* CTRL_EXT: Global Double VLAN Enable */
2081         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2082         ctrl |= IXGBE_EXTENDED_VLAN;
2083         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2084
2085         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2086         if (hw->mac.type == ixgbe_mac_X550 ||
2087             hw->mac.type == ixgbe_mac_X550EM_x ||
2088             hw->mac.type == ixgbe_mac_X550EM_a) {
2089                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2090                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2091                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2092         }
2093
2094         /*
2095          * VET EXT field in the EXVET register = 0x8100 by default
2096          * So no need to change. Same to VT field of DMATXCTL register
2097          */
2098 }
2099
2100 static void
2101 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2102 {
2103         if (mask & ETH_VLAN_STRIP_MASK) {
2104                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2105                         ixgbe_vlan_hw_strip_enable_all(dev);
2106                 else
2107                         ixgbe_vlan_hw_strip_disable_all(dev);
2108         }
2109
2110         if (mask & ETH_VLAN_FILTER_MASK) {
2111                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2112                         ixgbe_vlan_hw_filter_enable(dev);
2113                 else
2114                         ixgbe_vlan_hw_filter_disable(dev);
2115         }
2116
2117         if (mask & ETH_VLAN_EXTEND_MASK) {
2118                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2119                         ixgbe_vlan_hw_extend_enable(dev);
2120                 else
2121                         ixgbe_vlan_hw_extend_disable(dev);
2122         }
2123 }
2124
2125 static void
2126 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2127 {
2128         struct ixgbe_hw *hw =
2129                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2130         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2131         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2132
2133         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2134         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2135 }
2136
2137 static int
2138 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2139 {
2140         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2141
2142         switch (nb_rx_q) {
2143         case 1:
2144         case 2:
2145                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2146                 break;
2147         case 4:
2148                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2149                 break;
2150         default:
2151                 return -EINVAL;
2152         }
2153
2154         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2155         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2156
2157         return 0;
2158 }
2159
2160 static int
2161 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2162 {
2163         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2164         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2165         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2166         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2167
2168         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2169                 /* check multi-queue mode */
2170                 switch (dev_conf->rxmode.mq_mode) {
2171                 case ETH_MQ_RX_VMDQ_DCB:
2172                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2173                         break;
2174                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2175                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2176                         PMD_INIT_LOG(ERR, "SRIOV active,"
2177                                         " unsupported mq_mode rx %d.",
2178                                         dev_conf->rxmode.mq_mode);
2179                         return -EINVAL;
2180                 case ETH_MQ_RX_RSS:
2181                 case ETH_MQ_RX_VMDQ_RSS:
2182                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2183                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2184                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2185                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2186                                                 " invalid queue number"
2187                                                 " for VMDQ RSS, allowed"
2188                                                 " value are 1, 2 or 4.");
2189                                         return -EINVAL;
2190                                 }
2191                         break;
2192                 case ETH_MQ_RX_VMDQ_ONLY:
2193                 case ETH_MQ_RX_NONE:
2194                         /* if nothing mq mode configure, use default scheme */
2195                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2196                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2197                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2198                         break;
2199                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2200                         /* SRIOV only works in VMDq enable mode */
2201                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2202                                         " wrong mq_mode rx %d.",
2203                                         dev_conf->rxmode.mq_mode);
2204                         return -EINVAL;
2205                 }
2206
2207                 switch (dev_conf->txmode.mq_mode) {
2208                 case ETH_MQ_TX_VMDQ_DCB:
2209                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2210                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2211                         break;
2212                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2213                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2214                         break;
2215                 }
2216
2217                 /* check valid queue number */
2218                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2219                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2220                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2221                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2222                                         " must be less than or equal to %d.",
2223                                         nb_rx_q, nb_tx_q,
2224                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2225                         return -EINVAL;
2226                 }
2227         } else {
2228                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2229                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2230                                           " not supported.");
2231                         return -EINVAL;
2232                 }
2233                 /* check configuration for vmdb+dcb mode */
2234                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2235                         const struct rte_eth_vmdq_dcb_conf *conf;
2236
2237                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2238                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2239                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2240                                 return -EINVAL;
2241                         }
2242                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2243                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2244                                conf->nb_queue_pools == ETH_32_POOLS)) {
2245                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2246                                                 " nb_queue_pools must be %d or %d.",
2247                                                 ETH_16_POOLS, ETH_32_POOLS);
2248                                 return -EINVAL;
2249                         }
2250                 }
2251                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2252                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2253
2254                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2255                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2256                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2257                                 return -EINVAL;
2258                         }
2259                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2260                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2261                                conf->nb_queue_pools == ETH_32_POOLS)) {
2262                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2263                                                 " nb_queue_pools != %d and"
2264                                                 " nb_queue_pools != %d.",
2265                                                 ETH_16_POOLS, ETH_32_POOLS);
2266                                 return -EINVAL;
2267                         }
2268                 }
2269
2270                 /* For DCB mode check our configuration before we go further */
2271                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2272                         const struct rte_eth_dcb_rx_conf *conf;
2273
2274                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2275                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2276                                                  IXGBE_DCB_NB_QUEUES);
2277                                 return -EINVAL;
2278                         }
2279                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2280                         if (!(conf->nb_tcs == ETH_4_TCS ||
2281                                conf->nb_tcs == ETH_8_TCS)) {
2282                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2283                                                 " and nb_tcs != %d.",
2284                                                 ETH_4_TCS, ETH_8_TCS);
2285                                 return -EINVAL;
2286                         }
2287                 }
2288
2289                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2290                         const struct rte_eth_dcb_tx_conf *conf;
2291
2292                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2293                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2294                                                  IXGBE_DCB_NB_QUEUES);
2295                                 return -EINVAL;
2296                         }
2297                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2298                         if (!(conf->nb_tcs == ETH_4_TCS ||
2299                                conf->nb_tcs == ETH_8_TCS)) {
2300                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2301                                                 " and nb_tcs != %d.",
2302                                                 ETH_4_TCS, ETH_8_TCS);
2303                                 return -EINVAL;
2304                         }
2305                 }
2306
2307                 /*
2308                  * When DCB/VT is off, maximum number of queues changes,
2309                  * except for 82598EB, which remains constant.
2310                  */
2311                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2312                                 hw->mac.type != ixgbe_mac_82598EB) {
2313                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2314                                 PMD_INIT_LOG(ERR,
2315                                              "Neither VT nor DCB are enabled, "
2316                                              "nb_tx_q > %d.",
2317                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2318                                 return -EINVAL;
2319                         }
2320                 }
2321         }
2322         return 0;
2323 }
2324
2325 static int
2326 ixgbe_dev_configure(struct rte_eth_dev *dev)
2327 {
2328         struct ixgbe_interrupt *intr =
2329                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2330         struct ixgbe_adapter *adapter =
2331                 (struct ixgbe_adapter *)dev->data->dev_private;
2332         int ret;
2333
2334         PMD_INIT_FUNC_TRACE();
2335         /* multipe queue mode checking */
2336         ret  = ixgbe_check_mq_mode(dev);
2337         if (ret != 0) {
2338                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2339                             ret);
2340                 return ret;
2341         }
2342
2343         /* set flag to update link status after init */
2344         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2345
2346         /*
2347          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2348          * allocation or vector Rx preconditions we will reset it.
2349          */
2350         adapter->rx_bulk_alloc_allowed = true;
2351         adapter->rx_vec_allowed = true;
2352
2353         return 0;
2354 }
2355
2356 static void
2357 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2358 {
2359         struct ixgbe_hw *hw =
2360                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361         struct ixgbe_interrupt *intr =
2362                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2363         uint32_t gpie;
2364
2365         /* only set up it on X550EM_X */
2366         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2367                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2368                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2369                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2370                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2371                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2372         }
2373 }
2374
2375 /*
2376  * Configure device link speed and setup link.
2377  * It returns 0 on success.
2378  */
2379 static int
2380 ixgbe_dev_start(struct rte_eth_dev *dev)
2381 {
2382         struct ixgbe_hw *hw =
2383                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384         struct ixgbe_vf_info *vfinfo =
2385                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2386         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2387         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2388         uint32_t intr_vector = 0;
2389         int err, link_up = 0, negotiate = 0;
2390         uint32_t speed = 0;
2391         int mask = 0;
2392         int status;
2393         uint16_t vf, idx;
2394         uint32_t *link_speeds;
2395
2396         PMD_INIT_FUNC_TRACE();
2397
2398         /* IXGBE devices don't support:
2399         *    - half duplex (checked afterwards for valid speeds)
2400         *    - fixed speed: TODO implement
2401         */
2402         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2403                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2404                              dev->data->port_id);
2405                 return -EINVAL;
2406         }
2407
2408         /* disable uio/vfio intr/eventfd mapping */
2409         rte_intr_disable(intr_handle);
2410
2411         /* stop adapter */
2412         hw->adapter_stopped = 0;
2413         ixgbe_stop_adapter(hw);
2414
2415         /* reinitialize adapter
2416          * this calls reset and start
2417          */
2418         status = ixgbe_pf_reset_hw(hw);
2419         if (status != 0)
2420                 return -1;
2421         hw->mac.ops.start_hw(hw);
2422         hw->mac.get_link_status = true;
2423
2424         /* configure PF module if SRIOV enabled */
2425         ixgbe_pf_host_configure(dev);
2426
2427         ixgbe_dev_phy_intr_setup(dev);
2428
2429         /* check and configure queue intr-vector mapping */
2430         if ((rte_intr_cap_multiple(intr_handle) ||
2431              !RTE_ETH_DEV_SRIOV(dev).active) &&
2432             dev->data->dev_conf.intr_conf.rxq != 0) {
2433                 intr_vector = dev->data->nb_rx_queues;
2434                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2435                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2436                                         IXGBE_MAX_INTR_QUEUE_NUM);
2437                         return -ENOTSUP;
2438                 }
2439                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2440                         return -1;
2441         }
2442
2443         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2444                 intr_handle->intr_vec =
2445                         rte_zmalloc("intr_vec",
2446                                     dev->data->nb_rx_queues * sizeof(int), 0);
2447                 if (intr_handle->intr_vec == NULL) {
2448                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2449                                      " intr_vec\n", dev->data->nb_rx_queues);
2450                         return -ENOMEM;
2451                 }
2452         }
2453
2454         /* confiugre msix for sleep until rx interrupt */
2455         ixgbe_configure_msix(dev);
2456
2457         /* initialize transmission unit */
2458         ixgbe_dev_tx_init(dev);
2459
2460         /* This can fail when allocating mbufs for descriptor rings */
2461         err = ixgbe_dev_rx_init(dev);
2462         if (err) {
2463                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2464                 goto error;
2465         }
2466
2467     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2468                 ETH_VLAN_EXTEND_MASK;
2469         ixgbe_vlan_offload_set(dev, mask);
2470
2471         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2472                 /* Enable vlan filtering for VMDq */
2473                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2474         }
2475
2476         /* Configure DCB hw */
2477         ixgbe_configure_dcb(dev);
2478
2479         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2480                 err = ixgbe_fdir_configure(dev);
2481                 if (err)
2482                         goto error;
2483         }
2484
2485         /* Restore vf rate limit */
2486         if (vfinfo != NULL) {
2487                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2488                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2489                                 if (vfinfo[vf].tx_rate[idx] != 0)
2490                                         rte_pmd_ixgbe_set_vf_rate_limit(
2491                                                 dev->data->port_id, vf,
2492                                                 vfinfo[vf].tx_rate[idx],
2493                                                 1 << idx);
2494         }
2495
2496         ixgbe_restore_statistics_mapping(dev);
2497
2498         err = ixgbe_dev_rxtx_start(dev);
2499         if (err < 0) {
2500                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2501                 goto error;
2502         }
2503
2504         /* Skip link setup if loopback mode is enabled for 82599. */
2505         if (hw->mac.type == ixgbe_mac_82599EB &&
2506                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2507                 goto skip_link_setup;
2508
2509         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2510                 err = hw->mac.ops.setup_sfp(hw);
2511                 if (err)
2512                         goto error;
2513         }
2514
2515         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2516                 /* Turn on the copper */
2517                 ixgbe_set_phy_power(hw, true);
2518         } else {
2519                 /* Turn on the laser */
2520                 ixgbe_enable_tx_laser(hw);
2521         }
2522
2523         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2524         if (err)
2525                 goto error;
2526         dev->data->dev_link.link_status = link_up;
2527
2528         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2529         if (err)
2530                 goto error;
2531
2532         link_speeds = &dev->data->dev_conf.link_speeds;
2533         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2534                         ETH_LINK_SPEED_10G)) {
2535                 PMD_INIT_LOG(ERR, "Invalid link setting");
2536                 goto error;
2537         }
2538
2539         speed = 0x0;
2540         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2541                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2542                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2543                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2544         } else {
2545                 if (*link_speeds & ETH_LINK_SPEED_10G)
2546                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2547                 if (*link_speeds & ETH_LINK_SPEED_1G)
2548                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2549                 if (*link_speeds & ETH_LINK_SPEED_100M)
2550                         speed |= IXGBE_LINK_SPEED_100_FULL;
2551         }
2552
2553         err = ixgbe_setup_link(hw, speed, link_up);
2554         if (err)
2555                 goto error;
2556
2557 skip_link_setup:
2558
2559         if (rte_intr_allow_others(intr_handle)) {
2560                 /* check if lsc interrupt is enabled */
2561                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2562                         ixgbe_dev_lsc_interrupt_setup(dev);
2563                 ixgbe_dev_macsec_interrupt_setup(dev);
2564         } else {
2565                 rte_intr_callback_unregister(intr_handle,
2566                                              ixgbe_dev_interrupt_handler, dev);
2567                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2568                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2569                                      " no intr multiplex\n");
2570         }
2571
2572         /* check if rxq interrupt is enabled */
2573         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2574             rte_intr_dp_is_en(intr_handle))
2575                 ixgbe_dev_rxq_interrupt_setup(dev);
2576
2577         /* enable uio/vfio intr/eventfd mapping */
2578         rte_intr_enable(intr_handle);
2579
2580         /* resume enabled intr since hw reset */
2581         ixgbe_enable_intr(dev);
2582         ixgbe_filter_restore(dev);
2583
2584         return 0;
2585
2586 error:
2587         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2588         ixgbe_dev_clear_queues(dev);
2589         return -EIO;
2590 }
2591
2592 /*
2593  * Stop device: disable rx and tx functions to allow for reconfiguring.
2594  */
2595 static void
2596 ixgbe_dev_stop(struct rte_eth_dev *dev)
2597 {
2598         struct rte_eth_link link;
2599         struct ixgbe_hw *hw =
2600                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601         struct ixgbe_vf_info *vfinfo =
2602                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2603         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2604         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2605         int vf;
2606
2607         PMD_INIT_FUNC_TRACE();
2608
2609         /* disable interrupts */
2610         ixgbe_disable_intr(hw);
2611
2612         /* reset the NIC */
2613         ixgbe_pf_reset_hw(hw);
2614         hw->adapter_stopped = 0;
2615
2616         /* stop adapter */
2617         ixgbe_stop_adapter(hw);
2618
2619         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2620                 vfinfo[vf].clear_to_send = false;
2621
2622         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2623                 /* Turn off the copper */
2624                 ixgbe_set_phy_power(hw, false);
2625         } else {
2626                 /* Turn off the laser */
2627                 ixgbe_disable_tx_laser(hw);
2628         }
2629
2630         ixgbe_dev_clear_queues(dev);
2631
2632         /* Clear stored conf */
2633         dev->data->scattered_rx = 0;
2634         dev->data->lro = 0;
2635
2636         /* Clear recorded link status */
2637         memset(&link, 0, sizeof(link));
2638         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2639
2640         if (!rte_intr_allow_others(intr_handle))
2641                 /* resume to the default handler */
2642                 rte_intr_callback_register(intr_handle,
2643                                            ixgbe_dev_interrupt_handler,
2644                                            (void *)dev);
2645
2646         /* Clean datapath event and queue/vec mapping */
2647         rte_intr_efd_disable(intr_handle);
2648         if (intr_handle->intr_vec != NULL) {
2649                 rte_free(intr_handle->intr_vec);
2650                 intr_handle->intr_vec = NULL;
2651         }
2652 }
2653
2654 /*
2655  * Set device link up: enable tx.
2656  */
2657 static int
2658 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2659 {
2660         struct ixgbe_hw *hw =
2661                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2662         if (hw->mac.type == ixgbe_mac_82599EB) {
2663 #ifdef RTE_NIC_BYPASS
2664                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2665                         /* Not suported in bypass mode */
2666                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2667                                      "by device id 0x%x", hw->device_id);
2668                         return -ENOTSUP;
2669                 }
2670 #endif
2671         }
2672
2673         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2674                 /* Turn on the copper */
2675                 ixgbe_set_phy_power(hw, true);
2676         } else {
2677                 /* Turn on the laser */
2678                 ixgbe_enable_tx_laser(hw);
2679         }
2680
2681         return 0;
2682 }
2683
2684 /*
2685  * Set device link down: disable tx.
2686  */
2687 static int
2688 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2689 {
2690         struct ixgbe_hw *hw =
2691                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692         if (hw->mac.type == ixgbe_mac_82599EB) {
2693 #ifdef RTE_NIC_BYPASS
2694                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2695                         /* Not suported in bypass mode */
2696                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2697                                      "by device id 0x%x", hw->device_id);
2698                         return -ENOTSUP;
2699                 }
2700 #endif
2701         }
2702
2703         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2704                 /* Turn off the copper */
2705                 ixgbe_set_phy_power(hw, false);
2706         } else {
2707                 /* Turn off the laser */
2708                 ixgbe_disable_tx_laser(hw);
2709         }
2710
2711         return 0;
2712 }
2713
2714 /*
2715  * Reest and stop device.
2716  */
2717 static void
2718 ixgbe_dev_close(struct rte_eth_dev *dev)
2719 {
2720         struct ixgbe_hw *hw =
2721                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2722
2723         PMD_INIT_FUNC_TRACE();
2724
2725         ixgbe_pf_reset_hw(hw);
2726
2727         ixgbe_dev_stop(dev);
2728         hw->adapter_stopped = 1;
2729
2730         ixgbe_dev_free_queues(dev);
2731
2732         ixgbe_disable_pcie_master(hw);
2733
2734         /* reprogram the RAR[0] in case user changed it. */
2735         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2736 }
2737
2738 static void
2739 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2740                            struct ixgbe_hw_stats *hw_stats,
2741                            struct ixgbe_macsec_stats *macsec_stats,
2742                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2743                            uint64_t *total_qprc, uint64_t *total_qprdc)
2744 {
2745         uint32_t bprc, lxon, lxoff, total;
2746         uint32_t delta_gprc = 0;
2747         unsigned i;
2748         /* Workaround for RX byte count not including CRC bytes when CRC
2749          * strip is enabled. CRC bytes are removed from counters when crc_strip
2750          * is disabled.
2751          */
2752         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2753                         IXGBE_HLREG0_RXCRCSTRP);
2754
2755         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2756         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2757         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2758         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2759
2760         for (i = 0; i < 8; i++) {
2761                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2762
2763                 /* global total per queue */
2764                 hw_stats->mpc[i] += mp;
2765                 /* Running comprehensive total for stats display */
2766                 *total_missed_rx += hw_stats->mpc[i];
2767                 if (hw->mac.type == ixgbe_mac_82598EB) {
2768                         hw_stats->rnbc[i] +=
2769                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2770                         hw_stats->pxonrxc[i] +=
2771                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2772                         hw_stats->pxoffrxc[i] +=
2773                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2774                 } else {
2775                         hw_stats->pxonrxc[i] +=
2776                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2777                         hw_stats->pxoffrxc[i] +=
2778                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2779                         hw_stats->pxon2offc[i] +=
2780                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2781                 }
2782                 hw_stats->pxontxc[i] +=
2783                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2784                 hw_stats->pxofftxc[i] +=
2785                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2786         }
2787         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2788                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2789                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2790                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2791
2792                 delta_gprc += delta_qprc;
2793
2794                 hw_stats->qprc[i] += delta_qprc;
2795                 hw_stats->qptc[i] += delta_qptc;
2796
2797                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2798                 hw_stats->qbrc[i] +=
2799                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2800                 if (crc_strip == 0)
2801                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2802
2803                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2804                 hw_stats->qbtc[i] +=
2805                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2806
2807                 hw_stats->qprdc[i] += delta_qprdc;
2808                 *total_qprdc += hw_stats->qprdc[i];
2809
2810                 *total_qprc += hw_stats->qprc[i];
2811                 *total_qbrc += hw_stats->qbrc[i];
2812         }
2813         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2814         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2815         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2816
2817         /*
2818          * An errata states that gprc actually counts good + missed packets:
2819          * Workaround to set gprc to summated queue packet receives
2820          */
2821         hw_stats->gprc = *total_qprc;
2822
2823         if (hw->mac.type != ixgbe_mac_82598EB) {
2824                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2825                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2826                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2827                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2828                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2829                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2830                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2831                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2832         } else {
2833                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2834                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2835                 /* 82598 only has a counter in the high register */
2836                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2837                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2838                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2839         }
2840         uint64_t old_tpr = hw_stats->tpr;
2841
2842         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2843         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2844
2845         if (crc_strip == 0)
2846                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2847
2848         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2849         hw_stats->gptc += delta_gptc;
2850         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2851         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2852
2853         /*
2854          * Workaround: mprc hardware is incorrectly counting
2855          * broadcasts, so for now we subtract those.
2856          */
2857         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2858         hw_stats->bprc += bprc;
2859         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2860         if (hw->mac.type == ixgbe_mac_82598EB)
2861                 hw_stats->mprc -= bprc;
2862
2863         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2864         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2865         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2866         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2867         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2868         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2869
2870         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2871         hw_stats->lxontxc += lxon;
2872         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2873         hw_stats->lxofftxc += lxoff;
2874         total = lxon + lxoff;
2875
2876         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2877         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2878         hw_stats->gptc -= total;
2879         hw_stats->mptc -= total;
2880         hw_stats->ptc64 -= total;
2881         hw_stats->gotc -= total * ETHER_MIN_LEN;
2882
2883         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2884         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2885         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2886         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2887         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2888         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2889         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2890         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2891         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2892         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2893         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2894         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2895         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2896         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2897         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2898         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2899         /* Only read FCOE on 82599 */
2900         if (hw->mac.type != ixgbe_mac_82598EB) {
2901                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2902                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2903                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2904                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2905                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2906         }
2907
2908         /* Flow Director Stats registers */
2909         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2910         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2911
2912         /* MACsec Stats registers */
2913         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2914         macsec_stats->out_pkts_encrypted +=
2915                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2916         macsec_stats->out_pkts_protected +=
2917                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2918         macsec_stats->out_octets_encrypted +=
2919                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2920         macsec_stats->out_octets_protected +=
2921                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2922         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2923         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2924         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2925         macsec_stats->in_pkts_unknownsci +=
2926                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2927         macsec_stats->in_octets_decrypted +=
2928                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2929         macsec_stats->in_octets_validated +=
2930                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2931         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2932         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2933         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2934         for (i = 0; i < 2; i++) {
2935                 macsec_stats->in_pkts_ok +=
2936                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2937                 macsec_stats->in_pkts_invalid +=
2938                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2939                 macsec_stats->in_pkts_notvalid +=
2940                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2941         }
2942         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2943         macsec_stats->in_pkts_notusingsa +=
2944                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2945 }
2946
2947 /*
2948  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2949  */
2950 static void
2951 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2952 {
2953         struct ixgbe_hw *hw =
2954                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955         struct ixgbe_hw_stats *hw_stats =
2956                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2957         struct ixgbe_macsec_stats *macsec_stats =
2958                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2959                                 dev->data->dev_private);
2960         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2961         unsigned i;
2962
2963         total_missed_rx = 0;
2964         total_qbrc = 0;
2965         total_qprc = 0;
2966         total_qprdc = 0;
2967
2968         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2969                         &total_qbrc, &total_qprc, &total_qprdc);
2970
2971         if (stats == NULL)
2972                 return;
2973
2974         /* Fill out the rte_eth_stats statistics structure */
2975         stats->ipackets = total_qprc;
2976         stats->ibytes = total_qbrc;
2977         stats->opackets = hw_stats->gptc;
2978         stats->obytes = hw_stats->gotc;
2979
2980         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2981                 stats->q_ipackets[i] = hw_stats->qprc[i];
2982                 stats->q_opackets[i] = hw_stats->qptc[i];
2983                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2984                 stats->q_obytes[i] = hw_stats->qbtc[i];
2985                 stats->q_errors[i] = hw_stats->qprdc[i];
2986         }
2987
2988         /* Rx Errors */
2989         stats->imissed  = total_missed_rx;
2990         stats->ierrors  = hw_stats->crcerrs +
2991                           hw_stats->mspdc +
2992                           hw_stats->rlec +
2993                           hw_stats->ruc +
2994                           hw_stats->roc +
2995                           hw_stats->illerrc +
2996                           hw_stats->errbc +
2997                           hw_stats->rfc +
2998                           hw_stats->fccrc +
2999                           hw_stats->fclast;
3000
3001         /* Tx Errors */
3002         stats->oerrors  = 0;
3003 }
3004
3005 static void
3006 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3007 {
3008         struct ixgbe_hw_stats *stats =
3009                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3010
3011         /* HW registers are cleared on read */
3012         ixgbe_dev_stats_get(dev, NULL);
3013
3014         /* Reset software totals */
3015         memset(stats, 0, sizeof(*stats));
3016 }
3017
3018 /* This function calculates the number of xstats based on the current config */
3019 static unsigned
3020 ixgbe_xstats_calc_num(void) {
3021         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3022                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3023                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3024 }
3025
3026 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3027         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3028 {
3029         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3030         unsigned stat, i, count;
3031
3032         if (xstats_names != NULL) {
3033                 count = 0;
3034
3035                 /* Note: limit >= cnt_stats checked upstream
3036                  * in rte_eth_xstats_names()
3037                  */
3038
3039                 /* Extended stats from ixgbe_hw_stats */
3040                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3041                         snprintf(xstats_names[count].name,
3042                                 sizeof(xstats_names[count].name),
3043                                 "%s",
3044                                 rte_ixgbe_stats_strings[i].name);
3045                         count++;
3046                 }
3047
3048                 /* MACsec Stats */
3049                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3050                         snprintf(xstats_names[count].name,
3051                                 sizeof(xstats_names[count].name),
3052                                 "%s",
3053                                 rte_ixgbe_macsec_strings[i].name);
3054                         count++;
3055                 }
3056
3057                 /* RX Priority Stats */
3058                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3059                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3060                                 snprintf(xstats_names[count].name,
3061                                         sizeof(xstats_names[count].name),
3062                                         "rx_priority%u_%s", i,
3063                                         rte_ixgbe_rxq_strings[stat].name);
3064                                 count++;
3065                         }
3066                 }
3067
3068                 /* TX Priority Stats */
3069                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3070                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3071                                 snprintf(xstats_names[count].name,
3072                                         sizeof(xstats_names[count].name),
3073                                         "tx_priority%u_%s", i,
3074                                         rte_ixgbe_txq_strings[stat].name);
3075                                 count++;
3076                         }
3077                 }
3078         }
3079         return cnt_stats;
3080 }
3081
3082 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3083         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3084 {
3085         unsigned i;
3086
3087         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3088                 return -ENOMEM;
3089
3090         if (xstats_names != NULL)
3091                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3092                         snprintf(xstats_names[i].name,
3093                                 sizeof(xstats_names[i].name),
3094                                 "%s", rte_ixgbevf_stats_strings[i].name);
3095         return IXGBEVF_NB_XSTATS;
3096 }
3097
3098 static int
3099 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3100                                          unsigned n)
3101 {
3102         struct ixgbe_hw *hw =
3103                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3104         struct ixgbe_hw_stats *hw_stats =
3105                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3106         struct ixgbe_macsec_stats *macsec_stats =
3107                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3108                                 dev->data->dev_private);
3109         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3110         unsigned i, stat, count = 0;
3111
3112         count = ixgbe_xstats_calc_num();
3113
3114         if (n < count)
3115                 return count;
3116
3117         total_missed_rx = 0;
3118         total_qbrc = 0;
3119         total_qprc = 0;
3120         total_qprdc = 0;
3121
3122         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3123                         &total_qbrc, &total_qprc, &total_qprdc);
3124
3125         /* If this is a reset xstats is NULL, and we have cleared the
3126          * registers by reading them.
3127          */
3128         if (!xstats)
3129                 return 0;
3130
3131         /* Extended stats from ixgbe_hw_stats */
3132         count = 0;
3133         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3134                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3135                                 rte_ixgbe_stats_strings[i].offset);
3136                 xstats[count].id = count;
3137                 count++;
3138         }
3139
3140         /* MACsec Stats */
3141         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3142                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3143                                 rte_ixgbe_macsec_strings[i].offset);
3144                 xstats[count].id = count;
3145                 count++;
3146         }
3147
3148         /* RX Priority Stats */
3149         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3150                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3151                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3152                                         rte_ixgbe_rxq_strings[stat].offset +
3153                                         (sizeof(uint64_t) * i));
3154                         xstats[count].id = count;
3155                         count++;
3156                 }
3157         }
3158
3159         /* TX Priority Stats */
3160         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3161                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3162                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3163                                         rte_ixgbe_txq_strings[stat].offset +
3164                                         (sizeof(uint64_t) * i));
3165                         xstats[count].id = count;
3166                         count++;
3167                 }
3168         }
3169         return count;
3170 }
3171
3172 static void
3173 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3174 {
3175         struct ixgbe_hw_stats *stats =
3176                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3177         struct ixgbe_macsec_stats *macsec_stats =
3178                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3179                                 dev->data->dev_private);
3180
3181         unsigned count = ixgbe_xstats_calc_num();
3182
3183         /* HW registers are cleared on read */
3184         ixgbe_dev_xstats_get(dev, NULL, count);
3185
3186         /* Reset software totals */
3187         memset(stats, 0, sizeof(*stats));
3188         memset(macsec_stats, 0, sizeof(*macsec_stats));
3189 }
3190
3191 static void
3192 ixgbevf_update_stats(struct rte_eth_dev *dev)
3193 {
3194         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3195         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3196                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3197
3198         /* Good Rx packet, include VF loopback */
3199         UPDATE_VF_STAT(IXGBE_VFGPRC,
3200             hw_stats->last_vfgprc, hw_stats->vfgprc);
3201
3202         /* Good Rx octets, include VF loopback */
3203         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3204             hw_stats->last_vfgorc, hw_stats->vfgorc);
3205
3206         /* Good Tx packet, include VF loopback */
3207         UPDATE_VF_STAT(IXGBE_VFGPTC,
3208             hw_stats->last_vfgptc, hw_stats->vfgptc);
3209
3210         /* Good Tx octets, include VF loopback */
3211         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3212             hw_stats->last_vfgotc, hw_stats->vfgotc);
3213
3214         /* Rx Multicst Packet */
3215         UPDATE_VF_STAT(IXGBE_VFMPRC,
3216             hw_stats->last_vfmprc, hw_stats->vfmprc);
3217 }
3218
3219 static int
3220 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3221                        unsigned n)
3222 {
3223         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3224                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3225         unsigned i;
3226
3227         if (n < IXGBEVF_NB_XSTATS)
3228                 return IXGBEVF_NB_XSTATS;
3229
3230         ixgbevf_update_stats(dev);
3231
3232         if (!xstats)
3233                 return 0;
3234
3235         /* Extended stats */
3236         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3237                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3238                         rte_ixgbevf_stats_strings[i].offset);
3239         }
3240
3241         return IXGBEVF_NB_XSTATS;
3242 }
3243
3244 static void
3245 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3246 {
3247         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3248                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3249
3250         ixgbevf_update_stats(dev);
3251
3252         if (stats == NULL)
3253                 return;
3254
3255         stats->ipackets = hw_stats->vfgprc;
3256         stats->ibytes = hw_stats->vfgorc;
3257         stats->opackets = hw_stats->vfgptc;
3258         stats->obytes = hw_stats->vfgotc;
3259 }
3260
3261 static void
3262 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3263 {
3264         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3265                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3266
3267         /* Sync HW register to the last stats */
3268         ixgbevf_dev_stats_get(dev, NULL);
3269
3270         /* reset HW current stats*/
3271         hw_stats->vfgprc = 0;
3272         hw_stats->vfgorc = 0;
3273         hw_stats->vfgptc = 0;
3274         hw_stats->vfgotc = 0;
3275 }
3276
3277 static int
3278 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3279 {
3280         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281         u16 eeprom_verh, eeprom_verl;
3282         u32 etrack_id;
3283         int ret;
3284
3285         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3286         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3287
3288         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3289         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3290
3291         ret += 1; /* add the size of '\0' */
3292         if (fw_size < (u32)ret)
3293                 return ret;
3294         else
3295                 return 0;
3296 }
3297
3298 static void
3299 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3300 {
3301         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3302         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3303         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3304
3305         dev_info->pci_dev = pci_dev;
3306         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3307         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3308         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3309                 /*
3310                  * When DCB/VT is off, maximum number of queues changes,
3311                  * except for 82598EB, which remains constant.
3312                  */
3313                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3314                                 hw->mac.type != ixgbe_mac_82598EB)
3315                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3316         }
3317         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3318         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3319         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3320         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3321         dev_info->max_vfs = pci_dev->max_vfs;
3322         if (hw->mac.type == ixgbe_mac_82598EB)
3323                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3324         else
3325                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3326         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3327         dev_info->rx_offload_capa =
3328                 DEV_RX_OFFLOAD_VLAN_STRIP |
3329                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3330                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3331                 DEV_RX_OFFLOAD_TCP_CKSUM;
3332
3333         /*
3334          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3335          * mode.
3336          */
3337         if ((hw->mac.type == ixgbe_mac_82599EB ||
3338              hw->mac.type == ixgbe_mac_X540) &&
3339             !RTE_ETH_DEV_SRIOV(dev).active)
3340                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3341
3342         if (hw->mac.type == ixgbe_mac_82599EB ||
3343             hw->mac.type == ixgbe_mac_X540)
3344                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3345
3346         if (hw->mac.type == ixgbe_mac_X550 ||
3347             hw->mac.type == ixgbe_mac_X550EM_x ||
3348             hw->mac.type == ixgbe_mac_X550EM_a)
3349                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3350
3351         dev_info->tx_offload_capa =
3352                 DEV_TX_OFFLOAD_VLAN_INSERT |
3353                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3354                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3355                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3356                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3357                 DEV_TX_OFFLOAD_TCP_TSO;
3358
3359         if (hw->mac.type == ixgbe_mac_82599EB ||
3360             hw->mac.type == ixgbe_mac_X540)
3361                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3362
3363         if (hw->mac.type == ixgbe_mac_X550 ||
3364             hw->mac.type == ixgbe_mac_X550EM_x ||
3365             hw->mac.type == ixgbe_mac_X550EM_a)
3366                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3367
3368         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3369                 .rx_thresh = {
3370                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3371                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3372                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3373                 },
3374                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3375                 .rx_drop_en = 0,
3376         };
3377
3378         dev_info->default_txconf = (struct rte_eth_txconf) {
3379                 .tx_thresh = {
3380                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3381                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3382                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3383                 },
3384                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3385                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3386                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3387                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3388         };
3389
3390         dev_info->rx_desc_lim = rx_desc_lim;
3391         dev_info->tx_desc_lim = tx_desc_lim;
3392
3393         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3394         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3395         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3396
3397         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3398         if (hw->mac.type == ixgbe_mac_X540 ||
3399             hw->mac.type == ixgbe_mac_X540_vf ||
3400             hw->mac.type == ixgbe_mac_X550 ||
3401             hw->mac.type == ixgbe_mac_X550_vf) {
3402                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3403         }
3404 }
3405
3406 static const uint32_t *
3407 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3408 {
3409         static const uint32_t ptypes[] = {
3410                 /* For non-vec functions,
3411                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3412                  * for vec functions,
3413                  * refers to _recv_raw_pkts_vec().
3414                  */
3415                 RTE_PTYPE_L2_ETHER,
3416                 RTE_PTYPE_L3_IPV4,
3417                 RTE_PTYPE_L3_IPV4_EXT,
3418                 RTE_PTYPE_L3_IPV6,
3419                 RTE_PTYPE_L3_IPV6_EXT,
3420                 RTE_PTYPE_L4_SCTP,
3421                 RTE_PTYPE_L4_TCP,
3422                 RTE_PTYPE_L4_UDP,
3423                 RTE_PTYPE_TUNNEL_IP,
3424                 RTE_PTYPE_INNER_L3_IPV6,
3425                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3426                 RTE_PTYPE_INNER_L4_TCP,
3427                 RTE_PTYPE_INNER_L4_UDP,
3428                 RTE_PTYPE_UNKNOWN
3429         };
3430
3431         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3432             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3433             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3434             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3435                 return ptypes;
3436         return NULL;
3437 }
3438
3439 static void
3440 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3441                      struct rte_eth_dev_info *dev_info)
3442 {
3443         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3444         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445
3446         dev_info->pci_dev = pci_dev;
3447         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3448         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3449         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3450         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3451         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3452         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3453         dev_info->max_vfs = pci_dev->max_vfs;
3454         if (hw->mac.type == ixgbe_mac_82598EB)
3455                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3456         else
3457                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3458         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3459                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3460                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3461                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3462         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3463                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3464                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3465                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3466                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3467                                 DEV_TX_OFFLOAD_TCP_TSO;
3468
3469         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3470                 .rx_thresh = {
3471                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3472                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3473                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3474                 },
3475                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3476                 .rx_drop_en = 0,
3477         };
3478
3479         dev_info->default_txconf = (struct rte_eth_txconf) {
3480                 .tx_thresh = {
3481                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3482                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3483                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3484                 },
3485                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3486                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3487                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3488                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3489         };
3490
3491         dev_info->rx_desc_lim = rx_desc_lim;
3492         dev_info->tx_desc_lim = tx_desc_lim;
3493 }
3494
3495 /* return 0 means link status changed, -1 means not changed */
3496 static int
3497 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3498 {
3499         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3500         struct rte_eth_link link, old;
3501         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3502         int link_up;
3503         int diag;
3504
3505         link.link_status = ETH_LINK_DOWN;
3506         link.link_speed = 0;
3507         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3508         memset(&old, 0, sizeof(old));
3509         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3510
3511         hw->mac.get_link_status = true;
3512
3513         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3514         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3515                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3516         else
3517                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3518
3519         if (diag != 0) {
3520                 link.link_speed = ETH_SPEED_NUM_100M;
3521                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3522                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3523                 if (link.link_status == old.link_status)
3524                         return -1;
3525                 return 0;
3526         }
3527
3528         if (link_up == 0) {
3529                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3530                 if (link.link_status == old.link_status)
3531                         return -1;
3532                 return 0;
3533         }
3534         link.link_status = ETH_LINK_UP;
3535         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3536
3537         switch (link_speed) {
3538         default:
3539         case IXGBE_LINK_SPEED_UNKNOWN:
3540                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3541                 link.link_speed = ETH_SPEED_NUM_100M;
3542                 break;
3543
3544         case IXGBE_LINK_SPEED_100_FULL:
3545                 link.link_speed = ETH_SPEED_NUM_100M;
3546                 break;
3547
3548         case IXGBE_LINK_SPEED_1GB_FULL:
3549                 link.link_speed = ETH_SPEED_NUM_1G;
3550                 break;
3551
3552         case IXGBE_LINK_SPEED_10GB_FULL:
3553                 link.link_speed = ETH_SPEED_NUM_10G;
3554                 break;
3555         }
3556         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3557
3558         if (link.link_status == old.link_status)
3559                 return -1;
3560
3561         return 0;
3562 }
3563
3564 static void
3565 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3566 {
3567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3568         uint32_t fctrl;
3569
3570         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3571         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3572         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3573 }
3574
3575 static void
3576 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3577 {
3578         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3579         uint32_t fctrl;
3580
3581         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3582         fctrl &= (~IXGBE_FCTRL_UPE);
3583         if (dev->data->all_multicast == 1)
3584                 fctrl |= IXGBE_FCTRL_MPE;
3585         else
3586                 fctrl &= (~IXGBE_FCTRL_MPE);
3587         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3588 }
3589
3590 static void
3591 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3592 {
3593         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3594         uint32_t fctrl;
3595
3596         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3597         fctrl |= IXGBE_FCTRL_MPE;
3598         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3599 }
3600
3601 static void
3602 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3603 {
3604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605         uint32_t fctrl;
3606
3607         if (dev->data->promiscuous == 1)
3608                 return; /* must remain in all_multicast mode */
3609
3610         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3611         fctrl &= (~IXGBE_FCTRL_MPE);
3612         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3613 }
3614
3615 /**
3616  * It clears the interrupt causes and enables the interrupt.
3617  * It will be called once only during nic initialized.
3618  *
3619  * @param dev
3620  *  Pointer to struct rte_eth_dev.
3621  *
3622  * @return
3623  *  - On success, zero.
3624  *  - On failure, a negative value.
3625  */
3626 static int
3627 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3628 {
3629         struct ixgbe_interrupt *intr =
3630                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3631
3632         ixgbe_dev_link_status_print(dev);
3633         intr->mask |= IXGBE_EICR_LSC;
3634
3635         return 0;
3636 }
3637
3638 /**
3639  * It clears the interrupt causes and enables the interrupt.
3640  * It will be called once only during nic initialized.
3641  *
3642  * @param dev
3643  *  Pointer to struct rte_eth_dev.
3644  *
3645  * @return
3646  *  - On success, zero.
3647  *  - On failure, a negative value.
3648  */
3649 static int
3650 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3651 {
3652         struct ixgbe_interrupt *intr =
3653                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3654
3655         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3656
3657         return 0;
3658 }
3659
3660 /**
3661  * It clears the interrupt causes and enables the interrupt.
3662  * It will be called once only during nic initialized.
3663  *
3664  * @param dev
3665  *  Pointer to struct rte_eth_dev.
3666  *
3667  * @return
3668  *  - On success, zero.
3669  *  - On failure, a negative value.
3670  */
3671 static int
3672 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3673 {
3674         struct ixgbe_interrupt *intr =
3675                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3676
3677         intr->mask |= IXGBE_EICR_LINKSEC;
3678
3679         return 0;
3680 }
3681
3682 /*
3683  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3684  *
3685  * @param dev
3686  *  Pointer to struct rte_eth_dev.
3687  *
3688  * @return
3689  *  - On success, zero.
3690  *  - On failure, a negative value.
3691  */
3692 static int
3693 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3694 {
3695         uint32_t eicr;
3696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3697         struct ixgbe_interrupt *intr =
3698                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3699
3700         /* clear all cause mask */
3701         ixgbe_disable_intr(hw);
3702
3703         /* read-on-clear nic registers here */
3704         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3705         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3706
3707         intr->flags = 0;
3708
3709         /* set flag for async link update */
3710         if (eicr & IXGBE_EICR_LSC)
3711                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3712
3713         if (eicr & IXGBE_EICR_MAILBOX)
3714                 intr->flags |= IXGBE_FLAG_MAILBOX;
3715
3716         if (eicr & IXGBE_EICR_LINKSEC)
3717                 intr->flags |= IXGBE_FLAG_MACSEC;
3718
3719         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3720             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3721             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3722                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3723
3724         return 0;
3725 }
3726
3727 /**
3728  * It gets and then prints the link status.
3729  *
3730  * @param dev
3731  *  Pointer to struct rte_eth_dev.
3732  *
3733  * @return
3734  *  - On success, zero.
3735  *  - On failure, a negative value.
3736  */
3737 static void
3738 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3739 {
3740         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3741         struct rte_eth_link link;
3742
3743         memset(&link, 0, sizeof(link));
3744         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3745         if (link.link_status) {
3746                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3747                                         (int)(dev->data->port_id),
3748                                         (unsigned)link.link_speed,
3749                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3750                                         "full-duplex" : "half-duplex");
3751         } else {
3752                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3753                                 (int)(dev->data->port_id));
3754         }
3755         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3756                                 pci_dev->addr.domain,
3757                                 pci_dev->addr.bus,
3758                                 pci_dev->addr.devid,
3759                                 pci_dev->addr.function);
3760 }
3761
3762 /*
3763  * It executes link_update after knowing an interrupt occurred.
3764  *
3765  * @param dev
3766  *  Pointer to struct rte_eth_dev.
3767  *
3768  * @return
3769  *  - On success, zero.
3770  *  - On failure, a negative value.
3771  */
3772 static int
3773 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3774                            struct rte_intr_handle *intr_handle)
3775 {
3776         struct ixgbe_interrupt *intr =
3777                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3778         int64_t timeout;
3779         struct rte_eth_link link;
3780         int intr_enable_delay = false;
3781         struct ixgbe_hw *hw =
3782                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783
3784         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3785
3786         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3787                 ixgbe_pf_mbx_process(dev);
3788                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3789         }
3790
3791         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3792                 ixgbe_handle_lasi(hw);
3793                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3794         }
3795
3796         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3797                 /* get the link status before link update, for predicting later */
3798                 memset(&link, 0, sizeof(link));
3799                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3800
3801                 ixgbe_dev_link_update(dev, 0);
3802
3803                 /* likely to up */
3804                 if (!link.link_status)
3805                         /* handle it 1 sec later, wait it being stable */
3806                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3807                 /* likely to down */
3808                 else
3809                         /* handle it 4 sec later, wait it being stable */
3810                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3811
3812                 ixgbe_dev_link_status_print(dev);
3813
3814                 intr_enable_delay = true;
3815         }
3816
3817         if (intr_enable_delay) {
3818                 if (rte_eal_alarm_set(timeout * 1000,
3819                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3820                         PMD_DRV_LOG(ERR, "Error setting alarm");
3821         } else {
3822                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3823                 ixgbe_enable_intr(dev);
3824                 rte_intr_enable(intr_handle);
3825         }
3826
3827
3828         return 0;
3829 }
3830
3831 /**
3832  * Interrupt handler which shall be registered for alarm callback for delayed
3833  * handling specific interrupt to wait for the stable nic state. As the
3834  * NIC interrupt state is not stable for ixgbe after link is just down,
3835  * it needs to wait 4 seconds to get the stable status.
3836  *
3837  * @param handle
3838  *  Pointer to interrupt handle.
3839  * @param param
3840  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3841  *
3842  * @return
3843  *  void
3844  */
3845 static void
3846 ixgbe_dev_interrupt_delayed_handler(void *param)
3847 {
3848         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3849         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3850         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3851         struct ixgbe_interrupt *intr =
3852                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3853         struct ixgbe_hw *hw =
3854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3855         uint32_t eicr;
3856
3857         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3858         if (eicr & IXGBE_EICR_MAILBOX)
3859                 ixgbe_pf_mbx_process(dev);
3860
3861         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3862                 ixgbe_handle_lasi(hw);
3863                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3864         }
3865
3866         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3867                 ixgbe_dev_link_update(dev, 0);
3868                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3869                 ixgbe_dev_link_status_print(dev);
3870                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3871         }
3872
3873         if (intr->flags & IXGBE_FLAG_MACSEC) {
3874                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3875                                               NULL);
3876                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3877         }
3878
3879         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3880         ixgbe_enable_intr(dev);
3881         rte_intr_enable(intr_handle);
3882 }
3883
3884 /**
3885  * Interrupt handler triggered by NIC  for handling
3886  * specific interrupt.
3887  *
3888  * @param handle
3889  *  Pointer to interrupt handle.
3890  * @param param
3891  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3892  *
3893  * @return
3894  *  void
3895  */
3896 static void
3897 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3898                             void *param)
3899 {
3900         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3901
3902         ixgbe_dev_interrupt_get_status(dev);
3903         ixgbe_dev_interrupt_action(dev, handle);
3904 }
3905
3906 static int
3907 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3908 {
3909         struct ixgbe_hw *hw;
3910
3911         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3912         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3913 }
3914
3915 static int
3916 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3917 {
3918         struct ixgbe_hw *hw;
3919
3920         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3922 }
3923
3924 static int
3925 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3926 {
3927         struct ixgbe_hw *hw;
3928         uint32_t mflcn_reg;
3929         uint32_t fccfg_reg;
3930         int rx_pause;
3931         int tx_pause;
3932
3933         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3934
3935         fc_conf->pause_time = hw->fc.pause_time;
3936         fc_conf->high_water = hw->fc.high_water[0];
3937         fc_conf->low_water = hw->fc.low_water[0];
3938         fc_conf->send_xon = hw->fc.send_xon;
3939         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3940
3941         /*
3942          * Return rx_pause status according to actual setting of
3943          * MFLCN register.
3944          */
3945         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3946         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3947                 rx_pause = 1;
3948         else
3949                 rx_pause = 0;
3950
3951         /*
3952          * Return tx_pause status according to actual setting of
3953          * FCCFG register.
3954          */
3955         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3956         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3957                 tx_pause = 1;
3958         else
3959                 tx_pause = 0;
3960
3961         if (rx_pause && tx_pause)
3962                 fc_conf->mode = RTE_FC_FULL;
3963         else if (rx_pause)
3964                 fc_conf->mode = RTE_FC_RX_PAUSE;
3965         else if (tx_pause)
3966                 fc_conf->mode = RTE_FC_TX_PAUSE;
3967         else
3968                 fc_conf->mode = RTE_FC_NONE;
3969
3970         return 0;
3971 }
3972
3973 static int
3974 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3975 {
3976         struct ixgbe_hw *hw;
3977         int err;
3978         uint32_t rx_buf_size;
3979         uint32_t max_high_water;
3980         uint32_t mflcn;
3981         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3982                 ixgbe_fc_none,
3983                 ixgbe_fc_rx_pause,
3984                 ixgbe_fc_tx_pause,
3985                 ixgbe_fc_full
3986         };
3987
3988         PMD_INIT_FUNC_TRACE();
3989
3990         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3991         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3992         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3993
3994         /*
3995          * At least reserve one Ethernet frame for watermark
3996          * high_water/low_water in kilo bytes for ixgbe
3997          */
3998         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3999         if ((fc_conf->high_water > max_high_water) ||
4000                 (fc_conf->high_water < fc_conf->low_water)) {
4001                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4002                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4003                 return -EINVAL;
4004         }
4005
4006         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4007         hw->fc.pause_time     = fc_conf->pause_time;
4008         hw->fc.high_water[0]  = fc_conf->high_water;
4009         hw->fc.low_water[0]   = fc_conf->low_water;
4010         hw->fc.send_xon       = fc_conf->send_xon;
4011         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4012
4013         err = ixgbe_fc_enable(hw);
4014
4015         /* Not negotiated is not an error case */
4016         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4017
4018                 /* check if we want to forward MAC frames - driver doesn't have native
4019                  * capability to do that, so we'll write the registers ourselves */
4020
4021                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4022
4023                 /* set or clear MFLCN.PMCF bit depending on configuration */
4024                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4025                         mflcn |= IXGBE_MFLCN_PMCF;
4026                 else
4027                         mflcn &= ~IXGBE_MFLCN_PMCF;
4028
4029                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4030                 IXGBE_WRITE_FLUSH(hw);
4031
4032                 return 0;
4033         }
4034
4035         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4036         return -EIO;
4037 }
4038
4039 /**
4040  *  ixgbe_pfc_enable_generic - Enable flow control
4041  *  @hw: pointer to hardware structure
4042  *  @tc_num: traffic class number
4043  *  Enable flow control according to the current settings.
4044  */
4045 static int
4046 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4047 {
4048         int ret_val = 0;
4049         uint32_t mflcn_reg, fccfg_reg;
4050         uint32_t reg;
4051         uint32_t fcrtl, fcrth;
4052         uint8_t i;
4053         uint8_t nb_rx_en;
4054
4055         /* Validate the water mark configuration */
4056         if (!hw->fc.pause_time) {
4057                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4058                 goto out;
4059         }
4060
4061         /* Low water mark of zero causes XOFF floods */
4062         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4063                  /* High/Low water can not be 0 */
4064                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4065                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4066                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4067                         goto out;
4068                 }
4069
4070                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4071                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4072                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4073                         goto out;
4074                 }
4075         }
4076         /* Negotiate the fc mode to use */
4077         ixgbe_fc_autoneg(hw);
4078
4079         /* Disable any previous flow control settings */
4080         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4081         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4082
4083         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4084         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4085
4086         switch (hw->fc.current_mode) {
4087         case ixgbe_fc_none:
4088                 /*
4089                  * If the count of enabled RX Priority Flow control >1,
4090                  * and the TX pause can not be disabled
4091                  */
4092                 nb_rx_en = 0;
4093                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4094                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4095                         if (reg & IXGBE_FCRTH_FCEN)
4096                                 nb_rx_en++;
4097                 }
4098                 if (nb_rx_en > 1)
4099                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4100                 break;
4101         case ixgbe_fc_rx_pause:
4102                 /*
4103                  * Rx Flow control is enabled and Tx Flow control is
4104                  * disabled by software override. Since there really
4105                  * isn't a way to advertise that we are capable of RX
4106                  * Pause ONLY, we will advertise that we support both
4107                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4108                  * disable the adapter's ability to send PAUSE frames.
4109                  */
4110                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4111                 /*
4112                  * If the count of enabled RX Priority Flow control >1,
4113                  * and the TX pause can not be disabled
4114                  */
4115                 nb_rx_en = 0;
4116                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4117                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4118                         if (reg & IXGBE_FCRTH_FCEN)
4119                                 nb_rx_en++;
4120                 }
4121                 if (nb_rx_en > 1)
4122                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4123                 break;
4124         case ixgbe_fc_tx_pause:
4125                 /*
4126                  * Tx Flow control is enabled, and Rx Flow control is
4127                  * disabled by software override.
4128                  */
4129                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4130                 break;
4131         case ixgbe_fc_full:
4132                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4133                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4134                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4135                 break;
4136         default:
4137                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4138                 ret_val = IXGBE_ERR_CONFIG;
4139                 goto out;
4140         }
4141
4142         /* Set 802.3x based flow control settings. */
4143         mflcn_reg |= IXGBE_MFLCN_DPF;
4144         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4145         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4146
4147         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4148         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4149                 hw->fc.high_water[tc_num]) {
4150                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4151                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4152                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4153         } else {
4154                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4155                 /*
4156                  * In order to prevent Tx hangs when the internal Tx
4157                  * switch is enabled we must set the high water mark
4158                  * to the maximum FCRTH value.  This allows the Tx
4159                  * switch to function even under heavy Rx workloads.
4160                  */
4161                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4162         }
4163         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4164
4165         /* Configure pause time (2 TCs per register) */
4166         reg = hw->fc.pause_time * 0x00010001;
4167         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4168                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4169
4170         /* Configure flow control refresh threshold value */
4171         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4172
4173 out:
4174         return ret_val;
4175 }
4176
4177 static int
4178 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4179 {
4180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4181         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4182
4183         if (hw->mac.type != ixgbe_mac_82598EB) {
4184                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4185         }
4186         return ret_val;
4187 }
4188
4189 static int
4190 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4191 {
4192         int err;
4193         uint32_t rx_buf_size;
4194         uint32_t max_high_water;
4195         uint8_t tc_num;
4196         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4197         struct ixgbe_hw *hw =
4198                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199         struct ixgbe_dcb_config *dcb_config =
4200                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4201
4202         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4203                 ixgbe_fc_none,
4204                 ixgbe_fc_rx_pause,
4205                 ixgbe_fc_tx_pause,
4206                 ixgbe_fc_full
4207         };
4208
4209         PMD_INIT_FUNC_TRACE();
4210
4211         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4212         tc_num = map[pfc_conf->priority];
4213         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4214         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4215         /*
4216          * At least reserve one Ethernet frame for watermark
4217          * high_water/low_water in kilo bytes for ixgbe
4218          */
4219         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4220         if ((pfc_conf->fc.high_water > max_high_water) ||
4221             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4222                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4223                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4224                 return -EINVAL;
4225         }
4226
4227         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4228         hw->fc.pause_time = pfc_conf->fc.pause_time;
4229         hw->fc.send_xon = pfc_conf->fc.send_xon;
4230         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4231         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4232
4233         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4234
4235         /* Not negotiated is not an error case */
4236         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4237                 return 0;
4238
4239         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4240         return -EIO;
4241 }
4242
4243 static int
4244 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4245                           struct rte_eth_rss_reta_entry64 *reta_conf,
4246                           uint16_t reta_size)
4247 {
4248         uint16_t i, sp_reta_size;
4249         uint8_t j, mask;
4250         uint32_t reta, r;
4251         uint16_t idx, shift;
4252         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4253         uint32_t reta_reg;
4254
4255         PMD_INIT_FUNC_TRACE();
4256
4257         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4258                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4259                         "NIC.");
4260                 return -ENOTSUP;
4261         }
4262
4263         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4264         if (reta_size != sp_reta_size) {
4265                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4266                         "(%d) doesn't match the number hardware can supported "
4267                         "(%d)\n", reta_size, sp_reta_size);
4268                 return -EINVAL;
4269         }
4270
4271         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4272                 idx = i / RTE_RETA_GROUP_SIZE;
4273                 shift = i % RTE_RETA_GROUP_SIZE;
4274                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4275                                                 IXGBE_4_BIT_MASK);
4276                 if (!mask)
4277                         continue;
4278                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4279                 if (mask == IXGBE_4_BIT_MASK)
4280                         r = 0;
4281                 else
4282                         r = IXGBE_READ_REG(hw, reta_reg);
4283                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4284                         if (mask & (0x1 << j))
4285                                 reta |= reta_conf[idx].reta[shift + j] <<
4286                                                         (CHAR_BIT * j);
4287                         else
4288                                 reta |= r & (IXGBE_8_BIT_MASK <<
4289                                                 (CHAR_BIT * j));
4290                 }
4291                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4292         }
4293
4294         return 0;
4295 }
4296
4297 static int
4298 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4299                          struct rte_eth_rss_reta_entry64 *reta_conf,
4300                          uint16_t reta_size)
4301 {
4302         uint16_t i, sp_reta_size;
4303         uint8_t j, mask;
4304         uint32_t reta;
4305         uint16_t idx, shift;
4306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4307         uint32_t reta_reg;
4308
4309         PMD_INIT_FUNC_TRACE();
4310         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4311         if (reta_size != sp_reta_size) {
4312                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4313                         "(%d) doesn't match the number hardware can supported "
4314                         "(%d)\n", reta_size, sp_reta_size);
4315                 return -EINVAL;
4316         }
4317
4318         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4319                 idx = i / RTE_RETA_GROUP_SIZE;
4320                 shift = i % RTE_RETA_GROUP_SIZE;
4321                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4322                                                 IXGBE_4_BIT_MASK);
4323                 if (!mask)
4324                         continue;
4325
4326                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4327                 reta = IXGBE_READ_REG(hw, reta_reg);
4328                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4329                         if (mask & (0x1 << j))
4330                                 reta_conf[idx].reta[shift + j] =
4331                                         ((reta >> (CHAR_BIT * j)) &
4332                                                 IXGBE_8_BIT_MASK);
4333                 }
4334         }
4335
4336         return 0;
4337 }
4338
4339 static void
4340 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4341                                 uint32_t index, uint32_t pool)
4342 {
4343         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4344         uint32_t enable_addr = 1;
4345
4346         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4347 }
4348
4349 static void
4350 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4351 {
4352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4353
4354         ixgbe_clear_rar(hw, index);
4355 }
4356
4357 static void
4358 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4359 {
4360         ixgbe_remove_rar(dev, 0);
4361
4362         ixgbe_add_rar(dev, addr, 0, 0);
4363 }
4364
4365 static int
4366 is_ixgbe_pmd(const char *driver_name)
4367 {
4368         if (!strstr(driver_name, "ixgbe"))
4369                 return -ENOTSUP;
4370
4371         if (strstr(driver_name, "ixgbe_vf"))
4372                 return -ENOTSUP;
4373
4374         return 0;
4375 }
4376
4377 int
4378 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4379                 struct ether_addr *mac_addr)
4380 {
4381         struct ixgbe_hw *hw;
4382         struct ixgbe_vf_info *vfinfo;
4383         int rar_entry;
4384         uint8_t *new_mac = (uint8_t *)(mac_addr);
4385         struct rte_eth_dev *dev;
4386         struct rte_eth_dev_info dev_info;
4387
4388         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4389
4390         dev = &rte_eth_devices[port];
4391         rte_eth_dev_info_get(port, &dev_info);
4392
4393         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4394                 return -ENOTSUP;
4395
4396         if (vf >= dev_info.max_vfs)
4397                 return -EINVAL;
4398
4399         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4400         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4401         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4402
4403         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4404                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4405                                 ETHER_ADDR_LEN);
4406                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4407                                 IXGBE_RAH_AV);
4408         }
4409         return -EINVAL;
4410 }
4411
4412 static int
4413 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4414 {
4415         uint32_t hlreg0;
4416         uint32_t maxfrs;
4417         struct ixgbe_hw *hw;
4418         struct rte_eth_dev_info dev_info;
4419         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4420
4421         ixgbe_dev_info_get(dev, &dev_info);
4422
4423         /* check that mtu is within the allowed range */
4424         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4425                 return -EINVAL;
4426
4427         /* refuse mtu that requires the support of scattered packets when this
4428          * feature has not been enabled before.
4429          */
4430         if (!dev->data->scattered_rx &&
4431             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4432              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4433                 return -EINVAL;
4434
4435         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4436         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4437
4438         /* switch to jumbo mode if needed */
4439         if (frame_size > ETHER_MAX_LEN) {
4440                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4441                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4442         } else {
4443                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4444                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4445         }
4446         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4447
4448         /* update max frame size */
4449         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4450
4451         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4452         maxfrs &= 0x0000FFFF;
4453         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4454         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4455
4456         return 0;
4457 }
4458
4459 /*
4460  * Virtual Function operations
4461  */
4462 static void
4463 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4464 {
4465         PMD_INIT_FUNC_TRACE();
4466
4467         /* Clear interrupt mask to stop from interrupts being generated */
4468         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4469
4470         IXGBE_WRITE_FLUSH(hw);
4471 }
4472
4473 static void
4474 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4475 {
4476         PMD_INIT_FUNC_TRACE();
4477
4478         /* VF enable interrupt autoclean */
4479         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4480         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4481         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4482
4483         IXGBE_WRITE_FLUSH(hw);
4484 }
4485
4486 static int
4487 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4488 {
4489         struct rte_eth_conf *conf = &dev->data->dev_conf;
4490         struct ixgbe_adapter *adapter =
4491                         (struct ixgbe_adapter *)dev->data->dev_private;
4492
4493         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4494                      dev->data->port_id);
4495
4496         /*
4497          * VF has no ability to enable/disable HW CRC
4498          * Keep the persistent behavior the same as Host PF
4499          */
4500 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4501         if (!conf->rxmode.hw_strip_crc) {
4502                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4503                 conf->rxmode.hw_strip_crc = 1;
4504         }
4505 #else
4506         if (conf->rxmode.hw_strip_crc) {
4507                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4508                 conf->rxmode.hw_strip_crc = 0;
4509         }
4510 #endif
4511
4512         /*
4513          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4514          * allocation or vector Rx preconditions we will reset it.
4515          */
4516         adapter->rx_bulk_alloc_allowed = true;
4517         adapter->rx_vec_allowed = true;
4518
4519         return 0;
4520 }
4521
4522 static int
4523 ixgbevf_dev_start(struct rte_eth_dev *dev)
4524 {
4525         struct ixgbe_hw *hw =
4526                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527         uint32_t intr_vector = 0;
4528         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4529         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4530
4531         int err, mask = 0;
4532
4533         PMD_INIT_FUNC_TRACE();
4534
4535         hw->mac.ops.reset_hw(hw);
4536         hw->mac.get_link_status = true;
4537
4538         /* negotiate mailbox API version to use with the PF. */
4539         ixgbevf_negotiate_api(hw);
4540
4541         ixgbevf_dev_tx_init(dev);
4542
4543         /* This can fail when allocating mbufs for descriptor rings */
4544         err = ixgbevf_dev_rx_init(dev);
4545         if (err) {
4546                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4547                 ixgbe_dev_clear_queues(dev);
4548                 return err;
4549         }
4550
4551         /* Set vfta */
4552         ixgbevf_set_vfta_all(dev, 1);
4553
4554         /* Set HW strip */
4555         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4556                 ETH_VLAN_EXTEND_MASK;
4557         ixgbevf_vlan_offload_set(dev, mask);
4558
4559         ixgbevf_dev_rxtx_start(dev);
4560
4561         /* check and configure queue intr-vector mapping */
4562         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4563                 intr_vector = dev->data->nb_rx_queues;
4564                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4565                         return -1;
4566         }
4567
4568         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4569                 intr_handle->intr_vec =
4570                         rte_zmalloc("intr_vec",
4571                                     dev->data->nb_rx_queues * sizeof(int), 0);
4572                 if (intr_handle->intr_vec == NULL) {
4573                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4574                                      " intr_vec\n", dev->data->nb_rx_queues);
4575                         return -ENOMEM;
4576                 }
4577         }
4578         ixgbevf_configure_msix(dev);
4579
4580         rte_intr_enable(intr_handle);
4581
4582         /* Re-enable interrupt for VF */
4583         ixgbevf_intr_enable(hw);
4584
4585         return 0;
4586 }
4587
4588 static void
4589 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4590 {
4591         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4592         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4593         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4594
4595         PMD_INIT_FUNC_TRACE();
4596
4597         ixgbevf_intr_disable(hw);
4598
4599         hw->adapter_stopped = 1;
4600         ixgbe_stop_adapter(hw);
4601
4602         /*
4603           * Clear what we set, but we still keep shadow_vfta to
4604           * restore after device starts
4605           */
4606         ixgbevf_set_vfta_all(dev, 0);
4607
4608         /* Clear stored conf */
4609         dev->data->scattered_rx = 0;
4610
4611         ixgbe_dev_clear_queues(dev);
4612
4613         /* Clean datapath event and queue/vec mapping */
4614         rte_intr_efd_disable(intr_handle);
4615         if (intr_handle->intr_vec != NULL) {
4616                 rte_free(intr_handle->intr_vec);
4617                 intr_handle->intr_vec = NULL;
4618         }
4619 }
4620
4621 static void
4622 ixgbevf_dev_close(struct rte_eth_dev *dev)
4623 {
4624         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4625
4626         PMD_INIT_FUNC_TRACE();
4627
4628         ixgbe_reset_hw(hw);
4629
4630         ixgbevf_dev_stop(dev);
4631
4632         ixgbe_dev_free_queues(dev);
4633
4634         /**
4635          * Remove the VF MAC address ro ensure
4636          * that the VF traffic goes to the PF
4637          * after stop, close and detach of the VF
4638          **/
4639         ixgbevf_remove_mac_addr(dev, 0);
4640 }
4641
4642 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4643 {
4644         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4645         struct ixgbe_vfta *shadow_vfta =
4646                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4647         int i = 0, j = 0, vfta = 0, mask = 1;
4648
4649         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4650                 vfta = shadow_vfta->vfta[i];
4651                 if (vfta) {
4652                         mask = 1;
4653                         for (j = 0; j < 32; j++) {
4654                                 if (vfta & mask)
4655                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4656                                                        on, false);
4657                                 mask <<= 1;
4658                         }
4659                 }
4660         }
4661
4662 }
4663
4664 static int
4665 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4666 {
4667         struct ixgbe_hw *hw =
4668                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4669         struct ixgbe_vfta *shadow_vfta =
4670                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4671         uint32_t vid_idx = 0;
4672         uint32_t vid_bit = 0;
4673         int ret = 0;
4674
4675         PMD_INIT_FUNC_TRACE();
4676
4677         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4678         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4679         if (ret) {
4680                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4681                 return ret;
4682         }
4683         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4684         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4685
4686         /* Save what we set and retore it after device reset */
4687         if (on)
4688                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4689         else
4690                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4691
4692         return 0;
4693 }
4694
4695 static void
4696 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4697 {
4698         struct ixgbe_hw *hw =
4699                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700         uint32_t ctrl;
4701
4702         PMD_INIT_FUNC_TRACE();
4703
4704         if (queue >= hw->mac.max_rx_queues)
4705                 return;
4706
4707         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4708         if (on)
4709                 ctrl |= IXGBE_RXDCTL_VME;
4710         else
4711                 ctrl &= ~IXGBE_RXDCTL_VME;
4712         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4713
4714         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4715 }
4716
4717 static void
4718 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4719 {
4720         struct ixgbe_hw *hw =
4721                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4722         uint16_t i;
4723         int on = 0;
4724
4725         /* VF function only support hw strip feature, others are not support */
4726         if (mask & ETH_VLAN_STRIP_MASK) {
4727                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4728
4729                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4730                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4731         }
4732 }
4733
4734 static int
4735 ixgbe_vt_check(struct ixgbe_hw *hw)
4736 {
4737         uint32_t reg_val;
4738
4739         /* if Virtualization Technology is enabled */
4740         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4741         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4742                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4743                 return -1;
4744         }
4745
4746         return 0;
4747 }
4748
4749 static uint32_t
4750 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4751 {
4752         uint32_t vector = 0;
4753
4754         switch (hw->mac.mc_filter_type) {
4755         case 0:   /* use bits [47:36] of the address */
4756                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4757                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4758                 break;
4759         case 1:   /* use bits [46:35] of the address */
4760                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4761                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4762                 break;
4763         case 2:   /* use bits [45:34] of the address */
4764                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4765                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4766                 break;
4767         case 3:   /* use bits [43:32] of the address */
4768                 vector = ((uc_addr->addr_bytes[4]) |
4769                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4770                 break;
4771         default:  /* Invalid mc_filter_type */
4772                 break;
4773         }
4774
4775         /* vector can only be 12-bits or boundary will be exceeded */
4776         vector &= 0xFFF;
4777         return vector;
4778 }
4779
4780 static int
4781 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4782                         uint8_t on)
4783 {
4784         uint32_t vector;
4785         uint32_t uta_idx;
4786         uint32_t reg_val;
4787         uint32_t uta_shift;
4788         uint32_t rc;
4789         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4790         const uint32_t ixgbe_uta_bit_shift = 5;
4791         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4792         const uint32_t bit1 = 0x1;
4793
4794         struct ixgbe_hw *hw =
4795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4796         struct ixgbe_uta_info *uta_info =
4797                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4798
4799         /* The UTA table only exists on 82599 hardware and newer */
4800         if (hw->mac.type < ixgbe_mac_82599EB)
4801                 return -ENOTSUP;
4802
4803         vector = ixgbe_uta_vector(hw, mac_addr);
4804         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4805         uta_shift = vector & ixgbe_uta_bit_mask;
4806
4807         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4808         if (rc == on)
4809                 return 0;
4810
4811         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4812         if (on) {
4813                 uta_info->uta_in_use++;
4814                 reg_val |= (bit1 << uta_shift);
4815                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4816         } else {
4817                 uta_info->uta_in_use--;
4818                 reg_val &= ~(bit1 << uta_shift);
4819                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4820         }
4821
4822         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4823
4824         if (uta_info->uta_in_use > 0)
4825                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4826                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4827         else
4828                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4829
4830         return 0;
4831 }
4832
4833 static int
4834 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4835 {
4836         int i;
4837         struct ixgbe_hw *hw =
4838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839         struct ixgbe_uta_info *uta_info =
4840                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4841
4842         /* The UTA table only exists on 82599 hardware and newer */
4843         if (hw->mac.type < ixgbe_mac_82599EB)
4844                 return -ENOTSUP;
4845
4846         if (on) {
4847                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4848                         uta_info->uta_shadow[i] = ~0;
4849                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4850                 }
4851         } else {
4852                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4853                         uta_info->uta_shadow[i] = 0;
4854                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4855                 }
4856         }
4857         return 0;
4858
4859 }
4860
4861 uint32_t
4862 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4863 {
4864         uint32_t new_val = orig_val;
4865
4866         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4867                 new_val |= IXGBE_VMOLR_AUPE;
4868         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4869                 new_val |= IXGBE_VMOLR_ROMPE;
4870         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4871                 new_val |= IXGBE_VMOLR_ROPE;
4872         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4873                 new_val |= IXGBE_VMOLR_BAM;
4874         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4875                 new_val |= IXGBE_VMOLR_MPE;
4876
4877         return new_val;
4878 }
4879
4880
4881 int
4882 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4883 {
4884         struct ixgbe_hw *hw;
4885         struct ixgbe_mac_info *mac;
4886         struct rte_eth_dev *dev;
4887         struct rte_eth_dev_info dev_info;
4888
4889         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4890
4891         dev = &rte_eth_devices[port];
4892         rte_eth_dev_info_get(port, &dev_info);
4893
4894         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4895                 return -ENOTSUP;
4896
4897         if (vf >= dev_info.max_vfs)
4898                 return -EINVAL;
4899
4900         if (on > 1)
4901                 return -EINVAL;
4902
4903         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4904         mac = &hw->mac;
4905
4906         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4907
4908         return 0;
4909 }
4910
4911 int
4912 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4913 {
4914         struct ixgbe_hw *hw;
4915         struct ixgbe_mac_info *mac;
4916         struct rte_eth_dev *dev;
4917         struct rte_eth_dev_info dev_info;
4918
4919         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4920
4921         dev = &rte_eth_devices[port];
4922         rte_eth_dev_info_get(port, &dev_info);
4923
4924         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4925                 return -ENOTSUP;
4926
4927         if (vf >= dev_info.max_vfs)
4928                 return -EINVAL;
4929
4930         if (on > 1)
4931                 return -EINVAL;
4932
4933         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4934         mac = &hw->mac;
4935         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4936
4937         return 0;
4938 }
4939
4940 int
4941 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4942 {
4943         struct ixgbe_hw *hw;
4944         uint32_t ctrl;
4945         struct rte_eth_dev *dev;
4946         struct rte_eth_dev_info dev_info;
4947
4948         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4949
4950         dev = &rte_eth_devices[port];
4951         rte_eth_dev_info_get(port, &dev_info);
4952
4953         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4954                 return -ENOTSUP;
4955
4956         if (vf >= dev_info.max_vfs)
4957                 return -EINVAL;
4958
4959         if (vlan_id > ETHER_MAX_VLAN_ID)
4960                 return -EINVAL;
4961
4962         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4963         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4964         if (vlan_id) {
4965                 ctrl = vlan_id;
4966                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4967         } else {
4968                 ctrl = 0;
4969         }
4970
4971         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4972
4973         return 0;
4974 }
4975
4976 int
4977 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4978 {
4979         struct ixgbe_hw *hw;
4980         uint32_t ctrl;
4981         struct rte_eth_dev *dev;
4982         struct rte_eth_dev_info dev_info;
4983
4984         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4985
4986         dev = &rte_eth_devices[port];
4987         rte_eth_dev_info_get(port, &dev_info);
4988
4989         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4990                 return -ENOTSUP;
4991
4992         if (on > 1)
4993                 return -EINVAL;
4994
4995         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4996         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4997         /* enable or disable VMDQ loopback */
4998         if (on)
4999                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5000         else
5001                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5002
5003         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5004
5005         return 0;
5006 }
5007
5008 int
5009 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5010 {
5011         struct ixgbe_hw *hw;
5012         uint32_t reg_value;
5013         int i;
5014         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5015         struct rte_eth_dev *dev;
5016         struct rte_eth_dev_info dev_info;
5017
5018         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5019
5020         dev = &rte_eth_devices[port];
5021         rte_eth_dev_info_get(port, &dev_info);
5022
5023         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5024                 return -ENOTSUP;
5025
5026         if (on > 1)
5027                 return -EINVAL;
5028
5029         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5030         for (i = 0; i <= num_queues; i++) {
5031                 reg_value = IXGBE_QDE_WRITE |
5032                                 (i << IXGBE_QDE_IDX_SHIFT) |
5033                                 (on & IXGBE_QDE_ENABLE);
5034                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5035         }
5036
5037         return 0;
5038 }
5039
5040 int
5041 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5042 {
5043         struct ixgbe_hw *hw;
5044         uint32_t reg_value;
5045         struct rte_eth_dev *dev;
5046         struct rte_eth_dev_info dev_info;
5047
5048         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5049
5050         dev = &rte_eth_devices[port];
5051         rte_eth_dev_info_get(port, &dev_info);
5052
5053         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5054                 return -ENOTSUP;
5055
5056         /* only support VF's 0 to 63 */
5057         if ((vf >= dev_info.max_vfs) || (vf > 63))
5058                 return -EINVAL;
5059
5060         if (on > 1)
5061                 return -EINVAL;
5062
5063         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5064         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5065         if (on)
5066                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5067         else
5068                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5069
5070         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5071
5072         return 0;
5073 }
5074
5075 int
5076 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5077 {
5078         struct rte_eth_dev *dev;
5079         struct rte_eth_dev_info dev_info;
5080         uint16_t queues_per_pool;
5081         uint32_t q;
5082
5083         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5084
5085         dev = &rte_eth_devices[port];
5086         rte_eth_dev_info_get(port, &dev_info);
5087
5088         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5089                 return -ENOTSUP;
5090
5091         if (vf >= dev_info.max_vfs)
5092                 return -EINVAL;
5093
5094         if (on > 1)
5095                 return -EINVAL;
5096
5097         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5098
5099         /* The PF has 128 queue pairs and in SRIOV configuration
5100          * those queues will be assigned to VF's, so RXDCTL
5101          * registers will be dealing with queues which will be
5102          * assigned to VF's.
5103          * Let's say we have SRIOV configured with 31 VF's then the
5104          * first 124 queues 0-123 will be allocated to VF's and only
5105          * the last 4 queues 123-127 will be assigned to the PF.
5106          */
5107
5108         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5109
5110         for (q = 0; q < queues_per_pool; q++)
5111                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5112                                 q + vf * queues_per_pool, on);
5113         return 0;
5114 }
5115
5116 int
5117 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5118 {
5119         int val = 0;
5120         struct rte_eth_dev *dev;
5121         struct rte_eth_dev_info dev_info;
5122         struct ixgbe_hw *hw;
5123         uint32_t vmolr;
5124
5125         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5126
5127         dev = &rte_eth_devices[port];
5128         rte_eth_dev_info_get(port, &dev_info);
5129
5130         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5131                 return -ENOTSUP;
5132
5133         if (vf >= dev_info.max_vfs)
5134                 return -EINVAL;
5135
5136         if (on > 1)
5137                 return -EINVAL;
5138
5139         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5141
5142         if (hw->mac.type == ixgbe_mac_82598EB) {
5143                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5144                              " on 82599 hardware and newer");
5145                 return -ENOTSUP;
5146         }
5147         if (ixgbe_vt_check(hw) < 0)
5148                 return -ENOTSUP;
5149
5150         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5151
5152         if (on)
5153                 vmolr |= val;
5154         else
5155                 vmolr &= ~val;
5156
5157         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5158
5159         return 0;
5160 }
5161
5162 int
5163 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5164 {
5165         struct rte_eth_dev *dev;
5166         struct rte_eth_dev_info dev_info;
5167         uint32_t reg, addr;
5168         uint32_t val;
5169         const uint8_t bit1 = 0x1;
5170         struct ixgbe_hw *hw;
5171
5172         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5173
5174         dev = &rte_eth_devices[port];
5175         rte_eth_dev_info_get(port, &dev_info);
5176
5177         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5178                 return -ENOTSUP;
5179
5180         if (vf >= dev_info.max_vfs)
5181                 return -EINVAL;
5182
5183         if (on > 1)
5184                 return -EINVAL;
5185
5186         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5187
5188         if (ixgbe_vt_check(hw) < 0)
5189                 return -ENOTSUP;
5190
5191         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5192         if (vf >= 32) {
5193                 addr = IXGBE_VFRE(1);
5194                 val = bit1 << (vf - 32);
5195         } else {
5196                 addr = IXGBE_VFRE(0);
5197                 val = bit1 << vf;
5198         }
5199
5200         reg = IXGBE_READ_REG(hw, addr);
5201
5202         if (on)
5203                 reg |= val;
5204         else
5205                 reg &= ~val;
5206
5207         IXGBE_WRITE_REG(hw, addr, reg);
5208
5209         return 0;
5210 }
5211
5212 int
5213 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5214 {
5215         struct rte_eth_dev *dev;
5216         struct rte_eth_dev_info dev_info;
5217         uint32_t reg, addr;
5218         uint32_t val;
5219         const uint8_t bit1 = 0x1;
5220
5221         struct ixgbe_hw *hw;
5222
5223         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5224
5225         dev = &rte_eth_devices[port];
5226         rte_eth_dev_info_get(port, &dev_info);
5227
5228         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5229                 return -ENOTSUP;
5230
5231         if (vf >= dev_info.max_vfs)
5232                 return -EINVAL;
5233
5234         if (on > 1)
5235                 return -EINVAL;
5236
5237         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238         if (ixgbe_vt_check(hw) < 0)
5239                 return -ENOTSUP;
5240
5241         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5242         if (vf >= 32) {
5243                 addr = IXGBE_VFTE(1);
5244                 val = bit1 << (vf - 32);
5245         } else {
5246                 addr = IXGBE_VFTE(0);
5247                 val = bit1 << vf;
5248         }
5249
5250         reg = IXGBE_READ_REG(hw, addr);
5251
5252         if (on)
5253                 reg |= val;
5254         else
5255                 reg &= ~val;
5256
5257         IXGBE_WRITE_REG(hw, addr, reg);
5258
5259         return 0;
5260 }
5261
5262 int
5263 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5264                         uint64_t vf_mask, uint8_t vlan_on)
5265 {
5266         struct rte_eth_dev *dev;
5267         struct rte_eth_dev_info dev_info;
5268         int ret = 0;
5269         uint16_t vf_idx;
5270         struct ixgbe_hw *hw;
5271
5272         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5273
5274         dev = &rte_eth_devices[port];
5275         rte_eth_dev_info_get(port, &dev_info);
5276
5277         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5278                 return -ENOTSUP;
5279
5280         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5281                 return -EINVAL;
5282
5283         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5284         if (ixgbe_vt_check(hw) < 0)
5285                 return -ENOTSUP;
5286
5287         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5288                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5289                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5290                                                    vlan_on, false);
5291                         if (ret < 0)
5292                                 return ret;
5293                 }
5294         }
5295
5296         return ret;
5297 }
5298
5299 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5300         uint16_t tx_rate, uint64_t q_msk)
5301 {
5302         struct rte_eth_dev *dev;
5303         struct rte_eth_dev_info dev_info;
5304         struct ixgbe_hw *hw;
5305         struct ixgbe_vf_info *vfinfo;
5306         struct rte_eth_link link;
5307         uint8_t  nb_q_per_pool;
5308         uint32_t queue_stride;
5309         uint32_t queue_idx, idx = 0, vf_idx;
5310         uint32_t queue_end;
5311         uint16_t total_rate = 0;
5312         struct rte_pci_device *pci_dev;
5313
5314         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5315
5316         dev = &rte_eth_devices[port];
5317         rte_eth_dev_info_get(port, &dev_info);
5318         rte_eth_link_get_nowait(port, &link);
5319
5320         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5321                 return -ENOTSUP;
5322
5323         if (vf >= dev_info.max_vfs)
5324                 return -EINVAL;
5325
5326         if (tx_rate > link.link_speed)
5327                 return -EINVAL;
5328
5329         if (q_msk == 0)
5330                 return 0;
5331
5332         pci_dev = IXGBE_DEV_TO_PCI(dev);
5333         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5334         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5335         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5336         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5337         queue_idx = vf * queue_stride;
5338         queue_end = queue_idx + nb_q_per_pool - 1;
5339         if (queue_end >= hw->mac.max_tx_queues)
5340                 return -EINVAL;
5341
5342         if (vfinfo) {
5343                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5344                         if (vf_idx == vf)
5345                                 continue;
5346                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5347                                 idx++)
5348                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5349                 }
5350         } else {
5351                 return -EINVAL;
5352         }
5353
5354         /* Store tx_rate for this vf. */
5355         for (idx = 0; idx < nb_q_per_pool; idx++) {
5356                 if (((uint64_t)0x1 << idx) & q_msk) {
5357                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5358                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5359                         total_rate += tx_rate;
5360                 }
5361         }
5362
5363         if (total_rate > dev->data->dev_link.link_speed) {
5364                 /* Reset stored TX rate of the VF if it causes exceed
5365                  * link speed.
5366                  */
5367                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5368                 return -EINVAL;
5369         }
5370
5371         /* Set RTTBCNRC of each queue/pool for vf X  */
5372         for (; queue_idx <= queue_end; queue_idx++) {
5373                 if (0x1 & q_msk)
5374                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5375                 q_msk = q_msk >> 1;
5376         }
5377
5378         return 0;
5379 }
5380
5381 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5382 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5383 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5384 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5385 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5386         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5387         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5388
5389 static int
5390 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5391                         struct rte_eth_mirror_conf *mirror_conf,
5392                         uint8_t rule_id, uint8_t on)
5393 {
5394         uint32_t mr_ctl, vlvf;
5395         uint32_t mp_lsb = 0;
5396         uint32_t mv_msb = 0;
5397         uint32_t mv_lsb = 0;
5398         uint32_t mp_msb = 0;
5399         uint8_t i = 0;
5400         int reg_index = 0;
5401         uint64_t vlan_mask = 0;
5402
5403         const uint8_t pool_mask_offset = 32;
5404         const uint8_t vlan_mask_offset = 32;
5405         const uint8_t dst_pool_offset = 8;
5406         const uint8_t rule_mr_offset  = 4;
5407         const uint8_t mirror_rule_mask = 0x0F;
5408
5409         struct ixgbe_mirror_info *mr_info =
5410                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5411         struct ixgbe_hw *hw =
5412                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5413         uint8_t mirror_type = 0;
5414
5415         if (ixgbe_vt_check(hw) < 0)
5416                 return -ENOTSUP;
5417
5418         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5419                 return -EINVAL;
5420
5421         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5422                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5423                         mirror_conf->rule_type);
5424                 return -EINVAL;
5425         }
5426
5427         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5428                 mirror_type |= IXGBE_MRCTL_VLME;
5429                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5430                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5431                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5432                                 /* search vlan id related pool vlan filter index */
5433                                 reg_index = ixgbe_find_vlvf_slot(hw,
5434                                                  mirror_conf->vlan.vlan_id[i],
5435                                                  false);
5436                                 if (reg_index < 0)
5437                                         return -EINVAL;
5438                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5439                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5440                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5441                                       mirror_conf->vlan.vlan_id[i]))
5442                                         vlan_mask |= (1ULL << reg_index);
5443                                 else
5444                                         return -EINVAL;
5445                         }
5446                 }
5447
5448                 if (on) {
5449                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5450                         mv_msb = vlan_mask >> vlan_mask_offset;
5451
5452                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5453                                                 mirror_conf->vlan.vlan_mask;
5454                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5455                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5456                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5457                                                 mirror_conf->vlan.vlan_id[i];
5458                         }
5459                 } else {
5460                         mv_lsb = 0;
5461                         mv_msb = 0;
5462                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5463                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5464                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5465                 }
5466         }
5467
5468         /*
5469          * if enable pool mirror, write related pool mask register,if disable
5470          * pool mirror, clear PFMRVM register
5471          */
5472         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5473                 mirror_type |= IXGBE_MRCTL_VPME;
5474                 if (on) {
5475                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5476                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5477                         mr_info->mr_conf[rule_id].pool_mask =
5478                                         mirror_conf->pool_mask;
5479
5480                 } else {
5481                         mp_lsb = 0;
5482                         mp_msb = 0;
5483                         mr_info->mr_conf[rule_id].pool_mask = 0;
5484                 }
5485         }
5486         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5487                 mirror_type |= IXGBE_MRCTL_UPME;
5488         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5489                 mirror_type |= IXGBE_MRCTL_DPME;
5490
5491         /* read  mirror control register and recalculate it */
5492         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5493
5494         if (on) {
5495                 mr_ctl |= mirror_type;
5496                 mr_ctl &= mirror_rule_mask;
5497                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5498         } else
5499                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5500
5501         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5502         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5503
5504         /* write mirrror control  register */
5505         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5506
5507         /* write pool mirrror control  register */
5508         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5509                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5510                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5511                                 mp_msb);
5512         }
5513         /* write VLAN mirrror control  register */
5514         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5515                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5516                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5517                                 mv_msb);
5518         }
5519
5520         return 0;
5521 }
5522
5523 static int
5524 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5525 {
5526         int mr_ctl = 0;
5527         uint32_t lsb_val = 0;
5528         uint32_t msb_val = 0;
5529         const uint8_t rule_mr_offset = 4;
5530
5531         struct ixgbe_hw *hw =
5532                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5533         struct ixgbe_mirror_info *mr_info =
5534                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5535
5536         if (ixgbe_vt_check(hw) < 0)
5537                 return -ENOTSUP;
5538
5539         memset(&mr_info->mr_conf[rule_id], 0,
5540                 sizeof(struct rte_eth_mirror_conf));
5541
5542         /* clear PFVMCTL register */
5543         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5544
5545         /* clear pool mask register */
5546         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5547         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5548
5549         /* clear vlan mask register */
5550         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5551         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5552
5553         return 0;
5554 }
5555
5556 static int
5557 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5558 {
5559         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5560         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5561         uint32_t mask;
5562         struct ixgbe_hw *hw =
5563                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5564
5565         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5566         mask |= (1 << IXGBE_MISC_VEC_ID);
5567         RTE_SET_USED(queue_id);
5568         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5569
5570         rte_intr_enable(intr_handle);
5571
5572         return 0;
5573 }
5574
5575 static int
5576 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5577 {
5578         uint32_t mask;
5579         struct ixgbe_hw *hw =
5580                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5581
5582         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5583         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5584         RTE_SET_USED(queue_id);
5585         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5586
5587         return 0;
5588 }
5589
5590 static int
5591 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5592 {
5593         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5594         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5595         uint32_t mask;
5596         struct ixgbe_hw *hw =
5597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5598         struct ixgbe_interrupt *intr =
5599                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5600
5601         if (queue_id < 16) {
5602                 ixgbe_disable_intr(hw);
5603                 intr->mask |= (1 << queue_id);
5604                 ixgbe_enable_intr(dev);
5605         } else if (queue_id < 32) {
5606                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5607                 mask &= (1 << queue_id);
5608                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5609         } else if (queue_id < 64) {
5610                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5611                 mask &= (1 << (queue_id - 32));
5612                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5613         }
5614         rte_intr_enable(intr_handle);
5615
5616         return 0;
5617 }
5618
5619 static int
5620 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5621 {
5622         uint32_t mask;
5623         struct ixgbe_hw *hw =
5624                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5625         struct ixgbe_interrupt *intr =
5626                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5627
5628         if (queue_id < 16) {
5629                 ixgbe_disable_intr(hw);
5630                 intr->mask &= ~(1 << queue_id);
5631                 ixgbe_enable_intr(dev);
5632         } else if (queue_id < 32) {
5633                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5634                 mask &= ~(1 << queue_id);
5635                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5636         } else if (queue_id < 64) {
5637                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5638                 mask &= ~(1 << (queue_id - 32));
5639                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5640         }
5641
5642         return 0;
5643 }
5644
5645 static void
5646 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5647                      uint8_t queue, uint8_t msix_vector)
5648 {
5649         uint32_t tmp, idx;
5650
5651         if (direction == -1) {
5652                 /* other causes */
5653                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5654                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5655                 tmp &= ~0xFF;
5656                 tmp |= msix_vector;
5657                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5658         } else {
5659                 /* rx or tx cause */
5660                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5661                 idx = ((16 * (queue & 1)) + (8 * direction));
5662                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5663                 tmp &= ~(0xFF << idx);
5664                 tmp |= (msix_vector << idx);
5665                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5666         }
5667 }
5668
5669 /**
5670  * set the IVAR registers, mapping interrupt causes to vectors
5671  * @param hw
5672  *  pointer to ixgbe_hw struct
5673  * @direction
5674  *  0 for Rx, 1 for Tx, -1 for other causes
5675  * @queue
5676  *  queue to map the corresponding interrupt to
5677  * @msix_vector
5678  *  the vector to map to the corresponding queue
5679  */
5680 static void
5681 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5682                    uint8_t queue, uint8_t msix_vector)
5683 {
5684         uint32_t tmp, idx;
5685
5686         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5687         if (hw->mac.type == ixgbe_mac_82598EB) {
5688                 if (direction == -1)
5689                         direction = 0;
5690                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5691                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5692                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5693                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5694                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5695         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5696                         (hw->mac.type == ixgbe_mac_X540)) {
5697                 if (direction == -1) {
5698                         /* other causes */
5699                         idx = ((queue & 1) * 8);
5700                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5701                         tmp &= ~(0xFF << idx);
5702                         tmp |= (msix_vector << idx);
5703                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5704                 } else {
5705                         /* rx or tx causes */
5706                         idx = ((16 * (queue & 1)) + (8 * direction));
5707                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5708                         tmp &= ~(0xFF << idx);
5709                         tmp |= (msix_vector << idx);
5710                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5711                 }
5712         }
5713 }
5714
5715 static void
5716 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5717 {
5718         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5719         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5720         struct ixgbe_hw *hw =
5721                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5722         uint32_t q_idx;
5723         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5724
5725         /* Configure VF other cause ivar */
5726         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5727
5728         /* won't configure msix register if no mapping is done
5729          * between intr vector and event fd.
5730          */
5731         if (!rte_intr_dp_is_en(intr_handle))
5732                 return;
5733
5734         /* Configure all RX queues of VF */
5735         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5736                 /* Force all queue use vector 0,
5737                  * as IXGBE_VF_MAXMSIVECOTR = 1
5738                  */
5739                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5740                 intr_handle->intr_vec[q_idx] = vector_idx;
5741         }
5742 }
5743
5744 /**
5745  * Sets up the hardware to properly generate MSI-X interrupts
5746  * @hw
5747  *  board private structure
5748  */
5749 static void
5750 ixgbe_configure_msix(struct rte_eth_dev *dev)
5751 {
5752         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5753         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5754         struct ixgbe_hw *hw =
5755                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5756         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5757         uint32_t vec = IXGBE_MISC_VEC_ID;
5758         uint32_t mask;
5759         uint32_t gpie;
5760
5761         /* won't configure msix register if no mapping is done
5762          * between intr vector and event fd
5763          */
5764         if (!rte_intr_dp_is_en(intr_handle))
5765                 return;
5766
5767         if (rte_intr_allow_others(intr_handle))
5768                 vec = base = IXGBE_RX_VEC_START;
5769
5770         /* setup GPIE for MSI-x mode */
5771         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5772         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5773                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5774         /* auto clearing and auto setting corresponding bits in EIMS
5775          * when MSI-X interrupt is triggered
5776          */
5777         if (hw->mac.type == ixgbe_mac_82598EB) {
5778                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5779         } else {
5780                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5781                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5782         }
5783         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5784
5785         /* Populate the IVAR table and set the ITR values to the
5786          * corresponding register.
5787          */
5788         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5789              queue_id++) {
5790                 /* by default, 1:1 mapping */
5791                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5792                 intr_handle->intr_vec[queue_id] = vec;
5793                 if (vec < base + intr_handle->nb_efd - 1)
5794                         vec++;
5795         }
5796
5797         switch (hw->mac.type) {
5798         case ixgbe_mac_82598EB:
5799                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5800                                    IXGBE_MISC_VEC_ID);
5801                 break;
5802         case ixgbe_mac_82599EB:
5803         case ixgbe_mac_X540:
5804                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5805                 break;
5806         default:
5807                 break;
5808         }
5809         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5810                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5811
5812         /* set up to autoclear timer, and the vectors */
5813         mask = IXGBE_EIMS_ENABLE_MASK;
5814         mask &= ~(IXGBE_EIMS_OTHER |
5815                   IXGBE_EIMS_MAILBOX |
5816                   IXGBE_EIMS_LSC);
5817
5818         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5819 }
5820
5821 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5822         uint16_t queue_idx, uint16_t tx_rate)
5823 {
5824         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5825         uint32_t rf_dec, rf_int;
5826         uint32_t bcnrc_val;
5827         uint16_t link_speed = dev->data->dev_link.link_speed;
5828
5829         if (queue_idx >= hw->mac.max_tx_queues)
5830                 return -EINVAL;
5831
5832         if (tx_rate != 0) {
5833                 /* Calculate the rate factor values to set */
5834                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5835                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5836                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5837
5838                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5839                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5840                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5841                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5842         } else {
5843                 bcnrc_val = 0;
5844         }
5845
5846         /*
5847          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5848          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5849          * set as 0x4.
5850          */
5851         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5852                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5853                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5854                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5855                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5856         else
5857                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5858                         IXGBE_MMW_SIZE_DEFAULT);
5859
5860         /* Set RTTBCNRC of queue X */
5861         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5862         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5863         IXGBE_WRITE_FLUSH(hw);
5864
5865         return 0;
5866 }
5867
5868 static void
5869 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5870                      __attribute__((unused)) uint32_t index,
5871                      __attribute__((unused)) uint32_t pool)
5872 {
5873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5874         int diag;
5875
5876         /*
5877          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5878          * operation. Trap this case to avoid exhausting the [very limited]
5879          * set of PF resources used to store VF MAC addresses.
5880          */
5881         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5882                 return;
5883         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5884         if (diag == 0)
5885                 return;
5886         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5887 }
5888
5889 static void
5890 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5891 {
5892         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5893         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5894         struct ether_addr *mac_addr;
5895         uint32_t i;
5896         int diag;
5897
5898         /*
5899          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5900          * not support the deletion of a given MAC address.
5901          * Instead, it imposes to delete all MAC addresses, then to add again
5902          * all MAC addresses with the exception of the one to be deleted.
5903          */
5904         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5905
5906         /*
5907          * Add again all MAC addresses, with the exception of the deleted one
5908          * and of the permanent MAC address.
5909          */
5910         for (i = 0, mac_addr = dev->data->mac_addrs;
5911              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5912                 /* Skip the deleted MAC address */
5913                 if (i == index)
5914                         continue;
5915                 /* Skip NULL MAC addresses */
5916                 if (is_zero_ether_addr(mac_addr))
5917                         continue;
5918                 /* Skip the permanent MAC address */
5919                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5920                         continue;
5921                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5922                 if (diag != 0)
5923                         PMD_DRV_LOG(ERR,
5924                                     "Adding again MAC address "
5925                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5926                                     "diag=%d",
5927                                     mac_addr->addr_bytes[0],
5928                                     mac_addr->addr_bytes[1],
5929                                     mac_addr->addr_bytes[2],
5930                                     mac_addr->addr_bytes[3],
5931                                     mac_addr->addr_bytes[4],
5932                                     mac_addr->addr_bytes[5],
5933                                     diag);
5934         }
5935 }
5936
5937 static void
5938 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5939 {
5940         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941
5942         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5943 }
5944
5945 #define MAC_TYPE_FILTER_SUP(type)    do {\
5946         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5947                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5948                 (type) != ixgbe_mac_X550EM_a)\
5949                 return -ENOTSUP;\
5950 } while (0)
5951
5952 static int
5953 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5954                         struct rte_eth_syn_filter *filter,
5955                         bool add)
5956 {
5957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5958         struct ixgbe_filter_info *filter_info =
5959                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5960         uint32_t syn_info;
5961         uint32_t synqf;
5962
5963         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5964                 return -EINVAL;
5965
5966         syn_info = filter_info->syn_info;
5967
5968         if (add) {
5969                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5970                         return -EINVAL;
5971                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5972                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5973
5974                 if (filter->hig_pri)
5975                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5976                 else
5977                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5978         } else {
5979                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5980                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5981                         return -ENOENT;
5982                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5983         }
5984
5985         filter_info->syn_info = synqf;
5986         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5987         IXGBE_WRITE_FLUSH(hw);
5988         return 0;
5989 }
5990
5991 static int
5992 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5993                         struct rte_eth_syn_filter *filter)
5994 {
5995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5996         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5997
5998         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5999                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6000                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6001                 return 0;
6002         }
6003         return -ENOENT;
6004 }
6005
6006 static int
6007 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6008                         enum rte_filter_op filter_op,
6009                         void *arg)
6010 {
6011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6012         int ret;
6013
6014         MAC_TYPE_FILTER_SUP(hw->mac.type);
6015
6016         if (filter_op == RTE_ETH_FILTER_NOP)
6017                 return 0;
6018
6019         if (arg == NULL) {
6020                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6021                             filter_op);
6022                 return -EINVAL;
6023         }
6024
6025         switch (filter_op) {
6026         case RTE_ETH_FILTER_ADD:
6027                 ret = ixgbe_syn_filter_set(dev,
6028                                 (struct rte_eth_syn_filter *)arg,
6029                                 TRUE);
6030                 break;
6031         case RTE_ETH_FILTER_DELETE:
6032                 ret = ixgbe_syn_filter_set(dev,
6033                                 (struct rte_eth_syn_filter *)arg,
6034                                 FALSE);
6035                 break;
6036         case RTE_ETH_FILTER_GET:
6037                 ret = ixgbe_syn_filter_get(dev,
6038                                 (struct rte_eth_syn_filter *)arg);
6039                 break;
6040         default:
6041                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6042                 ret = -EINVAL;
6043                 break;
6044         }
6045
6046         return ret;
6047 }
6048
6049
6050 static inline enum ixgbe_5tuple_protocol
6051 convert_protocol_type(uint8_t protocol_value)
6052 {
6053         if (protocol_value == IPPROTO_TCP)
6054                 return IXGBE_FILTER_PROTOCOL_TCP;
6055         else if (protocol_value == IPPROTO_UDP)
6056                 return IXGBE_FILTER_PROTOCOL_UDP;
6057         else if (protocol_value == IPPROTO_SCTP)
6058                 return IXGBE_FILTER_PROTOCOL_SCTP;
6059         else
6060                 return IXGBE_FILTER_PROTOCOL_NONE;
6061 }
6062
6063 /* inject a 5-tuple filter to HW */
6064 static inline void
6065 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6066                            struct ixgbe_5tuple_filter *filter)
6067 {
6068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6069         int i;
6070         uint32_t ftqf, sdpqf;
6071         uint32_t l34timir = 0;
6072         uint8_t mask = 0xff;
6073
6074         i = filter->index;
6075
6076         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6077                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6078         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6079
6080         ftqf = (uint32_t)(filter->filter_info.proto &
6081                 IXGBE_FTQF_PROTOCOL_MASK);
6082         ftqf |= (uint32_t)((filter->filter_info.priority &
6083                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6084         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6085                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6086         if (filter->filter_info.dst_ip_mask == 0)
6087                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6088         if (filter->filter_info.src_port_mask == 0)
6089                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6090         if (filter->filter_info.dst_port_mask == 0)
6091                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6092         if (filter->filter_info.proto_mask == 0)
6093                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6094         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6095         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6096         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6097
6098         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6099         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6100         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6101         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6102
6103         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6104         l34timir |= (uint32_t)(filter->queue <<
6105                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6106         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6107 }
6108
6109 /*
6110  * add a 5tuple filter
6111  *
6112  * @param
6113  * dev: Pointer to struct rte_eth_dev.
6114  * index: the index the filter allocates.
6115  * filter: ponter to the filter that will be added.
6116  * rx_queue: the queue id the filter assigned to.
6117  *
6118  * @return
6119  *    - On success, zero.
6120  *    - On failure, a negative value.
6121  */
6122 static int
6123 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6124                         struct ixgbe_5tuple_filter *filter)
6125 {
6126         struct ixgbe_filter_info *filter_info =
6127                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6128         int i, idx, shift;
6129
6130         /*
6131          * look for an unused 5tuple filter index,
6132          * and insert the filter to list.
6133          */
6134         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6135                 idx = i / (sizeof(uint32_t) * NBBY);
6136                 shift = i % (sizeof(uint32_t) * NBBY);
6137                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6138                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6139                         filter->index = i;
6140                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6141                                           filter,
6142                                           entries);
6143                         break;
6144                 }
6145         }
6146         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6147                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6148                 return -ENOSYS;
6149         }
6150
6151         ixgbe_inject_5tuple_filter(dev, filter);
6152
6153         return 0;
6154 }
6155
6156 /*
6157  * remove a 5tuple filter
6158  *
6159  * @param
6160  * dev: Pointer to struct rte_eth_dev.
6161  * filter: the pointer of the filter will be removed.
6162  */
6163 static void
6164 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6165                         struct ixgbe_5tuple_filter *filter)
6166 {
6167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6168         struct ixgbe_filter_info *filter_info =
6169                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6170         uint16_t index = filter->index;
6171
6172         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6173                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6174         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6175         rte_free(filter);
6176
6177         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6178         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6179         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6180         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6181         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6182 }
6183
6184 static int
6185 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6186 {
6187         struct ixgbe_hw *hw;
6188         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6189
6190         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6191
6192         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6193                 return -EINVAL;
6194
6195         /* refuse mtu that requires the support of scattered packets when this
6196          * feature has not been enabled before.
6197          */
6198         if (!dev->data->scattered_rx &&
6199             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6200              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6201                 return -EINVAL;
6202
6203         /*
6204          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6205          * request of the version 2.0 of the mailbox API.
6206          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6207          * of the mailbox API.
6208          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6209          * prior to 3.11.33 which contains the following change:
6210          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6211          */
6212         ixgbevf_rlpml_set_vf(hw, max_frame);
6213
6214         /* update max frame size */
6215         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6216         return 0;
6217 }
6218
6219 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
6220         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6221                 return -ENOTSUP;\
6222 } while (0)
6223
6224 static inline struct ixgbe_5tuple_filter *
6225 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6226                         struct ixgbe_5tuple_filter_info *key)
6227 {
6228         struct ixgbe_5tuple_filter *it;
6229
6230         TAILQ_FOREACH(it, filter_list, entries) {
6231                 if (memcmp(key, &it->filter_info,
6232                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6233                         return it;
6234                 }
6235         }
6236         return NULL;
6237 }
6238
6239 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6240 static inline int
6241 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6242                         struct ixgbe_5tuple_filter_info *filter_info)
6243 {
6244         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6245                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6246                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6247                 return -EINVAL;
6248
6249         switch (filter->dst_ip_mask) {
6250         case UINT32_MAX:
6251                 filter_info->dst_ip_mask = 0;
6252                 filter_info->dst_ip = filter->dst_ip;
6253                 break;
6254         case 0:
6255                 filter_info->dst_ip_mask = 1;
6256                 break;
6257         default:
6258                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6259                 return -EINVAL;
6260         }
6261
6262         switch (filter->src_ip_mask) {
6263         case UINT32_MAX:
6264                 filter_info->src_ip_mask = 0;
6265                 filter_info->src_ip = filter->src_ip;
6266                 break;
6267         case 0:
6268                 filter_info->src_ip_mask = 1;
6269                 break;
6270         default:
6271                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6272                 return -EINVAL;
6273         }
6274
6275         switch (filter->dst_port_mask) {
6276         case UINT16_MAX:
6277                 filter_info->dst_port_mask = 0;
6278                 filter_info->dst_port = filter->dst_port;
6279                 break;
6280         case 0:
6281                 filter_info->dst_port_mask = 1;
6282                 break;
6283         default:
6284                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6285                 return -EINVAL;
6286         }
6287
6288         switch (filter->src_port_mask) {
6289         case UINT16_MAX:
6290                 filter_info->src_port_mask = 0;
6291                 filter_info->src_port = filter->src_port;
6292                 break;
6293         case 0:
6294                 filter_info->src_port_mask = 1;
6295                 break;
6296         default:
6297                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6298                 return -EINVAL;
6299         }
6300
6301         switch (filter->proto_mask) {
6302         case UINT8_MAX:
6303                 filter_info->proto_mask = 0;
6304                 filter_info->proto =
6305                         convert_protocol_type(filter->proto);
6306                 break;
6307         case 0:
6308                 filter_info->proto_mask = 1;
6309                 break;
6310         default:
6311                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6312                 return -EINVAL;
6313         }
6314
6315         filter_info->priority = (uint8_t)filter->priority;
6316         return 0;
6317 }
6318
6319 /*
6320  * add or delete a ntuple filter
6321  *
6322  * @param
6323  * dev: Pointer to struct rte_eth_dev.
6324  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6325  * add: if true, add filter, if false, remove filter
6326  *
6327  * @return
6328  *    - On success, zero.
6329  *    - On failure, a negative value.
6330  */
6331 static int
6332 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6333                         struct rte_eth_ntuple_filter *ntuple_filter,
6334                         bool add)
6335 {
6336         struct ixgbe_filter_info *filter_info =
6337                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6338         struct ixgbe_5tuple_filter_info filter_5tuple;
6339         struct ixgbe_5tuple_filter *filter;
6340         int ret;
6341
6342         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6343                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6344                 return -EINVAL;
6345         }
6346
6347         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6348         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6349         if (ret < 0)
6350                 return ret;
6351
6352         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6353                                          &filter_5tuple);
6354         if (filter != NULL && add) {
6355                 PMD_DRV_LOG(ERR, "filter exists.");
6356                 return -EEXIST;
6357         }
6358         if (filter == NULL && !add) {
6359                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6360                 return -ENOENT;
6361         }
6362
6363         if (add) {
6364                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6365                                 sizeof(struct ixgbe_5tuple_filter), 0);
6366                 if (filter == NULL)
6367                         return -ENOMEM;
6368                 (void)rte_memcpy(&filter->filter_info,
6369                                  &filter_5tuple,
6370                                  sizeof(struct ixgbe_5tuple_filter_info));
6371                 filter->queue = ntuple_filter->queue;
6372                 ret = ixgbe_add_5tuple_filter(dev, filter);
6373                 if (ret < 0) {
6374                         rte_free(filter);
6375                         return ret;
6376                 }
6377         } else
6378                 ixgbe_remove_5tuple_filter(dev, filter);
6379
6380         return 0;
6381 }
6382
6383 /*
6384  * get a ntuple filter
6385  *
6386  * @param
6387  * dev: Pointer to struct rte_eth_dev.
6388  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6389  *
6390  * @return
6391  *    - On success, zero.
6392  *    - On failure, a negative value.
6393  */
6394 static int
6395 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6396                         struct rte_eth_ntuple_filter *ntuple_filter)
6397 {
6398         struct ixgbe_filter_info *filter_info =
6399                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6400         struct ixgbe_5tuple_filter_info filter_5tuple;
6401         struct ixgbe_5tuple_filter *filter;
6402         int ret;
6403
6404         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6405                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6406                 return -EINVAL;
6407         }
6408
6409         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6410         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6411         if (ret < 0)
6412                 return ret;
6413
6414         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6415                                          &filter_5tuple);
6416         if (filter == NULL) {
6417                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6418                 return -ENOENT;
6419         }
6420         ntuple_filter->queue = filter->queue;
6421         return 0;
6422 }
6423
6424 /*
6425  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6426  * @dev: pointer to rte_eth_dev structure
6427  * @filter_op:operation will be taken.
6428  * @arg: a pointer to specific structure corresponding to the filter_op
6429  *
6430  * @return
6431  *    - On success, zero.
6432  *    - On failure, a negative value.
6433  */
6434 static int
6435 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6436                                 enum rte_filter_op filter_op,
6437                                 void *arg)
6438 {
6439         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6440         int ret;
6441
6442         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6443
6444         if (filter_op == RTE_ETH_FILTER_NOP)
6445                 return 0;
6446
6447         if (arg == NULL) {
6448                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6449                             filter_op);
6450                 return -EINVAL;
6451         }
6452
6453         switch (filter_op) {
6454         case RTE_ETH_FILTER_ADD:
6455                 ret = ixgbe_add_del_ntuple_filter(dev,
6456                         (struct rte_eth_ntuple_filter *)arg,
6457                         TRUE);
6458                 break;
6459         case RTE_ETH_FILTER_DELETE:
6460                 ret = ixgbe_add_del_ntuple_filter(dev,
6461                         (struct rte_eth_ntuple_filter *)arg,
6462                         FALSE);
6463                 break;
6464         case RTE_ETH_FILTER_GET:
6465                 ret = ixgbe_get_ntuple_filter(dev,
6466                         (struct rte_eth_ntuple_filter *)arg);
6467                 break;
6468         default:
6469                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6470                 ret = -EINVAL;
6471                 break;
6472         }
6473         return ret;
6474 }
6475
6476 static int
6477 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6478                         struct rte_eth_ethertype_filter *filter,
6479                         bool add)
6480 {
6481         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6482         struct ixgbe_filter_info *filter_info =
6483                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6484         uint32_t etqf = 0;
6485         uint32_t etqs = 0;
6486         int ret;
6487         struct ixgbe_ethertype_filter ethertype_filter;
6488
6489         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6490                 return -EINVAL;
6491
6492         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6493                 filter->ether_type == ETHER_TYPE_IPv6) {
6494                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6495                         " ethertype filter.", filter->ether_type);
6496                 return -EINVAL;
6497         }
6498
6499         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6500                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6501                 return -EINVAL;
6502         }
6503         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6504                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6505                 return -EINVAL;
6506         }
6507
6508         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6509         if (ret >= 0 && add) {
6510                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6511                             filter->ether_type);
6512                 return -EEXIST;
6513         }
6514         if (ret < 0 && !add) {
6515                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6516                             filter->ether_type);
6517                 return -ENOENT;
6518         }
6519
6520         if (add) {
6521                 etqf = IXGBE_ETQF_FILTER_EN;
6522                 etqf |= (uint32_t)filter->ether_type;
6523                 etqs |= (uint32_t)((filter->queue <<
6524                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6525                                     IXGBE_ETQS_RX_QUEUE);
6526                 etqs |= IXGBE_ETQS_QUEUE_EN;
6527
6528                 ethertype_filter.ethertype = filter->ether_type;
6529                 ethertype_filter.etqf = etqf;
6530                 ethertype_filter.etqs = etqs;
6531                 ret = ixgbe_ethertype_filter_insert(filter_info,
6532                                                     &ethertype_filter);
6533                 if (ret < 0) {
6534                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6535                         return -ENOSPC;
6536                 }
6537         } else {
6538                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6539                 if (ret < 0)
6540                         return -ENOSYS;
6541         }
6542         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6543         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6544         IXGBE_WRITE_FLUSH(hw);
6545
6546         return 0;
6547 }
6548
6549 static int
6550 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6551                         struct rte_eth_ethertype_filter *filter)
6552 {
6553         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6554         struct ixgbe_filter_info *filter_info =
6555                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6556         uint32_t etqf, etqs;
6557         int ret;
6558
6559         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6560         if (ret < 0) {
6561                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6562                             filter->ether_type);
6563                 return -ENOENT;
6564         }
6565
6566         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6567         if (etqf & IXGBE_ETQF_FILTER_EN) {
6568                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6569                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6570                 filter->flags = 0;
6571                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6572                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6573                 return 0;
6574         }
6575         return -ENOENT;
6576 }
6577
6578 /*
6579  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6580  * @dev: pointer to rte_eth_dev structure
6581  * @filter_op:operation will be taken.
6582  * @arg: a pointer to specific structure corresponding to the filter_op
6583  */
6584 static int
6585 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6586                                 enum rte_filter_op filter_op,
6587                                 void *arg)
6588 {
6589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6590         int ret;
6591
6592         MAC_TYPE_FILTER_SUP(hw->mac.type);
6593
6594         if (filter_op == RTE_ETH_FILTER_NOP)
6595                 return 0;
6596
6597         if (arg == NULL) {
6598                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6599                             filter_op);
6600                 return -EINVAL;
6601         }
6602
6603         switch (filter_op) {
6604         case RTE_ETH_FILTER_ADD:
6605                 ret = ixgbe_add_del_ethertype_filter(dev,
6606                         (struct rte_eth_ethertype_filter *)arg,
6607                         TRUE);
6608                 break;
6609         case RTE_ETH_FILTER_DELETE:
6610                 ret = ixgbe_add_del_ethertype_filter(dev,
6611                         (struct rte_eth_ethertype_filter *)arg,
6612                         FALSE);
6613                 break;
6614         case RTE_ETH_FILTER_GET:
6615                 ret = ixgbe_get_ethertype_filter(dev,
6616                         (struct rte_eth_ethertype_filter *)arg);
6617                 break;
6618         default:
6619                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6620                 ret = -EINVAL;
6621                 break;
6622         }
6623         return ret;
6624 }
6625
6626 static int
6627 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6628                      enum rte_filter_type filter_type,
6629                      enum rte_filter_op filter_op,
6630                      void *arg)
6631 {
6632         int ret = -EINVAL;
6633
6634         switch (filter_type) {
6635         case RTE_ETH_FILTER_NTUPLE:
6636                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6637                 break;
6638         case RTE_ETH_FILTER_ETHERTYPE:
6639                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6640                 break;
6641         case RTE_ETH_FILTER_SYN:
6642                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6643                 break;
6644         case RTE_ETH_FILTER_FDIR:
6645                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6646                 break;
6647         case RTE_ETH_FILTER_L2_TUNNEL:
6648                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6649                 break;
6650         default:
6651                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6652                                                         filter_type);
6653                 break;
6654         }
6655
6656         return ret;
6657 }
6658
6659 static u8 *
6660 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6661                         u8 **mc_addr_ptr, u32 *vmdq)
6662 {
6663         u8 *mc_addr;
6664
6665         *vmdq = 0;
6666         mc_addr = *mc_addr_ptr;
6667         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6668         return mc_addr;
6669 }
6670
6671 static int
6672 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6673                           struct ether_addr *mc_addr_set,
6674                           uint32_t nb_mc_addr)
6675 {
6676         struct ixgbe_hw *hw;
6677         u8 *mc_addr_list;
6678
6679         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6680         mc_addr_list = (u8 *)mc_addr_set;
6681         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6682                                          ixgbe_dev_addr_list_itr, TRUE);
6683 }
6684
6685 static uint64_t
6686 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6687 {
6688         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6689         uint64_t systime_cycles;
6690
6691         switch (hw->mac.type) {
6692         case ixgbe_mac_X550:
6693         case ixgbe_mac_X550EM_x:
6694         case ixgbe_mac_X550EM_a:
6695                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6696                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6697                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6698                                 * NSEC_PER_SEC;
6699                 break;
6700         default:
6701                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6702                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6703                                 << 32;
6704         }
6705
6706         return systime_cycles;
6707 }
6708
6709 static uint64_t
6710 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6711 {
6712         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6713         uint64_t rx_tstamp_cycles;
6714
6715         switch (hw->mac.type) {
6716         case ixgbe_mac_X550:
6717         case ixgbe_mac_X550EM_x:
6718         case ixgbe_mac_X550EM_a:
6719                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6720                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6721                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6722                                 * NSEC_PER_SEC;
6723                 break;
6724         default:
6725                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6726                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6727                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6728                                 << 32;
6729         }
6730
6731         return rx_tstamp_cycles;
6732 }
6733
6734 static uint64_t
6735 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6736 {
6737         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6738         uint64_t tx_tstamp_cycles;
6739
6740         switch (hw->mac.type) {
6741         case ixgbe_mac_X550:
6742         case ixgbe_mac_X550EM_x:
6743         case ixgbe_mac_X550EM_a:
6744                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6745                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6746                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6747                                 * NSEC_PER_SEC;
6748                 break;
6749         default:
6750                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6751                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6752                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6753                                 << 32;
6754         }
6755
6756         return tx_tstamp_cycles;
6757 }
6758
6759 static void
6760 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6761 {
6762         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6763         struct ixgbe_adapter *adapter =
6764                 (struct ixgbe_adapter *)dev->data->dev_private;
6765         struct rte_eth_link link;
6766         uint32_t incval = 0;
6767         uint32_t shift = 0;
6768
6769         /* Get current link speed. */
6770         memset(&link, 0, sizeof(link));
6771         ixgbe_dev_link_update(dev, 1);
6772         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6773
6774         switch (link.link_speed) {
6775         case ETH_SPEED_NUM_100M:
6776                 incval = IXGBE_INCVAL_100;
6777                 shift = IXGBE_INCVAL_SHIFT_100;
6778                 break;
6779         case ETH_SPEED_NUM_1G:
6780                 incval = IXGBE_INCVAL_1GB;
6781                 shift = IXGBE_INCVAL_SHIFT_1GB;
6782                 break;
6783         case ETH_SPEED_NUM_10G:
6784         default:
6785                 incval = IXGBE_INCVAL_10GB;
6786                 shift = IXGBE_INCVAL_SHIFT_10GB;
6787                 break;
6788         }
6789
6790         switch (hw->mac.type) {
6791         case ixgbe_mac_X550:
6792         case ixgbe_mac_X550EM_x:
6793         case ixgbe_mac_X550EM_a:
6794                 /* Independent of link speed. */
6795                 incval = 1;
6796                 /* Cycles read will be interpreted as ns. */
6797                 shift = 0;
6798                 /* Fall-through */
6799         case ixgbe_mac_X540:
6800                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6801                 break;
6802         case ixgbe_mac_82599EB:
6803                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6804                 shift -= IXGBE_INCVAL_SHIFT_82599;
6805                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6806                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6807                 break;
6808         default:
6809                 /* Not supported. */
6810                 return;
6811         }
6812
6813         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6814         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6815         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6816
6817         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6818         adapter->systime_tc.cc_shift = shift;
6819         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6820
6821         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6822         adapter->rx_tstamp_tc.cc_shift = shift;
6823         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6824
6825         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6826         adapter->tx_tstamp_tc.cc_shift = shift;
6827         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6828 }
6829
6830 static int
6831 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6832 {
6833         struct ixgbe_adapter *adapter =
6834                         (struct ixgbe_adapter *)dev->data->dev_private;
6835
6836         adapter->systime_tc.nsec += delta;
6837         adapter->rx_tstamp_tc.nsec += delta;
6838         adapter->tx_tstamp_tc.nsec += delta;
6839
6840         return 0;
6841 }
6842
6843 static int
6844 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6845 {
6846         uint64_t ns;
6847         struct ixgbe_adapter *adapter =
6848                         (struct ixgbe_adapter *)dev->data->dev_private;
6849
6850         ns = rte_timespec_to_ns(ts);
6851         /* Set the timecounters to a new value. */
6852         adapter->systime_tc.nsec = ns;
6853         adapter->rx_tstamp_tc.nsec = ns;
6854         adapter->tx_tstamp_tc.nsec = ns;
6855
6856         return 0;
6857 }
6858
6859 static int
6860 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6861 {
6862         uint64_t ns, systime_cycles;
6863         struct ixgbe_adapter *adapter =
6864                         (struct ixgbe_adapter *)dev->data->dev_private;
6865
6866         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6867         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6868         *ts = rte_ns_to_timespec(ns);
6869
6870         return 0;
6871 }
6872
6873 static int
6874 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6875 {
6876         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6877         uint32_t tsync_ctl;
6878         uint32_t tsauxc;
6879
6880         /* Stop the timesync system time. */
6881         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6882         /* Reset the timesync system time value. */
6883         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6884         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6885
6886         /* Enable system time for platforms where it isn't on by default. */
6887         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6888         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6889         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6890
6891         ixgbe_start_timecounters(dev);
6892
6893         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6894         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6895                         (ETHER_TYPE_1588 |
6896                          IXGBE_ETQF_FILTER_EN |
6897                          IXGBE_ETQF_1588));
6898
6899         /* Enable timestamping of received PTP packets. */
6900         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6901         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6902         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6903
6904         /* Enable timestamping of transmitted PTP packets. */
6905         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6906         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6907         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6908
6909         IXGBE_WRITE_FLUSH(hw);
6910
6911         return 0;
6912 }
6913
6914 static int
6915 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6916 {
6917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6918         uint32_t tsync_ctl;
6919
6920         /* Disable timestamping of transmitted PTP packets. */
6921         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6922         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6923         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6924
6925         /* Disable timestamping of received PTP packets. */
6926         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6927         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6928         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6929
6930         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6931         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6932
6933         /* Stop incrementating the System Time registers. */
6934         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6935
6936         return 0;
6937 }
6938
6939 static int
6940 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6941                                  struct timespec *timestamp,
6942                                  uint32_t flags __rte_unused)
6943 {
6944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6945         struct ixgbe_adapter *adapter =
6946                 (struct ixgbe_adapter *)dev->data->dev_private;
6947         uint32_t tsync_rxctl;
6948         uint64_t rx_tstamp_cycles;
6949         uint64_t ns;
6950
6951         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6952         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6953                 return -EINVAL;
6954
6955         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6956         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6957         *timestamp = rte_ns_to_timespec(ns);
6958
6959         return  0;
6960 }
6961
6962 static int
6963 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6964                                  struct timespec *timestamp)
6965 {
6966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6967         struct ixgbe_adapter *adapter =
6968                 (struct ixgbe_adapter *)dev->data->dev_private;
6969         uint32_t tsync_txctl;
6970         uint64_t tx_tstamp_cycles;
6971         uint64_t ns;
6972
6973         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6974         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6975                 return -EINVAL;
6976
6977         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6978         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6979         *timestamp = rte_ns_to_timespec(ns);
6980
6981         return 0;
6982 }
6983
6984 static int
6985 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6986 {
6987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6988         int count = 0;
6989         int g_ind = 0;
6990         const struct reg_info *reg_group;
6991         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6992                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6993
6994         while ((reg_group = reg_set[g_ind++]))
6995                 count += ixgbe_regs_group_count(reg_group);
6996
6997         return count;
6998 }
6999
7000 static int
7001 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7002 {
7003         int count = 0;
7004         int g_ind = 0;
7005         const struct reg_info *reg_group;
7006
7007         while ((reg_group = ixgbevf_regs[g_ind++]))
7008                 count += ixgbe_regs_group_count(reg_group);
7009
7010         return count;
7011 }
7012
7013 static int
7014 ixgbe_get_regs(struct rte_eth_dev *dev,
7015               struct rte_dev_reg_info *regs)
7016 {
7017         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7018         uint32_t *data = regs->data;
7019         int g_ind = 0;
7020         int count = 0;
7021         const struct reg_info *reg_group;
7022         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7023                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7024
7025         if (data == NULL) {
7026                 regs->length = ixgbe_get_reg_length(dev);
7027                 regs->width = sizeof(uint32_t);
7028                 return 0;
7029         }
7030
7031         /* Support only full register dump */
7032         if ((regs->length == 0) ||
7033             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7034                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7035                         hw->device_id;
7036                 while ((reg_group = reg_set[g_ind++]))
7037                         count += ixgbe_read_regs_group(dev, &data[count],
7038                                 reg_group);
7039                 return 0;
7040         }
7041
7042         return -ENOTSUP;
7043 }
7044
7045 static int
7046 ixgbevf_get_regs(struct rte_eth_dev *dev,
7047                 struct rte_dev_reg_info *regs)
7048 {
7049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7050         uint32_t *data = regs->data;
7051         int g_ind = 0;
7052         int count = 0;
7053         const struct reg_info *reg_group;
7054
7055         if (data == NULL) {
7056                 regs->length = ixgbevf_get_reg_length(dev);
7057                 regs->width = sizeof(uint32_t);
7058                 return 0;
7059         }
7060
7061         /* Support only full register dump */
7062         if ((regs->length == 0) ||
7063             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7064                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7065                         hw->device_id;
7066                 while ((reg_group = ixgbevf_regs[g_ind++]))
7067                         count += ixgbe_read_regs_group(dev, &data[count],
7068                                                       reg_group);
7069                 return 0;
7070         }
7071
7072         return -ENOTSUP;
7073 }
7074
7075 static int
7076 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7077 {
7078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7079
7080         /* Return unit is byte count */
7081         return hw->eeprom.word_size * 2;
7082 }
7083
7084 static int
7085 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7086                 struct rte_dev_eeprom_info *in_eeprom)
7087 {
7088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7089         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7090         uint16_t *data = in_eeprom->data;
7091         int first, length;
7092
7093         first = in_eeprom->offset >> 1;
7094         length = in_eeprom->length >> 1;
7095         if ((first > hw->eeprom.word_size) ||
7096             ((first + length) > hw->eeprom.word_size))
7097                 return -EINVAL;
7098
7099         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7100
7101         return eeprom->ops.read_buffer(hw, first, length, data);
7102 }
7103
7104 static int
7105 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7106                 struct rte_dev_eeprom_info *in_eeprom)
7107 {
7108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7109         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7110         uint16_t *data = in_eeprom->data;
7111         int first, length;
7112
7113         first = in_eeprom->offset >> 1;
7114         length = in_eeprom->length >> 1;
7115         if ((first > hw->eeprom.word_size) ||
7116             ((first + length) > hw->eeprom.word_size))
7117                 return -EINVAL;
7118
7119         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7120
7121         return eeprom->ops.write_buffer(hw,  first, length, data);
7122 }
7123
7124 uint16_t
7125 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7126         switch (mac_type) {
7127         case ixgbe_mac_X550:
7128         case ixgbe_mac_X550EM_x:
7129         case ixgbe_mac_X550EM_a:
7130                 return ETH_RSS_RETA_SIZE_512;
7131         case ixgbe_mac_X550_vf:
7132         case ixgbe_mac_X550EM_x_vf:
7133         case ixgbe_mac_X550EM_a_vf:
7134                 return ETH_RSS_RETA_SIZE_64;
7135         default:
7136                 return ETH_RSS_RETA_SIZE_128;
7137         }
7138 }
7139
7140 uint32_t
7141 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7142         switch (mac_type) {
7143         case ixgbe_mac_X550:
7144         case ixgbe_mac_X550EM_x:
7145         case ixgbe_mac_X550EM_a:
7146                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7147                         return IXGBE_RETA(reta_idx >> 2);
7148                 else
7149                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7150         case ixgbe_mac_X550_vf:
7151         case ixgbe_mac_X550EM_x_vf:
7152         case ixgbe_mac_X550EM_a_vf:
7153                 return IXGBE_VFRETA(reta_idx >> 2);
7154         default:
7155                 return IXGBE_RETA(reta_idx >> 2);
7156         }
7157 }
7158
7159 uint32_t
7160 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7161         switch (mac_type) {
7162         case ixgbe_mac_X550_vf:
7163         case ixgbe_mac_X550EM_x_vf:
7164         case ixgbe_mac_X550EM_a_vf:
7165                 return IXGBE_VFMRQC;
7166         default:
7167                 return IXGBE_MRQC;
7168         }
7169 }
7170
7171 uint32_t
7172 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7173         switch (mac_type) {
7174         case ixgbe_mac_X550_vf:
7175         case ixgbe_mac_X550EM_x_vf:
7176         case ixgbe_mac_X550EM_a_vf:
7177                 return IXGBE_VFRSSRK(i);
7178         default:
7179                 return IXGBE_RSSRK(i);
7180         }
7181 }
7182
7183 bool
7184 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7185         switch (mac_type) {
7186         case ixgbe_mac_82599_vf:
7187         case ixgbe_mac_X540_vf:
7188                 return 0;
7189         default:
7190                 return 1;
7191         }
7192 }
7193
7194 static int
7195 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7196                         struct rte_eth_dcb_info *dcb_info)
7197 {
7198         struct ixgbe_dcb_config *dcb_config =
7199                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7200         struct ixgbe_dcb_tc_config *tc;
7201         uint8_t i, j;
7202
7203         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7204                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7205         else
7206                 dcb_info->nb_tcs = 1;
7207
7208         if (dcb_config->vt_mode) { /* vt is enabled*/
7209                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7210                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7211                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7212                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7213                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7214                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7215                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7216                                                 i * dcb_info->nb_tcs + j;
7217                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7218                                 dcb_info->tc_queue.tc_txq[i][j].base =
7219                                                 i * dcb_info->nb_tcs + j;
7220                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7221                         }
7222                 }
7223         } else { /* vt is disabled*/
7224                 struct rte_eth_dcb_rx_conf *rx_conf =
7225                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7226                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7227                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7228                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7229                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7230                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7231                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7232                         }
7233                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7234                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7235                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7236                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7237                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7238                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7239                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7240                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7241                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7242                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7243                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7244                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7245                         }
7246                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7247                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7248                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7249                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7250                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7251                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7252                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7253                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7254                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7255                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7256                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7257                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7258                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7259                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7260                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7261                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7262                 }
7263         }
7264         for (i = 0; i < dcb_info->nb_tcs; i++) {
7265                 tc = &dcb_config->tc_config[i];
7266                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7267         }
7268         return 0;
7269 }
7270
7271 /* Update e-tag ether type */
7272 static int
7273 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7274                             uint16_t ether_type)
7275 {
7276         uint32_t etag_etype;
7277
7278         if (hw->mac.type != ixgbe_mac_X550 &&
7279             hw->mac.type != ixgbe_mac_X550EM_x &&
7280             hw->mac.type != ixgbe_mac_X550EM_a) {
7281                 return -ENOTSUP;
7282         }
7283
7284         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7285         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7286         etag_etype |= ether_type;
7287         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7288         IXGBE_WRITE_FLUSH(hw);
7289
7290         return 0;
7291 }
7292
7293 /* Config l2 tunnel ether type */
7294 static int
7295 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7296                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7297 {
7298         int ret = 0;
7299         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7300
7301         if (l2_tunnel == NULL)
7302                 return -EINVAL;
7303
7304         switch (l2_tunnel->l2_tunnel_type) {
7305         case RTE_L2_TUNNEL_TYPE_E_TAG:
7306                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7307                 break;
7308         default:
7309                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7310                 ret = -EINVAL;
7311                 break;
7312         }
7313
7314         return ret;
7315 }
7316
7317 /* Enable e-tag tunnel */
7318 static int
7319 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7320 {
7321         uint32_t etag_etype;
7322
7323         if (hw->mac.type != ixgbe_mac_X550 &&
7324             hw->mac.type != ixgbe_mac_X550EM_x &&
7325             hw->mac.type != ixgbe_mac_X550EM_a) {
7326                 return -ENOTSUP;
7327         }
7328
7329         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7330         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7331         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7332         IXGBE_WRITE_FLUSH(hw);
7333
7334         return 0;
7335 }
7336
7337 /* Enable l2 tunnel */
7338 static int
7339 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7340                            enum rte_eth_tunnel_type l2_tunnel_type)
7341 {
7342         int ret = 0;
7343         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7344
7345         switch (l2_tunnel_type) {
7346         case RTE_L2_TUNNEL_TYPE_E_TAG:
7347                 ret = ixgbe_e_tag_enable(hw);
7348                 break;
7349         default:
7350                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7351                 ret = -EINVAL;
7352                 break;
7353         }
7354
7355         return ret;
7356 }
7357
7358 /* Disable e-tag tunnel */
7359 static int
7360 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7361 {
7362         uint32_t etag_etype;
7363
7364         if (hw->mac.type != ixgbe_mac_X550 &&
7365             hw->mac.type != ixgbe_mac_X550EM_x &&
7366             hw->mac.type != ixgbe_mac_X550EM_a) {
7367                 return -ENOTSUP;
7368         }
7369
7370         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7371         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7372         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7373         IXGBE_WRITE_FLUSH(hw);
7374
7375         return 0;
7376 }
7377
7378 /* Disable l2 tunnel */
7379 static int
7380 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7381                             enum rte_eth_tunnel_type l2_tunnel_type)
7382 {
7383         int ret = 0;
7384         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7385
7386         switch (l2_tunnel_type) {
7387         case RTE_L2_TUNNEL_TYPE_E_TAG:
7388                 ret = ixgbe_e_tag_disable(hw);
7389                 break;
7390         default:
7391                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7392                 ret = -EINVAL;
7393                 break;
7394         }
7395
7396         return ret;
7397 }
7398
7399 static int
7400 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7401                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7402 {
7403         int ret = 0;
7404         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7405         uint32_t i, rar_entries;
7406         uint32_t rar_low, rar_high;
7407
7408         if (hw->mac.type != ixgbe_mac_X550 &&
7409             hw->mac.type != ixgbe_mac_X550EM_x &&
7410             hw->mac.type != ixgbe_mac_X550EM_a) {
7411                 return -ENOTSUP;
7412         }
7413
7414         rar_entries = ixgbe_get_num_rx_addrs(hw);
7415
7416         for (i = 1; i < rar_entries; i++) {
7417                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7418                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7419                 if ((rar_high & IXGBE_RAH_AV) &&
7420                     (rar_high & IXGBE_RAH_ADTYPE) &&
7421                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7422                      l2_tunnel->tunnel_id)) {
7423                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7424                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7425
7426                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7427
7428                         return ret;
7429                 }
7430         }
7431
7432         return ret;
7433 }
7434
7435 static int
7436 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7437                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7438 {
7439         int ret = 0;
7440         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7441         uint32_t i, rar_entries;
7442         uint32_t rar_low, rar_high;
7443
7444         if (hw->mac.type != ixgbe_mac_X550 &&
7445             hw->mac.type != ixgbe_mac_X550EM_x &&
7446             hw->mac.type != ixgbe_mac_X550EM_a) {
7447                 return -ENOTSUP;
7448         }
7449
7450         /* One entry for one tunnel. Try to remove potential existing entry. */
7451         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7452
7453         rar_entries = ixgbe_get_num_rx_addrs(hw);
7454
7455         for (i = 1; i < rar_entries; i++) {
7456                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7457                 if (rar_high & IXGBE_RAH_AV) {
7458                         continue;
7459                 } else {
7460                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7461                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7462                         rar_low = l2_tunnel->tunnel_id;
7463
7464                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7465                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7466
7467                         return ret;
7468                 }
7469         }
7470
7471         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7472                      " Please remove a rule before adding a new one.");
7473         return -EINVAL;
7474 }
7475
7476 static inline struct ixgbe_l2_tn_filter *
7477 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7478                           struct ixgbe_l2_tn_key *key)
7479 {
7480         int ret;
7481
7482         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7483         if (ret < 0)
7484                 return NULL;
7485
7486         return l2_tn_info->hash_map[ret];
7487 }
7488
7489 static inline int
7490 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7491                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7492 {
7493         int ret;
7494
7495         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7496                                &l2_tn_filter->key);
7497
7498         if (ret < 0) {
7499                 PMD_DRV_LOG(ERR,
7500                             "Failed to insert L2 tunnel filter"
7501                             " to hash table %d!",
7502                             ret);
7503                 return ret;
7504         }
7505
7506         l2_tn_info->hash_map[ret] = l2_tn_filter;
7507
7508         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7509
7510         return 0;
7511 }
7512
7513 static inline int
7514 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7515                           struct ixgbe_l2_tn_key *key)
7516 {
7517         int ret;
7518         struct ixgbe_l2_tn_filter *l2_tn_filter;
7519
7520         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7521
7522         if (ret < 0) {
7523                 PMD_DRV_LOG(ERR,
7524                             "No such L2 tunnel filter to delete %d!",
7525                             ret);
7526                 return ret;
7527         }
7528
7529         l2_tn_filter = l2_tn_info->hash_map[ret];
7530         l2_tn_info->hash_map[ret] = NULL;
7531
7532         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7533         rte_free(l2_tn_filter);
7534
7535         return 0;
7536 }
7537
7538 /* Add l2 tunnel filter */
7539 static int
7540 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7541                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7542 {
7543         int ret;
7544         struct ixgbe_l2_tn_info *l2_tn_info =
7545                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7546         struct ixgbe_l2_tn_key key;
7547         struct ixgbe_l2_tn_filter *node;
7548
7549         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7550         key.tn_id = l2_tunnel->tunnel_id;
7551
7552         node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7553
7554         if (node) {
7555                 PMD_DRV_LOG(ERR, "The L2 tunnel filter already exists!");
7556                 return -EINVAL;
7557         }
7558
7559         node = rte_zmalloc("ixgbe_l2_tn",
7560                            sizeof(struct ixgbe_l2_tn_filter),
7561                            0);
7562         if (!node)
7563                 return -ENOMEM;
7564
7565         (void)rte_memcpy(&node->key,
7566                          &key,
7567                          sizeof(struct ixgbe_l2_tn_key));
7568         node->pool = l2_tunnel->pool;
7569         ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7570         if (ret < 0) {
7571                 rte_free(node);
7572                 return ret;
7573         }
7574
7575         switch (l2_tunnel->l2_tunnel_type) {
7576         case RTE_L2_TUNNEL_TYPE_E_TAG:
7577                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7578                 break;
7579         default:
7580                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7581                 ret = -EINVAL;
7582                 break;
7583         }
7584
7585         if (ret < 0)
7586                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7587
7588         return ret;
7589 }
7590
7591 /* Delete l2 tunnel filter */
7592 static int
7593 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7594                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7595 {
7596         int ret;
7597         struct ixgbe_l2_tn_info *l2_tn_info =
7598                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7599         struct ixgbe_l2_tn_key key;
7600
7601         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7602         key.tn_id = l2_tunnel->tunnel_id;
7603         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7604         if (ret < 0)
7605                 return ret;
7606
7607         switch (l2_tunnel->l2_tunnel_type) {
7608         case RTE_L2_TUNNEL_TYPE_E_TAG:
7609                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7610                 break;
7611         default:
7612                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7613                 ret = -EINVAL;
7614                 break;
7615         }
7616
7617         return ret;
7618 }
7619
7620 /**
7621  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7622  * @dev: pointer to rte_eth_dev structure
7623  * @filter_op:operation will be taken.
7624  * @arg: a pointer to specific structure corresponding to the filter_op
7625  */
7626 static int
7627 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7628                                   enum rte_filter_op filter_op,
7629                                   void *arg)
7630 {
7631         int ret;
7632
7633         if (filter_op == RTE_ETH_FILTER_NOP)
7634                 return 0;
7635
7636         if (arg == NULL) {
7637                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7638                             filter_op);
7639                 return -EINVAL;
7640         }
7641
7642         switch (filter_op) {
7643         case RTE_ETH_FILTER_ADD:
7644                 ret = ixgbe_dev_l2_tunnel_filter_add
7645                         (dev,
7646                          (struct rte_eth_l2_tunnel_conf *)arg);
7647                 break;
7648         case RTE_ETH_FILTER_DELETE:
7649                 ret = ixgbe_dev_l2_tunnel_filter_del
7650                         (dev,
7651                          (struct rte_eth_l2_tunnel_conf *)arg);
7652                 break;
7653         default:
7654                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7655                 ret = -EINVAL;
7656                 break;
7657         }
7658         return ret;
7659 }
7660
7661 static int
7662 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7663 {
7664         int ret = 0;
7665         uint32_t ctrl;
7666         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7667
7668         if (hw->mac.type != ixgbe_mac_X550 &&
7669             hw->mac.type != ixgbe_mac_X550EM_x &&
7670             hw->mac.type != ixgbe_mac_X550EM_a) {
7671                 return -ENOTSUP;
7672         }
7673
7674         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7675         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7676         if (en)
7677                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7678         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7679
7680         return ret;
7681 }
7682
7683 /* Enable l2 tunnel forwarding */
7684 static int
7685 ixgbe_dev_l2_tunnel_forwarding_enable
7686         (struct rte_eth_dev *dev,
7687          enum rte_eth_tunnel_type l2_tunnel_type)
7688 {
7689         int ret = 0;
7690
7691         switch (l2_tunnel_type) {
7692         case RTE_L2_TUNNEL_TYPE_E_TAG:
7693                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7694                 break;
7695         default:
7696                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7697                 ret = -EINVAL;
7698                 break;
7699         }
7700
7701         return ret;
7702 }
7703
7704 /* Disable l2 tunnel forwarding */
7705 static int
7706 ixgbe_dev_l2_tunnel_forwarding_disable
7707         (struct rte_eth_dev *dev,
7708          enum rte_eth_tunnel_type l2_tunnel_type)
7709 {
7710         int ret = 0;
7711
7712         switch (l2_tunnel_type) {
7713         case RTE_L2_TUNNEL_TYPE_E_TAG:
7714                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7715                 break;
7716         default:
7717                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7718                 ret = -EINVAL;
7719                 break;
7720         }
7721
7722         return ret;
7723 }
7724
7725 static int
7726 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7727                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7728                              bool en)
7729 {
7730         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7731         int ret = 0;
7732         uint32_t vmtir, vmvir;
7733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7734
7735         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7736                 PMD_DRV_LOG(ERR,
7737                             "VF id %u should be less than %u",
7738                             l2_tunnel->vf_id,
7739                             pci_dev->max_vfs);
7740                 return -EINVAL;
7741         }
7742
7743         if (hw->mac.type != ixgbe_mac_X550 &&
7744             hw->mac.type != ixgbe_mac_X550EM_x &&
7745             hw->mac.type != ixgbe_mac_X550EM_a) {
7746                 return -ENOTSUP;
7747         }
7748
7749         if (en)
7750                 vmtir = l2_tunnel->tunnel_id;
7751         else
7752                 vmtir = 0;
7753
7754         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7755
7756         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7757         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7758         if (en)
7759                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7760         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7761
7762         return ret;
7763 }
7764
7765 /* Enable l2 tunnel tag insertion */
7766 static int
7767 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7768                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7769 {
7770         int ret = 0;
7771
7772         switch (l2_tunnel->l2_tunnel_type) {
7773         case RTE_L2_TUNNEL_TYPE_E_TAG:
7774                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7775                 break;
7776         default:
7777                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7778                 ret = -EINVAL;
7779                 break;
7780         }
7781
7782         return ret;
7783 }
7784
7785 /* Disable l2 tunnel tag insertion */
7786 static int
7787 ixgbe_dev_l2_tunnel_insertion_disable
7788         (struct rte_eth_dev *dev,
7789          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7790 {
7791         int ret = 0;
7792
7793         switch (l2_tunnel->l2_tunnel_type) {
7794         case RTE_L2_TUNNEL_TYPE_E_TAG:
7795                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7796                 break;
7797         default:
7798                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7799                 ret = -EINVAL;
7800                 break;
7801         }
7802
7803         return ret;
7804 }
7805
7806 static int
7807 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7808                              bool en)
7809 {
7810         int ret = 0;
7811         uint32_t qde;
7812         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7813
7814         if (hw->mac.type != ixgbe_mac_X550 &&
7815             hw->mac.type != ixgbe_mac_X550EM_x &&
7816             hw->mac.type != ixgbe_mac_X550EM_a) {
7817                 return -ENOTSUP;
7818         }
7819
7820         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7821         if (en)
7822                 qde |= IXGBE_QDE_STRIP_TAG;
7823         else
7824                 qde &= ~IXGBE_QDE_STRIP_TAG;
7825         qde &= ~IXGBE_QDE_READ;
7826         qde |= IXGBE_QDE_WRITE;
7827         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7828
7829         return ret;
7830 }
7831
7832 /* Enable l2 tunnel tag stripping */
7833 static int
7834 ixgbe_dev_l2_tunnel_stripping_enable
7835         (struct rte_eth_dev *dev,
7836          enum rte_eth_tunnel_type l2_tunnel_type)
7837 {
7838         int ret = 0;
7839
7840         switch (l2_tunnel_type) {
7841         case RTE_L2_TUNNEL_TYPE_E_TAG:
7842                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7843                 break;
7844         default:
7845                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7846                 ret = -EINVAL;
7847                 break;
7848         }
7849
7850         return ret;
7851 }
7852
7853 /* Disable l2 tunnel tag stripping */
7854 static int
7855 ixgbe_dev_l2_tunnel_stripping_disable
7856         (struct rte_eth_dev *dev,
7857          enum rte_eth_tunnel_type l2_tunnel_type)
7858 {
7859         int ret = 0;
7860
7861         switch (l2_tunnel_type) {
7862         case RTE_L2_TUNNEL_TYPE_E_TAG:
7863                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7864                 break;
7865         default:
7866                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7867                 ret = -EINVAL;
7868                 break;
7869         }
7870
7871         return ret;
7872 }
7873
7874 /* Enable/disable l2 tunnel offload functions */
7875 static int
7876 ixgbe_dev_l2_tunnel_offload_set
7877         (struct rte_eth_dev *dev,
7878          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7879          uint32_t mask,
7880          uint8_t en)
7881 {
7882         int ret = 0;
7883
7884         if (l2_tunnel == NULL)
7885                 return -EINVAL;
7886
7887         ret = -EINVAL;
7888         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7889                 if (en)
7890                         ret = ixgbe_dev_l2_tunnel_enable(
7891                                 dev,
7892                                 l2_tunnel->l2_tunnel_type);
7893                 else
7894                         ret = ixgbe_dev_l2_tunnel_disable(
7895                                 dev,
7896                                 l2_tunnel->l2_tunnel_type);
7897         }
7898
7899         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7900                 if (en)
7901                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7902                                 dev,
7903                                 l2_tunnel);
7904                 else
7905                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7906                                 dev,
7907                                 l2_tunnel);
7908         }
7909
7910         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7911                 if (en)
7912                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7913                                 dev,
7914                                 l2_tunnel->l2_tunnel_type);
7915                 else
7916                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7917                                 dev,
7918                                 l2_tunnel->l2_tunnel_type);
7919         }
7920
7921         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7922                 if (en)
7923                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7924                                 dev,
7925                                 l2_tunnel->l2_tunnel_type);
7926                 else
7927                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7928                                 dev,
7929                                 l2_tunnel->l2_tunnel_type);
7930         }
7931
7932         return ret;
7933 }
7934
7935 static int
7936 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7937                         uint16_t port)
7938 {
7939         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7940         IXGBE_WRITE_FLUSH(hw);
7941
7942         return 0;
7943 }
7944
7945 /* There's only one register for VxLAN UDP port.
7946  * So, we cannot add several ports. Will update it.
7947  */
7948 static int
7949 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7950                      uint16_t port)
7951 {
7952         if (port == 0) {
7953                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7954                 return -EINVAL;
7955         }
7956
7957         return ixgbe_update_vxlan_port(hw, port);
7958 }
7959
7960 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7961  * UDP port, it must have a value.
7962  * So, will reset it to the original value 0.
7963  */
7964 static int
7965 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7966                      uint16_t port)
7967 {
7968         uint16_t cur_port;
7969
7970         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7971
7972         if (cur_port != port) {
7973                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7974                 return -EINVAL;
7975         }
7976
7977         return ixgbe_update_vxlan_port(hw, 0);
7978 }
7979
7980 /* Add UDP tunneling port */
7981 static int
7982 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7983                               struct rte_eth_udp_tunnel *udp_tunnel)
7984 {
7985         int ret = 0;
7986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7987
7988         if (hw->mac.type != ixgbe_mac_X550 &&
7989             hw->mac.type != ixgbe_mac_X550EM_x &&
7990             hw->mac.type != ixgbe_mac_X550EM_a) {
7991                 return -ENOTSUP;
7992         }
7993
7994         if (udp_tunnel == NULL)
7995                 return -EINVAL;
7996
7997         switch (udp_tunnel->prot_type) {
7998         case RTE_TUNNEL_TYPE_VXLAN:
7999                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8000                 break;
8001
8002         case RTE_TUNNEL_TYPE_GENEVE:
8003         case RTE_TUNNEL_TYPE_TEREDO:
8004                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8005                 ret = -EINVAL;
8006                 break;
8007
8008         default:
8009                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8010                 ret = -EINVAL;
8011                 break;
8012         }
8013
8014         return ret;
8015 }
8016
8017 /* Remove UDP tunneling port */
8018 static int
8019 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8020                               struct rte_eth_udp_tunnel *udp_tunnel)
8021 {
8022         int ret = 0;
8023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8024
8025         if (hw->mac.type != ixgbe_mac_X550 &&
8026             hw->mac.type != ixgbe_mac_X550EM_x &&
8027             hw->mac.type != ixgbe_mac_X550EM_a) {
8028                 return -ENOTSUP;
8029         }
8030
8031         if (udp_tunnel == NULL)
8032                 return -EINVAL;
8033
8034         switch (udp_tunnel->prot_type) {
8035         case RTE_TUNNEL_TYPE_VXLAN:
8036                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8037                 break;
8038         case RTE_TUNNEL_TYPE_GENEVE:
8039         case RTE_TUNNEL_TYPE_TEREDO:
8040                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8041                 ret = -EINVAL;
8042                 break;
8043         default:
8044                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8045                 ret = -EINVAL;
8046                 break;
8047         }
8048
8049         return ret;
8050 }
8051
8052 static void
8053 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8054 {
8055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8056
8057         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8058 }
8059
8060 static void
8061 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8062 {
8063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8064
8065         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8066 }
8067
8068 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8069 {
8070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8071         u32 in_msg = 0;
8072
8073         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8074                 return;
8075
8076         /* PF reset VF event */
8077         if (in_msg == IXGBE_PF_CONTROL_MSG)
8078                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8079 }
8080
8081 static int
8082 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8083 {
8084         uint32_t eicr;
8085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8086         struct ixgbe_interrupt *intr =
8087                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8088         ixgbevf_intr_disable(hw);
8089
8090         /* read-on-clear nic registers here */
8091         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8092         intr->flags = 0;
8093
8094         /* only one misc vector supported - mailbox */
8095         eicr &= IXGBE_VTEICR_MASK;
8096         if (eicr == IXGBE_MISC_VEC_ID)
8097                 intr->flags |= IXGBE_FLAG_MAILBOX;
8098
8099         return 0;
8100 }
8101
8102 static int
8103 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8104 {
8105         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8106         struct ixgbe_interrupt *intr =
8107                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8108
8109         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8110                 ixgbevf_mbx_process(dev);
8111                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8112         }
8113
8114         ixgbevf_intr_enable(hw);
8115
8116         return 0;
8117 }
8118
8119 static void
8120 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8121                               void *param)
8122 {
8123         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8124
8125         ixgbevf_dev_interrupt_get_status(dev);
8126         ixgbevf_dev_interrupt_action(dev);
8127 }
8128
8129 /**
8130  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8131  *  @hw: pointer to hardware structure
8132  *
8133  *  Stops the transmit data path and waits for the HW to internally empty
8134  *  the Tx security block
8135  **/
8136 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8137 {
8138 #define IXGBE_MAX_SECTX_POLL 40
8139
8140         int i;
8141         int sectxreg;
8142
8143         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8144         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8145         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8146         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8147                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8148                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8149                         break;
8150                 /* Use interrupt-safe sleep just in case */
8151                 usec_delay(1000);
8152         }
8153
8154         /* For informational purposes only */
8155         if (i >= IXGBE_MAX_SECTX_POLL)
8156                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8157                          "path fully disabled.  Continuing with init.\n");
8158
8159         return IXGBE_SUCCESS;
8160 }
8161
8162 /**
8163  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8164  *  @hw: pointer to hardware structure
8165  *
8166  *  Enables the transmit data path.
8167  **/
8168 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8169 {
8170         uint32_t sectxreg;
8171
8172         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8173         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8174         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8175         IXGBE_WRITE_FLUSH(hw);
8176
8177         return IXGBE_SUCCESS;
8178 }
8179
8180 int
8181 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8182 {
8183         struct ixgbe_hw *hw;
8184         struct rte_eth_dev *dev;
8185         uint32_t ctrl;
8186
8187         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8188
8189         dev = &rte_eth_devices[port];
8190         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8191
8192         /* Stop the data paths */
8193         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8194                 return -ENOTSUP;
8195         /*
8196          * Workaround:
8197          * As no ixgbe_disable_sec_rx_path equivalent is
8198          * implemented for tx in the base code, and we are
8199          * not allowed to modify the base code in DPDK, so
8200          * just call the hand-written one directly for now.
8201          * The hardware support has been checked by
8202          * ixgbe_disable_sec_rx_path().
8203          */
8204         ixgbe_disable_sec_tx_path_generic(hw);
8205
8206         /* Enable Ethernet CRC (required by MACsec offload) */
8207         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8208         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8209         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8210
8211         /* Enable the TX and RX crypto engines */
8212         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8213         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8214         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8215
8216         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8217         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8218         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8219
8220         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8221         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8222         ctrl |= 0x3;
8223         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8224
8225         /* Enable SA lookup */
8226         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8227         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8228         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8229                      IXGBE_LSECTXCTRL_AUTH;
8230         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8231         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8232         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8233         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8234
8235         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8236         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8237         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8238         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8239         if (rp)
8240                 ctrl |= IXGBE_LSECRXCTRL_RP;
8241         else
8242                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8243         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8244
8245         /* Start the data paths */
8246         ixgbe_enable_sec_rx_path(hw);
8247         /*
8248          * Workaround:
8249          * As no ixgbe_enable_sec_rx_path equivalent is
8250          * implemented for tx in the base code, and we are
8251          * not allowed to modify the base code in DPDK, so
8252          * just call the hand-written one directly for now.
8253          */
8254         ixgbe_enable_sec_tx_path_generic(hw);
8255
8256         return 0;
8257 }
8258
8259 int
8260 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8261 {
8262         struct ixgbe_hw *hw;
8263         struct rte_eth_dev *dev;
8264         uint32_t ctrl;
8265
8266         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8267
8268         dev = &rte_eth_devices[port];
8269         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8270
8271         /* Stop the data paths */
8272         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8273                 return -ENOTSUP;
8274         /*
8275          * Workaround:
8276          * As no ixgbe_disable_sec_rx_path equivalent is
8277          * implemented for tx in the base code, and we are
8278          * not allowed to modify the base code in DPDK, so
8279          * just call the hand-written one directly for now.
8280          * The hardware support has been checked by
8281          * ixgbe_disable_sec_rx_path().
8282          */
8283         ixgbe_disable_sec_tx_path_generic(hw);
8284
8285         /* Disable the TX and RX crypto engines */
8286         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8287         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8288         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8289
8290         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8291         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8292         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8293
8294         /* Disable SA lookup */
8295         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8296         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8297         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8298         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8299
8300         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8301         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8302         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8303         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8304
8305         /* Start the data paths */
8306         ixgbe_enable_sec_rx_path(hw);
8307         /*
8308          * Workaround:
8309          * As no ixgbe_enable_sec_rx_path equivalent is
8310          * implemented for tx in the base code, and we are
8311          * not allowed to modify the base code in DPDK, so
8312          * just call the hand-written one directly for now.
8313          */
8314         ixgbe_enable_sec_tx_path_generic(hw);
8315
8316         return 0;
8317 }
8318
8319 int
8320 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8321 {
8322         struct ixgbe_hw *hw;
8323         struct rte_eth_dev *dev;
8324         uint32_t ctrl;
8325
8326         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8327
8328         dev = &rte_eth_devices[port];
8329         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8330
8331         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8332         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8333
8334         ctrl = mac[4] | (mac[5] << 8);
8335         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8336
8337         return 0;
8338 }
8339
8340 int
8341 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8342 {
8343         struct ixgbe_hw *hw;
8344         struct rte_eth_dev *dev;
8345         uint32_t ctrl;
8346
8347         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8348
8349         dev = &rte_eth_devices[port];
8350         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8351
8352         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8353         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8354
8355         pi = rte_cpu_to_be_16(pi);
8356         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8357         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8358
8359         return 0;
8360 }
8361
8362 int
8363 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8364                                  uint32_t pn, uint8_t *key)
8365 {
8366         struct ixgbe_hw *hw;
8367         struct rte_eth_dev *dev;
8368         uint32_t ctrl, i;
8369
8370         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8371
8372         dev = &rte_eth_devices[port];
8373         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8374
8375         if (idx != 0 && idx != 1)
8376                 return -EINVAL;
8377
8378         if (an >= 4)
8379                 return -EINVAL;
8380
8381         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8382
8383         /* Set the PN and key */
8384         pn = rte_cpu_to_be_32(pn);
8385         if (idx == 0) {
8386                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8387
8388                 for (i = 0; i < 4; i++) {
8389                         ctrl = (key[i * 4 + 0] <<  0) |
8390                                (key[i * 4 + 1] <<  8) |
8391                                (key[i * 4 + 2] << 16) |
8392                                (key[i * 4 + 3] << 24);
8393                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8394                 }
8395         } else {
8396                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8397
8398                 for (i = 0; i < 4; i++) {
8399                         ctrl = (key[i * 4 + 0] <<  0) |
8400                                (key[i * 4 + 1] <<  8) |
8401                                (key[i * 4 + 2] << 16) |
8402                                (key[i * 4 + 3] << 24);
8403                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8404                 }
8405         }
8406
8407         /* Set AN and select the SA */
8408         ctrl = (an << idx * 2) | (idx << 4);
8409         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8410
8411         return 0;
8412 }
8413
8414 int
8415 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8416                                  uint32_t pn, uint8_t *key)
8417 {
8418         struct ixgbe_hw *hw;
8419         struct rte_eth_dev *dev;
8420         uint32_t ctrl, i;
8421
8422         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8423
8424         dev = &rte_eth_devices[port];
8425         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8426
8427         if (idx != 0 && idx != 1)
8428                 return -EINVAL;
8429
8430         if (an >= 4)
8431                 return -EINVAL;
8432
8433         /* Set the PN */
8434         pn = rte_cpu_to_be_32(pn);
8435         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8436
8437         /* Set the key */
8438         for (i = 0; i < 4; i++) {
8439                 ctrl = (key[i * 4 + 0] <<  0) |
8440                        (key[i * 4 + 1] <<  8) |
8441                        (key[i * 4 + 2] << 16) |
8442                        (key[i * 4 + 3] << 24);
8443                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8444         }
8445
8446         /* Set the AN and validate the SA */
8447         ctrl = an | (1 << 2);
8448         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8449
8450         return 0;
8451 }
8452
8453 /* restore n-tuple filter */
8454 static inline void
8455 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8456 {
8457         struct ixgbe_filter_info *filter_info =
8458                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8459         struct ixgbe_5tuple_filter *node;
8460
8461         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8462                 ixgbe_inject_5tuple_filter(dev, node);
8463         }
8464 }
8465
8466 /* restore ethernet type filter */
8467 static inline void
8468 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8469 {
8470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8471         struct ixgbe_filter_info *filter_info =
8472                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8473         int i;
8474
8475         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8476                 if (filter_info->ethertype_mask & (1 << i)) {
8477                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8478                                         filter_info->ethertype_filters[i].etqf);
8479                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8480                                         filter_info->ethertype_filters[i].etqs);
8481                         IXGBE_WRITE_FLUSH(hw);
8482                 }
8483         }
8484 }
8485
8486 /* restore SYN filter */
8487 static inline void
8488 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8489 {
8490         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8491         struct ixgbe_filter_info *filter_info =
8492                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8493         uint32_t synqf;
8494
8495         synqf = filter_info->syn_info;
8496
8497         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8498                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8499                 IXGBE_WRITE_FLUSH(hw);
8500         }
8501 }
8502
8503 static int
8504 ixgbe_filter_restore(struct rte_eth_dev *dev)
8505 {
8506         ixgbe_ntuple_filter_restore(dev);
8507         ixgbe_ethertype_filter_restore(dev);
8508         ixgbe_syn_filter_restore(dev);
8509         ixgbe_fdir_filter_restore(dev);
8510
8511         return 0;
8512 }
8513
8514 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8515 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8516 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8517 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8518 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8519 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");