drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 #define IXGBE_HKEY_MAX_INDEX 10
 104
 105 /* Additional timesync values. */
 106 #define NSEC_PER_SEC             1000000000L
 107 #define IXGBE_INCVAL_10GB        0x66666666
 108 #define IXGBE_INCVAL_1GB         0x40000000
 109 #define IXGBE_INCVAL_100         0x50000000
 110 #define IXGBE_INCVAL_SHIFT_10GB  28
 111 #define IXGBE_INCVAL_SHIFT_1GB   24
 112 #define IXGBE_INCVAL_SHIFT_100   21
 113 #define IXGBE_INCVAL_SHIFT_82599 7
 114 #define IXGBE_INCPER_SHIFT_82599 24
 115
 116 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 117
 118 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 119 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 120 #define DEFAULT_ETAG_ETYPE                     0x893f
 121 #define IXGBE_ETAG_ETYPE                       0x00005084
 122 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 123 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 124 #define IXGBE_RAH_ADTYPE                       0x40000000
 125 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 126 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 127 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 128 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 129 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 130 #define IXGBE_VTEICR_MASK                      0x07
 131
 132 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 133 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 134
 135 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 136 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 154                                 int wait_to_complete);
 155 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *stats);
 157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstat *xstats, unsigned n);
 159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 160                                   struct rte_eth_xstat *xstats, unsigned n);
 161 static int
 162 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 163                 uint64_t *values, unsigned int n);
 164 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         unsigned int size);
 169 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 171 static int ixgbe_dev_xstats_get_names_by_id(
 172         struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names,
 174         const uint64_t *ids,
 175         unsigned int limit);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 181                                  size_t fw_size);
 182 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 183                                struct rte_eth_dev_info *dev_info);
 184 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 185 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 186                                  struct rte_eth_dev_info *dev_info);
 187 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 188
 189 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 190                 uint16_t vlan_id, int on);
 191 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 192                                enum rte_vlan_type vlan_type,
 193                                uint16_t tpid_id);
 194 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 195                 uint16_t queue, bool on);
 196 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 197                 int on);
 198 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 200 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 201 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 202 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 203
 204 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 205 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 206 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 209                                struct rte_eth_fc_conf *fc_conf);
 210 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 211                 struct rte_eth_pfc_conf *pfc_conf);
 212 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 220 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 224                                       struct rte_intr_handle *handle);
 225 static void ixgbe_dev_interrupt_handler(void *param);
 226 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 227 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 228                          uint32_t index, uint32_t pool);
 229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 230 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 231                                            struct ether_addr *mac_addr);
 232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 233 static bool is_device_supported(struct rte_eth_dev *dev,
 234                                 struct rte_pci_driver *drv);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 242                                    int wait_to_complete);
 243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 247 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 249                 struct rte_eth_stats *stats);
 250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 252                 uint16_t vlan_id, int on);
 253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                 uint16_t queue, int on);
 255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 258                                             uint16_t queue_id);
 259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 260                                              uint16_t queue_id);
 261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 262                                  uint8_t queue, uint8_t msix_vector);
 263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 266
 267 /* For Eth VMDQ APIs support */
 268 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 269                 ether_addr * mac_addr, uint8_t on);
 270 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 271 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 272                 struct rte_eth_mirror_conf *mirror_conf,
 273                 uint8_t rule_id, uint8_t on);
 274 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 275                 uint8_t rule_id);
 276 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                           uint16_t queue_id);
 278 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                            uint16_t queue_id);
 280 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                uint8_t queue, uint8_t msix_vector);
 282 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 283
 284 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                 struct ether_addr *mac_addr,
 286                                 uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter);
 292 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 293                         enum rte_filter_op filter_op,
 294                         void *arg);
 295 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 298                         struct ixgbe_5tuple_filter *filter);
 299 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 300                                 enum rte_filter_op filter_op,
 301                                 void *arg);
 302 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter);
 304 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 305                                 enum rte_filter_op filter_op,
 306                                 void *arg);
 307 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 308                         struct rte_eth_ethertype_filter *filter);
 309 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 310                      enum rte_filter_type filter_type,
 311                      enum rte_filter_op filter_op,
 312                      void *arg);
 313 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 314
 315 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 316                                       struct ether_addr *mc_addr_set,
 317                                       uint32_t nb_mc_addr);
 318 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 319                                    struct rte_eth_dcb_info *dcb_info);
 320
 321 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 323                             struct rte_dev_reg_info *regs);
 324 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 325 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 328                                 struct rte_dev_eeprom_info *eeprom);
 329
 330 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 331 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 332                                 struct rte_dev_reg_info *regs);
 333
 334 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 335 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 337                                             struct timespec *timestamp,
 338                                             uint32_t flags);
 339 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp);
 341 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 342 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 343                                    struct timespec *timestamp);
 344 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 345                                    const struct timespec *timestamp);
 346 static void ixgbevf_dev_interrupt_handler(void *param);
 347
 348 static int ixgbe_dev_l2_tunnel_eth_type_conf
 349         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 350 static int ixgbe_dev_l2_tunnel_offload_set
 351         (struct rte_eth_dev *dev,
 352          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 353          uint32_t mask,
 354          uint8_t en);
 355 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 356                                              enum rte_filter_op filter_op,
 357                                              void *arg);
 358
 359 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 360                                          struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 364 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 365
 366 /*
 367  * Define VF Stats MACRO for Non "cleared on read" register
 368  */
 369 #define UPDATE_VF_STAT(reg, last, cur)                          \
 370 {                                                               \
 371         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 372         cur += (latest - last) & UINT_MAX;                      \
 373         last = latest;                                          \
 374 }
 375
 376 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 377 {                                                                \
 378         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 379         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 380         u64 latest = ((new_msb << 32) | new_lsb);                \
 381         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 382         last = latest;                                           \
 383 }
 384
 385 #define IXGBE_SET_HWSTRIP(h, q) do {\
 386                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 387                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 388                 (h)->bitmap[idx] |= 1 << bit;\
 389         } while (0)
 390
 391 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 392                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] &= ~(1 << bit);\
 395         } while (0)
 396
 397 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 398                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 400                 (r) = (h)->bitmap[idx] >> bit & 1;\
 401         } while (0)
 402
 403 int ixgbe_logtype_init;
 404 int ixgbe_logtype_driver;
 405
 406 /*
 407  * The set of PCI devices this driver supports
 408  */
 409 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 458 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 460 #endif
 461         { .vendor_id = 0, /* sentinel */ },
 462 };
 463
 464 /*
 465  * The set of PCI devices this driver supports (for 82599 VF)
 466  */
 467 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct rte_eth_desc_lim rx_desc_lim = {
 482         .nb_max = IXGBE_MAX_RING_DESC,
 483         .nb_min = IXGBE_MIN_RING_DESC,
 484         .nb_align = IXGBE_RXD_ALIGN,
 485 };
 486
 487 static const struct rte_eth_desc_lim tx_desc_lim = {
 488         .nb_max = IXGBE_MAX_RING_DESC,
 489         .nb_min = IXGBE_MIN_RING_DESC,
 490         .nb_align = IXGBE_TXD_ALIGN,
 491         .nb_seg_max = IXGBE_TX_MAX_SEG,
 492         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 493 };
 494
 495 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 496         .dev_configure        = ixgbe_dev_configure,
 497         .dev_start            = ixgbe_dev_start,
 498         .dev_stop             = ixgbe_dev_stop,
 499         .dev_set_link_up    = ixgbe_dev_set_link_up,
 500         .dev_set_link_down  = ixgbe_dev_set_link_down,
 501         .dev_close            = ixgbe_dev_close,
 502         .dev_reset            = ixgbe_dev_reset,
 503         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 504         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 505         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 506         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 507         .link_update          = ixgbe_dev_link_update,
 508         .stats_get            = ixgbe_dev_stats_get,
 509         .xstats_get           = ixgbe_dev_xstats_get,
 510         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 511         .stats_reset          = ixgbe_dev_stats_reset,
 512         .xstats_reset         = ixgbe_dev_xstats_reset,
 513         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 514         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 515         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 516         .fw_version_get       = ixgbe_fw_version_get,
 517         .dev_infos_get        = ixgbe_dev_info_get,
 518         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 519         .mtu_set              = ixgbe_dev_mtu_set,
 520         .vlan_filter_set      = ixgbe_vlan_filter_set,
 521         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 522         .vlan_offload_set     = ixgbe_vlan_offload_set,
 523         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 524         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 525         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 526         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 527         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 528         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 529         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 530         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 531         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 532         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 533         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 534         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 535         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 536         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 537         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 538         .dev_led_on           = ixgbe_dev_led_on,
 539         .dev_led_off          = ixgbe_dev_led_off,
 540         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 541         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 542         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 543         .mac_addr_add         = ixgbe_add_rar,
 544         .mac_addr_remove      = ixgbe_remove_rar,
 545         .mac_addr_set         = ixgbe_set_default_mac_addr,
 546         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 547         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 548         .mirror_rule_set      = ixgbe_mirror_rule_set,
 549         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 550         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 551         .reta_update          = ixgbe_dev_rss_reta_update,
 552         .reta_query           = ixgbe_dev_rss_reta_query,
 553         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 554         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 555         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 556         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 557         .rxq_info_get         = ixgbe_rxq_info_get,
 558         .txq_info_get         = ixgbe_txq_info_get,
 559         .timesync_enable      = ixgbe_timesync_enable,
 560         .timesync_disable     = ixgbe_timesync_disable,
 561         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 562         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 563         .get_reg              = ixgbe_get_regs,
 564         .get_eeprom_length    = ixgbe_get_eeprom_length,
 565         .get_eeprom           = ixgbe_get_eeprom,
 566         .set_eeprom           = ixgbe_set_eeprom,
 567         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 568         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 569         .timesync_read_time   = ixgbe_timesync_read_time,
 570         .timesync_write_time  = ixgbe_timesync_write_time,
 571         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 572         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 573         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 574         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 575         .tm_ops_get           = ixgbe_tm_ops_get,
 576 };
 577
 578 /*
 579  * dev_ops for virtual function, bare necessities for basic vf
 580  * operation have been implemented
 581  */
 582 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 583         .dev_configure        = ixgbevf_dev_configure,
 584         .dev_start            = ixgbevf_dev_start,
 585         .dev_stop             = ixgbevf_dev_stop,
 586         .link_update          = ixgbevf_dev_link_update,
 587         .stats_get            = ixgbevf_dev_stats_get,
 588         .xstats_get           = ixgbevf_dev_xstats_get,
 589         .stats_reset          = ixgbevf_dev_stats_reset,
 590         .xstats_reset         = ixgbevf_dev_stats_reset,
 591         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 592         .dev_close            = ixgbevf_dev_close,
 593         .dev_reset            = ixgbevf_dev_reset,
 594         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 595         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 596         .dev_infos_get        = ixgbevf_dev_info_get,
 597         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 598         .mtu_set              = ixgbevf_dev_set_mtu,
 599         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 600         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 601         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 602         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 603         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 604         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 605         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 606         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 607         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 608         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 609         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 610         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 611         .mac_addr_add         = ixgbevf_add_mac_addr,
 612         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 613         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 614         .rxq_info_get         = ixgbe_rxq_info_get,
 615         .txq_info_get         = ixgbe_txq_info_get,
 616         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 617         .get_reg              = ixgbevf_get_regs,
 618         .reta_update          = ixgbe_dev_rss_reta_update,
 619         .reta_query           = ixgbe_dev_rss_reta_query,
 620         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 621         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 622 };
 623
 624 /* store statistics names and its offset in stats structure */
 625 struct rte_ixgbe_xstats_name_off {
 626         char name[RTE_ETH_XSTATS_NAME_SIZE];
 627         unsigned offset;
 628 };
 629
 630 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 631         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 632         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 633         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 634         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 635         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 636         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 637         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 638         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 639         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 640         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 641         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 642         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 643         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 644         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 645         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 646                 prc1023)},
 647         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 648                 prc1522)},
 649         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 650         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 651         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 652         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 653         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 654         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 655         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 656         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 657         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 658         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 659         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 660         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 661         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 662         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 663         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 664         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 665         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 666                 ptc1023)},
 667         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 668                 ptc1522)},
 669         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 670         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 671         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 672         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 673
 674         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 675                 fdirustat_add)},
 676         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 677                 fdirustat_remove)},
 678         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 679                 fdirfstat_fadd)},
 680         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 681                 fdirfstat_fremove)},
 682         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 683                 fdirmatch)},
 684         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 685                 fdirmiss)},
 686
 687         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 688         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 689         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 690                 fclast)},
 691         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 692         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 693         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 694         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 695         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 696                 fcoe_noddp)},
 697         {"rx_fcoe_no_direct_data_placement_ext_buff",
 698                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 699
 700         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 701                 lxontxc)},
 702         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 703                 lxonrxc)},
 704         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxofftxc)},
 706         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxoffrxc)},
 708         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 709 };
 710
 711 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 712                            sizeof(rte_ixgbe_stats_strings[0]))
 713
 714 /* MACsec statistics */
 715 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 716         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 717                 out_pkts_untagged)},
 718         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 719                 out_pkts_encrypted)},
 720         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_protected)},
 722         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_octets_encrypted)},
 724         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_octets_protected)},
 726         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_untagged)},
 728         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_badtag)},
 730         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_nosci)},
 732         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_unknownsci)},
 734         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 735                 in_octets_decrypted)},
 736         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 737                 in_octets_validated)},
 738         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_unchecked)},
 740         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_delayed)},
 742         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_late)},
 744         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_ok)},
 746         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_invalid)},
 748         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_notvalid)},
 750         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_unusedsa)},
 752         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notusingsa)},
 754 };
 755
 756 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 757                            sizeof(rte_ixgbe_macsec_strings[0]))
 758
 759 /* Per-queue statistics */
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 761         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 762         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 763         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 764         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 765 };
 766
 767 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 768                            sizeof(rte_ixgbe_rxq_strings[0]))
 769 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 772         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 773         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 774         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 775                 pxon2offc)},
 776 };
 777
 778 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 779                            sizeof(rte_ixgbe_txq_strings[0]))
 780 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 781
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 783         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 784 };
 785
 786 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 787                 sizeof(rte_ixgbevf_stats_strings[0]))
 788
 789 /*
 790  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 791  */
 792 static inline int
 793 ixgbe_is_sfp(struct ixgbe_hw *hw)
 794 {
 795         switch (hw->phy.type) {
 796         case ixgbe_phy_sfp_avago:
 797         case ixgbe_phy_sfp_ftl:
 798         case ixgbe_phy_sfp_intel:
 799         case ixgbe_phy_sfp_unknown:
 800         case ixgbe_phy_sfp_passive_tyco:
 801         case ixgbe_phy_sfp_passive_unknown:
 802                 return 1;
 803         default:
 804                 return 0;
 805         }
 806 }
 807
 808 static inline int32_t
 809 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 810 {
 811         uint32_t ctrl_ext;
 812         int32_t status;
 813
 814         status = ixgbe_reset_hw(hw);
 815
 816         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 817         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 818         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 819         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 820         IXGBE_WRITE_FLUSH(hw);
 821
 822         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 823                 status = IXGBE_SUCCESS;
 824         return status;
 825 }
 826
 827 static inline void
 828 ixgbe_enable_intr(struct rte_eth_dev *dev)
 829 {
 830         struct ixgbe_interrupt *intr =
 831                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 832         struct ixgbe_hw *hw =
 833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 834
 835         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 836         IXGBE_WRITE_FLUSH(hw);
 837 }
 838
 839 /*
 840  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 841  */
 842 static void
 843 ixgbe_disable_intr(struct ixgbe_hw *hw)
 844 {
 845         PMD_INIT_FUNC_TRACE();
 846
 847         if (hw->mac.type == ixgbe_mac_82598EB) {
 848                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 849         } else {
 850                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 853         }
 854         IXGBE_WRITE_FLUSH(hw);
 855 }
 856
 857 /*
 858  * This function resets queue statistics mapping registers.
 859  * From Niantic datasheet, Initialization of Statistics section:
 860  * "...if software requires the queue counters, the RQSMR and TQSM registers
 861  * must be re-programmed following a device reset.
 862  */
 863 static void
 864 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 865 {
 866         uint32_t i;
 867
 868         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 869                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 870                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 871         }
 872 }
 873
 874
 875 static int
 876 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 877                                   uint16_t queue_id,
 878                                   uint8_t stat_idx,
 879                                   uint8_t is_rx)
 880 {
 881 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 882 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 883 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 884
 885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 886         struct ixgbe_stat_mapping_registers *stat_mappings =
 887                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 888         uint32_t qsmr_mask = 0;
 889         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 890         uint32_t q_map;
 891         uint8_t n, offset;
 892
 893         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 894                 (hw->mac.type != ixgbe_mac_X540) &&
 895                 (hw->mac.type != ixgbe_mac_X550) &&
 896                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 897                 (hw->mac.type != ixgbe_mac_X550EM_a))
 898                 return -ENOSYS;
 899
 900         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 901                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 902                      queue_id, stat_idx);
 903
 904         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 905         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 906                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 907                 return -EIO;
 908         }
 909         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 910
 911         /* Now clear any previous stat_idx set */
 912         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 913         if (!is_rx)
 914                 stat_mappings->tqsm[n] &= ~clearing_mask;
 915         else
 916                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 917
 918         q_map = (uint32_t)stat_idx;
 919         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 920         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 921         if (!is_rx)
 922                 stat_mappings->tqsm[n] |= qsmr_mask;
 923         else
 924                 stat_mappings->rqsmr[n] |= qsmr_mask;
 925
 926         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 927                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 928                      queue_id, stat_idx);
 929         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 930                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 931
 932         /* Now write the mapping in the appropriate register */
 933         if (is_rx) {
 934                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 935                              stat_mappings->rqsmr[n], n);
 936                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 937         } else {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 939                              stat_mappings->tqsm[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 941         }
 942         return 0;
 943 }
 944
 945 static void
 946 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 947 {
 948         struct ixgbe_stat_mapping_registers *stat_mappings =
 949                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951         int i;
 952
 953         /* write whatever was in stat mapping table to the NIC */
 954         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 /* rx */
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 957
 958                 /* tx */
 959                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 960         }
 961 }
 962
 963 static void
 964 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 965 {
 966         uint8_t i;
 967         struct ixgbe_dcb_tc_config *tc;
 968         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 969
 970         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 971         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 972         for (i = 0; i < dcb_max_tc; i++) {
 973                 tc = &dcb_config->tc_config[i];
 974                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 975                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 976                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 977                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 978                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 979                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 980                 tc->pfc = ixgbe_dcb_pfc_disabled;
 981         }
 982
 983         /* Initialize default user to priority mapping, UPx->TC0 */
 984         tc = &dcb_config->tc_config[0];
 985         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 986         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 987         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 988                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 989                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 990         }
 991         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 992         dcb_config->pfc_mode_enable = false;
 993         dcb_config->vt_mode = true;
 994         dcb_config->round_robin_enable = false;
 995         /* support all DCB capabilities in 82599 */
 996         dcb_config->support.capabilities = 0xFF;
 997
 998         /*we only support 4 Tcs for X540, X550 */
 999         if (hw->mac.type == ixgbe_mac_X540 ||
1000                 hw->mac.type == ixgbe_mac_X550 ||
1001                 hw->mac.type == ixgbe_mac_X550EM_x ||
1002                 hw->mac.type == ixgbe_mac_X550EM_a) {
1003                 dcb_config->num_tcs.pg_tcs = 4;
1004                 dcb_config->num_tcs.pfc_tcs = 4;
1005         }
1006 }
1007
1008 /*
1009  * Ensure that all locks are released before first NVM or PHY access
1010  */
1011 static void
1012 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1013 {
1014         uint16_t mask;
1015
1016         /*
1017          * Phy lock should not fail in this early stage. If this is the case,
1018          * it is due to an improper exit of the application.
1019          * So force the release of the faulty lock. Release of common lock
1020          * is done automatically by swfw_sync function.
1021          */
1022         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1023         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1024                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1025         }
1026         ixgbe_release_swfw_semaphore(hw, mask);
1027
1028         /*
1029          * These ones are more tricky since they are common to all ports; but
1030          * swfw_sync retries last long enough (1s) to be almost sure that if
1031          * lock can not be taken it is due to an improper lock of the
1032          * semaphore.
1033          */
1034         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1035         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1037         }
1038         ixgbe_release_swfw_semaphore(hw, mask);
1039 }
1040
1041 /*
1042  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1043  * It returns 0 on success.
1044  */
1045 static int
1046 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1047 {
1048         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1049         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1050         struct ixgbe_hw *hw =
1051                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1052         struct ixgbe_vfta *shadow_vfta =
1053                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1054         struct ixgbe_hwstrip *hwstrip =
1055                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1056         struct ixgbe_dcb_config *dcb_config =
1057                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1058         struct ixgbe_filter_info *filter_info =
1059                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1060         struct ixgbe_bw_conf *bw_conf =
1061                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1062         uint32_t ctrl_ext;
1063         uint16_t csum;
1064         int diag, i;
1065
1066         PMD_INIT_FUNC_TRACE();
1067
1068         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1069         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1070         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1071         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1072
1073         /*
1074          * For secondary processes, we don't initialise any further as primary
1075          * has already done this work. Only check we don't need a different
1076          * RX and TX function.
1077          */
1078         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1079                 struct ixgbe_tx_queue *txq;
1080                 /* TX queue function in primary, set by last queue initialized
1081                  * Tx queue may not initialized by primary process
1082                  */
1083                 if (eth_dev->data->tx_queues) {
1084                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1085                         ixgbe_set_tx_function(eth_dev, txq);
1086                 } else {
1087                         /* Use default TX function if we get here */
1088                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1089                                      "Using default TX function.");
1090                 }
1091
1092                 ixgbe_set_rx_function(eth_dev);
1093
1094                 return 0;
1095         }
1096
1097         rte_eth_copy_pci_info(eth_dev, pci_dev);
1098
1099         /* Vendor and Device ID need to be set before init of shared code */
1100         hw->device_id = pci_dev->id.device_id;
1101         hw->vendor_id = pci_dev->id.vendor_id;
1102         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1103         hw->allow_unsupported_sfp = 1;
1104
1105         /* Initialize the shared code (base driver) */
1106 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1107         diag = ixgbe_bypass_init_shared_code(hw);
1108 #else
1109         diag = ixgbe_init_shared_code(hw);
1110 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1111
1112         if (diag != IXGBE_SUCCESS) {
1113                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1114                 return -EIO;
1115         }
1116
1117         /* pick up the PCI bus settings for reporting later */
1118         ixgbe_get_bus_info(hw);
1119
1120         /* Unlock any pending hardware semaphore */
1121         ixgbe_swfw_lock_reset(hw);
1122
1123 #ifdef RTE_LIBRTE_SECURITY
1124         /* Initialize security_ctx only for primary process*/
1125         if (ixgbe_ipsec_ctx_create(eth_dev))
1126                 return -ENOMEM;
1127 #endif
1128
1129         /* Initialize DCB configuration*/
1130         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1131         ixgbe_dcb_init(hw, dcb_config);
1132         /* Get Hardware Flow Control setting */
1133         hw->fc.requested_mode = ixgbe_fc_full;
1134         hw->fc.current_mode = ixgbe_fc_full;
1135         hw->fc.pause_time = IXGBE_FC_PAUSE;
1136         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1137                 hw->fc.low_water[i] = IXGBE_FC_LO;
1138                 hw->fc.high_water[i] = IXGBE_FC_HI;
1139         }
1140         hw->fc.send_xon = 1;
1141
1142         /* Make sure we have a good EEPROM before we read from it */
1143         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1144         if (diag != IXGBE_SUCCESS) {
1145                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1146                 return -EIO;
1147         }
1148
1149 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1150         diag = ixgbe_bypass_init_hw(hw);
1151 #else
1152         diag = ixgbe_init_hw(hw);
1153 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1154
1155         /*
1156          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1157          * is called too soon after the kernel driver unbinding/binding occurs.
1158          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1159          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1160          * also called. See ixgbe_identify_phy_82599(). The reason for the
1161          * failure is not known, and only occuts when virtualisation features
1162          * are disabled in the bios. A delay of 100ms  was found to be enough by
1163          * trial-and-error, and is doubled to be safe.
1164          */
1165         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1166                 rte_delay_ms(200);
1167                 diag = ixgbe_init_hw(hw);
1168         }
1169
1170         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1171                 diag = IXGBE_SUCCESS;
1172
1173         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1174                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1175                              "LOM.  Please be aware there may be issues associated "
1176                              "with your hardware.");
1177                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1178                              "please contact your Intel or hardware representative "
1179                              "who provided you with this hardware.");
1180         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1181                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1182         if (diag) {
1183                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1184                 return -EIO;
1185         }
1186
1187         /* Reset the hw statistics */
1188         ixgbe_dev_stats_reset(eth_dev);
1189
1190         /* disable interrupt */
1191         ixgbe_disable_intr(hw);
1192
1193         /* reset mappings for queue statistics hw counters*/
1194         ixgbe_reset_qstat_mappings(hw);
1195
1196         /* Allocate memory for storing MAC addresses */
1197         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1198                                                hw->mac.num_rar_entries, 0);
1199         if (eth_dev->data->mac_addrs == NULL) {
1200                 PMD_INIT_LOG(ERR,
1201                              "Failed to allocate %u bytes needed to store "
1202                              "MAC addresses",
1203                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1204                 return -ENOMEM;
1205         }
1206         /* Copy the permanent MAC address */
1207         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1208                         &eth_dev->data->mac_addrs[0]);
1209
1210         /* Allocate memory for storing hash filter MAC addresses */
1211         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1212                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1213         if (eth_dev->data->hash_mac_addrs == NULL) {
1214                 PMD_INIT_LOG(ERR,
1215                              "Failed to allocate %d bytes needed to store MAC addresses",
1216                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1217                 return -ENOMEM;
1218         }
1219
1220         /* initialize the vfta */
1221         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1222
1223         /* initialize the hw strip bitmap*/
1224         memset(hwstrip, 0, sizeof(*hwstrip));
1225
1226         /* initialize PF if max_vfs not zero */
1227         ixgbe_pf_host_init(eth_dev);
1228
1229         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1230         /* let hardware know driver is loaded */
1231         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1232         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1233         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1234         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1235         IXGBE_WRITE_FLUSH(hw);
1236
1237         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1238                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1239                              (int) hw->mac.type, (int) hw->phy.type,
1240                              (int) hw->phy.sfp_type);
1241         else
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type);
1244
1245         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1246                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1247                      pci_dev->id.device_id);
1248
1249         rte_intr_callback_register(intr_handle,
1250                                    ixgbe_dev_interrupt_handler, eth_dev);
1251
1252         /* enable uio/vfio intr/eventfd mapping */
1253         rte_intr_enable(intr_handle);
1254
1255         /* enable support intr */
1256         ixgbe_enable_intr(eth_dev);
1257
1258         /* initialize filter info */
1259         memset(filter_info, 0,
1260                sizeof(struct ixgbe_filter_info));
1261
1262         /* initialize 5tuple filter list */
1263         TAILQ_INIT(&filter_info->fivetuple_list);
1264
1265         /* initialize flow director filter list & hash */
1266         ixgbe_fdir_filter_init(eth_dev);
1267
1268         /* initialize l2 tunnel filter list & hash */
1269         ixgbe_l2_tn_filter_init(eth_dev);
1270
1271         /* initialize flow filter lists */
1272         ixgbe_filterlist_init();
1273
1274         /* initialize bandwidth configuration info */
1275         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1276
1277         /* initialize Traffic Manager configuration */
1278         ixgbe_tm_conf_init(eth_dev);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1285 {
1286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1287         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288         struct ixgbe_hw *hw;
1289         int retries = 0;
1290         int ret;
1291
1292         PMD_INIT_FUNC_TRACE();
1293
1294         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1295                 return -EPERM;
1296
1297         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1298
1299         if (hw->adapter_stopped == 0)
1300                 ixgbe_dev_close(eth_dev);
1301
1302         eth_dev->dev_ops = NULL;
1303         eth_dev->rx_pkt_burst = NULL;
1304         eth_dev->tx_pkt_burst = NULL;
1305
1306         /* Unlock any pending hardware semaphore */
1307         ixgbe_swfw_lock_reset(hw);
1308
1309         /* disable uio intr before callback unregister */
1310         rte_intr_disable(intr_handle);
1311
1312         do {
1313                 ret = rte_intr_callback_unregister(intr_handle,
1314                                 ixgbe_dev_interrupt_handler, eth_dev);
1315                 if (ret >= 0) {
1316                         break;
1317                 } else if (ret != -EAGAIN) {
1318                         PMD_INIT_LOG(ERR,
1319                                 "intr callback unregister failed: %d",
1320                                 ret);
1321                         return ret;
1322                 }
1323                 rte_delay_ms(100);
1324         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1325
1326         /* uninitialize PF if max_vfs not zero */
1327         ixgbe_pf_host_uninit(eth_dev);
1328
1329         rte_free(eth_dev->data->mac_addrs);
1330         eth_dev->data->mac_addrs = NULL;
1331
1332         rte_free(eth_dev->data->hash_mac_addrs);
1333         eth_dev->data->hash_mac_addrs = NULL;
1334
1335         /* remove all the fdir filters & hash */
1336         ixgbe_fdir_filter_uninit(eth_dev);
1337
1338         /* remove all the L2 tunnel filters & hash */
1339         ixgbe_l2_tn_filter_uninit(eth_dev);
1340
1341         /* Remove all ntuple filters of the device */
1342         ixgbe_ntuple_filter_uninit(eth_dev);
1343
1344         /* clear all the filters list */
1345         ixgbe_filterlist_flush();
1346
1347         /* Remove all Traffic Manager configuration */
1348         ixgbe_tm_conf_uninit(eth_dev);
1349
1350 #ifdef RTE_LIBRTE_SECURITY
1351         rte_free(eth_dev->security_ctx);
1352 #endif
1353
1354         return 0;
1355 }
1356
1357 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct ixgbe_filter_info *filter_info =
1360                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1361         struct ixgbe_5tuple_filter *p_5tuple;
1362
1363         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1364                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1365                              p_5tuple,
1366                              entries);
1367                 rte_free(p_5tuple);
1368         }
1369         memset(filter_info->fivetuple_mask, 0,
1370                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1371
1372         return 0;
1373 }
1374
1375 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1376 {
1377         struct ixgbe_hw_fdir_info *fdir_info =
1378                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1379         struct ixgbe_fdir_filter *fdir_filter;
1380
1381                 if (fdir_info->hash_map)
1382                 rte_free(fdir_info->hash_map);
1383         if (fdir_info->hash_handle)
1384                 rte_hash_free(fdir_info->hash_handle);
1385
1386         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1387                 TAILQ_REMOVE(&fdir_info->fdir_list,
1388                              fdir_filter,
1389                              entries);
1390                 rte_free(fdir_filter);
1391         }
1392
1393         return 0;
1394 }
1395
1396 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1397 {
1398         struct ixgbe_l2_tn_info *l2_tn_info =
1399                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1400         struct ixgbe_l2_tn_filter *l2_tn_filter;
1401
1402         if (l2_tn_info->hash_map)
1403                 rte_free(l2_tn_info->hash_map);
1404         if (l2_tn_info->hash_handle)
1405                 rte_hash_free(l2_tn_info->hash_handle);
1406
1407         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1408                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1409                              l2_tn_filter,
1410                              entries);
1411                 rte_free(l2_tn_filter);
1412         }
1413
1414         return 0;
1415 }
1416
1417 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1418 {
1419         struct ixgbe_hw_fdir_info *fdir_info =
1420                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1421         char fdir_hash_name[RTE_HASH_NAMESIZE];
1422         struct rte_hash_parameters fdir_hash_params = {
1423                 .name = fdir_hash_name,
1424                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1425                 .key_len = sizeof(union ixgbe_atr_input),
1426                 .hash_func = rte_hash_crc,
1427                 .hash_func_init_val = 0,
1428                 .socket_id = rte_socket_id(),
1429         };
1430
1431         TAILQ_INIT(&fdir_info->fdir_list);
1432         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1433                  "fdir_%s", eth_dev->device->name);
1434         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1435         if (!fdir_info->hash_handle) {
1436                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1437                 return -EINVAL;
1438         }
1439         fdir_info->hash_map = rte_zmalloc("ixgbe",
1440                                           sizeof(struct ixgbe_fdir_filter *) *
1441                                           IXGBE_MAX_FDIR_FILTER_NUM,
1442                                           0);
1443         if (!fdir_info->hash_map) {
1444                 PMD_INIT_LOG(ERR,
1445                              "Failed to allocate memory for fdir hash map!");
1446                 return -ENOMEM;
1447         }
1448         fdir_info->mask_added = FALSE;
1449
1450         return 0;
1451 }
1452
1453 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1454 {
1455         struct ixgbe_l2_tn_info *l2_tn_info =
1456                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1457         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1458         struct rte_hash_parameters l2_tn_hash_params = {
1459                 .name = l2_tn_hash_name,
1460                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1461                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1462                 .hash_func = rte_hash_crc,
1463                 .hash_func_init_val = 0,
1464                 .socket_id = rte_socket_id(),
1465         };
1466
1467         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1468         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1469                  "l2_tn_%s", eth_dev->device->name);
1470         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1471         if (!l2_tn_info->hash_handle) {
1472                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1473                 return -EINVAL;
1474         }
1475         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1476                                    sizeof(struct ixgbe_l2_tn_filter *) *
1477                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1478                                    0);
1479         if (!l2_tn_info->hash_map) {
1480                 PMD_INIT_LOG(ERR,
1481                         "Failed to allocate memory for L2 TN hash map!");
1482                 return -ENOMEM;
1483         }
1484         l2_tn_info->e_tag_en = FALSE;
1485         l2_tn_info->e_tag_fwd_en = FALSE;
1486         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1487
1488         return 0;
1489 }
1490 /*
1491  * Negotiate mailbox API version with the PF.
1492  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1493  * Then we try to negotiate starting with the most recent one.
1494  * If all negotiation attempts fail, then we will proceed with
1495  * the default one (ixgbe_mbox_api_10).
1496  */
1497 static void
1498 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1499 {
1500         int32_t i;
1501
1502         /* start with highest supported, proceed down */
1503         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1504                 ixgbe_mbox_api_12,
1505                 ixgbe_mbox_api_11,
1506                 ixgbe_mbox_api_10,
1507         };
1508
1509         for (i = 0;
1510                         i != RTE_DIM(sup_ver) &&
1511                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1512                         i++)
1513                 ;
1514 }
1515
1516 static void
1517 generate_random_mac_addr(struct ether_addr *mac_addr)
1518 {
1519         uint64_t random;
1520
1521         /* Set Organizationally Unique Identifier (OUI) prefix. */
1522         mac_addr->addr_bytes[0] = 0x00;
1523         mac_addr->addr_bytes[1] = 0x09;
1524         mac_addr->addr_bytes[2] = 0xC0;
1525         /* Force indication of locally assigned MAC address. */
1526         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1527         /* Generate the last 3 bytes of the MAC address with a random number. */
1528         random = rte_rand();
1529         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1530 }
1531
1532 /*
1533  * Virtual Function device init
1534  */
1535 static int
1536 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1537 {
1538         int diag;
1539         uint32_t tc, tcs;
1540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542         struct ixgbe_hw *hw =
1543                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1544         struct ixgbe_vfta *shadow_vfta =
1545                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1546         struct ixgbe_hwstrip *hwstrip =
1547                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1548         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1549
1550         PMD_INIT_FUNC_TRACE();
1551
1552         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1553         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1554         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1555
1556         /* for secondary processes, we don't initialise any further as primary
1557          * has already done this work. Only check we don't need a different
1558          * RX function
1559          */
1560         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1561                 struct ixgbe_tx_queue *txq;
1562                 /* TX queue function in primary, set by last queue initialized
1563                  * Tx queue may not initialized by primary process
1564                  */
1565                 if (eth_dev->data->tx_queues) {
1566                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1567                         ixgbe_set_tx_function(eth_dev, txq);
1568                 } else {
1569                         /* Use default TX function if we get here */
1570                         PMD_INIT_LOG(NOTICE,
1571                                      "No TX queues configured yet. Using default TX function.");
1572                 }
1573
1574                 ixgbe_set_rx_function(eth_dev);
1575
1576                 return 0;
1577         }
1578
1579         rte_eth_copy_pci_info(eth_dev, pci_dev);
1580
1581         hw->device_id = pci_dev->id.device_id;
1582         hw->vendor_id = pci_dev->id.vendor_id;
1583         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1584
1585         /* initialize the vfta */
1586         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1587
1588         /* initialize the hw strip bitmap*/
1589         memset(hwstrip, 0, sizeof(*hwstrip));
1590
1591         /* Initialize the shared code (base driver) */
1592         diag = ixgbe_init_shared_code(hw);
1593         if (diag != IXGBE_SUCCESS) {
1594                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1595                 return -EIO;
1596         }
1597
1598         /* init_mailbox_params */
1599         hw->mbx.ops.init_params(hw);
1600
1601         /* Reset the hw statistics */
1602         ixgbevf_dev_stats_reset(eth_dev);
1603
1604         /* Disable the interrupts for VF */
1605         ixgbevf_intr_disable(hw);
1606
1607         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1608         diag = hw->mac.ops.reset_hw(hw);
1609
1610         /*
1611          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1612          * the underlying PF driver has not assigned a MAC address to the VF.
1613          * In this case, assign a random MAC address.
1614          */
1615         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1616                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1617                 return diag;
1618         }
1619
1620         /* negotiate mailbox API version to use with the PF. */
1621         ixgbevf_negotiate_api(hw);
1622
1623         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1624         ixgbevf_get_queues(hw, &tcs, &tc);
1625
1626         /* Allocate memory for storing MAC addresses */
1627         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1628                                                hw->mac.num_rar_entries, 0);
1629         if (eth_dev->data->mac_addrs == NULL) {
1630                 PMD_INIT_LOG(ERR,
1631                              "Failed to allocate %u bytes needed to store "
1632                              "MAC addresses",
1633                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1634                 return -ENOMEM;
1635         }
1636
1637         /* Generate a random MAC address, if none was assigned by PF. */
1638         if (is_zero_ether_addr(perm_addr)) {
1639                 generate_random_mac_addr(perm_addr);
1640                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1641                 if (diag) {
1642                         rte_free(eth_dev->data->mac_addrs);
1643                         eth_dev->data->mac_addrs = NULL;
1644                         return diag;
1645                 }
1646                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1647                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1648                              "%02x:%02x:%02x:%02x:%02x:%02x",
1649                              perm_addr->addr_bytes[0],
1650                              perm_addr->addr_bytes[1],
1651                              perm_addr->addr_bytes[2],
1652                              perm_addr->addr_bytes[3],
1653                              perm_addr->addr_bytes[4],
1654                              perm_addr->addr_bytes[5]);
1655         }
1656
1657         /* Copy the permanent MAC address */
1658         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1659
1660         /* reset the hardware with the new settings */
1661         diag = hw->mac.ops.start_hw(hw);
1662         switch (diag) {
1663         case  0:
1664                 break;
1665
1666         default:
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return -EIO;
1669         }
1670
1671         rte_intr_callback_register(intr_handle,
1672                                    ixgbevf_dev_interrupt_handler, eth_dev);
1673         rte_intr_enable(intr_handle);
1674         ixgbevf_intr_enable(hw);
1675
1676         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1677                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1678                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1679
1680         return 0;
1681 }
1682
1683 /* Virtual Function device uninit */
1684
1685 static int
1686 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1687 {
1688         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1689         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690         struct ixgbe_hw *hw;
1691
1692         PMD_INIT_FUNC_TRACE();
1693
1694         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1695                 return -EPERM;
1696
1697         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1698
1699         if (hw->adapter_stopped == 0)
1700                 ixgbevf_dev_close(eth_dev);
1701
1702         eth_dev->dev_ops = NULL;
1703         eth_dev->rx_pkt_burst = NULL;
1704         eth_dev->tx_pkt_burst = NULL;
1705
1706         /* Disable the interrupts for VF */
1707         ixgbevf_intr_disable(hw);
1708
1709         rte_free(eth_dev->data->mac_addrs);
1710         eth_dev->data->mac_addrs = NULL;
1711
1712         rte_intr_disable(intr_handle);
1713         rte_intr_callback_unregister(intr_handle,
1714                                      ixgbevf_dev_interrupt_handler, eth_dev);
1715
1716         return 0;
1717 }
1718
1719 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1720         struct rte_pci_device *pci_dev)
1721 {
1722         return rte_eth_dev_pci_generic_probe(pci_dev,
1723                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1724 }
1725
1726 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1727 {
1728         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1729 }
1730
1731 static struct rte_pci_driver rte_ixgbe_pmd = {
1732         .id_table = pci_id_ixgbe_map,
1733         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1734                      RTE_PCI_DRV_IOVA_AS_VA,
1735         .probe = eth_ixgbe_pci_probe,
1736         .remove = eth_ixgbe_pci_remove,
1737 };
1738
1739 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1740         struct rte_pci_device *pci_dev)
1741 {
1742         return rte_eth_dev_pci_generic_probe(pci_dev,
1743                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1744 }
1745
1746 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1747 {
1748         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1749 }
1750
1751 /*
1752  * virtual function driver struct
1753  */
1754 static struct rte_pci_driver rte_ixgbevf_pmd = {
1755         .id_table = pci_id_ixgbevf_map,
1756         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1757         .probe = eth_ixgbevf_pci_probe,
1758         .remove = eth_ixgbevf_pci_remove,
1759 };
1760
1761 static int
1762 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1763 {
1764         struct ixgbe_hw *hw =
1765                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1766         struct ixgbe_vfta *shadow_vfta =
1767                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1768         uint32_t vfta;
1769         uint32_t vid_idx;
1770         uint32_t vid_bit;
1771
1772         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1773         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1774         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1775         if (on)
1776                 vfta |= vid_bit;
1777         else
1778                 vfta &= ~vid_bit;
1779         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1780
1781         /* update local VFTA copy */
1782         shadow_vfta->vfta[vid_idx] = vfta;
1783
1784         return 0;
1785 }
1786
1787 static void
1788 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1789 {
1790         if (on)
1791                 ixgbe_vlan_hw_strip_enable(dev, queue);
1792         else
1793                 ixgbe_vlan_hw_strip_disable(dev, queue);
1794 }
1795
1796 static int
1797 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1798                     enum rte_vlan_type vlan_type,
1799                     uint16_t tpid)
1800 {
1801         struct ixgbe_hw *hw =
1802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803         int ret = 0;
1804         uint32_t reg;
1805         uint32_t qinq;
1806
1807         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1808         qinq &= IXGBE_DMATXCTL_GDV;
1809
1810         switch (vlan_type) {
1811         case ETH_VLAN_TYPE_INNER:
1812                 if (qinq) {
1813                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1814                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1815                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1816                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1817                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1818                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1819                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1820                 } else {
1821                         ret = -ENOTSUP;
1822                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1823                                     " by single VLAN");
1824                 }
1825                 break;
1826         case ETH_VLAN_TYPE_OUTER:
1827                 if (qinq) {
1828                         /* Only the high 16-bits is valid */
1829                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1830                                         IXGBE_EXVET_VET_EXT_SHIFT);
1831                 } else {
1832                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1833                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1834                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1835                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1836                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1837                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1838                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1839                 }
1840
1841                 break;
1842         default:
1843                 ret = -EINVAL;
1844                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1845                 break;
1846         }
1847
1848         return ret;
1849 }
1850
1851 void
1852 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1853 {
1854         struct ixgbe_hw *hw =
1855                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856         uint32_t vlnctrl;
1857
1858         PMD_INIT_FUNC_TRACE();
1859
1860         /* Filter Table Disable */
1861         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1862         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1863
1864         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1865 }
1866
1867 void
1868 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         struct ixgbe_vfta *shadow_vfta =
1873                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1874         uint32_t vlnctrl;
1875         uint16_t i;
1876
1877         PMD_INIT_FUNC_TRACE();
1878
1879         /* Filter Table Enable */
1880         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1881         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1882         vlnctrl |= IXGBE_VLNCTRL_VFE;
1883
1884         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1885
1886         /* write whatever is in local vfta copy */
1887         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1888                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1889 }
1890
1891 static void
1892 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1893 {
1894         struct ixgbe_hwstrip *hwstrip =
1895                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1896         struct ixgbe_rx_queue *rxq;
1897
1898         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1899                 return;
1900
1901         if (on)
1902                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1903         else
1904                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1905
1906         if (queue >= dev->data->nb_rx_queues)
1907                 return;
1908
1909         rxq = dev->data->rx_queues[queue];
1910
1911         if (on)
1912                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1913         else
1914                 rxq->vlan_flags = PKT_RX_VLAN;
1915 }
1916
1917 static void
1918 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint32_t ctrl;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         if (hw->mac.type == ixgbe_mac_82598EB) {
1927                 /* No queue level support */
1928                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1929                 return;
1930         }
1931
1932         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1933         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1934         ctrl &= ~IXGBE_RXDCTL_VME;
1935         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1936
1937         /* record those setting for HW strip per queue */
1938         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1939 }
1940
1941 static void
1942 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1943 {
1944         struct ixgbe_hw *hw =
1945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946         uint32_t ctrl;
1947
1948         PMD_INIT_FUNC_TRACE();
1949
1950         if (hw->mac.type == ixgbe_mac_82598EB) {
1951                 /* No queue level supported */
1952                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1953                 return;
1954         }
1955
1956         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1957         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1958         ctrl |= IXGBE_RXDCTL_VME;
1959         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1960
1961         /* record those setting for HW strip per queue */
1962         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1963 }
1964
1965 static void
1966 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1967 {
1968         struct ixgbe_hw *hw =
1969                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970         uint32_t ctrl;
1971
1972         PMD_INIT_FUNC_TRACE();
1973
1974         /* DMATXCTRL: Geric Double VLAN Disable */
1975         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1976         ctrl &= ~IXGBE_DMATXCTL_GDV;
1977         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1978
1979         /* CTRL_EXT: Global Double VLAN Disable */
1980         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1981         ctrl &= ~IXGBE_EXTENDED_VLAN;
1982         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1983
1984 }
1985
1986 static void
1987 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1988 {
1989         struct ixgbe_hw *hw =
1990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         uint32_t ctrl;
1992
1993         PMD_INIT_FUNC_TRACE();
1994
1995         /* DMATXCTRL: Geric Double VLAN Enable */
1996         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1997         ctrl |= IXGBE_DMATXCTL_GDV;
1998         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1999
2000         /* CTRL_EXT: Global Double VLAN Enable */
2001         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2002         ctrl |= IXGBE_EXTENDED_VLAN;
2003         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2004
2005         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2006         if (hw->mac.type == ixgbe_mac_X550 ||
2007             hw->mac.type == ixgbe_mac_X550EM_x ||
2008             hw->mac.type == ixgbe_mac_X550EM_a) {
2009                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2010                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2011                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2012         }
2013
2014         /*
2015          * VET EXT field in the EXVET register = 0x8100 by default
2016          * So no need to change. Same to VT field of DMATXCTL register
2017          */
2018 }
2019
2020 void
2021 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2022 {
2023         struct ixgbe_hw *hw =
2024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2026         uint32_t ctrl;
2027         uint16_t i;
2028         struct ixgbe_rx_queue *rxq;
2029         bool on;
2030
2031         PMD_INIT_FUNC_TRACE();
2032
2033         if (hw->mac.type == ixgbe_mac_82598EB) {
2034                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2035                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2036                         ctrl |= IXGBE_VLNCTRL_VME;
2037                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2038                 } else {
2039                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2040                         ctrl &= ~IXGBE_VLNCTRL_VME;
2041                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2042                 }
2043         } else {
2044                 /*
2045                  * Other 10G NIC, the VLAN strip can be setup
2046                  * per queue in RXDCTL
2047                  */
2048                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2049                         rxq = dev->data->rx_queues[i];
2050                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2051                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2052                                 ctrl |= IXGBE_RXDCTL_VME;
2053                                 on = TRUE;
2054                         } else {
2055                                 ctrl &= ~IXGBE_RXDCTL_VME;
2056                                 on = FALSE;
2057                         }
2058                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2059
2060                         /* record those setting for HW strip per queue */
2061                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2062                 }
2063         }
2064 }
2065
2066 static int
2067 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2068 {
2069         struct rte_eth_rxmode *rxmode;
2070         rxmode = &dev->data->dev_conf.rxmode;
2071
2072         if (mask & ETH_VLAN_STRIP_MASK) {
2073                 ixgbe_vlan_hw_strip_config(dev);
2074         }
2075
2076         if (mask & ETH_VLAN_FILTER_MASK) {
2077                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2078                         ixgbe_vlan_hw_filter_enable(dev);
2079                 else
2080                         ixgbe_vlan_hw_filter_disable(dev);
2081         }
2082
2083         if (mask & ETH_VLAN_EXTEND_MASK) {
2084                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2085                         ixgbe_vlan_hw_extend_enable(dev);
2086                 else
2087                         ixgbe_vlan_hw_extend_disable(dev);
2088         }
2089
2090         return 0;
2091 }
2092
2093 static void
2094 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2095 {
2096         struct ixgbe_hw *hw =
2097                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2099         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2100
2101         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2102         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2103 }
2104
2105 static int
2106 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2107 {
2108         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2109
2110         switch (nb_rx_q) {
2111         case 1:
2112         case 2:
2113                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2114                 break;
2115         case 4:
2116                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2117                 break;
2118         default:
2119                 return -EINVAL;
2120         }
2121
2122         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2123                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2124         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2125                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2126         return 0;
2127 }
2128
2129 static int
2130 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2131 {
2132         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2135         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2136
2137         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2138                 /* check multi-queue mode */
2139                 switch (dev_conf->rxmode.mq_mode) {
2140                 case ETH_MQ_RX_VMDQ_DCB:
2141                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2142                         break;
2143                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2144                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2145                         PMD_INIT_LOG(ERR, "SRIOV active,"
2146                                         " unsupported mq_mode rx %d.",
2147                                         dev_conf->rxmode.mq_mode);
2148                         return -EINVAL;
2149                 case ETH_MQ_RX_RSS:
2150                 case ETH_MQ_RX_VMDQ_RSS:
2151                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2152                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2153                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2154                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2155                                                 " invalid queue number"
2156                                                 " for VMDQ RSS, allowed"
2157                                                 " value are 1, 2 or 4.");
2158                                         return -EINVAL;
2159                                 }
2160                         break;
2161                 case ETH_MQ_RX_VMDQ_ONLY:
2162                 case ETH_MQ_RX_NONE:
2163                         /* if nothing mq mode configure, use default scheme */
2164                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2165                         break;
2166                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2167                         /* SRIOV only works in VMDq enable mode */
2168                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2169                                         " wrong mq_mode rx %d.",
2170                                         dev_conf->rxmode.mq_mode);
2171                         return -EINVAL;
2172                 }
2173
2174                 switch (dev_conf->txmode.mq_mode) {
2175                 case ETH_MQ_TX_VMDQ_DCB:
2176                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2177                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2178                         break;
2179                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2180                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2181                         break;
2182                 }
2183
2184                 /* check valid queue number */
2185                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2186                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2187                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2188                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2189                                         " must be less than or equal to %d.",
2190                                         nb_rx_q, nb_tx_q,
2191                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2192                         return -EINVAL;
2193                 }
2194         } else {
2195                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2196                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2197                                           " not supported.");
2198                         return -EINVAL;
2199                 }
2200                 /* check configuration for vmdb+dcb mode */
2201                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2202                         const struct rte_eth_vmdq_dcb_conf *conf;
2203
2204                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2205                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2206                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2207                                 return -EINVAL;
2208                         }
2209                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2210                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2211                                conf->nb_queue_pools == ETH_32_POOLS)) {
2212                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2213                                                 " nb_queue_pools must be %d or %d.",
2214                                                 ETH_16_POOLS, ETH_32_POOLS);
2215                                 return -EINVAL;
2216                         }
2217                 }
2218                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2219                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2220
2221                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2222                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2223                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2224                                 return -EINVAL;
2225                         }
2226                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2227                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2228                                conf->nb_queue_pools == ETH_32_POOLS)) {
2229                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2230                                                 " nb_queue_pools != %d and"
2231                                                 " nb_queue_pools != %d.",
2232                                                 ETH_16_POOLS, ETH_32_POOLS);
2233                                 return -EINVAL;
2234                         }
2235                 }
2236
2237                 /* For DCB mode check our configuration before we go further */
2238                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2239                         const struct rte_eth_dcb_rx_conf *conf;
2240
2241                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2242                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2243                                                  IXGBE_DCB_NB_QUEUES);
2244                                 return -EINVAL;
2245                         }
2246                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2247                         if (!(conf->nb_tcs == ETH_4_TCS ||
2248                                conf->nb_tcs == ETH_8_TCS)) {
2249                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2250                                                 " and nb_tcs != %d.",
2251                                                 ETH_4_TCS, ETH_8_TCS);
2252                                 return -EINVAL;
2253                         }
2254                 }
2255
2256                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2257                         const struct rte_eth_dcb_tx_conf *conf;
2258
2259                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2260                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2261                                                  IXGBE_DCB_NB_QUEUES);
2262                                 return -EINVAL;
2263                         }
2264                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2265                         if (!(conf->nb_tcs == ETH_4_TCS ||
2266                                conf->nb_tcs == ETH_8_TCS)) {
2267                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2268                                                 " and nb_tcs != %d.",
2269                                                 ETH_4_TCS, ETH_8_TCS);
2270                                 return -EINVAL;
2271                         }
2272                 }
2273
2274                 /*
2275                  * When DCB/VT is off, maximum number of queues changes,
2276                  * except for 82598EB, which remains constant.
2277                  */
2278                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2279                                 hw->mac.type != ixgbe_mac_82598EB) {
2280                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2281                                 PMD_INIT_LOG(ERR,
2282                                              "Neither VT nor DCB are enabled, "
2283                                              "nb_tx_q > %d.",
2284                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2285                                 return -EINVAL;
2286                         }
2287                 }
2288         }
2289         return 0;
2290 }
2291
2292 static int
2293 ixgbe_dev_configure(struct rte_eth_dev *dev)
2294 {
2295         struct ixgbe_interrupt *intr =
2296                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2297         struct ixgbe_adapter *adapter =
2298                 (struct ixgbe_adapter *)dev->data->dev_private;
2299         struct rte_eth_dev_info dev_info;
2300         uint64_t rx_offloads;
2301         uint64_t tx_offloads;
2302         int ret;
2303
2304         PMD_INIT_FUNC_TRACE();
2305         /* multipe queue mode checking */
2306         ret  = ixgbe_check_mq_mode(dev);
2307         if (ret != 0) {
2308                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2309                             ret);
2310                 return ret;
2311         }
2312
2313         ixgbe_dev_info_get(dev, &dev_info);
2314         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2315         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2316                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2317                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2318                             rx_offloads, dev_info.rx_offload_capa);
2319                 return -ENOTSUP;
2320         }
2321         tx_offloads = dev->data->dev_conf.txmode.offloads;
2322         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2323                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2324                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2325                             tx_offloads, dev_info.tx_offload_capa);
2326                 return -ENOTSUP;
2327         }
2328
2329         /* set flag to update link status after init */
2330         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2331
2332         /*
2333          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2334          * allocation or vector Rx preconditions we will reset it.
2335          */
2336         adapter->rx_bulk_alloc_allowed = true;
2337         adapter->rx_vec_allowed = true;
2338
2339         return 0;
2340 }
2341
2342 static void
2343 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2344 {
2345         struct ixgbe_hw *hw =
2346                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         struct ixgbe_interrupt *intr =
2348                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2349         uint32_t gpie;
2350
2351         /* only set up it on X550EM_X */
2352         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2353                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2354                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2355                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2356                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2357                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2358         }
2359 }
2360
2361 int
2362 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2363                         uint16_t tx_rate, uint64_t q_msk)
2364 {
2365         struct ixgbe_hw *hw;
2366         struct ixgbe_vf_info *vfinfo;
2367         struct rte_eth_link link;
2368         uint8_t  nb_q_per_pool;
2369         uint32_t queue_stride;
2370         uint32_t queue_idx, idx = 0, vf_idx;
2371         uint32_t queue_end;
2372         uint16_t total_rate = 0;
2373         struct rte_pci_device *pci_dev;
2374
2375         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2376         rte_eth_link_get_nowait(dev->data->port_id, &link);
2377
2378         if (vf >= pci_dev->max_vfs)
2379                 return -EINVAL;
2380
2381         if (tx_rate > link.link_speed)
2382                 return -EINVAL;
2383
2384         if (q_msk == 0)
2385                 return 0;
2386
2387         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2389         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2390         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2391         queue_idx = vf * queue_stride;
2392         queue_end = queue_idx + nb_q_per_pool - 1;
2393         if (queue_end >= hw->mac.max_tx_queues)
2394                 return -EINVAL;
2395
2396         if (vfinfo) {
2397                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2398                         if (vf_idx == vf)
2399                                 continue;
2400                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2401                                 idx++)
2402                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2403                 }
2404         } else {
2405                 return -EINVAL;
2406         }
2407
2408         /* Store tx_rate for this vf. */
2409         for (idx = 0; idx < nb_q_per_pool; idx++) {
2410                 if (((uint64_t)0x1 << idx) & q_msk) {
2411                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2412                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2413                         total_rate += tx_rate;
2414                 }
2415         }
2416
2417         if (total_rate > dev->data->dev_link.link_speed) {
2418                 /* Reset stored TX rate of the VF if it causes exceed
2419                  * link speed.
2420                  */
2421                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2422                 return -EINVAL;
2423         }
2424
2425         /* Set RTTBCNRC of each queue/pool for vf X  */
2426         for (; queue_idx <= queue_end; queue_idx++) {
2427                 if (0x1 & q_msk)
2428                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2429                 q_msk = q_msk >> 1;
2430         }
2431
2432         return 0;
2433 }
2434
2435 /*
2436  * Configure device link speed and setup link.
2437  * It returns 0 on success.
2438  */
2439 static int
2440 ixgbe_dev_start(struct rte_eth_dev *dev)
2441 {
2442         struct ixgbe_hw *hw =
2443                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444         struct ixgbe_vf_info *vfinfo =
2445                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2446         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2447         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2448         uint32_t intr_vector = 0;
2449         int err, link_up = 0, negotiate = 0;
2450         uint32_t speed = 0;
2451         uint32_t allowed_speeds = 0;
2452         int mask = 0;
2453         int status;
2454         uint16_t vf, idx;
2455         uint32_t *link_speeds;
2456         struct ixgbe_tm_conf *tm_conf =
2457                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2458
2459         PMD_INIT_FUNC_TRACE();
2460
2461         /* IXGBE devices don't support:
2462         *    - half duplex (checked afterwards for valid speeds)
2463         *    - fixed speed: TODO implement
2464         */
2465         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2466                 PMD_INIT_LOG(ERR,
2467                 "Invalid link_speeds for port %u, fix speed not supported",
2468                                 dev->data->port_id);
2469                 return -EINVAL;
2470         }
2471
2472         /* disable uio/vfio intr/eventfd mapping */
2473         rte_intr_disable(intr_handle);
2474
2475         /* stop adapter */
2476         hw->adapter_stopped = 0;
2477         ixgbe_stop_adapter(hw);
2478
2479         /* reinitialize adapter
2480          * this calls reset and start
2481          */
2482         status = ixgbe_pf_reset_hw(hw);
2483         if (status != 0)
2484                 return -1;
2485         hw->mac.ops.start_hw(hw);
2486         hw->mac.get_link_status = true;
2487
2488         /* configure PF module if SRIOV enabled */
2489         ixgbe_pf_host_configure(dev);
2490
2491         ixgbe_dev_phy_intr_setup(dev);
2492
2493         /* check and configure queue intr-vector mapping */
2494         if ((rte_intr_cap_multiple(intr_handle) ||
2495              !RTE_ETH_DEV_SRIOV(dev).active) &&
2496             dev->data->dev_conf.intr_conf.rxq != 0) {
2497                 intr_vector = dev->data->nb_rx_queues;
2498                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2499                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2500                                         IXGBE_MAX_INTR_QUEUE_NUM);
2501                         return -ENOTSUP;
2502                 }
2503                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2504                         return -1;
2505         }
2506
2507         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2508                 intr_handle->intr_vec =
2509                         rte_zmalloc("intr_vec",
2510                                     dev->data->nb_rx_queues * sizeof(int), 0);
2511                 if (intr_handle->intr_vec == NULL) {
2512                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2513                                      " intr_vec", dev->data->nb_rx_queues);
2514                         return -ENOMEM;
2515                 }
2516         }
2517
2518         /* confiugre msix for sleep until rx interrupt */
2519         ixgbe_configure_msix(dev);
2520
2521         /* initialize transmission unit */
2522         ixgbe_dev_tx_init(dev);
2523
2524         /* This can fail when allocating mbufs for descriptor rings */
2525         err = ixgbe_dev_rx_init(dev);
2526         if (err) {
2527                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2528                 goto error;
2529         }
2530
2531         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2532                 ETH_VLAN_EXTEND_MASK;
2533         err = ixgbe_vlan_offload_set(dev, mask);
2534         if (err) {
2535                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2536                 goto error;
2537         }
2538
2539         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2540                 /* Enable vlan filtering for VMDq */
2541                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2542         }
2543
2544         /* Configure DCB hw */
2545         ixgbe_configure_dcb(dev);
2546
2547         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2548                 err = ixgbe_fdir_configure(dev);
2549                 if (err)
2550                         goto error;
2551         }
2552
2553         /* Restore vf rate limit */
2554         if (vfinfo != NULL) {
2555                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2556                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2557                                 if (vfinfo[vf].tx_rate[idx] != 0)
2558                                         ixgbe_set_vf_rate_limit(
2559                                                 dev, vf,
2560                                                 vfinfo[vf].tx_rate[idx],
2561                                                 1 << idx);
2562         }
2563
2564         ixgbe_restore_statistics_mapping(dev);
2565
2566         err = ixgbe_dev_rxtx_start(dev);
2567         if (err < 0) {
2568                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2569                 goto error;
2570         }
2571
2572         /* Skip link setup if loopback mode is enabled for 82599. */
2573         if (hw->mac.type == ixgbe_mac_82599EB &&
2574                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2575                 goto skip_link_setup;
2576
2577         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2578                 err = hw->mac.ops.setup_sfp(hw);
2579                 if (err)
2580                         goto error;
2581         }
2582
2583         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2584                 /* Turn on the copper */
2585                 ixgbe_set_phy_power(hw, true);
2586         } else {
2587                 /* Turn on the laser */
2588                 ixgbe_enable_tx_laser(hw);
2589         }
2590
2591         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2592         if (err)
2593                 goto error;
2594         dev->data->dev_link.link_status = link_up;
2595
2596         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2597         if (err)
2598                 goto error;
2599
2600         switch (hw->mac.type) {
2601         case ixgbe_mac_X550:
2602         case ixgbe_mac_X550EM_x:
2603         case ixgbe_mac_X550EM_a:
2604                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2605                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2606                         ETH_LINK_SPEED_10G;
2607                 break;
2608         default:
2609                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2610                         ETH_LINK_SPEED_10G;
2611         }
2612
2613         link_speeds = &dev->data->dev_conf.link_speeds;
2614         if (*link_speeds & ~allowed_speeds) {
2615                 PMD_INIT_LOG(ERR, "Invalid link setting");
2616                 goto error;
2617         }
2618
2619         speed = 0x0;
2620         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2621                 switch (hw->mac.type) {
2622                 case ixgbe_mac_82598EB:
2623                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2624                         break;
2625                 case ixgbe_mac_82599EB:
2626                 case ixgbe_mac_X540:
2627                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2628                         break;
2629                 case ixgbe_mac_X550:
2630                 case ixgbe_mac_X550EM_x:
2631                 case ixgbe_mac_X550EM_a:
2632                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2633                         break;
2634                 default:
2635                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2636                 }
2637         } else {
2638                 if (*link_speeds & ETH_LINK_SPEED_10G)
2639                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2640                 if (*link_speeds & ETH_LINK_SPEED_5G)
2641                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2642                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2643                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2644                 if (*link_speeds & ETH_LINK_SPEED_1G)
2645                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2646                 if (*link_speeds & ETH_LINK_SPEED_100M)
2647                         speed |= IXGBE_LINK_SPEED_100_FULL;
2648         }
2649
2650         err = ixgbe_setup_link(hw, speed, link_up);
2651         if (err)
2652                 goto error;
2653
2654         ixgbe_dev_link_update(dev, 0);
2655
2656 skip_link_setup:
2657
2658         if (rte_intr_allow_others(intr_handle)) {
2659                 /* check if lsc interrupt is enabled */
2660                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2661                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2662                 else
2663                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2664                 ixgbe_dev_macsec_interrupt_setup(dev);
2665         } else {
2666                 rte_intr_callback_unregister(intr_handle,
2667                                              ixgbe_dev_interrupt_handler, dev);
2668                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2669                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2670                                      " no intr multiplex");
2671         }
2672
2673         /* check if rxq interrupt is enabled */
2674         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2675             rte_intr_dp_is_en(intr_handle))
2676                 ixgbe_dev_rxq_interrupt_setup(dev);
2677
2678         /* enable uio/vfio intr/eventfd mapping */
2679         rte_intr_enable(intr_handle);
2680
2681         /* resume enabled intr since hw reset */
2682         ixgbe_enable_intr(dev);
2683         ixgbe_l2_tunnel_conf(dev);
2684         ixgbe_filter_restore(dev);
2685
2686         if (tm_conf->root && !tm_conf->committed)
2687                 PMD_DRV_LOG(WARNING,
2688                             "please call hierarchy_commit() "
2689                             "before starting the port");
2690
2691         return 0;
2692
2693 error:
2694         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2695         ixgbe_dev_clear_queues(dev);
2696         return -EIO;
2697 }
2698
2699 /*
2700  * Stop device: disable rx and tx functions to allow for reconfiguring.
2701  */
2702 static void
2703 ixgbe_dev_stop(struct rte_eth_dev *dev)
2704 {
2705         struct rte_eth_link link;
2706         struct ixgbe_hw *hw =
2707                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2708         struct ixgbe_vf_info *vfinfo =
2709                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2710         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2711         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2712         int vf;
2713         struct ixgbe_tm_conf *tm_conf =
2714                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2715
2716         PMD_INIT_FUNC_TRACE();
2717
2718         /* disable interrupts */
2719         ixgbe_disable_intr(hw);
2720
2721         /* reset the NIC */
2722         ixgbe_pf_reset_hw(hw);
2723         hw->adapter_stopped = 0;
2724
2725         /* stop adapter */
2726         ixgbe_stop_adapter(hw);
2727
2728         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2729                 vfinfo[vf].clear_to_send = false;
2730
2731         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2732                 /* Turn off the copper */
2733                 ixgbe_set_phy_power(hw, false);
2734         } else {
2735                 /* Turn off the laser */
2736                 ixgbe_disable_tx_laser(hw);
2737         }
2738
2739         ixgbe_dev_clear_queues(dev);
2740
2741         /* Clear stored conf */
2742         dev->data->scattered_rx = 0;
2743         dev->data->lro = 0;
2744
2745         /* Clear recorded link status */
2746         memset(&link, 0, sizeof(link));
2747         rte_eth_linkstatus_set(dev, &link);
2748
2749         if (!rte_intr_allow_others(intr_handle))
2750                 /* resume to the default handler */
2751                 rte_intr_callback_register(intr_handle,
2752                                            ixgbe_dev_interrupt_handler,
2753                                            (void *)dev);
2754
2755         /* Clean datapath event and queue/vec mapping */
2756         rte_intr_efd_disable(intr_handle);
2757         if (intr_handle->intr_vec != NULL) {
2758                 rte_free(intr_handle->intr_vec);
2759                 intr_handle->intr_vec = NULL;
2760         }
2761
2762         /* reset hierarchy commit */
2763         tm_conf->committed = false;
2764 }
2765
2766 /*
2767  * Set device link up: enable tx.
2768  */
2769 static int
2770 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2771 {
2772         struct ixgbe_hw *hw =
2773                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774         if (hw->mac.type == ixgbe_mac_82599EB) {
2775 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2776                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2777                         /* Not suported in bypass mode */
2778                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2779                                      "by device id 0x%x", hw->device_id);
2780                         return -ENOTSUP;
2781                 }
2782 #endif
2783         }
2784
2785         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2786                 /* Turn on the copper */
2787                 ixgbe_set_phy_power(hw, true);
2788         } else {
2789                 /* Turn on the laser */
2790                 ixgbe_enable_tx_laser(hw);
2791         }
2792
2793         return 0;
2794 }
2795
2796 /*
2797  * Set device link down: disable tx.
2798  */
2799 static int
2800 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2801 {
2802         struct ixgbe_hw *hw =
2803                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2804         if (hw->mac.type == ixgbe_mac_82599EB) {
2805 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2806                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2807                         /* Not suported in bypass mode */
2808                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2809                                      "by device id 0x%x", hw->device_id);
2810                         return -ENOTSUP;
2811                 }
2812 #endif
2813         }
2814
2815         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2816                 /* Turn off the copper */
2817                 ixgbe_set_phy_power(hw, false);
2818         } else {
2819                 /* Turn off the laser */
2820                 ixgbe_disable_tx_laser(hw);
2821         }
2822
2823         return 0;
2824 }
2825
2826 /*
2827  * Reset and stop device.
2828  */
2829 static void
2830 ixgbe_dev_close(struct rte_eth_dev *dev)
2831 {
2832         struct ixgbe_hw *hw =
2833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2834
2835         PMD_INIT_FUNC_TRACE();
2836
2837         ixgbe_pf_reset_hw(hw);
2838
2839         ixgbe_dev_stop(dev);
2840         hw->adapter_stopped = 1;
2841
2842         ixgbe_dev_free_queues(dev);
2843
2844         ixgbe_disable_pcie_master(hw);
2845
2846         /* reprogram the RAR[0] in case user changed it. */
2847         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2848 }
2849
2850 /*
2851  * Reset PF device.
2852  */
2853 static int
2854 ixgbe_dev_reset(struct rte_eth_dev *dev)
2855 {
2856         int ret;
2857
2858         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2859          * its VF to make them align with it. The detailed notification
2860          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2861          * To avoid unexpected behavior in VF, currently reset of PF with
2862          * SR-IOV activation is not supported. It might be supported later.
2863          */
2864         if (dev->data->sriov.active)
2865                 return -ENOTSUP;
2866
2867         ret = eth_ixgbe_dev_uninit(dev);
2868         if (ret)
2869                 return ret;
2870
2871         ret = eth_ixgbe_dev_init(dev);
2872
2873         return ret;
2874 }
2875
2876 static void
2877 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2878                            struct ixgbe_hw_stats *hw_stats,
2879                            struct ixgbe_macsec_stats *macsec_stats,
2880                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2881                            uint64_t *total_qprc, uint64_t *total_qprdc)
2882 {
2883         uint32_t bprc, lxon, lxoff, total;
2884         uint32_t delta_gprc = 0;
2885         unsigned i;
2886         /* Workaround for RX byte count not including CRC bytes when CRC
2887          * strip is enabled. CRC bytes are removed from counters when crc_strip
2888          * is disabled.
2889          */
2890         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2891                         IXGBE_HLREG0_RXCRCSTRP);
2892
2893         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2894         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2895         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2896         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2897
2898         for (i = 0; i < 8; i++) {
2899                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2900
2901                 /* global total per queue */
2902                 hw_stats->mpc[i] += mp;
2903                 /* Running comprehensive total for stats display */
2904                 *total_missed_rx += hw_stats->mpc[i];
2905                 if (hw->mac.type == ixgbe_mac_82598EB) {
2906                         hw_stats->rnbc[i] +=
2907                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2908                         hw_stats->pxonrxc[i] +=
2909                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2910                         hw_stats->pxoffrxc[i] +=
2911                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2912                 } else {
2913                         hw_stats->pxonrxc[i] +=
2914                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2915                         hw_stats->pxoffrxc[i] +=
2916                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2917                         hw_stats->pxon2offc[i] +=
2918                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2919                 }
2920                 hw_stats->pxontxc[i] +=
2921                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2922                 hw_stats->pxofftxc[i] +=
2923                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2924         }
2925         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2926                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2927                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2928                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2929
2930                 delta_gprc += delta_qprc;
2931
2932                 hw_stats->qprc[i] += delta_qprc;
2933                 hw_stats->qptc[i] += delta_qptc;
2934
2935                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2936                 hw_stats->qbrc[i] +=
2937                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2938                 if (crc_strip == 0)
2939                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2940
2941                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2942                 hw_stats->qbtc[i] +=
2943                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2944
2945                 hw_stats->qprdc[i] += delta_qprdc;
2946                 *total_qprdc += hw_stats->qprdc[i];
2947
2948                 *total_qprc += hw_stats->qprc[i];
2949                 *total_qbrc += hw_stats->qbrc[i];
2950         }
2951         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2952         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2953         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2954
2955         /*
2956          * An errata states that gprc actually counts good + missed packets:
2957          * Workaround to set gprc to summated queue packet receives
2958          */
2959         hw_stats->gprc = *total_qprc;
2960
2961         if (hw->mac.type != ixgbe_mac_82598EB) {
2962                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2963                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2964                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2965                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2966                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2967                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2968                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2969                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2970         } else {
2971                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2972                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2973                 /* 82598 only has a counter in the high register */
2974                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2975                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2976                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2977         }
2978         uint64_t old_tpr = hw_stats->tpr;
2979
2980         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2981         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2982
2983         if (crc_strip == 0)
2984                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2985
2986         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2987         hw_stats->gptc += delta_gptc;
2988         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2989         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2990
2991         /*
2992          * Workaround: mprc hardware is incorrectly counting
2993          * broadcasts, so for now we subtract those.
2994          */
2995         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2996         hw_stats->bprc += bprc;
2997         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2998         if (hw->mac.type == ixgbe_mac_82598EB)
2999                 hw_stats->mprc -= bprc;
3000
3001         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3002         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3003         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3004         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3005         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3006         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3007
3008         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3009         hw_stats->lxontxc += lxon;
3010         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3011         hw_stats->lxofftxc += lxoff;
3012         total = lxon + lxoff;
3013
3014         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3015         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3016         hw_stats->gptc -= total;
3017         hw_stats->mptc -= total;
3018         hw_stats->ptc64 -= total;
3019         hw_stats->gotc -= total * ETHER_MIN_LEN;
3020
3021         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3022         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3023         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3024         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3025         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3026         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3027         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3028         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3029         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3030         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3031         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3032         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3033         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3034         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3035         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3036         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3037         /* Only read FCOE on 82599 */
3038         if (hw->mac.type != ixgbe_mac_82598EB) {
3039                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3040                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3041                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3042                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3043                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3044         }
3045
3046         /* Flow Director Stats registers */
3047         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3048         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3049
3050         /* MACsec Stats registers */
3051         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3052         macsec_stats->out_pkts_encrypted +=
3053                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3054         macsec_stats->out_pkts_protected +=
3055                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3056         macsec_stats->out_octets_encrypted +=
3057                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3058         macsec_stats->out_octets_protected +=
3059                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3060         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3061         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3062         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3063         macsec_stats->in_pkts_unknownsci +=
3064                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3065         macsec_stats->in_octets_decrypted +=
3066                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3067         macsec_stats->in_octets_validated +=
3068                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3069         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3070         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3071         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3072         for (i = 0; i < 2; i++) {
3073                 macsec_stats->in_pkts_ok +=
3074                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3075                 macsec_stats->in_pkts_invalid +=
3076                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3077                 macsec_stats->in_pkts_notvalid +=
3078                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3079         }
3080         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3081         macsec_stats->in_pkts_notusingsa +=
3082                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3083 }
3084
3085 /*
3086  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3087  */
3088 static int
3089 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3090 {
3091         struct ixgbe_hw *hw =
3092                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3093         struct ixgbe_hw_stats *hw_stats =
3094                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3095         struct ixgbe_macsec_stats *macsec_stats =
3096                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3097                                 dev->data->dev_private);
3098         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3099         unsigned i;
3100
3101         total_missed_rx = 0;
3102         total_qbrc = 0;
3103         total_qprc = 0;
3104         total_qprdc = 0;
3105
3106         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3107                         &total_qbrc, &total_qprc, &total_qprdc);
3108
3109         if (stats == NULL)
3110                 return -EINVAL;
3111
3112         /* Fill out the rte_eth_stats statistics structure */
3113         stats->ipackets = total_qprc;
3114         stats->ibytes = total_qbrc;
3115         stats->opackets = hw_stats->gptc;
3116         stats->obytes = hw_stats->gotc;
3117
3118         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3119                 stats->q_ipackets[i] = hw_stats->qprc[i];
3120                 stats->q_opackets[i] = hw_stats->qptc[i];
3121                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3122                 stats->q_obytes[i] = hw_stats->qbtc[i];
3123                 stats->q_errors[i] = hw_stats->qprdc[i];
3124         }
3125
3126         /* Rx Errors */
3127         stats->imissed  = total_missed_rx;
3128         stats->ierrors  = hw_stats->crcerrs +
3129                           hw_stats->mspdc +
3130                           hw_stats->rlec +
3131                           hw_stats->ruc +
3132                           hw_stats->roc +
3133                           hw_stats->illerrc +
3134                           hw_stats->errbc +
3135                           hw_stats->rfc +
3136                           hw_stats->fccrc +
3137                           hw_stats->fclast;
3138
3139         /* Tx Errors */
3140         stats->oerrors  = 0;
3141         return 0;
3142 }
3143
3144 static void
3145 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3146 {
3147         struct ixgbe_hw_stats *stats =
3148                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3149
3150         /* HW registers are cleared on read */
3151         ixgbe_dev_stats_get(dev, NULL);
3152
3153         /* Reset software totals */
3154         memset(stats, 0, sizeof(*stats));
3155 }
3156
3157 /* This function calculates the number of xstats based on the current config */
3158 static unsigned
3159 ixgbe_xstats_calc_num(void) {
3160         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3161                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3162                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3163 }
3164
3165 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3166         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3167 {
3168         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3169         unsigned stat, i, count;
3170
3171         if (xstats_names != NULL) {
3172                 count = 0;
3173
3174                 /* Note: limit >= cnt_stats checked upstream
3175                  * in rte_eth_xstats_names()
3176                  */
3177
3178                 /* Extended stats from ixgbe_hw_stats */
3179                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3180                         snprintf(xstats_names[count].name,
3181                                 sizeof(xstats_names[count].name),
3182                                 "%s",
3183                                 rte_ixgbe_stats_strings[i].name);
3184                         count++;
3185                 }
3186
3187                 /* MACsec Stats */
3188                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3189                         snprintf(xstats_names[count].name,
3190                                 sizeof(xstats_names[count].name),
3191                                 "%s",
3192                                 rte_ixgbe_macsec_strings[i].name);
3193                         count++;
3194                 }
3195
3196                 /* RX Priority Stats */
3197                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3198                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3199                                 snprintf(xstats_names[count].name,
3200                                         sizeof(xstats_names[count].name),
3201                                         "rx_priority%u_%s", i,
3202                                         rte_ixgbe_rxq_strings[stat].name);
3203                                 count++;
3204                         }
3205                 }
3206
3207                 /* TX Priority Stats */
3208                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3209                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3210                                 snprintf(xstats_names[count].name,
3211                                         sizeof(xstats_names[count].name),
3212                                         "tx_priority%u_%s", i,
3213                                         rte_ixgbe_txq_strings[stat].name);
3214                                 count++;
3215                         }
3216                 }
3217         }
3218         return cnt_stats;
3219 }
3220
3221 static int ixgbe_dev_xstats_get_names_by_id(
3222         struct rte_eth_dev *dev,
3223         struct rte_eth_xstat_name *xstats_names,
3224         const uint64_t *ids,
3225         unsigned int limit)
3226 {
3227         if (!ids) {
3228                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3229                 unsigned int stat, i, count;
3230
3231                 if (xstats_names != NULL) {
3232                         count = 0;
3233
3234                         /* Note: limit >= cnt_stats checked upstream
3235                          * in rte_eth_xstats_names()
3236                          */
3237
3238                         /* Extended stats from ixgbe_hw_stats */
3239                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3240                                 snprintf(xstats_names[count].name,
3241                                         sizeof(xstats_names[count].name),
3242                                         "%s",
3243                                         rte_ixgbe_stats_strings[i].name);
3244                                 count++;
3245                         }
3246
3247                         /* MACsec Stats */
3248                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3249                                 snprintf(xstats_names[count].name,
3250                                         sizeof(xstats_names[count].name),
3251                                         "%s",
3252                                         rte_ixgbe_macsec_strings[i].name);
3253                                 count++;
3254                         }
3255
3256                         /* RX Priority Stats */
3257                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3258                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3259                                         snprintf(xstats_names[count].name,
3260                                             sizeof(xstats_names[count].name),
3261                                             "rx_priority%u_%s", i,
3262                                             rte_ixgbe_rxq_strings[stat].name);
3263                                         count++;
3264                                 }
3265                         }
3266
3267                         /* TX Priority Stats */
3268                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3269                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3270                                         snprintf(xstats_names[count].name,
3271                                             sizeof(xstats_names[count].name),
3272                                             "tx_priority%u_%s", i,
3273                                             rte_ixgbe_txq_strings[stat].name);
3274                                         count++;
3275                                 }
3276                         }
3277                 }
3278                 return cnt_stats;
3279         }
3280
3281         uint16_t i;
3282         uint16_t size = ixgbe_xstats_calc_num();
3283         struct rte_eth_xstat_name xstats_names_copy[size];
3284
3285         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3286                         size);
3287
3288         for (i = 0; i < limit; i++) {
3289                 if (ids[i] >= size) {
3290                         PMD_INIT_LOG(ERR, "id value isn't valid");
3291                         return -1;
3292                 }
3293                 strcpy(xstats_names[i].name,
3294                                 xstats_names_copy[ids[i]].name);
3295         }
3296         return limit;
3297 }
3298
3299 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3300         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3301 {
3302         unsigned i;
3303
3304         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3305                 return -ENOMEM;
3306
3307         if (xstats_names != NULL)
3308                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3309                         snprintf(xstats_names[i].name,
3310                                 sizeof(xstats_names[i].name),
3311                                 "%s", rte_ixgbevf_stats_strings[i].name);
3312         return IXGBEVF_NB_XSTATS;
3313 }
3314
3315 static int
3316 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3317                                          unsigned n)
3318 {
3319         struct ixgbe_hw *hw =
3320                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3321         struct ixgbe_hw_stats *hw_stats =
3322                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3323         struct ixgbe_macsec_stats *macsec_stats =
3324                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3325                                 dev->data->dev_private);
3326         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3327         unsigned i, stat, count = 0;
3328
3329         count = ixgbe_xstats_calc_num();
3330
3331         if (n < count)
3332                 return count;
3333
3334         total_missed_rx = 0;
3335         total_qbrc = 0;
3336         total_qprc = 0;
3337         total_qprdc = 0;
3338
3339         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3340                         &total_qbrc, &total_qprc, &total_qprdc);
3341
3342         /* If this is a reset xstats is NULL, and we have cleared the
3343          * registers by reading them.
3344          */
3345         if (!xstats)
3346                 return 0;
3347
3348         /* Extended stats from ixgbe_hw_stats */
3349         count = 0;
3350         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3351                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3352                                 rte_ixgbe_stats_strings[i].offset);
3353                 xstats[count].id = count;
3354                 count++;
3355         }
3356
3357         /* MACsec Stats */
3358         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3359                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3360                                 rte_ixgbe_macsec_strings[i].offset);
3361                 xstats[count].id = count;
3362                 count++;
3363         }
3364
3365         /* RX Priority Stats */
3366         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3367                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3368                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3369                                         rte_ixgbe_rxq_strings[stat].offset +
3370                                         (sizeof(uint64_t) * i));
3371                         xstats[count].id = count;
3372                         count++;
3373                 }
3374         }
3375
3376         /* TX Priority Stats */
3377         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3378                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3379                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3380                                         rte_ixgbe_txq_strings[stat].offset +
3381                                         (sizeof(uint64_t) * i));
3382                         xstats[count].id = count;
3383                         count++;
3384                 }
3385         }
3386         return count;
3387 }
3388
3389 static int
3390 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3391                 uint64_t *values, unsigned int n)
3392 {
3393         if (!ids) {
3394                 struct ixgbe_hw *hw =
3395                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3396                 struct ixgbe_hw_stats *hw_stats =
3397                                 IXGBE_DEV_PRIVATE_TO_STATS(
3398                                                 dev->data->dev_private);
3399                 struct ixgbe_macsec_stats *macsec_stats =
3400                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3401                                         dev->data->dev_private);
3402                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3403                 unsigned int i, stat, count = 0;
3404
3405                 count = ixgbe_xstats_calc_num();
3406
3407                 if (!ids && n < count)
3408                         return count;
3409
3410                 total_missed_rx = 0;
3411                 total_qbrc = 0;
3412                 total_qprc = 0;
3413                 total_qprdc = 0;
3414
3415                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3416                                 &total_missed_rx, &total_qbrc, &total_qprc,
3417                                 &total_qprdc);
3418
3419                 /* If this is a reset xstats is NULL, and we have cleared the
3420                  * registers by reading them.
3421                  */
3422                 if (!ids && !values)
3423                         return 0;
3424
3425                 /* Extended stats from ixgbe_hw_stats */
3426                 count = 0;
3427                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3428                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3429                                         rte_ixgbe_stats_strings[i].offset);
3430                         count++;
3431                 }
3432
3433                 /* MACsec Stats */
3434                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3435                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3436                                         rte_ixgbe_macsec_strings[i].offset);
3437                         count++;
3438                 }
3439
3440                 /* RX Priority Stats */
3441                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3442                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3443                                 values[count] =
3444                                         *(uint64_t *)(((char *)hw_stats) +
3445                                         rte_ixgbe_rxq_strings[stat].offset +
3446                                         (sizeof(uint64_t) * i));
3447                                 count++;
3448                         }
3449                 }
3450
3451                 /* TX Priority Stats */
3452                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3453                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3454                                 values[count] =
3455                                         *(uint64_t *)(((char *)hw_stats) +
3456                                         rte_ixgbe_txq_strings[stat].offset +
3457                                         (sizeof(uint64_t) * i));
3458                                 count++;
3459                         }
3460                 }
3461                 return count;
3462         }
3463
3464         uint16_t i;
3465         uint16_t size = ixgbe_xstats_calc_num();
3466         uint64_t values_copy[size];
3467
3468         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3469
3470         for (i = 0; i < n; i++) {
3471                 if (ids[i] >= size) {
3472                         PMD_INIT_LOG(ERR, "id value isn't valid");
3473                         return -1;
3474                 }
3475                 values[i] = values_copy[ids[i]];
3476         }
3477         return n;
3478 }
3479
3480 static void
3481 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3482 {
3483         struct ixgbe_hw_stats *stats =
3484                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3485         struct ixgbe_macsec_stats *macsec_stats =
3486                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3487                                 dev->data->dev_private);
3488
3489         unsigned count = ixgbe_xstats_calc_num();
3490
3491         /* HW registers are cleared on read */
3492         ixgbe_dev_xstats_get(dev, NULL, count);
3493
3494         /* Reset software totals */
3495         memset(stats, 0, sizeof(*stats));
3496         memset(macsec_stats, 0, sizeof(*macsec_stats));
3497 }
3498
3499 static void
3500 ixgbevf_update_stats(struct rte_eth_dev *dev)
3501 {
3502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3503         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3504                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3505
3506         /* Good Rx packet, include VF loopback */
3507         UPDATE_VF_STAT(IXGBE_VFGPRC,
3508             hw_stats->last_vfgprc, hw_stats->vfgprc);
3509
3510         /* Good Rx octets, include VF loopback */
3511         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3512             hw_stats->last_vfgorc, hw_stats->vfgorc);
3513
3514         /* Good Tx packet, include VF loopback */
3515         UPDATE_VF_STAT(IXGBE_VFGPTC,
3516             hw_stats->last_vfgptc, hw_stats->vfgptc);
3517
3518         /* Good Tx octets, include VF loopback */
3519         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3520             hw_stats->last_vfgotc, hw_stats->vfgotc);
3521
3522         /* Rx Multicst Packet */
3523         UPDATE_VF_STAT(IXGBE_VFMPRC,
3524             hw_stats->last_vfmprc, hw_stats->vfmprc);
3525 }
3526
3527 static int
3528 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3529                        unsigned n)
3530 {
3531         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3532                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3533         unsigned i;
3534
3535         if (n < IXGBEVF_NB_XSTATS)
3536                 return IXGBEVF_NB_XSTATS;
3537
3538         ixgbevf_update_stats(dev);
3539
3540         if (!xstats)
3541                 return 0;
3542
3543         /* Extended stats */
3544         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3545                 xstats[i].id = i;
3546                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3547                         rte_ixgbevf_stats_strings[i].offset);
3548         }
3549
3550         return IXGBEVF_NB_XSTATS;
3551 }
3552
3553 static int
3554 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3555 {
3556         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3557                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3558
3559         ixgbevf_update_stats(dev);
3560
3561         if (stats == NULL)
3562                 return -EINVAL;
3563
3564         stats->ipackets = hw_stats->vfgprc;
3565         stats->ibytes = hw_stats->vfgorc;
3566         stats->opackets = hw_stats->vfgptc;
3567         stats->obytes = hw_stats->vfgotc;
3568         return 0;
3569 }
3570
3571 static void
3572 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3573 {
3574         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3575                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3576
3577         /* Sync HW register to the last stats */
3578         ixgbevf_dev_stats_get(dev, NULL);
3579
3580         /* reset HW current stats*/
3581         hw_stats->vfgprc = 0;
3582         hw_stats->vfgorc = 0;
3583         hw_stats->vfgptc = 0;
3584         hw_stats->vfgotc = 0;
3585 }
3586
3587 static int
3588 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3589 {
3590         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3591         u16 eeprom_verh, eeprom_verl;
3592         u32 etrack_id;
3593         int ret;
3594
3595         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3596         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3597
3598         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3599         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3600
3601         ret += 1; /* add the size of '\0' */
3602         if (fw_size < (u32)ret)
3603                 return ret;
3604         else
3605                 return 0;
3606 }
3607
3608 static void
3609 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3610 {
3611         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3613         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3614
3615         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3616         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3617         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3618                 /*
3619                  * When DCB/VT is off, maximum number of queues changes,
3620                  * except for 82598EB, which remains constant.
3621                  */
3622                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3623                                 hw->mac.type != ixgbe_mac_82598EB)
3624                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3625         }
3626         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3627         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3628         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3629         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3630         dev_info->max_vfs = pci_dev->max_vfs;
3631         if (hw->mac.type == ixgbe_mac_82598EB)
3632                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3633         else
3634                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3635         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3636         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3637         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3638                                      dev_info->rx_queue_offload_capa);
3639         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3640         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3641
3642         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3643                 .rx_thresh = {
3644                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3645                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3646                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3647                 },
3648                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3649                 .rx_drop_en = 0,
3650                 .offloads = 0,
3651         };
3652
3653         dev_info->default_txconf = (struct rte_eth_txconf) {
3654                 .tx_thresh = {
3655                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3656                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3657                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3658                 },
3659                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3660                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3661                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3662                              ETH_TXQ_FLAGS_NOOFFLOADS |
3663                              ETH_TXQ_FLAGS_IGNORE,
3664                 .offloads = 0,
3665         };
3666
3667         dev_info->rx_desc_lim = rx_desc_lim;
3668         dev_info->tx_desc_lim = tx_desc_lim;
3669
3670         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3671         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3672         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3673
3674         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3675         if (hw->mac.type == ixgbe_mac_X540 ||
3676             hw->mac.type == ixgbe_mac_X540_vf ||
3677             hw->mac.type == ixgbe_mac_X550 ||
3678             hw->mac.type == ixgbe_mac_X550_vf) {
3679                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3680         }
3681         if (hw->mac.type == ixgbe_mac_X550) {
3682                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3683                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3684         }
3685 }
3686
3687 static const uint32_t *
3688 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3689 {
3690         static const uint32_t ptypes[] = {
3691                 /* For non-vec functions,
3692                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3693                  * for vec functions,
3694                  * refers to _recv_raw_pkts_vec().
3695                  */
3696                 RTE_PTYPE_L2_ETHER,
3697                 RTE_PTYPE_L3_IPV4,
3698                 RTE_PTYPE_L3_IPV4_EXT,
3699                 RTE_PTYPE_L3_IPV6,
3700                 RTE_PTYPE_L3_IPV6_EXT,
3701                 RTE_PTYPE_L4_SCTP,
3702                 RTE_PTYPE_L4_TCP,
3703                 RTE_PTYPE_L4_UDP,
3704                 RTE_PTYPE_TUNNEL_IP,
3705                 RTE_PTYPE_INNER_L3_IPV6,
3706                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3707                 RTE_PTYPE_INNER_L4_TCP,
3708                 RTE_PTYPE_INNER_L4_UDP,
3709                 RTE_PTYPE_UNKNOWN
3710         };
3711
3712         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3713             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3714             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3715             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3716                 return ptypes;
3717
3718 #if defined(RTE_ARCH_X86)
3719         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3720             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3721                 return ptypes;
3722 #endif
3723         return NULL;
3724 }
3725
3726 static void
3727 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3728                      struct rte_eth_dev_info *dev_info)
3729 {
3730         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3732
3733         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3734         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3735         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3736         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3737         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3738         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3739         dev_info->max_vfs = pci_dev->max_vfs;
3740         if (hw->mac.type == ixgbe_mac_82598EB)
3741                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3742         else
3743                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3744         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3745         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3746                                      dev_info->rx_queue_offload_capa);
3747         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3748         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3749
3750         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3751                 .rx_thresh = {
3752                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3753                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3754                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3755                 },
3756                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3757                 .rx_drop_en = 0,
3758                 .offloads = 0,
3759         };
3760
3761         dev_info->default_txconf = (struct rte_eth_txconf) {
3762                 .tx_thresh = {
3763                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3764                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3765                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3766                 },
3767                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3768                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3769                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3770                              ETH_TXQ_FLAGS_NOOFFLOADS |
3771                              ETH_TXQ_FLAGS_IGNORE,
3772                 .offloads = 0,
3773         };
3774
3775         dev_info->rx_desc_lim = rx_desc_lim;
3776         dev_info->tx_desc_lim = tx_desc_lim;
3777 }
3778
3779 static int
3780 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3781                    int *link_up, int wait_to_complete)
3782 {
3783         /**
3784          * for a quick link status checking, wait_to_compelet == 0,
3785          * skip PF link status checking
3786          */
3787         bool no_pflink_check = wait_to_complete == 0;
3788         struct ixgbe_mbx_info *mbx = &hw->mbx;
3789         struct ixgbe_mac_info *mac = &hw->mac;
3790         uint32_t links_reg, in_msg;
3791         int ret_val = 0;
3792
3793         /* If we were hit with a reset drop the link */
3794         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3795                 mac->get_link_status = true;
3796
3797         if (!mac->get_link_status)
3798                 goto out;
3799
3800         /* if link status is down no point in checking to see if pf is up */
3801         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3802         if (!(links_reg & IXGBE_LINKS_UP))
3803                 goto out;
3804
3805         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3806          * before the link status is correct
3807          */
3808         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3809                 int i;
3810
3811                 for (i = 0; i < 5; i++) {
3812                         rte_delay_us(100);
3813                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3814
3815                         if (!(links_reg & IXGBE_LINKS_UP))
3816                                 goto out;
3817                 }
3818         }
3819
3820         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3821         case IXGBE_LINKS_SPEED_10G_82599:
3822                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3823                 if (hw->mac.type >= ixgbe_mac_X550) {
3824                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3825                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3826                 }
3827                 break;
3828         case IXGBE_LINKS_SPEED_1G_82599:
3829                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3830                 break;
3831         case IXGBE_LINKS_SPEED_100_82599:
3832                 *speed = IXGBE_LINK_SPEED_100_FULL;
3833                 if (hw->mac.type == ixgbe_mac_X550) {
3834                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3835                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3836                 }
3837                 break;
3838         case IXGBE_LINKS_SPEED_10_X550EM_A:
3839                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3840                 /* Since Reserved in older MAC's */
3841                 if (hw->mac.type >= ixgbe_mac_X550)
3842                         *speed = IXGBE_LINK_SPEED_10_FULL;
3843                 break;
3844         default:
3845                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3846         }
3847
3848         if (no_pflink_check) {
3849                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3850                         mac->get_link_status = true;
3851                 else
3852                         mac->get_link_status = false;
3853
3854                 goto out;
3855         }
3856         /* if the read failed it could just be a mailbox collision, best wait
3857          * until we are called again and don't report an error
3858          */
3859         if (mbx->ops.read(hw, &in_msg, 1, 0))
3860                 goto out;
3861
3862         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3863                 /* msg is not CTS and is NACK we must have lost CTS status */
3864                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3865                         ret_val = -1;
3866                 goto out;
3867         }
3868
3869         /* the pf is talking, if we timed out in the past we reinit */
3870         if (!mbx->timeout) {
3871                 ret_val = -1;
3872                 goto out;
3873         }
3874
3875         /* if we passed all the tests above then the link is up and we no
3876          * longer need to check for link
3877          */
3878         mac->get_link_status = false;
3879
3880 out:
3881         *link_up = !mac->get_link_status;
3882         return ret_val;
3883 }
3884
3885 /* return 0 means link status changed, -1 means not changed */
3886 static int
3887 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3888                             int wait_to_complete, int vf)
3889 {
3890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3891         struct rte_eth_link link;
3892         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3893         struct ixgbe_interrupt *intr =
3894                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3895         int link_up;
3896         int diag;
3897         u32 speed = 0;
3898         int wait = 1;
3899         bool autoneg = false;
3900
3901         memset(&link, 0, sizeof(link));
3902         link.link_status = ETH_LINK_DOWN;
3903         link.link_speed = 0;
3904         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3905         link.link_autoneg = ETH_LINK_AUTONEG;
3906
3907         hw->mac.get_link_status = true;
3908
3909         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3910                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3911                 speed = hw->phy.autoneg_advertised;
3912                 if (!speed)
3913                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3914                 ixgbe_setup_link(hw, speed, true);
3915         }
3916
3917         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3918         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3919                 wait = 0;
3920
3921         if (vf)
3922                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3923         else
3924                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3925
3926         if (diag != 0) {
3927                 link.link_speed = ETH_SPEED_NUM_100M;
3928                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3929                 return rte_eth_linkstatus_set(dev, &link);
3930         }
3931
3932         if (link_up == 0) {
3933                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3934                 return rte_eth_linkstatus_set(dev, &link);
3935         }
3936
3937         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3938         link.link_status = ETH_LINK_UP;
3939         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3940
3941         switch (link_speed) {
3942         default:
3943         case IXGBE_LINK_SPEED_UNKNOWN:
3944                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3945                 link.link_speed = ETH_SPEED_NUM_100M;
3946                 break;
3947
3948         case IXGBE_LINK_SPEED_100_FULL:
3949                 link.link_speed = ETH_SPEED_NUM_100M;
3950                 break;
3951
3952         case IXGBE_LINK_SPEED_1GB_FULL:
3953                 link.link_speed = ETH_SPEED_NUM_1G;
3954                 break;
3955
3956         case IXGBE_LINK_SPEED_2_5GB_FULL:
3957                 link.link_speed = ETH_SPEED_NUM_2_5G;
3958                 break;
3959
3960         case IXGBE_LINK_SPEED_5GB_FULL:
3961                 link.link_speed = ETH_SPEED_NUM_5G;
3962                 break;
3963
3964         case IXGBE_LINK_SPEED_10GB_FULL:
3965                 link.link_speed = ETH_SPEED_NUM_10G;
3966                 break;
3967         }
3968
3969         return rte_eth_linkstatus_set(dev, &link);
3970 }
3971
3972 static int
3973 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3974 {
3975         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3976 }
3977
3978 static int
3979 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3980 {
3981         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3982 }
3983
3984 static void
3985 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3986 {
3987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3988         uint32_t fctrl;
3989
3990         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3991         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3992         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3993 }
3994
3995 static void
3996 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3997 {
3998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3999         uint32_t fctrl;
4000
4001         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4002         fctrl &= (~IXGBE_FCTRL_UPE);
4003         if (dev->data->all_multicast == 1)
4004                 fctrl |= IXGBE_FCTRL_MPE;
4005         else
4006                 fctrl &= (~IXGBE_FCTRL_MPE);
4007         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4008 }
4009
4010 static void
4011 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4012 {
4013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4014         uint32_t fctrl;
4015
4016         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4017         fctrl |= IXGBE_FCTRL_MPE;
4018         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4019 }
4020
4021 static void
4022 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4023 {
4024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4025         uint32_t fctrl;
4026
4027         if (dev->data->promiscuous == 1)
4028                 return; /* must remain in all_multicast mode */
4029
4030         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4031         fctrl &= (~IXGBE_FCTRL_MPE);
4032         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4033 }
4034
4035 /**
4036  * It clears the interrupt causes and enables the interrupt.
4037  * It will be called once only during nic initialized.
4038  *
4039  * @param dev
4040  *  Pointer to struct rte_eth_dev.
4041  * @param on
4042  *  Enable or Disable.
4043  *
4044  * @return
4045  *  - On success, zero.
4046  *  - On failure, a negative value.
4047  */
4048 static int
4049 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4050 {
4051         struct ixgbe_interrupt *intr =
4052                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4053
4054         ixgbe_dev_link_status_print(dev);
4055         if (on)
4056                 intr->mask |= IXGBE_EICR_LSC;
4057         else
4058                 intr->mask &= ~IXGBE_EICR_LSC;
4059
4060         return 0;
4061 }
4062
4063 /**
4064  * It clears the interrupt causes and enables the interrupt.
4065  * It will be called once only during nic initialized.
4066  *
4067  * @param dev
4068  *  Pointer to struct rte_eth_dev.
4069  *
4070  * @return
4071  *  - On success, zero.
4072  *  - On failure, a negative value.
4073  */
4074 static int
4075 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4076 {
4077         struct ixgbe_interrupt *intr =
4078                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4079
4080         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4081
4082         return 0;
4083 }
4084
4085 /**
4086  * It clears the interrupt causes and enables the interrupt.
4087  * It will be called once only during nic initialized.
4088  *
4089  * @param dev
4090  *  Pointer to struct rte_eth_dev.
4091  *
4092  * @return
4093  *  - On success, zero.
4094  *  - On failure, a negative value.
4095  */
4096 static int
4097 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4098 {
4099         struct ixgbe_interrupt *intr =
4100                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4101
4102         intr->mask |= IXGBE_EICR_LINKSEC;
4103
4104         return 0;
4105 }
4106
4107 /*
4108  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4109  *
4110  * @param dev
4111  *  Pointer to struct rte_eth_dev.
4112  *
4113  * @return
4114  *  - On success, zero.
4115  *  - On failure, a negative value.
4116  */
4117 static int
4118 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4119 {
4120         uint32_t eicr;
4121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4122         struct ixgbe_interrupt *intr =
4123                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4124
4125         /* clear all cause mask */
4126         ixgbe_disable_intr(hw);
4127
4128         /* read-on-clear nic registers here */
4129         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4130         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4131
4132         intr->flags = 0;
4133
4134         /* set flag for async link update */
4135         if (eicr & IXGBE_EICR_LSC)
4136                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4137
4138         if (eicr & IXGBE_EICR_MAILBOX)
4139                 intr->flags |= IXGBE_FLAG_MAILBOX;
4140
4141         if (eicr & IXGBE_EICR_LINKSEC)
4142                 intr->flags |= IXGBE_FLAG_MACSEC;
4143
4144         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4145             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4146             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4147                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4148
4149         return 0;
4150 }
4151
4152 /**
4153  * It gets and then prints the link status.
4154  *
4155  * @param dev
4156  *  Pointer to struct rte_eth_dev.
4157  *
4158  * @return
4159  *  - On success, zero.
4160  *  - On failure, a negative value.
4161  */
4162 static void
4163 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4164 {
4165         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4166         struct rte_eth_link link;
4167
4168         rte_eth_linkstatus_get(dev, &link);
4169
4170         if (link.link_status) {
4171                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4172                                         (int)(dev->data->port_id),
4173                                         (unsigned)link.link_speed,
4174                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4175                                         "full-duplex" : "half-duplex");
4176         } else {
4177                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4178                                 (int)(dev->data->port_id));
4179         }
4180         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4181                                 pci_dev->addr.domain,
4182                                 pci_dev->addr.bus,
4183                                 pci_dev->addr.devid,
4184                                 pci_dev->addr.function);
4185 }
4186
4187 /*
4188  * It executes link_update after knowing an interrupt occurred.
4189  *
4190  * @param dev
4191  *  Pointer to struct rte_eth_dev.
4192  *
4193  * @return
4194  *  - On success, zero.
4195  *  - On failure, a negative value.
4196  */
4197 static int
4198 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4199                            struct rte_intr_handle *intr_handle)
4200 {
4201         struct ixgbe_interrupt *intr =
4202                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4203         int64_t timeout;
4204         struct ixgbe_hw *hw =
4205                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4206
4207         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4208
4209         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4210                 ixgbe_pf_mbx_process(dev);
4211                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4212         }
4213
4214         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4215                 ixgbe_handle_lasi(hw);
4216                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4217         }
4218
4219         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4220                 struct rte_eth_link link;
4221
4222                 /* get the link status before link update, for predicting later */
4223                 rte_eth_linkstatus_get(dev, &link);
4224
4225                 ixgbe_dev_link_update(dev, 0);
4226
4227                 /* likely to up */
4228                 if (!link.link_status)
4229                         /* handle it 1 sec later, wait it being stable */
4230                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4231                 /* likely to down */
4232                 else
4233                         /* handle it 4 sec later, wait it being stable */
4234                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4235
4236                 ixgbe_dev_link_status_print(dev);
4237                 if (rte_eal_alarm_set(timeout * 1000,
4238                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4239                         PMD_DRV_LOG(ERR, "Error setting alarm");
4240                 else {
4241                         /* remember original mask */
4242                         intr->mask_original = intr->mask;
4243                         /* only disable lsc interrupt */
4244                         intr->mask &= ~IXGBE_EIMS_LSC;
4245                 }
4246         }
4247
4248         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4249         ixgbe_enable_intr(dev);
4250         rte_intr_enable(intr_handle);
4251
4252         return 0;
4253 }
4254
4255 /**
4256  * Interrupt handler which shall be registered for alarm callback for delayed
4257  * handling specific interrupt to wait for the stable nic state. As the
4258  * NIC interrupt state is not stable for ixgbe after link is just down,
4259  * it needs to wait 4 seconds to get the stable status.
4260  *
4261  * @param handle
4262  *  Pointer to interrupt handle.
4263  * @param param
4264  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4265  *
4266  * @return
4267  *  void
4268  */
4269 static void
4270 ixgbe_dev_interrupt_delayed_handler(void *param)
4271 {
4272         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4273         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4274         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4275         struct ixgbe_interrupt *intr =
4276                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4277         struct ixgbe_hw *hw =
4278                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4279         uint32_t eicr;
4280
4281         ixgbe_disable_intr(hw);
4282
4283         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4284         if (eicr & IXGBE_EICR_MAILBOX)
4285                 ixgbe_pf_mbx_process(dev);
4286
4287         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4288                 ixgbe_handle_lasi(hw);
4289                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4290         }
4291
4292         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4293                 ixgbe_dev_link_update(dev, 0);
4294                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4295                 ixgbe_dev_link_status_print(dev);
4296                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4297                                               NULL);
4298         }
4299
4300         if (intr->flags & IXGBE_FLAG_MACSEC) {
4301                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4302                                               NULL);
4303                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4304         }
4305
4306         /* restore original mask */
4307         intr->mask = intr->mask_original;
4308         intr->mask_original = 0;
4309
4310         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4311         ixgbe_enable_intr(dev);
4312         rte_intr_enable(intr_handle);
4313 }
4314
4315 /**
4316  * Interrupt handler triggered by NIC  for handling
4317  * specific interrupt.
4318  *
4319  * @param handle
4320  *  Pointer to interrupt handle.
4321  * @param param
4322  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4323  *
4324  * @return
4325  *  void
4326  */
4327 static void
4328 ixgbe_dev_interrupt_handler(void *param)
4329 {
4330         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4331
4332         ixgbe_dev_interrupt_get_status(dev);
4333         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4334 }
4335
4336 static int
4337 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4338 {
4339         struct ixgbe_hw *hw;
4340
4341         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4343 }
4344
4345 static int
4346 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4347 {
4348         struct ixgbe_hw *hw;
4349
4350         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4352 }
4353
4354 static int
4355 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4356 {
4357         struct ixgbe_hw *hw;
4358         uint32_t mflcn_reg;
4359         uint32_t fccfg_reg;
4360         int rx_pause;
4361         int tx_pause;
4362
4363         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4364
4365         fc_conf->pause_time = hw->fc.pause_time;
4366         fc_conf->high_water = hw->fc.high_water[0];
4367         fc_conf->low_water = hw->fc.low_water[0];
4368         fc_conf->send_xon = hw->fc.send_xon;
4369         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4370
4371         /*
4372          * Return rx_pause status according to actual setting of
4373          * MFLCN register.
4374          */
4375         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4376         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4377                 rx_pause = 1;
4378         else
4379                 rx_pause = 0;
4380
4381         /*
4382          * Return tx_pause status according to actual setting of
4383          * FCCFG register.
4384          */
4385         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4386         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4387                 tx_pause = 1;
4388         else
4389                 tx_pause = 0;
4390
4391         if (rx_pause && tx_pause)
4392                 fc_conf->mode = RTE_FC_FULL;
4393         else if (rx_pause)
4394                 fc_conf->mode = RTE_FC_RX_PAUSE;
4395         else if (tx_pause)
4396                 fc_conf->mode = RTE_FC_TX_PAUSE;
4397         else
4398                 fc_conf->mode = RTE_FC_NONE;
4399
4400         return 0;
4401 }
4402
4403 static int
4404 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4405 {
4406         struct ixgbe_hw *hw;
4407         int err;
4408         uint32_t rx_buf_size;
4409         uint32_t max_high_water;
4410         uint32_t mflcn;
4411         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4412                 ixgbe_fc_none,
4413                 ixgbe_fc_rx_pause,
4414                 ixgbe_fc_tx_pause,
4415                 ixgbe_fc_full
4416         };
4417
4418         PMD_INIT_FUNC_TRACE();
4419
4420         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4422         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4423
4424         /*
4425          * At least reserve one Ethernet frame for watermark
4426          * high_water/low_water in kilo bytes for ixgbe
4427          */
4428         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4429         if ((fc_conf->high_water > max_high_water) ||
4430                 (fc_conf->high_water < fc_conf->low_water)) {
4431                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4432                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4433                 return -EINVAL;
4434         }
4435
4436         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4437         hw->fc.pause_time     = fc_conf->pause_time;
4438         hw->fc.high_water[0]  = fc_conf->high_water;
4439         hw->fc.low_water[0]   = fc_conf->low_water;
4440         hw->fc.send_xon       = fc_conf->send_xon;
4441         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4442
4443         err = ixgbe_fc_enable(hw);
4444
4445         /* Not negotiated is not an error case */
4446         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4447
4448                 /* check if we want to forward MAC frames - driver doesn't have native
4449                  * capability to do that, so we'll write the registers ourselves */
4450
4451                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4452
4453                 /* set or clear MFLCN.PMCF bit depending on configuration */
4454                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4455                         mflcn |= IXGBE_MFLCN_PMCF;
4456                 else
4457                         mflcn &= ~IXGBE_MFLCN_PMCF;
4458
4459                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4460                 IXGBE_WRITE_FLUSH(hw);
4461
4462                 return 0;
4463         }
4464
4465         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4466         return -EIO;
4467 }
4468
4469 /**
4470  *  ixgbe_pfc_enable_generic - Enable flow control
4471  *  @hw: pointer to hardware structure
4472  *  @tc_num: traffic class number
4473  *  Enable flow control according to the current settings.
4474  */
4475 static int
4476 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4477 {
4478         int ret_val = 0;
4479         uint32_t mflcn_reg, fccfg_reg;
4480         uint32_t reg;
4481         uint32_t fcrtl, fcrth;
4482         uint8_t i;
4483         uint8_t nb_rx_en;
4484
4485         /* Validate the water mark configuration */
4486         if (!hw->fc.pause_time) {
4487                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4488                 goto out;
4489         }
4490
4491         /* Low water mark of zero causes XOFF floods */
4492         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4493                  /* High/Low water can not be 0 */
4494                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4495                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4496                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4497                         goto out;
4498                 }
4499
4500                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4501                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4502                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4503                         goto out;
4504                 }
4505         }
4506         /* Negotiate the fc mode to use */
4507         ixgbe_fc_autoneg(hw);
4508
4509         /* Disable any previous flow control settings */
4510         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4511         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4512
4513         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4514         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4515
4516         switch (hw->fc.current_mode) {
4517         case ixgbe_fc_none:
4518                 /*
4519                  * If the count of enabled RX Priority Flow control >1,
4520                  * and the TX pause can not be disabled
4521                  */
4522                 nb_rx_en = 0;
4523                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4524                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4525                         if (reg & IXGBE_FCRTH_FCEN)
4526                                 nb_rx_en++;
4527                 }
4528                 if (nb_rx_en > 1)
4529                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4530                 break;
4531         case ixgbe_fc_rx_pause:
4532                 /*
4533                  * Rx Flow control is enabled and Tx Flow control is
4534                  * disabled by software override. Since there really
4535                  * isn't a way to advertise that we are capable of RX
4536                  * Pause ONLY, we will advertise that we support both
4537                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4538                  * disable the adapter's ability to send PAUSE frames.
4539                  */
4540                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4541                 /*
4542                  * If the count of enabled RX Priority Flow control >1,
4543                  * and the TX pause can not be disabled
4544                  */
4545                 nb_rx_en = 0;
4546                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4547                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4548                         if (reg & IXGBE_FCRTH_FCEN)
4549                                 nb_rx_en++;
4550                 }
4551                 if (nb_rx_en > 1)
4552                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4553                 break;
4554         case ixgbe_fc_tx_pause:
4555                 /*
4556                  * Tx Flow control is enabled, and Rx Flow control is
4557                  * disabled by software override.
4558                  */
4559                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4560                 break;
4561         case ixgbe_fc_full:
4562                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4563                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4564                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4565                 break;
4566         default:
4567                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4568                 ret_val = IXGBE_ERR_CONFIG;
4569                 goto out;
4570         }
4571
4572         /* Set 802.3x based flow control settings. */
4573         mflcn_reg |= IXGBE_MFLCN_DPF;
4574         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4575         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4576
4577         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4578         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4579                 hw->fc.high_water[tc_num]) {
4580                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4581                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4582                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4583         } else {
4584                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4585                 /*
4586                  * In order to prevent Tx hangs when the internal Tx
4587                  * switch is enabled we must set the high water mark
4588                  * to the maximum FCRTH value.  This allows the Tx
4589                  * switch to function even under heavy Rx workloads.
4590                  */
4591                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4592         }
4593         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4594
4595         /* Configure pause time (2 TCs per register) */
4596         reg = hw->fc.pause_time * 0x00010001;
4597         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4598                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4599
4600         /* Configure flow control refresh threshold value */
4601         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4602
4603 out:
4604         return ret_val;
4605 }
4606
4607 static int
4608 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4609 {
4610         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4611         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4612
4613         if (hw->mac.type != ixgbe_mac_82598EB) {
4614                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4615         }
4616         return ret_val;
4617 }
4618
4619 static int
4620 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4621 {
4622         int err;
4623         uint32_t rx_buf_size;
4624         uint32_t max_high_water;
4625         uint8_t tc_num;
4626         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4627         struct ixgbe_hw *hw =
4628                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629         struct ixgbe_dcb_config *dcb_config =
4630                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4631
4632         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4633                 ixgbe_fc_none,
4634                 ixgbe_fc_rx_pause,
4635                 ixgbe_fc_tx_pause,
4636                 ixgbe_fc_full
4637         };
4638
4639         PMD_INIT_FUNC_TRACE();
4640
4641         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4642         tc_num = map[pfc_conf->priority];
4643         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4644         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4645         /*
4646          * At least reserve one Ethernet frame for watermark
4647          * high_water/low_water in kilo bytes for ixgbe
4648          */
4649         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4650         if ((pfc_conf->fc.high_water > max_high_water) ||
4651             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4652                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4653                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4654                 return -EINVAL;
4655         }
4656
4657         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4658         hw->fc.pause_time = pfc_conf->fc.pause_time;
4659         hw->fc.send_xon = pfc_conf->fc.send_xon;
4660         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4661         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4662
4663         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4664
4665         /* Not negotiated is not an error case */
4666         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4667                 return 0;
4668
4669         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4670         return -EIO;
4671 }
4672
4673 static int
4674 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4675                           struct rte_eth_rss_reta_entry64 *reta_conf,
4676                           uint16_t reta_size)
4677 {
4678         uint16_t i, sp_reta_size;
4679         uint8_t j, mask;
4680         uint32_t reta, r;
4681         uint16_t idx, shift;
4682         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4683         uint32_t reta_reg;
4684
4685         PMD_INIT_FUNC_TRACE();
4686
4687         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4688                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4689                         "NIC.");
4690                 return -ENOTSUP;
4691         }
4692
4693         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4694         if (reta_size != sp_reta_size) {
4695                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4696                         "(%d) doesn't match the number hardware can supported "
4697                         "(%d)", reta_size, sp_reta_size);
4698                 return -EINVAL;
4699         }
4700
4701         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4702                 idx = i / RTE_RETA_GROUP_SIZE;
4703                 shift = i % RTE_RETA_GROUP_SIZE;
4704                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4705                                                 IXGBE_4_BIT_MASK);
4706                 if (!mask)
4707                         continue;
4708                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4709                 if (mask == IXGBE_4_BIT_MASK)
4710                         r = 0;
4711                 else
4712                         r = IXGBE_READ_REG(hw, reta_reg);
4713                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4714                         if (mask & (0x1 << j))
4715                                 reta |= reta_conf[idx].reta[shift + j] <<
4716                                                         (CHAR_BIT * j);
4717                         else
4718                                 reta |= r & (IXGBE_8_BIT_MASK <<
4719                                                 (CHAR_BIT * j));
4720                 }
4721                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4722         }
4723
4724         return 0;
4725 }
4726
4727 static int
4728 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4729                          struct rte_eth_rss_reta_entry64 *reta_conf,
4730                          uint16_t reta_size)
4731 {
4732         uint16_t i, sp_reta_size;
4733         uint8_t j, mask;
4734         uint32_t reta;
4735         uint16_t idx, shift;
4736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4737         uint32_t reta_reg;
4738
4739         PMD_INIT_FUNC_TRACE();
4740         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4741         if (reta_size != sp_reta_size) {
4742                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4743                         "(%d) doesn't match the number hardware can supported "
4744                         "(%d)", reta_size, sp_reta_size);
4745                 return -EINVAL;
4746         }
4747
4748         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4749                 idx = i / RTE_RETA_GROUP_SIZE;
4750                 shift = i % RTE_RETA_GROUP_SIZE;
4751                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4752                                                 IXGBE_4_BIT_MASK);
4753                 if (!mask)
4754                         continue;
4755
4756                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4757                 reta = IXGBE_READ_REG(hw, reta_reg);
4758                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4759                         if (mask & (0x1 << j))
4760                                 reta_conf[idx].reta[shift + j] =
4761                                         ((reta >> (CHAR_BIT * j)) &
4762                                                 IXGBE_8_BIT_MASK);
4763                 }
4764         }
4765
4766         return 0;
4767 }
4768
4769 static int
4770 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4771                                 uint32_t index, uint32_t pool)
4772 {
4773         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4774         uint32_t enable_addr = 1;
4775
4776         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4777                              pool, enable_addr);
4778 }
4779
4780 static void
4781 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4782 {
4783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4784
4785         ixgbe_clear_rar(hw, index);
4786 }
4787
4788 static void
4789 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4790 {
4791         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4792
4793         ixgbe_remove_rar(dev, 0);
4794
4795         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4796 }
4797
4798 static bool
4799 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4800 {
4801         if (strcmp(dev->device->driver->name, drv->driver.name))
4802                 return false;
4803
4804         return true;
4805 }
4806
4807 bool
4808 is_ixgbe_supported(struct rte_eth_dev *dev)
4809 {
4810         return is_device_supported(dev, &rte_ixgbe_pmd);
4811 }
4812
4813 static int
4814 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4815 {
4816         uint32_t hlreg0;
4817         uint32_t maxfrs;
4818         struct ixgbe_hw *hw;
4819         struct rte_eth_dev_info dev_info;
4820         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4821         struct rte_eth_dev_data *dev_data = dev->data;
4822
4823         ixgbe_dev_info_get(dev, &dev_info);
4824
4825         /* check that mtu is within the allowed range */
4826         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4827                 return -EINVAL;
4828
4829         /* If device is started, refuse mtu that requires the support of
4830          * scattered packets when this feature has not been enabled before.
4831          */
4832         if (dev_data->dev_started && !dev_data->scattered_rx &&
4833             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4834              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4835                 PMD_INIT_LOG(ERR, "Stop port first.");
4836                 return -EINVAL;
4837         }
4838
4839         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4840         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4841
4842         /* switch to jumbo mode if needed */
4843         if (frame_size > ETHER_MAX_LEN) {
4844                 dev->data->dev_conf.rxmode.offloads |=
4845                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4846                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4847         } else {
4848                 dev->data->dev_conf.rxmode.offloads &=
4849                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4850                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4851         }
4852         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4853
4854         /* update max frame size */
4855         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4856
4857         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4858         maxfrs &= 0x0000FFFF;
4859         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4860         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4861
4862         return 0;
4863 }
4864
4865 /*
4866  * Virtual Function operations
4867  */
4868 static void
4869 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4870 {
4871         PMD_INIT_FUNC_TRACE();
4872
4873         /* Clear interrupt mask to stop from interrupts being generated */
4874         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4875
4876         IXGBE_WRITE_FLUSH(hw);
4877 }
4878
4879 static void
4880 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4881 {
4882         PMD_INIT_FUNC_TRACE();
4883
4884         /* VF enable interrupt autoclean */
4885         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4886         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4887         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4888
4889         IXGBE_WRITE_FLUSH(hw);
4890 }
4891
4892 static int
4893 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4894 {
4895         struct rte_eth_conf *conf = &dev->data->dev_conf;
4896         struct ixgbe_adapter *adapter =
4897                         (struct ixgbe_adapter *)dev->data->dev_private;
4898         struct rte_eth_dev_info dev_info;
4899         uint64_t rx_offloads;
4900         uint64_t tx_offloads;
4901
4902         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4903                      dev->data->port_id);
4904
4905         ixgbevf_dev_info_get(dev, &dev_info);
4906         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4907         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4908                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4909                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4910                             rx_offloads, dev_info.rx_offload_capa);
4911                 return -ENOTSUP;
4912         }
4913         tx_offloads = dev->data->dev_conf.txmode.offloads;
4914         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4915                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4916                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4917                             tx_offloads, dev_info.tx_offload_capa);
4918                 return -ENOTSUP;
4919         }
4920
4921         /*
4922          * VF has no ability to enable/disable HW CRC
4923          * Keep the persistent behavior the same as Host PF
4924          */
4925 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4926         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4927                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4928                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4929         }
4930 #else
4931         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4932                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4933                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4934         }
4935 #endif
4936
4937         /*
4938          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4939          * allocation or vector Rx preconditions we will reset it.
4940          */
4941         adapter->rx_bulk_alloc_allowed = true;
4942         adapter->rx_vec_allowed = true;
4943
4944         return 0;
4945 }
4946
4947 static int
4948 ixgbevf_dev_start(struct rte_eth_dev *dev)
4949 {
4950         struct ixgbe_hw *hw =
4951                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4952         uint32_t intr_vector = 0;
4953         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4954         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4955
4956         int err, mask = 0;
4957
4958         PMD_INIT_FUNC_TRACE();
4959
4960         err = hw->mac.ops.reset_hw(hw);
4961         if (err) {
4962                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4963                 return err;
4964         }
4965         hw->mac.get_link_status = true;
4966
4967         /* negotiate mailbox API version to use with the PF. */
4968         ixgbevf_negotiate_api(hw);
4969
4970         ixgbevf_dev_tx_init(dev);
4971
4972         /* This can fail when allocating mbufs for descriptor rings */
4973         err = ixgbevf_dev_rx_init(dev);
4974         if (err) {
4975                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4976                 ixgbe_dev_clear_queues(dev);
4977                 return err;
4978         }
4979
4980         /* Set vfta */
4981         ixgbevf_set_vfta_all(dev, 1);
4982
4983         /* Set HW strip */
4984         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4985                 ETH_VLAN_EXTEND_MASK;
4986         err = ixgbevf_vlan_offload_set(dev, mask);
4987         if (err) {
4988                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4989                 ixgbe_dev_clear_queues(dev);
4990                 return err;
4991         }
4992
4993         ixgbevf_dev_rxtx_start(dev);
4994
4995         ixgbevf_dev_link_update(dev, 0);
4996
4997         /* check and configure queue intr-vector mapping */
4998         if (rte_intr_cap_multiple(intr_handle) &&
4999             dev->data->dev_conf.intr_conf.rxq) {
5000                 /* According to datasheet, only vector 0/1/2 can be used,
5001                  * now only one vector is used for Rx queue
5002                  */
5003                 intr_vector = 1;
5004                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5005                         return -1;
5006         }
5007
5008         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5009                 intr_handle->intr_vec =
5010                         rte_zmalloc("intr_vec",
5011                                     dev->data->nb_rx_queues * sizeof(int), 0);
5012                 if (intr_handle->intr_vec == NULL) {
5013                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5014                                      " intr_vec", dev->data->nb_rx_queues);
5015                         return -ENOMEM;
5016                 }
5017         }
5018         ixgbevf_configure_msix(dev);
5019
5020         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5021          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5022          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5023          * is not cleared, it will fail when following rte_intr_enable( ) tries
5024          * to map Rx queue interrupt to other VFIO vectors.
5025          * So clear uio/vfio intr/evevnfd first to avoid failure.
5026          */
5027         rte_intr_disable(intr_handle);
5028
5029         rte_intr_enable(intr_handle);
5030
5031         /* Re-enable interrupt for VF */
5032         ixgbevf_intr_enable(hw);
5033
5034         return 0;
5035 }
5036
5037 static void
5038 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5039 {
5040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5041         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5042         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5043
5044         PMD_INIT_FUNC_TRACE();
5045
5046         ixgbevf_intr_disable(hw);
5047
5048         hw->adapter_stopped = 1;
5049         ixgbe_stop_adapter(hw);
5050
5051         /*
5052           * Clear what we set, but we still keep shadow_vfta to
5053           * restore after device starts
5054           */
5055         ixgbevf_set_vfta_all(dev, 0);
5056
5057         /* Clear stored conf */
5058         dev->data->scattered_rx = 0;
5059
5060         ixgbe_dev_clear_queues(dev);
5061
5062         /* Clean datapath event and queue/vec mapping */
5063         rte_intr_efd_disable(intr_handle);
5064         if (intr_handle->intr_vec != NULL) {
5065                 rte_free(intr_handle->intr_vec);
5066                 intr_handle->intr_vec = NULL;
5067         }
5068 }
5069
5070 static void
5071 ixgbevf_dev_close(struct rte_eth_dev *dev)
5072 {
5073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5074
5075         PMD_INIT_FUNC_TRACE();
5076
5077         ixgbe_reset_hw(hw);
5078
5079         ixgbevf_dev_stop(dev);
5080
5081         ixgbe_dev_free_queues(dev);
5082
5083         /**
5084          * Remove the VF MAC address ro ensure
5085          * that the VF traffic goes to the PF
5086          * after stop, close and detach of the VF
5087          **/
5088         ixgbevf_remove_mac_addr(dev, 0);
5089 }
5090
5091 /*
5092  * Reset VF device
5093  */
5094 static int
5095 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5096 {
5097         int ret;
5098
5099         ret = eth_ixgbevf_dev_uninit(dev);
5100         if (ret)
5101                 return ret;
5102
5103         ret = eth_ixgbevf_dev_init(dev);
5104
5105         return ret;
5106 }
5107
5108 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5109 {
5110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5111         struct ixgbe_vfta *shadow_vfta =
5112                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5113         int i = 0, j = 0, vfta = 0, mask = 1;
5114
5115         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5116                 vfta = shadow_vfta->vfta[i];
5117                 if (vfta) {
5118                         mask = 1;
5119                         for (j = 0; j < 32; j++) {
5120                                 if (vfta & mask)
5121                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5122                                                        on, false);
5123                                 mask <<= 1;
5124                         }
5125                 }
5126         }
5127
5128 }
5129
5130 static int
5131 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5132 {
5133         struct ixgbe_hw *hw =
5134                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5135         struct ixgbe_vfta *shadow_vfta =
5136                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5137         uint32_t vid_idx = 0;
5138         uint32_t vid_bit = 0;
5139         int ret = 0;
5140
5141         PMD_INIT_FUNC_TRACE();
5142
5143         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5144         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5145         if (ret) {
5146                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5147                 return ret;
5148         }
5149         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5150         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5151
5152         /* Save what we set and retore it after device reset */
5153         if (on)
5154                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5155         else
5156                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5157
5158         return 0;
5159 }
5160
5161 static void
5162 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5163 {
5164         struct ixgbe_hw *hw =
5165                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5166         uint32_t ctrl;
5167
5168         PMD_INIT_FUNC_TRACE();
5169
5170         if (queue >= hw->mac.max_rx_queues)
5171                 return;
5172
5173         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5174         if (on)
5175                 ctrl |= IXGBE_RXDCTL_VME;
5176         else
5177                 ctrl &= ~IXGBE_RXDCTL_VME;
5178         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5179
5180         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5181 }
5182
5183 static int
5184 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5185 {
5186         struct ixgbe_hw *hw =
5187                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5188         struct ixgbe_rx_queue *rxq;
5189         uint16_t i;
5190         int on = 0;
5191
5192         /* VF function only support hw strip feature, others are not support */
5193         if (mask & ETH_VLAN_STRIP_MASK) {
5194                 for (i = 0; i < hw->mac.max_rx_queues; i++) {
5195                         rxq = dev->data->rx_queues[i];
5196                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5197                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5198                 }
5199         }
5200
5201         return 0;
5202 }
5203
5204 int
5205 ixgbe_vt_check(struct ixgbe_hw *hw)
5206 {
5207         uint32_t reg_val;
5208
5209         /* if Virtualization Technology is enabled */
5210         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5211         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5212                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5213                 return -1;
5214         }
5215
5216         return 0;
5217 }
5218
5219 static uint32_t
5220 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5221 {
5222         uint32_t vector = 0;
5223
5224         switch (hw->mac.mc_filter_type) {
5225         case 0:   /* use bits [47:36] of the address */
5226                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5227                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5228                 break;
5229         case 1:   /* use bits [46:35] of the address */
5230                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5231                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5232                 break;
5233         case 2:   /* use bits [45:34] of the address */
5234                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5235                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5236                 break;
5237         case 3:   /* use bits [43:32] of the address */
5238                 vector = ((uc_addr->addr_bytes[4]) |
5239                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5240                 break;
5241         default:  /* Invalid mc_filter_type */
5242                 break;
5243         }
5244
5245         /* vector can only be 12-bits or boundary will be exceeded */
5246         vector &= 0xFFF;
5247         return vector;
5248 }
5249
5250 static int
5251 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5252                         uint8_t on)
5253 {
5254         uint32_t vector;
5255         uint32_t uta_idx;
5256         uint32_t reg_val;
5257         uint32_t uta_shift;
5258         uint32_t rc;
5259         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5260         const uint32_t ixgbe_uta_bit_shift = 5;
5261         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5262         const uint32_t bit1 = 0x1;
5263
5264         struct ixgbe_hw *hw =
5265                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5266         struct ixgbe_uta_info *uta_info =
5267                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5268
5269         /* The UTA table only exists on 82599 hardware and newer */
5270         if (hw->mac.type < ixgbe_mac_82599EB)
5271                 return -ENOTSUP;
5272
5273         vector = ixgbe_uta_vector(hw, mac_addr);
5274         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5275         uta_shift = vector & ixgbe_uta_bit_mask;
5276
5277         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5278         if (rc == on)
5279                 return 0;
5280
5281         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5282         if (on) {
5283                 uta_info->uta_in_use++;
5284                 reg_val |= (bit1 << uta_shift);
5285                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5286         } else {
5287                 uta_info->uta_in_use--;
5288                 reg_val &= ~(bit1 << uta_shift);
5289                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5290         }
5291
5292         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5293
5294         if (uta_info->uta_in_use > 0)
5295                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5296                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5297         else
5298                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5299
5300         return 0;
5301 }
5302
5303 static int
5304 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5305 {
5306         int i;
5307         struct ixgbe_hw *hw =
5308                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5309         struct ixgbe_uta_info *uta_info =
5310                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5311
5312         /* The UTA table only exists on 82599 hardware and newer */
5313         if (hw->mac.type < ixgbe_mac_82599EB)
5314                 return -ENOTSUP;
5315
5316         if (on) {
5317                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5318                         uta_info->uta_shadow[i] = ~0;
5319                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5320                 }
5321         } else {
5322                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5323                         uta_info->uta_shadow[i] = 0;
5324                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5325                 }
5326         }
5327         return 0;
5328
5329 }
5330
5331 uint32_t
5332 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5333 {
5334         uint32_t new_val = orig_val;
5335
5336         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5337                 new_val |= IXGBE_VMOLR_AUPE;
5338         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5339                 new_val |= IXGBE_VMOLR_ROMPE;
5340         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5341                 new_val |= IXGBE_VMOLR_ROPE;
5342         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5343                 new_val |= IXGBE_VMOLR_BAM;
5344         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5345                 new_val |= IXGBE_VMOLR_MPE;
5346
5347         return new_val;
5348 }
5349
5350 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5351 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5352 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5353 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5354 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5355         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5356         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5357
5358 static int
5359 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5360                       struct rte_eth_mirror_conf *mirror_conf,
5361                       uint8_t rule_id, uint8_t on)
5362 {
5363         uint32_t mr_ctl, vlvf;
5364         uint32_t mp_lsb = 0;
5365         uint32_t mv_msb = 0;
5366         uint32_t mv_lsb = 0;
5367         uint32_t mp_msb = 0;
5368         uint8_t i = 0;
5369         int reg_index = 0;
5370         uint64_t vlan_mask = 0;
5371
5372         const uint8_t pool_mask_offset = 32;
5373         const uint8_t vlan_mask_offset = 32;
5374         const uint8_t dst_pool_offset = 8;
5375         const uint8_t rule_mr_offset  = 4;
5376         const uint8_t mirror_rule_mask = 0x0F;
5377
5378         struct ixgbe_mirror_info *mr_info =
5379                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5380         struct ixgbe_hw *hw =
5381                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5382         uint8_t mirror_type = 0;
5383
5384         if (ixgbe_vt_check(hw) < 0)
5385                 return -ENOTSUP;
5386
5387         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5388                 return -EINVAL;
5389
5390         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5391                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5392                             mirror_conf->rule_type);
5393                 return -EINVAL;
5394         }
5395
5396         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5397                 mirror_type |= IXGBE_MRCTL_VLME;
5398                 /* Check if vlan id is valid and find conresponding VLAN ID
5399                  * index in VLVF
5400                  */
5401                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5402                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5403                                 /* search vlan id related pool vlan filter
5404                                  * index
5405                                  */
5406                                 reg_index = ixgbe_find_vlvf_slot(
5407                                                 hw,
5408                                                 mirror_conf->vlan.vlan_id[i],
5409                                                 false);
5410                                 if (reg_index < 0)
5411                                         return -EINVAL;
5412                                 vlvf = IXGBE_READ_REG(hw,
5413                                                       IXGBE_VLVF(reg_index));
5414                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5415                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5416                                       mirror_conf->vlan.vlan_id[i]))
5417                                         vlan_mask |= (1ULL << reg_index);
5418                                 else
5419                                         return -EINVAL;
5420                         }
5421                 }
5422
5423                 if (on) {
5424                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5425                         mv_msb = vlan_mask >> vlan_mask_offset;
5426
5427                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5428                                                 mirror_conf->vlan.vlan_mask;
5429                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5430                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5431                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5432                                                 mirror_conf->vlan.vlan_id[i];
5433                         }
5434                 } else {
5435                         mv_lsb = 0;
5436                         mv_msb = 0;
5437                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5438                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5439                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5440                 }
5441         }
5442
5443         /**
5444          * if enable pool mirror, write related pool mask register,if disable
5445          * pool mirror, clear PFMRVM register
5446          */
5447         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5448                 mirror_type |= IXGBE_MRCTL_VPME;
5449                 if (on) {
5450                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5451                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5452                         mr_info->mr_conf[rule_id].pool_mask =
5453                                         mirror_conf->pool_mask;
5454
5455                 } else {
5456                         mp_lsb = 0;
5457                         mp_msb = 0;
5458                         mr_info->mr_conf[rule_id].pool_mask = 0;
5459                 }
5460         }
5461         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5462                 mirror_type |= IXGBE_MRCTL_UPME;
5463         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5464                 mirror_type |= IXGBE_MRCTL_DPME;
5465
5466         /* read  mirror control register and recalculate it */
5467         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5468
5469         if (on) {
5470                 mr_ctl |= mirror_type;
5471                 mr_ctl &= mirror_rule_mask;
5472                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5473         } else {
5474                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5475         }
5476
5477         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5478         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5479
5480         /* write mirrror control  register */
5481         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5482
5483         /* write pool mirrror control  register */
5484         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5485                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5486                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5487                                 mp_msb);
5488         }
5489         /* write VLAN mirrror control  register */
5490         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5491                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5492                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5493                                 mv_msb);
5494         }
5495
5496         return 0;
5497 }
5498
5499 static int
5500 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5501 {
5502         int mr_ctl = 0;
5503         uint32_t lsb_val = 0;
5504         uint32_t msb_val = 0;
5505         const uint8_t rule_mr_offset = 4;
5506
5507         struct ixgbe_hw *hw =
5508                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5509         struct ixgbe_mirror_info *mr_info =
5510                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5511
5512         if (ixgbe_vt_check(hw) < 0)
5513                 return -ENOTSUP;
5514
5515         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5516                 return -EINVAL;
5517
5518         memset(&mr_info->mr_conf[rule_id], 0,
5519                sizeof(struct rte_eth_mirror_conf));
5520
5521         /* clear PFVMCTL register */
5522         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5523
5524         /* clear pool mask register */
5525         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5526         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5527
5528         /* clear vlan mask register */
5529         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5530         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5531
5532         return 0;
5533 }
5534
5535 static int
5536 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5537 {
5538         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5539         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5540         uint32_t mask;
5541         struct ixgbe_hw *hw =
5542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5543         uint32_t vec = IXGBE_MISC_VEC_ID;
5544
5545         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5546         if (rte_intr_allow_others(intr_handle))
5547                 vec = IXGBE_RX_VEC_START;
5548         mask |= (1 << vec);
5549         RTE_SET_USED(queue_id);
5550         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5551
5552         rte_intr_enable(intr_handle);
5553
5554         return 0;
5555 }
5556
5557 static int
5558 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5559 {
5560         uint32_t mask;
5561         struct ixgbe_hw *hw =
5562                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5563         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5564         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5565         uint32_t vec = IXGBE_MISC_VEC_ID;
5566
5567         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5568         if (rte_intr_allow_others(intr_handle))
5569                 vec = IXGBE_RX_VEC_START;
5570         mask &= ~(1 << vec);
5571         RTE_SET_USED(queue_id);
5572         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5573
5574         return 0;
5575 }
5576
5577 static int
5578 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5579 {
5580         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5581         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5582         uint32_t mask;
5583         struct ixgbe_hw *hw =
5584                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5585         struct ixgbe_interrupt *intr =
5586                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5587
5588         if (queue_id < 16) {
5589                 ixgbe_disable_intr(hw);
5590                 intr->mask |= (1 << queue_id);
5591                 ixgbe_enable_intr(dev);
5592         } else if (queue_id < 32) {
5593                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5594                 mask &= (1 << queue_id);
5595                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5596         } else if (queue_id < 64) {
5597                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5598                 mask &= (1 << (queue_id - 32));
5599                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5600         }
5601         rte_intr_enable(intr_handle);
5602
5603         return 0;
5604 }
5605
5606 static int
5607 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5608 {
5609         uint32_t mask;
5610         struct ixgbe_hw *hw =
5611                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5612         struct ixgbe_interrupt *intr =
5613                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5614
5615         if (queue_id < 16) {
5616                 ixgbe_disable_intr(hw);
5617                 intr->mask &= ~(1 << queue_id);
5618                 ixgbe_enable_intr(dev);
5619         } else if (queue_id < 32) {
5620                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5621                 mask &= ~(1 << queue_id);
5622                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5623         } else if (queue_id < 64) {
5624                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5625                 mask &= ~(1 << (queue_id - 32));
5626                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5627         }
5628
5629         return 0;
5630 }
5631
5632 static void
5633 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5634                      uint8_t queue, uint8_t msix_vector)
5635 {
5636         uint32_t tmp, idx;
5637
5638         if (direction == -1) {
5639                 /* other causes */
5640                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5641                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5642                 tmp &= ~0xFF;
5643                 tmp |= msix_vector;
5644                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5645         } else {
5646                 /* rx or tx cause */
5647                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5648                 idx = ((16 * (queue & 1)) + (8 * direction));
5649                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5650                 tmp &= ~(0xFF << idx);
5651                 tmp |= (msix_vector << idx);
5652                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5653         }
5654 }
5655
5656 /**
5657  * set the IVAR registers, mapping interrupt causes to vectors
5658  * @param hw
5659  *  pointer to ixgbe_hw struct
5660  * @direction
5661  *  0 for Rx, 1 for Tx, -1 for other causes
5662  * @queue
5663  *  queue to map the corresponding interrupt to
5664  * @msix_vector
5665  *  the vector to map to the corresponding queue
5666  */
5667 static void
5668 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5669                    uint8_t queue, uint8_t msix_vector)
5670 {
5671         uint32_t tmp, idx;
5672
5673         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5674         if (hw->mac.type == ixgbe_mac_82598EB) {
5675                 if (direction == -1)
5676                         direction = 0;
5677                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5678                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5679                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5680                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5681                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5682         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5683                         (hw->mac.type == ixgbe_mac_X540) ||
5684                         (hw->mac.type == ixgbe_mac_X550)) {
5685                 if (direction == -1) {
5686                         /* other causes */
5687                         idx = ((queue & 1) * 8);
5688                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5689                         tmp &= ~(0xFF << idx);
5690                         tmp |= (msix_vector << idx);
5691                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5692                 } else {
5693                         /* rx or tx causes */
5694                         idx = ((16 * (queue & 1)) + (8 * direction));
5695                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5696                         tmp &= ~(0xFF << idx);
5697                         tmp |= (msix_vector << idx);
5698                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5699                 }
5700         }
5701 }
5702
5703 static void
5704 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5705 {
5706         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5707         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5708         struct ixgbe_hw *hw =
5709                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5710         uint32_t q_idx;
5711         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5712         uint32_t base = IXGBE_MISC_VEC_ID;
5713
5714         /* Configure VF other cause ivar */
5715         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5716
5717         /* won't configure msix register if no mapping is done
5718          * between intr vector and event fd.
5719          */
5720         if (!rte_intr_dp_is_en(intr_handle))
5721                 return;
5722
5723         if (rte_intr_allow_others(intr_handle)) {
5724                 base = IXGBE_RX_VEC_START;
5725                 vector_idx = IXGBE_RX_VEC_START;
5726         }
5727
5728         /* Configure all RX queues of VF */
5729         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5730                 /* Force all queue use vector 0,
5731                  * as IXGBE_VF_MAXMSIVECOTR = 1
5732                  */
5733                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5734                 intr_handle->intr_vec[q_idx] = vector_idx;
5735                 if (vector_idx < base + intr_handle->nb_efd - 1)
5736                         vector_idx++;
5737         }
5738 }
5739
5740 /**
5741  * Sets up the hardware to properly generate MSI-X interrupts
5742  * @hw
5743  *  board private structure
5744  */
5745 static void
5746 ixgbe_configure_msix(struct rte_eth_dev *dev)
5747 {
5748         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5749         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5750         struct ixgbe_hw *hw =
5751                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5752         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5753         uint32_t vec = IXGBE_MISC_VEC_ID;
5754         uint32_t mask;
5755         uint32_t gpie;
5756
5757         /* won't configure msix register if no mapping is done
5758          * between intr vector and event fd
5759          */
5760         if (!rte_intr_dp_is_en(intr_handle))
5761                 return;
5762
5763         if (rte_intr_allow_others(intr_handle))
5764                 vec = base = IXGBE_RX_VEC_START;
5765
5766         /* setup GPIE for MSI-x mode */
5767         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5768         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5769                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5770         /* auto clearing and auto setting corresponding bits in EIMS
5771          * when MSI-X interrupt is triggered
5772          */
5773         if (hw->mac.type == ixgbe_mac_82598EB) {
5774                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5775         } else {
5776                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5777                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5778         }
5779         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5780
5781         /* Populate the IVAR table and set the ITR values to the
5782          * corresponding register.
5783          */
5784         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5785              queue_id++) {
5786                 /* by default, 1:1 mapping */
5787                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5788                 intr_handle->intr_vec[queue_id] = vec;
5789                 if (vec < base + intr_handle->nb_efd - 1)
5790                         vec++;
5791         }
5792
5793         switch (hw->mac.type) {
5794         case ixgbe_mac_82598EB:
5795                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5796                                    IXGBE_MISC_VEC_ID);
5797                 break;
5798         case ixgbe_mac_82599EB:
5799         case ixgbe_mac_X540:
5800         case ixgbe_mac_X550:
5801                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5802                 break;
5803         default:
5804                 break;
5805         }
5806         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5807                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5808
5809         /* set up to autoclear timer, and the vectors */
5810         mask = IXGBE_EIMS_ENABLE_MASK;
5811         mask &= ~(IXGBE_EIMS_OTHER |
5812                   IXGBE_EIMS_MAILBOX |
5813                   IXGBE_EIMS_LSC);
5814
5815         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5816 }
5817
5818 int
5819 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5820                            uint16_t queue_idx, uint16_t tx_rate)
5821 {
5822         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5823         struct rte_eth_rxmode *rxmode;
5824         uint32_t rf_dec, rf_int;
5825         uint32_t bcnrc_val;
5826         uint16_t link_speed = dev->data->dev_link.link_speed;
5827
5828         if (queue_idx >= hw->mac.max_tx_queues)
5829                 return -EINVAL;
5830
5831         if (tx_rate != 0) {
5832                 /* Calculate the rate factor values to set */
5833                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5834                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5835                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5836
5837                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5838                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5839                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5840                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5841         } else {
5842                 bcnrc_val = 0;
5843         }
5844
5845         rxmode = &dev->data->dev_conf.rxmode;
5846         /*
5847          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5848          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5849          * set as 0x4.
5850          */
5851         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5852             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5853                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5854                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5855         else
5856                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5857                         IXGBE_MMW_SIZE_DEFAULT);
5858
5859         /* Set RTTBCNRC of queue X */
5860         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5861         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5862         IXGBE_WRITE_FLUSH(hw);
5863
5864         return 0;
5865 }
5866
5867 static int
5868 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5869                      __attribute__((unused)) uint32_t index,
5870                      __attribute__((unused)) uint32_t pool)
5871 {
5872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5873         int diag;
5874
5875         /*
5876          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5877          * operation. Trap this case to avoid exhausting the [very limited]
5878          * set of PF resources used to store VF MAC addresses.
5879          */
5880         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5881                 return -1;
5882         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5883         if (diag != 0)
5884                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5885                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5886                             mac_addr->addr_bytes[0],
5887                             mac_addr->addr_bytes[1],
5888                             mac_addr->addr_bytes[2],
5889                             mac_addr->addr_bytes[3],
5890                             mac_addr->addr_bytes[4],
5891                             mac_addr->addr_bytes[5],
5892                             diag);
5893         return diag;
5894 }
5895
5896 static void
5897 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5898 {
5899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5900         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5901         struct ether_addr *mac_addr;
5902         uint32_t i;
5903         int diag;
5904
5905         /*
5906          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5907          * not support the deletion of a given MAC address.
5908          * Instead, it imposes to delete all MAC addresses, then to add again
5909          * all MAC addresses with the exception of the one to be deleted.
5910          */
5911         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5912
5913         /*
5914          * Add again all MAC addresses, with the exception of the deleted one
5915          * and of the permanent MAC address.
5916          */
5917         for (i = 0, mac_addr = dev->data->mac_addrs;
5918              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5919                 /* Skip the deleted MAC address */
5920                 if (i == index)
5921                         continue;
5922                 /* Skip NULL MAC addresses */
5923                 if (is_zero_ether_addr(mac_addr))
5924                         continue;
5925                 /* Skip the permanent MAC address */
5926                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5927                         continue;
5928                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5929                 if (diag != 0)
5930                         PMD_DRV_LOG(ERR,
5931                                     "Adding again MAC address "
5932                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5933                                     "diag=%d",
5934                                     mac_addr->addr_bytes[0],
5935                                     mac_addr->addr_bytes[1],
5936                                     mac_addr->addr_bytes[2],
5937                                     mac_addr->addr_bytes[3],
5938                                     mac_addr->addr_bytes[4],
5939                                     mac_addr->addr_bytes[5],
5940                                     diag);
5941         }
5942 }
5943
5944 static void
5945 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5946 {
5947         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5948
5949         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5950 }
5951
5952 int
5953 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5954                         struct rte_eth_syn_filter *filter,
5955                         bool add)
5956 {
5957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5958         struct ixgbe_filter_info *filter_info =
5959                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5960         uint32_t syn_info;
5961         uint32_t synqf;
5962
5963         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5964                 return -EINVAL;
5965
5966         syn_info = filter_info->syn_info;
5967
5968         if (add) {
5969                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5970                         return -EINVAL;
5971                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5972                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5973
5974                 if (filter->hig_pri)
5975                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5976                 else
5977                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5978         } else {
5979                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5980                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5981                         return -ENOENT;
5982                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5983         }
5984
5985         filter_info->syn_info = synqf;
5986         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5987         IXGBE_WRITE_FLUSH(hw);
5988         return 0;
5989 }
5990
5991 static int
5992 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5993                         struct rte_eth_syn_filter *filter)
5994 {
5995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5996         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5997
5998         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5999                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6000                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6001                 return 0;
6002         }
6003         return -ENOENT;
6004 }
6005
6006 static int
6007 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6008                         enum rte_filter_op filter_op,
6009                         void *arg)
6010 {
6011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6012         int ret;
6013
6014         MAC_TYPE_FILTER_SUP(hw->mac.type);
6015
6016         if (filter_op == RTE_ETH_FILTER_NOP)
6017                 return 0;
6018
6019         if (arg == NULL) {
6020                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6021                             filter_op);
6022                 return -EINVAL;
6023         }
6024
6025         switch (filter_op) {
6026         case RTE_ETH_FILTER_ADD:
6027                 ret = ixgbe_syn_filter_set(dev,
6028                                 (struct rte_eth_syn_filter *)arg,
6029                                 TRUE);
6030                 break;
6031         case RTE_ETH_FILTER_DELETE:
6032                 ret = ixgbe_syn_filter_set(dev,
6033                                 (struct rte_eth_syn_filter *)arg,
6034                                 FALSE);
6035                 break;
6036         case RTE_ETH_FILTER_GET:
6037                 ret = ixgbe_syn_filter_get(dev,
6038                                 (struct rte_eth_syn_filter *)arg);
6039                 break;
6040         default:
6041                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6042                 ret = -EINVAL;
6043                 break;
6044         }
6045
6046         return ret;
6047 }
6048
6049
6050 static inline enum ixgbe_5tuple_protocol
6051 convert_protocol_type(uint8_t protocol_value)
6052 {
6053         if (protocol_value == IPPROTO_TCP)
6054                 return IXGBE_FILTER_PROTOCOL_TCP;
6055         else if (protocol_value == IPPROTO_UDP)
6056                 return IXGBE_FILTER_PROTOCOL_UDP;
6057         else if (protocol_value == IPPROTO_SCTP)
6058                 return IXGBE_FILTER_PROTOCOL_SCTP;
6059         else
6060                 return IXGBE_FILTER_PROTOCOL_NONE;
6061 }
6062
6063 /* inject a 5-tuple filter to HW */
6064 static inline void
6065 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6066                            struct ixgbe_5tuple_filter *filter)
6067 {
6068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6069         int i;
6070         uint32_t ftqf, sdpqf;
6071         uint32_t l34timir = 0;
6072         uint8_t mask = 0xff;
6073
6074         i = filter->index;
6075
6076         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6077                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6078         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6079
6080         ftqf = (uint32_t)(filter->filter_info.proto &
6081                 IXGBE_FTQF_PROTOCOL_MASK);
6082         ftqf |= (uint32_t)((filter->filter_info.priority &
6083                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6084         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6085                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6086         if (filter->filter_info.dst_ip_mask == 0)
6087                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6088         if (filter->filter_info.src_port_mask == 0)
6089                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6090         if (filter->filter_info.dst_port_mask == 0)
6091                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6092         if (filter->filter_info.proto_mask == 0)
6093                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6094         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6095         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6096         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6097
6098         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6099         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6100         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6101         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6102
6103         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6104         l34timir |= (uint32_t)(filter->queue <<
6105                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6106         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6107 }
6108
6109 /*
6110  * add a 5tuple filter
6111  *
6112  * @param
6113  * dev: Pointer to struct rte_eth_dev.
6114  * index: the index the filter allocates.
6115  * filter: ponter to the filter that will be added.
6116  * rx_queue: the queue id the filter assigned to.
6117  *
6118  * @return
6119  *    - On success, zero.
6120  *    - On failure, a negative value.
6121  */
6122 static int
6123 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6124                         struct ixgbe_5tuple_filter *filter)
6125 {
6126         struct ixgbe_filter_info *filter_info =
6127                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6128         int i, idx, shift;
6129
6130         /*
6131          * look for an unused 5tuple filter index,
6132          * and insert the filter to list.
6133          */
6134         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6135                 idx = i / (sizeof(uint32_t) * NBBY);
6136                 shift = i % (sizeof(uint32_t) * NBBY);
6137                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6138                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6139                         filter->index = i;
6140                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6141                                           filter,
6142                                           entries);
6143                         break;
6144                 }
6145         }
6146         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6147                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6148                 return -ENOSYS;
6149         }
6150
6151         ixgbe_inject_5tuple_filter(dev, filter);
6152
6153         return 0;
6154 }
6155
6156 /*
6157  * remove a 5tuple filter
6158  *
6159  * @param
6160  * dev: Pointer to struct rte_eth_dev.
6161  * filter: the pointer of the filter will be removed.
6162  */
6163 static void
6164 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6165                         struct ixgbe_5tuple_filter *filter)
6166 {
6167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6168         struct ixgbe_filter_info *filter_info =
6169                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6170         uint16_t index = filter->index;
6171
6172         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6173                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6174         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6175         rte_free(filter);
6176
6177         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6178         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6179         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6180         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6181         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6182 }
6183
6184 static int
6185 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6186 {
6187         struct ixgbe_hw *hw;
6188         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6189         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6190
6191         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6192
6193         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6194                 return -EINVAL;
6195
6196         /* refuse mtu that requires the support of scattered packets when this
6197          * feature has not been enabled before.
6198          */
6199         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6200             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6201              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6202                 return -EINVAL;
6203
6204         /*
6205          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6206          * request of the version 2.0 of the mailbox API.
6207          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6208          * of the mailbox API.
6209          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6210          * prior to 3.11.33 which contains the following change:
6211          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6212          */
6213         ixgbevf_rlpml_set_vf(hw, max_frame);
6214
6215         /* update max frame size */
6216         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6217         return 0;
6218 }
6219
6220 static inline struct ixgbe_5tuple_filter *
6221 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6222                         struct ixgbe_5tuple_filter_info *key)
6223 {
6224         struct ixgbe_5tuple_filter *it;
6225
6226         TAILQ_FOREACH(it, filter_list, entries) {
6227                 if (memcmp(key, &it->filter_info,
6228                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6229                         return it;
6230                 }
6231         }
6232         return NULL;
6233 }
6234
6235 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6236 static inline int
6237 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6238                         struct ixgbe_5tuple_filter_info *filter_info)
6239 {
6240         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6241                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6242                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6243                 return -EINVAL;
6244
6245         switch (filter->dst_ip_mask) {
6246         case UINT32_MAX:
6247                 filter_info->dst_ip_mask = 0;
6248                 filter_info->dst_ip = filter->dst_ip;
6249                 break;
6250         case 0:
6251                 filter_info->dst_ip_mask = 1;
6252                 break;
6253         default:
6254                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6255                 return -EINVAL;
6256         }
6257
6258         switch (filter->src_ip_mask) {
6259         case UINT32_MAX:
6260                 filter_info->src_ip_mask = 0;
6261                 filter_info->src_ip = filter->src_ip;
6262                 break;
6263         case 0:
6264                 filter_info->src_ip_mask = 1;
6265                 break;
6266         default:
6267                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6268                 return -EINVAL;
6269         }
6270
6271         switch (filter->dst_port_mask) {
6272         case UINT16_MAX:
6273                 filter_info->dst_port_mask = 0;
6274                 filter_info->dst_port = filter->dst_port;
6275                 break;
6276         case 0:
6277                 filter_info->dst_port_mask = 1;
6278                 break;
6279         default:
6280                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6281                 return -EINVAL;
6282         }
6283
6284         switch (filter->src_port_mask) {
6285         case UINT16_MAX:
6286                 filter_info->src_port_mask = 0;
6287                 filter_info->src_port = filter->src_port;
6288                 break;
6289         case 0:
6290                 filter_info->src_port_mask = 1;
6291                 break;
6292         default:
6293                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6294                 return -EINVAL;
6295         }
6296
6297         switch (filter->proto_mask) {
6298         case UINT8_MAX:
6299                 filter_info->proto_mask = 0;
6300                 filter_info->proto =
6301                         convert_protocol_type(filter->proto);
6302                 break;
6303         case 0:
6304                 filter_info->proto_mask = 1;
6305                 break;
6306         default:
6307                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6308                 return -EINVAL;
6309         }
6310
6311         filter_info->priority = (uint8_t)filter->priority;
6312         return 0;
6313 }
6314
6315 /*
6316  * add or delete a ntuple filter
6317  *
6318  * @param
6319  * dev: Pointer to struct rte_eth_dev.
6320  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6321  * add: if true, add filter, if false, remove filter
6322  *
6323  * @return
6324  *    - On success, zero.
6325  *    - On failure, a negative value.
6326  */
6327 int
6328 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6329                         struct rte_eth_ntuple_filter *ntuple_filter,
6330                         bool add)
6331 {
6332         struct ixgbe_filter_info *filter_info =
6333                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6334         struct ixgbe_5tuple_filter_info filter_5tuple;
6335         struct ixgbe_5tuple_filter *filter;
6336         int ret;
6337
6338         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6339                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6340                 return -EINVAL;
6341         }
6342
6343         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6344         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6345         if (ret < 0)
6346                 return ret;
6347
6348         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6349                                          &filter_5tuple);
6350         if (filter != NULL && add) {
6351                 PMD_DRV_LOG(ERR, "filter exists.");
6352                 return -EEXIST;
6353         }
6354         if (filter == NULL && !add) {
6355                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6356                 return -ENOENT;
6357         }
6358
6359         if (add) {
6360                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6361                                 sizeof(struct ixgbe_5tuple_filter), 0);
6362                 if (filter == NULL)
6363                         return -ENOMEM;
6364                 rte_memcpy(&filter->filter_info,
6365                                  &filter_5tuple,
6366                                  sizeof(struct ixgbe_5tuple_filter_info));
6367                 filter->queue = ntuple_filter->queue;
6368                 ret = ixgbe_add_5tuple_filter(dev, filter);
6369                 if (ret < 0) {
6370                         rte_free(filter);
6371                         return ret;
6372                 }
6373         } else
6374                 ixgbe_remove_5tuple_filter(dev, filter);
6375
6376         return 0;
6377 }
6378
6379 /*
6380  * get a ntuple filter
6381  *
6382  * @param
6383  * dev: Pointer to struct rte_eth_dev.
6384  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6385  *
6386  * @return
6387  *    - On success, zero.
6388  *    - On failure, a negative value.
6389  */
6390 static int
6391 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6392                         struct rte_eth_ntuple_filter *ntuple_filter)
6393 {
6394         struct ixgbe_filter_info *filter_info =
6395                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6396         struct ixgbe_5tuple_filter_info filter_5tuple;
6397         struct ixgbe_5tuple_filter *filter;
6398         int ret;
6399
6400         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6401                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6402                 return -EINVAL;
6403         }
6404
6405         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6406         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6407         if (ret < 0)
6408                 return ret;
6409
6410         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6411                                          &filter_5tuple);
6412         if (filter == NULL) {
6413                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6414                 return -ENOENT;
6415         }
6416         ntuple_filter->queue = filter->queue;
6417         return 0;
6418 }
6419
6420 /*
6421  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6422  * @dev: pointer to rte_eth_dev structure
6423  * @filter_op:operation will be taken.
6424  * @arg: a pointer to specific structure corresponding to the filter_op
6425  *
6426  * @return
6427  *    - On success, zero.
6428  *    - On failure, a negative value.
6429  */
6430 static int
6431 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6432                                 enum rte_filter_op filter_op,
6433                                 void *arg)
6434 {
6435         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6436         int ret;
6437
6438         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6439
6440         if (filter_op == RTE_ETH_FILTER_NOP)
6441                 return 0;
6442
6443         if (arg == NULL) {
6444                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6445                             filter_op);
6446                 return -EINVAL;
6447         }
6448
6449         switch (filter_op) {
6450         case RTE_ETH_FILTER_ADD:
6451                 ret = ixgbe_add_del_ntuple_filter(dev,
6452                         (struct rte_eth_ntuple_filter *)arg,
6453                         TRUE);
6454                 break;
6455         case RTE_ETH_FILTER_DELETE:
6456                 ret = ixgbe_add_del_ntuple_filter(dev,
6457                         (struct rte_eth_ntuple_filter *)arg,
6458                         FALSE);
6459                 break;
6460         case RTE_ETH_FILTER_GET:
6461                 ret = ixgbe_get_ntuple_filter(dev,
6462                         (struct rte_eth_ntuple_filter *)arg);
6463                 break;
6464         default:
6465                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6466                 ret = -EINVAL;
6467                 break;
6468         }
6469         return ret;
6470 }
6471
6472 int
6473 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6474                         struct rte_eth_ethertype_filter *filter,
6475                         bool add)
6476 {
6477         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6478         struct ixgbe_filter_info *filter_info =
6479                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6480         uint32_t etqf = 0;
6481         uint32_t etqs = 0;
6482         int ret;
6483         struct ixgbe_ethertype_filter ethertype_filter;
6484
6485         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6486                 return -EINVAL;
6487
6488         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6489                 filter->ether_type == ETHER_TYPE_IPv6) {
6490                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6491                         " ethertype filter.", filter->ether_type);
6492                 return -EINVAL;
6493         }
6494
6495         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6496                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6497                 return -EINVAL;
6498         }
6499         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6500                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6501                 return -EINVAL;
6502         }
6503
6504         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6505         if (ret >= 0 && add) {
6506                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6507                             filter->ether_type);
6508                 return -EEXIST;
6509         }
6510         if (ret < 0 && !add) {
6511                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6512                             filter->ether_type);
6513                 return -ENOENT;
6514         }
6515
6516         if (add) {
6517                 etqf = IXGBE_ETQF_FILTER_EN;
6518                 etqf |= (uint32_t)filter->ether_type;
6519                 etqs |= (uint32_t)((filter->queue <<
6520                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6521                                     IXGBE_ETQS_RX_QUEUE);
6522                 etqs |= IXGBE_ETQS_QUEUE_EN;
6523
6524                 ethertype_filter.ethertype = filter->ether_type;
6525                 ethertype_filter.etqf = etqf;
6526                 ethertype_filter.etqs = etqs;
6527                 ethertype_filter.conf = FALSE;
6528                 ret = ixgbe_ethertype_filter_insert(filter_info,
6529                                                     &ethertype_filter);
6530                 if (ret < 0) {
6531                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6532                         return -ENOSPC;
6533                 }
6534         } else {
6535                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6536                 if (ret < 0)
6537                         return -ENOSYS;
6538         }
6539         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6540         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6541         IXGBE_WRITE_FLUSH(hw);
6542
6543         return 0;
6544 }
6545
6546 static int
6547 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6548                         struct rte_eth_ethertype_filter *filter)
6549 {
6550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6551         struct ixgbe_filter_info *filter_info =
6552                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6553         uint32_t etqf, etqs;
6554         int ret;
6555
6556         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6557         if (ret < 0) {
6558                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6559                             filter->ether_type);
6560                 return -ENOENT;
6561         }
6562
6563         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6564         if (etqf & IXGBE_ETQF_FILTER_EN) {
6565                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6566                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6567                 filter->flags = 0;
6568                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6569                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6570                 return 0;
6571         }
6572         return -ENOENT;
6573 }
6574
6575 /*
6576  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6577  * @dev: pointer to rte_eth_dev structure
6578  * @filter_op:operation will be taken.
6579  * @arg: a pointer to specific structure corresponding to the filter_op
6580  */
6581 static int
6582 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6583                                 enum rte_filter_op filter_op,
6584                                 void *arg)
6585 {
6586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6587         int ret;
6588
6589         MAC_TYPE_FILTER_SUP(hw->mac.type);
6590
6591         if (filter_op == RTE_ETH_FILTER_NOP)
6592                 return 0;
6593
6594         if (arg == NULL) {
6595                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6596                             filter_op);
6597                 return -EINVAL;
6598         }
6599
6600         switch (filter_op) {
6601         case RTE_ETH_FILTER_ADD:
6602                 ret = ixgbe_add_del_ethertype_filter(dev,
6603                         (struct rte_eth_ethertype_filter *)arg,
6604                         TRUE);
6605                 break;
6606         case RTE_ETH_FILTER_DELETE:
6607                 ret = ixgbe_add_del_ethertype_filter(dev,
6608                         (struct rte_eth_ethertype_filter *)arg,
6609                         FALSE);
6610                 break;
6611         case RTE_ETH_FILTER_GET:
6612                 ret = ixgbe_get_ethertype_filter(dev,
6613                         (struct rte_eth_ethertype_filter *)arg);
6614                 break;
6615         default:
6616                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6617                 ret = -EINVAL;
6618                 break;
6619         }
6620         return ret;
6621 }
6622
6623 static int
6624 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6625                      enum rte_filter_type filter_type,
6626                      enum rte_filter_op filter_op,
6627                      void *arg)
6628 {
6629         int ret = 0;
6630
6631         switch (filter_type) {
6632         case RTE_ETH_FILTER_NTUPLE:
6633                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6634                 break;
6635         case RTE_ETH_FILTER_ETHERTYPE:
6636                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6637                 break;
6638         case RTE_ETH_FILTER_SYN:
6639                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6640                 break;
6641         case RTE_ETH_FILTER_FDIR:
6642                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6643                 break;
6644         case RTE_ETH_FILTER_L2_TUNNEL:
6645                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6646                 break;
6647         case RTE_ETH_FILTER_GENERIC:
6648                 if (filter_op != RTE_ETH_FILTER_GET)
6649                         return -EINVAL;
6650                 *(const void **)arg = &ixgbe_flow_ops;
6651                 break;
6652         default:
6653                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6654                                                         filter_type);
6655                 ret = -EINVAL;
6656                 break;
6657         }
6658
6659         return ret;
6660 }
6661
6662 static u8 *
6663 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6664                         u8 **mc_addr_ptr, u32 *vmdq)
6665 {
6666         u8 *mc_addr;
6667
6668         *vmdq = 0;
6669         mc_addr = *mc_addr_ptr;
6670         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6671         return mc_addr;
6672 }
6673
6674 static int
6675 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6676                           struct ether_addr *mc_addr_set,
6677                           uint32_t nb_mc_addr)
6678 {
6679         struct ixgbe_hw *hw;
6680         u8 *mc_addr_list;
6681
6682         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6683         mc_addr_list = (u8 *)mc_addr_set;
6684         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6685                                          ixgbe_dev_addr_list_itr, TRUE);
6686 }
6687
6688 static uint64_t
6689 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6690 {
6691         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6692         uint64_t systime_cycles;
6693
6694         switch (hw->mac.type) {
6695         case ixgbe_mac_X550:
6696         case ixgbe_mac_X550EM_x:
6697         case ixgbe_mac_X550EM_a:
6698                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6699                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6700                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6701                                 * NSEC_PER_SEC;
6702                 break;
6703         default:
6704                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6705                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6706                                 << 32;
6707         }
6708
6709         return systime_cycles;
6710 }
6711
6712 static uint64_t
6713 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6714 {
6715         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6716         uint64_t rx_tstamp_cycles;
6717
6718         switch (hw->mac.type) {
6719         case ixgbe_mac_X550:
6720         case ixgbe_mac_X550EM_x:
6721         case ixgbe_mac_X550EM_a:
6722                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6723                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6724                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6725                                 * NSEC_PER_SEC;
6726                 break;
6727         default:
6728                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6729                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6730                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6731                                 << 32;
6732         }
6733
6734         return rx_tstamp_cycles;
6735 }
6736
6737 static uint64_t
6738 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6739 {
6740         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6741         uint64_t tx_tstamp_cycles;
6742
6743         switch (hw->mac.type) {
6744         case ixgbe_mac_X550:
6745         case ixgbe_mac_X550EM_x:
6746         case ixgbe_mac_X550EM_a:
6747                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6748                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6749                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6750                                 * NSEC_PER_SEC;
6751                 break;
6752         default:
6753                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6754                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6755                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6756                                 << 32;
6757         }
6758
6759         return tx_tstamp_cycles;
6760 }
6761
6762 static void
6763 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6764 {
6765         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6766         struct ixgbe_adapter *adapter =
6767                 (struct ixgbe_adapter *)dev->data->dev_private;
6768         struct rte_eth_link link;
6769         uint32_t incval = 0;
6770         uint32_t shift = 0;
6771
6772         /* Get current link speed. */
6773         ixgbe_dev_link_update(dev, 1);
6774         rte_eth_linkstatus_get(dev, &link);
6775
6776         switch (link.link_speed) {
6777         case ETH_SPEED_NUM_100M:
6778                 incval = IXGBE_INCVAL_100;
6779                 shift = IXGBE_INCVAL_SHIFT_100;
6780                 break;
6781         case ETH_SPEED_NUM_1G:
6782                 incval = IXGBE_INCVAL_1GB;
6783                 shift = IXGBE_INCVAL_SHIFT_1GB;
6784                 break;
6785         case ETH_SPEED_NUM_10G:
6786         default:
6787                 incval = IXGBE_INCVAL_10GB;
6788                 shift = IXGBE_INCVAL_SHIFT_10GB;
6789                 break;
6790         }
6791
6792         switch (hw->mac.type) {
6793         case ixgbe_mac_X550:
6794         case ixgbe_mac_X550EM_x:
6795         case ixgbe_mac_X550EM_a:
6796                 /* Independent of link speed. */
6797                 incval = 1;
6798                 /* Cycles read will be interpreted as ns. */
6799                 shift = 0;
6800                 /* Fall-through */
6801         case ixgbe_mac_X540:
6802                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6803                 break;
6804         case ixgbe_mac_82599EB:
6805                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6806                 shift -= IXGBE_INCVAL_SHIFT_82599;
6807                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6808                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6809                 break;
6810         default:
6811                 /* Not supported. */
6812                 return;
6813         }
6814
6815         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6816         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6817         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6818
6819         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6820         adapter->systime_tc.cc_shift = shift;
6821         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6822
6823         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6824         adapter->rx_tstamp_tc.cc_shift = shift;
6825         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6826
6827         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6828         adapter->tx_tstamp_tc.cc_shift = shift;
6829         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6830 }
6831
6832 static int
6833 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6834 {
6835         struct ixgbe_adapter *adapter =
6836                         (struct ixgbe_adapter *)dev->data->dev_private;
6837
6838         adapter->systime_tc.nsec += delta;
6839         adapter->rx_tstamp_tc.nsec += delta;
6840         adapter->tx_tstamp_tc.nsec += delta;
6841
6842         return 0;
6843 }
6844
6845 static int
6846 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6847 {
6848         uint64_t ns;
6849         struct ixgbe_adapter *adapter =
6850                         (struct ixgbe_adapter *)dev->data->dev_private;
6851
6852         ns = rte_timespec_to_ns(ts);
6853         /* Set the timecounters to a new value. */
6854         adapter->systime_tc.nsec = ns;
6855         adapter->rx_tstamp_tc.nsec = ns;
6856         adapter->tx_tstamp_tc.nsec = ns;
6857
6858         return 0;
6859 }
6860
6861 static int
6862 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6863 {
6864         uint64_t ns, systime_cycles;
6865         struct ixgbe_adapter *adapter =
6866                         (struct ixgbe_adapter *)dev->data->dev_private;
6867
6868         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6869         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6870         *ts = rte_ns_to_timespec(ns);
6871
6872         return 0;
6873 }
6874
6875 static int
6876 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6877 {
6878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6879         uint32_t tsync_ctl;
6880         uint32_t tsauxc;
6881
6882         /* Stop the timesync system time. */
6883         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6884         /* Reset the timesync system time value. */
6885         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6886         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6887
6888         /* Enable system time for platforms where it isn't on by default. */
6889         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6890         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6891         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6892
6893         ixgbe_start_timecounters(dev);
6894
6895         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6896         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6897                         (ETHER_TYPE_1588 |
6898                          IXGBE_ETQF_FILTER_EN |
6899                          IXGBE_ETQF_1588));
6900
6901         /* Enable timestamping of received PTP packets. */
6902         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6903         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6904         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6905
6906         /* Enable timestamping of transmitted PTP packets. */
6907         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6908         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6909         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6910
6911         IXGBE_WRITE_FLUSH(hw);
6912
6913         return 0;
6914 }
6915
6916 static int
6917 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6918 {
6919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6920         uint32_t tsync_ctl;
6921
6922         /* Disable timestamping of transmitted PTP packets. */
6923         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6924         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6925         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6926
6927         /* Disable timestamping of received PTP packets. */
6928         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6929         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6930         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6931
6932         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6933         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6934
6935         /* Stop incrementating the System Time registers. */
6936         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6937
6938         return 0;
6939 }
6940
6941 static int
6942 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6943                                  struct timespec *timestamp,
6944                                  uint32_t flags __rte_unused)
6945 {
6946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6947         struct ixgbe_adapter *adapter =
6948                 (struct ixgbe_adapter *)dev->data->dev_private;
6949         uint32_t tsync_rxctl;
6950         uint64_t rx_tstamp_cycles;
6951         uint64_t ns;
6952
6953         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6954         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6955                 return -EINVAL;
6956
6957         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6958         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6959         *timestamp = rte_ns_to_timespec(ns);
6960
6961         return  0;
6962 }
6963
6964 static int
6965 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6966                                  struct timespec *timestamp)
6967 {
6968         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6969         struct ixgbe_adapter *adapter =
6970                 (struct ixgbe_adapter *)dev->data->dev_private;
6971         uint32_t tsync_txctl;
6972         uint64_t tx_tstamp_cycles;
6973         uint64_t ns;
6974
6975         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6976         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6977                 return -EINVAL;
6978
6979         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6980         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6981         *timestamp = rte_ns_to_timespec(ns);
6982
6983         return 0;
6984 }
6985
6986 static int
6987 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6988 {
6989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6990         int count = 0;
6991         int g_ind = 0;
6992         const struct reg_info *reg_group;
6993         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6994                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6995
6996         while ((reg_group = reg_set[g_ind++]))
6997                 count += ixgbe_regs_group_count(reg_group);
6998
6999         return count;
7000 }
7001
7002 static int
7003 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7004 {
7005         int count = 0;
7006         int g_ind = 0;
7007         const struct reg_info *reg_group;
7008
7009         while ((reg_group = ixgbevf_regs[g_ind++]))
7010                 count += ixgbe_regs_group_count(reg_group);
7011
7012         return count;
7013 }
7014
7015 static int
7016 ixgbe_get_regs(struct rte_eth_dev *dev,
7017               struct rte_dev_reg_info *regs)
7018 {
7019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7020         uint32_t *data = regs->data;
7021         int g_ind = 0;
7022         int count = 0;
7023         const struct reg_info *reg_group;
7024         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7025                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7026
7027         if (data == NULL) {
7028                 regs->length = ixgbe_get_reg_length(dev);
7029                 regs->width = sizeof(uint32_t);
7030                 return 0;
7031         }
7032
7033         /* Support only full register dump */
7034         if ((regs->length == 0) ||
7035             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7036                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7037                         hw->device_id;
7038                 while ((reg_group = reg_set[g_ind++]))
7039                         count += ixgbe_read_regs_group(dev, &data[count],
7040                                 reg_group);
7041                 return 0;
7042         }
7043
7044         return -ENOTSUP;
7045 }
7046
7047 static int
7048 ixgbevf_get_regs(struct rte_eth_dev *dev,
7049                 struct rte_dev_reg_info *regs)
7050 {
7051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7052         uint32_t *data = regs->data;
7053         int g_ind = 0;
7054         int count = 0;
7055         const struct reg_info *reg_group;
7056
7057         if (data == NULL) {
7058                 regs->length = ixgbevf_get_reg_length(dev);
7059                 regs->width = sizeof(uint32_t);
7060                 return 0;
7061         }
7062
7063         /* Support only full register dump */
7064         if ((regs->length == 0) ||
7065             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7066                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7067                         hw->device_id;
7068                 while ((reg_group = ixgbevf_regs[g_ind++]))
7069                         count += ixgbe_read_regs_group(dev, &data[count],
7070                                                       reg_group);
7071                 return 0;
7072         }
7073
7074         return -ENOTSUP;
7075 }
7076
7077 static int
7078 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7079 {
7080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7081
7082         /* Return unit is byte count */
7083         return hw->eeprom.word_size * 2;
7084 }
7085
7086 static int
7087 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7088                 struct rte_dev_eeprom_info *in_eeprom)
7089 {
7090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7091         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7092         uint16_t *data = in_eeprom->data;
7093         int first, length;
7094
7095         first = in_eeprom->offset >> 1;
7096         length = in_eeprom->length >> 1;
7097         if ((first > hw->eeprom.word_size) ||
7098             ((first + length) > hw->eeprom.word_size))
7099                 return -EINVAL;
7100
7101         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7102
7103         return eeprom->ops.read_buffer(hw, first, length, data);
7104 }
7105
7106 static int
7107 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7108                 struct rte_dev_eeprom_info *in_eeprom)
7109 {
7110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7111         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7112         uint16_t *data = in_eeprom->data;
7113         int first, length;
7114
7115         first = in_eeprom->offset >> 1;
7116         length = in_eeprom->length >> 1;
7117         if ((first > hw->eeprom.word_size) ||
7118             ((first + length) > hw->eeprom.word_size))
7119                 return -EINVAL;
7120
7121         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7122
7123         return eeprom->ops.write_buffer(hw,  first, length, data);
7124 }
7125
7126 uint16_t
7127 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7128         switch (mac_type) {
7129         case ixgbe_mac_X550:
7130         case ixgbe_mac_X550EM_x:
7131         case ixgbe_mac_X550EM_a:
7132                 return ETH_RSS_RETA_SIZE_512;
7133         case ixgbe_mac_X550_vf:
7134         case ixgbe_mac_X550EM_x_vf:
7135         case ixgbe_mac_X550EM_a_vf:
7136                 return ETH_RSS_RETA_SIZE_64;
7137         default:
7138                 return ETH_RSS_RETA_SIZE_128;
7139         }
7140 }
7141
7142 uint32_t
7143 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7144         switch (mac_type) {
7145         case ixgbe_mac_X550:
7146         case ixgbe_mac_X550EM_x:
7147         case ixgbe_mac_X550EM_a:
7148                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7149                         return IXGBE_RETA(reta_idx >> 2);
7150                 else
7151                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7152         case ixgbe_mac_X550_vf:
7153         case ixgbe_mac_X550EM_x_vf:
7154         case ixgbe_mac_X550EM_a_vf:
7155                 return IXGBE_VFRETA(reta_idx >> 2);
7156         default:
7157                 return IXGBE_RETA(reta_idx >> 2);
7158         }
7159 }
7160
7161 uint32_t
7162 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7163         switch (mac_type) {
7164         case ixgbe_mac_X550_vf:
7165         case ixgbe_mac_X550EM_x_vf:
7166         case ixgbe_mac_X550EM_a_vf:
7167                 return IXGBE_VFMRQC;
7168         default:
7169                 return IXGBE_MRQC;
7170         }
7171 }
7172
7173 uint32_t
7174 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7175         switch (mac_type) {
7176         case ixgbe_mac_X550_vf:
7177         case ixgbe_mac_X550EM_x_vf:
7178         case ixgbe_mac_X550EM_a_vf:
7179                 return IXGBE_VFRSSRK(i);
7180         default:
7181                 return IXGBE_RSSRK(i);
7182         }
7183 }
7184
7185 bool
7186 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7187         switch (mac_type) {
7188         case ixgbe_mac_82599_vf:
7189         case ixgbe_mac_X540_vf:
7190                 return 0;
7191         default:
7192                 return 1;
7193         }
7194 }
7195
7196 static int
7197 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7198                         struct rte_eth_dcb_info *dcb_info)
7199 {
7200         struct ixgbe_dcb_config *dcb_config =
7201                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7202         struct ixgbe_dcb_tc_config *tc;
7203         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7204         uint8_t nb_tcs;
7205         uint8_t i, j;
7206
7207         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7208                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7209         else
7210                 dcb_info->nb_tcs = 1;
7211
7212         tc_queue = &dcb_info->tc_queue;
7213         nb_tcs = dcb_info->nb_tcs;
7214
7215         if (dcb_config->vt_mode) { /* vt is enabled*/
7216                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7217                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7218                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7219                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7220                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7221                         for (j = 0; j < nb_tcs; j++) {
7222                                 tc_queue->tc_rxq[0][j].base = j;
7223                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7224                                 tc_queue->tc_txq[0][j].base = j;
7225                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7226                         }
7227                 } else {
7228                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7229                                 for (j = 0; j < nb_tcs; j++) {
7230                                         tc_queue->tc_rxq[i][j].base =
7231                                                 i * nb_tcs + j;
7232                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7233                                         tc_queue->tc_txq[i][j].base =
7234                                                 i * nb_tcs + j;
7235                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7236                                 }
7237                         }
7238                 }
7239         } else { /* vt is disabled*/
7240                 struct rte_eth_dcb_rx_conf *rx_conf =
7241                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7242                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7243                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7244                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7245                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7246                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7247                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7248                         }
7249                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7250                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7251                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7252                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7253                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7254                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7255                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7256                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7257                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7258                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7259                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7260                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7261                         }
7262                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7263                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7264                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7265                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7266                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7267                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7268                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7269                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7270                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7271                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7272                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7273                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7274                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7275                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7276                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7277                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7278                 }
7279         }
7280         for (i = 0; i < dcb_info->nb_tcs; i++) {
7281                 tc = &dcb_config->tc_config[i];
7282                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7283         }
7284         return 0;
7285 }
7286
7287 /* Update e-tag ether type */
7288 static int
7289 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7290                             uint16_t ether_type)
7291 {
7292         uint32_t etag_etype;
7293
7294         if (hw->mac.type != ixgbe_mac_X550 &&
7295             hw->mac.type != ixgbe_mac_X550EM_x &&
7296             hw->mac.type != ixgbe_mac_X550EM_a) {
7297                 return -ENOTSUP;
7298         }
7299
7300         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7301         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7302         etag_etype |= ether_type;
7303         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7304         IXGBE_WRITE_FLUSH(hw);
7305
7306         return 0;
7307 }
7308
7309 /* Config l2 tunnel ether type */
7310 static int
7311 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7312                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7313 {
7314         int ret = 0;
7315         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7316         struct ixgbe_l2_tn_info *l2_tn_info =
7317                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7318
7319         if (l2_tunnel == NULL)
7320                 return -EINVAL;
7321
7322         switch (l2_tunnel->l2_tunnel_type) {
7323         case RTE_L2_TUNNEL_TYPE_E_TAG:
7324                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7325                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7326                 break;
7327         default:
7328                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7329                 ret = -EINVAL;
7330                 break;
7331         }
7332
7333         return ret;
7334 }
7335
7336 /* Enable e-tag tunnel */
7337 static int
7338 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7339 {
7340         uint32_t etag_etype;
7341
7342         if (hw->mac.type != ixgbe_mac_X550 &&
7343             hw->mac.type != ixgbe_mac_X550EM_x &&
7344             hw->mac.type != ixgbe_mac_X550EM_a) {
7345                 return -ENOTSUP;
7346         }
7347
7348         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7349         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7350         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7351         IXGBE_WRITE_FLUSH(hw);
7352
7353         return 0;
7354 }
7355
7356 /* Enable l2 tunnel */
7357 static int
7358 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7359                            enum rte_eth_tunnel_type l2_tunnel_type)
7360 {
7361         int ret = 0;
7362         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7363         struct ixgbe_l2_tn_info *l2_tn_info =
7364                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7365
7366         switch (l2_tunnel_type) {
7367         case RTE_L2_TUNNEL_TYPE_E_TAG:
7368                 l2_tn_info->e_tag_en = TRUE;
7369                 ret = ixgbe_e_tag_enable(hw);
7370                 break;
7371         default:
7372                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7373                 ret = -EINVAL;
7374                 break;
7375         }
7376
7377         return ret;
7378 }
7379
7380 /* Disable e-tag tunnel */
7381 static int
7382 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7383 {
7384         uint32_t etag_etype;
7385
7386         if (hw->mac.type != ixgbe_mac_X550 &&
7387             hw->mac.type != ixgbe_mac_X550EM_x &&
7388             hw->mac.type != ixgbe_mac_X550EM_a) {
7389                 return -ENOTSUP;
7390         }
7391
7392         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7393         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7394         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7395         IXGBE_WRITE_FLUSH(hw);
7396
7397         return 0;
7398 }
7399
7400 /* Disable l2 tunnel */
7401 static int
7402 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7403                             enum rte_eth_tunnel_type l2_tunnel_type)
7404 {
7405         int ret = 0;
7406         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7407         struct ixgbe_l2_tn_info *l2_tn_info =
7408                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7409
7410         switch (l2_tunnel_type) {
7411         case RTE_L2_TUNNEL_TYPE_E_TAG:
7412                 l2_tn_info->e_tag_en = FALSE;
7413                 ret = ixgbe_e_tag_disable(hw);
7414                 break;
7415         default:
7416                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7417                 ret = -EINVAL;
7418                 break;
7419         }
7420
7421         return ret;
7422 }
7423
7424 static int
7425 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7426                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7427 {
7428         int ret = 0;
7429         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7430         uint32_t i, rar_entries;
7431         uint32_t rar_low, rar_high;
7432
7433         if (hw->mac.type != ixgbe_mac_X550 &&
7434             hw->mac.type != ixgbe_mac_X550EM_x &&
7435             hw->mac.type != ixgbe_mac_X550EM_a) {
7436                 return -ENOTSUP;
7437         }
7438
7439         rar_entries = ixgbe_get_num_rx_addrs(hw);
7440
7441         for (i = 1; i < rar_entries; i++) {
7442                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7443                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7444                 if ((rar_high & IXGBE_RAH_AV) &&
7445                     (rar_high & IXGBE_RAH_ADTYPE) &&
7446                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7447                      l2_tunnel->tunnel_id)) {
7448                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7449                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7450
7451                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7452
7453                         return ret;
7454                 }
7455         }
7456
7457         return ret;
7458 }
7459
7460 static int
7461 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7462                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7463 {
7464         int ret = 0;
7465         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7466         uint32_t i, rar_entries;
7467         uint32_t rar_low, rar_high;
7468
7469         if (hw->mac.type != ixgbe_mac_X550 &&
7470             hw->mac.type != ixgbe_mac_X550EM_x &&
7471             hw->mac.type != ixgbe_mac_X550EM_a) {
7472                 return -ENOTSUP;
7473         }
7474
7475         /* One entry for one tunnel. Try to remove potential existing entry. */
7476         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7477
7478         rar_entries = ixgbe_get_num_rx_addrs(hw);
7479
7480         for (i = 1; i < rar_entries; i++) {
7481                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7482                 if (rar_high & IXGBE_RAH_AV) {
7483                         continue;
7484                 } else {
7485                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7486                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7487                         rar_low = l2_tunnel->tunnel_id;
7488
7489                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7490                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7491
7492                         return ret;
7493                 }
7494         }
7495
7496         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7497                      " Please remove a rule before adding a new one.");
7498         return -EINVAL;
7499 }
7500
7501 static inline struct ixgbe_l2_tn_filter *
7502 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7503                           struct ixgbe_l2_tn_key *key)
7504 {
7505         int ret;
7506
7507         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7508         if (ret < 0)
7509                 return NULL;
7510
7511         return l2_tn_info->hash_map[ret];
7512 }
7513
7514 static inline int
7515 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7516                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7517 {
7518         int ret;
7519
7520         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7521                                &l2_tn_filter->key);
7522
7523         if (ret < 0) {
7524                 PMD_DRV_LOG(ERR,
7525                             "Failed to insert L2 tunnel filter"
7526                             " to hash table %d!",
7527                             ret);
7528                 return ret;
7529         }
7530
7531         l2_tn_info->hash_map[ret] = l2_tn_filter;
7532
7533         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7534
7535         return 0;
7536 }
7537
7538 static inline int
7539 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7540                           struct ixgbe_l2_tn_key *key)
7541 {
7542         int ret;
7543         struct ixgbe_l2_tn_filter *l2_tn_filter;
7544
7545         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7546
7547         if (ret < 0) {
7548                 PMD_DRV_LOG(ERR,
7549                             "No such L2 tunnel filter to delete %d!",
7550                             ret);
7551                 return ret;
7552         }
7553
7554         l2_tn_filter = l2_tn_info->hash_map[ret];
7555         l2_tn_info->hash_map[ret] = NULL;
7556
7557         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7558         rte_free(l2_tn_filter);
7559
7560         return 0;
7561 }
7562
7563 /* Add l2 tunnel filter */
7564 int
7565 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7566                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7567                                bool restore)
7568 {
7569         int ret;
7570         struct ixgbe_l2_tn_info *l2_tn_info =
7571                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7572         struct ixgbe_l2_tn_key key;
7573         struct ixgbe_l2_tn_filter *node;
7574
7575         if (!restore) {
7576                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7577                 key.tn_id = l2_tunnel->tunnel_id;
7578
7579                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7580
7581                 if (node) {
7582                         PMD_DRV_LOG(ERR,
7583                                     "The L2 tunnel filter already exists!");
7584                         return -EINVAL;
7585                 }
7586
7587                 node = rte_zmalloc("ixgbe_l2_tn",
7588                                    sizeof(struct ixgbe_l2_tn_filter),
7589                                    0);
7590                 if (!node)
7591                         return -ENOMEM;
7592
7593                 rte_memcpy(&node->key,
7594                                  &key,
7595                                  sizeof(struct ixgbe_l2_tn_key));
7596                 node->pool = l2_tunnel->pool;
7597                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7598                 if (ret < 0) {
7599                         rte_free(node);
7600                         return ret;
7601                 }
7602         }
7603
7604         switch (l2_tunnel->l2_tunnel_type) {
7605         case RTE_L2_TUNNEL_TYPE_E_TAG:
7606                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7607                 break;
7608         default:
7609                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7610                 ret = -EINVAL;
7611                 break;
7612         }
7613
7614         if ((!restore) && (ret < 0))
7615                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7616
7617         return ret;
7618 }
7619
7620 /* Delete l2 tunnel filter */
7621 int
7622 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7623                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7624 {
7625         int ret;
7626         struct ixgbe_l2_tn_info *l2_tn_info =
7627                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7628         struct ixgbe_l2_tn_key key;
7629
7630         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7631         key.tn_id = l2_tunnel->tunnel_id;
7632         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7633         if (ret < 0)
7634                 return ret;
7635
7636         switch (l2_tunnel->l2_tunnel_type) {
7637         case RTE_L2_TUNNEL_TYPE_E_TAG:
7638                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7639                 break;
7640         default:
7641                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7642                 ret = -EINVAL;
7643                 break;
7644         }
7645
7646         return ret;
7647 }
7648
7649 /**
7650  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7651  * @dev: pointer to rte_eth_dev structure
7652  * @filter_op:operation will be taken.
7653  * @arg: a pointer to specific structure corresponding to the filter_op
7654  */
7655 static int
7656 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7657                                   enum rte_filter_op filter_op,
7658                                   void *arg)
7659 {
7660         int ret;
7661
7662         if (filter_op == RTE_ETH_FILTER_NOP)
7663                 return 0;
7664
7665         if (arg == NULL) {
7666                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7667                             filter_op);
7668                 return -EINVAL;
7669         }
7670
7671         switch (filter_op) {
7672         case RTE_ETH_FILTER_ADD:
7673                 ret = ixgbe_dev_l2_tunnel_filter_add
7674                         (dev,
7675                          (struct rte_eth_l2_tunnel_conf *)arg,
7676                          FALSE);
7677                 break;
7678         case RTE_ETH_FILTER_DELETE:
7679                 ret = ixgbe_dev_l2_tunnel_filter_del
7680                         (dev,
7681                          (struct rte_eth_l2_tunnel_conf *)arg);
7682                 break;
7683         default:
7684                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7685                 ret = -EINVAL;
7686                 break;
7687         }
7688         return ret;
7689 }
7690
7691 static int
7692 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7693 {
7694         int ret = 0;
7695         uint32_t ctrl;
7696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7697
7698         if (hw->mac.type != ixgbe_mac_X550 &&
7699             hw->mac.type != ixgbe_mac_X550EM_x &&
7700             hw->mac.type != ixgbe_mac_X550EM_a) {
7701                 return -ENOTSUP;
7702         }
7703
7704         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7705         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7706         if (en)
7707                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7708         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7709
7710         return ret;
7711 }
7712
7713 /* Enable l2 tunnel forwarding */
7714 static int
7715 ixgbe_dev_l2_tunnel_forwarding_enable
7716         (struct rte_eth_dev *dev,
7717          enum rte_eth_tunnel_type l2_tunnel_type)
7718 {
7719         struct ixgbe_l2_tn_info *l2_tn_info =
7720                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7721         int ret = 0;
7722
7723         switch (l2_tunnel_type) {
7724         case RTE_L2_TUNNEL_TYPE_E_TAG:
7725                 l2_tn_info->e_tag_fwd_en = TRUE;
7726                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7727                 break;
7728         default:
7729                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7730                 ret = -EINVAL;
7731                 break;
7732         }
7733
7734         return ret;
7735 }
7736
7737 /* Disable l2 tunnel forwarding */
7738 static int
7739 ixgbe_dev_l2_tunnel_forwarding_disable
7740         (struct rte_eth_dev *dev,
7741          enum rte_eth_tunnel_type l2_tunnel_type)
7742 {
7743         struct ixgbe_l2_tn_info *l2_tn_info =
7744                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7745         int ret = 0;
7746
7747         switch (l2_tunnel_type) {
7748         case RTE_L2_TUNNEL_TYPE_E_TAG:
7749                 l2_tn_info->e_tag_fwd_en = FALSE;
7750                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7751                 break;
7752         default:
7753                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7754                 ret = -EINVAL;
7755                 break;
7756         }
7757
7758         return ret;
7759 }
7760
7761 static int
7762 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7763                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7764                              bool en)
7765 {
7766         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7767         int ret = 0;
7768         uint32_t vmtir, vmvir;
7769         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7770
7771         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7772                 PMD_DRV_LOG(ERR,
7773                             "VF id %u should be less than %u",
7774                             l2_tunnel->vf_id,
7775                             pci_dev->max_vfs);
7776                 return -EINVAL;
7777         }
7778
7779         if (hw->mac.type != ixgbe_mac_X550 &&
7780             hw->mac.type != ixgbe_mac_X550EM_x &&
7781             hw->mac.type != ixgbe_mac_X550EM_a) {
7782                 return -ENOTSUP;
7783         }
7784
7785         if (en)
7786                 vmtir = l2_tunnel->tunnel_id;
7787         else
7788                 vmtir = 0;
7789
7790         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7791
7792         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7793         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7794         if (en)
7795                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7796         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7797
7798         return ret;
7799 }
7800
7801 /* Enable l2 tunnel tag insertion */
7802 static int
7803 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7804                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7805 {
7806         int ret = 0;
7807
7808         switch (l2_tunnel->l2_tunnel_type) {
7809         case RTE_L2_TUNNEL_TYPE_E_TAG:
7810                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7811                 break;
7812         default:
7813                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7814                 ret = -EINVAL;
7815                 break;
7816         }
7817
7818         return ret;
7819 }
7820
7821 /* Disable l2 tunnel tag insertion */
7822 static int
7823 ixgbe_dev_l2_tunnel_insertion_disable
7824         (struct rte_eth_dev *dev,
7825          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7826 {
7827         int ret = 0;
7828
7829         switch (l2_tunnel->l2_tunnel_type) {
7830         case RTE_L2_TUNNEL_TYPE_E_TAG:
7831                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7832                 break;
7833         default:
7834                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7835                 ret = -EINVAL;
7836                 break;
7837         }
7838
7839         return ret;
7840 }
7841
7842 static int
7843 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7844                              bool en)
7845 {
7846         int ret = 0;
7847         uint32_t qde;
7848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7849
7850         if (hw->mac.type != ixgbe_mac_X550 &&
7851             hw->mac.type != ixgbe_mac_X550EM_x &&
7852             hw->mac.type != ixgbe_mac_X550EM_a) {
7853                 return -ENOTSUP;
7854         }
7855
7856         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7857         if (en)
7858                 qde |= IXGBE_QDE_STRIP_TAG;
7859         else
7860                 qde &= ~IXGBE_QDE_STRIP_TAG;
7861         qde &= ~IXGBE_QDE_READ;
7862         qde |= IXGBE_QDE_WRITE;
7863         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7864
7865         return ret;
7866 }
7867
7868 /* Enable l2 tunnel tag stripping */
7869 static int
7870 ixgbe_dev_l2_tunnel_stripping_enable
7871         (struct rte_eth_dev *dev,
7872          enum rte_eth_tunnel_type l2_tunnel_type)
7873 {
7874         int ret = 0;
7875
7876         switch (l2_tunnel_type) {
7877         case RTE_L2_TUNNEL_TYPE_E_TAG:
7878                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7879                 break;
7880         default:
7881                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7882                 ret = -EINVAL;
7883                 break;
7884         }
7885
7886         return ret;
7887 }
7888
7889 /* Disable l2 tunnel tag stripping */
7890 static int
7891 ixgbe_dev_l2_tunnel_stripping_disable
7892         (struct rte_eth_dev *dev,
7893          enum rte_eth_tunnel_type l2_tunnel_type)
7894 {
7895         int ret = 0;
7896
7897         switch (l2_tunnel_type) {
7898         case RTE_L2_TUNNEL_TYPE_E_TAG:
7899                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7900                 break;
7901         default:
7902                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7903                 ret = -EINVAL;
7904                 break;
7905         }
7906
7907         return ret;
7908 }
7909
7910 /* Enable/disable l2 tunnel offload functions */
7911 static int
7912 ixgbe_dev_l2_tunnel_offload_set
7913         (struct rte_eth_dev *dev,
7914          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7915          uint32_t mask,
7916          uint8_t en)
7917 {
7918         int ret = 0;
7919
7920         if (l2_tunnel == NULL)
7921                 return -EINVAL;
7922
7923         ret = -EINVAL;
7924         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7925                 if (en)
7926                         ret = ixgbe_dev_l2_tunnel_enable(
7927                                 dev,
7928                                 l2_tunnel->l2_tunnel_type);
7929                 else
7930                         ret = ixgbe_dev_l2_tunnel_disable(
7931                                 dev,
7932                                 l2_tunnel->l2_tunnel_type);
7933         }
7934
7935         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7936                 if (en)
7937                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7938                                 dev,
7939                                 l2_tunnel);
7940                 else
7941                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7942                                 dev,
7943                                 l2_tunnel);
7944         }
7945
7946         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7947                 if (en)
7948                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7949                                 dev,
7950                                 l2_tunnel->l2_tunnel_type);
7951                 else
7952                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7953                                 dev,
7954                                 l2_tunnel->l2_tunnel_type);
7955         }
7956
7957         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7958                 if (en)
7959                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7960                                 dev,
7961                                 l2_tunnel->l2_tunnel_type);
7962                 else
7963                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7964                                 dev,
7965                                 l2_tunnel->l2_tunnel_type);
7966         }
7967
7968         return ret;
7969 }
7970
7971 static int
7972 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7973                         uint16_t port)
7974 {
7975         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7976         IXGBE_WRITE_FLUSH(hw);
7977
7978         return 0;
7979 }
7980
7981 /* There's only one register for VxLAN UDP port.
7982  * So, we cannot add several ports. Will update it.
7983  */
7984 static int
7985 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7986                      uint16_t port)
7987 {
7988         if (port == 0) {
7989                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7990                 return -EINVAL;
7991         }
7992
7993         return ixgbe_update_vxlan_port(hw, port);
7994 }
7995
7996 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7997  * UDP port, it must have a value.
7998  * So, will reset it to the original value 0.
7999  */
8000 static int
8001 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8002                      uint16_t port)
8003 {
8004         uint16_t cur_port;
8005
8006         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8007
8008         if (cur_port != port) {
8009                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8010                 return -EINVAL;
8011         }
8012
8013         return ixgbe_update_vxlan_port(hw, 0);
8014 }
8015
8016 /* Add UDP tunneling port */
8017 static int
8018 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8019                               struct rte_eth_udp_tunnel *udp_tunnel)
8020 {
8021         int ret = 0;
8022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8023
8024         if (hw->mac.type != ixgbe_mac_X550 &&
8025             hw->mac.type != ixgbe_mac_X550EM_x &&
8026             hw->mac.type != ixgbe_mac_X550EM_a) {
8027                 return -ENOTSUP;
8028         }
8029
8030         if (udp_tunnel == NULL)
8031                 return -EINVAL;
8032
8033         switch (udp_tunnel->prot_type) {
8034         case RTE_TUNNEL_TYPE_VXLAN:
8035                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8036                 break;
8037
8038         case RTE_TUNNEL_TYPE_GENEVE:
8039         case RTE_TUNNEL_TYPE_TEREDO:
8040                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8041                 ret = -EINVAL;
8042                 break;
8043
8044         default:
8045                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8046                 ret = -EINVAL;
8047                 break;
8048         }
8049
8050         return ret;
8051 }
8052
8053 /* Remove UDP tunneling port */
8054 static int
8055 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8056                               struct rte_eth_udp_tunnel *udp_tunnel)
8057 {
8058         int ret = 0;
8059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8060
8061         if (hw->mac.type != ixgbe_mac_X550 &&
8062             hw->mac.type != ixgbe_mac_X550EM_x &&
8063             hw->mac.type != ixgbe_mac_X550EM_a) {
8064                 return -ENOTSUP;
8065         }
8066
8067         if (udp_tunnel == NULL)
8068                 return -EINVAL;
8069
8070         switch (udp_tunnel->prot_type) {
8071         case RTE_TUNNEL_TYPE_VXLAN:
8072                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8073                 break;
8074         case RTE_TUNNEL_TYPE_GENEVE:
8075         case RTE_TUNNEL_TYPE_TEREDO:
8076                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8077                 ret = -EINVAL;
8078                 break;
8079         default:
8080                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8081                 ret = -EINVAL;
8082                 break;
8083         }
8084
8085         return ret;
8086 }
8087
8088 static void
8089 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8090 {
8091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8092
8093         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8094 }
8095
8096 static void
8097 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8098 {
8099         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8100
8101         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8102 }
8103
8104 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8105 {
8106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8107         u32 in_msg = 0;
8108
8109         /* peek the message first */
8110         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8111
8112         /* PF reset VF event */
8113         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8114                 /* dummy mbx read to ack pf */
8115                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8116                         return;
8117                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8118                                               NULL);
8119         }
8120 }
8121
8122 static int
8123 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8124 {
8125         uint32_t eicr;
8126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8127         struct ixgbe_interrupt *intr =
8128                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8129         ixgbevf_intr_disable(hw);
8130
8131         /* read-on-clear nic registers here */
8132         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8133         intr->flags = 0;
8134
8135         /* only one misc vector supported - mailbox */
8136         eicr &= IXGBE_VTEICR_MASK;
8137         if (eicr == IXGBE_MISC_VEC_ID)
8138                 intr->flags |= IXGBE_FLAG_MAILBOX;
8139
8140         return 0;
8141 }
8142
8143 static int
8144 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8145 {
8146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8147         struct ixgbe_interrupt *intr =
8148                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8149
8150         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8151                 ixgbevf_mbx_process(dev);
8152                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8153         }
8154
8155         ixgbevf_intr_enable(hw);
8156
8157         return 0;
8158 }
8159
8160 static void
8161 ixgbevf_dev_interrupt_handler(void *param)
8162 {
8163         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8164
8165         ixgbevf_dev_interrupt_get_status(dev);
8166         ixgbevf_dev_interrupt_action(dev);
8167 }
8168
8169 /**
8170  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8171  *  @hw: pointer to hardware structure
8172  *
8173  *  Stops the transmit data path and waits for the HW to internally empty
8174  *  the Tx security block
8175  **/
8176 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8177 {
8178 #define IXGBE_MAX_SECTX_POLL 40
8179
8180         int i;
8181         int sectxreg;
8182
8183         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8184         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8185         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8186         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8187                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8188                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8189                         break;
8190                 /* Use interrupt-safe sleep just in case */
8191                 usec_delay(1000);
8192         }
8193
8194         /* For informational purposes only */
8195         if (i >= IXGBE_MAX_SECTX_POLL)
8196                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8197                          "path fully disabled.  Continuing with init.");
8198
8199         return IXGBE_SUCCESS;
8200 }
8201
8202 /**
8203  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8204  *  @hw: pointer to hardware structure
8205  *
8206  *  Enables the transmit data path.
8207  **/
8208 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8209 {
8210         uint32_t sectxreg;
8211
8212         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8213         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8214         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8215         IXGBE_WRITE_FLUSH(hw);
8216
8217         return IXGBE_SUCCESS;
8218 }
8219
8220 /* restore n-tuple filter */
8221 static inline void
8222 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8223 {
8224         struct ixgbe_filter_info *filter_info =
8225                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8226         struct ixgbe_5tuple_filter *node;
8227
8228         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8229                 ixgbe_inject_5tuple_filter(dev, node);
8230         }
8231 }
8232
8233 /* restore ethernet type filter */
8234 static inline void
8235 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8236 {
8237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8238         struct ixgbe_filter_info *filter_info =
8239                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8240         int i;
8241
8242         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8243                 if (filter_info->ethertype_mask & (1 << i)) {
8244                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8245                                         filter_info->ethertype_filters[i].etqf);
8246                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8247                                         filter_info->ethertype_filters[i].etqs);
8248                         IXGBE_WRITE_FLUSH(hw);
8249                 }
8250         }
8251 }
8252
8253 /* restore SYN filter */
8254 static inline void
8255 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8256 {
8257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8258         struct ixgbe_filter_info *filter_info =
8259                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8260         uint32_t synqf;
8261
8262         synqf = filter_info->syn_info;
8263
8264         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8265                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8266                 IXGBE_WRITE_FLUSH(hw);
8267         }
8268 }
8269
8270 /* restore L2 tunnel filter */
8271 static inline void
8272 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8273 {
8274         struct ixgbe_l2_tn_info *l2_tn_info =
8275                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8276         struct ixgbe_l2_tn_filter *node;
8277         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8278
8279         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8280                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8281                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8282                 l2_tn_conf.pool           = node->pool;
8283                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8284         }
8285 }
8286
8287 /* restore rss filter */
8288 static inline void
8289 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8290 {
8291         struct ixgbe_filter_info *filter_info =
8292                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8293
8294         if (filter_info->rss_info.num)
8295                 ixgbe_config_rss_filter(dev,
8296                         &filter_info->rss_info, TRUE);
8297 }
8298
8299 static int
8300 ixgbe_filter_restore(struct rte_eth_dev *dev)
8301 {
8302         ixgbe_ntuple_filter_restore(dev);
8303         ixgbe_ethertype_filter_restore(dev);
8304         ixgbe_syn_filter_restore(dev);
8305         ixgbe_fdir_filter_restore(dev);
8306         ixgbe_l2_tn_filter_restore(dev);
8307         ixgbe_rss_filter_restore(dev);
8308
8309         return 0;
8310 }
8311
8312 static void
8313 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8314 {
8315         struct ixgbe_l2_tn_info *l2_tn_info =
8316                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8317         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8318
8319         if (l2_tn_info->e_tag_en)
8320                 (void)ixgbe_e_tag_enable(hw);
8321
8322         if (l2_tn_info->e_tag_fwd_en)
8323                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8324
8325         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8326 }
8327
8328 /* remove all the n-tuple filters */
8329 void
8330 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8331 {
8332         struct ixgbe_filter_info *filter_info =
8333                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8334         struct ixgbe_5tuple_filter *p_5tuple;
8335
8336         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8337                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8338 }
8339
8340 /* remove all the ether type filters */
8341 void
8342 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8343 {
8344         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8345         struct ixgbe_filter_info *filter_info =
8346                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8347         int i;
8348
8349         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8350                 if (filter_info->ethertype_mask & (1 << i) &&
8351                     !filter_info->ethertype_filters[i].conf) {
8352                         (void)ixgbe_ethertype_filter_remove(filter_info,
8353                                                             (uint8_t)i);
8354                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8355                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8356                         IXGBE_WRITE_FLUSH(hw);
8357                 }
8358         }
8359 }
8360
8361 /* remove the SYN filter */
8362 void
8363 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8364 {
8365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8366         struct ixgbe_filter_info *filter_info =
8367                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8368
8369         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8370                 filter_info->syn_info = 0;
8371
8372                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8373                 IXGBE_WRITE_FLUSH(hw);
8374         }
8375 }
8376
8377 /* remove all the L2 tunnel filters */
8378 int
8379 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8380 {
8381         struct ixgbe_l2_tn_info *l2_tn_info =
8382                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8383         struct ixgbe_l2_tn_filter *l2_tn_filter;
8384         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8385         int ret = 0;
8386
8387         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8388                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8389                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8390                 l2_tn_conf.pool           = l2_tn_filter->pool;
8391                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8392                 if (ret < 0)
8393                         return ret;
8394         }
8395
8396         return 0;
8397 }
8398
8399 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8400 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8401 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8402 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8403 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8404 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8405
8406 RTE_INIT(ixgbe_init_log);
8407 static void
8408 ixgbe_init_log(void)
8409 {
8410         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8411         if (ixgbe_logtype_init >= 0)
8412                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8413         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8414         if (ixgbe_logtype_driver >= 0)
8415                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8416 }