drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Timer value included in XOFF frames. */
  63 #define IXGBE_FC_PAUSE 0x680
  64
  65 /*Default value of Max Rx Queue*/
  66 #define IXGBE_MAX_RX_QUEUE_NUM 128
  67
  68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  71
  72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  75
  76 /*
  77  *  Default values for RX/TX configuration
  78  */
  79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  80 #define IXGBE_DEFAULT_RX_PTHRESH      8
  81 #define IXGBE_DEFAULT_RX_HTHRESH      8
  82 #define IXGBE_DEFAULT_RX_WTHRESH      0
  83
  84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  85 #define IXGBE_DEFAULT_TX_PTHRESH      32
  86 #define IXGBE_DEFAULT_TX_HTHRESH      0
  87 #define IXGBE_DEFAULT_TX_WTHRESH      0
  88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  89
  90 /* Bit shift and mask */
  91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  94 #define IXGBE_8_BIT_MASK   UINT8_MAX
  95
  96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  97
  98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  99
 100 /* Additional timesync values. */
 101 #define NSEC_PER_SEC             1000000000L
 102 #define IXGBE_INCVAL_10GB        0x66666666
 103 #define IXGBE_INCVAL_1GB         0x40000000
 104 #define IXGBE_INCVAL_100         0x50000000
 105 #define IXGBE_INCVAL_SHIFT_10GB  28
 106 #define IXGBE_INCVAL_SHIFT_1GB   24
 107 #define IXGBE_INCVAL_SHIFT_100   21
 108 #define IXGBE_INCVAL_SHIFT_82599 7
 109 #define IXGBE_INCPER_SHIFT_82599 24
 110
 111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 115 #define IXGBE_ETAG_ETYPE                       0x00005084
 116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 118 #define IXGBE_RAH_ADTYPE                       0x40000000
 119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 124 #define IXGBE_VTEICR_MASK                      0x07
 125
 126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 128
 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 148                                 int wait_to_complete);
 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 150                                 struct rte_eth_stats *stats);
 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 152                                 struct rte_eth_xstat *xstats, unsigned n);
 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 154                                   struct rte_eth_xstat *xstats, unsigned n);
 155 static int
 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 157                 uint64_t *values, unsigned int n);
 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 161         struct rte_eth_xstat_name *xstats_names,
 162         unsigned int size);
 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 165 static int ixgbe_dev_xstats_get_names_by_id(
 166         struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         const uint64_t *ids,
 169         unsigned int limit);
 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 171                                              uint16_t queue_id,
 172                                              uint8_t stat_idx,
 173                                              uint8_t is_rx);
 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 175                                  size_t fw_size);
 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_dev_info *dev_info);
 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 180                                  struct rte_eth_dev_info *dev_info);
 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 182
 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 184                 uint16_t vlan_id, int on);
 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 186                                enum rte_vlan_type vlan_type,
 187                                uint16_t tpid_id);
 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 189                 uint16_t queue, bool on);
 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 191                 int on);
 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 193                                                   int mask);
 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 221 static void ixgbe_dev_interrupt_handler(void *param);
 222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 223 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 224
 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 226                          uint32_t index, uint32_t pool);
 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 228 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 229                                            struct ether_addr *mac_addr);
 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 231 static bool is_device_supported(struct rte_eth_dev *dev,
 232                                 struct rte_pci_driver *drv);
 233
 234 /* For Virtual Function support */
 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 237 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 238 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 240                                    int wait_to_complete);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 245 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 254 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 256 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 257                                             uint16_t queue_id);
 258 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 259                                              uint16_t queue_id);
 260 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 261                                  uint8_t queue, uint8_t msix_vector);
 262 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 265
 266 /* For Eth VMDQ APIs support */
 267 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 268                 ether_addr * mac_addr, uint8_t on);
 269 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 270 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 271                 struct rte_eth_mirror_conf *mirror_conf,
 272                 uint8_t rule_id, uint8_t on);
 273 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 274                 uint8_t rule_id);
 275 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 276                                           uint16_t queue_id);
 277 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 278                                            uint16_t queue_id);
 279 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 280                                uint8_t queue, uint8_t msix_vector);
 281 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 282
 283 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 284                                 struct ether_addr *mac_addr,
 285                                 uint32_t index, uint32_t pool);
 286 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 287 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 288                                              struct ether_addr *mac_addr);
 289 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 290                         struct rte_eth_syn_filter *filter);
 291 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 292                         enum rte_filter_op filter_op,
 293                         void *arg);
 294 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 295                         struct ixgbe_5tuple_filter *filter);
 296 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 297                         struct ixgbe_5tuple_filter *filter);
 298 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 299                                 enum rte_filter_op filter_op,
 300                                 void *arg);
 301 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 302                         struct rte_eth_ntuple_filter *filter);
 303 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 304                                 enum rte_filter_op filter_op,
 305                                 void *arg);
 306 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 307                         struct rte_eth_ethertype_filter *filter);
 308 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 309                      enum rte_filter_type filter_type,
 310                      enum rte_filter_op filter_op,
 311                      void *arg);
 312 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 313
 314 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 315                                       struct ether_addr *mc_addr_set,
 316                                       uint32_t nb_mc_addr);
 317 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 318                                    struct rte_eth_dcb_info *dcb_info);
 319
 320 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 321 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 322                             struct rte_dev_reg_info *regs);
 323 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 324 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 325                                 struct rte_dev_eeprom_info *eeprom);
 326 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 327                                 struct rte_dev_eeprom_info *eeprom);
 328
 329 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 330                                  struct rte_eth_dev_module_info *modinfo);
 331 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 332                                    struct rte_dev_eeprom_info *info);
 333
 334 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 336                                 struct rte_dev_reg_info *regs);
 337
 338 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 340 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 341                                             struct timespec *timestamp,
 342                                             uint32_t flags);
 343 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 344                                             struct timespec *timestamp);
 345 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 346 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 347                                    struct timespec *timestamp);
 348 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 349                                    const struct timespec *timestamp);
 350 static void ixgbevf_dev_interrupt_handler(void *param);
 351
 352 static int ixgbe_dev_l2_tunnel_eth_type_conf
 353         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 354 static int ixgbe_dev_l2_tunnel_offload_set
 355         (struct rte_eth_dev *dev,
 356          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 357          uint32_t mask,
 358          uint8_t en);
 359 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 360                                              enum rte_filter_op filter_op,
 361                                              void *arg);
 362
 363 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 364                                          struct rte_eth_udp_tunnel *udp_tunnel);
 365 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 366                                          struct rte_eth_udp_tunnel *udp_tunnel);
 367 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 368 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 369
 370 /*
 371  * Define VF Stats MACRO for Non "cleared on read" register
 372  */
 373 #define UPDATE_VF_STAT(reg, last, cur)                          \
 374 {                                                               \
 375         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 376         cur += (latest - last) & UINT_MAX;                      \
 377         last = latest;                                          \
 378 }
 379
 380 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 381 {                                                                \
 382         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 383         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 384         u64 latest = ((new_msb << 32) | new_lsb);                \
 385         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 386         last = latest;                                           \
 387 }
 388
 389 #define IXGBE_SET_HWSTRIP(h, q) do {\
 390                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 391                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 392                 (h)->bitmap[idx] |= 1 << bit;\
 393         } while (0)
 394
 395 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 396                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 397                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 398                 (h)->bitmap[idx] &= ~(1 << bit);\
 399         } while (0)
 400
 401 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (r) = (h)->bitmap[idx] >> bit & 1;\
 405         } while (0)
 406
 407 int ixgbe_logtype_init;
 408 int ixgbe_logtype_driver;
 409
 410 /*
 411  * The set of PCI devices this driver supports
 412  */
 413 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 461 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 463 #endif
 464         { .vendor_id = 0, /* sentinel */ },
 465 };
 466
 467 /*
 468  * The set of PCI devices this driver supports (for 82599 VF)
 469  */
 470 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 481         { .vendor_id = 0, /* sentinel */ },
 482 };
 483
 484 static const struct rte_eth_desc_lim rx_desc_lim = {
 485         .nb_max = IXGBE_MAX_RING_DESC,
 486         .nb_min = IXGBE_MIN_RING_DESC,
 487         .nb_align = IXGBE_RXD_ALIGN,
 488 };
 489
 490 static const struct rte_eth_desc_lim tx_desc_lim = {
 491         .nb_max = IXGBE_MAX_RING_DESC,
 492         .nb_min = IXGBE_MIN_RING_DESC,
 493         .nb_align = IXGBE_TXD_ALIGN,
 494         .nb_seg_max = IXGBE_TX_MAX_SEG,
 495         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 496 };
 497
 498 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 499         .dev_configure        = ixgbe_dev_configure,
 500         .dev_start            = ixgbe_dev_start,
 501         .dev_stop             = ixgbe_dev_stop,
 502         .dev_set_link_up    = ixgbe_dev_set_link_up,
 503         .dev_set_link_down  = ixgbe_dev_set_link_down,
 504         .dev_close            = ixgbe_dev_close,
 505         .dev_reset            = ixgbe_dev_reset,
 506         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 507         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 508         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 509         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 510         .link_update          = ixgbe_dev_link_update,
 511         .stats_get            = ixgbe_dev_stats_get,
 512         .xstats_get           = ixgbe_dev_xstats_get,
 513         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 514         .stats_reset          = ixgbe_dev_stats_reset,
 515         .xstats_reset         = ixgbe_dev_xstats_reset,
 516         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 517         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 518         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 519         .fw_version_get       = ixgbe_fw_version_get,
 520         .dev_infos_get        = ixgbe_dev_info_get,
 521         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 522         .mtu_set              = ixgbe_dev_mtu_set,
 523         .vlan_filter_set      = ixgbe_vlan_filter_set,
 524         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 525         .vlan_offload_set     = ixgbe_vlan_offload_set,
 526         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 527         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 528         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 529         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 530         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 531         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 532         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 533         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 534         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 535         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 536         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 537         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 538         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 539         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 540         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 541         .dev_led_on           = ixgbe_dev_led_on,
 542         .dev_led_off          = ixgbe_dev_led_off,
 543         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 544         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 545         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 546         .mac_addr_add         = ixgbe_add_rar,
 547         .mac_addr_remove      = ixgbe_remove_rar,
 548         .mac_addr_set         = ixgbe_set_default_mac_addr,
 549         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 550         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 551         .mirror_rule_set      = ixgbe_mirror_rule_set,
 552         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 553         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 554         .reta_update          = ixgbe_dev_rss_reta_update,
 555         .reta_query           = ixgbe_dev_rss_reta_query,
 556         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 557         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 558         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 559         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 560         .rxq_info_get         = ixgbe_rxq_info_get,
 561         .txq_info_get         = ixgbe_txq_info_get,
 562         .timesync_enable      = ixgbe_timesync_enable,
 563         .timesync_disable     = ixgbe_timesync_disable,
 564         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 565         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 566         .get_reg              = ixgbe_get_regs,
 567         .get_eeprom_length    = ixgbe_get_eeprom_length,
 568         .get_eeprom           = ixgbe_get_eeprom,
 569         .set_eeprom           = ixgbe_set_eeprom,
 570         .get_module_info      = ixgbe_get_module_info,
 571         .get_module_eeprom    = ixgbe_get_module_eeprom,
 572         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 573         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 574         .timesync_read_time   = ixgbe_timesync_read_time,
 575         .timesync_write_time  = ixgbe_timesync_write_time,
 576         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 577         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 578         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 579         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 580         .tm_ops_get           = ixgbe_tm_ops_get,
 581 };
 582
 583 /*
 584  * dev_ops for virtual function, bare necessities for basic vf
 585  * operation have been implemented
 586  */
 587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 588         .dev_configure        = ixgbevf_dev_configure,
 589         .dev_start            = ixgbevf_dev_start,
 590         .dev_stop             = ixgbevf_dev_stop,
 591         .link_update          = ixgbevf_dev_link_update,
 592         .stats_get            = ixgbevf_dev_stats_get,
 593         .xstats_get           = ixgbevf_dev_xstats_get,
 594         .stats_reset          = ixgbevf_dev_stats_reset,
 595         .xstats_reset         = ixgbevf_dev_stats_reset,
 596         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 597         .dev_close            = ixgbevf_dev_close,
 598         .dev_reset            = ixgbevf_dev_reset,
 599         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 600         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 601         .dev_infos_get        = ixgbevf_dev_info_get,
 602         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 603         .mtu_set              = ixgbevf_dev_set_mtu,
 604         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 605         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 606         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 607         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 608         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 609         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 610         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 611         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 612         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 613         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 614         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 615         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 616         .mac_addr_add         = ixgbevf_add_mac_addr,
 617         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 618         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 619         .rxq_info_get         = ixgbe_rxq_info_get,
 620         .txq_info_get         = ixgbe_txq_info_get,
 621         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 622         .get_reg              = ixgbevf_get_regs,
 623         .reta_update          = ixgbe_dev_rss_reta_update,
 624         .reta_query           = ixgbe_dev_rss_reta_query,
 625         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 626         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 627 };
 628
 629 /* store statistics names and its offset in stats structure */
 630 struct rte_ixgbe_xstats_name_off {
 631         char name[RTE_ETH_XSTATS_NAME_SIZE];
 632         unsigned offset;
 633 };
 634
 635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 636         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 637         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 638         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 639         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 640         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 641         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 642         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 643         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 644         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 645         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 646         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 647         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 648         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 649         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 650         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 651                 prc1023)},
 652         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 653                 prc1522)},
 654         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 655         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 656         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 657         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 658         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 659         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 660         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 661         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 662         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 663         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 664         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 665         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 666         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 667         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 668         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 669         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 670         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 671                 ptc1023)},
 672         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 673                 ptc1522)},
 674         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 675         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 676         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 677         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 678
 679         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 680                 fdirustat_add)},
 681         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 682                 fdirustat_remove)},
 683         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 684                 fdirfstat_fadd)},
 685         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 686                 fdirfstat_fremove)},
 687         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 688                 fdirmatch)},
 689         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirmiss)},
 691
 692         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 693         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 694         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 695                 fclast)},
 696         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 697         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 698         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 699         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 700         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 701                 fcoe_noddp)},
 702         {"rx_fcoe_no_direct_data_placement_ext_buff",
 703                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 704
 705         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxontxc)},
 707         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxonrxc)},
 709         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxofftxc)},
 711         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxoffrxc)},
 713         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 714 };
 715
 716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 717                            sizeof(rte_ixgbe_stats_strings[0]))
 718
 719 /* MACsec statistics */
 720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 721         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_untagged)},
 723         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_pkts_encrypted)},
 725         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_protected)},
 727         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 728                 out_octets_encrypted)},
 729         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 730                 out_octets_protected)},
 731         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_untagged)},
 733         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_badtag)},
 735         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_nosci)},
 737         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unknownsci)},
 739         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 740                 in_octets_decrypted)},
 741         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 742                 in_octets_validated)},
 743         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_unchecked)},
 745         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_delayed)},
 747         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_late)},
 749         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_ok)},
 751         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_invalid)},
 753         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notvalid)},
 755         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unusedsa)},
 757         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_notusingsa)},
 759 };
 760
 761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 762                            sizeof(rte_ixgbe_macsec_strings[0]))
 763
 764 /* Per-queue statistics */
 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 766         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 767         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 768         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 769         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 770 };
 771
 772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 773                            sizeof(rte_ixgbe_rxq_strings[0]))
 774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 775
 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 777         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 778         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 779         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 780                 pxon2offc)},
 781 };
 782
 783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 784                            sizeof(rte_ixgbe_txq_strings[0]))
 785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 786
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 788         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 789 };
 790
 791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 792                 sizeof(rte_ixgbevf_stats_strings[0]))
 793
 794 /*
 795  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 796  */
 797 static inline int
 798 ixgbe_is_sfp(struct ixgbe_hw *hw)
 799 {
 800         switch (hw->phy.type) {
 801         case ixgbe_phy_sfp_avago:
 802         case ixgbe_phy_sfp_ftl:
 803         case ixgbe_phy_sfp_intel:
 804         case ixgbe_phy_sfp_unknown:
 805         case ixgbe_phy_sfp_passive_tyco:
 806         case ixgbe_phy_sfp_passive_unknown:
 807                 return 1;
 808         default:
 809                 return 0;
 810         }
 811 }
 812
 813 static inline int32_t
 814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 815 {
 816         uint32_t ctrl_ext;
 817         int32_t status;
 818
 819         status = ixgbe_reset_hw(hw);
 820
 821         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 822         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 823         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 824         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 825         IXGBE_WRITE_FLUSH(hw);
 826
 827         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 828                 status = IXGBE_SUCCESS;
 829         return status;
 830 }
 831
 832 static inline void
 833 ixgbe_enable_intr(struct rte_eth_dev *dev)
 834 {
 835         struct ixgbe_interrupt *intr =
 836                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 837         struct ixgbe_hw *hw =
 838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839
 840         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 846  */
 847 static void
 848 ixgbe_disable_intr(struct ixgbe_hw *hw)
 849 {
 850         PMD_INIT_FUNC_TRACE();
 851
 852         if (hw->mac.type == ixgbe_mac_82598EB) {
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 854         } else {
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 858         }
 859         IXGBE_WRITE_FLUSH(hw);
 860 }
 861
 862 /*
 863  * This function resets queue statistics mapping registers.
 864  * From Niantic datasheet, Initialization of Statistics section:
 865  * "...if software requires the queue counters, the RQSMR and TQSM registers
 866  * must be re-programmed following a device reset.
 867  */
 868 static void
 869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 870 {
 871         uint32_t i;
 872
 873         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 875                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 876         }
 877 }
 878
 879
 880 static int
 881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 882                                   uint16_t queue_id,
 883                                   uint8_t stat_idx,
 884                                   uint8_t is_rx)
 885 {
 886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 889
 890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 891         struct ixgbe_stat_mapping_registers *stat_mappings =
 892                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 893         uint32_t qsmr_mask = 0;
 894         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 895         uint32_t q_map;
 896         uint8_t n, offset;
 897
 898         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 899                 (hw->mac.type != ixgbe_mac_X540) &&
 900                 (hw->mac.type != ixgbe_mac_X550) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 902                 (hw->mac.type != ixgbe_mac_X550EM_a))
 903                 return -ENOSYS;
 904
 905         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 906                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 907                      queue_id, stat_idx);
 908
 909         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 910         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 911                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 912                 return -EIO;
 913         }
 914         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 915
 916         /* Now clear any previous stat_idx set */
 917         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 918         if (!is_rx)
 919                 stat_mappings->tqsm[n] &= ~clearing_mask;
 920         else
 921                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 922
 923         q_map = (uint32_t)stat_idx;
 924         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 925         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 926         if (!is_rx)
 927                 stat_mappings->tqsm[n] |= qsmr_mask;
 928         else
 929                 stat_mappings->rqsmr[n] |= qsmr_mask;
 930
 931         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 932                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 933                      queue_id, stat_idx);
 934         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 935                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 936
 937         /* Now write the mapping in the appropriate register */
 938         if (is_rx) {
 939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 940                              stat_mappings->rqsmr[n], n);
 941                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 942         } else {
 943                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 944                              stat_mappings->tqsm[n], n);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 946         }
 947         return 0;
 948 }
 949
 950 static void
 951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 952 {
 953         struct ixgbe_stat_mapping_registers *stat_mappings =
 954                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956         int i;
 957
 958         /* write whatever was in stat mapping table to the NIC */
 959         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 960                 /* rx */
 961                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 962
 963                 /* tx */
 964                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 965         }
 966 }
 967
 968 static void
 969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 970 {
 971         uint8_t i;
 972         struct ixgbe_dcb_tc_config *tc;
 973         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 974
 975         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 976         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 977         for (i = 0; i < dcb_max_tc; i++) {
 978                 tc = &dcb_config->tc_config[i];
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 980                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 981                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 983                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 984                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 985                 tc->pfc = ixgbe_dcb_pfc_disabled;
 986         }
 987
 988         /* Initialize default user to priority mapping, UPx->TC0 */
 989         tc = &dcb_config->tc_config[0];
 990         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 992         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 993                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 994                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 995         }
 996         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 997         dcb_config->pfc_mode_enable = false;
 998         dcb_config->vt_mode = true;
 999         dcb_config->round_robin_enable = false;
1000         /* support all DCB capabilities in 82599 */
1001         dcb_config->support.capabilities = 0xFF;
1002
1003         /*we only support 4 Tcs for X540, X550 */
1004         if (hw->mac.type == ixgbe_mac_X540 ||
1005                 hw->mac.type == ixgbe_mac_X550 ||
1006                 hw->mac.type == ixgbe_mac_X550EM_x ||
1007                 hw->mac.type == ixgbe_mac_X550EM_a) {
1008                 dcb_config->num_tcs.pg_tcs = 4;
1009                 dcb_config->num_tcs.pfc_tcs = 4;
1010         }
1011 }
1012
1013 /*
1014  * Ensure that all locks are released before first NVM or PHY access
1015  */
1016 static void
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1018 {
1019         uint16_t mask;
1020
1021         /*
1022          * Phy lock should not fail in this early stage. If this is the case,
1023          * it is due to an improper exit of the application.
1024          * So force the release of the faulty lock. Release of common lock
1025          * is done automatically by swfw_sync function.
1026          */
1027         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1030         }
1031         ixgbe_release_swfw_semaphore(hw, mask);
1032
1033         /*
1034          * These ones are more tricky since they are common to all ports; but
1035          * swfw_sync retries last long enough (1s) to be almost sure that if
1036          * lock can not be taken it is due to an improper lock of the
1037          * semaphore.
1038          */
1039         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1042         }
1043         ixgbe_release_swfw_semaphore(hw, mask);
1044 }
1045
1046 /*
1047  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048  * It returns 0 on success.
1049  */
1050 static int
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1052 {
1053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1055         struct ixgbe_hw *hw =
1056                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1057         struct ixgbe_vfta *shadow_vfta =
1058                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1059         struct ixgbe_hwstrip *hwstrip =
1060                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1061         struct ixgbe_dcb_config *dcb_config =
1062                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1063         struct ixgbe_filter_info *filter_info =
1064                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1065         struct ixgbe_bw_conf *bw_conf =
1066                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1067         uint32_t ctrl_ext;
1068         uint16_t csum;
1069         int diag, i;
1070
1071         PMD_INIT_FUNC_TRACE();
1072
1073         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1074         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1075         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1076         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1077
1078         /*
1079          * For secondary processes, we don't initialise any further as primary
1080          * has already done this work. Only check we don't need a different
1081          * RX and TX function.
1082          */
1083         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1084                 struct ixgbe_tx_queue *txq;
1085                 /* TX queue function in primary, set by last queue initialized
1086                  * Tx queue may not initialized by primary process
1087                  */
1088                 if (eth_dev->data->tx_queues) {
1089                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1090                         ixgbe_set_tx_function(eth_dev, txq);
1091                 } else {
1092                         /* Use default TX function if we get here */
1093                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1094                                      "Using default TX function.");
1095                 }
1096
1097                 ixgbe_set_rx_function(eth_dev);
1098
1099                 return 0;
1100         }
1101
1102         rte_eth_copy_pci_info(eth_dev, pci_dev);
1103
1104         /* Vendor and Device ID need to be set before init of shared code */
1105         hw->device_id = pci_dev->id.device_id;
1106         hw->vendor_id = pci_dev->id.vendor_id;
1107         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1108         hw->allow_unsupported_sfp = 1;
1109
1110         /* Initialize the shared code (base driver) */
1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1112         diag = ixgbe_bypass_init_shared_code(hw);
1113 #else
1114         diag = ixgbe_init_shared_code(hw);
1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1116
1117         if (diag != IXGBE_SUCCESS) {
1118                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1119                 return -EIO;
1120         }
1121
1122         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1123                 PMD_INIT_LOG(ERR, "\nERROR: "
1124                         "Firmware recovery mode detected. Limiting functionality.\n"
1125                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1126                         "User Guide for details on firmware recovery mode.");
1127                 return -EIO;
1128         }
1129
1130         /* pick up the PCI bus settings for reporting later */
1131         ixgbe_get_bus_info(hw);
1132
1133         /* Unlock any pending hardware semaphore */
1134         ixgbe_swfw_lock_reset(hw);
1135
1136 #ifdef RTE_LIBRTE_SECURITY
1137         /* Initialize security_ctx only for primary process*/
1138         if (ixgbe_ipsec_ctx_create(eth_dev))
1139                 return -ENOMEM;
1140 #endif
1141
1142         /* Initialize DCB configuration*/
1143         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1144         ixgbe_dcb_init(hw, dcb_config);
1145         /* Get Hardware Flow Control setting */
1146         hw->fc.requested_mode = ixgbe_fc_full;
1147         hw->fc.current_mode = ixgbe_fc_full;
1148         hw->fc.pause_time = IXGBE_FC_PAUSE;
1149         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1150                 hw->fc.low_water[i] = IXGBE_FC_LO;
1151                 hw->fc.high_water[i] = IXGBE_FC_HI;
1152         }
1153         hw->fc.send_xon = 1;
1154
1155         /* Make sure we have a good EEPROM before we read from it */
1156         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1157         if (diag != IXGBE_SUCCESS) {
1158                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1159                 return -EIO;
1160         }
1161
1162 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1163         diag = ixgbe_bypass_init_hw(hw);
1164 #else
1165         diag = ixgbe_init_hw(hw);
1166 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1167
1168         /*
1169          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1170          * is called too soon after the kernel driver unbinding/binding occurs.
1171          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1172          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1173          * also called. See ixgbe_identify_phy_82599(). The reason for the
1174          * failure is not known, and only occuts when virtualisation features
1175          * are disabled in the bios. A delay of 100ms  was found to be enough by
1176          * trial-and-error, and is doubled to be safe.
1177          */
1178         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1179                 rte_delay_ms(200);
1180                 diag = ixgbe_init_hw(hw);
1181         }
1182
1183         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1184                 diag = IXGBE_SUCCESS;
1185
1186         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1187                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1188                              "LOM.  Please be aware there may be issues associated "
1189                              "with your hardware.");
1190                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1191                              "please contact your Intel or hardware representative "
1192                              "who provided you with this hardware.");
1193         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1194                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1195         if (diag) {
1196                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1197                 return -EIO;
1198         }
1199
1200         /* Reset the hw statistics */
1201         ixgbe_dev_stats_reset(eth_dev);
1202
1203         /* disable interrupt */
1204         ixgbe_disable_intr(hw);
1205
1206         /* reset mappings for queue statistics hw counters*/
1207         ixgbe_reset_qstat_mappings(hw);
1208
1209         /* Allocate memory for storing MAC addresses */
1210         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1211                                                hw->mac.num_rar_entries, 0);
1212         if (eth_dev->data->mac_addrs == NULL) {
1213                 PMD_INIT_LOG(ERR,
1214                              "Failed to allocate %u bytes needed to store "
1215                              "MAC addresses",
1216                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1217                 return -ENOMEM;
1218         }
1219         /* Copy the permanent MAC address */
1220         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1221                         &eth_dev->data->mac_addrs[0]);
1222
1223         /* Allocate memory for storing hash filter MAC addresses */
1224         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1225                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1226         if (eth_dev->data->hash_mac_addrs == NULL) {
1227                 PMD_INIT_LOG(ERR,
1228                              "Failed to allocate %d bytes needed to store MAC addresses",
1229                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1230                 return -ENOMEM;
1231         }
1232
1233         /* initialize the vfta */
1234         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1235
1236         /* initialize the hw strip bitmap*/
1237         memset(hwstrip, 0, sizeof(*hwstrip));
1238
1239         /* initialize PF if max_vfs not zero */
1240         ixgbe_pf_host_init(eth_dev);
1241
1242         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1243         /* let hardware know driver is loaded */
1244         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1245         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1246         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1247         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1248         IXGBE_WRITE_FLUSH(hw);
1249
1250         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1251                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1252                              (int) hw->mac.type, (int) hw->phy.type,
1253                              (int) hw->phy.sfp_type);
1254         else
1255                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1256                              (int) hw->mac.type, (int) hw->phy.type);
1257
1258         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1259                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1260                      pci_dev->id.device_id);
1261
1262         rte_intr_callback_register(intr_handle,
1263                                    ixgbe_dev_interrupt_handler, eth_dev);
1264
1265         /* enable uio/vfio intr/eventfd mapping */
1266         rte_intr_enable(intr_handle);
1267
1268         /* enable support intr */
1269         ixgbe_enable_intr(eth_dev);
1270
1271         /* initialize filter info */
1272         memset(filter_info, 0,
1273                sizeof(struct ixgbe_filter_info));
1274
1275         /* initialize 5tuple filter list */
1276         TAILQ_INIT(&filter_info->fivetuple_list);
1277
1278         /* initialize flow director filter list & hash */
1279         ixgbe_fdir_filter_init(eth_dev);
1280
1281         /* initialize l2 tunnel filter list & hash */
1282         ixgbe_l2_tn_filter_init(eth_dev);
1283
1284         /* initialize flow filter lists */
1285         ixgbe_filterlist_init();
1286
1287         /* initialize bandwidth configuration info */
1288         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1289
1290         /* initialize Traffic Manager configuration */
1291         ixgbe_tm_conf_init(eth_dev);
1292
1293         return 0;
1294 }
1295
1296 static int
1297 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1298 {
1299         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1300         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1301         struct ixgbe_hw *hw;
1302         int retries = 0;
1303         int ret;
1304
1305         PMD_INIT_FUNC_TRACE();
1306
1307         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1308                 return 0;
1309
1310         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1311
1312         if (hw->adapter_stopped == 0)
1313                 ixgbe_dev_close(eth_dev);
1314
1315         eth_dev->dev_ops = NULL;
1316         eth_dev->rx_pkt_burst = NULL;
1317         eth_dev->tx_pkt_burst = NULL;
1318
1319         /* Unlock any pending hardware semaphore */
1320         ixgbe_swfw_lock_reset(hw);
1321
1322         /* disable uio intr before callback unregister */
1323         rte_intr_disable(intr_handle);
1324
1325         do {
1326                 ret = rte_intr_callback_unregister(intr_handle,
1327                                 ixgbe_dev_interrupt_handler, eth_dev);
1328                 if (ret >= 0) {
1329                         break;
1330                 } else if (ret != -EAGAIN) {
1331                         PMD_INIT_LOG(ERR,
1332                                 "intr callback unregister failed: %d",
1333                                 ret);
1334                         return ret;
1335                 }
1336                 rte_delay_ms(100);
1337         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1338
1339         /* cancel the delay handler before remove dev */
1340         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1341
1342         /* uninitialize PF if max_vfs not zero */
1343         ixgbe_pf_host_uninit(eth_dev);
1344
1345         /* remove all the fdir filters & hash */
1346         ixgbe_fdir_filter_uninit(eth_dev);
1347
1348         /* remove all the L2 tunnel filters & hash */
1349         ixgbe_l2_tn_filter_uninit(eth_dev);
1350
1351         /* Remove all ntuple filters of the device */
1352         ixgbe_ntuple_filter_uninit(eth_dev);
1353
1354         /* clear all the filters list */
1355         ixgbe_filterlist_flush();
1356
1357         /* Remove all Traffic Manager configuration */
1358         ixgbe_tm_conf_uninit(eth_dev);
1359
1360 #ifdef RTE_LIBRTE_SECURITY
1361         rte_free(eth_dev->security_ctx);
1362 #endif
1363
1364         return 0;
1365 }
1366
1367 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1368 {
1369         struct ixgbe_filter_info *filter_info =
1370                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1371         struct ixgbe_5tuple_filter *p_5tuple;
1372
1373         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1374                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1375                              p_5tuple,
1376                              entries);
1377                 rte_free(p_5tuple);
1378         }
1379         memset(filter_info->fivetuple_mask, 0,
1380                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1381
1382         return 0;
1383 }
1384
1385 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1386 {
1387         struct ixgbe_hw_fdir_info *fdir_info =
1388                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1389         struct ixgbe_fdir_filter *fdir_filter;
1390
1391                 if (fdir_info->hash_map)
1392                 rte_free(fdir_info->hash_map);
1393         if (fdir_info->hash_handle)
1394                 rte_hash_free(fdir_info->hash_handle);
1395
1396         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1397                 TAILQ_REMOVE(&fdir_info->fdir_list,
1398                              fdir_filter,
1399                              entries);
1400                 rte_free(fdir_filter);
1401         }
1402
1403         return 0;
1404 }
1405
1406 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1407 {
1408         struct ixgbe_l2_tn_info *l2_tn_info =
1409                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1410         struct ixgbe_l2_tn_filter *l2_tn_filter;
1411
1412         if (l2_tn_info->hash_map)
1413                 rte_free(l2_tn_info->hash_map);
1414         if (l2_tn_info->hash_handle)
1415                 rte_hash_free(l2_tn_info->hash_handle);
1416
1417         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1418                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1419                              l2_tn_filter,
1420                              entries);
1421                 rte_free(l2_tn_filter);
1422         }
1423
1424         return 0;
1425 }
1426
1427 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1428 {
1429         struct ixgbe_hw_fdir_info *fdir_info =
1430                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1431         char fdir_hash_name[RTE_HASH_NAMESIZE];
1432         struct rte_hash_parameters fdir_hash_params = {
1433                 .name = fdir_hash_name,
1434                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1435                 .key_len = sizeof(union ixgbe_atr_input),
1436                 .hash_func = rte_hash_crc,
1437                 .hash_func_init_val = 0,
1438                 .socket_id = rte_socket_id(),
1439         };
1440
1441         TAILQ_INIT(&fdir_info->fdir_list);
1442         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1443                  "fdir_%s", eth_dev->device->name);
1444         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1445         if (!fdir_info->hash_handle) {
1446                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1447                 return -EINVAL;
1448         }
1449         fdir_info->hash_map = rte_zmalloc("ixgbe",
1450                                           sizeof(struct ixgbe_fdir_filter *) *
1451                                           IXGBE_MAX_FDIR_FILTER_NUM,
1452                                           0);
1453         if (!fdir_info->hash_map) {
1454                 PMD_INIT_LOG(ERR,
1455                              "Failed to allocate memory for fdir hash map!");
1456                 return -ENOMEM;
1457         }
1458         fdir_info->mask_added = FALSE;
1459
1460         return 0;
1461 }
1462
1463 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1464 {
1465         struct ixgbe_l2_tn_info *l2_tn_info =
1466                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1467         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1468         struct rte_hash_parameters l2_tn_hash_params = {
1469                 .name = l2_tn_hash_name,
1470                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1471                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1472                 .hash_func = rte_hash_crc,
1473                 .hash_func_init_val = 0,
1474                 .socket_id = rte_socket_id(),
1475         };
1476
1477         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1478         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1479                  "l2_tn_%s", eth_dev->device->name);
1480         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1481         if (!l2_tn_info->hash_handle) {
1482                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1483                 return -EINVAL;
1484         }
1485         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1486                                    sizeof(struct ixgbe_l2_tn_filter *) *
1487                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1488                                    0);
1489         if (!l2_tn_info->hash_map) {
1490                 PMD_INIT_LOG(ERR,
1491                         "Failed to allocate memory for L2 TN hash map!");
1492                 return -ENOMEM;
1493         }
1494         l2_tn_info->e_tag_en = FALSE;
1495         l2_tn_info->e_tag_fwd_en = FALSE;
1496         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1497
1498         return 0;
1499 }
1500 /*
1501  * Negotiate mailbox API version with the PF.
1502  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1503  * Then we try to negotiate starting with the most recent one.
1504  * If all negotiation attempts fail, then we will proceed with
1505  * the default one (ixgbe_mbox_api_10).
1506  */
1507 static void
1508 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1509 {
1510         int32_t i;
1511
1512         /* start with highest supported, proceed down */
1513         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1514                 ixgbe_mbox_api_12,
1515                 ixgbe_mbox_api_11,
1516                 ixgbe_mbox_api_10,
1517         };
1518
1519         for (i = 0;
1520                         i != RTE_DIM(sup_ver) &&
1521                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1522                         i++)
1523                 ;
1524 }
1525
1526 static void
1527 generate_random_mac_addr(struct ether_addr *mac_addr)
1528 {
1529         uint64_t random;
1530
1531         /* Set Organizationally Unique Identifier (OUI) prefix. */
1532         mac_addr->addr_bytes[0] = 0x00;
1533         mac_addr->addr_bytes[1] = 0x09;
1534         mac_addr->addr_bytes[2] = 0xC0;
1535         /* Force indication of locally assigned MAC address. */
1536         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1537         /* Generate the last 3 bytes of the MAC address with a random number. */
1538         random = rte_rand();
1539         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1540 }
1541
1542 /*
1543  * Virtual Function device init
1544  */
1545 static int
1546 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1547 {
1548         int diag;
1549         uint32_t tc, tcs;
1550         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1551         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1552         struct ixgbe_hw *hw =
1553                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1554         struct ixgbe_vfta *shadow_vfta =
1555                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1556         struct ixgbe_hwstrip *hwstrip =
1557                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1558         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1559
1560         PMD_INIT_FUNC_TRACE();
1561
1562         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1563         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1564         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1565
1566         /* for secondary processes, we don't initialise any further as primary
1567          * has already done this work. Only check we don't need a different
1568          * RX function
1569          */
1570         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1571                 struct ixgbe_tx_queue *txq;
1572                 /* TX queue function in primary, set by last queue initialized
1573                  * Tx queue may not initialized by primary process
1574                  */
1575                 if (eth_dev->data->tx_queues) {
1576                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1577                         ixgbe_set_tx_function(eth_dev, txq);
1578                 } else {
1579                         /* Use default TX function if we get here */
1580                         PMD_INIT_LOG(NOTICE,
1581                                      "No TX queues configured yet. Using default TX function.");
1582                 }
1583
1584                 ixgbe_set_rx_function(eth_dev);
1585
1586                 return 0;
1587         }
1588
1589         rte_eth_copy_pci_info(eth_dev, pci_dev);
1590
1591         hw->device_id = pci_dev->id.device_id;
1592         hw->vendor_id = pci_dev->id.vendor_id;
1593         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1594
1595         /* initialize the vfta */
1596         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1597
1598         /* initialize the hw strip bitmap*/
1599         memset(hwstrip, 0, sizeof(*hwstrip));
1600
1601         /* Initialize the shared code (base driver) */
1602         diag = ixgbe_init_shared_code(hw);
1603         if (diag != IXGBE_SUCCESS) {
1604                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1605                 return -EIO;
1606         }
1607
1608         /* init_mailbox_params */
1609         hw->mbx.ops.init_params(hw);
1610
1611         /* Reset the hw statistics */
1612         ixgbevf_dev_stats_reset(eth_dev);
1613
1614         /* Disable the interrupts for VF */
1615         ixgbevf_intr_disable(eth_dev);
1616
1617         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1618         diag = hw->mac.ops.reset_hw(hw);
1619
1620         /*
1621          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1622          * the underlying PF driver has not assigned a MAC address to the VF.
1623          * In this case, assign a random MAC address.
1624          */
1625         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1626                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1627                 /*
1628                  * This error code will be propagated to the app by
1629                  * rte_eth_dev_reset, so use a public error code rather than
1630                  * the internal-only IXGBE_ERR_RESET_FAILED
1631                  */
1632                 return -EAGAIN;
1633         }
1634
1635         /* negotiate mailbox API version to use with the PF. */
1636         ixgbevf_negotiate_api(hw);
1637
1638         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1639         ixgbevf_get_queues(hw, &tcs, &tc);
1640
1641         /* Allocate memory for storing MAC addresses */
1642         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1643                                                hw->mac.num_rar_entries, 0);
1644         if (eth_dev->data->mac_addrs == NULL) {
1645                 PMD_INIT_LOG(ERR,
1646                              "Failed to allocate %u bytes needed to store "
1647                              "MAC addresses",
1648                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1649                 return -ENOMEM;
1650         }
1651
1652         /* Generate a random MAC address, if none was assigned by PF. */
1653         if (is_zero_ether_addr(perm_addr)) {
1654                 generate_random_mac_addr(perm_addr);
1655                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1656                 if (diag) {
1657                         rte_free(eth_dev->data->mac_addrs);
1658                         eth_dev->data->mac_addrs = NULL;
1659                         return diag;
1660                 }
1661                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1662                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1663                              "%02x:%02x:%02x:%02x:%02x:%02x",
1664                              perm_addr->addr_bytes[0],
1665                              perm_addr->addr_bytes[1],
1666                              perm_addr->addr_bytes[2],
1667                              perm_addr->addr_bytes[3],
1668                              perm_addr->addr_bytes[4],
1669                              perm_addr->addr_bytes[5]);
1670         }
1671
1672         /* Copy the permanent MAC address */
1673         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1674
1675         /* reset the hardware with the new settings */
1676         diag = hw->mac.ops.start_hw(hw);
1677         switch (diag) {
1678         case  0:
1679                 break;
1680
1681         default:
1682                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1683                 return -EIO;
1684         }
1685
1686         rte_intr_callback_register(intr_handle,
1687                                    ixgbevf_dev_interrupt_handler, eth_dev);
1688         rte_intr_enable(intr_handle);
1689         ixgbevf_intr_enable(eth_dev);
1690
1691         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1692                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1693                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1694
1695         return 0;
1696 }
1697
1698 /* Virtual Function device uninit */
1699
1700 static int
1701 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1702 {
1703         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1704         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1705         struct ixgbe_hw *hw;
1706
1707         PMD_INIT_FUNC_TRACE();
1708
1709         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1710                 return 0;
1711
1712         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1713
1714         if (hw->adapter_stopped == 0)
1715                 ixgbevf_dev_close(eth_dev);
1716
1717         eth_dev->dev_ops = NULL;
1718         eth_dev->rx_pkt_burst = NULL;
1719         eth_dev->tx_pkt_burst = NULL;
1720
1721         /* Disable the interrupts for VF */
1722         ixgbevf_intr_disable(eth_dev);
1723
1724         rte_intr_disable(intr_handle);
1725         rte_intr_callback_unregister(intr_handle,
1726                                      ixgbevf_dev_interrupt_handler, eth_dev);
1727
1728         return 0;
1729 }
1730
1731 static int
1732 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1733                 struct rte_pci_device *pci_dev)
1734 {
1735         char name[RTE_ETH_NAME_MAX_LEN];
1736         struct rte_eth_dev *pf_ethdev;
1737         struct rte_eth_devargs eth_da;
1738         int i, retval;
1739
1740         if (pci_dev->device.devargs) {
1741                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1742                                 &eth_da);
1743                 if (retval)
1744                         return retval;
1745         } else
1746                 memset(&eth_da, 0, sizeof(eth_da));
1747
1748         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1749                 sizeof(struct ixgbe_adapter),
1750                 eth_dev_pci_specific_init, pci_dev,
1751                 eth_ixgbe_dev_init, NULL);
1752
1753         if (retval || eth_da.nb_representor_ports < 1)
1754                 return retval;
1755
1756         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1757         if (pf_ethdev == NULL)
1758                 return -ENODEV;
1759
1760         /* probe VF representor ports */
1761         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1762                 struct ixgbe_vf_info *vfinfo;
1763                 struct ixgbe_vf_representor representor;
1764
1765                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1766                         pf_ethdev->data->dev_private);
1767                 if (vfinfo == NULL) {
1768                         PMD_DRV_LOG(ERR,
1769                                 "no virtual functions supported by PF");
1770                         break;
1771                 }
1772
1773                 representor.vf_id = eth_da.representor_ports[i];
1774                 representor.switch_domain_id = vfinfo->switch_domain_id;
1775                 representor.pf_ethdev = pf_ethdev;
1776
1777                 /* representor port net_bdf_port */
1778                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1779                         pci_dev->device.name,
1780                         eth_da.representor_ports[i]);
1781
1782                 retval = rte_eth_dev_create(&pci_dev->device, name,
1783                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1784                         ixgbe_vf_representor_init, &representor);
1785
1786                 if (retval)
1787                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1788                                 "representor %s.", name);
1789         }
1790
1791         return 0;
1792 }
1793
1794 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1795 {
1796         struct rte_eth_dev *ethdev;
1797
1798         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1799         if (!ethdev)
1800                 return -ENODEV;
1801
1802         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1803                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1804         else
1805                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1806 }
1807
1808 static struct rte_pci_driver rte_ixgbe_pmd = {
1809         .id_table = pci_id_ixgbe_map,
1810         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1811                      RTE_PCI_DRV_IOVA_AS_VA,
1812         .probe = eth_ixgbe_pci_probe,
1813         .remove = eth_ixgbe_pci_remove,
1814 };
1815
1816 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1817         struct rte_pci_device *pci_dev)
1818 {
1819         return rte_eth_dev_pci_generic_probe(pci_dev,
1820                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1821 }
1822
1823 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1824 {
1825         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1826 }
1827
1828 /*
1829  * virtual function driver struct
1830  */
1831 static struct rte_pci_driver rte_ixgbevf_pmd = {
1832         .id_table = pci_id_ixgbevf_map,
1833         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1834         .probe = eth_ixgbevf_pci_probe,
1835         .remove = eth_ixgbevf_pci_remove,
1836 };
1837
1838 static int
1839 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1840 {
1841         struct ixgbe_hw *hw =
1842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843         struct ixgbe_vfta *shadow_vfta =
1844                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1845         uint32_t vfta;
1846         uint32_t vid_idx;
1847         uint32_t vid_bit;
1848
1849         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1850         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1851         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1852         if (on)
1853                 vfta |= vid_bit;
1854         else
1855                 vfta &= ~vid_bit;
1856         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1857
1858         /* update local VFTA copy */
1859         shadow_vfta->vfta[vid_idx] = vfta;
1860
1861         return 0;
1862 }
1863
1864 static void
1865 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1866 {
1867         if (on)
1868                 ixgbe_vlan_hw_strip_enable(dev, queue);
1869         else
1870                 ixgbe_vlan_hw_strip_disable(dev, queue);
1871 }
1872
1873 static int
1874 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1875                     enum rte_vlan_type vlan_type,
1876                     uint16_t tpid)
1877 {
1878         struct ixgbe_hw *hw =
1879                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1880         int ret = 0;
1881         uint32_t reg;
1882         uint32_t qinq;
1883
1884         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1885         qinq &= IXGBE_DMATXCTL_GDV;
1886
1887         switch (vlan_type) {
1888         case ETH_VLAN_TYPE_INNER:
1889                 if (qinq) {
1890                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1891                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1892                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1893                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1894                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1895                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1896                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1897                 } else {
1898                         ret = -ENOTSUP;
1899                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1900                                     " by single VLAN");
1901                 }
1902                 break;
1903         case ETH_VLAN_TYPE_OUTER:
1904                 if (qinq) {
1905                         /* Only the high 16-bits is valid */
1906                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1907                                         IXGBE_EXVET_VET_EXT_SHIFT);
1908                 } else {
1909                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1910                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1911                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1912                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1913                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1914                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1915                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1916                 }
1917
1918                 break;
1919         default:
1920                 ret = -EINVAL;
1921                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1922                 break;
1923         }
1924
1925         return ret;
1926 }
1927
1928 void
1929 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1930 {
1931         struct ixgbe_hw *hw =
1932                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933         uint32_t vlnctrl;
1934
1935         PMD_INIT_FUNC_TRACE();
1936
1937         /* Filter Table Disable */
1938         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1939         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1940
1941         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1942 }
1943
1944 void
1945 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1946 {
1947         struct ixgbe_hw *hw =
1948                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949         struct ixgbe_vfta *shadow_vfta =
1950                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1951         uint32_t vlnctrl;
1952         uint16_t i;
1953
1954         PMD_INIT_FUNC_TRACE();
1955
1956         /* Filter Table Enable */
1957         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1958         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1959         vlnctrl |= IXGBE_VLNCTRL_VFE;
1960
1961         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1962
1963         /* write whatever is in local vfta copy */
1964         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1965                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1966 }
1967
1968 static void
1969 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1970 {
1971         struct ixgbe_hwstrip *hwstrip =
1972                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1973         struct ixgbe_rx_queue *rxq;
1974
1975         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1976                 return;
1977
1978         if (on)
1979                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1980         else
1981                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1982
1983         if (queue >= dev->data->nb_rx_queues)
1984                 return;
1985
1986         rxq = dev->data->rx_queues[queue];
1987
1988         if (on) {
1989                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1990                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1991         } else {
1992                 rxq->vlan_flags = PKT_RX_VLAN;
1993                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1994         }
1995 }
1996
1997 static void
1998 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1999 {
2000         struct ixgbe_hw *hw =
2001                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2002         uint32_t ctrl;
2003
2004         PMD_INIT_FUNC_TRACE();
2005
2006         if (hw->mac.type == ixgbe_mac_82598EB) {
2007                 /* No queue level support */
2008                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2009                 return;
2010         }
2011
2012         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2013         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2014         ctrl &= ~IXGBE_RXDCTL_VME;
2015         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2016
2017         /* record those setting for HW strip per queue */
2018         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2019 }
2020
2021 static void
2022 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2023 {
2024         struct ixgbe_hw *hw =
2025                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2026         uint32_t ctrl;
2027
2028         PMD_INIT_FUNC_TRACE();
2029
2030         if (hw->mac.type == ixgbe_mac_82598EB) {
2031                 /* No queue level supported */
2032                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2033                 return;
2034         }
2035
2036         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2037         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2038         ctrl |= IXGBE_RXDCTL_VME;
2039         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2040
2041         /* record those setting for HW strip per queue */
2042         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2043 }
2044
2045 static void
2046 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2047 {
2048         struct ixgbe_hw *hw =
2049                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050         uint32_t ctrl;
2051
2052         PMD_INIT_FUNC_TRACE();
2053
2054         /* DMATXCTRL: Geric Double VLAN Disable */
2055         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2056         ctrl &= ~IXGBE_DMATXCTL_GDV;
2057         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2058
2059         /* CTRL_EXT: Global Double VLAN Disable */
2060         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2061         ctrl &= ~IXGBE_EXTENDED_VLAN;
2062         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2063
2064 }
2065
2066 static void
2067 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2068 {
2069         struct ixgbe_hw *hw =
2070                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2071         uint32_t ctrl;
2072
2073         PMD_INIT_FUNC_TRACE();
2074
2075         /* DMATXCTRL: Geric Double VLAN Enable */
2076         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2077         ctrl |= IXGBE_DMATXCTL_GDV;
2078         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2079
2080         /* CTRL_EXT: Global Double VLAN Enable */
2081         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2082         ctrl |= IXGBE_EXTENDED_VLAN;
2083         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2084
2085         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2086         if (hw->mac.type == ixgbe_mac_X550 ||
2087             hw->mac.type == ixgbe_mac_X550EM_x ||
2088             hw->mac.type == ixgbe_mac_X550EM_a) {
2089                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2090                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2091                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2092         }
2093
2094         /*
2095          * VET EXT field in the EXVET register = 0x8100 by default
2096          * So no need to change. Same to VT field of DMATXCTL register
2097          */
2098 }
2099
2100 void
2101 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2102 {
2103         struct ixgbe_hw *hw =
2104                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2106         uint32_t ctrl;
2107         uint16_t i;
2108         struct ixgbe_rx_queue *rxq;
2109         bool on;
2110
2111         PMD_INIT_FUNC_TRACE();
2112
2113         if (hw->mac.type == ixgbe_mac_82598EB) {
2114                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2115                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2116                         ctrl |= IXGBE_VLNCTRL_VME;
2117                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2118                 } else {
2119                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2120                         ctrl &= ~IXGBE_VLNCTRL_VME;
2121                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2122                 }
2123         } else {
2124                 /*
2125                  * Other 10G NIC, the VLAN strip can be setup
2126                  * per queue in RXDCTL
2127                  */
2128                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2129                         rxq = dev->data->rx_queues[i];
2130                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2131                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2132                                 ctrl |= IXGBE_RXDCTL_VME;
2133                                 on = TRUE;
2134                         } else {
2135                                 ctrl &= ~IXGBE_RXDCTL_VME;
2136                                 on = FALSE;
2137                         }
2138                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2139
2140                         /* record those setting for HW strip per queue */
2141                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2142                 }
2143         }
2144 }
2145
2146 static void
2147 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2148 {
2149         uint16_t i;
2150         struct rte_eth_rxmode *rxmode;
2151         struct ixgbe_rx_queue *rxq;
2152
2153         if (mask & ETH_VLAN_STRIP_MASK) {
2154                 rxmode = &dev->data->dev_conf.rxmode;
2155                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2156                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2157                                 rxq = dev->data->rx_queues[i];
2158                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2159                         }
2160                 else
2161                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2162                                 rxq = dev->data->rx_queues[i];
2163                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2164                         }
2165         }
2166 }
2167
2168 static int
2169 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2170 {
2171         struct rte_eth_rxmode *rxmode;
2172         rxmode = &dev->data->dev_conf.rxmode;
2173
2174         if (mask & ETH_VLAN_STRIP_MASK) {
2175                 ixgbe_vlan_hw_strip_config(dev);
2176         }
2177
2178         if (mask & ETH_VLAN_FILTER_MASK) {
2179                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2180                         ixgbe_vlan_hw_filter_enable(dev);
2181                 else
2182                         ixgbe_vlan_hw_filter_disable(dev);
2183         }
2184
2185         if (mask & ETH_VLAN_EXTEND_MASK) {
2186                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2187                         ixgbe_vlan_hw_extend_enable(dev);
2188                 else
2189                         ixgbe_vlan_hw_extend_disable(dev);
2190         }
2191
2192         return 0;
2193 }
2194
2195 static int
2196 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2197 {
2198         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2199
2200         ixgbe_vlan_offload_config(dev, mask);
2201
2202         return 0;
2203 }
2204
2205 static void
2206 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2207 {
2208         struct ixgbe_hw *hw =
2209                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2210         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2211         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2212
2213         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2214         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2215 }
2216
2217 static int
2218 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2219 {
2220         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2221
2222         switch (nb_rx_q) {
2223         case 1:
2224         case 2:
2225                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2226                 break;
2227         case 4:
2228                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2229                 break;
2230         default:
2231                 return -EINVAL;
2232         }
2233
2234         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2235                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2236         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2237                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2238         return 0;
2239 }
2240
2241 static int
2242 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2243 {
2244         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2245         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2247         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2248
2249         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2250                 /* check multi-queue mode */
2251                 switch (dev_conf->rxmode.mq_mode) {
2252                 case ETH_MQ_RX_VMDQ_DCB:
2253                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2254                         break;
2255                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2256                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2257                         PMD_INIT_LOG(ERR, "SRIOV active,"
2258                                         " unsupported mq_mode rx %d.",
2259                                         dev_conf->rxmode.mq_mode);
2260                         return -EINVAL;
2261                 case ETH_MQ_RX_RSS:
2262                 case ETH_MQ_RX_VMDQ_RSS:
2263                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2264                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2265                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2266                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2267                                                 " invalid queue number"
2268                                                 " for VMDQ RSS, allowed"
2269                                                 " value are 1, 2 or 4.");
2270                                         return -EINVAL;
2271                                 }
2272                         break;
2273                 case ETH_MQ_RX_VMDQ_ONLY:
2274                 case ETH_MQ_RX_NONE:
2275                         /* if nothing mq mode configure, use default scheme */
2276                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2277                         break;
2278                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2279                         /* SRIOV only works in VMDq enable mode */
2280                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2281                                         " wrong mq_mode rx %d.",
2282                                         dev_conf->rxmode.mq_mode);
2283                         return -EINVAL;
2284                 }
2285
2286                 switch (dev_conf->txmode.mq_mode) {
2287                 case ETH_MQ_TX_VMDQ_DCB:
2288                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2289                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2290                         break;
2291                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2292                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2293                         break;
2294                 }
2295
2296                 /* check valid queue number */
2297                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2298                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2299                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2300                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2301                                         " must be less than or equal to %d.",
2302                                         nb_rx_q, nb_tx_q,
2303                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2304                         return -EINVAL;
2305                 }
2306         } else {
2307                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2308                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2309                                           " not supported.");
2310                         return -EINVAL;
2311                 }
2312                 /* check configuration for vmdb+dcb mode */
2313                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2314                         const struct rte_eth_vmdq_dcb_conf *conf;
2315
2316                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2317                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2318                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2319                                 return -EINVAL;
2320                         }
2321                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2322                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2323                                conf->nb_queue_pools == ETH_32_POOLS)) {
2324                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2325                                                 " nb_queue_pools must be %d or %d.",
2326                                                 ETH_16_POOLS, ETH_32_POOLS);
2327                                 return -EINVAL;
2328                         }
2329                 }
2330                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2331                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2332
2333                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2334                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2335                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2336                                 return -EINVAL;
2337                         }
2338                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2339                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2340                                conf->nb_queue_pools == ETH_32_POOLS)) {
2341                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2342                                                 " nb_queue_pools != %d and"
2343                                                 " nb_queue_pools != %d.",
2344                                                 ETH_16_POOLS, ETH_32_POOLS);
2345                                 return -EINVAL;
2346                         }
2347                 }
2348
2349                 /* For DCB mode check our configuration before we go further */
2350                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2351                         const struct rte_eth_dcb_rx_conf *conf;
2352
2353                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2354                         if (!(conf->nb_tcs == ETH_4_TCS ||
2355                                conf->nb_tcs == ETH_8_TCS)) {
2356                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2357                                                 " and nb_tcs != %d.",
2358                                                 ETH_4_TCS, ETH_8_TCS);
2359                                 return -EINVAL;
2360                         }
2361                 }
2362
2363                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2364                         const struct rte_eth_dcb_tx_conf *conf;
2365
2366                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2367                         if (!(conf->nb_tcs == ETH_4_TCS ||
2368                                conf->nb_tcs == ETH_8_TCS)) {
2369                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2370                                                 " and nb_tcs != %d.",
2371                                                 ETH_4_TCS, ETH_8_TCS);
2372                                 return -EINVAL;
2373                         }
2374                 }
2375
2376                 /*
2377                  * When DCB/VT is off, maximum number of queues changes,
2378                  * except for 82598EB, which remains constant.
2379                  */
2380                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2381                                 hw->mac.type != ixgbe_mac_82598EB) {
2382                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2383                                 PMD_INIT_LOG(ERR,
2384                                              "Neither VT nor DCB are enabled, "
2385                                              "nb_tx_q > %d.",
2386                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2387                                 return -EINVAL;
2388                         }
2389                 }
2390         }
2391         return 0;
2392 }
2393
2394 static int
2395 ixgbe_dev_configure(struct rte_eth_dev *dev)
2396 {
2397         struct ixgbe_interrupt *intr =
2398                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2399         struct ixgbe_adapter *adapter =
2400                 (struct ixgbe_adapter *)dev->data->dev_private;
2401         int ret;
2402
2403         PMD_INIT_FUNC_TRACE();
2404         /* multipe queue mode checking */
2405         ret  = ixgbe_check_mq_mode(dev);
2406         if (ret != 0) {
2407                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2408                             ret);
2409                 return ret;
2410         }
2411
2412         /* set flag to update link status after init */
2413         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2414
2415         /*
2416          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2417          * allocation or vector Rx preconditions we will reset it.
2418          */
2419         adapter->rx_bulk_alloc_allowed = true;
2420         adapter->rx_vec_allowed = true;
2421
2422         return 0;
2423 }
2424
2425 static void
2426 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2427 {
2428         struct ixgbe_hw *hw =
2429                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430         struct ixgbe_interrupt *intr =
2431                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2432         uint32_t gpie;
2433
2434         /* only set up it on X550EM_X */
2435         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2436                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2437                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2438                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2439                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2440                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2441         }
2442 }
2443
2444 int
2445 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2446                         uint16_t tx_rate, uint64_t q_msk)
2447 {
2448         struct ixgbe_hw *hw;
2449         struct ixgbe_vf_info *vfinfo;
2450         struct rte_eth_link link;
2451         uint8_t  nb_q_per_pool;
2452         uint32_t queue_stride;
2453         uint32_t queue_idx, idx = 0, vf_idx;
2454         uint32_t queue_end;
2455         uint16_t total_rate = 0;
2456         struct rte_pci_device *pci_dev;
2457
2458         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2459         rte_eth_link_get_nowait(dev->data->port_id, &link);
2460
2461         if (vf >= pci_dev->max_vfs)
2462                 return -EINVAL;
2463
2464         if (tx_rate > link.link_speed)
2465                 return -EINVAL;
2466
2467         if (q_msk == 0)
2468                 return 0;
2469
2470         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2472         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2473         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2474         queue_idx = vf * queue_stride;
2475         queue_end = queue_idx + nb_q_per_pool - 1;
2476         if (queue_end >= hw->mac.max_tx_queues)
2477                 return -EINVAL;
2478
2479         if (vfinfo) {
2480                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2481                         if (vf_idx == vf)
2482                                 continue;
2483                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2484                                 idx++)
2485                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2486                 }
2487         } else {
2488                 return -EINVAL;
2489         }
2490
2491         /* Store tx_rate for this vf. */
2492         for (idx = 0; idx < nb_q_per_pool; idx++) {
2493                 if (((uint64_t)0x1 << idx) & q_msk) {
2494                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2495                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2496                         total_rate += tx_rate;
2497                 }
2498         }
2499
2500         if (total_rate > dev->data->dev_link.link_speed) {
2501                 /* Reset stored TX rate of the VF if it causes exceed
2502                  * link speed.
2503                  */
2504                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2505                 return -EINVAL;
2506         }
2507
2508         /* Set RTTBCNRC of each queue/pool for vf X  */
2509         for (; queue_idx <= queue_end; queue_idx++) {
2510                 if (0x1 & q_msk)
2511                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2512                 q_msk = q_msk >> 1;
2513         }
2514
2515         return 0;
2516 }
2517
2518 /*
2519  * Configure device link speed and setup link.
2520  * It returns 0 on success.
2521  */
2522 static int
2523 ixgbe_dev_start(struct rte_eth_dev *dev)
2524 {
2525         struct ixgbe_hw *hw =
2526                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527         struct ixgbe_vf_info *vfinfo =
2528                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2529         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2530         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2531         uint32_t intr_vector = 0;
2532         int err, link_up = 0, negotiate = 0;
2533         uint32_t speed = 0;
2534         uint32_t allowed_speeds = 0;
2535         int mask = 0;
2536         int status;
2537         uint16_t vf, idx;
2538         uint32_t *link_speeds;
2539         struct ixgbe_tm_conf *tm_conf =
2540                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2541
2542         PMD_INIT_FUNC_TRACE();
2543
2544         /* IXGBE devices don't support:
2545         *    - half duplex (checked afterwards for valid speeds)
2546         *    - fixed speed: TODO implement
2547         */
2548         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2549                 PMD_INIT_LOG(ERR,
2550                 "Invalid link_speeds for port %u, fix speed not supported",
2551                                 dev->data->port_id);
2552                 return -EINVAL;
2553         }
2554
2555         /* Stop the link setup handler before resetting the HW. */
2556         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2557
2558         /* disable uio/vfio intr/eventfd mapping */
2559         rte_intr_disable(intr_handle);
2560
2561         /* stop adapter */
2562         hw->adapter_stopped = 0;
2563         ixgbe_stop_adapter(hw);
2564
2565         /* reinitialize adapter
2566          * this calls reset and start
2567          */
2568         status = ixgbe_pf_reset_hw(hw);
2569         if (status != 0)
2570                 return -1;
2571         hw->mac.ops.start_hw(hw);
2572         hw->mac.get_link_status = true;
2573
2574         /* configure PF module if SRIOV enabled */
2575         ixgbe_pf_host_configure(dev);
2576
2577         ixgbe_dev_phy_intr_setup(dev);
2578
2579         /* check and configure queue intr-vector mapping */
2580         if ((rte_intr_cap_multiple(intr_handle) ||
2581              !RTE_ETH_DEV_SRIOV(dev).active) &&
2582             dev->data->dev_conf.intr_conf.rxq != 0) {
2583                 intr_vector = dev->data->nb_rx_queues;
2584                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2585                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2586                                         IXGBE_MAX_INTR_QUEUE_NUM);
2587                         return -ENOTSUP;
2588                 }
2589                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2590                         return -1;
2591         }
2592
2593         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2594                 intr_handle->intr_vec =
2595                         rte_zmalloc("intr_vec",
2596                                     dev->data->nb_rx_queues * sizeof(int), 0);
2597                 if (intr_handle->intr_vec == NULL) {
2598                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2599                                      " intr_vec", dev->data->nb_rx_queues);
2600                         return -ENOMEM;
2601                 }
2602         }
2603
2604         /* confiugre msix for sleep until rx interrupt */
2605         ixgbe_configure_msix(dev);
2606
2607         /* initialize transmission unit */
2608         ixgbe_dev_tx_init(dev);
2609
2610         /* This can fail when allocating mbufs for descriptor rings */
2611         err = ixgbe_dev_rx_init(dev);
2612         if (err) {
2613                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2614                 goto error;
2615         }
2616
2617         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2618                 ETH_VLAN_EXTEND_MASK;
2619         err = ixgbe_vlan_offload_config(dev, mask);
2620         if (err) {
2621                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2622                 goto error;
2623         }
2624
2625         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2626                 /* Enable vlan filtering for VMDq */
2627                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2628         }
2629
2630         /* Configure DCB hw */
2631         ixgbe_configure_dcb(dev);
2632
2633         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2634                 err = ixgbe_fdir_configure(dev);
2635                 if (err)
2636                         goto error;
2637         }
2638
2639         /* Restore vf rate limit */
2640         if (vfinfo != NULL) {
2641                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2642                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2643                                 if (vfinfo[vf].tx_rate[idx] != 0)
2644                                         ixgbe_set_vf_rate_limit(
2645                                                 dev, vf,
2646                                                 vfinfo[vf].tx_rate[idx],
2647                                                 1 << idx);
2648         }
2649
2650         ixgbe_restore_statistics_mapping(dev);
2651
2652         err = ixgbe_dev_rxtx_start(dev);
2653         if (err < 0) {
2654                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2655                 goto error;
2656         }
2657
2658         /* Skip link setup if loopback mode is enabled. */
2659         if (dev->data->dev_conf.lpbk_mode != 0) {
2660                 err = ixgbe_check_supported_loopback_mode(dev);
2661                 if (err < 0) {
2662                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2663                         goto error;
2664                 } else {
2665                         goto skip_link_setup;
2666                 }
2667         }
2668
2669         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2670                 err = hw->mac.ops.setup_sfp(hw);
2671                 if (err)
2672                         goto error;
2673         }
2674
2675         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2676                 /* Turn on the copper */
2677                 ixgbe_set_phy_power(hw, true);
2678         } else {
2679                 /* Turn on the laser */
2680                 ixgbe_enable_tx_laser(hw);
2681         }
2682
2683         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2684         if (err)
2685                 goto error;
2686         dev->data->dev_link.link_status = link_up;
2687
2688         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2689         if (err)
2690                 goto error;
2691
2692         switch (hw->mac.type) {
2693         case ixgbe_mac_X550:
2694         case ixgbe_mac_X550EM_x:
2695         case ixgbe_mac_X550EM_a:
2696                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2697                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2698                         ETH_LINK_SPEED_10G;
2699                 break;
2700         default:
2701                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2702                         ETH_LINK_SPEED_10G;
2703         }
2704
2705         link_speeds = &dev->data->dev_conf.link_speeds;
2706         if (*link_speeds & ~allowed_speeds) {
2707                 PMD_INIT_LOG(ERR, "Invalid link setting");
2708                 goto error;
2709         }
2710
2711         speed = 0x0;
2712         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2713                 switch (hw->mac.type) {
2714                 case ixgbe_mac_82598EB:
2715                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2716                         break;
2717                 case ixgbe_mac_82599EB:
2718                 case ixgbe_mac_X540:
2719                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2720                         break;
2721                 case ixgbe_mac_X550:
2722                 case ixgbe_mac_X550EM_x:
2723                 case ixgbe_mac_X550EM_a:
2724                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2725                         break;
2726                 default:
2727                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2728                 }
2729         } else {
2730                 if (*link_speeds & ETH_LINK_SPEED_10G)
2731                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2732                 if (*link_speeds & ETH_LINK_SPEED_5G)
2733                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2734                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2735                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2736                 if (*link_speeds & ETH_LINK_SPEED_1G)
2737                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2738                 if (*link_speeds & ETH_LINK_SPEED_100M)
2739                         speed |= IXGBE_LINK_SPEED_100_FULL;
2740         }
2741
2742         err = ixgbe_setup_link(hw, speed, link_up);
2743         if (err)
2744                 goto error;
2745
2746 skip_link_setup:
2747
2748         if (rte_intr_allow_others(intr_handle)) {
2749                 /* check if lsc interrupt is enabled */
2750                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2751                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2752                 else
2753                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2754                 ixgbe_dev_macsec_interrupt_setup(dev);
2755         } else {
2756                 rte_intr_callback_unregister(intr_handle,
2757                                              ixgbe_dev_interrupt_handler, dev);
2758                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2759                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2760                                      " no intr multiplex");
2761         }
2762
2763         /* check if rxq interrupt is enabled */
2764         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2765             rte_intr_dp_is_en(intr_handle))
2766                 ixgbe_dev_rxq_interrupt_setup(dev);
2767
2768         /* enable uio/vfio intr/eventfd mapping */
2769         rte_intr_enable(intr_handle);
2770
2771         /* resume enabled intr since hw reset */
2772         ixgbe_enable_intr(dev);
2773         ixgbe_l2_tunnel_conf(dev);
2774         ixgbe_filter_restore(dev);
2775
2776         if (tm_conf->root && !tm_conf->committed)
2777                 PMD_DRV_LOG(WARNING,
2778                             "please call hierarchy_commit() "
2779                             "before starting the port");
2780
2781         /*
2782          * Update link status right before return, because it may
2783          * start link configuration process in a separate thread.
2784          */
2785         ixgbe_dev_link_update(dev, 0);
2786
2787         return 0;
2788
2789 error:
2790         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2791         ixgbe_dev_clear_queues(dev);
2792         return -EIO;
2793 }
2794
2795 /*
2796  * Stop device: disable rx and tx functions to allow for reconfiguring.
2797  */
2798 static void
2799 ixgbe_dev_stop(struct rte_eth_dev *dev)
2800 {
2801         struct rte_eth_link link;
2802         struct ixgbe_adapter *adapter =
2803                 (struct ixgbe_adapter *)dev->data->dev_private;
2804         struct ixgbe_hw *hw =
2805                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806         struct ixgbe_vf_info *vfinfo =
2807                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2808         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2809         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2810         int vf;
2811         struct ixgbe_tm_conf *tm_conf =
2812                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2813
2814         PMD_INIT_FUNC_TRACE();
2815
2816         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2817
2818         /* disable interrupts */
2819         ixgbe_disable_intr(hw);
2820
2821         /* reset the NIC */
2822         ixgbe_pf_reset_hw(hw);
2823         hw->adapter_stopped = 0;
2824
2825         /* stop adapter */
2826         ixgbe_stop_adapter(hw);
2827
2828         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2829                 vfinfo[vf].clear_to_send = false;
2830
2831         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2832                 /* Turn off the copper */
2833                 ixgbe_set_phy_power(hw, false);
2834         } else {
2835                 /* Turn off the laser */
2836                 ixgbe_disable_tx_laser(hw);
2837         }
2838
2839         ixgbe_dev_clear_queues(dev);
2840
2841         /* Clear stored conf */
2842         dev->data->scattered_rx = 0;
2843         dev->data->lro = 0;
2844
2845         /* Clear recorded link status */
2846         memset(&link, 0, sizeof(link));
2847         rte_eth_linkstatus_set(dev, &link);
2848
2849         if (!rte_intr_allow_others(intr_handle))
2850                 /* resume to the default handler */
2851                 rte_intr_callback_register(intr_handle,
2852                                            ixgbe_dev_interrupt_handler,
2853                                            (void *)dev);
2854
2855         /* Clean datapath event and queue/vec mapping */
2856         rte_intr_efd_disable(intr_handle);
2857         if (intr_handle->intr_vec != NULL) {
2858                 rte_free(intr_handle->intr_vec);
2859                 intr_handle->intr_vec = NULL;
2860         }
2861
2862         /* reset hierarchy commit */
2863         tm_conf->committed = false;
2864
2865         adapter->rss_reta_updated = 0;
2866 }
2867
2868 /*
2869  * Set device link up: enable tx.
2870  */
2871 static int
2872 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2873 {
2874         struct ixgbe_hw *hw =
2875                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         if (hw->mac.type == ixgbe_mac_82599EB) {
2877 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2878                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2879                         /* Not suported in bypass mode */
2880                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2881                                      "by device id 0x%x", hw->device_id);
2882                         return -ENOTSUP;
2883                 }
2884 #endif
2885         }
2886
2887         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2888                 /* Turn on the copper */
2889                 ixgbe_set_phy_power(hw, true);
2890         } else {
2891                 /* Turn on the laser */
2892                 ixgbe_enable_tx_laser(hw);
2893         }
2894
2895         return 0;
2896 }
2897
2898 /*
2899  * Set device link down: disable tx.
2900  */
2901 static int
2902 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2903 {
2904         struct ixgbe_hw *hw =
2905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2906         if (hw->mac.type == ixgbe_mac_82599EB) {
2907 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2908                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2909                         /* Not suported in bypass mode */
2910                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2911                                      "by device id 0x%x", hw->device_id);
2912                         return -ENOTSUP;
2913                 }
2914 #endif
2915         }
2916
2917         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2918                 /* Turn off the copper */
2919                 ixgbe_set_phy_power(hw, false);
2920         } else {
2921                 /* Turn off the laser */
2922                 ixgbe_disable_tx_laser(hw);
2923         }
2924
2925         return 0;
2926 }
2927
2928 /*
2929  * Reset and stop device.
2930  */
2931 static void
2932 ixgbe_dev_close(struct rte_eth_dev *dev)
2933 {
2934         struct ixgbe_hw *hw =
2935                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936
2937         PMD_INIT_FUNC_TRACE();
2938
2939         ixgbe_pf_reset_hw(hw);
2940
2941         ixgbe_dev_stop(dev);
2942         hw->adapter_stopped = 1;
2943
2944         ixgbe_dev_free_queues(dev);
2945
2946         ixgbe_disable_pcie_master(hw);
2947
2948         /* reprogram the RAR[0] in case user changed it. */
2949         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2950 }
2951
2952 /*
2953  * Reset PF device.
2954  */
2955 static int
2956 ixgbe_dev_reset(struct rte_eth_dev *dev)
2957 {
2958         int ret;
2959
2960         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2961          * its VF to make them align with it. The detailed notification
2962          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2963          * To avoid unexpected behavior in VF, currently reset of PF with
2964          * SR-IOV activation is not supported. It might be supported later.
2965          */
2966         if (dev->data->sriov.active)
2967                 return -ENOTSUP;
2968
2969         ret = eth_ixgbe_dev_uninit(dev);
2970         if (ret)
2971                 return ret;
2972
2973         ret = eth_ixgbe_dev_init(dev, NULL);
2974
2975         return ret;
2976 }
2977
2978 static void
2979 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2980                            struct ixgbe_hw_stats *hw_stats,
2981                            struct ixgbe_macsec_stats *macsec_stats,
2982                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2983                            uint64_t *total_qprc, uint64_t *total_qprdc)
2984 {
2985         uint32_t bprc, lxon, lxoff, total;
2986         uint32_t delta_gprc = 0;
2987         unsigned i;
2988         /* Workaround for RX byte count not including CRC bytes when CRC
2989          * strip is enabled. CRC bytes are removed from counters when crc_strip
2990          * is disabled.
2991          */
2992         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2993                         IXGBE_HLREG0_RXCRCSTRP);
2994
2995         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2996         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2997         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2998         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2999
3000         for (i = 0; i < 8; i++) {
3001                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3002
3003                 /* global total per queue */
3004                 hw_stats->mpc[i] += mp;
3005                 /* Running comprehensive total for stats display */
3006                 *total_missed_rx += hw_stats->mpc[i];
3007                 if (hw->mac.type == ixgbe_mac_82598EB) {
3008                         hw_stats->rnbc[i] +=
3009                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3010                         hw_stats->pxonrxc[i] +=
3011                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3012                         hw_stats->pxoffrxc[i] +=
3013                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3014                 } else {
3015                         hw_stats->pxonrxc[i] +=
3016                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3017                         hw_stats->pxoffrxc[i] +=
3018                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3019                         hw_stats->pxon2offc[i] +=
3020                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3021                 }
3022                 hw_stats->pxontxc[i] +=
3023                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3024                 hw_stats->pxofftxc[i] +=
3025                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3026         }
3027         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3028                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3029                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3030                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3031
3032                 delta_gprc += delta_qprc;
3033
3034                 hw_stats->qprc[i] += delta_qprc;
3035                 hw_stats->qptc[i] += delta_qptc;
3036
3037                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3038                 hw_stats->qbrc[i] +=
3039                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3040                 if (crc_strip == 0)
3041                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3042
3043                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3044                 hw_stats->qbtc[i] +=
3045                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3046
3047                 hw_stats->qprdc[i] += delta_qprdc;
3048                 *total_qprdc += hw_stats->qprdc[i];
3049
3050                 *total_qprc += hw_stats->qprc[i];
3051                 *total_qbrc += hw_stats->qbrc[i];
3052         }
3053         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3054         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3055         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3056
3057         /*
3058          * An errata states that gprc actually counts good + missed packets:
3059          * Workaround to set gprc to summated queue packet receives
3060          */
3061         hw_stats->gprc = *total_qprc;
3062
3063         if (hw->mac.type != ixgbe_mac_82598EB) {
3064                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3065                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3066                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3067                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3068                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3069                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3070                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3071                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3072         } else {
3073                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3074                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3075                 /* 82598 only has a counter in the high register */
3076                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3077                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3078                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3079         }
3080         uint64_t old_tpr = hw_stats->tpr;
3081
3082         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3083         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3084
3085         if (crc_strip == 0)
3086                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3087
3088         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3089         hw_stats->gptc += delta_gptc;
3090         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3091         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3092
3093         /*
3094          * Workaround: mprc hardware is incorrectly counting
3095          * broadcasts, so for now we subtract those.
3096          */
3097         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3098         hw_stats->bprc += bprc;
3099         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3100         if (hw->mac.type == ixgbe_mac_82598EB)
3101                 hw_stats->mprc -= bprc;
3102
3103         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3104         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3105         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3106         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3107         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3108         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3109
3110         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3111         hw_stats->lxontxc += lxon;
3112         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3113         hw_stats->lxofftxc += lxoff;
3114         total = lxon + lxoff;
3115
3116         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3117         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3118         hw_stats->gptc -= total;
3119         hw_stats->mptc -= total;
3120         hw_stats->ptc64 -= total;
3121         hw_stats->gotc -= total * ETHER_MIN_LEN;
3122
3123         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3124         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3125         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3126         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3127         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3128         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3129         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3130         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3131         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3132         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3133         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3134         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3135         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3136         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3137         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3138         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3139         /* Only read FCOE on 82599 */
3140         if (hw->mac.type != ixgbe_mac_82598EB) {
3141                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3142                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3143                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3144                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3145                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3146         }
3147
3148         /* Flow Director Stats registers */
3149         if (hw->mac.type != ixgbe_mac_82598EB) {
3150                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3151                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3152                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3153                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3154                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3155                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3156                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3157                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3158                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3159                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3160         }
3161         /* MACsec Stats registers */
3162         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3163         macsec_stats->out_pkts_encrypted +=
3164                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3165         macsec_stats->out_pkts_protected +=
3166                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3167         macsec_stats->out_octets_encrypted +=
3168                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3169         macsec_stats->out_octets_protected +=
3170                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3171         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3172         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3173         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3174         macsec_stats->in_pkts_unknownsci +=
3175                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3176         macsec_stats->in_octets_decrypted +=
3177                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3178         macsec_stats->in_octets_validated +=
3179                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3180         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3181         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3182         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3183         for (i = 0; i < 2; i++) {
3184                 macsec_stats->in_pkts_ok +=
3185                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3186                 macsec_stats->in_pkts_invalid +=
3187                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3188                 macsec_stats->in_pkts_notvalid +=
3189                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3190         }
3191         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3192         macsec_stats->in_pkts_notusingsa +=
3193                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3194 }
3195
3196 /*
3197  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3198  */
3199 static int
3200 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3201 {
3202         struct ixgbe_hw *hw =
3203                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3204         struct ixgbe_hw_stats *hw_stats =
3205                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3206         struct ixgbe_macsec_stats *macsec_stats =
3207                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3208                                 dev->data->dev_private);
3209         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3210         unsigned i;
3211
3212         total_missed_rx = 0;
3213         total_qbrc = 0;
3214         total_qprc = 0;
3215         total_qprdc = 0;
3216
3217         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3218                         &total_qbrc, &total_qprc, &total_qprdc);
3219
3220         if (stats == NULL)
3221                 return -EINVAL;
3222
3223         /* Fill out the rte_eth_stats statistics structure */
3224         stats->ipackets = total_qprc;
3225         stats->ibytes = total_qbrc;
3226         stats->opackets = hw_stats->gptc;
3227         stats->obytes = hw_stats->gotc;
3228
3229         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3230                 stats->q_ipackets[i] = hw_stats->qprc[i];
3231                 stats->q_opackets[i] = hw_stats->qptc[i];
3232                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3233                 stats->q_obytes[i] = hw_stats->qbtc[i];
3234                 stats->q_errors[i] = hw_stats->qprdc[i];
3235         }
3236
3237         /* Rx Errors */
3238         stats->imissed  = total_missed_rx;
3239         stats->ierrors  = hw_stats->crcerrs +
3240                           hw_stats->mspdc +
3241                           hw_stats->rlec +
3242                           hw_stats->ruc +
3243                           hw_stats->roc +
3244                           hw_stats->illerrc +
3245                           hw_stats->errbc +
3246                           hw_stats->rfc +
3247                           hw_stats->fccrc +
3248                           hw_stats->fclast;
3249
3250         /* Tx Errors */
3251         stats->oerrors  = 0;
3252         return 0;
3253 }
3254
3255 static void
3256 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3257 {
3258         struct ixgbe_hw_stats *stats =
3259                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3260
3261         /* HW registers are cleared on read */
3262         ixgbe_dev_stats_get(dev, NULL);
3263
3264         /* Reset software totals */
3265         memset(stats, 0, sizeof(*stats));
3266 }
3267
3268 /* This function calculates the number of xstats based on the current config */
3269 static unsigned
3270 ixgbe_xstats_calc_num(void) {
3271         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3272                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3273                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3274 }
3275
3276 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3277         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3278 {
3279         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3280         unsigned stat, i, count;
3281
3282         if (xstats_names != NULL) {
3283                 count = 0;
3284
3285                 /* Note: limit >= cnt_stats checked upstream
3286                  * in rte_eth_xstats_names()
3287                  */
3288
3289                 /* Extended stats from ixgbe_hw_stats */
3290                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3291                         snprintf(xstats_names[count].name,
3292                                 sizeof(xstats_names[count].name),
3293                                 "%s",
3294                                 rte_ixgbe_stats_strings[i].name);
3295                         count++;
3296                 }
3297
3298                 /* MACsec Stats */
3299                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3300                         snprintf(xstats_names[count].name,
3301                                 sizeof(xstats_names[count].name),
3302                                 "%s",
3303                                 rte_ixgbe_macsec_strings[i].name);
3304                         count++;
3305                 }
3306
3307                 /* RX Priority Stats */
3308                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3309                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3310                                 snprintf(xstats_names[count].name,
3311                                         sizeof(xstats_names[count].name),
3312                                         "rx_priority%u_%s", i,
3313                                         rte_ixgbe_rxq_strings[stat].name);
3314                                 count++;
3315                         }
3316                 }
3317
3318                 /* TX Priority Stats */
3319                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3320                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3321                                 snprintf(xstats_names[count].name,
3322                                         sizeof(xstats_names[count].name),
3323                                         "tx_priority%u_%s", i,
3324                                         rte_ixgbe_txq_strings[stat].name);
3325                                 count++;
3326                         }
3327                 }
3328         }
3329         return cnt_stats;
3330 }
3331
3332 static int ixgbe_dev_xstats_get_names_by_id(
3333         struct rte_eth_dev *dev,
3334         struct rte_eth_xstat_name *xstats_names,
3335         const uint64_t *ids,
3336         unsigned int limit)
3337 {
3338         if (!ids) {
3339                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3340                 unsigned int stat, i, count;
3341
3342                 if (xstats_names != NULL) {
3343                         count = 0;
3344
3345                         /* Note: limit >= cnt_stats checked upstream
3346                          * in rte_eth_xstats_names()
3347                          */
3348
3349                         /* Extended stats from ixgbe_hw_stats */
3350                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3351                                 snprintf(xstats_names[count].name,
3352                                         sizeof(xstats_names[count].name),
3353                                         "%s",
3354                                         rte_ixgbe_stats_strings[i].name);
3355                                 count++;
3356                         }
3357
3358                         /* MACsec Stats */
3359                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3360                                 snprintf(xstats_names[count].name,
3361                                         sizeof(xstats_names[count].name),
3362                                         "%s",
3363                                         rte_ixgbe_macsec_strings[i].name);
3364                                 count++;
3365                         }
3366
3367                         /* RX Priority Stats */
3368                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3369                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3370                                         snprintf(xstats_names[count].name,
3371                                             sizeof(xstats_names[count].name),
3372                                             "rx_priority%u_%s", i,
3373                                             rte_ixgbe_rxq_strings[stat].name);
3374                                         count++;
3375                                 }
3376                         }
3377
3378                         /* TX Priority Stats */
3379                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3380                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3381                                         snprintf(xstats_names[count].name,
3382                                             sizeof(xstats_names[count].name),
3383                                             "tx_priority%u_%s", i,
3384                                             rte_ixgbe_txq_strings[stat].name);
3385                                         count++;
3386                                 }
3387                         }
3388                 }
3389                 return cnt_stats;
3390         }
3391
3392         uint16_t i;
3393         uint16_t size = ixgbe_xstats_calc_num();
3394         struct rte_eth_xstat_name xstats_names_copy[size];
3395
3396         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3397                         size);
3398
3399         for (i = 0; i < limit; i++) {
3400                 if (ids[i] >= size) {
3401                         PMD_INIT_LOG(ERR, "id value isn't valid");
3402                         return -1;
3403                 }
3404                 strcpy(xstats_names[i].name,
3405                                 xstats_names_copy[ids[i]].name);
3406         }
3407         return limit;
3408 }
3409
3410 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3411         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3412 {
3413         unsigned i;
3414
3415         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3416                 return -ENOMEM;
3417
3418         if (xstats_names != NULL)
3419                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3420                         snprintf(xstats_names[i].name,
3421                                 sizeof(xstats_names[i].name),
3422                                 "%s", rte_ixgbevf_stats_strings[i].name);
3423         return IXGBEVF_NB_XSTATS;
3424 }
3425
3426 static int
3427 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3428                                          unsigned n)
3429 {
3430         struct ixgbe_hw *hw =
3431                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3432         struct ixgbe_hw_stats *hw_stats =
3433                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3434         struct ixgbe_macsec_stats *macsec_stats =
3435                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3436                                 dev->data->dev_private);
3437         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3438         unsigned i, stat, count = 0;
3439
3440         count = ixgbe_xstats_calc_num();
3441
3442         if (n < count)
3443                 return count;
3444
3445         total_missed_rx = 0;
3446         total_qbrc = 0;
3447         total_qprc = 0;
3448         total_qprdc = 0;
3449
3450         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3451                         &total_qbrc, &total_qprc, &total_qprdc);
3452
3453         /* If this is a reset xstats is NULL, and we have cleared the
3454          * registers by reading them.
3455          */
3456         if (!xstats)
3457                 return 0;
3458
3459         /* Extended stats from ixgbe_hw_stats */
3460         count = 0;
3461         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3462                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3463                                 rte_ixgbe_stats_strings[i].offset);
3464                 xstats[count].id = count;
3465                 count++;
3466         }
3467
3468         /* MACsec Stats */
3469         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3470                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3471                                 rte_ixgbe_macsec_strings[i].offset);
3472                 xstats[count].id = count;
3473                 count++;
3474         }
3475
3476         /* RX Priority Stats */
3477         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3478                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3479                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3480                                         rte_ixgbe_rxq_strings[stat].offset +
3481                                         (sizeof(uint64_t) * i));
3482                         xstats[count].id = count;
3483                         count++;
3484                 }
3485         }
3486
3487         /* TX Priority Stats */
3488         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3489                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3490                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3491                                         rte_ixgbe_txq_strings[stat].offset +
3492                                         (sizeof(uint64_t) * i));
3493                         xstats[count].id = count;
3494                         count++;
3495                 }
3496         }
3497         return count;
3498 }
3499
3500 static int
3501 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3502                 uint64_t *values, unsigned int n)
3503 {
3504         if (!ids) {
3505                 struct ixgbe_hw *hw =
3506                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3507                 struct ixgbe_hw_stats *hw_stats =
3508                                 IXGBE_DEV_PRIVATE_TO_STATS(
3509                                                 dev->data->dev_private);
3510                 struct ixgbe_macsec_stats *macsec_stats =
3511                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3512                                         dev->data->dev_private);
3513                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3514                 unsigned int i, stat, count = 0;
3515
3516                 count = ixgbe_xstats_calc_num();
3517
3518                 if (!ids && n < count)
3519                         return count;
3520
3521                 total_missed_rx = 0;
3522                 total_qbrc = 0;
3523                 total_qprc = 0;
3524                 total_qprdc = 0;
3525
3526                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3527                                 &total_missed_rx, &total_qbrc, &total_qprc,
3528                                 &total_qprdc);
3529
3530                 /* If this is a reset xstats is NULL, and we have cleared the
3531                  * registers by reading them.
3532                  */
3533                 if (!ids && !values)
3534                         return 0;
3535
3536                 /* Extended stats from ixgbe_hw_stats */
3537                 count = 0;
3538                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3539                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3540                                         rte_ixgbe_stats_strings[i].offset);
3541                         count++;
3542                 }
3543
3544                 /* MACsec Stats */
3545                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3546                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3547                                         rte_ixgbe_macsec_strings[i].offset);
3548                         count++;
3549                 }
3550
3551                 /* RX Priority Stats */
3552                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3553                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3554                                 values[count] =
3555                                         *(uint64_t *)(((char *)hw_stats) +
3556                                         rte_ixgbe_rxq_strings[stat].offset +
3557                                         (sizeof(uint64_t) * i));
3558                                 count++;
3559                         }
3560                 }
3561
3562                 /* TX Priority Stats */
3563                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3564                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3565                                 values[count] =
3566                                         *(uint64_t *)(((char *)hw_stats) +
3567                                         rte_ixgbe_txq_strings[stat].offset +
3568                                         (sizeof(uint64_t) * i));
3569                                 count++;
3570                         }
3571                 }
3572                 return count;
3573         }
3574
3575         uint16_t i;
3576         uint16_t size = ixgbe_xstats_calc_num();
3577         uint64_t values_copy[size];
3578
3579         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3580
3581         for (i = 0; i < n; i++) {
3582                 if (ids[i] >= size) {
3583                         PMD_INIT_LOG(ERR, "id value isn't valid");
3584                         return -1;
3585                 }
3586                 values[i] = values_copy[ids[i]];
3587         }
3588         return n;
3589 }
3590
3591 static void
3592 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3593 {
3594         struct ixgbe_hw_stats *stats =
3595                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3596         struct ixgbe_macsec_stats *macsec_stats =
3597                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3598                                 dev->data->dev_private);
3599
3600         unsigned count = ixgbe_xstats_calc_num();
3601
3602         /* HW registers are cleared on read */
3603         ixgbe_dev_xstats_get(dev, NULL, count);
3604
3605         /* Reset software totals */
3606         memset(stats, 0, sizeof(*stats));
3607         memset(macsec_stats, 0, sizeof(*macsec_stats));
3608 }
3609
3610 static void
3611 ixgbevf_update_stats(struct rte_eth_dev *dev)
3612 {
3613         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3614         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3615                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3616
3617         /* Good Rx packet, include VF loopback */
3618         UPDATE_VF_STAT(IXGBE_VFGPRC,
3619             hw_stats->last_vfgprc, hw_stats->vfgprc);
3620
3621         /* Good Rx octets, include VF loopback */
3622         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3623             hw_stats->last_vfgorc, hw_stats->vfgorc);
3624
3625         /* Good Tx packet, include VF loopback */
3626         UPDATE_VF_STAT(IXGBE_VFGPTC,
3627             hw_stats->last_vfgptc, hw_stats->vfgptc);
3628
3629         /* Good Tx octets, include VF loopback */
3630         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3631             hw_stats->last_vfgotc, hw_stats->vfgotc);
3632
3633         /* Rx Multicst Packet */
3634         UPDATE_VF_STAT(IXGBE_VFMPRC,
3635             hw_stats->last_vfmprc, hw_stats->vfmprc);
3636 }
3637
3638 static int
3639 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3640                        unsigned n)
3641 {
3642         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3643                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3644         unsigned i;
3645
3646         if (n < IXGBEVF_NB_XSTATS)
3647                 return IXGBEVF_NB_XSTATS;
3648
3649         ixgbevf_update_stats(dev);
3650
3651         if (!xstats)
3652                 return 0;
3653
3654         /* Extended stats */
3655         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3656                 xstats[i].id = i;
3657                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3658                         rte_ixgbevf_stats_strings[i].offset);
3659         }
3660
3661         return IXGBEVF_NB_XSTATS;
3662 }
3663
3664 static int
3665 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3666 {
3667         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3668                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3669
3670         ixgbevf_update_stats(dev);
3671
3672         if (stats == NULL)
3673                 return -EINVAL;
3674
3675         stats->ipackets = hw_stats->vfgprc;
3676         stats->ibytes = hw_stats->vfgorc;
3677         stats->opackets = hw_stats->vfgptc;
3678         stats->obytes = hw_stats->vfgotc;
3679         return 0;
3680 }
3681
3682 static void
3683 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3684 {
3685         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3686                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3687
3688         /* Sync HW register to the last stats */
3689         ixgbevf_dev_stats_get(dev, NULL);
3690
3691         /* reset HW current stats*/
3692         hw_stats->vfgprc = 0;
3693         hw_stats->vfgorc = 0;
3694         hw_stats->vfgptc = 0;
3695         hw_stats->vfgotc = 0;
3696 }
3697
3698 static int
3699 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3700 {
3701         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3702         u16 eeprom_verh, eeprom_verl;
3703         u32 etrack_id;
3704         int ret;
3705
3706         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3707         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3708
3709         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3710         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3711
3712         ret += 1; /* add the size of '\0' */
3713         if (fw_size < (u32)ret)
3714                 return ret;
3715         else
3716                 return 0;
3717 }
3718
3719 static void
3720 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3721 {
3722         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3723         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3724         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3725
3726         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3727         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3728         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3729                 /*
3730                  * When DCB/VT is off, maximum number of queues changes,
3731                  * except for 82598EB, which remains constant.
3732                  */
3733                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3734                                 hw->mac.type != ixgbe_mac_82598EB)
3735                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3736         }
3737         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3738         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3739         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3740         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3741         dev_info->max_vfs = pci_dev->max_vfs;
3742         if (hw->mac.type == ixgbe_mac_82598EB)
3743                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3744         else
3745                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3746         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3747         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3748         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3749                                      dev_info->rx_queue_offload_capa);
3750         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3751         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3752
3753         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3754                 .rx_thresh = {
3755                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3756                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3757                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3758                 },
3759                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3760                 .rx_drop_en = 0,
3761                 .offloads = 0,
3762         };
3763
3764         dev_info->default_txconf = (struct rte_eth_txconf) {
3765                 .tx_thresh = {
3766                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3767                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3768                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3769                 },
3770                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3771                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3772                 .offloads = 0,
3773         };
3774
3775         dev_info->rx_desc_lim = rx_desc_lim;
3776         dev_info->tx_desc_lim = tx_desc_lim;
3777
3778         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3779         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3780         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3781
3782         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3783         if (hw->mac.type == ixgbe_mac_X540 ||
3784             hw->mac.type == ixgbe_mac_X540_vf ||
3785             hw->mac.type == ixgbe_mac_X550 ||
3786             hw->mac.type == ixgbe_mac_X550_vf) {
3787                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3788         }
3789         if (hw->mac.type == ixgbe_mac_X550) {
3790                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3791                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3792         }
3793
3794         /* Driver-preferred Rx/Tx parameters */
3795         dev_info->default_rxportconf.burst_size = 32;
3796         dev_info->default_txportconf.burst_size = 32;
3797         dev_info->default_rxportconf.nb_queues = 1;
3798         dev_info->default_txportconf.nb_queues = 1;
3799         dev_info->default_rxportconf.ring_size = 256;
3800         dev_info->default_txportconf.ring_size = 256;
3801 }
3802
3803 static const uint32_t *
3804 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3805 {
3806         static const uint32_t ptypes[] = {
3807                 /* For non-vec functions,
3808                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3809                  * for vec functions,
3810                  * refers to _recv_raw_pkts_vec().
3811                  */
3812                 RTE_PTYPE_L2_ETHER,
3813                 RTE_PTYPE_L3_IPV4,
3814                 RTE_PTYPE_L3_IPV4_EXT,
3815                 RTE_PTYPE_L3_IPV6,
3816                 RTE_PTYPE_L3_IPV6_EXT,
3817                 RTE_PTYPE_L4_SCTP,
3818                 RTE_PTYPE_L4_TCP,
3819                 RTE_PTYPE_L4_UDP,
3820                 RTE_PTYPE_TUNNEL_IP,
3821                 RTE_PTYPE_INNER_L3_IPV6,
3822                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3823                 RTE_PTYPE_INNER_L4_TCP,
3824                 RTE_PTYPE_INNER_L4_UDP,
3825                 RTE_PTYPE_UNKNOWN
3826         };
3827
3828         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3829             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3830             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3831             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3832                 return ptypes;
3833
3834 #if defined(RTE_ARCH_X86)
3835         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3836             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3837                 return ptypes;
3838 #endif
3839         return NULL;
3840 }
3841
3842 static void
3843 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3844                      struct rte_eth_dev_info *dev_info)
3845 {
3846         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3847         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3848
3849         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3850         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3851         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3852         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3853         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3854         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3855         dev_info->max_vfs = pci_dev->max_vfs;
3856         if (hw->mac.type == ixgbe_mac_82598EB)
3857                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3858         else
3859                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3860         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3861         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3862                                      dev_info->rx_queue_offload_capa);
3863         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3864         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3865
3866         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3867                 .rx_thresh = {
3868                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3869                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3870                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3871                 },
3872                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3873                 .rx_drop_en = 0,
3874                 .offloads = 0,
3875         };
3876
3877         dev_info->default_txconf = (struct rte_eth_txconf) {
3878                 .tx_thresh = {
3879                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3880                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3881                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3882                 },
3883                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3884                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3885                 .offloads = 0,
3886         };
3887
3888         dev_info->rx_desc_lim = rx_desc_lim;
3889         dev_info->tx_desc_lim = tx_desc_lim;
3890 }
3891
3892 static int
3893 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3894                    int *link_up, int wait_to_complete)
3895 {
3896         struct ixgbe_mbx_info *mbx = &hw->mbx;
3897         struct ixgbe_mac_info *mac = &hw->mac;
3898         uint32_t links_reg, in_msg;
3899         int ret_val = 0;
3900
3901         /* If we were hit with a reset drop the link */
3902         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3903                 mac->get_link_status = true;
3904
3905         if (!mac->get_link_status)
3906                 goto out;
3907
3908         /* if link status is down no point in checking to see if pf is up */
3909         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3910         if (!(links_reg & IXGBE_LINKS_UP))
3911                 goto out;
3912
3913         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3914          * before the link status is correct
3915          */
3916         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3917                 int i;
3918
3919                 for (i = 0; i < 5; i++) {
3920                         rte_delay_us(100);
3921                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3922
3923                         if (!(links_reg & IXGBE_LINKS_UP))
3924                                 goto out;
3925                 }
3926         }
3927
3928         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3929         case IXGBE_LINKS_SPEED_10G_82599:
3930                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3931                 if (hw->mac.type >= ixgbe_mac_X550) {
3932                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3933                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3934                 }
3935                 break;
3936         case IXGBE_LINKS_SPEED_1G_82599:
3937                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3938                 break;
3939         case IXGBE_LINKS_SPEED_100_82599:
3940                 *speed = IXGBE_LINK_SPEED_100_FULL;
3941                 if (hw->mac.type == ixgbe_mac_X550) {
3942                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3943                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3944                 }
3945                 break;
3946         case IXGBE_LINKS_SPEED_10_X550EM_A:
3947                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3948                 /* Since Reserved in older MAC's */
3949                 if (hw->mac.type >= ixgbe_mac_X550)
3950                         *speed = IXGBE_LINK_SPEED_10_FULL;
3951                 break;
3952         default:
3953                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3954         }
3955
3956         /* if the read failed it could just be a mailbox collision, best wait
3957          * until we are called again and don't report an error
3958          */
3959         if (mbx->ops.read(hw, &in_msg, 1, 0))
3960                 goto out;
3961
3962         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3963                 /* msg is not CTS and is NACK we must have lost CTS status */
3964                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3965                         mac->get_link_status = false;
3966                 goto out;
3967         }
3968
3969         /* the pf is talking, if we timed out in the past we reinit */
3970         if (!mbx->timeout) {
3971                 ret_val = -1;
3972                 goto out;
3973         }
3974
3975         /* if we passed all the tests above then the link is up and we no
3976          * longer need to check for link
3977          */
3978         mac->get_link_status = false;
3979
3980 out:
3981         *link_up = !mac->get_link_status;
3982         return ret_val;
3983 }
3984
3985 static void
3986 ixgbe_dev_setup_link_alarm_handler(void *param)
3987 {
3988         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3990         struct ixgbe_interrupt *intr =
3991                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3992         u32 speed;
3993         bool autoneg = false;
3994
3995         speed = hw->phy.autoneg_advertised;
3996         if (!speed)
3997                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3998
3999         ixgbe_setup_link(hw, speed, true);
4000
4001         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4002 }
4003
4004 /* return 0 means link status changed, -1 means not changed */
4005 int
4006 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4007                             int wait_to_complete, int vf)
4008 {
4009         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4010         struct rte_eth_link link;
4011         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4012         struct ixgbe_interrupt *intr =
4013                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4014         int link_up;
4015         int diag;
4016         int wait = 1;
4017
4018         memset(&link, 0, sizeof(link));
4019         link.link_status = ETH_LINK_DOWN;
4020         link.link_speed = ETH_SPEED_NUM_NONE;
4021         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4022         link.link_autoneg = ETH_LINK_AUTONEG;
4023
4024         hw->mac.get_link_status = true;
4025
4026         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4027                 return rte_eth_linkstatus_set(dev, &link);
4028
4029         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4030         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4031                 wait = 0;
4032
4033         if (vf)
4034                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4035         else
4036                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4037
4038         if (diag != 0) {
4039                 link.link_speed = ETH_SPEED_NUM_100M;
4040                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4041                 return rte_eth_linkstatus_set(dev, &link);
4042         }
4043
4044         if (link_up == 0) {
4045                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4046                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4047                         rte_eal_alarm_set(10,
4048                                 ixgbe_dev_setup_link_alarm_handler, dev);
4049                 }
4050                 return rte_eth_linkstatus_set(dev, &link);
4051         }
4052
4053         link.link_status = ETH_LINK_UP;
4054         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4055
4056         switch (link_speed) {
4057         default:
4058         case IXGBE_LINK_SPEED_UNKNOWN:
4059                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4060                 link.link_speed = ETH_SPEED_NUM_100M;
4061                 break;
4062
4063         case IXGBE_LINK_SPEED_100_FULL:
4064                 link.link_speed = ETH_SPEED_NUM_100M;
4065                 break;
4066
4067         case IXGBE_LINK_SPEED_1GB_FULL:
4068                 link.link_speed = ETH_SPEED_NUM_1G;
4069                 break;
4070
4071         case IXGBE_LINK_SPEED_2_5GB_FULL:
4072                 link.link_speed = ETH_SPEED_NUM_2_5G;
4073                 break;
4074
4075         case IXGBE_LINK_SPEED_5GB_FULL:
4076                 link.link_speed = ETH_SPEED_NUM_5G;
4077                 break;
4078
4079         case IXGBE_LINK_SPEED_10GB_FULL:
4080                 link.link_speed = ETH_SPEED_NUM_10G;
4081                 break;
4082         }
4083
4084         return rte_eth_linkstatus_set(dev, &link);
4085 }
4086
4087 static int
4088 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4089 {
4090         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4091 }
4092
4093 static int
4094 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4095 {
4096         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4097 }
4098
4099 static void
4100 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4101 {
4102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4103         uint32_t fctrl;
4104
4105         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4106         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4107         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4108 }
4109
4110 static void
4111 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4112 {
4113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114         uint32_t fctrl;
4115
4116         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4117         fctrl &= (~IXGBE_FCTRL_UPE);
4118         if (dev->data->all_multicast == 1)
4119                 fctrl |= IXGBE_FCTRL_MPE;
4120         else
4121                 fctrl &= (~IXGBE_FCTRL_MPE);
4122         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4123 }
4124
4125 static void
4126 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4127 {
4128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4129         uint32_t fctrl;
4130
4131         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4132         fctrl |= IXGBE_FCTRL_MPE;
4133         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4134 }
4135
4136 static void
4137 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4138 {
4139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4140         uint32_t fctrl;
4141
4142         if (dev->data->promiscuous == 1)
4143                 return; /* must remain in all_multicast mode */
4144
4145         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4146         fctrl &= (~IXGBE_FCTRL_MPE);
4147         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4148 }
4149
4150 /**
4151  * It clears the interrupt causes and enables the interrupt.
4152  * It will be called once only during nic initialized.
4153  *
4154  * @param dev
4155  *  Pointer to struct rte_eth_dev.
4156  * @param on
4157  *  Enable or Disable.
4158  *
4159  * @return
4160  *  - On success, zero.
4161  *  - On failure, a negative value.
4162  */
4163 static int
4164 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4165 {
4166         struct ixgbe_interrupt *intr =
4167                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4168
4169         ixgbe_dev_link_status_print(dev);
4170         if (on)
4171                 intr->mask |= IXGBE_EICR_LSC;
4172         else
4173                 intr->mask &= ~IXGBE_EICR_LSC;
4174
4175         return 0;
4176 }
4177
4178 /**
4179  * It clears the interrupt causes and enables the interrupt.
4180  * It will be called once only during nic initialized.
4181  *
4182  * @param dev
4183  *  Pointer to struct rte_eth_dev.
4184  *
4185  * @return
4186  *  - On success, zero.
4187  *  - On failure, a negative value.
4188  */
4189 static int
4190 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4191 {
4192         struct ixgbe_interrupt *intr =
4193                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4194
4195         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4196
4197         return 0;
4198 }
4199
4200 /**
4201  * It clears the interrupt causes and enables the interrupt.
4202  * It will be called once only during nic initialized.
4203  *
4204  * @param dev
4205  *  Pointer to struct rte_eth_dev.
4206  *
4207  * @return
4208  *  - On success, zero.
4209  *  - On failure, a negative value.
4210  */
4211 static int
4212 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4213 {
4214         struct ixgbe_interrupt *intr =
4215                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4216
4217         intr->mask |= IXGBE_EICR_LINKSEC;
4218
4219         return 0;
4220 }
4221
4222 /*
4223  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4224  *
4225  * @param dev
4226  *  Pointer to struct rte_eth_dev.
4227  *
4228  * @return
4229  *  - On success, zero.
4230  *  - On failure, a negative value.
4231  */
4232 static int
4233 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4234 {
4235         uint32_t eicr;
4236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4237         struct ixgbe_interrupt *intr =
4238                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4239
4240         /* clear all cause mask */
4241         ixgbe_disable_intr(hw);
4242
4243         /* read-on-clear nic registers here */
4244         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4245         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4246
4247         intr->flags = 0;
4248
4249         /* set flag for async link update */
4250         if (eicr & IXGBE_EICR_LSC)
4251                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4252
4253         if (eicr & IXGBE_EICR_MAILBOX)
4254                 intr->flags |= IXGBE_FLAG_MAILBOX;
4255
4256         if (eicr & IXGBE_EICR_LINKSEC)
4257                 intr->flags |= IXGBE_FLAG_MACSEC;
4258
4259         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4260             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4261             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4262                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4263
4264         return 0;
4265 }
4266
4267 /**
4268  * It gets and then prints the link status.
4269  *
4270  * @param dev
4271  *  Pointer to struct rte_eth_dev.
4272  *
4273  * @return
4274  *  - On success, zero.
4275  *  - On failure, a negative value.
4276  */
4277 static void
4278 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4279 {
4280         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4281         struct rte_eth_link link;
4282
4283         rte_eth_linkstatus_get(dev, &link);
4284
4285         if (link.link_status) {
4286                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4287                                         (int)(dev->data->port_id),
4288                                         (unsigned)link.link_speed,
4289                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4290                                         "full-duplex" : "half-duplex");
4291         } else {
4292                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4293                                 (int)(dev->data->port_id));
4294         }
4295         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4296                                 pci_dev->addr.domain,
4297                                 pci_dev->addr.bus,
4298                                 pci_dev->addr.devid,
4299                                 pci_dev->addr.function);
4300 }
4301
4302 /*
4303  * It executes link_update after knowing an interrupt occurred.
4304  *
4305  * @param dev
4306  *  Pointer to struct rte_eth_dev.
4307  *
4308  * @return
4309  *  - On success, zero.
4310  *  - On failure, a negative value.
4311  */
4312 static int
4313 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4314 {
4315         struct ixgbe_interrupt *intr =
4316                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4317         int64_t timeout;
4318         struct ixgbe_hw *hw =
4319                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4320
4321         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4322
4323         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4324                 ixgbe_pf_mbx_process(dev);
4325                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4326         }
4327
4328         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4329                 ixgbe_handle_lasi(hw);
4330                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4331         }
4332
4333         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4334                 struct rte_eth_link link;
4335
4336                 /* get the link status before link update, for predicting later */
4337                 rte_eth_linkstatus_get(dev, &link);
4338
4339                 ixgbe_dev_link_update(dev, 0);
4340
4341                 /* likely to up */
4342                 if (!link.link_status)
4343                         /* handle it 1 sec later, wait it being stable */
4344                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4345                 /* likely to down */
4346                 else
4347                         /* handle it 4 sec later, wait it being stable */
4348                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4349
4350                 ixgbe_dev_link_status_print(dev);
4351                 if (rte_eal_alarm_set(timeout * 1000,
4352                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4353                         PMD_DRV_LOG(ERR, "Error setting alarm");
4354                 else {
4355                         /* remember original mask */
4356                         intr->mask_original = intr->mask;
4357                         /* only disable lsc interrupt */
4358                         intr->mask &= ~IXGBE_EIMS_LSC;
4359                 }
4360         }
4361
4362         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4363         ixgbe_enable_intr(dev);
4364
4365         return 0;
4366 }
4367
4368 /**
4369  * Interrupt handler which shall be registered for alarm callback for delayed
4370  * handling specific interrupt to wait for the stable nic state. As the
4371  * NIC interrupt state is not stable for ixgbe after link is just down,
4372  * it needs to wait 4 seconds to get the stable status.
4373  *
4374  * @param handle
4375  *  Pointer to interrupt handle.
4376  * @param param
4377  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4378  *
4379  * @return
4380  *  void
4381  */
4382 static void
4383 ixgbe_dev_interrupt_delayed_handler(void *param)
4384 {
4385         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4386         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4387         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4388         struct ixgbe_interrupt *intr =
4389                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4390         struct ixgbe_hw *hw =
4391                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4392         uint32_t eicr;
4393
4394         ixgbe_disable_intr(hw);
4395
4396         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4397         if (eicr & IXGBE_EICR_MAILBOX)
4398                 ixgbe_pf_mbx_process(dev);
4399
4400         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4401                 ixgbe_handle_lasi(hw);
4402                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4403         }
4404
4405         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4406                 ixgbe_dev_link_update(dev, 0);
4407                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4408                 ixgbe_dev_link_status_print(dev);
4409                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4410                                               NULL);
4411         }
4412
4413         if (intr->flags & IXGBE_FLAG_MACSEC) {
4414                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4415                                               NULL);
4416                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4417         }
4418
4419         /* restore original mask */
4420         intr->mask = intr->mask_original;
4421         intr->mask_original = 0;
4422
4423         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4424         ixgbe_enable_intr(dev);
4425         rte_intr_enable(intr_handle);
4426 }
4427
4428 /**
4429  * Interrupt handler triggered by NIC  for handling
4430  * specific interrupt.
4431  *
4432  * @param handle
4433  *  Pointer to interrupt handle.
4434  * @param param
4435  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4436  *
4437  * @return
4438  *  void
4439  */
4440 static void
4441 ixgbe_dev_interrupt_handler(void *param)
4442 {
4443         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4444
4445         ixgbe_dev_interrupt_get_status(dev);
4446         ixgbe_dev_interrupt_action(dev);
4447 }
4448
4449 static int
4450 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4451 {
4452         struct ixgbe_hw *hw;
4453
4454         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4455         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4456 }
4457
4458 static int
4459 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4460 {
4461         struct ixgbe_hw *hw;
4462
4463         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4464         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4465 }
4466
4467 static int
4468 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4469 {
4470         struct ixgbe_hw *hw;
4471         uint32_t mflcn_reg;
4472         uint32_t fccfg_reg;
4473         int rx_pause;
4474         int tx_pause;
4475
4476         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4477
4478         fc_conf->pause_time = hw->fc.pause_time;
4479         fc_conf->high_water = hw->fc.high_water[0];
4480         fc_conf->low_water = hw->fc.low_water[0];
4481         fc_conf->send_xon = hw->fc.send_xon;
4482         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4483
4484         /*
4485          * Return rx_pause status according to actual setting of
4486          * MFLCN register.
4487          */
4488         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4489         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4490                 rx_pause = 1;
4491         else
4492                 rx_pause = 0;
4493
4494         /*
4495          * Return tx_pause status according to actual setting of
4496          * FCCFG register.
4497          */
4498         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4499         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4500                 tx_pause = 1;
4501         else
4502                 tx_pause = 0;
4503
4504         if (rx_pause && tx_pause)
4505                 fc_conf->mode = RTE_FC_FULL;
4506         else if (rx_pause)
4507                 fc_conf->mode = RTE_FC_RX_PAUSE;
4508         else if (tx_pause)
4509                 fc_conf->mode = RTE_FC_TX_PAUSE;
4510         else
4511                 fc_conf->mode = RTE_FC_NONE;
4512
4513         return 0;
4514 }
4515
4516 static int
4517 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4518 {
4519         struct ixgbe_hw *hw;
4520         int err;
4521         uint32_t rx_buf_size;
4522         uint32_t max_high_water;
4523         uint32_t mflcn;
4524         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4525                 ixgbe_fc_none,
4526                 ixgbe_fc_rx_pause,
4527                 ixgbe_fc_tx_pause,
4528                 ixgbe_fc_full
4529         };
4530
4531         PMD_INIT_FUNC_TRACE();
4532
4533         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4534         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4535         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4536
4537         /*
4538          * At least reserve one Ethernet frame for watermark
4539          * high_water/low_water in kilo bytes for ixgbe
4540          */
4541         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4542         if ((fc_conf->high_water > max_high_water) ||
4543                 (fc_conf->high_water < fc_conf->low_water)) {
4544                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4545                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4546                 return -EINVAL;
4547         }
4548
4549         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4550         hw->fc.pause_time     = fc_conf->pause_time;
4551         hw->fc.high_water[0]  = fc_conf->high_water;
4552         hw->fc.low_water[0]   = fc_conf->low_water;
4553         hw->fc.send_xon       = fc_conf->send_xon;
4554         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4555
4556         err = ixgbe_fc_enable(hw);
4557
4558         /* Not negotiated is not an error case */
4559         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4560
4561                 /* check if we want to forward MAC frames - driver doesn't have native
4562                  * capability to do that, so we'll write the registers ourselves */
4563
4564                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4565
4566                 /* set or clear MFLCN.PMCF bit depending on configuration */
4567                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4568                         mflcn |= IXGBE_MFLCN_PMCF;
4569                 else
4570                         mflcn &= ~IXGBE_MFLCN_PMCF;
4571
4572                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4573                 IXGBE_WRITE_FLUSH(hw);
4574
4575                 return 0;
4576         }
4577
4578         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4579         return -EIO;
4580 }
4581
4582 /**
4583  *  ixgbe_pfc_enable_generic - Enable flow control
4584  *  @hw: pointer to hardware structure
4585  *  @tc_num: traffic class number
4586  *  Enable flow control according to the current settings.
4587  */
4588 static int
4589 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4590 {
4591         int ret_val = 0;
4592         uint32_t mflcn_reg, fccfg_reg;
4593         uint32_t reg;
4594         uint32_t fcrtl, fcrth;
4595         uint8_t i;
4596         uint8_t nb_rx_en;
4597
4598         /* Validate the water mark configuration */
4599         if (!hw->fc.pause_time) {
4600                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4601                 goto out;
4602         }
4603
4604         /* Low water mark of zero causes XOFF floods */
4605         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4606                  /* High/Low water can not be 0 */
4607                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4608                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4609                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4610                         goto out;
4611                 }
4612
4613                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4614                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4615                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4616                         goto out;
4617                 }
4618         }
4619         /* Negotiate the fc mode to use */
4620         ixgbe_fc_autoneg(hw);
4621
4622         /* Disable any previous flow control settings */
4623         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4624         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4625
4626         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4627         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4628
4629         switch (hw->fc.current_mode) {
4630         case ixgbe_fc_none:
4631                 /*
4632                  * If the count of enabled RX Priority Flow control >1,
4633                  * and the TX pause can not be disabled
4634                  */
4635                 nb_rx_en = 0;
4636                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4637                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4638                         if (reg & IXGBE_FCRTH_FCEN)
4639                                 nb_rx_en++;
4640                 }
4641                 if (nb_rx_en > 1)
4642                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4643                 break;
4644         case ixgbe_fc_rx_pause:
4645                 /*
4646                  * Rx Flow control is enabled and Tx Flow control is
4647                  * disabled by software override. Since there really
4648                  * isn't a way to advertise that we are capable of RX
4649                  * Pause ONLY, we will advertise that we support both
4650                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4651                  * disable the adapter's ability to send PAUSE frames.
4652                  */
4653                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4654                 /*
4655                  * If the count of enabled RX Priority Flow control >1,
4656                  * and the TX pause can not be disabled
4657                  */
4658                 nb_rx_en = 0;
4659                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4660                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4661                         if (reg & IXGBE_FCRTH_FCEN)
4662                                 nb_rx_en++;
4663                 }
4664                 if (nb_rx_en > 1)
4665                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4666                 break;
4667         case ixgbe_fc_tx_pause:
4668                 /*
4669                  * Tx Flow control is enabled, and Rx Flow control is
4670                  * disabled by software override.
4671                  */
4672                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4673                 break;
4674         case ixgbe_fc_full:
4675                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4676                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4677                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4678                 break;
4679         default:
4680                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4681                 ret_val = IXGBE_ERR_CONFIG;
4682                 goto out;
4683         }
4684
4685         /* Set 802.3x based flow control settings. */
4686         mflcn_reg |= IXGBE_MFLCN_DPF;
4687         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4688         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4689
4690         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4691         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4692                 hw->fc.high_water[tc_num]) {
4693                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4694                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4695                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4696         } else {
4697                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4698                 /*
4699                  * In order to prevent Tx hangs when the internal Tx
4700                  * switch is enabled we must set the high water mark
4701                  * to the maximum FCRTH value.  This allows the Tx
4702                  * switch to function even under heavy Rx workloads.
4703                  */
4704                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4705         }
4706         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4707
4708         /* Configure pause time (2 TCs per register) */
4709         reg = hw->fc.pause_time * 0x00010001;
4710         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4711                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4712
4713         /* Configure flow control refresh threshold value */
4714         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4715
4716 out:
4717         return ret_val;
4718 }
4719
4720 static int
4721 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4722 {
4723         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4725
4726         if (hw->mac.type != ixgbe_mac_82598EB) {
4727                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4728         }
4729         return ret_val;
4730 }
4731
4732 static int
4733 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4734 {
4735         int err;
4736         uint32_t rx_buf_size;
4737         uint32_t max_high_water;
4738         uint8_t tc_num;
4739         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4740         struct ixgbe_hw *hw =
4741                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742         struct ixgbe_dcb_config *dcb_config =
4743                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4744
4745         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4746                 ixgbe_fc_none,
4747                 ixgbe_fc_rx_pause,
4748                 ixgbe_fc_tx_pause,
4749                 ixgbe_fc_full
4750         };
4751
4752         PMD_INIT_FUNC_TRACE();
4753
4754         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4755         tc_num = map[pfc_conf->priority];
4756         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4757         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4758         /*
4759          * At least reserve one Ethernet frame for watermark
4760          * high_water/low_water in kilo bytes for ixgbe
4761          */
4762         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4763         if ((pfc_conf->fc.high_water > max_high_water) ||
4764             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4765                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4766                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4767                 return -EINVAL;
4768         }
4769
4770         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4771         hw->fc.pause_time = pfc_conf->fc.pause_time;
4772         hw->fc.send_xon = pfc_conf->fc.send_xon;
4773         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4774         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4775
4776         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4777
4778         /* Not negotiated is not an error case */
4779         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4780                 return 0;
4781
4782         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4783         return -EIO;
4784 }
4785
4786 static int
4787 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4788                           struct rte_eth_rss_reta_entry64 *reta_conf,
4789                           uint16_t reta_size)
4790 {
4791         uint16_t i, sp_reta_size;
4792         uint8_t j, mask;
4793         uint32_t reta, r;
4794         uint16_t idx, shift;
4795         struct ixgbe_adapter *adapter =
4796                 (struct ixgbe_adapter *)dev->data->dev_private;
4797         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4798         uint32_t reta_reg;
4799
4800         PMD_INIT_FUNC_TRACE();
4801
4802         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4803                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4804                         "NIC.");
4805                 return -ENOTSUP;
4806         }
4807
4808         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4809         if (reta_size != sp_reta_size) {
4810                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4811                         "(%d) doesn't match the number hardware can supported "
4812                         "(%d)", reta_size, sp_reta_size);
4813                 return -EINVAL;
4814         }
4815
4816         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4817                 idx = i / RTE_RETA_GROUP_SIZE;
4818                 shift = i % RTE_RETA_GROUP_SIZE;
4819                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4820                                                 IXGBE_4_BIT_MASK);
4821                 if (!mask)
4822                         continue;
4823                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4824                 if (mask == IXGBE_4_BIT_MASK)
4825                         r = 0;
4826                 else
4827                         r = IXGBE_READ_REG(hw, reta_reg);
4828                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4829                         if (mask & (0x1 << j))
4830                                 reta |= reta_conf[idx].reta[shift + j] <<
4831                                                         (CHAR_BIT * j);
4832                         else
4833                                 reta |= r & (IXGBE_8_BIT_MASK <<
4834                                                 (CHAR_BIT * j));
4835                 }
4836                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4837         }
4838         adapter->rss_reta_updated = 1;
4839
4840         return 0;
4841 }
4842
4843 static int
4844 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4845                          struct rte_eth_rss_reta_entry64 *reta_conf,
4846                          uint16_t reta_size)
4847 {
4848         uint16_t i, sp_reta_size;
4849         uint8_t j, mask;
4850         uint32_t reta;
4851         uint16_t idx, shift;
4852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4853         uint32_t reta_reg;
4854
4855         PMD_INIT_FUNC_TRACE();
4856         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4857         if (reta_size != sp_reta_size) {
4858                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4859                         "(%d) doesn't match the number hardware can supported "
4860                         "(%d)", reta_size, sp_reta_size);
4861                 return -EINVAL;
4862         }
4863
4864         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4865                 idx = i / RTE_RETA_GROUP_SIZE;
4866                 shift = i % RTE_RETA_GROUP_SIZE;
4867                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4868                                                 IXGBE_4_BIT_MASK);
4869                 if (!mask)
4870                         continue;
4871
4872                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4873                 reta = IXGBE_READ_REG(hw, reta_reg);
4874                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4875                         if (mask & (0x1 << j))
4876                                 reta_conf[idx].reta[shift + j] =
4877                                         ((reta >> (CHAR_BIT * j)) &
4878                                                 IXGBE_8_BIT_MASK);
4879                 }
4880         }
4881
4882         return 0;
4883 }
4884
4885 static int
4886 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4887                                 uint32_t index, uint32_t pool)
4888 {
4889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4890         uint32_t enable_addr = 1;
4891
4892         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4893                              pool, enable_addr);
4894 }
4895
4896 static void
4897 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4898 {
4899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4900
4901         ixgbe_clear_rar(hw, index);
4902 }
4903
4904 static int
4905 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4906 {
4907         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4908
4909         ixgbe_remove_rar(dev, 0);
4910         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4911
4912         return 0;
4913 }
4914
4915 static bool
4916 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4917 {
4918         if (strcmp(dev->device->driver->name, drv->driver.name))
4919                 return false;
4920
4921         return true;
4922 }
4923
4924 bool
4925 is_ixgbe_supported(struct rte_eth_dev *dev)
4926 {
4927         return is_device_supported(dev, &rte_ixgbe_pmd);
4928 }
4929
4930 static int
4931 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4932 {
4933         uint32_t hlreg0;
4934         uint32_t maxfrs;
4935         struct ixgbe_hw *hw;
4936         struct rte_eth_dev_info dev_info;
4937         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4938         struct rte_eth_dev_data *dev_data = dev->data;
4939
4940         ixgbe_dev_info_get(dev, &dev_info);
4941
4942         /* check that mtu is within the allowed range */
4943         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4944                 return -EINVAL;
4945
4946         /* If device is started, refuse mtu that requires the support of
4947          * scattered packets when this feature has not been enabled before.
4948          */
4949         if (dev_data->dev_started && !dev_data->scattered_rx &&
4950             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4951              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4952                 PMD_INIT_LOG(ERR, "Stop port first.");
4953                 return -EINVAL;
4954         }
4955
4956         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4957         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4958
4959         /* switch to jumbo mode if needed */
4960         if (frame_size > ETHER_MAX_LEN) {
4961                 dev->data->dev_conf.rxmode.offloads |=
4962                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4963                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4964         } else {
4965                 dev->data->dev_conf.rxmode.offloads &=
4966                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4967                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4968         }
4969         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4970
4971         /* update max frame size */
4972         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4973
4974         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4975         maxfrs &= 0x0000FFFF;
4976         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4977         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4978
4979         return 0;
4980 }
4981
4982 /*
4983  * Virtual Function operations
4984  */
4985 static void
4986 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4987 {
4988         struct ixgbe_interrupt *intr =
4989                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4990         struct ixgbe_hw *hw =
4991                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992
4993         PMD_INIT_FUNC_TRACE();
4994
4995         /* Clear interrupt mask to stop from interrupts being generated */
4996         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4997
4998         IXGBE_WRITE_FLUSH(hw);
4999
5000         /* Clear mask value. */
5001         intr->mask = 0;
5002 }
5003
5004 static void
5005 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5006 {
5007         struct ixgbe_interrupt *intr =
5008                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5009         struct ixgbe_hw *hw =
5010                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5011
5012         PMD_INIT_FUNC_TRACE();
5013
5014         /* VF enable interrupt autoclean */
5015         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5016         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5017         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5018
5019         IXGBE_WRITE_FLUSH(hw);
5020
5021         /* Save IXGBE_VTEIMS value to mask. */
5022         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5023 }
5024
5025 static int
5026 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5027 {
5028         struct rte_eth_conf *conf = &dev->data->dev_conf;
5029         struct ixgbe_adapter *adapter =
5030                         (struct ixgbe_adapter *)dev->data->dev_private;
5031
5032         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5033                      dev->data->port_id);
5034
5035         /*
5036          * VF has no ability to enable/disable HW CRC
5037          * Keep the persistent behavior the same as Host PF
5038          */
5039 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5040         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5041                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5042                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5043         }
5044 #else
5045         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5046                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5047                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5048         }
5049 #endif
5050
5051         /*
5052          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5053          * allocation or vector Rx preconditions we will reset it.
5054          */
5055         adapter->rx_bulk_alloc_allowed = true;
5056         adapter->rx_vec_allowed = true;
5057
5058         return 0;
5059 }
5060
5061 static int
5062 ixgbevf_dev_start(struct rte_eth_dev *dev)
5063 {
5064         struct ixgbe_hw *hw =
5065                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5066         uint32_t intr_vector = 0;
5067         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5068         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5069
5070         int err, mask = 0;
5071
5072         PMD_INIT_FUNC_TRACE();
5073
5074         /* Stop the link setup handler before resetting the HW. */
5075         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5076
5077         err = hw->mac.ops.reset_hw(hw);
5078         if (err) {
5079                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5080                 return err;
5081         }
5082         hw->mac.get_link_status = true;
5083
5084         /* negotiate mailbox API version to use with the PF. */
5085         ixgbevf_negotiate_api(hw);
5086
5087         ixgbevf_dev_tx_init(dev);
5088
5089         /* This can fail when allocating mbufs for descriptor rings */
5090         err = ixgbevf_dev_rx_init(dev);
5091         if (err) {
5092                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5093                 ixgbe_dev_clear_queues(dev);
5094                 return err;
5095         }
5096
5097         /* Set vfta */
5098         ixgbevf_set_vfta_all(dev, 1);
5099
5100         /* Set HW strip */
5101         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5102                 ETH_VLAN_EXTEND_MASK;
5103         err = ixgbevf_vlan_offload_config(dev, mask);
5104         if (err) {
5105                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5106                 ixgbe_dev_clear_queues(dev);
5107                 return err;
5108         }
5109
5110         ixgbevf_dev_rxtx_start(dev);
5111
5112         /* check and configure queue intr-vector mapping */
5113         if (rte_intr_cap_multiple(intr_handle) &&
5114             dev->data->dev_conf.intr_conf.rxq) {
5115                 /* According to datasheet, only vector 0/1/2 can be used,
5116                  * now only one vector is used for Rx queue
5117                  */
5118                 intr_vector = 1;
5119                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5120                         return -1;
5121         }
5122
5123         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5124                 intr_handle->intr_vec =
5125                         rte_zmalloc("intr_vec",
5126                                     dev->data->nb_rx_queues * sizeof(int), 0);
5127                 if (intr_handle->intr_vec == NULL) {
5128                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5129                                      " intr_vec", dev->data->nb_rx_queues);
5130                         return -ENOMEM;
5131                 }
5132         }
5133         ixgbevf_configure_msix(dev);
5134
5135         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5136          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5137          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5138          * is not cleared, it will fail when following rte_intr_enable( ) tries
5139          * to map Rx queue interrupt to other VFIO vectors.
5140          * So clear uio/vfio intr/evevnfd first to avoid failure.
5141          */
5142         rte_intr_disable(intr_handle);
5143
5144         rte_intr_enable(intr_handle);
5145
5146         /* Re-enable interrupt for VF */
5147         ixgbevf_intr_enable(dev);
5148
5149         /*
5150          * Update link status right before return, because it may
5151          * start link configuration process in a separate thread.
5152          */
5153         ixgbevf_dev_link_update(dev, 0);
5154
5155         return 0;
5156 }
5157
5158 static void
5159 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5160 {
5161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5162         struct ixgbe_adapter *adapter =
5163                 (struct ixgbe_adapter *)dev->data->dev_private;
5164         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5165         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5166
5167         PMD_INIT_FUNC_TRACE();
5168
5169         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5170
5171         ixgbevf_intr_disable(dev);
5172
5173         hw->adapter_stopped = 1;
5174         ixgbe_stop_adapter(hw);
5175
5176         /*
5177           * Clear what we set, but we still keep shadow_vfta to
5178           * restore after device starts
5179           */
5180         ixgbevf_set_vfta_all(dev, 0);
5181
5182         /* Clear stored conf */
5183         dev->data->scattered_rx = 0;
5184
5185         ixgbe_dev_clear_queues(dev);
5186
5187         /* Clean datapath event and queue/vec mapping */
5188         rte_intr_efd_disable(intr_handle);
5189         if (intr_handle->intr_vec != NULL) {
5190                 rte_free(intr_handle->intr_vec);
5191                 intr_handle->intr_vec = NULL;
5192         }
5193
5194         adapter->rss_reta_updated = 0;
5195 }
5196
5197 static void
5198 ixgbevf_dev_close(struct rte_eth_dev *dev)
5199 {
5200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201
5202         PMD_INIT_FUNC_TRACE();
5203
5204         ixgbe_reset_hw(hw);
5205
5206         ixgbevf_dev_stop(dev);
5207
5208         ixgbe_dev_free_queues(dev);
5209
5210         /**
5211          * Remove the VF MAC address ro ensure
5212          * that the VF traffic goes to the PF
5213          * after stop, close and detach of the VF
5214          **/
5215         ixgbevf_remove_mac_addr(dev, 0);
5216 }
5217
5218 /*
5219  * Reset VF device
5220  */
5221 static int
5222 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5223 {
5224         int ret;
5225
5226         ret = eth_ixgbevf_dev_uninit(dev);
5227         if (ret)
5228                 return ret;
5229
5230         ret = eth_ixgbevf_dev_init(dev);
5231
5232         return ret;
5233 }
5234
5235 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5236 {
5237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238         struct ixgbe_vfta *shadow_vfta =
5239                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5240         int i = 0, j = 0, vfta = 0, mask = 1;
5241
5242         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5243                 vfta = shadow_vfta->vfta[i];
5244                 if (vfta) {
5245                         mask = 1;
5246                         for (j = 0; j < 32; j++) {
5247                                 if (vfta & mask)
5248                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5249                                                        on, false);
5250                                 mask <<= 1;
5251                         }
5252                 }
5253         }
5254
5255 }
5256
5257 static int
5258 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5259 {
5260         struct ixgbe_hw *hw =
5261                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5262         struct ixgbe_vfta *shadow_vfta =
5263                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5264         uint32_t vid_idx = 0;
5265         uint32_t vid_bit = 0;
5266         int ret = 0;
5267
5268         PMD_INIT_FUNC_TRACE();
5269
5270         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5271         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5272         if (ret) {
5273                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5274                 return ret;
5275         }
5276         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5277         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5278
5279         /* Save what we set and retore it after device reset */
5280         if (on)
5281                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5282         else
5283                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5284
5285         return 0;
5286 }
5287
5288 static void
5289 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5290 {
5291         struct ixgbe_hw *hw =
5292                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5293         uint32_t ctrl;
5294
5295         PMD_INIT_FUNC_TRACE();
5296
5297         if (queue >= hw->mac.max_rx_queues)
5298                 return;
5299
5300         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5301         if (on)
5302                 ctrl |= IXGBE_RXDCTL_VME;
5303         else
5304                 ctrl &= ~IXGBE_RXDCTL_VME;
5305         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5306
5307         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5308 }
5309
5310 static int
5311 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5312 {
5313         struct ixgbe_rx_queue *rxq;
5314         uint16_t i;
5315         int on = 0;
5316
5317         /* VF function only support hw strip feature, others are not support */
5318         if (mask & ETH_VLAN_STRIP_MASK) {
5319                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5320                         rxq = dev->data->rx_queues[i];
5321                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5322                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5323                 }
5324         }
5325
5326         return 0;
5327 }
5328
5329 static int
5330 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5331 {
5332         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5333
5334         ixgbevf_vlan_offload_config(dev, mask);
5335
5336         return 0;
5337 }
5338
5339 int
5340 ixgbe_vt_check(struct ixgbe_hw *hw)
5341 {
5342         uint32_t reg_val;
5343
5344         /* if Virtualization Technology is enabled */
5345         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5346         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5347                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5348                 return -1;
5349         }
5350
5351         return 0;
5352 }
5353
5354 static uint32_t
5355 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5356 {
5357         uint32_t vector = 0;
5358
5359         switch (hw->mac.mc_filter_type) {
5360         case 0:   /* use bits [47:36] of the address */
5361                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5362                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5363                 break;
5364         case 1:   /* use bits [46:35] of the address */
5365                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5366                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5367                 break;
5368         case 2:   /* use bits [45:34] of the address */
5369                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5370                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5371                 break;
5372         case 3:   /* use bits [43:32] of the address */
5373                 vector = ((uc_addr->addr_bytes[4]) |
5374                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5375                 break;
5376         default:  /* Invalid mc_filter_type */
5377                 break;
5378         }
5379
5380         /* vector can only be 12-bits or boundary will be exceeded */
5381         vector &= 0xFFF;
5382         return vector;
5383 }
5384
5385 static int
5386 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5387                         uint8_t on)
5388 {
5389         uint32_t vector;
5390         uint32_t uta_idx;
5391         uint32_t reg_val;
5392         uint32_t uta_shift;
5393         uint32_t rc;
5394         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5395         const uint32_t ixgbe_uta_bit_shift = 5;
5396         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5397         const uint32_t bit1 = 0x1;
5398
5399         struct ixgbe_hw *hw =
5400                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5401         struct ixgbe_uta_info *uta_info =
5402                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5403
5404         /* The UTA table only exists on 82599 hardware and newer */
5405         if (hw->mac.type < ixgbe_mac_82599EB)
5406                 return -ENOTSUP;
5407
5408         vector = ixgbe_uta_vector(hw, mac_addr);
5409         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5410         uta_shift = vector & ixgbe_uta_bit_mask;
5411
5412         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5413         if (rc == on)
5414                 return 0;
5415
5416         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5417         if (on) {
5418                 uta_info->uta_in_use++;
5419                 reg_val |= (bit1 << uta_shift);
5420                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5421         } else {
5422                 uta_info->uta_in_use--;
5423                 reg_val &= ~(bit1 << uta_shift);
5424                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5425         }
5426
5427         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5428
5429         if (uta_info->uta_in_use > 0)
5430                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5431                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5432         else
5433                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5434
5435         return 0;
5436 }
5437
5438 static int
5439 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5440 {
5441         int i;
5442         struct ixgbe_hw *hw =
5443                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5444         struct ixgbe_uta_info *uta_info =
5445                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5446
5447         /* The UTA table only exists on 82599 hardware and newer */
5448         if (hw->mac.type < ixgbe_mac_82599EB)
5449                 return -ENOTSUP;
5450
5451         if (on) {
5452                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5453                         uta_info->uta_shadow[i] = ~0;
5454                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5455                 }
5456         } else {
5457                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5458                         uta_info->uta_shadow[i] = 0;
5459                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5460                 }
5461         }
5462         return 0;
5463
5464 }
5465
5466 uint32_t
5467 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5468 {
5469         uint32_t new_val = orig_val;
5470
5471         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5472                 new_val |= IXGBE_VMOLR_AUPE;
5473         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5474                 new_val |= IXGBE_VMOLR_ROMPE;
5475         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5476                 new_val |= IXGBE_VMOLR_ROPE;
5477         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5478                 new_val |= IXGBE_VMOLR_BAM;
5479         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5480                 new_val |= IXGBE_VMOLR_MPE;
5481
5482         return new_val;
5483 }
5484
5485 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5486 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5487 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5488 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5489 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5490         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5491         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5492
5493 static int
5494 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5495                       struct rte_eth_mirror_conf *mirror_conf,
5496                       uint8_t rule_id, uint8_t on)
5497 {
5498         uint32_t mr_ctl, vlvf;
5499         uint32_t mp_lsb = 0;
5500         uint32_t mv_msb = 0;
5501         uint32_t mv_lsb = 0;
5502         uint32_t mp_msb = 0;
5503         uint8_t i = 0;
5504         int reg_index = 0;
5505         uint64_t vlan_mask = 0;
5506
5507         const uint8_t pool_mask_offset = 32;
5508         const uint8_t vlan_mask_offset = 32;
5509         const uint8_t dst_pool_offset = 8;
5510         const uint8_t rule_mr_offset  = 4;
5511         const uint8_t mirror_rule_mask = 0x0F;
5512
5513         struct ixgbe_mirror_info *mr_info =
5514                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5515         struct ixgbe_hw *hw =
5516                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5517         uint8_t mirror_type = 0;
5518
5519         if (ixgbe_vt_check(hw) < 0)
5520                 return -ENOTSUP;
5521
5522         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5523                 return -EINVAL;
5524
5525         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5526                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5527                             mirror_conf->rule_type);
5528                 return -EINVAL;
5529         }
5530
5531         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5532                 mirror_type |= IXGBE_MRCTL_VLME;
5533                 /* Check if vlan id is valid and find conresponding VLAN ID
5534                  * index in VLVF
5535                  */
5536                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5537                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5538                                 /* search vlan id related pool vlan filter
5539                                  * index
5540                                  */
5541                                 reg_index = ixgbe_find_vlvf_slot(
5542                                                 hw,
5543                                                 mirror_conf->vlan.vlan_id[i],
5544                                                 false);
5545                                 if (reg_index < 0)
5546                                         return -EINVAL;
5547                                 vlvf = IXGBE_READ_REG(hw,
5548                                                       IXGBE_VLVF(reg_index));
5549                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5550                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5551                                       mirror_conf->vlan.vlan_id[i]))
5552                                         vlan_mask |= (1ULL << reg_index);
5553                                 else
5554                                         return -EINVAL;
5555                         }
5556                 }
5557
5558                 if (on) {
5559                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5560                         mv_msb = vlan_mask >> vlan_mask_offset;
5561
5562                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5563                                                 mirror_conf->vlan.vlan_mask;
5564                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5565                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5566                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5567                                                 mirror_conf->vlan.vlan_id[i];
5568                         }
5569                 } else {
5570                         mv_lsb = 0;
5571                         mv_msb = 0;
5572                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5573                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5574                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5575                 }
5576         }
5577
5578         /**
5579          * if enable pool mirror, write related pool mask register,if disable
5580          * pool mirror, clear PFMRVM register
5581          */
5582         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5583                 mirror_type |= IXGBE_MRCTL_VPME;
5584                 if (on) {
5585                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5586                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5587                         mr_info->mr_conf[rule_id].pool_mask =
5588                                         mirror_conf->pool_mask;
5589
5590                 } else {
5591                         mp_lsb = 0;
5592                         mp_msb = 0;
5593                         mr_info->mr_conf[rule_id].pool_mask = 0;
5594                 }
5595         }
5596         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5597                 mirror_type |= IXGBE_MRCTL_UPME;
5598         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5599                 mirror_type |= IXGBE_MRCTL_DPME;
5600
5601         /* read  mirror control register and recalculate it */
5602         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5603
5604         if (on) {
5605                 mr_ctl |= mirror_type;
5606                 mr_ctl &= mirror_rule_mask;
5607                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5608         } else {
5609                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5610         }
5611
5612         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5613         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5614
5615         /* write mirrror control  register */
5616         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5617
5618         /* write pool mirrror control  register */
5619         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5620                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5621                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5622                                 mp_msb);
5623         }
5624         /* write VLAN mirrror control  register */
5625         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5626                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5627                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5628                                 mv_msb);
5629         }
5630
5631         return 0;
5632 }
5633
5634 static int
5635 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5636 {
5637         int mr_ctl = 0;
5638         uint32_t lsb_val = 0;
5639         uint32_t msb_val = 0;
5640         const uint8_t rule_mr_offset = 4;
5641
5642         struct ixgbe_hw *hw =
5643                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5644         struct ixgbe_mirror_info *mr_info =
5645                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5646
5647         if (ixgbe_vt_check(hw) < 0)
5648                 return -ENOTSUP;
5649
5650         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5651                 return -EINVAL;
5652
5653         memset(&mr_info->mr_conf[rule_id], 0,
5654                sizeof(struct rte_eth_mirror_conf));
5655
5656         /* clear PFVMCTL register */
5657         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5658
5659         /* clear pool mask register */
5660         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5661         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5662
5663         /* clear vlan mask register */
5664         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5665         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5666
5667         return 0;
5668 }
5669
5670 static int
5671 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5672 {
5673         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5674         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5675         struct ixgbe_interrupt *intr =
5676                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5677         struct ixgbe_hw *hw =
5678                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5679         uint32_t vec = IXGBE_MISC_VEC_ID;
5680
5681         if (rte_intr_allow_others(intr_handle))
5682                 vec = IXGBE_RX_VEC_START;
5683         intr->mask |= (1 << vec);
5684         RTE_SET_USED(queue_id);
5685         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5686
5687         rte_intr_enable(intr_handle);
5688
5689         return 0;
5690 }
5691
5692 static int
5693 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5694 {
5695         struct ixgbe_interrupt *intr =
5696                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5697         struct ixgbe_hw *hw =
5698                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5699         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5700         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5701         uint32_t vec = IXGBE_MISC_VEC_ID;
5702
5703         if (rte_intr_allow_others(intr_handle))
5704                 vec = IXGBE_RX_VEC_START;
5705         intr->mask &= ~(1 << vec);
5706         RTE_SET_USED(queue_id);
5707         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5708
5709         return 0;
5710 }
5711
5712 static int
5713 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5714 {
5715         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5716         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5717         uint32_t mask;
5718         struct ixgbe_hw *hw =
5719                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5720         struct ixgbe_interrupt *intr =
5721                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5722
5723         if (queue_id < 16) {
5724                 ixgbe_disable_intr(hw);
5725                 intr->mask |= (1 << queue_id);
5726                 ixgbe_enable_intr(dev);
5727         } else if (queue_id < 32) {
5728                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5729                 mask &= (1 << queue_id);
5730                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5731         } else if (queue_id < 64) {
5732                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5733                 mask &= (1 << (queue_id - 32));
5734                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5735         }
5736         rte_intr_enable(intr_handle);
5737
5738         return 0;
5739 }
5740
5741 static int
5742 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5743 {
5744         uint32_t mask;
5745         struct ixgbe_hw *hw =
5746                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5747         struct ixgbe_interrupt *intr =
5748                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5749
5750         if (queue_id < 16) {
5751                 ixgbe_disable_intr(hw);
5752                 intr->mask &= ~(1 << queue_id);
5753                 ixgbe_enable_intr(dev);
5754         } else if (queue_id < 32) {
5755                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5756                 mask &= ~(1 << queue_id);
5757                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5758         } else if (queue_id < 64) {
5759                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5760                 mask &= ~(1 << (queue_id - 32));
5761                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5762         }
5763
5764         return 0;
5765 }
5766
5767 static void
5768 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5769                      uint8_t queue, uint8_t msix_vector)
5770 {
5771         uint32_t tmp, idx;
5772
5773         if (direction == -1) {
5774                 /* other causes */
5775                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5776                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5777                 tmp &= ~0xFF;
5778                 tmp |= msix_vector;
5779                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5780         } else {
5781                 /* rx or tx cause */
5782                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5783                 idx = ((16 * (queue & 1)) + (8 * direction));
5784                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5785                 tmp &= ~(0xFF << idx);
5786                 tmp |= (msix_vector << idx);
5787                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5788         }
5789 }
5790
5791 /**
5792  * set the IVAR registers, mapping interrupt causes to vectors
5793  * @param hw
5794  *  pointer to ixgbe_hw struct
5795  * @direction
5796  *  0 for Rx, 1 for Tx, -1 for other causes
5797  * @queue
5798  *  queue to map the corresponding interrupt to
5799  * @msix_vector
5800  *  the vector to map to the corresponding queue
5801  */
5802 static void
5803 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5804                    uint8_t queue, uint8_t msix_vector)
5805 {
5806         uint32_t tmp, idx;
5807
5808         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5809         if (hw->mac.type == ixgbe_mac_82598EB) {
5810                 if (direction == -1)
5811                         direction = 0;
5812                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5813                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5814                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5815                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5816                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5817         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5818                         (hw->mac.type == ixgbe_mac_X540) ||
5819                         (hw->mac.type == ixgbe_mac_X550)) {
5820                 if (direction == -1) {
5821                         /* other causes */
5822                         idx = ((queue & 1) * 8);
5823                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5824                         tmp &= ~(0xFF << idx);
5825                         tmp |= (msix_vector << idx);
5826                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5827                 } else {
5828                         /* rx or tx causes */
5829                         idx = ((16 * (queue & 1)) + (8 * direction));
5830                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5831                         tmp &= ~(0xFF << idx);
5832                         tmp |= (msix_vector << idx);
5833                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5834                 }
5835         }
5836 }
5837
5838 static void
5839 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5840 {
5841         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5842         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5843         struct ixgbe_hw *hw =
5844                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5845         uint32_t q_idx;
5846         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5847         uint32_t base = IXGBE_MISC_VEC_ID;
5848
5849         /* Configure VF other cause ivar */
5850         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5851
5852         /* won't configure msix register if no mapping is done
5853          * between intr vector and event fd.
5854          */
5855         if (!rte_intr_dp_is_en(intr_handle))
5856                 return;
5857
5858         if (rte_intr_allow_others(intr_handle)) {
5859                 base = IXGBE_RX_VEC_START;
5860                 vector_idx = IXGBE_RX_VEC_START;
5861         }
5862
5863         /* Configure all RX queues of VF */
5864         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5865                 /* Force all queue use vector 0,
5866                  * as IXGBE_VF_MAXMSIVECOTR = 1
5867                  */
5868                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5869                 intr_handle->intr_vec[q_idx] = vector_idx;
5870                 if (vector_idx < base + intr_handle->nb_efd - 1)
5871                         vector_idx++;
5872         }
5873
5874         /* As RX queue setting above show, all queues use the vector 0.
5875          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5876          */
5877         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5878                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5879                         | IXGBE_EITR_CNT_WDIS);
5880 }
5881
5882 /**
5883  * Sets up the hardware to properly generate MSI-X interrupts
5884  * @hw
5885  *  board private structure
5886  */
5887 static void
5888 ixgbe_configure_msix(struct rte_eth_dev *dev)
5889 {
5890         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5891         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5892         struct ixgbe_hw *hw =
5893                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5894         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5895         uint32_t vec = IXGBE_MISC_VEC_ID;
5896         uint32_t mask;
5897         uint32_t gpie;
5898
5899         /* won't configure msix register if no mapping is done
5900          * between intr vector and event fd
5901          * but if misx has been enabled already, need to configure
5902          * auto clean, auto mask and throttling.
5903          */
5904         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5905         if (!rte_intr_dp_is_en(intr_handle) &&
5906             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5907                 return;
5908
5909         if (rte_intr_allow_others(intr_handle))
5910                 vec = base = IXGBE_RX_VEC_START;
5911
5912         /* setup GPIE for MSI-x mode */
5913         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5914         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5915                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5916         /* auto clearing and auto setting corresponding bits in EIMS
5917          * when MSI-X interrupt is triggered
5918          */
5919         if (hw->mac.type == ixgbe_mac_82598EB) {
5920                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5921         } else {
5922                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5923                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5924         }
5925         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5926
5927         /* Populate the IVAR table and set the ITR values to the
5928          * corresponding register.
5929          */
5930         if (rte_intr_dp_is_en(intr_handle)) {
5931                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5932                         queue_id++) {
5933                         /* by default, 1:1 mapping */
5934                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5935                         intr_handle->intr_vec[queue_id] = vec;
5936                         if (vec < base + intr_handle->nb_efd - 1)
5937                                 vec++;
5938                 }
5939
5940                 switch (hw->mac.type) {
5941                 case ixgbe_mac_82598EB:
5942                         ixgbe_set_ivar_map(hw, -1,
5943                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5944                                            IXGBE_MISC_VEC_ID);
5945                         break;
5946                 case ixgbe_mac_82599EB:
5947                 case ixgbe_mac_X540:
5948                 case ixgbe_mac_X550:
5949                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5950                         break;
5951                 default:
5952                         break;
5953                 }
5954         }
5955         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5956                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5957                         | IXGBE_EITR_CNT_WDIS);
5958
5959         /* set up to autoclear timer, and the vectors */
5960         mask = IXGBE_EIMS_ENABLE_MASK;
5961         mask &= ~(IXGBE_EIMS_OTHER |
5962                   IXGBE_EIMS_MAILBOX |
5963                   IXGBE_EIMS_LSC);
5964
5965         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5966 }
5967
5968 int
5969 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5970                            uint16_t queue_idx, uint16_t tx_rate)
5971 {
5972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5973         struct rte_eth_rxmode *rxmode;
5974         uint32_t rf_dec, rf_int;
5975         uint32_t bcnrc_val;
5976         uint16_t link_speed = dev->data->dev_link.link_speed;
5977
5978         if (queue_idx >= hw->mac.max_tx_queues)
5979                 return -EINVAL;
5980
5981         if (tx_rate != 0) {
5982                 /* Calculate the rate factor values to set */
5983                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5984                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5985                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5986
5987                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5988                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5989                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5990                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5991         } else {
5992                 bcnrc_val = 0;
5993         }
5994
5995         rxmode = &dev->data->dev_conf.rxmode;
5996         /*
5997          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5998          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5999          * set as 0x4.
6000          */
6001         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6002             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6003                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6004                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6005         else
6006                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6007                         IXGBE_MMW_SIZE_DEFAULT);
6008
6009         /* Set RTTBCNRC of queue X */
6010         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6011         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6012         IXGBE_WRITE_FLUSH(hw);
6013
6014         return 0;
6015 }
6016
6017 static int
6018 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
6019                      __attribute__((unused)) uint32_t index,
6020                      __attribute__((unused)) uint32_t pool)
6021 {
6022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6023         int diag;
6024
6025         /*
6026          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6027          * operation. Trap this case to avoid exhausting the [very limited]
6028          * set of PF resources used to store VF MAC addresses.
6029          */
6030         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6031                 return -1;
6032         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6033         if (diag != 0)
6034                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6035                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6036                             mac_addr->addr_bytes[0],
6037                             mac_addr->addr_bytes[1],
6038                             mac_addr->addr_bytes[2],
6039                             mac_addr->addr_bytes[3],
6040                             mac_addr->addr_bytes[4],
6041                             mac_addr->addr_bytes[5],
6042                             diag);
6043         return diag;
6044 }
6045
6046 static void
6047 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6048 {
6049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6050         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6051         struct ether_addr *mac_addr;
6052         uint32_t i;
6053         int diag;
6054
6055         /*
6056          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6057          * not support the deletion of a given MAC address.
6058          * Instead, it imposes to delete all MAC addresses, then to add again
6059          * all MAC addresses with the exception of the one to be deleted.
6060          */
6061         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6062
6063         /*
6064          * Add again all MAC addresses, with the exception of the deleted one
6065          * and of the permanent MAC address.
6066          */
6067         for (i = 0, mac_addr = dev->data->mac_addrs;
6068              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6069                 /* Skip the deleted MAC address */
6070                 if (i == index)
6071                         continue;
6072                 /* Skip NULL MAC addresses */
6073                 if (is_zero_ether_addr(mac_addr))
6074                         continue;
6075                 /* Skip the permanent MAC address */
6076                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6077                         continue;
6078                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6079                 if (diag != 0)
6080                         PMD_DRV_LOG(ERR,
6081                                     "Adding again MAC address "
6082                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6083                                     "diag=%d",
6084                                     mac_addr->addr_bytes[0],
6085                                     mac_addr->addr_bytes[1],
6086                                     mac_addr->addr_bytes[2],
6087                                     mac_addr->addr_bytes[3],
6088                                     mac_addr->addr_bytes[4],
6089                                     mac_addr->addr_bytes[5],
6090                                     diag);
6091         }
6092 }
6093
6094 static int
6095 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6096 {
6097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6098
6099         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6100
6101         return 0;
6102 }
6103
6104 int
6105 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6106                         struct rte_eth_syn_filter *filter,
6107                         bool add)
6108 {
6109         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6110         struct ixgbe_filter_info *filter_info =
6111                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6112         uint32_t syn_info;
6113         uint32_t synqf;
6114
6115         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6116                 return -EINVAL;
6117
6118         syn_info = filter_info->syn_info;
6119
6120         if (add) {
6121                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6122                         return -EINVAL;
6123                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6124                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6125
6126                 if (filter->hig_pri)
6127                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6128                 else
6129                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6130         } else {
6131                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6132                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6133                         return -ENOENT;
6134                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6135         }
6136
6137         filter_info->syn_info = synqf;
6138         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6139         IXGBE_WRITE_FLUSH(hw);
6140         return 0;
6141 }
6142
6143 static int
6144 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6145                         struct rte_eth_syn_filter *filter)
6146 {
6147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6148         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6149
6150         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6151                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6152                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6153                 return 0;
6154         }
6155         return -ENOENT;
6156 }
6157
6158 static int
6159 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6160                         enum rte_filter_op filter_op,
6161                         void *arg)
6162 {
6163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6164         int ret;
6165
6166         MAC_TYPE_FILTER_SUP(hw->mac.type);
6167
6168         if (filter_op == RTE_ETH_FILTER_NOP)
6169                 return 0;
6170
6171         if (arg == NULL) {
6172                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6173                             filter_op);
6174                 return -EINVAL;
6175         }
6176
6177         switch (filter_op) {
6178         case RTE_ETH_FILTER_ADD:
6179                 ret = ixgbe_syn_filter_set(dev,
6180                                 (struct rte_eth_syn_filter *)arg,
6181                                 TRUE);
6182                 break;
6183         case RTE_ETH_FILTER_DELETE:
6184                 ret = ixgbe_syn_filter_set(dev,
6185                                 (struct rte_eth_syn_filter *)arg,
6186                                 FALSE);
6187                 break;
6188         case RTE_ETH_FILTER_GET:
6189                 ret = ixgbe_syn_filter_get(dev,
6190                                 (struct rte_eth_syn_filter *)arg);
6191                 break;
6192         default:
6193                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6194                 ret = -EINVAL;
6195                 break;
6196         }
6197
6198         return ret;
6199 }
6200
6201
6202 static inline enum ixgbe_5tuple_protocol
6203 convert_protocol_type(uint8_t protocol_value)
6204 {
6205         if (protocol_value == IPPROTO_TCP)
6206                 return IXGBE_FILTER_PROTOCOL_TCP;
6207         else if (protocol_value == IPPROTO_UDP)
6208                 return IXGBE_FILTER_PROTOCOL_UDP;
6209         else if (protocol_value == IPPROTO_SCTP)
6210                 return IXGBE_FILTER_PROTOCOL_SCTP;
6211         else
6212                 return IXGBE_FILTER_PROTOCOL_NONE;
6213 }
6214
6215 /* inject a 5-tuple filter to HW */
6216 static inline void
6217 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6218                            struct ixgbe_5tuple_filter *filter)
6219 {
6220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6221         int i;
6222         uint32_t ftqf, sdpqf;
6223         uint32_t l34timir = 0;
6224         uint8_t mask = 0xff;
6225
6226         i = filter->index;
6227
6228         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6229                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6230         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6231
6232         ftqf = (uint32_t)(filter->filter_info.proto &
6233                 IXGBE_FTQF_PROTOCOL_MASK);
6234         ftqf |= (uint32_t)((filter->filter_info.priority &
6235                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6236         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6237                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6238         if (filter->filter_info.dst_ip_mask == 0)
6239                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6240         if (filter->filter_info.src_port_mask == 0)
6241                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6242         if (filter->filter_info.dst_port_mask == 0)
6243                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6244         if (filter->filter_info.proto_mask == 0)
6245                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6246         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6247         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6248         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6249
6250         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6251         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6252         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6253         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6254
6255         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6256         l34timir |= (uint32_t)(filter->queue <<
6257                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6258         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6259 }
6260
6261 /*
6262  * add a 5tuple filter
6263  *
6264  * @param
6265  * dev: Pointer to struct rte_eth_dev.
6266  * index: the index the filter allocates.
6267  * filter: ponter to the filter that will be added.
6268  * rx_queue: the queue id the filter assigned to.
6269  *
6270  * @return
6271  *    - On success, zero.
6272  *    - On failure, a negative value.
6273  */
6274 static int
6275 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6276                         struct ixgbe_5tuple_filter *filter)
6277 {
6278         struct ixgbe_filter_info *filter_info =
6279                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6280         int i, idx, shift;
6281
6282         /*
6283          * look for an unused 5tuple filter index,
6284          * and insert the filter to list.
6285          */
6286         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6287                 idx = i / (sizeof(uint32_t) * NBBY);
6288                 shift = i % (sizeof(uint32_t) * NBBY);
6289                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6290                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6291                         filter->index = i;
6292                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6293                                           filter,
6294                                           entries);
6295                         break;
6296                 }
6297         }
6298         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6299                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6300                 return -ENOSYS;
6301         }
6302
6303         ixgbe_inject_5tuple_filter(dev, filter);
6304
6305         return 0;
6306 }
6307
6308 /*
6309  * remove a 5tuple filter
6310  *
6311  * @param
6312  * dev: Pointer to struct rte_eth_dev.
6313  * filter: the pointer of the filter will be removed.
6314  */
6315 static void
6316 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6317                         struct ixgbe_5tuple_filter *filter)
6318 {
6319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6320         struct ixgbe_filter_info *filter_info =
6321                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6322         uint16_t index = filter->index;
6323
6324         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6325                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6326         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6327         rte_free(filter);
6328
6329         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6330         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6331         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6332         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6333         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6334 }
6335
6336 static int
6337 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6338 {
6339         struct ixgbe_hw *hw;
6340         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6341         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6342
6343         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6344
6345         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6346                 return -EINVAL;
6347
6348         /* refuse mtu that requires the support of scattered packets when this
6349          * feature has not been enabled before.
6350          */
6351         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6352             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6353              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6354                 return -EINVAL;
6355
6356         /*
6357          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6358          * request of the version 2.0 of the mailbox API.
6359          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6360          * of the mailbox API.
6361          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6362          * prior to 3.11.33 which contains the following change:
6363          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6364          */
6365         ixgbevf_rlpml_set_vf(hw, max_frame);
6366
6367         /* update max frame size */
6368         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6369         return 0;
6370 }
6371
6372 static inline struct ixgbe_5tuple_filter *
6373 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6374                         struct ixgbe_5tuple_filter_info *key)
6375 {
6376         struct ixgbe_5tuple_filter *it;
6377
6378         TAILQ_FOREACH(it, filter_list, entries) {
6379                 if (memcmp(key, &it->filter_info,
6380                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6381                         return it;
6382                 }
6383         }
6384         return NULL;
6385 }
6386
6387 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6388 static inline int
6389 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6390                         struct ixgbe_5tuple_filter_info *filter_info)
6391 {
6392         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6393                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6394                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6395                 return -EINVAL;
6396
6397         switch (filter->dst_ip_mask) {
6398         case UINT32_MAX:
6399                 filter_info->dst_ip_mask = 0;
6400                 filter_info->dst_ip = filter->dst_ip;
6401                 break;
6402         case 0:
6403                 filter_info->dst_ip_mask = 1;
6404                 break;
6405         default:
6406                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6407                 return -EINVAL;
6408         }
6409
6410         switch (filter->src_ip_mask) {
6411         case UINT32_MAX:
6412                 filter_info->src_ip_mask = 0;
6413                 filter_info->src_ip = filter->src_ip;
6414                 break;
6415         case 0:
6416                 filter_info->src_ip_mask = 1;
6417                 break;
6418         default:
6419                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6420                 return -EINVAL;
6421         }
6422
6423         switch (filter->dst_port_mask) {
6424         case UINT16_MAX:
6425                 filter_info->dst_port_mask = 0;
6426                 filter_info->dst_port = filter->dst_port;
6427                 break;
6428         case 0:
6429                 filter_info->dst_port_mask = 1;
6430                 break;
6431         default:
6432                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6433                 return -EINVAL;
6434         }
6435
6436         switch (filter->src_port_mask) {
6437         case UINT16_MAX:
6438                 filter_info->src_port_mask = 0;
6439                 filter_info->src_port = filter->src_port;
6440                 break;
6441         case 0:
6442                 filter_info->src_port_mask = 1;
6443                 break;
6444         default:
6445                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6446                 return -EINVAL;
6447         }
6448
6449         switch (filter->proto_mask) {
6450         case UINT8_MAX:
6451                 filter_info->proto_mask = 0;
6452                 filter_info->proto =
6453                         convert_protocol_type(filter->proto);
6454                 break;
6455         case 0:
6456                 filter_info->proto_mask = 1;
6457                 break;
6458         default:
6459                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6460                 return -EINVAL;
6461         }
6462
6463         filter_info->priority = (uint8_t)filter->priority;
6464         return 0;
6465 }
6466
6467 /*
6468  * add or delete a ntuple filter
6469  *
6470  * @param
6471  * dev: Pointer to struct rte_eth_dev.
6472  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6473  * add: if true, add filter, if false, remove filter
6474  *
6475  * @return
6476  *    - On success, zero.
6477  *    - On failure, a negative value.
6478  */
6479 int
6480 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6481                         struct rte_eth_ntuple_filter *ntuple_filter,
6482                         bool add)
6483 {
6484         struct ixgbe_filter_info *filter_info =
6485                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6486         struct ixgbe_5tuple_filter_info filter_5tuple;
6487         struct ixgbe_5tuple_filter *filter;
6488         int ret;
6489
6490         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6491                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6492                 return -EINVAL;
6493         }
6494
6495         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6496         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6497         if (ret < 0)
6498                 return ret;
6499
6500         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6501                                          &filter_5tuple);
6502         if (filter != NULL && add) {
6503                 PMD_DRV_LOG(ERR, "filter exists.");
6504                 return -EEXIST;
6505         }
6506         if (filter == NULL && !add) {
6507                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6508                 return -ENOENT;
6509         }
6510
6511         if (add) {
6512                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6513                                 sizeof(struct ixgbe_5tuple_filter), 0);
6514                 if (filter == NULL)
6515                         return -ENOMEM;
6516                 rte_memcpy(&filter->filter_info,
6517                                  &filter_5tuple,
6518                                  sizeof(struct ixgbe_5tuple_filter_info));
6519                 filter->queue = ntuple_filter->queue;
6520                 ret = ixgbe_add_5tuple_filter(dev, filter);
6521                 if (ret < 0) {
6522                         rte_free(filter);
6523                         return ret;
6524                 }
6525         } else
6526                 ixgbe_remove_5tuple_filter(dev, filter);
6527
6528         return 0;
6529 }
6530
6531 /*
6532  * get a ntuple filter
6533  *
6534  * @param
6535  * dev: Pointer to struct rte_eth_dev.
6536  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6537  *
6538  * @return
6539  *    - On success, zero.
6540  *    - On failure, a negative value.
6541  */
6542 static int
6543 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6544                         struct rte_eth_ntuple_filter *ntuple_filter)
6545 {
6546         struct ixgbe_filter_info *filter_info =
6547                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6548         struct ixgbe_5tuple_filter_info filter_5tuple;
6549         struct ixgbe_5tuple_filter *filter;
6550         int ret;
6551
6552         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6553                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6554                 return -EINVAL;
6555         }
6556
6557         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6558         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6559         if (ret < 0)
6560                 return ret;
6561
6562         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6563                                          &filter_5tuple);
6564         if (filter == NULL) {
6565                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6566                 return -ENOENT;
6567         }
6568         ntuple_filter->queue = filter->queue;
6569         return 0;
6570 }
6571
6572 /*
6573  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6574  * @dev: pointer to rte_eth_dev structure
6575  * @filter_op:operation will be taken.
6576  * @arg: a pointer to specific structure corresponding to the filter_op
6577  *
6578  * @return
6579  *    - On success, zero.
6580  *    - On failure, a negative value.
6581  */
6582 static int
6583 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6584                                 enum rte_filter_op filter_op,
6585                                 void *arg)
6586 {
6587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6588         int ret;
6589
6590         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6591
6592         if (filter_op == RTE_ETH_FILTER_NOP)
6593                 return 0;
6594
6595         if (arg == NULL) {
6596                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6597                             filter_op);
6598                 return -EINVAL;
6599         }
6600
6601         switch (filter_op) {
6602         case RTE_ETH_FILTER_ADD:
6603                 ret = ixgbe_add_del_ntuple_filter(dev,
6604                         (struct rte_eth_ntuple_filter *)arg,
6605                         TRUE);
6606                 break;
6607         case RTE_ETH_FILTER_DELETE:
6608                 ret = ixgbe_add_del_ntuple_filter(dev,
6609                         (struct rte_eth_ntuple_filter *)arg,
6610                         FALSE);
6611                 break;
6612         case RTE_ETH_FILTER_GET:
6613                 ret = ixgbe_get_ntuple_filter(dev,
6614                         (struct rte_eth_ntuple_filter *)arg);
6615                 break;
6616         default:
6617                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6618                 ret = -EINVAL;
6619                 break;
6620         }
6621         return ret;
6622 }
6623
6624 int
6625 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6626                         struct rte_eth_ethertype_filter *filter,
6627                         bool add)
6628 {
6629         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6630         struct ixgbe_filter_info *filter_info =
6631                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6632         uint32_t etqf = 0;
6633         uint32_t etqs = 0;
6634         int ret;
6635         struct ixgbe_ethertype_filter ethertype_filter;
6636
6637         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6638                 return -EINVAL;
6639
6640         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6641                 filter->ether_type == ETHER_TYPE_IPv6) {
6642                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6643                         " ethertype filter.", filter->ether_type);
6644                 return -EINVAL;
6645         }
6646
6647         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6648                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6649                 return -EINVAL;
6650         }
6651         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6652                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6653                 return -EINVAL;
6654         }
6655
6656         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6657         if (ret >= 0 && add) {
6658                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6659                             filter->ether_type);
6660                 return -EEXIST;
6661         }
6662         if (ret < 0 && !add) {
6663                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6664                             filter->ether_type);
6665                 return -ENOENT;
6666         }
6667
6668         if (add) {
6669                 etqf = IXGBE_ETQF_FILTER_EN;
6670                 etqf |= (uint32_t)filter->ether_type;
6671                 etqs |= (uint32_t)((filter->queue <<
6672                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6673                                     IXGBE_ETQS_RX_QUEUE);
6674                 etqs |= IXGBE_ETQS_QUEUE_EN;
6675
6676                 ethertype_filter.ethertype = filter->ether_type;
6677                 ethertype_filter.etqf = etqf;
6678                 ethertype_filter.etqs = etqs;
6679                 ethertype_filter.conf = FALSE;
6680                 ret = ixgbe_ethertype_filter_insert(filter_info,
6681                                                     &ethertype_filter);
6682                 if (ret < 0) {
6683                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6684                         return -ENOSPC;
6685                 }
6686         } else {
6687                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6688                 if (ret < 0)
6689                         return -ENOSYS;
6690         }
6691         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6692         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6693         IXGBE_WRITE_FLUSH(hw);
6694
6695         return 0;
6696 }
6697
6698 static int
6699 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6700                         struct rte_eth_ethertype_filter *filter)
6701 {
6702         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6703         struct ixgbe_filter_info *filter_info =
6704                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6705         uint32_t etqf, etqs;
6706         int ret;
6707
6708         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6709         if (ret < 0) {
6710                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6711                             filter->ether_type);
6712                 return -ENOENT;
6713         }
6714
6715         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6716         if (etqf & IXGBE_ETQF_FILTER_EN) {
6717                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6718                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6719                 filter->flags = 0;
6720                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6721                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6722                 return 0;
6723         }
6724         return -ENOENT;
6725 }
6726
6727 /*
6728  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6729  * @dev: pointer to rte_eth_dev structure
6730  * @filter_op:operation will be taken.
6731  * @arg: a pointer to specific structure corresponding to the filter_op
6732  */
6733 static int
6734 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6735                                 enum rte_filter_op filter_op,
6736                                 void *arg)
6737 {
6738         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6739         int ret;
6740
6741         MAC_TYPE_FILTER_SUP(hw->mac.type);
6742
6743         if (filter_op == RTE_ETH_FILTER_NOP)
6744                 return 0;
6745
6746         if (arg == NULL) {
6747                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6748                             filter_op);
6749                 return -EINVAL;
6750         }
6751
6752         switch (filter_op) {
6753         case RTE_ETH_FILTER_ADD:
6754                 ret = ixgbe_add_del_ethertype_filter(dev,
6755                         (struct rte_eth_ethertype_filter *)arg,
6756                         TRUE);
6757                 break;
6758         case RTE_ETH_FILTER_DELETE:
6759                 ret = ixgbe_add_del_ethertype_filter(dev,
6760                         (struct rte_eth_ethertype_filter *)arg,
6761                         FALSE);
6762                 break;
6763         case RTE_ETH_FILTER_GET:
6764                 ret = ixgbe_get_ethertype_filter(dev,
6765                         (struct rte_eth_ethertype_filter *)arg);
6766                 break;
6767         default:
6768                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6769                 ret = -EINVAL;
6770                 break;
6771         }
6772         return ret;
6773 }
6774
6775 static int
6776 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6777                      enum rte_filter_type filter_type,
6778                      enum rte_filter_op filter_op,
6779                      void *arg)
6780 {
6781         int ret = 0;
6782
6783         switch (filter_type) {
6784         case RTE_ETH_FILTER_NTUPLE:
6785                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6786                 break;
6787         case RTE_ETH_FILTER_ETHERTYPE:
6788                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6789                 break;
6790         case RTE_ETH_FILTER_SYN:
6791                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6792                 break;
6793         case RTE_ETH_FILTER_FDIR:
6794                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6795                 break;
6796         case RTE_ETH_FILTER_L2_TUNNEL:
6797                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6798                 break;
6799         case RTE_ETH_FILTER_GENERIC:
6800                 if (filter_op != RTE_ETH_FILTER_GET)
6801                         return -EINVAL;
6802                 *(const void **)arg = &ixgbe_flow_ops;
6803                 break;
6804         default:
6805                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6806                                                         filter_type);
6807                 ret = -EINVAL;
6808                 break;
6809         }
6810
6811         return ret;
6812 }
6813
6814 static u8 *
6815 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6816                         u8 **mc_addr_ptr, u32 *vmdq)
6817 {
6818         u8 *mc_addr;
6819
6820         *vmdq = 0;
6821         mc_addr = *mc_addr_ptr;
6822         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6823         return mc_addr;
6824 }
6825
6826 static int
6827 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6828                           struct ether_addr *mc_addr_set,
6829                           uint32_t nb_mc_addr)
6830 {
6831         struct ixgbe_hw *hw;
6832         u8 *mc_addr_list;
6833
6834         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6835         mc_addr_list = (u8 *)mc_addr_set;
6836         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6837                                          ixgbe_dev_addr_list_itr, TRUE);
6838 }
6839
6840 static uint64_t
6841 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6842 {
6843         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6844         uint64_t systime_cycles;
6845
6846         switch (hw->mac.type) {
6847         case ixgbe_mac_X550:
6848         case ixgbe_mac_X550EM_x:
6849         case ixgbe_mac_X550EM_a:
6850                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6851                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6852                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6853                                 * NSEC_PER_SEC;
6854                 break;
6855         default:
6856                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6857                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6858                                 << 32;
6859         }
6860
6861         return systime_cycles;
6862 }
6863
6864 static uint64_t
6865 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6866 {
6867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6868         uint64_t rx_tstamp_cycles;
6869
6870         switch (hw->mac.type) {
6871         case ixgbe_mac_X550:
6872         case ixgbe_mac_X550EM_x:
6873         case ixgbe_mac_X550EM_a:
6874                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6875                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6876                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6877                                 * NSEC_PER_SEC;
6878                 break;
6879         default:
6880                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6881                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6882                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6883                                 << 32;
6884         }
6885
6886         return rx_tstamp_cycles;
6887 }
6888
6889 static uint64_t
6890 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6891 {
6892         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6893         uint64_t tx_tstamp_cycles;
6894
6895         switch (hw->mac.type) {
6896         case ixgbe_mac_X550:
6897         case ixgbe_mac_X550EM_x:
6898         case ixgbe_mac_X550EM_a:
6899                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6900                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6901                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6902                                 * NSEC_PER_SEC;
6903                 break;
6904         default:
6905                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6906                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6907                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6908                                 << 32;
6909         }
6910
6911         return tx_tstamp_cycles;
6912 }
6913
6914 static void
6915 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6916 {
6917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6918         struct ixgbe_adapter *adapter =
6919                 (struct ixgbe_adapter *)dev->data->dev_private;
6920         struct rte_eth_link link;
6921         uint32_t incval = 0;
6922         uint32_t shift = 0;
6923
6924         /* Get current link speed. */
6925         ixgbe_dev_link_update(dev, 1);
6926         rte_eth_linkstatus_get(dev, &link);
6927
6928         switch (link.link_speed) {
6929         case ETH_SPEED_NUM_100M:
6930                 incval = IXGBE_INCVAL_100;
6931                 shift = IXGBE_INCVAL_SHIFT_100;
6932                 break;
6933         case ETH_SPEED_NUM_1G:
6934                 incval = IXGBE_INCVAL_1GB;
6935                 shift = IXGBE_INCVAL_SHIFT_1GB;
6936                 break;
6937         case ETH_SPEED_NUM_10G:
6938         default:
6939                 incval = IXGBE_INCVAL_10GB;
6940                 shift = IXGBE_INCVAL_SHIFT_10GB;
6941                 break;
6942         }
6943
6944         switch (hw->mac.type) {
6945         case ixgbe_mac_X550:
6946         case ixgbe_mac_X550EM_x:
6947         case ixgbe_mac_X550EM_a:
6948                 /* Independent of link speed. */
6949                 incval = 1;
6950                 /* Cycles read will be interpreted as ns. */
6951                 shift = 0;
6952                 /* Fall-through */
6953         case ixgbe_mac_X540:
6954                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6955                 break;
6956         case ixgbe_mac_82599EB:
6957                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6958                 shift -= IXGBE_INCVAL_SHIFT_82599;
6959                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6960                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6961                 break;
6962         default:
6963                 /* Not supported. */
6964                 return;
6965         }
6966
6967         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6968         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6969         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6970
6971         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6972         adapter->systime_tc.cc_shift = shift;
6973         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6974
6975         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6976         adapter->rx_tstamp_tc.cc_shift = shift;
6977         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6978
6979         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6980         adapter->tx_tstamp_tc.cc_shift = shift;
6981         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6982 }
6983
6984 static int
6985 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6986 {
6987         struct ixgbe_adapter *adapter =
6988                         (struct ixgbe_adapter *)dev->data->dev_private;
6989
6990         adapter->systime_tc.nsec += delta;
6991         adapter->rx_tstamp_tc.nsec += delta;
6992         adapter->tx_tstamp_tc.nsec += delta;
6993
6994         return 0;
6995 }
6996
6997 static int
6998 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6999 {
7000         uint64_t ns;
7001         struct ixgbe_adapter *adapter =
7002                         (struct ixgbe_adapter *)dev->data->dev_private;
7003
7004         ns = rte_timespec_to_ns(ts);
7005         /* Set the timecounters to a new value. */
7006         adapter->systime_tc.nsec = ns;
7007         adapter->rx_tstamp_tc.nsec = ns;
7008         adapter->tx_tstamp_tc.nsec = ns;
7009
7010         return 0;
7011 }
7012
7013 static int
7014 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7015 {
7016         uint64_t ns, systime_cycles;
7017         struct ixgbe_adapter *adapter =
7018                         (struct ixgbe_adapter *)dev->data->dev_private;
7019
7020         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7021         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7022         *ts = rte_ns_to_timespec(ns);
7023
7024         return 0;
7025 }
7026
7027 static int
7028 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7029 {
7030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7031         uint32_t tsync_ctl;
7032         uint32_t tsauxc;
7033
7034         /* Stop the timesync system time. */
7035         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7036         /* Reset the timesync system time value. */
7037         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7038         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7039
7040         /* Enable system time for platforms where it isn't on by default. */
7041         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7042         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7043         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7044
7045         ixgbe_start_timecounters(dev);
7046
7047         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7048         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7049                         (ETHER_TYPE_1588 |
7050                          IXGBE_ETQF_FILTER_EN |
7051                          IXGBE_ETQF_1588));
7052
7053         /* Enable timestamping of received PTP packets. */
7054         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7055         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7056         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7057
7058         /* Enable timestamping of transmitted PTP packets. */
7059         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7060         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7061         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7062
7063         IXGBE_WRITE_FLUSH(hw);
7064
7065         return 0;
7066 }
7067
7068 static int
7069 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7070 {
7071         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7072         uint32_t tsync_ctl;
7073
7074         /* Disable timestamping of transmitted PTP packets. */
7075         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7076         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7077         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7078
7079         /* Disable timestamping of received PTP packets. */
7080         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7081         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7082         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7083
7084         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7085         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7086
7087         /* Stop incrementating the System Time registers. */
7088         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7089
7090         return 0;
7091 }
7092
7093 static int
7094 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7095                                  struct timespec *timestamp,
7096                                  uint32_t flags __rte_unused)
7097 {
7098         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7099         struct ixgbe_adapter *adapter =
7100                 (struct ixgbe_adapter *)dev->data->dev_private;
7101         uint32_t tsync_rxctl;
7102         uint64_t rx_tstamp_cycles;
7103         uint64_t ns;
7104
7105         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7106         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7107                 return -EINVAL;
7108
7109         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7110         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7111         *timestamp = rte_ns_to_timespec(ns);
7112
7113         return  0;
7114 }
7115
7116 static int
7117 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7118                                  struct timespec *timestamp)
7119 {
7120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7121         struct ixgbe_adapter *adapter =
7122                 (struct ixgbe_adapter *)dev->data->dev_private;
7123         uint32_t tsync_txctl;
7124         uint64_t tx_tstamp_cycles;
7125         uint64_t ns;
7126
7127         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7128         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7129                 return -EINVAL;
7130
7131         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7132         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7133         *timestamp = rte_ns_to_timespec(ns);
7134
7135         return 0;
7136 }
7137
7138 static int
7139 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7140 {
7141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7142         int count = 0;
7143         int g_ind = 0;
7144         const struct reg_info *reg_group;
7145         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7146                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7147
7148         while ((reg_group = reg_set[g_ind++]))
7149                 count += ixgbe_regs_group_count(reg_group);
7150
7151         return count;
7152 }
7153
7154 static int
7155 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7156 {
7157         int count = 0;
7158         int g_ind = 0;
7159         const struct reg_info *reg_group;
7160
7161         while ((reg_group = ixgbevf_regs[g_ind++]))
7162                 count += ixgbe_regs_group_count(reg_group);
7163
7164         return count;
7165 }
7166
7167 static int
7168 ixgbe_get_regs(struct rte_eth_dev *dev,
7169               struct rte_dev_reg_info *regs)
7170 {
7171         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7172         uint32_t *data = regs->data;
7173         int g_ind = 0;
7174         int count = 0;
7175         const struct reg_info *reg_group;
7176         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7177                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7178
7179         if (data == NULL) {
7180                 regs->length = ixgbe_get_reg_length(dev);
7181                 regs->width = sizeof(uint32_t);
7182                 return 0;
7183         }
7184
7185         /* Support only full register dump */
7186         if ((regs->length == 0) ||
7187             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7188                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7189                         hw->device_id;
7190                 while ((reg_group = reg_set[g_ind++]))
7191                         count += ixgbe_read_regs_group(dev, &data[count],
7192                                 reg_group);
7193                 return 0;
7194         }
7195
7196         return -ENOTSUP;
7197 }
7198
7199 static int
7200 ixgbevf_get_regs(struct rte_eth_dev *dev,
7201                 struct rte_dev_reg_info *regs)
7202 {
7203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7204         uint32_t *data = regs->data;
7205         int g_ind = 0;
7206         int count = 0;
7207         const struct reg_info *reg_group;
7208
7209         if (data == NULL) {
7210                 regs->length = ixgbevf_get_reg_length(dev);
7211                 regs->width = sizeof(uint32_t);
7212                 return 0;
7213         }
7214
7215         /* Support only full register dump */
7216         if ((regs->length == 0) ||
7217             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7218                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7219                         hw->device_id;
7220                 while ((reg_group = ixgbevf_regs[g_ind++]))
7221                         count += ixgbe_read_regs_group(dev, &data[count],
7222                                                       reg_group);
7223                 return 0;
7224         }
7225
7226         return -ENOTSUP;
7227 }
7228
7229 static int
7230 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7231 {
7232         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7233
7234         /* Return unit is byte count */
7235         return hw->eeprom.word_size * 2;
7236 }
7237
7238 static int
7239 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7240                 struct rte_dev_eeprom_info *in_eeprom)
7241 {
7242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7243         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7244         uint16_t *data = in_eeprom->data;
7245         int first, length;
7246
7247         first = in_eeprom->offset >> 1;
7248         length = in_eeprom->length >> 1;
7249         if ((first > hw->eeprom.word_size) ||
7250             ((first + length) > hw->eeprom.word_size))
7251                 return -EINVAL;
7252
7253         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7254
7255         return eeprom->ops.read_buffer(hw, first, length, data);
7256 }
7257
7258 static int
7259 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7260                 struct rte_dev_eeprom_info *in_eeprom)
7261 {
7262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7263         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7264         uint16_t *data = in_eeprom->data;
7265         int first, length;
7266
7267         first = in_eeprom->offset >> 1;
7268         length = in_eeprom->length >> 1;
7269         if ((first > hw->eeprom.word_size) ||
7270             ((first + length) > hw->eeprom.word_size))
7271                 return -EINVAL;
7272
7273         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7274
7275         return eeprom->ops.write_buffer(hw,  first, length, data);
7276 }
7277
7278 static int
7279 ixgbe_get_module_info(struct rte_eth_dev *dev,
7280                       struct rte_eth_dev_module_info *modinfo)
7281 {
7282         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7283         uint32_t status;
7284         uint8_t sff8472_rev, addr_mode;
7285         bool page_swap = false;
7286
7287         /* Check whether we support SFF-8472 or not */
7288         status = hw->phy.ops.read_i2c_eeprom(hw,
7289                                              IXGBE_SFF_SFF_8472_COMP,
7290                                              &sff8472_rev);
7291         if (status != 0)
7292                 return -EIO;
7293
7294         /* addressing mode is not supported */
7295         status = hw->phy.ops.read_i2c_eeprom(hw,
7296                                              IXGBE_SFF_SFF_8472_SWAP,
7297                                              &addr_mode);
7298         if (status != 0)
7299                 return -EIO;
7300
7301         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7302                 PMD_DRV_LOG(ERR,
7303                             "Address change required to access page 0xA2, "
7304                             "but not supported. Please report the module "
7305                             "type to the driver maintainers.");
7306                 page_swap = true;
7307         }
7308
7309         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7310                 /* We have a SFP, but it does not support SFF-8472 */
7311                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7312                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7313         } else {
7314                 /* We have a SFP which supports a revision of SFF-8472. */
7315                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7316                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7317         }
7318
7319         return 0;
7320 }
7321
7322 static int
7323 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7324                         struct rte_dev_eeprom_info *info)
7325 {
7326         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7327         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7328         uint8_t databyte = 0xFF;
7329         uint8_t *data = info->data;
7330         uint32_t i = 0;
7331
7332         if (info->length == 0)
7333                 return -EINVAL;
7334
7335         for (i = info->offset; i < info->offset + info->length; i++) {
7336                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7337                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7338                 else
7339                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7340
7341                 if (status != 0)
7342                         return -EIO;
7343
7344                 data[i - info->offset] = databyte;
7345         }
7346
7347         return 0;
7348 }
7349
7350 uint16_t
7351 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7352         switch (mac_type) {
7353         case ixgbe_mac_X550:
7354         case ixgbe_mac_X550EM_x:
7355         case ixgbe_mac_X550EM_a:
7356                 return ETH_RSS_RETA_SIZE_512;
7357         case ixgbe_mac_X550_vf:
7358         case ixgbe_mac_X550EM_x_vf:
7359         case ixgbe_mac_X550EM_a_vf:
7360                 return ETH_RSS_RETA_SIZE_64;
7361         default:
7362                 return ETH_RSS_RETA_SIZE_128;
7363         }
7364 }
7365
7366 uint32_t
7367 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7368         switch (mac_type) {
7369         case ixgbe_mac_X550:
7370         case ixgbe_mac_X550EM_x:
7371         case ixgbe_mac_X550EM_a:
7372                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7373                         return IXGBE_RETA(reta_idx >> 2);
7374                 else
7375                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7376         case ixgbe_mac_X550_vf:
7377         case ixgbe_mac_X550EM_x_vf:
7378         case ixgbe_mac_X550EM_a_vf:
7379                 return IXGBE_VFRETA(reta_idx >> 2);
7380         default:
7381                 return IXGBE_RETA(reta_idx >> 2);
7382         }
7383 }
7384
7385 uint32_t
7386 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7387         switch (mac_type) {
7388         case ixgbe_mac_X550_vf:
7389         case ixgbe_mac_X550EM_x_vf:
7390         case ixgbe_mac_X550EM_a_vf:
7391                 return IXGBE_VFMRQC;
7392         default:
7393                 return IXGBE_MRQC;
7394         }
7395 }
7396
7397 uint32_t
7398 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7399         switch (mac_type) {
7400         case ixgbe_mac_X550_vf:
7401         case ixgbe_mac_X550EM_x_vf:
7402         case ixgbe_mac_X550EM_a_vf:
7403                 return IXGBE_VFRSSRK(i);
7404         default:
7405                 return IXGBE_RSSRK(i);
7406         }
7407 }
7408
7409 bool
7410 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7411         switch (mac_type) {
7412         case ixgbe_mac_82599_vf:
7413         case ixgbe_mac_X540_vf:
7414                 return 0;
7415         default:
7416                 return 1;
7417         }
7418 }
7419
7420 static int
7421 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7422                         struct rte_eth_dcb_info *dcb_info)
7423 {
7424         struct ixgbe_dcb_config *dcb_config =
7425                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7426         struct ixgbe_dcb_tc_config *tc;
7427         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7428         uint8_t nb_tcs;
7429         uint8_t i, j;
7430
7431         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7432                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7433         else
7434                 dcb_info->nb_tcs = 1;
7435
7436         tc_queue = &dcb_info->tc_queue;
7437         nb_tcs = dcb_info->nb_tcs;
7438
7439         if (dcb_config->vt_mode) { /* vt is enabled*/
7440                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7441                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7442                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7443                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7444                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7445                         for (j = 0; j < nb_tcs; j++) {
7446                                 tc_queue->tc_rxq[0][j].base = j;
7447                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7448                                 tc_queue->tc_txq[0][j].base = j;
7449                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7450                         }
7451                 } else {
7452                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7453                                 for (j = 0; j < nb_tcs; j++) {
7454                                         tc_queue->tc_rxq[i][j].base =
7455                                                 i * nb_tcs + j;
7456                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7457                                         tc_queue->tc_txq[i][j].base =
7458                                                 i * nb_tcs + j;
7459                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7460                                 }
7461                         }
7462                 }
7463         } else { /* vt is disabled*/
7464                 struct rte_eth_dcb_rx_conf *rx_conf =
7465                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7466                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7467                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7468                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7469                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7470                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7471                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7472                         }
7473                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7474                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7475                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7476                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7477                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7478                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7479                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7480                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7481                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7482                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7483                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7484                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7485                         }
7486                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7487                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7488                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7489                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7490                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7491                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7492                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7493                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7494                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7495                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7496                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7497                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7498                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7499                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7500                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7501                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7502                 }
7503         }
7504         for (i = 0; i < dcb_info->nb_tcs; i++) {
7505                 tc = &dcb_config->tc_config[i];
7506                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7507         }
7508         return 0;
7509 }
7510
7511 /* Update e-tag ether type */
7512 static int
7513 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7514                             uint16_t ether_type)
7515 {
7516         uint32_t etag_etype;
7517
7518         if (hw->mac.type != ixgbe_mac_X550 &&
7519             hw->mac.type != ixgbe_mac_X550EM_x &&
7520             hw->mac.type != ixgbe_mac_X550EM_a) {
7521                 return -ENOTSUP;
7522         }
7523
7524         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7525         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7526         etag_etype |= ether_type;
7527         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7528         IXGBE_WRITE_FLUSH(hw);
7529
7530         return 0;
7531 }
7532
7533 /* Config l2 tunnel ether type */
7534 static int
7535 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7536                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7537 {
7538         int ret = 0;
7539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7540         struct ixgbe_l2_tn_info *l2_tn_info =
7541                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7542
7543         if (l2_tunnel == NULL)
7544                 return -EINVAL;
7545
7546         switch (l2_tunnel->l2_tunnel_type) {
7547         case RTE_L2_TUNNEL_TYPE_E_TAG:
7548                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7549                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7550                 break;
7551         default:
7552                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7553                 ret = -EINVAL;
7554                 break;
7555         }
7556
7557         return ret;
7558 }
7559
7560 /* Enable e-tag tunnel */
7561 static int
7562 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7563 {
7564         uint32_t etag_etype;
7565
7566         if (hw->mac.type != ixgbe_mac_X550 &&
7567             hw->mac.type != ixgbe_mac_X550EM_x &&
7568             hw->mac.type != ixgbe_mac_X550EM_a) {
7569                 return -ENOTSUP;
7570         }
7571
7572         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7573         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7574         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7575         IXGBE_WRITE_FLUSH(hw);
7576
7577         return 0;
7578 }
7579
7580 /* Enable l2 tunnel */
7581 static int
7582 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7583                            enum rte_eth_tunnel_type l2_tunnel_type)
7584 {
7585         int ret = 0;
7586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7587         struct ixgbe_l2_tn_info *l2_tn_info =
7588                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7589
7590         switch (l2_tunnel_type) {
7591         case RTE_L2_TUNNEL_TYPE_E_TAG:
7592                 l2_tn_info->e_tag_en = TRUE;
7593                 ret = ixgbe_e_tag_enable(hw);
7594                 break;
7595         default:
7596                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7597                 ret = -EINVAL;
7598                 break;
7599         }
7600
7601         return ret;
7602 }
7603
7604 /* Disable e-tag tunnel */
7605 static int
7606 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7607 {
7608         uint32_t etag_etype;
7609
7610         if (hw->mac.type != ixgbe_mac_X550 &&
7611             hw->mac.type != ixgbe_mac_X550EM_x &&
7612             hw->mac.type != ixgbe_mac_X550EM_a) {
7613                 return -ENOTSUP;
7614         }
7615
7616         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7617         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7618         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7619         IXGBE_WRITE_FLUSH(hw);
7620
7621         return 0;
7622 }
7623
7624 /* Disable l2 tunnel */
7625 static int
7626 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7627                             enum rte_eth_tunnel_type l2_tunnel_type)
7628 {
7629         int ret = 0;
7630         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7631         struct ixgbe_l2_tn_info *l2_tn_info =
7632                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7633
7634         switch (l2_tunnel_type) {
7635         case RTE_L2_TUNNEL_TYPE_E_TAG:
7636                 l2_tn_info->e_tag_en = FALSE;
7637                 ret = ixgbe_e_tag_disable(hw);
7638                 break;
7639         default:
7640                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7641                 ret = -EINVAL;
7642                 break;
7643         }
7644
7645         return ret;
7646 }
7647
7648 static int
7649 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7650                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7651 {
7652         int ret = 0;
7653         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7654         uint32_t i, rar_entries;
7655         uint32_t rar_low, rar_high;
7656
7657         if (hw->mac.type != ixgbe_mac_X550 &&
7658             hw->mac.type != ixgbe_mac_X550EM_x &&
7659             hw->mac.type != ixgbe_mac_X550EM_a) {
7660                 return -ENOTSUP;
7661         }
7662
7663         rar_entries = ixgbe_get_num_rx_addrs(hw);
7664
7665         for (i = 1; i < rar_entries; i++) {
7666                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7667                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7668                 if ((rar_high & IXGBE_RAH_AV) &&
7669                     (rar_high & IXGBE_RAH_ADTYPE) &&
7670                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7671                      l2_tunnel->tunnel_id)) {
7672                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7673                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7674
7675                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7676
7677                         return ret;
7678                 }
7679         }
7680
7681         return ret;
7682 }
7683
7684 static int
7685 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7686                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7687 {
7688         int ret = 0;
7689         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7690         uint32_t i, rar_entries;
7691         uint32_t rar_low, rar_high;
7692
7693         if (hw->mac.type != ixgbe_mac_X550 &&
7694             hw->mac.type != ixgbe_mac_X550EM_x &&
7695             hw->mac.type != ixgbe_mac_X550EM_a) {
7696                 return -ENOTSUP;
7697         }
7698
7699         /* One entry for one tunnel. Try to remove potential existing entry. */
7700         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7701
7702         rar_entries = ixgbe_get_num_rx_addrs(hw);
7703
7704         for (i = 1; i < rar_entries; i++) {
7705                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7706                 if (rar_high & IXGBE_RAH_AV) {
7707                         continue;
7708                 } else {
7709                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7710                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7711                         rar_low = l2_tunnel->tunnel_id;
7712
7713                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7714                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7715
7716                         return ret;
7717                 }
7718         }
7719
7720         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7721                      " Please remove a rule before adding a new one.");
7722         return -EINVAL;
7723 }
7724
7725 static inline struct ixgbe_l2_tn_filter *
7726 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7727                           struct ixgbe_l2_tn_key *key)
7728 {
7729         int ret;
7730
7731         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7732         if (ret < 0)
7733                 return NULL;
7734
7735         return l2_tn_info->hash_map[ret];
7736 }
7737
7738 static inline int
7739 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7740                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7741 {
7742         int ret;
7743
7744         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7745                                &l2_tn_filter->key);
7746
7747         if (ret < 0) {
7748                 PMD_DRV_LOG(ERR,
7749                             "Failed to insert L2 tunnel filter"
7750                             " to hash table %d!",
7751                             ret);
7752                 return ret;
7753         }
7754
7755         l2_tn_info->hash_map[ret] = l2_tn_filter;
7756
7757         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7758
7759         return 0;
7760 }
7761
7762 static inline int
7763 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7764                           struct ixgbe_l2_tn_key *key)
7765 {
7766         int ret;
7767         struct ixgbe_l2_tn_filter *l2_tn_filter;
7768
7769         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7770
7771         if (ret < 0) {
7772                 PMD_DRV_LOG(ERR,
7773                             "No such L2 tunnel filter to delete %d!",
7774                             ret);
7775                 return ret;
7776         }
7777
7778         l2_tn_filter = l2_tn_info->hash_map[ret];
7779         l2_tn_info->hash_map[ret] = NULL;
7780
7781         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7782         rte_free(l2_tn_filter);
7783
7784         return 0;
7785 }
7786
7787 /* Add l2 tunnel filter */
7788 int
7789 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7790                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7791                                bool restore)
7792 {
7793         int ret;
7794         struct ixgbe_l2_tn_info *l2_tn_info =
7795                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7796         struct ixgbe_l2_tn_key key;
7797         struct ixgbe_l2_tn_filter *node;
7798
7799         if (!restore) {
7800                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7801                 key.tn_id = l2_tunnel->tunnel_id;
7802
7803                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7804
7805                 if (node) {
7806                         PMD_DRV_LOG(ERR,
7807                                     "The L2 tunnel filter already exists!");
7808                         return -EINVAL;
7809                 }
7810
7811                 node = rte_zmalloc("ixgbe_l2_tn",
7812                                    sizeof(struct ixgbe_l2_tn_filter),
7813                                    0);
7814                 if (!node)
7815                         return -ENOMEM;
7816
7817                 rte_memcpy(&node->key,
7818                                  &key,
7819                                  sizeof(struct ixgbe_l2_tn_key));
7820                 node->pool = l2_tunnel->pool;
7821                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7822                 if (ret < 0) {
7823                         rte_free(node);
7824                         return ret;
7825                 }
7826         }
7827
7828         switch (l2_tunnel->l2_tunnel_type) {
7829         case RTE_L2_TUNNEL_TYPE_E_TAG:
7830                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7831                 break;
7832         default:
7833                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7834                 ret = -EINVAL;
7835                 break;
7836         }
7837
7838         if ((!restore) && (ret < 0))
7839                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7840
7841         return ret;
7842 }
7843
7844 /* Delete l2 tunnel filter */
7845 int
7846 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7847                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7848 {
7849         int ret;
7850         struct ixgbe_l2_tn_info *l2_tn_info =
7851                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7852         struct ixgbe_l2_tn_key key;
7853
7854         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7855         key.tn_id = l2_tunnel->tunnel_id;
7856         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7857         if (ret < 0)
7858                 return ret;
7859
7860         switch (l2_tunnel->l2_tunnel_type) {
7861         case RTE_L2_TUNNEL_TYPE_E_TAG:
7862                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7863                 break;
7864         default:
7865                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7866                 ret = -EINVAL;
7867                 break;
7868         }
7869
7870         return ret;
7871 }
7872
7873 /**
7874  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7875  * @dev: pointer to rte_eth_dev structure
7876  * @filter_op:operation will be taken.
7877  * @arg: a pointer to specific structure corresponding to the filter_op
7878  */
7879 static int
7880 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7881                                   enum rte_filter_op filter_op,
7882                                   void *arg)
7883 {
7884         int ret;
7885
7886         if (filter_op == RTE_ETH_FILTER_NOP)
7887                 return 0;
7888
7889         if (arg == NULL) {
7890                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7891                             filter_op);
7892                 return -EINVAL;
7893         }
7894
7895         switch (filter_op) {
7896         case RTE_ETH_FILTER_ADD:
7897                 ret = ixgbe_dev_l2_tunnel_filter_add
7898                         (dev,
7899                          (struct rte_eth_l2_tunnel_conf *)arg,
7900                          FALSE);
7901                 break;
7902         case RTE_ETH_FILTER_DELETE:
7903                 ret = ixgbe_dev_l2_tunnel_filter_del
7904                         (dev,
7905                          (struct rte_eth_l2_tunnel_conf *)arg);
7906                 break;
7907         default:
7908                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7909                 ret = -EINVAL;
7910                 break;
7911         }
7912         return ret;
7913 }
7914
7915 static int
7916 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7917 {
7918         int ret = 0;
7919         uint32_t ctrl;
7920         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7921
7922         if (hw->mac.type != ixgbe_mac_X550 &&
7923             hw->mac.type != ixgbe_mac_X550EM_x &&
7924             hw->mac.type != ixgbe_mac_X550EM_a) {
7925                 return -ENOTSUP;
7926         }
7927
7928         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7929         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7930         if (en)
7931                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7932         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7933
7934         return ret;
7935 }
7936
7937 /* Enable l2 tunnel forwarding */
7938 static int
7939 ixgbe_dev_l2_tunnel_forwarding_enable
7940         (struct rte_eth_dev *dev,
7941          enum rte_eth_tunnel_type l2_tunnel_type)
7942 {
7943         struct ixgbe_l2_tn_info *l2_tn_info =
7944                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7945         int ret = 0;
7946
7947         switch (l2_tunnel_type) {
7948         case RTE_L2_TUNNEL_TYPE_E_TAG:
7949                 l2_tn_info->e_tag_fwd_en = TRUE;
7950                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7951                 break;
7952         default:
7953                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7954                 ret = -EINVAL;
7955                 break;
7956         }
7957
7958         return ret;
7959 }
7960
7961 /* Disable l2 tunnel forwarding */
7962 static int
7963 ixgbe_dev_l2_tunnel_forwarding_disable
7964         (struct rte_eth_dev *dev,
7965          enum rte_eth_tunnel_type l2_tunnel_type)
7966 {
7967         struct ixgbe_l2_tn_info *l2_tn_info =
7968                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7969         int ret = 0;
7970
7971         switch (l2_tunnel_type) {
7972         case RTE_L2_TUNNEL_TYPE_E_TAG:
7973                 l2_tn_info->e_tag_fwd_en = FALSE;
7974                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7975                 break;
7976         default:
7977                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7978                 ret = -EINVAL;
7979                 break;
7980         }
7981
7982         return ret;
7983 }
7984
7985 static int
7986 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7987                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7988                              bool en)
7989 {
7990         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7991         int ret = 0;
7992         uint32_t vmtir, vmvir;
7993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7994
7995         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7996                 PMD_DRV_LOG(ERR,
7997                             "VF id %u should be less than %u",
7998                             l2_tunnel->vf_id,
7999                             pci_dev->max_vfs);
8000                 return -EINVAL;
8001         }
8002
8003         if (hw->mac.type != ixgbe_mac_X550 &&
8004             hw->mac.type != ixgbe_mac_X550EM_x &&
8005             hw->mac.type != ixgbe_mac_X550EM_a) {
8006                 return -ENOTSUP;
8007         }
8008
8009         if (en)
8010                 vmtir = l2_tunnel->tunnel_id;
8011         else
8012                 vmtir = 0;
8013
8014         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8015
8016         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8017         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8018         if (en)
8019                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8020         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8021
8022         return ret;
8023 }
8024
8025 /* Enable l2 tunnel tag insertion */
8026 static int
8027 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8028                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8029 {
8030         int ret = 0;
8031
8032         switch (l2_tunnel->l2_tunnel_type) {
8033         case RTE_L2_TUNNEL_TYPE_E_TAG:
8034                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8035                 break;
8036         default:
8037                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8038                 ret = -EINVAL;
8039                 break;
8040         }
8041
8042         return ret;
8043 }
8044
8045 /* Disable l2 tunnel tag insertion */
8046 static int
8047 ixgbe_dev_l2_tunnel_insertion_disable
8048         (struct rte_eth_dev *dev,
8049          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8050 {
8051         int ret = 0;
8052
8053         switch (l2_tunnel->l2_tunnel_type) {
8054         case RTE_L2_TUNNEL_TYPE_E_TAG:
8055                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8056                 break;
8057         default:
8058                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8059                 ret = -EINVAL;
8060                 break;
8061         }
8062
8063         return ret;
8064 }
8065
8066 static int
8067 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8068                              bool en)
8069 {
8070         int ret = 0;
8071         uint32_t qde;
8072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8073
8074         if (hw->mac.type != ixgbe_mac_X550 &&
8075             hw->mac.type != ixgbe_mac_X550EM_x &&
8076             hw->mac.type != ixgbe_mac_X550EM_a) {
8077                 return -ENOTSUP;
8078         }
8079
8080         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8081         if (en)
8082                 qde |= IXGBE_QDE_STRIP_TAG;
8083         else
8084                 qde &= ~IXGBE_QDE_STRIP_TAG;
8085         qde &= ~IXGBE_QDE_READ;
8086         qde |= IXGBE_QDE_WRITE;
8087         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8088
8089         return ret;
8090 }
8091
8092 /* Enable l2 tunnel tag stripping */
8093 static int
8094 ixgbe_dev_l2_tunnel_stripping_enable
8095         (struct rte_eth_dev *dev,
8096          enum rte_eth_tunnel_type l2_tunnel_type)
8097 {
8098         int ret = 0;
8099
8100         switch (l2_tunnel_type) {
8101         case RTE_L2_TUNNEL_TYPE_E_TAG:
8102                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8103                 break;
8104         default:
8105                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8106                 ret = -EINVAL;
8107                 break;
8108         }
8109
8110         return ret;
8111 }
8112
8113 /* Disable l2 tunnel tag stripping */
8114 static int
8115 ixgbe_dev_l2_tunnel_stripping_disable
8116         (struct rte_eth_dev *dev,
8117          enum rte_eth_tunnel_type l2_tunnel_type)
8118 {
8119         int ret = 0;
8120
8121         switch (l2_tunnel_type) {
8122         case RTE_L2_TUNNEL_TYPE_E_TAG:
8123                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8124                 break;
8125         default:
8126                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8127                 ret = -EINVAL;
8128                 break;
8129         }
8130
8131         return ret;
8132 }
8133
8134 /* Enable/disable l2 tunnel offload functions */
8135 static int
8136 ixgbe_dev_l2_tunnel_offload_set
8137         (struct rte_eth_dev *dev,
8138          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8139          uint32_t mask,
8140          uint8_t en)
8141 {
8142         int ret = 0;
8143
8144         if (l2_tunnel == NULL)
8145                 return -EINVAL;
8146
8147         ret = -EINVAL;
8148         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8149                 if (en)
8150                         ret = ixgbe_dev_l2_tunnel_enable(
8151                                 dev,
8152                                 l2_tunnel->l2_tunnel_type);
8153                 else
8154                         ret = ixgbe_dev_l2_tunnel_disable(
8155                                 dev,
8156                                 l2_tunnel->l2_tunnel_type);
8157         }
8158
8159         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8160                 if (en)
8161                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8162                                 dev,
8163                                 l2_tunnel);
8164                 else
8165                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8166                                 dev,
8167                                 l2_tunnel);
8168         }
8169
8170         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8171                 if (en)
8172                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8173                                 dev,
8174                                 l2_tunnel->l2_tunnel_type);
8175                 else
8176                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8177                                 dev,
8178                                 l2_tunnel->l2_tunnel_type);
8179         }
8180
8181         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8182                 if (en)
8183                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8184                                 dev,
8185                                 l2_tunnel->l2_tunnel_type);
8186                 else
8187                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8188                                 dev,
8189                                 l2_tunnel->l2_tunnel_type);
8190         }
8191
8192         return ret;
8193 }
8194
8195 static int
8196 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8197                         uint16_t port)
8198 {
8199         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8200         IXGBE_WRITE_FLUSH(hw);
8201
8202         return 0;
8203 }
8204
8205 /* There's only one register for VxLAN UDP port.
8206  * So, we cannot add several ports. Will update it.
8207  */
8208 static int
8209 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8210                      uint16_t port)
8211 {
8212         if (port == 0) {
8213                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8214                 return -EINVAL;
8215         }
8216
8217         return ixgbe_update_vxlan_port(hw, port);
8218 }
8219
8220 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8221  * UDP port, it must have a value.
8222  * So, will reset it to the original value 0.
8223  */
8224 static int
8225 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8226                      uint16_t port)
8227 {
8228         uint16_t cur_port;
8229
8230         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8231
8232         if (cur_port != port) {
8233                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8234                 return -EINVAL;
8235         }
8236
8237         return ixgbe_update_vxlan_port(hw, 0);
8238 }
8239
8240 /* Add UDP tunneling port */
8241 static int
8242 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8243                               struct rte_eth_udp_tunnel *udp_tunnel)
8244 {
8245         int ret = 0;
8246         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8247
8248         if (hw->mac.type != ixgbe_mac_X550 &&
8249             hw->mac.type != ixgbe_mac_X550EM_x &&
8250             hw->mac.type != ixgbe_mac_X550EM_a) {
8251                 return -ENOTSUP;
8252         }
8253
8254         if (udp_tunnel == NULL)
8255                 return -EINVAL;
8256
8257         switch (udp_tunnel->prot_type) {
8258         case RTE_TUNNEL_TYPE_VXLAN:
8259                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8260                 break;
8261
8262         case RTE_TUNNEL_TYPE_GENEVE:
8263         case RTE_TUNNEL_TYPE_TEREDO:
8264                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8265                 ret = -EINVAL;
8266                 break;
8267
8268         default:
8269                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8270                 ret = -EINVAL;
8271                 break;
8272         }
8273
8274         return ret;
8275 }
8276
8277 /* Remove UDP tunneling port */
8278 static int
8279 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8280                               struct rte_eth_udp_tunnel *udp_tunnel)
8281 {
8282         int ret = 0;
8283         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8284
8285         if (hw->mac.type != ixgbe_mac_X550 &&
8286             hw->mac.type != ixgbe_mac_X550EM_x &&
8287             hw->mac.type != ixgbe_mac_X550EM_a) {
8288                 return -ENOTSUP;
8289         }
8290
8291         if (udp_tunnel == NULL)
8292                 return -EINVAL;
8293
8294         switch (udp_tunnel->prot_type) {
8295         case RTE_TUNNEL_TYPE_VXLAN:
8296                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8297                 break;
8298         case RTE_TUNNEL_TYPE_GENEVE:
8299         case RTE_TUNNEL_TYPE_TEREDO:
8300                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8301                 ret = -EINVAL;
8302                 break;
8303         default:
8304                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8305                 ret = -EINVAL;
8306                 break;
8307         }
8308
8309         return ret;
8310 }
8311
8312 static void
8313 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8314 {
8315         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8316
8317         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8318 }
8319
8320 static void
8321 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8322 {
8323         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8324
8325         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8326 }
8327
8328 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8329 {
8330         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8331         u32 in_msg = 0;
8332
8333         /* peek the message first */
8334         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8335
8336         /* PF reset VF event */
8337         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8338                 /* dummy mbx read to ack pf */
8339                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8340                         return;
8341                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8342                                               NULL);
8343         }
8344 }
8345
8346 static int
8347 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8348 {
8349         uint32_t eicr;
8350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8351         struct ixgbe_interrupt *intr =
8352                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8353         ixgbevf_intr_disable(dev);
8354
8355         /* read-on-clear nic registers here */
8356         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8357         intr->flags = 0;
8358
8359         /* only one misc vector supported - mailbox */
8360         eicr &= IXGBE_VTEICR_MASK;
8361         if (eicr == IXGBE_MISC_VEC_ID)
8362                 intr->flags |= IXGBE_FLAG_MAILBOX;
8363
8364         return 0;
8365 }
8366
8367 static int
8368 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8369 {
8370         struct ixgbe_interrupt *intr =
8371                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8372
8373         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8374                 ixgbevf_mbx_process(dev);
8375                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8376         }
8377
8378         ixgbevf_intr_enable(dev);
8379
8380         return 0;
8381 }
8382
8383 static void
8384 ixgbevf_dev_interrupt_handler(void *param)
8385 {
8386         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8387
8388         ixgbevf_dev_interrupt_get_status(dev);
8389         ixgbevf_dev_interrupt_action(dev);
8390 }
8391
8392 /**
8393  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8394  *  @hw: pointer to hardware structure
8395  *
8396  *  Stops the transmit data path and waits for the HW to internally empty
8397  *  the Tx security block
8398  **/
8399 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8400 {
8401 #define IXGBE_MAX_SECTX_POLL 40
8402
8403         int i;
8404         int sectxreg;
8405
8406         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8407         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8408         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8409         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8410                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8411                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8412                         break;
8413                 /* Use interrupt-safe sleep just in case */
8414                 usec_delay(1000);
8415         }
8416
8417         /* For informational purposes only */
8418         if (i >= IXGBE_MAX_SECTX_POLL)
8419                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8420                          "path fully disabled.  Continuing with init.");
8421
8422         return IXGBE_SUCCESS;
8423 }
8424
8425 /**
8426  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8427  *  @hw: pointer to hardware structure
8428  *
8429  *  Enables the transmit data path.
8430  **/
8431 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8432 {
8433         uint32_t sectxreg;
8434
8435         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8436         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8437         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8438         IXGBE_WRITE_FLUSH(hw);
8439
8440         return IXGBE_SUCCESS;
8441 }
8442
8443 /* restore n-tuple filter */
8444 static inline void
8445 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8446 {
8447         struct ixgbe_filter_info *filter_info =
8448                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8449         struct ixgbe_5tuple_filter *node;
8450
8451         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8452                 ixgbe_inject_5tuple_filter(dev, node);
8453         }
8454 }
8455
8456 /* restore ethernet type filter */
8457 static inline void
8458 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8459 {
8460         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8461         struct ixgbe_filter_info *filter_info =
8462                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8463         int i;
8464
8465         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8466                 if (filter_info->ethertype_mask & (1 << i)) {
8467                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8468                                         filter_info->ethertype_filters[i].etqf);
8469                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8470                                         filter_info->ethertype_filters[i].etqs);
8471                         IXGBE_WRITE_FLUSH(hw);
8472                 }
8473         }
8474 }
8475
8476 /* restore SYN filter */
8477 static inline void
8478 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8479 {
8480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8481         struct ixgbe_filter_info *filter_info =
8482                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8483         uint32_t synqf;
8484
8485         synqf = filter_info->syn_info;
8486
8487         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8488                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8489                 IXGBE_WRITE_FLUSH(hw);
8490         }
8491 }
8492
8493 /* restore L2 tunnel filter */
8494 static inline void
8495 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8496 {
8497         struct ixgbe_l2_tn_info *l2_tn_info =
8498                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8499         struct ixgbe_l2_tn_filter *node;
8500         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8501
8502         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8503                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8504                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8505                 l2_tn_conf.pool           = node->pool;
8506                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8507         }
8508 }
8509
8510 /* restore rss filter */
8511 static inline void
8512 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8513 {
8514         struct ixgbe_filter_info *filter_info =
8515                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8516
8517         if (filter_info->rss_info.conf.queue_num)
8518                 ixgbe_config_rss_filter(dev,
8519                         &filter_info->rss_info, TRUE);
8520 }
8521
8522 static int
8523 ixgbe_filter_restore(struct rte_eth_dev *dev)
8524 {
8525         ixgbe_ntuple_filter_restore(dev);
8526         ixgbe_ethertype_filter_restore(dev);
8527         ixgbe_syn_filter_restore(dev);
8528         ixgbe_fdir_filter_restore(dev);
8529         ixgbe_l2_tn_filter_restore(dev);
8530         ixgbe_rss_filter_restore(dev);
8531
8532         return 0;
8533 }
8534
8535 static void
8536 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8537 {
8538         struct ixgbe_l2_tn_info *l2_tn_info =
8539                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8540         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8541
8542         if (l2_tn_info->e_tag_en)
8543                 (void)ixgbe_e_tag_enable(hw);
8544
8545         if (l2_tn_info->e_tag_fwd_en)
8546                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8547
8548         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8549 }
8550
8551 /* remove all the n-tuple filters */
8552 void
8553 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8554 {
8555         struct ixgbe_filter_info *filter_info =
8556                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8557         struct ixgbe_5tuple_filter *p_5tuple;
8558
8559         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8560                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8561 }
8562
8563 /* remove all the ether type filters */
8564 void
8565 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8566 {
8567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8568         struct ixgbe_filter_info *filter_info =
8569                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8570         int i;
8571
8572         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8573                 if (filter_info->ethertype_mask & (1 << i) &&
8574                     !filter_info->ethertype_filters[i].conf) {
8575                         (void)ixgbe_ethertype_filter_remove(filter_info,
8576                                                             (uint8_t)i);
8577                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8578                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8579                         IXGBE_WRITE_FLUSH(hw);
8580                 }
8581         }
8582 }
8583
8584 /* remove the SYN filter */
8585 void
8586 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8587 {
8588         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8589         struct ixgbe_filter_info *filter_info =
8590                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8591
8592         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8593                 filter_info->syn_info = 0;
8594
8595                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8596                 IXGBE_WRITE_FLUSH(hw);
8597         }
8598 }
8599
8600 /* remove all the L2 tunnel filters */
8601 int
8602 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8603 {
8604         struct ixgbe_l2_tn_info *l2_tn_info =
8605                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8606         struct ixgbe_l2_tn_filter *l2_tn_filter;
8607         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8608         int ret = 0;
8609
8610         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8611                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8612                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8613                 l2_tn_conf.pool           = l2_tn_filter->pool;
8614                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8615                 if (ret < 0)
8616                         return ret;
8617         }
8618
8619         return 0;
8620 }
8621
8622 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8623 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8624 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8625 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8626 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8627 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8628
8629 RTE_INIT(ixgbe_init_log)
8630 {
8631         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8632         if (ixgbe_logtype_init >= 0)
8633                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8634         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8635         if (ixgbe_logtype_driver >= 0)
8636                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8637 }