drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64 #include <rte_hash_crc.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 158 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 168 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static int
 186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 187                 uint64_t *values, unsigned int n);
 188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names,
 192         unsigned int size);
 193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 195 static int ixgbe_dev_xstats_get_names_by_id(
 196         struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names,
 198         const uint64_t *ids,
 199         unsigned int limit);
 200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 201                                              uint16_t queue_id,
 202                                              uint8_t stat_idx,
 203                                              uint8_t is_rx);
 204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 205                                  size_t fw_size);
 206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_dev_info *dev_info);
 208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 210                                  struct rte_eth_dev_info *dev_info);
 211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 212
 213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 216                                enum rte_vlan_type vlan_type,
 217                                uint16_t tpid_id);
 218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 219                 uint16_t queue, bool on);
 220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 221                 int on);
 222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 227
 228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 233                                struct rte_eth_fc_conf *fc_conf);
 234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 235                 struct rte_eth_pfc_conf *pfc_conf);
 236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 237                         struct rte_eth_rss_reta_entry64 *reta_conf,
 238                         uint16_t reta_size);
 239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_reta_entry64 *reta_conf,
 241                         uint16_t reta_size);
 242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 248                                       struct rte_intr_handle *handle);
 249 static void ixgbe_dev_interrupt_handler(void *param);
 250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 252                          uint32_t index, uint32_t pool);
 253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 255                                            struct ether_addr *mac_addr);
 256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 257 static bool is_device_supported(struct rte_eth_dev *dev,
 258                                 struct rte_pci_driver *drv);
 259
 260 /* For Virtual Function support */
 261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 263 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 264 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 265 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 266                                    int wait_to_complete);
 267 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 268 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 269 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 270 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 271 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 272                 struct rte_eth_stats *stats);
 273 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 274 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 275                 uint16_t vlan_id, int on);
 276 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 277                 uint16_t queue, int on);
 278 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 279 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 280 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 281                                             uint16_t queue_id);
 282 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 283                                              uint16_t queue_id);
 284 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 285                                  uint8_t queue, uint8_t msix_vector);
 286 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 287 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 288 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 289
 290 /* For Eth VMDQ APIs support */
 291 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 292                 ether_addr * mac_addr, uint8_t on);
 293 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 294 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 295                 struct rte_eth_mirror_conf *mirror_conf,
 296                 uint8_t rule_id, uint8_t on);
 297 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 298                 uint8_t rule_id);
 299 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 300                                           uint16_t queue_id);
 301 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 302                                            uint16_t queue_id);
 303 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 304                                uint8_t queue, uint8_t msix_vector);
 305 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 306
 307 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 308                 uint16_t queue_idx, uint16_t tx_rate);
 309
 310 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 311                                 struct ether_addr *mac_addr,
 312                                 uint32_t index, uint32_t pool);
 313 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 314 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 315                                              struct ether_addr *mac_addr);
 316 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 317                         struct rte_eth_syn_filter *filter);
 318 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 319                         enum rte_filter_op filter_op,
 320                         void *arg);
 321 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 322                         struct ixgbe_5tuple_filter *filter);
 323 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 324                         struct ixgbe_5tuple_filter *filter);
 325 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 326                                 enum rte_filter_op filter_op,
 327                                 void *arg);
 328 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 329                         struct rte_eth_ntuple_filter *filter);
 330 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 331                                 enum rte_filter_op filter_op,
 332                                 void *arg);
 333 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 334                         struct rte_eth_ethertype_filter *filter);
 335 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 336                      enum rte_filter_type filter_type,
 337                      enum rte_filter_op filter_op,
 338                      void *arg);
 339 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 340
 341 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 342                                       struct ether_addr *mc_addr_set,
 343                                       uint32_t nb_mc_addr);
 344 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 345                                    struct rte_eth_dcb_info *dcb_info);
 346
 347 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 349                             struct rte_dev_reg_info *regs);
 350 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 351 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 354                                 struct rte_dev_eeprom_info *eeprom);
 355
 356 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 357 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 358                                 struct rte_dev_reg_info *regs);
 359
 360 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 361 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 362 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 363                                             struct timespec *timestamp,
 364                                             uint32_t flags);
 365 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 366                                             struct timespec *timestamp);
 367 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 368 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 369                                    struct timespec *timestamp);
 370 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 371                                    const struct timespec *timestamp);
 372 static void ixgbevf_dev_interrupt_handler(void *param);
 373
 374 static int ixgbe_dev_l2_tunnel_eth_type_conf
 375         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 376 static int ixgbe_dev_l2_tunnel_offload_set
 377         (struct rte_eth_dev *dev,
 378          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 379          uint32_t mask,
 380          uint8_t en);
 381 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 382                                              enum rte_filter_op filter_op,
 383                                              void *arg);
 384
 385 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 386                                          struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 388                                          struct rte_eth_udp_tunnel *udp_tunnel);
 389 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 390 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 391
 392 /*
 393  * Define VF Stats MACRO for Non "cleared on read" register
 394  */
 395 #define UPDATE_VF_STAT(reg, last, cur)                          \
 396 {                                                               \
 397         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 398         cur += (latest - last) & UINT_MAX;                      \
 399         last = latest;                                          \
 400 }
 401
 402 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 403 {                                                                \
 404         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 405         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 406         u64 latest = ((new_msb << 32) | new_lsb);                \
 407         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 408         last = latest;                                           \
 409 }
 410
 411 #define IXGBE_SET_HWSTRIP(h, q) do {\
 412                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 413                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 414                 (h)->bitmap[idx] |= 1 << bit;\
 415         } while (0)
 416
 417 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 418                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 419                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 420                 (h)->bitmap[idx] &= ~(1 << bit);\
 421         } while (0)
 422
 423 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 424                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 425                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 426                 (r) = (h)->bitmap[idx] >> bit & 1;\
 427         } while (0)
 428
 429 /*
 430  * The set of PCI devices this driver supports
 431  */
 432 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 486 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 488 #endif
 489         { .vendor_id = 0, /* sentinel */ },
 490 };
 491
 492 /*
 493  * The set of PCI devices this driver supports (for 82599 VF)
 494  */
 495 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 506         { .vendor_id = 0, /* sentinel */ },
 507 };
 508
 509 static const struct rte_eth_desc_lim rx_desc_lim = {
 510         .nb_max = IXGBE_MAX_RING_DESC,
 511         .nb_min = IXGBE_MIN_RING_DESC,
 512         .nb_align = IXGBE_RXD_ALIGN,
 513 };
 514
 515 static const struct rte_eth_desc_lim tx_desc_lim = {
 516         .nb_max = IXGBE_MAX_RING_DESC,
 517         .nb_min = IXGBE_MIN_RING_DESC,
 518         .nb_align = IXGBE_TXD_ALIGN,
 519         .nb_seg_max = IXGBE_TX_MAX_SEG,
 520         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 521 };
 522
 523 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 524         .dev_configure        = ixgbe_dev_configure,
 525         .dev_start            = ixgbe_dev_start,
 526         .dev_stop             = ixgbe_dev_stop,
 527         .dev_set_link_up    = ixgbe_dev_set_link_up,
 528         .dev_set_link_down  = ixgbe_dev_set_link_down,
 529         .dev_close            = ixgbe_dev_close,
 530         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 531         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 532         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 533         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 534         .link_update          = ixgbe_dev_link_update,
 535         .stats_get            = ixgbe_dev_stats_get,
 536         .xstats_get           = ixgbe_dev_xstats_get,
 537         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 538         .stats_reset          = ixgbe_dev_stats_reset,
 539         .xstats_reset         = ixgbe_dev_xstats_reset,
 540         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 541         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 542         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 543         .fw_version_get       = ixgbe_fw_version_get,
 544         .dev_infos_get        = ixgbe_dev_info_get,
 545         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 546         .mtu_set              = ixgbe_dev_mtu_set,
 547         .vlan_filter_set      = ixgbe_vlan_filter_set,
 548         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 549         .vlan_offload_set     = ixgbe_vlan_offload_set,
 550         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 551         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 552         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 553         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 554         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 555         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 556         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 557         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 558         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 559         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 560         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 561         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 562         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 563         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 564         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 565         .dev_led_on           = ixgbe_dev_led_on,
 566         .dev_led_off          = ixgbe_dev_led_off,
 567         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 568         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 569         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 570         .mac_addr_add         = ixgbe_add_rar,
 571         .mac_addr_remove      = ixgbe_remove_rar,
 572         .mac_addr_set         = ixgbe_set_default_mac_addr,
 573         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 574         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 575         .mirror_rule_set      = ixgbe_mirror_rule_set,
 576         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 577         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 578         .reta_update          = ixgbe_dev_rss_reta_update,
 579         .reta_query           = ixgbe_dev_rss_reta_query,
 580         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 581         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 582         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 583         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 584         .rxq_info_get         = ixgbe_rxq_info_get,
 585         .txq_info_get         = ixgbe_txq_info_get,
 586         .timesync_enable      = ixgbe_timesync_enable,
 587         .timesync_disable     = ixgbe_timesync_disable,
 588         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 589         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 590         .get_reg              = ixgbe_get_regs,
 591         .get_eeprom_length    = ixgbe_get_eeprom_length,
 592         .get_eeprom           = ixgbe_get_eeprom,
 593         .set_eeprom           = ixgbe_set_eeprom,
 594         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 595         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 596         .timesync_read_time   = ixgbe_timesync_read_time,
 597         .timesync_write_time  = ixgbe_timesync_write_time,
 598         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 599         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 600         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 601         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 602         .tm_ops_get           = ixgbe_tm_ops_get,
 603 };
 604
 605 /*
 606  * dev_ops for virtual function, bare necessities for basic vf
 607  * operation have been implemented
 608  */
 609 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 610         .dev_configure        = ixgbevf_dev_configure,
 611         .dev_start            = ixgbevf_dev_start,
 612         .dev_stop             = ixgbevf_dev_stop,
 613         .link_update          = ixgbevf_dev_link_update,
 614         .stats_get            = ixgbevf_dev_stats_get,
 615         .xstats_get           = ixgbevf_dev_xstats_get,
 616         .stats_reset          = ixgbevf_dev_stats_reset,
 617         .xstats_reset         = ixgbevf_dev_stats_reset,
 618         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 619         .dev_close            = ixgbevf_dev_close,
 620         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 621         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 622         .dev_infos_get        = ixgbevf_dev_info_get,
 623         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 624         .mtu_set              = ixgbevf_dev_set_mtu,
 625         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 626         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 627         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 628         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 629         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 630         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 631         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 632         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 633         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 634         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 635         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 636         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 637         .mac_addr_add         = ixgbevf_add_mac_addr,
 638         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 639         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 640         .rxq_info_get         = ixgbe_rxq_info_get,
 641         .txq_info_get         = ixgbe_txq_info_get,
 642         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 643         .get_reg              = ixgbevf_get_regs,
 644         .reta_update          = ixgbe_dev_rss_reta_update,
 645         .reta_query           = ixgbe_dev_rss_reta_query,
 646         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 647         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 648 };
 649
 650 /* store statistics names and its offset in stats structure */
 651 struct rte_ixgbe_xstats_name_off {
 652         char name[RTE_ETH_XSTATS_NAME_SIZE];
 653         unsigned offset;
 654 };
 655
 656 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 657         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 658         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 659         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 660         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 661         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 662         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 663         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 664         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 665         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 666         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 667         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 668         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 669         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 670         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 671         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 672                 prc1023)},
 673         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 674                 prc1522)},
 675         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 676         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 677         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 678         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 679         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 680         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 681         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 682         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 683         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 684         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 685         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 686         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 687         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 688         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 689         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 690         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 691         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 692                 ptc1023)},
 693         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 694                 ptc1522)},
 695         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 696         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 697         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 698         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 699
 700         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 701                 fdirustat_add)},
 702         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 703                 fdirustat_remove)},
 704         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 705                 fdirfstat_fadd)},
 706         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 707                 fdirfstat_fremove)},
 708         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirmatch)},
 710         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirmiss)},
 712
 713         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 714         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 715         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 716                 fclast)},
 717         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 718         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 719         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 720         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 721         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 722                 fcoe_noddp)},
 723         {"rx_fcoe_no_direct_data_placement_ext_buff",
 724                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 725
 726         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxontxc)},
 728         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxonrxc)},
 730         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 731                 lxofftxc)},
 732         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 733                 lxoffrxc)},
 734         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 735 };
 736
 737 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 738                            sizeof(rte_ixgbe_stats_strings[0]))
 739
 740 /* MACsec statistics */
 741 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 742         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 743                 out_pkts_untagged)},
 744         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 745                 out_pkts_encrypted)},
 746         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 747                 out_pkts_protected)},
 748         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 749                 out_octets_encrypted)},
 750         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 751                 out_octets_protected)},
 752         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_untagged)},
 754         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_badtag)},
 756         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_nosci)},
 758         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_unknownsci)},
 760         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 761                 in_octets_decrypted)},
 762         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 763                 in_octets_validated)},
 764         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_unchecked)},
 766         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_delayed)},
 768         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_late)},
 770         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_ok)},
 772         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_invalid)},
 774         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_notvalid)},
 776         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_unusedsa)},
 778         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_notusingsa)},
 780 };
 781
 782 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 783                            sizeof(rte_ixgbe_macsec_strings[0]))
 784
 785 /* Per-queue statistics */
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 787         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 788         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 789         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 790         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 791 };
 792
 793 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 794                            sizeof(rte_ixgbe_rxq_strings[0]))
 795 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 796
 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 798         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 799         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 800         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 801                 pxon2offc)},
 802 };
 803
 804 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 805                            sizeof(rte_ixgbe_txq_strings[0]))
 806 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 807
 808 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 809         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 810 };
 811
 812 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 813                 sizeof(rte_ixgbevf_stats_strings[0]))
 814
 815 /**
 816  * Atomically reads the link status information from global
 817  * structure rte_eth_dev.
 818  *
 819  * @param dev
 820  *   - Pointer to the structure rte_eth_dev to read from.
 821  *   - Pointer to the buffer to be saved with the link status.
 822  *
 823  * @return
 824  *   - On success, zero.
 825  *   - On failure, negative value.
 826  */
 827 static inline int
 828 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 829                                 struct rte_eth_link *link)
 830 {
 831         struct rte_eth_link *dst = link;
 832         struct rte_eth_link *src = &(dev->data->dev_link);
 833
 834         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 835                                         *(uint64_t *)src) == 0)
 836                 return -1;
 837
 838         return 0;
 839 }
 840
 841 /**
 842  * Atomically writes the link status information into global
 843  * structure rte_eth_dev.
 844  *
 845  * @param dev
 846  *   - Pointer to the structure rte_eth_dev to read from.
 847  *   - Pointer to the buffer to be saved with the link status.
 848  *
 849  * @return
 850  *   - On success, zero.
 851  *   - On failure, negative value.
 852  */
 853 static inline int
 854 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 855                                 struct rte_eth_link *link)
 856 {
 857         struct rte_eth_link *dst = &(dev->data->dev_link);
 858         struct rte_eth_link *src = link;
 859
 860         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 861                                         *(uint64_t *)src) == 0)
 862                 return -1;
 863
 864         return 0;
 865 }
 866
 867 /*
 868  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 869  */
 870 static inline int
 871 ixgbe_is_sfp(struct ixgbe_hw *hw)
 872 {
 873         switch (hw->phy.type) {
 874         case ixgbe_phy_sfp_avago:
 875         case ixgbe_phy_sfp_ftl:
 876         case ixgbe_phy_sfp_intel:
 877         case ixgbe_phy_sfp_unknown:
 878         case ixgbe_phy_sfp_passive_tyco:
 879         case ixgbe_phy_sfp_passive_unknown:
 880                 return 1;
 881         default:
 882                 return 0;
 883         }
 884 }
 885
 886 static inline int32_t
 887 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 888 {
 889         uint32_t ctrl_ext;
 890         int32_t status;
 891
 892         status = ixgbe_reset_hw(hw);
 893
 894         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 895         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 896         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 897         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 898         IXGBE_WRITE_FLUSH(hw);
 899
 900         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 901                 status = IXGBE_SUCCESS;
 902         return status;
 903 }
 904
 905 static inline void
 906 ixgbe_enable_intr(struct rte_eth_dev *dev)
 907 {
 908         struct ixgbe_interrupt *intr =
 909                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 910         struct ixgbe_hw *hw =
 911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 912
 913         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 914         IXGBE_WRITE_FLUSH(hw);
 915 }
 916
 917 /*
 918  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 919  */
 920 static void
 921 ixgbe_disable_intr(struct ixgbe_hw *hw)
 922 {
 923         PMD_INIT_FUNC_TRACE();
 924
 925         if (hw->mac.type == ixgbe_mac_82598EB) {
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 927         } else {
 928                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 930                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 931         }
 932         IXGBE_WRITE_FLUSH(hw);
 933 }
 934
 935 /*
 936  * This function resets queue statistics mapping registers.
 937  * From Niantic datasheet, Initialization of Statistics section:
 938  * "...if software requires the queue counters, the RQSMR and TQSM registers
 939  * must be re-programmed following a device reset.
 940  */
 941 static void
 942 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 943 {
 944         uint32_t i;
 945
 946         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 947                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 948                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 949         }
 950 }
 951
 952
 953 static int
 954 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 955                                   uint16_t queue_id,
 956                                   uint8_t stat_idx,
 957                                   uint8_t is_rx)
 958 {
 959 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 960 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 961 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 962
 963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 964         struct ixgbe_stat_mapping_registers *stat_mappings =
 965                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 966         uint32_t qsmr_mask = 0;
 967         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 968         uint32_t q_map;
 969         uint8_t n, offset;
 970
 971         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 972                 (hw->mac.type != ixgbe_mac_X540) &&
 973                 (hw->mac.type != ixgbe_mac_X550) &&
 974                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 975                 (hw->mac.type != ixgbe_mac_X550EM_a))
 976                 return -ENOSYS;
 977
 978         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 979                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 980                      queue_id, stat_idx);
 981
 982         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 983         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 984                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 985                 return -EIO;
 986         }
 987         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 988
 989         /* Now clear any previous stat_idx set */
 990         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 991         if (!is_rx)
 992                 stat_mappings->tqsm[n] &= ~clearing_mask;
 993         else
 994                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 995
 996         q_map = (uint32_t)stat_idx;
 997         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 998         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 999         if (!is_rx)
1000                 stat_mappings->tqsm[n] |= qsmr_mask;
1001         else
1002                 stat_mappings->rqsmr[n] |= qsmr_mask;
1003
1004         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1005                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1006                      queue_id, stat_idx);
1007         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1008                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1009
1010         /* Now write the mapping in the appropriate register */
1011         if (is_rx) {
1012                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1013                              stat_mappings->rqsmr[n], n);
1014                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1015         } else {
1016                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1017                              stat_mappings->tqsm[n], n);
1018                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1019         }
1020         return 0;
1021 }
1022
1023 static void
1024 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1025 {
1026         struct ixgbe_stat_mapping_registers *stat_mappings =
1027                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1029         int i;
1030
1031         /* write whatever was in stat mapping table to the NIC */
1032         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1033                 /* rx */
1034                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1035
1036                 /* tx */
1037                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1038         }
1039 }
1040
1041 static void
1042 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1043 {
1044         uint8_t i;
1045         struct ixgbe_dcb_tc_config *tc;
1046         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1047
1048         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1049         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1050         for (i = 0; i < dcb_max_tc; i++) {
1051                 tc = &dcb_config->tc_config[i];
1052                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1053                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1054                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1055                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1056                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1057                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1058                 tc->pfc = ixgbe_dcb_pfc_disabled;
1059         }
1060
1061         /* Initialize default user to priority mapping, UPx->TC0 */
1062         tc = &dcb_config->tc_config[0];
1063         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1064         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1065         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1066                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1067                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1068         }
1069         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1070         dcb_config->pfc_mode_enable = false;
1071         dcb_config->vt_mode = true;
1072         dcb_config->round_robin_enable = false;
1073         /* support all DCB capabilities in 82599 */
1074         dcb_config->support.capabilities = 0xFF;
1075
1076         /*we only support 4 Tcs for X540, X550 */
1077         if (hw->mac.type == ixgbe_mac_X540 ||
1078                 hw->mac.type == ixgbe_mac_X550 ||
1079                 hw->mac.type == ixgbe_mac_X550EM_x ||
1080                 hw->mac.type == ixgbe_mac_X550EM_a) {
1081                 dcb_config->num_tcs.pg_tcs = 4;
1082                 dcb_config->num_tcs.pfc_tcs = 4;
1083         }
1084 }
1085
1086 /*
1087  * Ensure that all locks are released before first NVM or PHY access
1088  */
1089 static void
1090 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1091 {
1092         uint16_t mask;
1093
1094         /*
1095          * Phy lock should not fail in this early stage. If this is the case,
1096          * it is due to an improper exit of the application.
1097          * So force the release of the faulty lock. Release of common lock
1098          * is done automatically by swfw_sync function.
1099          */
1100         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1101         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1102                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1103         }
1104         ixgbe_release_swfw_semaphore(hw, mask);
1105
1106         /*
1107          * These ones are more tricky since they are common to all ports; but
1108          * swfw_sync retries last long enough (1s) to be almost sure that if
1109          * lock can not be taken it is due to an improper lock of the
1110          * semaphore.
1111          */
1112         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1113         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1114                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1115         }
1116         ixgbe_release_swfw_semaphore(hw, mask);
1117 }
1118
1119 /*
1120  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1121  * It returns 0 on success.
1122  */
1123 static int
1124 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1125 {
1126         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1127         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1128         struct ixgbe_hw *hw =
1129                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1130         struct ixgbe_vfta *shadow_vfta =
1131                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1132         struct ixgbe_hwstrip *hwstrip =
1133                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1134         struct ixgbe_dcb_config *dcb_config =
1135                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1136         struct ixgbe_filter_info *filter_info =
1137                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1138         struct ixgbe_bw_conf *bw_conf =
1139                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1140         uint32_t ctrl_ext;
1141         uint16_t csum;
1142         int diag, i;
1143
1144         PMD_INIT_FUNC_TRACE();
1145
1146         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1147         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1148         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1149         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1150
1151         /*
1152          * For secondary processes, we don't initialise any further as primary
1153          * has already done this work. Only check we don't need a different
1154          * RX and TX function.
1155          */
1156         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1157                 struct ixgbe_tx_queue *txq;
1158                 /* TX queue function in primary, set by last queue initialized
1159                  * Tx queue may not initialized by primary process
1160                  */
1161                 if (eth_dev->data->tx_queues) {
1162                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1163                         ixgbe_set_tx_function(eth_dev, txq);
1164                 } else {
1165                         /* Use default TX function if we get here */
1166                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1167                                      "Using default TX function.");
1168                 }
1169
1170                 ixgbe_set_rx_function(eth_dev);
1171
1172                 return 0;
1173         }
1174
1175         rte_eth_copy_pci_info(eth_dev, pci_dev);
1176         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1177
1178         /* Vendor and Device ID need to be set before init of shared code */
1179         hw->device_id = pci_dev->id.device_id;
1180         hw->vendor_id = pci_dev->id.vendor_id;
1181         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1182         hw->allow_unsupported_sfp = 1;
1183
1184         /* Initialize the shared code (base driver) */
1185 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1186         diag = ixgbe_bypass_init_shared_code(hw);
1187 #else
1188         diag = ixgbe_init_shared_code(hw);
1189 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1190
1191         if (diag != IXGBE_SUCCESS) {
1192                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1193                 return -EIO;
1194         }
1195
1196         /* pick up the PCI bus settings for reporting later */
1197         ixgbe_get_bus_info(hw);
1198
1199         /* Unlock any pending hardware semaphore */
1200         ixgbe_swfw_lock_reset(hw);
1201
1202         /* Initialize DCB configuration*/
1203         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1204         ixgbe_dcb_init(hw, dcb_config);
1205         /* Get Hardware Flow Control setting */
1206         hw->fc.requested_mode = ixgbe_fc_full;
1207         hw->fc.current_mode = ixgbe_fc_full;
1208         hw->fc.pause_time = IXGBE_FC_PAUSE;
1209         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1210                 hw->fc.low_water[i] = IXGBE_FC_LO;
1211                 hw->fc.high_water[i] = IXGBE_FC_HI;
1212         }
1213         hw->fc.send_xon = 1;
1214
1215         /* Make sure we have a good EEPROM before we read from it */
1216         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1217         if (diag != IXGBE_SUCCESS) {
1218                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1219                 return -EIO;
1220         }
1221
1222 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1223         diag = ixgbe_bypass_init_hw(hw);
1224 #else
1225         diag = ixgbe_init_hw(hw);
1226 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1227
1228         /*
1229          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1230          * is called too soon after the kernel driver unbinding/binding occurs.
1231          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1232          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1233          * also called. See ixgbe_identify_phy_82599(). The reason for the
1234          * failure is not known, and only occuts when virtualisation features
1235          * are disabled in the bios. A delay of 100ms  was found to be enough by
1236          * trial-and-error, and is doubled to be safe.
1237          */
1238         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1239                 rte_delay_ms(200);
1240                 diag = ixgbe_init_hw(hw);
1241         }
1242
1243         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1244                 diag = IXGBE_SUCCESS;
1245
1246         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1247                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1248                              "LOM.  Please be aware there may be issues associated "
1249                              "with your hardware.");
1250                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1251                              "please contact your Intel or hardware representative "
1252                              "who provided you with this hardware.");
1253         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1254                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1255         if (diag) {
1256                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1257                 return -EIO;
1258         }
1259
1260         /* Reset the hw statistics */
1261         ixgbe_dev_stats_reset(eth_dev);
1262
1263         /* disable interrupt */
1264         ixgbe_disable_intr(hw);
1265
1266         /* reset mappings for queue statistics hw counters*/
1267         ixgbe_reset_qstat_mappings(hw);
1268
1269         /* Allocate memory for storing MAC addresses */
1270         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1271                                                hw->mac.num_rar_entries, 0);
1272         if (eth_dev->data->mac_addrs == NULL) {
1273                 PMD_INIT_LOG(ERR,
1274                              "Failed to allocate %u bytes needed to store "
1275                              "MAC addresses",
1276                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1277                 return -ENOMEM;
1278         }
1279         /* Copy the permanent MAC address */
1280         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1281                         &eth_dev->data->mac_addrs[0]);
1282
1283         /* Allocate memory for storing hash filter MAC addresses */
1284         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1285                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1286         if (eth_dev->data->hash_mac_addrs == NULL) {
1287                 PMD_INIT_LOG(ERR,
1288                              "Failed to allocate %d bytes needed to store MAC addresses",
1289                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1290                 return -ENOMEM;
1291         }
1292
1293         /* initialize the vfta */
1294         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1295
1296         /* initialize the hw strip bitmap*/
1297         memset(hwstrip, 0, sizeof(*hwstrip));
1298
1299         /* initialize PF if max_vfs not zero */
1300         ixgbe_pf_host_init(eth_dev);
1301
1302         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1303         /* let hardware know driver is loaded */
1304         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1305         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1306         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1307         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1308         IXGBE_WRITE_FLUSH(hw);
1309
1310         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1311                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1312                              (int) hw->mac.type, (int) hw->phy.type,
1313                              (int) hw->phy.sfp_type);
1314         else
1315                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1316                              (int) hw->mac.type, (int) hw->phy.type);
1317
1318         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1319                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1320                      pci_dev->id.device_id);
1321
1322         rte_intr_callback_register(intr_handle,
1323                                    ixgbe_dev_interrupt_handler, eth_dev);
1324
1325         /* enable uio/vfio intr/eventfd mapping */
1326         rte_intr_enable(intr_handle);
1327
1328         /* enable support intr */
1329         ixgbe_enable_intr(eth_dev);
1330
1331         /* initialize filter info */
1332         memset(filter_info, 0,
1333                sizeof(struct ixgbe_filter_info));
1334
1335         /* initialize 5tuple filter list */
1336         TAILQ_INIT(&filter_info->fivetuple_list);
1337
1338         /* initialize flow director filter list & hash */
1339         ixgbe_fdir_filter_init(eth_dev);
1340
1341         /* initialize l2 tunnel filter list & hash */
1342         ixgbe_l2_tn_filter_init(eth_dev);
1343
1344         TAILQ_INIT(&filter_ntuple_list);
1345         TAILQ_INIT(&filter_ethertype_list);
1346         TAILQ_INIT(&filter_syn_list);
1347         TAILQ_INIT(&filter_fdir_list);
1348         TAILQ_INIT(&filter_l2_tunnel_list);
1349         TAILQ_INIT(&ixgbe_flow_list);
1350
1351         /* initialize bandwidth configuration info */
1352         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1353
1354         /* initialize Traffic Manager configuration */
1355         ixgbe_tm_conf_init(eth_dev);
1356
1357         return 0;
1358 }
1359
1360 static int
1361 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1362 {
1363         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1364         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1365         struct ixgbe_hw *hw;
1366
1367         PMD_INIT_FUNC_TRACE();
1368
1369         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1370                 return -EPERM;
1371
1372         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1373
1374         if (hw->adapter_stopped == 0)
1375                 ixgbe_dev_close(eth_dev);
1376
1377         eth_dev->dev_ops = NULL;
1378         eth_dev->rx_pkt_burst = NULL;
1379         eth_dev->tx_pkt_burst = NULL;
1380
1381         /* Unlock any pending hardware semaphore */
1382         ixgbe_swfw_lock_reset(hw);
1383
1384         /* disable uio intr before callback unregister */
1385         rte_intr_disable(intr_handle);
1386         rte_intr_callback_unregister(intr_handle,
1387                                      ixgbe_dev_interrupt_handler, eth_dev);
1388
1389         /* uninitialize PF if max_vfs not zero */
1390         ixgbe_pf_host_uninit(eth_dev);
1391
1392         rte_free(eth_dev->data->mac_addrs);
1393         eth_dev->data->mac_addrs = NULL;
1394
1395         rte_free(eth_dev->data->hash_mac_addrs);
1396         eth_dev->data->hash_mac_addrs = NULL;
1397
1398         /* remove all the fdir filters & hash */
1399         ixgbe_fdir_filter_uninit(eth_dev);
1400
1401         /* remove all the L2 tunnel filters & hash */
1402         ixgbe_l2_tn_filter_uninit(eth_dev);
1403
1404         /* Remove all ntuple filters of the device */
1405         ixgbe_ntuple_filter_uninit(eth_dev);
1406
1407         /* clear all the filters list */
1408         ixgbe_filterlist_flush();
1409
1410         /* Remove all Traffic Manager configuration */
1411         ixgbe_tm_conf_uninit(eth_dev);
1412
1413         return 0;
1414 }
1415
1416 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1417 {
1418         struct ixgbe_filter_info *filter_info =
1419                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1420         struct ixgbe_5tuple_filter *p_5tuple;
1421
1422         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1423                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1424                              p_5tuple,
1425                              entries);
1426                 rte_free(p_5tuple);
1427         }
1428         memset(filter_info->fivetuple_mask, 0,
1429                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1430
1431         return 0;
1432 }
1433
1434 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1435 {
1436         struct ixgbe_hw_fdir_info *fdir_info =
1437                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1438         struct ixgbe_fdir_filter *fdir_filter;
1439
1440                 if (fdir_info->hash_map)
1441                 rte_free(fdir_info->hash_map);
1442         if (fdir_info->hash_handle)
1443                 rte_hash_free(fdir_info->hash_handle);
1444
1445         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1446                 TAILQ_REMOVE(&fdir_info->fdir_list,
1447                              fdir_filter,
1448                              entries);
1449                 rte_free(fdir_filter);
1450         }
1451
1452         return 0;
1453 }
1454
1455 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1456 {
1457         struct ixgbe_l2_tn_info *l2_tn_info =
1458                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1459         struct ixgbe_l2_tn_filter *l2_tn_filter;
1460
1461         if (l2_tn_info->hash_map)
1462                 rte_free(l2_tn_info->hash_map);
1463         if (l2_tn_info->hash_handle)
1464                 rte_hash_free(l2_tn_info->hash_handle);
1465
1466         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1467                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1468                              l2_tn_filter,
1469                              entries);
1470                 rte_free(l2_tn_filter);
1471         }
1472
1473         return 0;
1474 }
1475
1476 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1477 {
1478         struct ixgbe_hw_fdir_info *fdir_info =
1479                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1480         char fdir_hash_name[RTE_HASH_NAMESIZE];
1481         struct rte_hash_parameters fdir_hash_params = {
1482                 .name = fdir_hash_name,
1483                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1484                 .key_len = sizeof(union ixgbe_atr_input),
1485                 .hash_func = rte_hash_crc,
1486                 .hash_func_init_val = 0,
1487                 .socket_id = rte_socket_id(),
1488         };
1489
1490         TAILQ_INIT(&fdir_info->fdir_list);
1491         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1492                  "fdir_%s", eth_dev->device->name);
1493         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1494         if (!fdir_info->hash_handle) {
1495                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1496                 return -EINVAL;
1497         }
1498         fdir_info->hash_map = rte_zmalloc("ixgbe",
1499                                           sizeof(struct ixgbe_fdir_filter *) *
1500                                           IXGBE_MAX_FDIR_FILTER_NUM,
1501                                           0);
1502         if (!fdir_info->hash_map) {
1503                 PMD_INIT_LOG(ERR,
1504                              "Failed to allocate memory for fdir hash map!");
1505                 return -ENOMEM;
1506         }
1507         fdir_info->mask_added = FALSE;
1508
1509         return 0;
1510 }
1511
1512 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1513 {
1514         struct ixgbe_l2_tn_info *l2_tn_info =
1515                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1516         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1517         struct rte_hash_parameters l2_tn_hash_params = {
1518                 .name = l2_tn_hash_name,
1519                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1520                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1521                 .hash_func = rte_hash_crc,
1522                 .hash_func_init_val = 0,
1523                 .socket_id = rte_socket_id(),
1524         };
1525
1526         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1527         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1528                  "l2_tn_%s", eth_dev->device->name);
1529         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1530         if (!l2_tn_info->hash_handle) {
1531                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1532                 return -EINVAL;
1533         }
1534         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1535                                    sizeof(struct ixgbe_l2_tn_filter *) *
1536                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1537                                    0);
1538         if (!l2_tn_info->hash_map) {
1539                 PMD_INIT_LOG(ERR,
1540                         "Failed to allocate memory for L2 TN hash map!");
1541                 return -ENOMEM;
1542         }
1543         l2_tn_info->e_tag_en = FALSE;
1544         l2_tn_info->e_tag_fwd_en = FALSE;
1545         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1546
1547         return 0;
1548 }
1549 /*
1550  * Negotiate mailbox API version with the PF.
1551  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1552  * Then we try to negotiate starting with the most recent one.
1553  * If all negotiation attempts fail, then we will proceed with
1554  * the default one (ixgbe_mbox_api_10).
1555  */
1556 static void
1557 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1558 {
1559         int32_t i;
1560
1561         /* start with highest supported, proceed down */
1562         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1563                 ixgbe_mbox_api_12,
1564                 ixgbe_mbox_api_11,
1565                 ixgbe_mbox_api_10,
1566         };
1567
1568         for (i = 0;
1569                         i != RTE_DIM(sup_ver) &&
1570                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1571                         i++)
1572                 ;
1573 }
1574
1575 static void
1576 generate_random_mac_addr(struct ether_addr *mac_addr)
1577 {
1578         uint64_t random;
1579
1580         /* Set Organizationally Unique Identifier (OUI) prefix. */
1581         mac_addr->addr_bytes[0] = 0x00;
1582         mac_addr->addr_bytes[1] = 0x09;
1583         mac_addr->addr_bytes[2] = 0xC0;
1584         /* Force indication of locally assigned MAC address. */
1585         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1586         /* Generate the last 3 bytes of the MAC address with a random number. */
1587         random = rte_rand();
1588         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1589 }
1590
1591 /*
1592  * Virtual Function device init
1593  */
1594 static int
1595 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1596 {
1597         int diag;
1598         uint32_t tc, tcs;
1599         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1600         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1601         struct ixgbe_hw *hw =
1602                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1603         struct ixgbe_vfta *shadow_vfta =
1604                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1605         struct ixgbe_hwstrip *hwstrip =
1606                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1607         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1608
1609         PMD_INIT_FUNC_TRACE();
1610
1611         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1612         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1613         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1614
1615         /* for secondary processes, we don't initialise any further as primary
1616          * has already done this work. Only check we don't need a different
1617          * RX function
1618          */
1619         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1620                 struct ixgbe_tx_queue *txq;
1621                 /* TX queue function in primary, set by last queue initialized
1622                  * Tx queue may not initialized by primary process
1623                  */
1624                 if (eth_dev->data->tx_queues) {
1625                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1626                         ixgbe_set_tx_function(eth_dev, txq);
1627                 } else {
1628                         /* Use default TX function if we get here */
1629                         PMD_INIT_LOG(NOTICE,
1630                                      "No TX queues configured yet. Using default TX function.");
1631                 }
1632
1633                 ixgbe_set_rx_function(eth_dev);
1634
1635                 return 0;
1636         }
1637
1638         rte_eth_copy_pci_info(eth_dev, pci_dev);
1639         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1640
1641         hw->device_id = pci_dev->id.device_id;
1642         hw->vendor_id = pci_dev->id.vendor_id;
1643         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1644
1645         /* initialize the vfta */
1646         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1647
1648         /* initialize the hw strip bitmap*/
1649         memset(hwstrip, 0, sizeof(*hwstrip));
1650
1651         /* Initialize the shared code (base driver) */
1652         diag = ixgbe_init_shared_code(hw);
1653         if (diag != IXGBE_SUCCESS) {
1654                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1655                 return -EIO;
1656         }
1657
1658         /* init_mailbox_params */
1659         hw->mbx.ops.init_params(hw);
1660
1661         /* Reset the hw statistics */
1662         ixgbevf_dev_stats_reset(eth_dev);
1663
1664         /* Disable the interrupts for VF */
1665         ixgbevf_intr_disable(hw);
1666
1667         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1668         diag = hw->mac.ops.reset_hw(hw);
1669
1670         /*
1671          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1672          * the underlying PF driver has not assigned a MAC address to the VF.
1673          * In this case, assign a random MAC address.
1674          */
1675         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1676                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1677                 return diag;
1678         }
1679
1680         /* negotiate mailbox API version to use with the PF. */
1681         ixgbevf_negotiate_api(hw);
1682
1683         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1684         ixgbevf_get_queues(hw, &tcs, &tc);
1685
1686         /* Allocate memory for storing MAC addresses */
1687         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1688                                                hw->mac.num_rar_entries, 0);
1689         if (eth_dev->data->mac_addrs == NULL) {
1690                 PMD_INIT_LOG(ERR,
1691                              "Failed to allocate %u bytes needed to store "
1692                              "MAC addresses",
1693                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1694                 return -ENOMEM;
1695         }
1696
1697         /* Generate a random MAC address, if none was assigned by PF. */
1698         if (is_zero_ether_addr(perm_addr)) {
1699                 generate_random_mac_addr(perm_addr);
1700                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1701                 if (diag) {
1702                         rte_free(eth_dev->data->mac_addrs);
1703                         eth_dev->data->mac_addrs = NULL;
1704                         return diag;
1705                 }
1706                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1707                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1708                              "%02x:%02x:%02x:%02x:%02x:%02x",
1709                              perm_addr->addr_bytes[0],
1710                              perm_addr->addr_bytes[1],
1711                              perm_addr->addr_bytes[2],
1712                              perm_addr->addr_bytes[3],
1713                              perm_addr->addr_bytes[4],
1714                              perm_addr->addr_bytes[5]);
1715         }
1716
1717         /* Copy the permanent MAC address */
1718         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1719
1720         /* reset the hardware with the new settings */
1721         diag = hw->mac.ops.start_hw(hw);
1722         switch (diag) {
1723         case  0:
1724                 break;
1725
1726         default:
1727                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1728                 return -EIO;
1729         }
1730
1731         rte_intr_callback_register(intr_handle,
1732                                    ixgbevf_dev_interrupt_handler, eth_dev);
1733         rte_intr_enable(intr_handle);
1734         ixgbevf_intr_enable(hw);
1735
1736         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1737                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1738                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1739
1740         return 0;
1741 }
1742
1743 /* Virtual Function device uninit */
1744
1745 static int
1746 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1747 {
1748         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1749         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1750         struct ixgbe_hw *hw;
1751
1752         PMD_INIT_FUNC_TRACE();
1753
1754         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1755                 return -EPERM;
1756
1757         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1758
1759         if (hw->adapter_stopped == 0)
1760                 ixgbevf_dev_close(eth_dev);
1761
1762         eth_dev->dev_ops = NULL;
1763         eth_dev->rx_pkt_burst = NULL;
1764         eth_dev->tx_pkt_burst = NULL;
1765
1766         /* Disable the interrupts for VF */
1767         ixgbevf_intr_disable(hw);
1768
1769         rte_free(eth_dev->data->mac_addrs);
1770         eth_dev->data->mac_addrs = NULL;
1771
1772         rte_intr_disable(intr_handle);
1773         rte_intr_callback_unregister(intr_handle,
1774                                      ixgbevf_dev_interrupt_handler, eth_dev);
1775
1776         return 0;
1777 }
1778
1779 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1780         struct rte_pci_device *pci_dev)
1781 {
1782         return rte_eth_dev_pci_generic_probe(pci_dev,
1783                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1784 }
1785
1786 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1787 {
1788         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1789 }
1790
1791 static struct rte_pci_driver rte_ixgbe_pmd = {
1792         .id_table = pci_id_ixgbe_map,
1793         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1794         .probe = eth_ixgbe_pci_probe,
1795         .remove = eth_ixgbe_pci_remove,
1796 };
1797
1798 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1799         struct rte_pci_device *pci_dev)
1800 {
1801         return rte_eth_dev_pci_generic_probe(pci_dev,
1802                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1803 }
1804
1805 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1806 {
1807         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1808 }
1809
1810 /*
1811  * virtual function driver struct
1812  */
1813 static struct rte_pci_driver rte_ixgbevf_pmd = {
1814         .id_table = pci_id_ixgbevf_map,
1815         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1816         .probe = eth_ixgbevf_pci_probe,
1817         .remove = eth_ixgbevf_pci_remove,
1818 };
1819
1820 static int
1821 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1822 {
1823         struct ixgbe_hw *hw =
1824                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825         struct ixgbe_vfta *shadow_vfta =
1826                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1827         uint32_t vfta;
1828         uint32_t vid_idx;
1829         uint32_t vid_bit;
1830
1831         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1832         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1833         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1834         if (on)
1835                 vfta |= vid_bit;
1836         else
1837                 vfta &= ~vid_bit;
1838         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1839
1840         /* update local VFTA copy */
1841         shadow_vfta->vfta[vid_idx] = vfta;
1842
1843         return 0;
1844 }
1845
1846 static void
1847 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1848 {
1849         if (on)
1850                 ixgbe_vlan_hw_strip_enable(dev, queue);
1851         else
1852                 ixgbe_vlan_hw_strip_disable(dev, queue);
1853 }
1854
1855 static int
1856 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1857                     enum rte_vlan_type vlan_type,
1858                     uint16_t tpid)
1859 {
1860         struct ixgbe_hw *hw =
1861                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862         int ret = 0;
1863         uint32_t reg;
1864         uint32_t qinq;
1865
1866         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867         qinq &= IXGBE_DMATXCTL_GDV;
1868
1869         switch (vlan_type) {
1870         case ETH_VLAN_TYPE_INNER:
1871                 if (qinq) {
1872                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1873                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1874                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1875                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1876                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1877                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1878                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1879                 } else {
1880                         ret = -ENOTSUP;
1881                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1882                                     " by single VLAN");
1883                 }
1884                 break;
1885         case ETH_VLAN_TYPE_OUTER:
1886                 if (qinq) {
1887                         /* Only the high 16-bits is valid */
1888                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1889                                         IXGBE_EXVET_VET_EXT_SHIFT);
1890                 } else {
1891                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1892                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1893                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1894                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1895                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1896                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1897                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1898                 }
1899
1900                 break;
1901         default:
1902                 ret = -EINVAL;
1903                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1904                 break;
1905         }
1906
1907         return ret;
1908 }
1909
1910 void
1911 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1912 {
1913         struct ixgbe_hw *hw =
1914                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1915         uint32_t vlnctrl;
1916
1917         PMD_INIT_FUNC_TRACE();
1918
1919         /* Filter Table Disable */
1920         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1921         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1922
1923         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1924 }
1925
1926 void
1927 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1928 {
1929         struct ixgbe_hw *hw =
1930                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1931         struct ixgbe_vfta *shadow_vfta =
1932                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1933         uint32_t vlnctrl;
1934         uint16_t i;
1935
1936         PMD_INIT_FUNC_TRACE();
1937
1938         /* Filter Table Enable */
1939         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1940         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1941         vlnctrl |= IXGBE_VLNCTRL_VFE;
1942
1943         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1944
1945         /* write whatever is in local vfta copy */
1946         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1947                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1948 }
1949
1950 static void
1951 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1952 {
1953         struct ixgbe_hwstrip *hwstrip =
1954                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1955         struct ixgbe_rx_queue *rxq;
1956
1957         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1958                 return;
1959
1960         if (on)
1961                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1962         else
1963                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1964
1965         if (queue >= dev->data->nb_rx_queues)
1966                 return;
1967
1968         rxq = dev->data->rx_queues[queue];
1969
1970         if (on)
1971                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1972         else
1973                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1974 }
1975
1976 static void
1977 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1978 {
1979         struct ixgbe_hw *hw =
1980                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1981         uint32_t ctrl;
1982
1983         PMD_INIT_FUNC_TRACE();
1984
1985         if (hw->mac.type == ixgbe_mac_82598EB) {
1986                 /* No queue level support */
1987                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1988                 return;
1989         }
1990
1991         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1992         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1993         ctrl &= ~IXGBE_RXDCTL_VME;
1994         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1995
1996         /* record those setting for HW strip per queue */
1997         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1998 }
1999
2000 static void
2001 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2002 {
2003         struct ixgbe_hw *hw =
2004                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005         uint32_t ctrl;
2006
2007         PMD_INIT_FUNC_TRACE();
2008
2009         if (hw->mac.type == ixgbe_mac_82598EB) {
2010                 /* No queue level supported */
2011                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2012                 return;
2013         }
2014
2015         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2016         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2017         ctrl |= IXGBE_RXDCTL_VME;
2018         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2019
2020         /* record those setting for HW strip per queue */
2021         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2022 }
2023
2024 void
2025 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2026 {
2027         struct ixgbe_hw *hw =
2028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         uint32_t ctrl;
2030         uint16_t i;
2031         struct ixgbe_rx_queue *rxq;
2032
2033         PMD_INIT_FUNC_TRACE();
2034
2035         if (hw->mac.type == ixgbe_mac_82598EB) {
2036                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2037                 ctrl &= ~IXGBE_VLNCTRL_VME;
2038                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2039         } else {
2040                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2041                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2042                         rxq = dev->data->rx_queues[i];
2043                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2044                         ctrl &= ~IXGBE_RXDCTL_VME;
2045                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2046
2047                         /* record those setting for HW strip per queue */
2048                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2049                 }
2050         }
2051 }
2052
2053 void
2054 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2055 {
2056         struct ixgbe_hw *hw =
2057                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058         uint32_t ctrl;
2059         uint16_t i;
2060         struct ixgbe_rx_queue *rxq;
2061
2062         PMD_INIT_FUNC_TRACE();
2063
2064         if (hw->mac.type == ixgbe_mac_82598EB) {
2065                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2066                 ctrl |= IXGBE_VLNCTRL_VME;
2067                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2068         } else {
2069                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2070                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2071                         rxq = dev->data->rx_queues[i];
2072                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2073                         ctrl |= IXGBE_RXDCTL_VME;
2074                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2075
2076                         /* record those setting for HW strip per queue */
2077                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2078                 }
2079         }
2080 }
2081
2082 static void
2083 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2084 {
2085         struct ixgbe_hw *hw =
2086                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087         uint32_t ctrl;
2088
2089         PMD_INIT_FUNC_TRACE();
2090
2091         /* DMATXCTRL: Geric Double VLAN Disable */
2092         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2093         ctrl &= ~IXGBE_DMATXCTL_GDV;
2094         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2095
2096         /* CTRL_EXT: Global Double VLAN Disable */
2097         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2098         ctrl &= ~IXGBE_EXTENDED_VLAN;
2099         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2100
2101 }
2102
2103 static void
2104 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2105 {
2106         struct ixgbe_hw *hw =
2107                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2108         uint32_t ctrl;
2109
2110         PMD_INIT_FUNC_TRACE();
2111
2112         /* DMATXCTRL: Geric Double VLAN Enable */
2113         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2114         ctrl |= IXGBE_DMATXCTL_GDV;
2115         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2116
2117         /* CTRL_EXT: Global Double VLAN Enable */
2118         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2119         ctrl |= IXGBE_EXTENDED_VLAN;
2120         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2121
2122         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2123         if (hw->mac.type == ixgbe_mac_X550 ||
2124             hw->mac.type == ixgbe_mac_X550EM_x ||
2125             hw->mac.type == ixgbe_mac_X550EM_a) {
2126                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2127                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2128                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2129         }
2130
2131         /*
2132          * VET EXT field in the EXVET register = 0x8100 by default
2133          * So no need to change. Same to VT field of DMATXCTL register
2134          */
2135 }
2136
2137 static void
2138 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2139 {
2140         if (mask & ETH_VLAN_STRIP_MASK) {
2141                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2142                         ixgbe_vlan_hw_strip_enable_all(dev);
2143                 else
2144                         ixgbe_vlan_hw_strip_disable_all(dev);
2145         }
2146
2147         if (mask & ETH_VLAN_FILTER_MASK) {
2148                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2149                         ixgbe_vlan_hw_filter_enable(dev);
2150                 else
2151                         ixgbe_vlan_hw_filter_disable(dev);
2152         }
2153
2154         if (mask & ETH_VLAN_EXTEND_MASK) {
2155                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2156                         ixgbe_vlan_hw_extend_enable(dev);
2157                 else
2158                         ixgbe_vlan_hw_extend_disable(dev);
2159         }
2160 }
2161
2162 static void
2163 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2164 {
2165         struct ixgbe_hw *hw =
2166                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2168         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2169
2170         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2171         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2172 }
2173
2174 static int
2175 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2176 {
2177         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2178
2179         switch (nb_rx_q) {
2180         case 1:
2181         case 2:
2182                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2183                 break;
2184         case 4:
2185                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2186                 break;
2187         default:
2188                 return -EINVAL;
2189         }
2190
2191         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2192         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2193
2194         return 0;
2195 }
2196
2197 static int
2198 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2199 {
2200         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2203         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2204
2205         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2206                 /* check multi-queue mode */
2207                 switch (dev_conf->rxmode.mq_mode) {
2208                 case ETH_MQ_RX_VMDQ_DCB:
2209                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2210                         break;
2211                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2212                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2213                         PMD_INIT_LOG(ERR, "SRIOV active,"
2214                                         " unsupported mq_mode rx %d.",
2215                                         dev_conf->rxmode.mq_mode);
2216                         return -EINVAL;
2217                 case ETH_MQ_RX_RSS:
2218                 case ETH_MQ_RX_VMDQ_RSS:
2219                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2220                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2221                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2222                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2223                                                 " invalid queue number"
2224                                                 " for VMDQ RSS, allowed"
2225                                                 " value are 1, 2 or 4.");
2226                                         return -EINVAL;
2227                                 }
2228                         break;
2229                 case ETH_MQ_RX_VMDQ_ONLY:
2230                 case ETH_MQ_RX_NONE:
2231                         /* if nothing mq mode configure, use default scheme */
2232                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2233                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2234                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2235                         break;
2236                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2237                         /* SRIOV only works in VMDq enable mode */
2238                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2239                                         " wrong mq_mode rx %d.",
2240                                         dev_conf->rxmode.mq_mode);
2241                         return -EINVAL;
2242                 }
2243
2244                 switch (dev_conf->txmode.mq_mode) {
2245                 case ETH_MQ_TX_VMDQ_DCB:
2246                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2247                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2248                         break;
2249                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2250                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2251                         break;
2252                 }
2253
2254                 /* check valid queue number */
2255                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2256                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2257                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2258                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2259                                         " must be less than or equal to %d.",
2260                                         nb_rx_q, nb_tx_q,
2261                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2262                         return -EINVAL;
2263                 }
2264         } else {
2265                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2266                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2267                                           " not supported.");
2268                         return -EINVAL;
2269                 }
2270                 /* check configuration for vmdb+dcb mode */
2271                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2272                         const struct rte_eth_vmdq_dcb_conf *conf;
2273
2274                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2275                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2276                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2277                                 return -EINVAL;
2278                         }
2279                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2280                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2281                                conf->nb_queue_pools == ETH_32_POOLS)) {
2282                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2283                                                 " nb_queue_pools must be %d or %d.",
2284                                                 ETH_16_POOLS, ETH_32_POOLS);
2285                                 return -EINVAL;
2286                         }
2287                 }
2288                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2289                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2290
2291                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2292                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2293                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2294                                 return -EINVAL;
2295                         }
2296                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2297                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2298                                conf->nb_queue_pools == ETH_32_POOLS)) {
2299                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2300                                                 " nb_queue_pools != %d and"
2301                                                 " nb_queue_pools != %d.",
2302                                                 ETH_16_POOLS, ETH_32_POOLS);
2303                                 return -EINVAL;
2304                         }
2305                 }
2306
2307                 /* For DCB mode check our configuration before we go further */
2308                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2309                         const struct rte_eth_dcb_rx_conf *conf;
2310
2311                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2312                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2313                                                  IXGBE_DCB_NB_QUEUES);
2314                                 return -EINVAL;
2315                         }
2316                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2317                         if (!(conf->nb_tcs == ETH_4_TCS ||
2318                                conf->nb_tcs == ETH_8_TCS)) {
2319                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2320                                                 " and nb_tcs != %d.",
2321                                                 ETH_4_TCS, ETH_8_TCS);
2322                                 return -EINVAL;
2323                         }
2324                 }
2325
2326                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2327                         const struct rte_eth_dcb_tx_conf *conf;
2328
2329                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2330                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2331                                                  IXGBE_DCB_NB_QUEUES);
2332                                 return -EINVAL;
2333                         }
2334                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2335                         if (!(conf->nb_tcs == ETH_4_TCS ||
2336                                conf->nb_tcs == ETH_8_TCS)) {
2337                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2338                                                 " and nb_tcs != %d.",
2339                                                 ETH_4_TCS, ETH_8_TCS);
2340                                 return -EINVAL;
2341                         }
2342                 }
2343
2344                 /*
2345                  * When DCB/VT is off, maximum number of queues changes,
2346                  * except for 82598EB, which remains constant.
2347                  */
2348                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2349                                 hw->mac.type != ixgbe_mac_82598EB) {
2350                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2351                                 PMD_INIT_LOG(ERR,
2352                                              "Neither VT nor DCB are enabled, "
2353                                              "nb_tx_q > %d.",
2354                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2355                                 return -EINVAL;
2356                         }
2357                 }
2358         }
2359         return 0;
2360 }
2361
2362 static int
2363 ixgbe_dev_configure(struct rte_eth_dev *dev)
2364 {
2365         struct ixgbe_interrupt *intr =
2366                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2367         struct ixgbe_adapter *adapter =
2368                 (struct ixgbe_adapter *)dev->data->dev_private;
2369         int ret;
2370
2371         PMD_INIT_FUNC_TRACE();
2372         /* multipe queue mode checking */
2373         ret  = ixgbe_check_mq_mode(dev);
2374         if (ret != 0) {
2375                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2376                             ret);
2377                 return ret;
2378         }
2379
2380         /* set flag to update link status after init */
2381         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2382
2383         /*
2384          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2385          * allocation or vector Rx preconditions we will reset it.
2386          */
2387         adapter->rx_bulk_alloc_allowed = true;
2388         adapter->rx_vec_allowed = true;
2389
2390         return 0;
2391 }
2392
2393 static void
2394 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2395 {
2396         struct ixgbe_hw *hw =
2397                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398         struct ixgbe_interrupt *intr =
2399                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2400         uint32_t gpie;
2401
2402         /* only set up it on X550EM_X */
2403         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2404                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2405                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2406                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2407                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2408                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2409         }
2410 }
2411
2412 int
2413 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2414                         uint16_t tx_rate, uint64_t q_msk)
2415 {
2416         struct ixgbe_hw *hw;
2417         struct ixgbe_vf_info *vfinfo;
2418         struct rte_eth_link link;
2419         uint8_t  nb_q_per_pool;
2420         uint32_t queue_stride;
2421         uint32_t queue_idx, idx = 0, vf_idx;
2422         uint32_t queue_end;
2423         uint16_t total_rate = 0;
2424         struct rte_pci_device *pci_dev;
2425
2426         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2427         rte_eth_link_get_nowait(dev->data->port_id, &link);
2428
2429         if (vf >= pci_dev->max_vfs)
2430                 return -EINVAL;
2431
2432         if (tx_rate > link.link_speed)
2433                 return -EINVAL;
2434
2435         if (q_msk == 0)
2436                 return 0;
2437
2438         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2440         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2441         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2442         queue_idx = vf * queue_stride;
2443         queue_end = queue_idx + nb_q_per_pool - 1;
2444         if (queue_end >= hw->mac.max_tx_queues)
2445                 return -EINVAL;
2446
2447         if (vfinfo) {
2448                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2449                         if (vf_idx == vf)
2450                                 continue;
2451                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2452                                 idx++)
2453                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2454                 }
2455         } else {
2456                 return -EINVAL;
2457         }
2458
2459         /* Store tx_rate for this vf. */
2460         for (idx = 0; idx < nb_q_per_pool; idx++) {
2461                 if (((uint64_t)0x1 << idx) & q_msk) {
2462                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2463                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2464                         total_rate += tx_rate;
2465                 }
2466         }
2467
2468         if (total_rate > dev->data->dev_link.link_speed) {
2469                 /* Reset stored TX rate of the VF if it causes exceed
2470                  * link speed.
2471                  */
2472                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2473                 return -EINVAL;
2474         }
2475
2476         /* Set RTTBCNRC of each queue/pool for vf X  */
2477         for (; queue_idx <= queue_end; queue_idx++) {
2478                 if (0x1 & q_msk)
2479                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2480                 q_msk = q_msk >> 1;
2481         }
2482
2483         return 0;
2484 }
2485
2486 /*
2487  * Configure device link speed and setup link.
2488  * It returns 0 on success.
2489  */
2490 static int
2491 ixgbe_dev_start(struct rte_eth_dev *dev)
2492 {
2493         struct ixgbe_hw *hw =
2494                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2495         struct ixgbe_vf_info *vfinfo =
2496                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2497         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2498         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2499         uint32_t intr_vector = 0;
2500         int err, link_up = 0, negotiate = 0;
2501         uint32_t speed = 0;
2502         int mask = 0;
2503         int status;
2504         uint16_t vf, idx;
2505         uint32_t *link_speeds;
2506
2507         PMD_INIT_FUNC_TRACE();
2508
2509         /* IXGBE devices don't support:
2510         *    - half duplex (checked afterwards for valid speeds)
2511         *    - fixed speed: TODO implement
2512         */
2513         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2514                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2515                              dev->data->port_id);
2516                 return -EINVAL;
2517         }
2518
2519         /* disable uio/vfio intr/eventfd mapping */
2520         rte_intr_disable(intr_handle);
2521
2522         /* stop adapter */
2523         hw->adapter_stopped = 0;
2524         ixgbe_stop_adapter(hw);
2525
2526         /* reinitialize adapter
2527          * this calls reset and start
2528          */
2529         status = ixgbe_pf_reset_hw(hw);
2530         if (status != 0)
2531                 return -1;
2532         hw->mac.ops.start_hw(hw);
2533         hw->mac.get_link_status = true;
2534
2535         /* configure PF module if SRIOV enabled */
2536         ixgbe_pf_host_configure(dev);
2537
2538         ixgbe_dev_phy_intr_setup(dev);
2539
2540         /* check and configure queue intr-vector mapping */
2541         if ((rte_intr_cap_multiple(intr_handle) ||
2542              !RTE_ETH_DEV_SRIOV(dev).active) &&
2543             dev->data->dev_conf.intr_conf.rxq != 0) {
2544                 intr_vector = dev->data->nb_rx_queues;
2545                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2546                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2547                                         IXGBE_MAX_INTR_QUEUE_NUM);
2548                         return -ENOTSUP;
2549                 }
2550                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2551                         return -1;
2552         }
2553
2554         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2555                 intr_handle->intr_vec =
2556                         rte_zmalloc("intr_vec",
2557                                     dev->data->nb_rx_queues * sizeof(int), 0);
2558                 if (intr_handle->intr_vec == NULL) {
2559                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2560                                      " intr_vec", dev->data->nb_rx_queues);
2561                         return -ENOMEM;
2562                 }
2563         }
2564
2565         /* confiugre msix for sleep until rx interrupt */
2566         ixgbe_configure_msix(dev);
2567
2568         /* initialize transmission unit */
2569         ixgbe_dev_tx_init(dev);
2570
2571         /* This can fail when allocating mbufs for descriptor rings */
2572         err = ixgbe_dev_rx_init(dev);
2573         if (err) {
2574                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2575                 goto error;
2576         }
2577
2578     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2579                 ETH_VLAN_EXTEND_MASK;
2580         ixgbe_vlan_offload_set(dev, mask);
2581
2582         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2583                 /* Enable vlan filtering for VMDq */
2584                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2585         }
2586
2587         /* Configure DCB hw */
2588         ixgbe_configure_dcb(dev);
2589
2590         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2591                 err = ixgbe_fdir_configure(dev);
2592                 if (err)
2593                         goto error;
2594         }
2595
2596         /* Restore vf rate limit */
2597         if (vfinfo != NULL) {
2598                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2599                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2600                                 if (vfinfo[vf].tx_rate[idx] != 0)
2601                                         ixgbe_set_vf_rate_limit(
2602                                                 dev, vf,
2603                                                 vfinfo[vf].tx_rate[idx],
2604                                                 1 << idx);
2605         }
2606
2607         ixgbe_restore_statistics_mapping(dev);
2608
2609         err = ixgbe_dev_rxtx_start(dev);
2610         if (err < 0) {
2611                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2612                 goto error;
2613         }
2614
2615         /* Skip link setup if loopback mode is enabled for 82599. */
2616         if (hw->mac.type == ixgbe_mac_82599EB &&
2617                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2618                 goto skip_link_setup;
2619
2620         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2621                 err = hw->mac.ops.setup_sfp(hw);
2622                 if (err)
2623                         goto error;
2624         }
2625
2626         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2627                 /* Turn on the copper */
2628                 ixgbe_set_phy_power(hw, true);
2629         } else {
2630                 /* Turn on the laser */
2631                 ixgbe_enable_tx_laser(hw);
2632         }
2633
2634         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2635         if (err)
2636                 goto error;
2637         dev->data->dev_link.link_status = link_up;
2638
2639         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2640         if (err)
2641                 goto error;
2642
2643         link_speeds = &dev->data->dev_conf.link_speeds;
2644         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2645                         ETH_LINK_SPEED_10G)) {
2646                 PMD_INIT_LOG(ERR, "Invalid link setting");
2647                 goto error;
2648         }
2649
2650         speed = 0x0;
2651         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2652                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2653                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2654                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2655         } else {
2656                 if (*link_speeds & ETH_LINK_SPEED_10G)
2657                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2658                 if (*link_speeds & ETH_LINK_SPEED_1G)
2659                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2660                 if (*link_speeds & ETH_LINK_SPEED_100M)
2661                         speed |= IXGBE_LINK_SPEED_100_FULL;
2662         }
2663
2664         err = ixgbe_setup_link(hw, speed, link_up);
2665         if (err)
2666                 goto error;
2667
2668 skip_link_setup:
2669
2670         if (rte_intr_allow_others(intr_handle)) {
2671                 /* check if lsc interrupt is enabled */
2672                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2673                         ixgbe_dev_lsc_interrupt_setup(dev);
2674                 ixgbe_dev_macsec_interrupt_setup(dev);
2675         } else {
2676                 rte_intr_callback_unregister(intr_handle,
2677                                              ixgbe_dev_interrupt_handler, dev);
2678                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2679                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2680                                      " no intr multiplex");
2681         }
2682
2683         /* check if rxq interrupt is enabled */
2684         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2685             rte_intr_dp_is_en(intr_handle))
2686                 ixgbe_dev_rxq_interrupt_setup(dev);
2687
2688         /* enable uio/vfio intr/eventfd mapping */
2689         rte_intr_enable(intr_handle);
2690
2691         /* resume enabled intr since hw reset */
2692         ixgbe_enable_intr(dev);
2693         ixgbe_l2_tunnel_conf(dev);
2694         ixgbe_filter_restore(dev);
2695
2696         return 0;
2697
2698 error:
2699         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2700         ixgbe_dev_clear_queues(dev);
2701         return -EIO;
2702 }
2703
2704 /*
2705  * Stop device: disable rx and tx functions to allow for reconfiguring.
2706  */
2707 static void
2708 ixgbe_dev_stop(struct rte_eth_dev *dev)
2709 {
2710         struct rte_eth_link link;
2711         struct ixgbe_hw *hw =
2712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713         struct ixgbe_vf_info *vfinfo =
2714                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2715         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2716         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2717         int vf;
2718         struct ixgbe_tm_conf *tm_conf =
2719                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2720
2721         PMD_INIT_FUNC_TRACE();
2722
2723         /* disable interrupts */
2724         ixgbe_disable_intr(hw);
2725
2726         /* reset the NIC */
2727         ixgbe_pf_reset_hw(hw);
2728         hw->adapter_stopped = 0;
2729
2730         /* stop adapter */
2731         ixgbe_stop_adapter(hw);
2732
2733         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2734                 vfinfo[vf].clear_to_send = false;
2735
2736         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2737                 /* Turn off the copper */
2738                 ixgbe_set_phy_power(hw, false);
2739         } else {
2740                 /* Turn off the laser */
2741                 ixgbe_disable_tx_laser(hw);
2742         }
2743
2744         ixgbe_dev_clear_queues(dev);
2745
2746         /* Clear stored conf */
2747         dev->data->scattered_rx = 0;
2748         dev->data->lro = 0;
2749
2750         /* Clear recorded link status */
2751         memset(&link, 0, sizeof(link));
2752         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2753
2754         if (!rte_intr_allow_others(intr_handle))
2755                 /* resume to the default handler */
2756                 rte_intr_callback_register(intr_handle,
2757                                            ixgbe_dev_interrupt_handler,
2758                                            (void *)dev);
2759
2760         /* Clean datapath event and queue/vec mapping */
2761         rte_intr_efd_disable(intr_handle);
2762         if (intr_handle->intr_vec != NULL) {
2763                 rte_free(intr_handle->intr_vec);
2764                 intr_handle->intr_vec = NULL;
2765         }
2766
2767         /* reset hierarchy commit */
2768         tm_conf->committed = false;
2769 }
2770
2771 /*
2772  * Set device link up: enable tx.
2773  */
2774 static int
2775 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2776 {
2777         struct ixgbe_hw *hw =
2778                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2779         if (hw->mac.type == ixgbe_mac_82599EB) {
2780 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2781                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2782                         /* Not suported in bypass mode */
2783                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2784                                      "by device id 0x%x", hw->device_id);
2785                         return -ENOTSUP;
2786                 }
2787 #endif
2788         }
2789
2790         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2791                 /* Turn on the copper */
2792                 ixgbe_set_phy_power(hw, true);
2793         } else {
2794                 /* Turn on the laser */
2795                 ixgbe_enable_tx_laser(hw);
2796         }
2797
2798         return 0;
2799 }
2800
2801 /*
2802  * Set device link down: disable tx.
2803  */
2804 static int
2805 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2806 {
2807         struct ixgbe_hw *hw =
2808                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2809         if (hw->mac.type == ixgbe_mac_82599EB) {
2810 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2811                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2812                         /* Not suported in bypass mode */
2813                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2814                                      "by device id 0x%x", hw->device_id);
2815                         return -ENOTSUP;
2816                 }
2817 #endif
2818         }
2819
2820         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2821                 /* Turn off the copper */
2822                 ixgbe_set_phy_power(hw, false);
2823         } else {
2824                 /* Turn off the laser */
2825                 ixgbe_disable_tx_laser(hw);
2826         }
2827
2828         return 0;
2829 }
2830
2831 /*
2832  * Reest and stop device.
2833  */
2834 static void
2835 ixgbe_dev_close(struct rte_eth_dev *dev)
2836 {
2837         struct ixgbe_hw *hw =
2838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839
2840         PMD_INIT_FUNC_TRACE();
2841
2842         ixgbe_pf_reset_hw(hw);
2843
2844         ixgbe_dev_stop(dev);
2845         hw->adapter_stopped = 1;
2846
2847         ixgbe_dev_free_queues(dev);
2848
2849         ixgbe_disable_pcie_master(hw);
2850
2851         /* reprogram the RAR[0] in case user changed it. */
2852         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2853 }
2854
2855 static void
2856 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2857                            struct ixgbe_hw_stats *hw_stats,
2858                            struct ixgbe_macsec_stats *macsec_stats,
2859                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2860                            uint64_t *total_qprc, uint64_t *total_qprdc)
2861 {
2862         uint32_t bprc, lxon, lxoff, total;
2863         uint32_t delta_gprc = 0;
2864         unsigned i;
2865         /* Workaround for RX byte count not including CRC bytes when CRC
2866          * strip is enabled. CRC bytes are removed from counters when crc_strip
2867          * is disabled.
2868          */
2869         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2870                         IXGBE_HLREG0_RXCRCSTRP);
2871
2872         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2873         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2874         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2875         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2876
2877         for (i = 0; i < 8; i++) {
2878                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2879
2880                 /* global total per queue */
2881                 hw_stats->mpc[i] += mp;
2882                 /* Running comprehensive total for stats display */
2883                 *total_missed_rx += hw_stats->mpc[i];
2884                 if (hw->mac.type == ixgbe_mac_82598EB) {
2885                         hw_stats->rnbc[i] +=
2886                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2887                         hw_stats->pxonrxc[i] +=
2888                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2889                         hw_stats->pxoffrxc[i] +=
2890                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2891                 } else {
2892                         hw_stats->pxonrxc[i] +=
2893                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2894                         hw_stats->pxoffrxc[i] +=
2895                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2896                         hw_stats->pxon2offc[i] +=
2897                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2898                 }
2899                 hw_stats->pxontxc[i] +=
2900                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2901                 hw_stats->pxofftxc[i] +=
2902                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2903         }
2904         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2905                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2906                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2907                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2908
2909                 delta_gprc += delta_qprc;
2910
2911                 hw_stats->qprc[i] += delta_qprc;
2912                 hw_stats->qptc[i] += delta_qptc;
2913
2914                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2915                 hw_stats->qbrc[i] +=
2916                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2917                 if (crc_strip == 0)
2918                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2919
2920                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2921                 hw_stats->qbtc[i] +=
2922                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2923
2924                 hw_stats->qprdc[i] += delta_qprdc;
2925                 *total_qprdc += hw_stats->qprdc[i];
2926
2927                 *total_qprc += hw_stats->qprc[i];
2928                 *total_qbrc += hw_stats->qbrc[i];
2929         }
2930         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2931         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2932         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2933
2934         /*
2935          * An errata states that gprc actually counts good + missed packets:
2936          * Workaround to set gprc to summated queue packet receives
2937          */
2938         hw_stats->gprc = *total_qprc;
2939
2940         if (hw->mac.type != ixgbe_mac_82598EB) {
2941                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2942                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2943                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2944                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2945                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2946                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2947                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2948                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2949         } else {
2950                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2951                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2952                 /* 82598 only has a counter in the high register */
2953                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2954                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2955                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2956         }
2957         uint64_t old_tpr = hw_stats->tpr;
2958
2959         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2960         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2961
2962         if (crc_strip == 0)
2963                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2964
2965         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2966         hw_stats->gptc += delta_gptc;
2967         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2968         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2969
2970         /*
2971          * Workaround: mprc hardware is incorrectly counting
2972          * broadcasts, so for now we subtract those.
2973          */
2974         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2975         hw_stats->bprc += bprc;
2976         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2977         if (hw->mac.type == ixgbe_mac_82598EB)
2978                 hw_stats->mprc -= bprc;
2979
2980         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2981         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2982         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2983         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2984         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2985         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2986
2987         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2988         hw_stats->lxontxc += lxon;
2989         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2990         hw_stats->lxofftxc += lxoff;
2991         total = lxon + lxoff;
2992
2993         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2994         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2995         hw_stats->gptc -= total;
2996         hw_stats->mptc -= total;
2997         hw_stats->ptc64 -= total;
2998         hw_stats->gotc -= total * ETHER_MIN_LEN;
2999
3000         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3001         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3002         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3003         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3004         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3005         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3006         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3007         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3008         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3009         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3010         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3011         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3012         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3013         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3014         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3015         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3016         /* Only read FCOE on 82599 */
3017         if (hw->mac.type != ixgbe_mac_82598EB) {
3018                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3019                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3020                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3021                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3022                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3023         }
3024
3025         /* Flow Director Stats registers */
3026         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3027         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3028
3029         /* MACsec Stats registers */
3030         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3031         macsec_stats->out_pkts_encrypted +=
3032                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3033         macsec_stats->out_pkts_protected +=
3034                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3035         macsec_stats->out_octets_encrypted +=
3036                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3037         macsec_stats->out_octets_protected +=
3038                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3039         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3040         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3041         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3042         macsec_stats->in_pkts_unknownsci +=
3043                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3044         macsec_stats->in_octets_decrypted +=
3045                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3046         macsec_stats->in_octets_validated +=
3047                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3048         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3049         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3050         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3051         for (i = 0; i < 2; i++) {
3052                 macsec_stats->in_pkts_ok +=
3053                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3054                 macsec_stats->in_pkts_invalid +=
3055                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3056                 macsec_stats->in_pkts_notvalid +=
3057                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3058         }
3059         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3060         macsec_stats->in_pkts_notusingsa +=
3061                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3062 }
3063
3064 /*
3065  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3066  */
3067 static void
3068 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3069 {
3070         struct ixgbe_hw *hw =
3071                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3072         struct ixgbe_hw_stats *hw_stats =
3073                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3074         struct ixgbe_macsec_stats *macsec_stats =
3075                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3076                                 dev->data->dev_private);
3077         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3078         unsigned i;
3079
3080         total_missed_rx = 0;
3081         total_qbrc = 0;
3082         total_qprc = 0;
3083         total_qprdc = 0;
3084
3085         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3086                         &total_qbrc, &total_qprc, &total_qprdc);
3087
3088         if (stats == NULL)
3089                 return;
3090
3091         /* Fill out the rte_eth_stats statistics structure */
3092         stats->ipackets = total_qprc;
3093         stats->ibytes = total_qbrc;
3094         stats->opackets = hw_stats->gptc;
3095         stats->obytes = hw_stats->gotc;
3096
3097         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3098                 stats->q_ipackets[i] = hw_stats->qprc[i];
3099                 stats->q_opackets[i] = hw_stats->qptc[i];
3100                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3101                 stats->q_obytes[i] = hw_stats->qbtc[i];
3102                 stats->q_errors[i] = hw_stats->qprdc[i];
3103         }
3104
3105         /* Rx Errors */
3106         stats->imissed  = total_missed_rx;
3107         stats->ierrors  = hw_stats->crcerrs +
3108                           hw_stats->mspdc +
3109                           hw_stats->rlec +
3110                           hw_stats->ruc +
3111                           hw_stats->roc +
3112                           hw_stats->illerrc +
3113                           hw_stats->errbc +
3114                           hw_stats->rfc +
3115                           hw_stats->fccrc +
3116                           hw_stats->fclast;
3117
3118         /* Tx Errors */
3119         stats->oerrors  = 0;
3120 }
3121
3122 static void
3123 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3124 {
3125         struct ixgbe_hw_stats *stats =
3126                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3127
3128         /* HW registers are cleared on read */
3129         ixgbe_dev_stats_get(dev, NULL);
3130
3131         /* Reset software totals */
3132         memset(stats, 0, sizeof(*stats));
3133 }
3134
3135 /* This function calculates the number of xstats based on the current config */
3136 static unsigned
3137 ixgbe_xstats_calc_num(void) {
3138         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3139                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3140                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3141 }
3142
3143 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3144         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3145 {
3146         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3147         unsigned stat, i, count;
3148
3149         if (xstats_names != NULL) {
3150                 count = 0;
3151
3152                 /* Note: limit >= cnt_stats checked upstream
3153                  * in rte_eth_xstats_names()
3154                  */
3155
3156                 /* Extended stats from ixgbe_hw_stats */
3157                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3158                         snprintf(xstats_names[count].name,
3159                                 sizeof(xstats_names[count].name),
3160                                 "%s",
3161                                 rte_ixgbe_stats_strings[i].name);
3162                         count++;
3163                 }
3164
3165                 /* MACsec Stats */
3166                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3167                         snprintf(xstats_names[count].name,
3168                                 sizeof(xstats_names[count].name),
3169                                 "%s",
3170                                 rte_ixgbe_macsec_strings[i].name);
3171                         count++;
3172                 }
3173
3174                 /* RX Priority Stats */
3175                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3176                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3177                                 snprintf(xstats_names[count].name,
3178                                         sizeof(xstats_names[count].name),
3179                                         "rx_priority%u_%s", i,
3180                                         rte_ixgbe_rxq_strings[stat].name);
3181                                 count++;
3182                         }
3183                 }
3184
3185                 /* TX Priority Stats */
3186                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3187                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3188                                 snprintf(xstats_names[count].name,
3189                                         sizeof(xstats_names[count].name),
3190                                         "tx_priority%u_%s", i,
3191                                         rte_ixgbe_txq_strings[stat].name);
3192                                 count++;
3193                         }
3194                 }
3195         }
3196         return cnt_stats;
3197 }
3198
3199 static int ixgbe_dev_xstats_get_names_by_id(
3200         struct rte_eth_dev *dev,
3201         struct rte_eth_xstat_name *xstats_names,
3202         const uint64_t *ids,
3203         unsigned int limit)
3204 {
3205         if (!ids) {
3206                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3207                 unsigned int stat, i, count;
3208
3209                 if (xstats_names != NULL) {
3210                         count = 0;
3211
3212                         /* Note: limit >= cnt_stats checked upstream
3213                          * in rte_eth_xstats_names()
3214                          */
3215
3216                         /* Extended stats from ixgbe_hw_stats */
3217                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3218                                 snprintf(xstats_names[count].name,
3219                                         sizeof(xstats_names[count].name),
3220                                         "%s",
3221                                         rte_ixgbe_stats_strings[i].name);
3222                                 count++;
3223                         }
3224
3225                         /* MACsec Stats */
3226                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3227                                 snprintf(xstats_names[count].name,
3228                                         sizeof(xstats_names[count].name),
3229                                         "%s",
3230                                         rte_ixgbe_macsec_strings[i].name);
3231                                 count++;
3232                         }
3233
3234                         /* RX Priority Stats */
3235                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3236                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3237                                         snprintf(xstats_names[count].name,
3238                                             sizeof(xstats_names[count].name),
3239                                             "rx_priority%u_%s", i,
3240                                             rte_ixgbe_rxq_strings[stat].name);
3241                                         count++;
3242                                 }
3243                         }
3244
3245                         /* TX Priority Stats */
3246                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3247                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3248                                         snprintf(xstats_names[count].name,
3249                                             sizeof(xstats_names[count].name),
3250                                             "tx_priority%u_%s", i,
3251                                             rte_ixgbe_txq_strings[stat].name);
3252                                         count++;
3253                                 }
3254                         }
3255                 }
3256                 return cnt_stats;
3257         }
3258
3259         uint16_t i;
3260         uint16_t size = ixgbe_xstats_calc_num();
3261         struct rte_eth_xstat_name xstats_names_copy[size];
3262
3263         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3264                         size);
3265
3266         for (i = 0; i < limit; i++) {
3267                 if (ids[i] >= size) {
3268                         PMD_INIT_LOG(ERR, "id value isn't valid");
3269                         return -1;
3270                 }
3271                 strcpy(xstats_names[i].name,
3272                                 xstats_names_copy[ids[i]].name);
3273         }
3274         return limit;
3275 }
3276
3277 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3278         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3279 {
3280         unsigned i;
3281
3282         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3283                 return -ENOMEM;
3284
3285         if (xstats_names != NULL)
3286                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3287                         snprintf(xstats_names[i].name,
3288                                 sizeof(xstats_names[i].name),
3289                                 "%s", rte_ixgbevf_stats_strings[i].name);
3290         return IXGBEVF_NB_XSTATS;
3291 }
3292
3293 static int
3294 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3295                                          unsigned n)
3296 {
3297         struct ixgbe_hw *hw =
3298                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3299         struct ixgbe_hw_stats *hw_stats =
3300                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3301         struct ixgbe_macsec_stats *macsec_stats =
3302                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3303                                 dev->data->dev_private);
3304         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3305         unsigned i, stat, count = 0;
3306
3307         count = ixgbe_xstats_calc_num();
3308
3309         if (n < count)
3310                 return count;
3311
3312         total_missed_rx = 0;
3313         total_qbrc = 0;
3314         total_qprc = 0;
3315         total_qprdc = 0;
3316
3317         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3318                         &total_qbrc, &total_qprc, &total_qprdc);
3319
3320         /* If this is a reset xstats is NULL, and we have cleared the
3321          * registers by reading them.
3322          */
3323         if (!xstats)
3324                 return 0;
3325
3326         /* Extended stats from ixgbe_hw_stats */
3327         count = 0;
3328         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3329                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3330                                 rte_ixgbe_stats_strings[i].offset);
3331                 xstats[count].id = count;
3332                 count++;
3333         }
3334
3335         /* MACsec Stats */
3336         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3337                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3338                                 rte_ixgbe_macsec_strings[i].offset);
3339                 xstats[count].id = count;
3340                 count++;
3341         }
3342
3343         /* RX Priority Stats */
3344         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3345                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3346                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3347                                         rte_ixgbe_rxq_strings[stat].offset +
3348                                         (sizeof(uint64_t) * i));
3349                         xstats[count].id = count;
3350                         count++;
3351                 }
3352         }
3353
3354         /* TX Priority Stats */
3355         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3356                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3357                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3358                                         rte_ixgbe_txq_strings[stat].offset +
3359                                         (sizeof(uint64_t) * i));
3360                         xstats[count].id = count;
3361                         count++;
3362                 }
3363         }
3364         return count;
3365 }
3366
3367 static int
3368 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3369                 uint64_t *values, unsigned int n)
3370 {
3371         if (!ids) {
3372                 struct ixgbe_hw *hw =
3373                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374                 struct ixgbe_hw_stats *hw_stats =
3375                                 IXGBE_DEV_PRIVATE_TO_STATS(
3376                                                 dev->data->dev_private);
3377                 struct ixgbe_macsec_stats *macsec_stats =
3378                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3379                                         dev->data->dev_private);
3380                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3381                 unsigned int i, stat, count = 0;
3382
3383                 count = ixgbe_xstats_calc_num();
3384
3385                 if (!ids && n < count)
3386                         return count;
3387
3388                 total_missed_rx = 0;
3389                 total_qbrc = 0;
3390                 total_qprc = 0;
3391                 total_qprdc = 0;
3392
3393                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3394                                 &total_missed_rx, &total_qbrc, &total_qprc,
3395                                 &total_qprdc);
3396
3397                 /* If this is a reset xstats is NULL, and we have cleared the
3398                  * registers by reading them.
3399                  */
3400                 if (!ids && !values)
3401                         return 0;
3402
3403                 /* Extended stats from ixgbe_hw_stats */
3404                 count = 0;
3405                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3406                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3407                                         rte_ixgbe_stats_strings[i].offset);
3408                         count++;
3409                 }
3410
3411                 /* MACsec Stats */
3412                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3413                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3414                                         rte_ixgbe_macsec_strings[i].offset);
3415                         count++;
3416                 }
3417
3418                 /* RX Priority Stats */
3419                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3420                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3421                                 values[count] =
3422                                         *(uint64_t *)(((char *)hw_stats) +
3423                                         rte_ixgbe_rxq_strings[stat].offset +
3424                                         (sizeof(uint64_t) * i));
3425                                 count++;
3426                         }
3427                 }
3428
3429                 /* TX Priority Stats */
3430                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3431                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3432                                 values[count] =
3433                                         *(uint64_t *)(((char *)hw_stats) +
3434                                         rte_ixgbe_txq_strings[stat].offset +
3435                                         (sizeof(uint64_t) * i));
3436                                 count++;
3437                         }
3438                 }
3439                 return count;
3440         }
3441
3442         uint16_t i;
3443         uint16_t size = ixgbe_xstats_calc_num();
3444         uint64_t values_copy[size];
3445
3446         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3447
3448         for (i = 0; i < n; i++) {
3449                 if (ids[i] >= size) {
3450                         PMD_INIT_LOG(ERR, "id value isn't valid");
3451                         return -1;
3452                 }
3453                 values[i] = values_copy[ids[i]];
3454         }
3455         return n;
3456 }
3457
3458 static void
3459 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3460 {
3461         struct ixgbe_hw_stats *stats =
3462                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3463         struct ixgbe_macsec_stats *macsec_stats =
3464                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3465                                 dev->data->dev_private);
3466
3467         unsigned count = ixgbe_xstats_calc_num();
3468
3469         /* HW registers are cleared on read */
3470         ixgbe_dev_xstats_get(dev, NULL, count);
3471
3472         /* Reset software totals */
3473         memset(stats, 0, sizeof(*stats));
3474         memset(macsec_stats, 0, sizeof(*macsec_stats));
3475 }
3476
3477 static void
3478 ixgbevf_update_stats(struct rte_eth_dev *dev)
3479 {
3480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3481         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3482                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3483
3484         /* Good Rx packet, include VF loopback */
3485         UPDATE_VF_STAT(IXGBE_VFGPRC,
3486             hw_stats->last_vfgprc, hw_stats->vfgprc);
3487
3488         /* Good Rx octets, include VF loopback */
3489         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3490             hw_stats->last_vfgorc, hw_stats->vfgorc);
3491
3492         /* Good Tx packet, include VF loopback */
3493         UPDATE_VF_STAT(IXGBE_VFGPTC,
3494             hw_stats->last_vfgptc, hw_stats->vfgptc);
3495
3496         /* Good Tx octets, include VF loopback */
3497         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3498             hw_stats->last_vfgotc, hw_stats->vfgotc);
3499
3500         /* Rx Multicst Packet */
3501         UPDATE_VF_STAT(IXGBE_VFMPRC,
3502             hw_stats->last_vfmprc, hw_stats->vfmprc);
3503 }
3504
3505 static int
3506 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3507                        unsigned n)
3508 {
3509         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3510                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3511         unsigned i;
3512
3513         if (n < IXGBEVF_NB_XSTATS)
3514                 return IXGBEVF_NB_XSTATS;
3515
3516         ixgbevf_update_stats(dev);
3517
3518         if (!xstats)
3519                 return 0;
3520
3521         /* Extended stats */
3522         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3523                 xstats[i].id = i;
3524                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3525                         rte_ixgbevf_stats_strings[i].offset);
3526         }
3527
3528         return IXGBEVF_NB_XSTATS;
3529 }
3530
3531 static void
3532 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3533 {
3534         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3535                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3536
3537         ixgbevf_update_stats(dev);
3538
3539         if (stats == NULL)
3540                 return;
3541
3542         stats->ipackets = hw_stats->vfgprc;
3543         stats->ibytes = hw_stats->vfgorc;
3544         stats->opackets = hw_stats->vfgptc;
3545         stats->obytes = hw_stats->vfgotc;
3546 }
3547
3548 static void
3549 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3550 {
3551         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3552                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3553
3554         /* Sync HW register to the last stats */
3555         ixgbevf_dev_stats_get(dev, NULL);
3556
3557         /* reset HW current stats*/
3558         hw_stats->vfgprc = 0;
3559         hw_stats->vfgorc = 0;
3560         hw_stats->vfgptc = 0;
3561         hw_stats->vfgotc = 0;
3562 }
3563
3564 static int
3565 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3566 {
3567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3568         u16 eeprom_verh, eeprom_verl;
3569         u32 etrack_id;
3570         int ret;
3571
3572         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3573         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3574
3575         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3576         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3577
3578         ret += 1; /* add the size of '\0' */
3579         if (fw_size < (u32)ret)
3580                 return ret;
3581         else
3582                 return 0;
3583 }
3584
3585 static void
3586 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3587 {
3588         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3590         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3591
3592         dev_info->pci_dev = pci_dev;
3593         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3594         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3595         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3596                 /*
3597                  * When DCB/VT is off, maximum number of queues changes,
3598                  * except for 82598EB, which remains constant.
3599                  */
3600                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3601                                 hw->mac.type != ixgbe_mac_82598EB)
3602                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3603         }
3604         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3605         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3606         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3607         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3608         dev_info->max_vfs = pci_dev->max_vfs;
3609         if (hw->mac.type == ixgbe_mac_82598EB)
3610                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3611         else
3612                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3613         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3614         dev_info->rx_offload_capa =
3615                 DEV_RX_OFFLOAD_VLAN_STRIP |
3616                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3617                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3618                 DEV_RX_OFFLOAD_TCP_CKSUM;
3619
3620         /*
3621          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3622          * mode.
3623          */
3624         if ((hw->mac.type == ixgbe_mac_82599EB ||
3625              hw->mac.type == ixgbe_mac_X540) &&
3626             !RTE_ETH_DEV_SRIOV(dev).active)
3627                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3628
3629         if (hw->mac.type == ixgbe_mac_82599EB ||
3630             hw->mac.type == ixgbe_mac_X540)
3631                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3632
3633         if (hw->mac.type == ixgbe_mac_X550 ||
3634             hw->mac.type == ixgbe_mac_X550EM_x ||
3635             hw->mac.type == ixgbe_mac_X550EM_a)
3636                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3637
3638         dev_info->tx_offload_capa =
3639                 DEV_TX_OFFLOAD_VLAN_INSERT |
3640                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3641                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3642                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3643                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3644                 DEV_TX_OFFLOAD_TCP_TSO;
3645
3646         if (hw->mac.type == ixgbe_mac_82599EB ||
3647             hw->mac.type == ixgbe_mac_X540)
3648                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3649
3650         if (hw->mac.type == ixgbe_mac_X550 ||
3651             hw->mac.type == ixgbe_mac_X550EM_x ||
3652             hw->mac.type == ixgbe_mac_X550EM_a)
3653                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3654
3655         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3656                 .rx_thresh = {
3657                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3658                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3659                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3660                 },
3661                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3662                 .rx_drop_en = 0,
3663         };
3664
3665         dev_info->default_txconf = (struct rte_eth_txconf) {
3666                 .tx_thresh = {
3667                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3668                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3669                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3670                 },
3671                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3672                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3673                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3674                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3675         };
3676
3677         dev_info->rx_desc_lim = rx_desc_lim;
3678         dev_info->tx_desc_lim = tx_desc_lim;
3679
3680         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3681         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3682         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3683
3684         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3685         if (hw->mac.type == ixgbe_mac_X540 ||
3686             hw->mac.type == ixgbe_mac_X540_vf ||
3687             hw->mac.type == ixgbe_mac_X550 ||
3688             hw->mac.type == ixgbe_mac_X550_vf) {
3689                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3690         }
3691 }
3692
3693 static const uint32_t *
3694 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3695 {
3696         static const uint32_t ptypes[] = {
3697                 /* For non-vec functions,
3698                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3699                  * for vec functions,
3700                  * refers to _recv_raw_pkts_vec().
3701                  */
3702                 RTE_PTYPE_L2_ETHER,
3703                 RTE_PTYPE_L3_IPV4,
3704                 RTE_PTYPE_L3_IPV4_EXT,
3705                 RTE_PTYPE_L3_IPV6,
3706                 RTE_PTYPE_L3_IPV6_EXT,
3707                 RTE_PTYPE_L4_SCTP,
3708                 RTE_PTYPE_L4_TCP,
3709                 RTE_PTYPE_L4_UDP,
3710                 RTE_PTYPE_TUNNEL_IP,
3711                 RTE_PTYPE_INNER_L3_IPV6,
3712                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3713                 RTE_PTYPE_INNER_L4_TCP,
3714                 RTE_PTYPE_INNER_L4_UDP,
3715                 RTE_PTYPE_UNKNOWN
3716         };
3717
3718         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3719             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3720             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3721             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3722                 return ptypes;
3723
3724 #if defined(RTE_ARCH_X86)
3725         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3726             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3727                 return ptypes;
3728 #endif
3729         return NULL;
3730 }
3731
3732 static void
3733 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3734                      struct rte_eth_dev_info *dev_info)
3735 {
3736         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3737         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3738
3739         dev_info->pci_dev = pci_dev;
3740         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3741         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3742         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3743         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3744         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3745         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3746         dev_info->max_vfs = pci_dev->max_vfs;
3747         if (hw->mac.type == ixgbe_mac_82598EB)
3748                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3749         else
3750                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3751         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3752                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3753                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3754                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3755         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3756                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3757                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3758                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3759                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3760                                 DEV_TX_OFFLOAD_TCP_TSO;
3761
3762         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3763                 .rx_thresh = {
3764                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3765                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3766                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3767                 },
3768                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3769                 .rx_drop_en = 0,
3770         };
3771
3772         dev_info->default_txconf = (struct rte_eth_txconf) {
3773                 .tx_thresh = {
3774                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3775                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3776                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3777                 },
3778                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3779                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3780                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3781                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3782         };
3783
3784         dev_info->rx_desc_lim = rx_desc_lim;
3785         dev_info->tx_desc_lim = tx_desc_lim;
3786 }
3787
3788 static int
3789 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3790                    int *link_up, int wait_to_complete)
3791 {
3792         /**
3793          * for a quick link status checking, wait_to_compelet == 0,
3794          * skip PF link status checking
3795          */
3796         bool no_pflink_check = wait_to_complete == 0;
3797         struct ixgbe_mbx_info *mbx = &hw->mbx;
3798         struct ixgbe_mac_info *mac = &hw->mac;
3799         uint32_t links_reg, in_msg;
3800         int ret_val = 0;
3801
3802         /* If we were hit with a reset drop the link */
3803         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3804                 mac->get_link_status = true;
3805
3806         if (!mac->get_link_status)
3807                 goto out;
3808
3809         /* if link status is down no point in checking to see if pf is up */
3810         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3811         if (!(links_reg & IXGBE_LINKS_UP))
3812                 goto out;
3813
3814         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3815          * before the link status is correct
3816          */
3817         if (mac->type == ixgbe_mac_82599_vf) {
3818                 int i;
3819
3820                 for (i = 0; i < 5; i++) {
3821                         rte_delay_us(100);
3822                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3823
3824                         if (!(links_reg & IXGBE_LINKS_UP))
3825                                 goto out;
3826                 }
3827         }
3828
3829         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3830         case IXGBE_LINKS_SPEED_10G_82599:
3831                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3832                 if (hw->mac.type >= ixgbe_mac_X550) {
3833                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3834                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3835                 }
3836                 break;
3837         case IXGBE_LINKS_SPEED_1G_82599:
3838                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3839                 break;
3840         case IXGBE_LINKS_SPEED_100_82599:
3841                 *speed = IXGBE_LINK_SPEED_100_FULL;
3842                 if (hw->mac.type == ixgbe_mac_X550) {
3843                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3844                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3845                 }
3846                 break;
3847         case IXGBE_LINKS_SPEED_10_X550EM_A:
3848                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3849                 /* Since Reserved in older MAC's */
3850                 if (hw->mac.type >= ixgbe_mac_X550)
3851                         *speed = IXGBE_LINK_SPEED_10_FULL;
3852                 break;
3853         default:
3854                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3855         }
3856
3857         if (no_pflink_check) {
3858                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3859                         mac->get_link_status = true;
3860                 else
3861                         mac->get_link_status = false;
3862
3863                 goto out;
3864         }
3865         /* if the read failed it could just be a mailbox collision, best wait
3866          * until we are called again and don't report an error
3867          */
3868         if (mbx->ops.read(hw, &in_msg, 1, 0))
3869                 goto out;
3870
3871         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3872                 /* msg is not CTS and is NACK we must have lost CTS status */
3873                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3874                         ret_val = -1;
3875                 goto out;
3876         }
3877
3878         /* the pf is talking, if we timed out in the past we reinit */
3879         if (!mbx->timeout) {
3880                 ret_val = -1;
3881                 goto out;
3882         }
3883
3884         /* if we passed all the tests above then the link is up and we no
3885          * longer need to check for link
3886          */
3887         mac->get_link_status = false;
3888
3889 out:
3890         *link_up = !mac->get_link_status;
3891         return ret_val;
3892 }
3893
3894 /* return 0 means link status changed, -1 means not changed */
3895 static int
3896 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3897                             int wait_to_complete, int vf)
3898 {
3899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3900         struct rte_eth_link link, old;
3901         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3902         struct ixgbe_interrupt *intr =
3903                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3904         int link_up;
3905         int diag;
3906         u32 speed = 0;
3907         int wait = 1;
3908         bool autoneg = false;
3909
3910         link.link_status = ETH_LINK_DOWN;
3911         link.link_speed = 0;
3912         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3913         memset(&old, 0, sizeof(old));
3914         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3915
3916         hw->mac.get_link_status = true;
3917
3918         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3919                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3920                 speed = hw->phy.autoneg_advertised;
3921                 if (!speed)
3922                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3923                 ixgbe_setup_link(hw, speed, true);
3924         }
3925
3926         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3927         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3928                 wait = 0;
3929
3930         if (vf)
3931                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3932         else
3933                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3934
3935         if (diag != 0) {
3936                 link.link_speed = ETH_SPEED_NUM_100M;
3937                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3938                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3939                 if (link.link_status == old.link_status)
3940                         return -1;
3941                 return 0;
3942         }
3943
3944         if (link_up == 0) {
3945                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3946                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3947                 if (link.link_status == old.link_status)
3948                         return -1;
3949                 return 0;
3950         }
3951         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3952         link.link_status = ETH_LINK_UP;
3953         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3954
3955         switch (link_speed) {
3956         default:
3957         case IXGBE_LINK_SPEED_UNKNOWN:
3958                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3959                 link.link_speed = ETH_SPEED_NUM_100M;
3960                 break;
3961
3962         case IXGBE_LINK_SPEED_100_FULL:
3963                 link.link_speed = ETH_SPEED_NUM_100M;
3964                 break;
3965
3966         case IXGBE_LINK_SPEED_1GB_FULL:
3967                 link.link_speed = ETH_SPEED_NUM_1G;
3968                 break;
3969
3970         case IXGBE_LINK_SPEED_10GB_FULL:
3971                 link.link_speed = ETH_SPEED_NUM_10G;
3972                 break;
3973         }
3974         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3975
3976         if (link.link_status == old.link_status)
3977                 return -1;
3978
3979         return 0;
3980 }
3981
3982 static int
3983 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3984 {
3985         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3986 }
3987
3988 static int
3989 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3990 {
3991         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3992 }
3993
3994 static void
3995 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3996 {
3997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3998         uint32_t fctrl;
3999
4000         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4001         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4002         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4003 }
4004
4005 static void
4006 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4007 {
4008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4009         uint32_t fctrl;
4010
4011         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4012         fctrl &= (~IXGBE_FCTRL_UPE);
4013         if (dev->data->all_multicast == 1)
4014                 fctrl |= IXGBE_FCTRL_MPE;
4015         else
4016                 fctrl &= (~IXGBE_FCTRL_MPE);
4017         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4018 }
4019
4020 static void
4021 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4022 {
4023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4024         uint32_t fctrl;
4025
4026         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4027         fctrl |= IXGBE_FCTRL_MPE;
4028         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4029 }
4030
4031 static void
4032 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4033 {
4034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4035         uint32_t fctrl;
4036
4037         if (dev->data->promiscuous == 1)
4038                 return; /* must remain in all_multicast mode */
4039
4040         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4041         fctrl &= (~IXGBE_FCTRL_MPE);
4042         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4043 }
4044
4045 /**
4046  * It clears the interrupt causes and enables the interrupt.
4047  * It will be called once only during nic initialized.
4048  *
4049  * @param dev
4050  *  Pointer to struct rte_eth_dev.
4051  *
4052  * @return
4053  *  - On success, zero.
4054  *  - On failure, a negative value.
4055  */
4056 static int
4057 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
4058 {
4059         struct ixgbe_interrupt *intr =
4060                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4061
4062         ixgbe_dev_link_status_print(dev);
4063         intr->mask |= IXGBE_EICR_LSC;
4064
4065         return 0;
4066 }
4067
4068 /**
4069  * It clears the interrupt causes and enables the interrupt.
4070  * It will be called once only during nic initialized.
4071  *
4072  * @param dev
4073  *  Pointer to struct rte_eth_dev.
4074  *
4075  * @return
4076  *  - On success, zero.
4077  *  - On failure, a negative value.
4078  */
4079 static int
4080 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4081 {
4082         struct ixgbe_interrupt *intr =
4083                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4084
4085         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4086
4087         return 0;
4088 }
4089
4090 /**
4091  * It clears the interrupt causes and enables the interrupt.
4092  * It will be called once only during nic initialized.
4093  *
4094  * @param dev
4095  *  Pointer to struct rte_eth_dev.
4096  *
4097  * @return
4098  *  - On success, zero.
4099  *  - On failure, a negative value.
4100  */
4101 static int
4102 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4103 {
4104         struct ixgbe_interrupt *intr =
4105                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4106
4107         intr->mask |= IXGBE_EICR_LINKSEC;
4108
4109         return 0;
4110 }
4111
4112 /*
4113  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4114  *
4115  * @param dev
4116  *  Pointer to struct rte_eth_dev.
4117  *
4118  * @return
4119  *  - On success, zero.
4120  *  - On failure, a negative value.
4121  */
4122 static int
4123 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4124 {
4125         uint32_t eicr;
4126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127         struct ixgbe_interrupt *intr =
4128                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4129
4130         /* clear all cause mask */
4131         ixgbe_disable_intr(hw);
4132
4133         /* read-on-clear nic registers here */
4134         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4135         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4136
4137         intr->flags = 0;
4138
4139         /* set flag for async link update */
4140         if (eicr & IXGBE_EICR_LSC)
4141                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4142
4143         if (eicr & IXGBE_EICR_MAILBOX)
4144                 intr->flags |= IXGBE_FLAG_MAILBOX;
4145
4146         if (eicr & IXGBE_EICR_LINKSEC)
4147                 intr->flags |= IXGBE_FLAG_MACSEC;
4148
4149         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4150             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4151             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4152                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4153
4154         return 0;
4155 }
4156
4157 /**
4158  * It gets and then prints the link status.
4159  *
4160  * @param dev
4161  *  Pointer to struct rte_eth_dev.
4162  *
4163  * @return
4164  *  - On success, zero.
4165  *  - On failure, a negative value.
4166  */
4167 static void
4168 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4169 {
4170         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4171         struct rte_eth_link link;
4172
4173         memset(&link, 0, sizeof(link));
4174         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4175         if (link.link_status) {
4176                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4177                                         (int)(dev->data->port_id),
4178                                         (unsigned)link.link_speed,
4179                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4180                                         "full-duplex" : "half-duplex");
4181         } else {
4182                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4183                                 (int)(dev->data->port_id));
4184         }
4185         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4186                                 pci_dev->addr.domain,
4187                                 pci_dev->addr.bus,
4188                                 pci_dev->addr.devid,
4189                                 pci_dev->addr.function);
4190 }
4191
4192 /*
4193  * It executes link_update after knowing an interrupt occurred.
4194  *
4195  * @param dev
4196  *  Pointer to struct rte_eth_dev.
4197  *
4198  * @return
4199  *  - On success, zero.
4200  *  - On failure, a negative value.
4201  */
4202 static int
4203 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4204                            struct rte_intr_handle *intr_handle)
4205 {
4206         struct ixgbe_interrupt *intr =
4207                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4208         int64_t timeout;
4209         struct rte_eth_link link;
4210         struct ixgbe_hw *hw =
4211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4212
4213         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4214
4215         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4216                 ixgbe_pf_mbx_process(dev);
4217                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4218         }
4219
4220         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4221                 ixgbe_handle_lasi(hw);
4222                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4223         }
4224
4225         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4226                 /* get the link status before link update, for predicting later */
4227                 memset(&link, 0, sizeof(link));
4228                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4229
4230                 ixgbe_dev_link_update(dev, 0);
4231
4232                 /* likely to up */
4233                 if (!link.link_status)
4234                         /* handle it 1 sec later, wait it being stable */
4235                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4236                 /* likely to down */
4237                 else
4238                         /* handle it 4 sec later, wait it being stable */
4239                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4240
4241                 ixgbe_dev_link_status_print(dev);
4242                 if (rte_eal_alarm_set(timeout * 1000,
4243                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4244                         PMD_DRV_LOG(ERR, "Error setting alarm");
4245                 else {
4246                         /* remember original mask */
4247                         intr->mask_original = intr->mask;
4248                         /* only disable lsc interrupt */
4249                         intr->mask &= ~IXGBE_EIMS_LSC;
4250                 }
4251         }
4252
4253         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4254         ixgbe_enable_intr(dev);
4255         rte_intr_enable(intr_handle);
4256
4257         return 0;
4258 }
4259
4260 /**
4261  * Interrupt handler which shall be registered for alarm callback for delayed
4262  * handling specific interrupt to wait for the stable nic state. As the
4263  * NIC interrupt state is not stable for ixgbe after link is just down,
4264  * it needs to wait 4 seconds to get the stable status.
4265  *
4266  * @param handle
4267  *  Pointer to interrupt handle.
4268  * @param param
4269  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4270  *
4271  * @return
4272  *  void
4273  */
4274 static void
4275 ixgbe_dev_interrupt_delayed_handler(void *param)
4276 {
4277         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4278         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4279         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4280         struct ixgbe_interrupt *intr =
4281                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4282         struct ixgbe_hw *hw =
4283                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4284         uint32_t eicr;
4285
4286         ixgbe_disable_intr(hw);
4287
4288         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4289         if (eicr & IXGBE_EICR_MAILBOX)
4290                 ixgbe_pf_mbx_process(dev);
4291
4292         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4293                 ixgbe_handle_lasi(hw);
4294                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4295         }
4296
4297         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4298                 ixgbe_dev_link_update(dev, 0);
4299                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4300                 ixgbe_dev_link_status_print(dev);
4301                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4302                                               NULL, NULL);
4303         }
4304
4305         if (intr->flags & IXGBE_FLAG_MACSEC) {
4306                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4307                                               NULL, NULL);
4308                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4309         }
4310
4311         /* restore original mask */
4312         intr->mask = intr->mask_original;
4313         intr->mask_original = 0;
4314
4315         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4316         ixgbe_enable_intr(dev);
4317         rte_intr_enable(intr_handle);
4318 }
4319
4320 /**
4321  * Interrupt handler triggered by NIC  for handling
4322  * specific interrupt.
4323  *
4324  * @param handle
4325  *  Pointer to interrupt handle.
4326  * @param param
4327  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4328  *
4329  * @return
4330  *  void
4331  */
4332 static void
4333 ixgbe_dev_interrupt_handler(void *param)
4334 {
4335         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4336
4337         ixgbe_dev_interrupt_get_status(dev);
4338         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4339 }
4340
4341 static int
4342 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4343 {
4344         struct ixgbe_hw *hw;
4345
4346         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4347         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4348 }
4349
4350 static int
4351 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4352 {
4353         struct ixgbe_hw *hw;
4354
4355         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4356         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4357 }
4358
4359 static int
4360 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4361 {
4362         struct ixgbe_hw *hw;
4363         uint32_t mflcn_reg;
4364         uint32_t fccfg_reg;
4365         int rx_pause;
4366         int tx_pause;
4367
4368         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4369
4370         fc_conf->pause_time = hw->fc.pause_time;
4371         fc_conf->high_water = hw->fc.high_water[0];
4372         fc_conf->low_water = hw->fc.low_water[0];
4373         fc_conf->send_xon = hw->fc.send_xon;
4374         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4375
4376         /*
4377          * Return rx_pause status according to actual setting of
4378          * MFLCN register.
4379          */
4380         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4381         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4382                 rx_pause = 1;
4383         else
4384                 rx_pause = 0;
4385
4386         /*
4387          * Return tx_pause status according to actual setting of
4388          * FCCFG register.
4389          */
4390         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4391         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4392                 tx_pause = 1;
4393         else
4394                 tx_pause = 0;
4395
4396         if (rx_pause && tx_pause)
4397                 fc_conf->mode = RTE_FC_FULL;
4398         else if (rx_pause)
4399                 fc_conf->mode = RTE_FC_RX_PAUSE;
4400         else if (tx_pause)
4401                 fc_conf->mode = RTE_FC_TX_PAUSE;
4402         else
4403                 fc_conf->mode = RTE_FC_NONE;
4404
4405         return 0;
4406 }
4407
4408 static int
4409 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4410 {
4411         struct ixgbe_hw *hw;
4412         int err;
4413         uint32_t rx_buf_size;
4414         uint32_t max_high_water;
4415         uint32_t mflcn;
4416         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4417                 ixgbe_fc_none,
4418                 ixgbe_fc_rx_pause,
4419                 ixgbe_fc_tx_pause,
4420                 ixgbe_fc_full
4421         };
4422
4423         PMD_INIT_FUNC_TRACE();
4424
4425         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4426         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4427         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4428
4429         /*
4430          * At least reserve one Ethernet frame for watermark
4431          * high_water/low_water in kilo bytes for ixgbe
4432          */
4433         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4434         if ((fc_conf->high_water > max_high_water) ||
4435                 (fc_conf->high_water < fc_conf->low_water)) {
4436                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4437                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4438                 return -EINVAL;
4439         }
4440
4441         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4442         hw->fc.pause_time     = fc_conf->pause_time;
4443         hw->fc.high_water[0]  = fc_conf->high_water;
4444         hw->fc.low_water[0]   = fc_conf->low_water;
4445         hw->fc.send_xon       = fc_conf->send_xon;
4446         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4447
4448         err = ixgbe_fc_enable(hw);
4449
4450         /* Not negotiated is not an error case */
4451         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4452
4453                 /* check if we want to forward MAC frames - driver doesn't have native
4454                  * capability to do that, so we'll write the registers ourselves */
4455
4456                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4457
4458                 /* set or clear MFLCN.PMCF bit depending on configuration */
4459                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4460                         mflcn |= IXGBE_MFLCN_PMCF;
4461                 else
4462                         mflcn &= ~IXGBE_MFLCN_PMCF;
4463
4464                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4465                 IXGBE_WRITE_FLUSH(hw);
4466
4467                 return 0;
4468         }
4469
4470         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4471         return -EIO;
4472 }
4473
4474 /**
4475  *  ixgbe_pfc_enable_generic - Enable flow control
4476  *  @hw: pointer to hardware structure
4477  *  @tc_num: traffic class number
4478  *  Enable flow control according to the current settings.
4479  */
4480 static int
4481 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4482 {
4483         int ret_val = 0;
4484         uint32_t mflcn_reg, fccfg_reg;
4485         uint32_t reg;
4486         uint32_t fcrtl, fcrth;
4487         uint8_t i;
4488         uint8_t nb_rx_en;
4489
4490         /* Validate the water mark configuration */
4491         if (!hw->fc.pause_time) {
4492                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4493                 goto out;
4494         }
4495
4496         /* Low water mark of zero causes XOFF floods */
4497         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4498                  /* High/Low water can not be 0 */
4499                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4500                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4501                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4502                         goto out;
4503                 }
4504
4505                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4506                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4507                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4508                         goto out;
4509                 }
4510         }
4511         /* Negotiate the fc mode to use */
4512         ixgbe_fc_autoneg(hw);
4513
4514         /* Disable any previous flow control settings */
4515         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4516         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4517
4518         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4519         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4520
4521         switch (hw->fc.current_mode) {
4522         case ixgbe_fc_none:
4523                 /*
4524                  * If the count of enabled RX Priority Flow control >1,
4525                  * and the TX pause can not be disabled
4526                  */
4527                 nb_rx_en = 0;
4528                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4529                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4530                         if (reg & IXGBE_FCRTH_FCEN)
4531                                 nb_rx_en++;
4532                 }
4533                 if (nb_rx_en > 1)
4534                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4535                 break;
4536         case ixgbe_fc_rx_pause:
4537                 /*
4538                  * Rx Flow control is enabled and Tx Flow control is
4539                  * disabled by software override. Since there really
4540                  * isn't a way to advertise that we are capable of RX
4541                  * Pause ONLY, we will advertise that we support both
4542                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4543                  * disable the adapter's ability to send PAUSE frames.
4544                  */
4545                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4546                 /*
4547                  * If the count of enabled RX Priority Flow control >1,
4548                  * and the TX pause can not be disabled
4549                  */
4550                 nb_rx_en = 0;
4551                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4552                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4553                         if (reg & IXGBE_FCRTH_FCEN)
4554                                 nb_rx_en++;
4555                 }
4556                 if (nb_rx_en > 1)
4557                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4558                 break;
4559         case ixgbe_fc_tx_pause:
4560                 /*
4561                  * Tx Flow control is enabled, and Rx Flow control is
4562                  * disabled by software override.
4563                  */
4564                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4565                 break;
4566         case ixgbe_fc_full:
4567                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4568                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4569                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4570                 break;
4571         default:
4572                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4573                 ret_val = IXGBE_ERR_CONFIG;
4574                 goto out;
4575         }
4576
4577         /* Set 802.3x based flow control settings. */
4578         mflcn_reg |= IXGBE_MFLCN_DPF;
4579         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4580         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4581
4582         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4583         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4584                 hw->fc.high_water[tc_num]) {
4585                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4586                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4587                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4588         } else {
4589                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4590                 /*
4591                  * In order to prevent Tx hangs when the internal Tx
4592                  * switch is enabled we must set the high water mark
4593                  * to the maximum FCRTH value.  This allows the Tx
4594                  * switch to function even under heavy Rx workloads.
4595                  */
4596                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4597         }
4598         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4599
4600         /* Configure pause time (2 TCs per register) */
4601         reg = hw->fc.pause_time * 0x00010001;
4602         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4603                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4604
4605         /* Configure flow control refresh threshold value */
4606         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4607
4608 out:
4609         return ret_val;
4610 }
4611
4612 static int
4613 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4614 {
4615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4617
4618         if (hw->mac.type != ixgbe_mac_82598EB) {
4619                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4620         }
4621         return ret_val;
4622 }
4623
4624 static int
4625 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4626 {
4627         int err;
4628         uint32_t rx_buf_size;
4629         uint32_t max_high_water;
4630         uint8_t tc_num;
4631         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4632         struct ixgbe_hw *hw =
4633                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4634         struct ixgbe_dcb_config *dcb_config =
4635                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4636
4637         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4638                 ixgbe_fc_none,
4639                 ixgbe_fc_rx_pause,
4640                 ixgbe_fc_tx_pause,
4641                 ixgbe_fc_full
4642         };
4643
4644         PMD_INIT_FUNC_TRACE();
4645
4646         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4647         tc_num = map[pfc_conf->priority];
4648         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4649         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4650         /*
4651          * At least reserve one Ethernet frame for watermark
4652          * high_water/low_water in kilo bytes for ixgbe
4653          */
4654         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4655         if ((pfc_conf->fc.high_water > max_high_water) ||
4656             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4657                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4658                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4659                 return -EINVAL;
4660         }
4661
4662         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4663         hw->fc.pause_time = pfc_conf->fc.pause_time;
4664         hw->fc.send_xon = pfc_conf->fc.send_xon;
4665         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4666         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4667
4668         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4669
4670         /* Not negotiated is not an error case */
4671         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4672                 return 0;
4673
4674         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4675         return -EIO;
4676 }
4677
4678 static int
4679 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4680                           struct rte_eth_rss_reta_entry64 *reta_conf,
4681                           uint16_t reta_size)
4682 {
4683         uint16_t i, sp_reta_size;
4684         uint8_t j, mask;
4685         uint32_t reta, r;
4686         uint16_t idx, shift;
4687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4688         uint32_t reta_reg;
4689
4690         PMD_INIT_FUNC_TRACE();
4691
4692         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4693                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4694                         "NIC.");
4695                 return -ENOTSUP;
4696         }
4697
4698         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4699         if (reta_size != sp_reta_size) {
4700                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4701                         "(%d) doesn't match the number hardware can supported "
4702                         "(%d)", reta_size, sp_reta_size);
4703                 return -EINVAL;
4704         }
4705
4706         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4707                 idx = i / RTE_RETA_GROUP_SIZE;
4708                 shift = i % RTE_RETA_GROUP_SIZE;
4709                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4710                                                 IXGBE_4_BIT_MASK);
4711                 if (!mask)
4712                         continue;
4713                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4714                 if (mask == IXGBE_4_BIT_MASK)
4715                         r = 0;
4716                 else
4717                         r = IXGBE_READ_REG(hw, reta_reg);
4718                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4719                         if (mask & (0x1 << j))
4720                                 reta |= reta_conf[idx].reta[shift + j] <<
4721                                                         (CHAR_BIT * j);
4722                         else
4723                                 reta |= r & (IXGBE_8_BIT_MASK <<
4724                                                 (CHAR_BIT * j));
4725                 }
4726                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4727         }
4728
4729         return 0;
4730 }
4731
4732 static int
4733 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4734                          struct rte_eth_rss_reta_entry64 *reta_conf,
4735                          uint16_t reta_size)
4736 {
4737         uint16_t i, sp_reta_size;
4738         uint8_t j, mask;
4739         uint32_t reta;
4740         uint16_t idx, shift;
4741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742         uint32_t reta_reg;
4743
4744         PMD_INIT_FUNC_TRACE();
4745         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4746         if (reta_size != sp_reta_size) {
4747                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4748                         "(%d) doesn't match the number hardware can supported "
4749                         "(%d)", reta_size, sp_reta_size);
4750                 return -EINVAL;
4751         }
4752
4753         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4754                 idx = i / RTE_RETA_GROUP_SIZE;
4755                 shift = i % RTE_RETA_GROUP_SIZE;
4756                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4757                                                 IXGBE_4_BIT_MASK);
4758                 if (!mask)
4759                         continue;
4760
4761                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4762                 reta = IXGBE_READ_REG(hw, reta_reg);
4763                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4764                         if (mask & (0x1 << j))
4765                                 reta_conf[idx].reta[shift + j] =
4766                                         ((reta >> (CHAR_BIT * j)) &
4767                                                 IXGBE_8_BIT_MASK);
4768                 }
4769         }
4770
4771         return 0;
4772 }
4773
4774 static int
4775 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4776                                 uint32_t index, uint32_t pool)
4777 {
4778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4779         uint32_t enable_addr = 1;
4780
4781         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4782                              pool, enable_addr);
4783 }
4784
4785 static void
4786 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4787 {
4788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789
4790         ixgbe_clear_rar(hw, index);
4791 }
4792
4793 static void
4794 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4795 {
4796         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4797
4798         ixgbe_remove_rar(dev, 0);
4799
4800         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4801 }
4802
4803 static bool
4804 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4805 {
4806         if (strcmp(dev->device->driver->name, drv->driver.name))
4807                 return false;
4808
4809         return true;
4810 }
4811
4812 bool
4813 is_ixgbe_supported(struct rte_eth_dev *dev)
4814 {
4815         return is_device_supported(dev, &rte_ixgbe_pmd);
4816 }
4817
4818 static int
4819 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4820 {
4821         uint32_t hlreg0;
4822         uint32_t maxfrs;
4823         struct ixgbe_hw *hw;
4824         struct rte_eth_dev_info dev_info;
4825         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4826         struct rte_eth_dev_data *dev_data = dev->data;
4827
4828         ixgbe_dev_info_get(dev, &dev_info);
4829
4830         /* check that mtu is within the allowed range */
4831         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4832                 return -EINVAL;
4833
4834         /* If device is started, refuse mtu that requires the support of
4835          * scattered packets when this feature has not been enabled before.
4836          */
4837         if (dev_data->dev_started && !dev_data->scattered_rx &&
4838             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4839              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4840                 PMD_INIT_LOG(ERR, "Stop port first.");
4841                 return -EINVAL;
4842         }
4843
4844         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4846
4847         /* switch to jumbo mode if needed */
4848         if (frame_size > ETHER_MAX_LEN) {
4849                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4850                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4851         } else {
4852                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4853                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4854         }
4855         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4856
4857         /* update max frame size */
4858         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4859
4860         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4861         maxfrs &= 0x0000FFFF;
4862         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4863         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4864
4865         return 0;
4866 }
4867
4868 /*
4869  * Virtual Function operations
4870  */
4871 static void
4872 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4873 {
4874         PMD_INIT_FUNC_TRACE();
4875
4876         /* Clear interrupt mask to stop from interrupts being generated */
4877         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4878
4879         IXGBE_WRITE_FLUSH(hw);
4880 }
4881
4882 static void
4883 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4884 {
4885         PMD_INIT_FUNC_TRACE();
4886
4887         /* VF enable interrupt autoclean */
4888         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4889         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4890         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4891
4892         IXGBE_WRITE_FLUSH(hw);
4893 }
4894
4895 static int
4896 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4897 {
4898         struct rte_eth_conf *conf = &dev->data->dev_conf;
4899         struct ixgbe_adapter *adapter =
4900                         (struct ixgbe_adapter *)dev->data->dev_private;
4901
4902         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4903                      dev->data->port_id);
4904
4905         /*
4906          * VF has no ability to enable/disable HW CRC
4907          * Keep the persistent behavior the same as Host PF
4908          */
4909 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4910         if (!conf->rxmode.hw_strip_crc) {
4911                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4912                 conf->rxmode.hw_strip_crc = 1;
4913         }
4914 #else
4915         if (conf->rxmode.hw_strip_crc) {
4916                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4917                 conf->rxmode.hw_strip_crc = 0;
4918         }
4919 #endif
4920
4921         /*
4922          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4923          * allocation or vector Rx preconditions we will reset it.
4924          */
4925         adapter->rx_bulk_alloc_allowed = true;
4926         adapter->rx_vec_allowed = true;
4927
4928         return 0;
4929 }
4930
4931 static int
4932 ixgbevf_dev_start(struct rte_eth_dev *dev)
4933 {
4934         struct ixgbe_hw *hw =
4935                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4936         uint32_t intr_vector = 0;
4937         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4938         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4939
4940         int err, mask = 0;
4941
4942         PMD_INIT_FUNC_TRACE();
4943
4944         hw->mac.ops.reset_hw(hw);
4945         hw->mac.get_link_status = true;
4946
4947         /* negotiate mailbox API version to use with the PF. */
4948         ixgbevf_negotiate_api(hw);
4949
4950         ixgbevf_dev_tx_init(dev);
4951
4952         /* This can fail when allocating mbufs for descriptor rings */
4953         err = ixgbevf_dev_rx_init(dev);
4954         if (err) {
4955                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4956                 ixgbe_dev_clear_queues(dev);
4957                 return err;
4958         }
4959
4960         /* Set vfta */
4961         ixgbevf_set_vfta_all(dev, 1);
4962
4963         /* Set HW strip */
4964         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4965                 ETH_VLAN_EXTEND_MASK;
4966         ixgbevf_vlan_offload_set(dev, mask);
4967
4968         ixgbevf_dev_rxtx_start(dev);
4969
4970         /* check and configure queue intr-vector mapping */
4971         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4972                 intr_vector = dev->data->nb_rx_queues;
4973                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4974                         return -1;
4975         }
4976
4977         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4978                 intr_handle->intr_vec =
4979                         rte_zmalloc("intr_vec",
4980                                     dev->data->nb_rx_queues * sizeof(int), 0);
4981                 if (intr_handle->intr_vec == NULL) {
4982                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4983                                      " intr_vec", dev->data->nb_rx_queues);
4984                         return -ENOMEM;
4985                 }
4986         }
4987         ixgbevf_configure_msix(dev);
4988
4989         rte_intr_enable(intr_handle);
4990
4991         /* Re-enable interrupt for VF */
4992         ixgbevf_intr_enable(hw);
4993
4994         return 0;
4995 }
4996
4997 static void
4998 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4999 {
5000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5001         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5002         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5003
5004         PMD_INIT_FUNC_TRACE();
5005
5006         ixgbevf_intr_disable(hw);
5007
5008         hw->adapter_stopped = 1;
5009         ixgbe_stop_adapter(hw);
5010
5011         /*
5012           * Clear what we set, but we still keep shadow_vfta to
5013           * restore after device starts
5014           */
5015         ixgbevf_set_vfta_all(dev, 0);
5016
5017         /* Clear stored conf */
5018         dev->data->scattered_rx = 0;
5019
5020         ixgbe_dev_clear_queues(dev);
5021
5022         /* Clean datapath event and queue/vec mapping */
5023         rte_intr_efd_disable(intr_handle);
5024         if (intr_handle->intr_vec != NULL) {
5025                 rte_free(intr_handle->intr_vec);
5026                 intr_handle->intr_vec = NULL;
5027         }
5028 }
5029
5030 static void
5031 ixgbevf_dev_close(struct rte_eth_dev *dev)
5032 {
5033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5034
5035         PMD_INIT_FUNC_TRACE();
5036
5037         ixgbe_reset_hw(hw);
5038
5039         ixgbevf_dev_stop(dev);
5040
5041         ixgbe_dev_free_queues(dev);
5042
5043         /**
5044          * Remove the VF MAC address ro ensure
5045          * that the VF traffic goes to the PF
5046          * after stop, close and detach of the VF
5047          **/
5048         ixgbevf_remove_mac_addr(dev, 0);
5049 }
5050
5051 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5052 {
5053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5054         struct ixgbe_vfta *shadow_vfta =
5055                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5056         int i = 0, j = 0, vfta = 0, mask = 1;
5057
5058         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5059                 vfta = shadow_vfta->vfta[i];
5060                 if (vfta) {
5061                         mask = 1;
5062                         for (j = 0; j < 32; j++) {
5063                                 if (vfta & mask)
5064                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5065                                                        on, false);
5066                                 mask <<= 1;
5067                         }
5068                 }
5069         }
5070
5071 }
5072
5073 static int
5074 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5075 {
5076         struct ixgbe_hw *hw =
5077                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5078         struct ixgbe_vfta *shadow_vfta =
5079                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5080         uint32_t vid_idx = 0;
5081         uint32_t vid_bit = 0;
5082         int ret = 0;
5083
5084         PMD_INIT_FUNC_TRACE();
5085
5086         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5087         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5088         if (ret) {
5089                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5090                 return ret;
5091         }
5092         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5093         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5094
5095         /* Save what we set and retore it after device reset */
5096         if (on)
5097                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5098         else
5099                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5100
5101         return 0;
5102 }
5103
5104 static void
5105 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5106 {
5107         struct ixgbe_hw *hw =
5108                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109         uint32_t ctrl;
5110
5111         PMD_INIT_FUNC_TRACE();
5112
5113         if (queue >= hw->mac.max_rx_queues)
5114                 return;
5115
5116         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5117         if (on)
5118                 ctrl |= IXGBE_RXDCTL_VME;
5119         else
5120                 ctrl &= ~IXGBE_RXDCTL_VME;
5121         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5122
5123         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5124 }
5125
5126 static void
5127 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5128 {
5129         struct ixgbe_hw *hw =
5130                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131         uint16_t i;
5132         int on = 0;
5133
5134         /* VF function only support hw strip feature, others are not support */
5135         if (mask & ETH_VLAN_STRIP_MASK) {
5136                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5137
5138                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5139                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5140         }
5141 }
5142
5143 int
5144 ixgbe_vt_check(struct ixgbe_hw *hw)
5145 {
5146         uint32_t reg_val;
5147
5148         /* if Virtualization Technology is enabled */
5149         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5150         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5151                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5152                 return -1;
5153         }
5154
5155         return 0;
5156 }
5157
5158 static uint32_t
5159 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5160 {
5161         uint32_t vector = 0;
5162
5163         switch (hw->mac.mc_filter_type) {
5164         case 0:   /* use bits [47:36] of the address */
5165                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5166                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5167                 break;
5168         case 1:   /* use bits [46:35] of the address */
5169                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5170                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5171                 break;
5172         case 2:   /* use bits [45:34] of the address */
5173                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5174                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5175                 break;
5176         case 3:   /* use bits [43:32] of the address */
5177                 vector = ((uc_addr->addr_bytes[4]) |
5178                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5179                 break;
5180         default:  /* Invalid mc_filter_type */
5181                 break;
5182         }
5183
5184         /* vector can only be 12-bits or boundary will be exceeded */
5185         vector &= 0xFFF;
5186         return vector;
5187 }
5188
5189 static int
5190 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5191                         uint8_t on)
5192 {
5193         uint32_t vector;
5194         uint32_t uta_idx;
5195         uint32_t reg_val;
5196         uint32_t uta_shift;
5197         uint32_t rc;
5198         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5199         const uint32_t ixgbe_uta_bit_shift = 5;
5200         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5201         const uint32_t bit1 = 0x1;
5202
5203         struct ixgbe_hw *hw =
5204                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205         struct ixgbe_uta_info *uta_info =
5206                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5207
5208         /* The UTA table only exists on 82599 hardware and newer */
5209         if (hw->mac.type < ixgbe_mac_82599EB)
5210                 return -ENOTSUP;
5211
5212         vector = ixgbe_uta_vector(hw, mac_addr);
5213         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5214         uta_shift = vector & ixgbe_uta_bit_mask;
5215
5216         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5217         if (rc == on)
5218                 return 0;
5219
5220         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5221         if (on) {
5222                 uta_info->uta_in_use++;
5223                 reg_val |= (bit1 << uta_shift);
5224                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5225         } else {
5226                 uta_info->uta_in_use--;
5227                 reg_val &= ~(bit1 << uta_shift);
5228                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5229         }
5230
5231         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5232
5233         if (uta_info->uta_in_use > 0)
5234                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5235                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5236         else
5237                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5238
5239         return 0;
5240 }
5241
5242 static int
5243 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5244 {
5245         int i;
5246         struct ixgbe_hw *hw =
5247                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5248         struct ixgbe_uta_info *uta_info =
5249                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5250
5251         /* The UTA table only exists on 82599 hardware and newer */
5252         if (hw->mac.type < ixgbe_mac_82599EB)
5253                 return -ENOTSUP;
5254
5255         if (on) {
5256                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5257                         uta_info->uta_shadow[i] = ~0;
5258                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5259                 }
5260         } else {
5261                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5262                         uta_info->uta_shadow[i] = 0;
5263                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5264                 }
5265         }
5266         return 0;
5267
5268 }
5269
5270 uint32_t
5271 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5272 {
5273         uint32_t new_val = orig_val;
5274
5275         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5276                 new_val |= IXGBE_VMOLR_AUPE;
5277         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5278                 new_val |= IXGBE_VMOLR_ROMPE;
5279         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5280                 new_val |= IXGBE_VMOLR_ROPE;
5281         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5282                 new_val |= IXGBE_VMOLR_BAM;
5283         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5284                 new_val |= IXGBE_VMOLR_MPE;
5285
5286         return new_val;
5287 }
5288
5289 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5290 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5291 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5292 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5293 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5294         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5295         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5296
5297 static int
5298 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5299                       struct rte_eth_mirror_conf *mirror_conf,
5300                       uint8_t rule_id, uint8_t on)
5301 {
5302         uint32_t mr_ctl, vlvf;
5303         uint32_t mp_lsb = 0;
5304         uint32_t mv_msb = 0;
5305         uint32_t mv_lsb = 0;
5306         uint32_t mp_msb = 0;
5307         uint8_t i = 0;
5308         int reg_index = 0;
5309         uint64_t vlan_mask = 0;
5310
5311         const uint8_t pool_mask_offset = 32;
5312         const uint8_t vlan_mask_offset = 32;
5313         const uint8_t dst_pool_offset = 8;
5314         const uint8_t rule_mr_offset  = 4;
5315         const uint8_t mirror_rule_mask = 0x0F;
5316
5317         struct ixgbe_mirror_info *mr_info =
5318                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5319         struct ixgbe_hw *hw =
5320                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5321         uint8_t mirror_type = 0;
5322
5323         if (ixgbe_vt_check(hw) < 0)
5324                 return -ENOTSUP;
5325
5326         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5327                 return -EINVAL;
5328
5329         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5330                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5331                             mirror_conf->rule_type);
5332                 return -EINVAL;
5333         }
5334
5335         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5336                 mirror_type |= IXGBE_MRCTL_VLME;
5337                 /* Check if vlan id is valid and find conresponding VLAN ID
5338                  * index in VLVF
5339                  */
5340                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5341                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5342                                 /* search vlan id related pool vlan filter
5343                                  * index
5344                                  */
5345                                 reg_index = ixgbe_find_vlvf_slot(
5346                                                 hw,
5347                                                 mirror_conf->vlan.vlan_id[i],
5348                                                 false);
5349                                 if (reg_index < 0)
5350                                         return -EINVAL;
5351                                 vlvf = IXGBE_READ_REG(hw,
5352                                                       IXGBE_VLVF(reg_index));
5353                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5354                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5355                                       mirror_conf->vlan.vlan_id[i]))
5356                                         vlan_mask |= (1ULL << reg_index);
5357                                 else
5358                                         return -EINVAL;
5359                         }
5360                 }
5361
5362                 if (on) {
5363                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5364                         mv_msb = vlan_mask >> vlan_mask_offset;
5365
5366                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5367                                                 mirror_conf->vlan.vlan_mask;
5368                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5369                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5370                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5371                                                 mirror_conf->vlan.vlan_id[i];
5372                         }
5373                 } else {
5374                         mv_lsb = 0;
5375                         mv_msb = 0;
5376                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5377                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5378                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5379                 }
5380         }
5381
5382         /**
5383          * if enable pool mirror, write related pool mask register,if disable
5384          * pool mirror, clear PFMRVM register
5385          */
5386         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5387                 mirror_type |= IXGBE_MRCTL_VPME;
5388                 if (on) {
5389                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5390                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5391                         mr_info->mr_conf[rule_id].pool_mask =
5392                                         mirror_conf->pool_mask;
5393
5394                 } else {
5395                         mp_lsb = 0;
5396                         mp_msb = 0;
5397                         mr_info->mr_conf[rule_id].pool_mask = 0;
5398                 }
5399         }
5400         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5401                 mirror_type |= IXGBE_MRCTL_UPME;
5402         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5403                 mirror_type |= IXGBE_MRCTL_DPME;
5404
5405         /* read  mirror control register and recalculate it */
5406         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5407
5408         if (on) {
5409                 mr_ctl |= mirror_type;
5410                 mr_ctl &= mirror_rule_mask;
5411                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5412         } else {
5413                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5414         }
5415
5416         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5417         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5418
5419         /* write mirrror control  register */
5420         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5421
5422         /* write pool mirrror control  register */
5423         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5424                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5425                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5426                                 mp_msb);
5427         }
5428         /* write VLAN mirrror control  register */
5429         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5430                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5431                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5432                                 mv_msb);
5433         }
5434
5435         return 0;
5436 }
5437
5438 static int
5439 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5440 {
5441         int mr_ctl = 0;
5442         uint32_t lsb_val = 0;
5443         uint32_t msb_val = 0;
5444         const uint8_t rule_mr_offset = 4;
5445
5446         struct ixgbe_hw *hw =
5447                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5448         struct ixgbe_mirror_info *mr_info =
5449                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5450
5451         if (ixgbe_vt_check(hw) < 0)
5452                 return -ENOTSUP;
5453
5454         memset(&mr_info->mr_conf[rule_id], 0,
5455                sizeof(struct rte_eth_mirror_conf));
5456
5457         /* clear PFVMCTL register */
5458         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5459
5460         /* clear pool mask register */
5461         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5462         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5463
5464         /* clear vlan mask register */
5465         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5466         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5467
5468         return 0;
5469 }
5470
5471 static int
5472 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5473 {
5474         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5475         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5476         uint32_t mask;
5477         struct ixgbe_hw *hw =
5478                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5479
5480         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5481         mask |= (1 << IXGBE_MISC_VEC_ID);
5482         RTE_SET_USED(queue_id);
5483         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5484
5485         rte_intr_enable(intr_handle);
5486
5487         return 0;
5488 }
5489
5490 static int
5491 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5492 {
5493         uint32_t mask;
5494         struct ixgbe_hw *hw =
5495                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5496
5497         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5498         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5499         RTE_SET_USED(queue_id);
5500         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5501
5502         return 0;
5503 }
5504
5505 static int
5506 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5507 {
5508         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5509         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5510         uint32_t mask;
5511         struct ixgbe_hw *hw =
5512                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5513         struct ixgbe_interrupt *intr =
5514                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5515
5516         if (queue_id < 16) {
5517                 ixgbe_disable_intr(hw);
5518                 intr->mask |= (1 << queue_id);
5519                 ixgbe_enable_intr(dev);
5520         } else if (queue_id < 32) {
5521                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5522                 mask &= (1 << queue_id);
5523                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5524         } else if (queue_id < 64) {
5525                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5526                 mask &= (1 << (queue_id - 32));
5527                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5528         }
5529         rte_intr_enable(intr_handle);
5530
5531         return 0;
5532 }
5533
5534 static int
5535 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5536 {
5537         uint32_t mask;
5538         struct ixgbe_hw *hw =
5539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5540         struct ixgbe_interrupt *intr =
5541                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5542
5543         if (queue_id < 16) {
5544                 ixgbe_disable_intr(hw);
5545                 intr->mask &= ~(1 << queue_id);
5546                 ixgbe_enable_intr(dev);
5547         } else if (queue_id < 32) {
5548                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5549                 mask &= ~(1 << queue_id);
5550                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5551         } else if (queue_id < 64) {
5552                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5553                 mask &= ~(1 << (queue_id - 32));
5554                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5555         }
5556
5557         return 0;
5558 }
5559
5560 static void
5561 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5562                      uint8_t queue, uint8_t msix_vector)
5563 {
5564         uint32_t tmp, idx;
5565
5566         if (direction == -1) {
5567                 /* other causes */
5568                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5569                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5570                 tmp &= ~0xFF;
5571                 tmp |= msix_vector;
5572                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5573         } else {
5574                 /* rx or tx cause */
5575                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5576                 idx = ((16 * (queue & 1)) + (8 * direction));
5577                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5578                 tmp &= ~(0xFF << idx);
5579                 tmp |= (msix_vector << idx);
5580                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5581         }
5582 }
5583
5584 /**
5585  * set the IVAR registers, mapping interrupt causes to vectors
5586  * @param hw
5587  *  pointer to ixgbe_hw struct
5588  * @direction
5589  *  0 for Rx, 1 for Tx, -1 for other causes
5590  * @queue
5591  *  queue to map the corresponding interrupt to
5592  * @msix_vector
5593  *  the vector to map to the corresponding queue
5594  */
5595 static void
5596 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5597                    uint8_t queue, uint8_t msix_vector)
5598 {
5599         uint32_t tmp, idx;
5600
5601         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5602         if (hw->mac.type == ixgbe_mac_82598EB) {
5603                 if (direction == -1)
5604                         direction = 0;
5605                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5606                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5607                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5608                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5609                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5610         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5611                         (hw->mac.type == ixgbe_mac_X540)) {
5612                 if (direction == -1) {
5613                         /* other causes */
5614                         idx = ((queue & 1) * 8);
5615                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5616                         tmp &= ~(0xFF << idx);
5617                         tmp |= (msix_vector << idx);
5618                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5619                 } else {
5620                         /* rx or tx causes */
5621                         idx = ((16 * (queue & 1)) + (8 * direction));
5622                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5623                         tmp &= ~(0xFF << idx);
5624                         tmp |= (msix_vector << idx);
5625                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5626                 }
5627         }
5628 }
5629
5630 static void
5631 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5632 {
5633         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5634         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5635         struct ixgbe_hw *hw =
5636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5637         uint32_t q_idx;
5638         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5639
5640         /* Configure VF other cause ivar */
5641         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5642
5643         /* won't configure msix register if no mapping is done
5644          * between intr vector and event fd.
5645          */
5646         if (!rte_intr_dp_is_en(intr_handle))
5647                 return;
5648
5649         /* Configure all RX queues of VF */
5650         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5651                 /* Force all queue use vector 0,
5652                  * as IXGBE_VF_MAXMSIVECOTR = 1
5653                  */
5654                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5655                 intr_handle->intr_vec[q_idx] = vector_idx;
5656         }
5657 }
5658
5659 /**
5660  * Sets up the hardware to properly generate MSI-X interrupts
5661  * @hw
5662  *  board private structure
5663  */
5664 static void
5665 ixgbe_configure_msix(struct rte_eth_dev *dev)
5666 {
5667         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5668         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5669         struct ixgbe_hw *hw =
5670                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5671         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5672         uint32_t vec = IXGBE_MISC_VEC_ID;
5673         uint32_t mask;
5674         uint32_t gpie;
5675
5676         /* won't configure msix register if no mapping is done
5677          * between intr vector and event fd
5678          */
5679         if (!rte_intr_dp_is_en(intr_handle))
5680                 return;
5681
5682         if (rte_intr_allow_others(intr_handle))
5683                 vec = base = IXGBE_RX_VEC_START;
5684
5685         /* setup GPIE for MSI-x mode */
5686         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5687         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5688                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5689         /* auto clearing and auto setting corresponding bits in EIMS
5690          * when MSI-X interrupt is triggered
5691          */
5692         if (hw->mac.type == ixgbe_mac_82598EB) {
5693                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5694         } else {
5695                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5696                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5697         }
5698         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5699
5700         /* Populate the IVAR table and set the ITR values to the
5701          * corresponding register.
5702          */
5703         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5704              queue_id++) {
5705                 /* by default, 1:1 mapping */
5706                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5707                 intr_handle->intr_vec[queue_id] = vec;
5708                 if (vec < base + intr_handle->nb_efd - 1)
5709                         vec++;
5710         }
5711
5712         switch (hw->mac.type) {
5713         case ixgbe_mac_82598EB:
5714                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5715                                    IXGBE_MISC_VEC_ID);
5716                 break;
5717         case ixgbe_mac_82599EB:
5718         case ixgbe_mac_X540:
5719                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5720                 break;
5721         default:
5722                 break;
5723         }
5724         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5725                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5726
5727         /* set up to autoclear timer, and the vectors */
5728         mask = IXGBE_EIMS_ENABLE_MASK;
5729         mask &= ~(IXGBE_EIMS_OTHER |
5730                   IXGBE_EIMS_MAILBOX |
5731                   IXGBE_EIMS_LSC);
5732
5733         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5734 }
5735
5736 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5737         uint16_t queue_idx, uint16_t tx_rate)
5738 {
5739         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5740         uint32_t rf_dec, rf_int;
5741         uint32_t bcnrc_val;
5742         uint16_t link_speed = dev->data->dev_link.link_speed;
5743
5744         if (queue_idx >= hw->mac.max_tx_queues)
5745                 return -EINVAL;
5746
5747         if (tx_rate != 0) {
5748                 /* Calculate the rate factor values to set */
5749                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5750                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5751                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5752
5753                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5754                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5755                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5756                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5757         } else {
5758                 bcnrc_val = 0;
5759         }
5760
5761         /*
5762          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5763          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5764          * set as 0x4.
5765          */
5766         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5767                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5768                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5769                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5770                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5771         else
5772                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5773                         IXGBE_MMW_SIZE_DEFAULT);
5774
5775         /* Set RTTBCNRC of queue X */
5776         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5777         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5778         IXGBE_WRITE_FLUSH(hw);
5779
5780         return 0;
5781 }
5782
5783 static int
5784 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5785                      __attribute__((unused)) uint32_t index,
5786                      __attribute__((unused)) uint32_t pool)
5787 {
5788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5789         int diag;
5790
5791         /*
5792          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5793          * operation. Trap this case to avoid exhausting the [very limited]
5794          * set of PF resources used to store VF MAC addresses.
5795          */
5796         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5797                 return -1;
5798         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5799         if (diag != 0)
5800                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5801                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5802                             mac_addr->addr_bytes[0],
5803                             mac_addr->addr_bytes[1],
5804                             mac_addr->addr_bytes[2],
5805                             mac_addr->addr_bytes[3],
5806                             mac_addr->addr_bytes[4],
5807                             mac_addr->addr_bytes[5],
5808                             diag);
5809         return diag;
5810 }
5811
5812 static void
5813 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5814 {
5815         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5816         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5817         struct ether_addr *mac_addr;
5818         uint32_t i;
5819         int diag;
5820
5821         /*
5822          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5823          * not support the deletion of a given MAC address.
5824          * Instead, it imposes to delete all MAC addresses, then to add again
5825          * all MAC addresses with the exception of the one to be deleted.
5826          */
5827         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5828
5829         /*
5830          * Add again all MAC addresses, with the exception of the deleted one
5831          * and of the permanent MAC address.
5832          */
5833         for (i = 0, mac_addr = dev->data->mac_addrs;
5834              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5835                 /* Skip the deleted MAC address */
5836                 if (i == index)
5837                         continue;
5838                 /* Skip NULL MAC addresses */
5839                 if (is_zero_ether_addr(mac_addr))
5840                         continue;
5841                 /* Skip the permanent MAC address */
5842                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5843                         continue;
5844                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5845                 if (diag != 0)
5846                         PMD_DRV_LOG(ERR,
5847                                     "Adding again MAC address "
5848                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5849                                     "diag=%d",
5850                                     mac_addr->addr_bytes[0],
5851                                     mac_addr->addr_bytes[1],
5852                                     mac_addr->addr_bytes[2],
5853                                     mac_addr->addr_bytes[3],
5854                                     mac_addr->addr_bytes[4],
5855                                     mac_addr->addr_bytes[5],
5856                                     diag);
5857         }
5858 }
5859
5860 static void
5861 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5862 {
5863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5864
5865         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5866 }
5867
5868 int
5869 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5870                         struct rte_eth_syn_filter *filter,
5871                         bool add)
5872 {
5873         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5874         struct ixgbe_filter_info *filter_info =
5875                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5876         uint32_t syn_info;
5877         uint32_t synqf;
5878
5879         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5880                 return -EINVAL;
5881
5882         syn_info = filter_info->syn_info;
5883
5884         if (add) {
5885                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5886                         return -EINVAL;
5887                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5888                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5889
5890                 if (filter->hig_pri)
5891                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5892                 else
5893                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5894         } else {
5895                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5896                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5897                         return -ENOENT;
5898                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5899         }
5900
5901         filter_info->syn_info = synqf;
5902         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5903         IXGBE_WRITE_FLUSH(hw);
5904         return 0;
5905 }
5906
5907 static int
5908 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5909                         struct rte_eth_syn_filter *filter)
5910 {
5911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5912         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5913
5914         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5915                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5916                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5917                 return 0;
5918         }
5919         return -ENOENT;
5920 }
5921
5922 static int
5923 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5924                         enum rte_filter_op filter_op,
5925                         void *arg)
5926 {
5927         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5928         int ret;
5929
5930         MAC_TYPE_FILTER_SUP(hw->mac.type);
5931
5932         if (filter_op == RTE_ETH_FILTER_NOP)
5933                 return 0;
5934
5935         if (arg == NULL) {
5936                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5937                             filter_op);
5938                 return -EINVAL;
5939         }
5940
5941         switch (filter_op) {
5942         case RTE_ETH_FILTER_ADD:
5943                 ret = ixgbe_syn_filter_set(dev,
5944                                 (struct rte_eth_syn_filter *)arg,
5945                                 TRUE);
5946                 break;
5947         case RTE_ETH_FILTER_DELETE:
5948                 ret = ixgbe_syn_filter_set(dev,
5949                                 (struct rte_eth_syn_filter *)arg,
5950                                 FALSE);
5951                 break;
5952         case RTE_ETH_FILTER_GET:
5953                 ret = ixgbe_syn_filter_get(dev,
5954                                 (struct rte_eth_syn_filter *)arg);
5955                 break;
5956         default:
5957                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5958                 ret = -EINVAL;
5959                 break;
5960         }
5961
5962         return ret;
5963 }
5964
5965
5966 static inline enum ixgbe_5tuple_protocol
5967 convert_protocol_type(uint8_t protocol_value)
5968 {
5969         if (protocol_value == IPPROTO_TCP)
5970                 return IXGBE_FILTER_PROTOCOL_TCP;
5971         else if (protocol_value == IPPROTO_UDP)
5972                 return IXGBE_FILTER_PROTOCOL_UDP;
5973         else if (protocol_value == IPPROTO_SCTP)
5974                 return IXGBE_FILTER_PROTOCOL_SCTP;
5975         else
5976                 return IXGBE_FILTER_PROTOCOL_NONE;
5977 }
5978
5979 /* inject a 5-tuple filter to HW */
5980 static inline void
5981 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5982                            struct ixgbe_5tuple_filter *filter)
5983 {
5984         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5985         int i;
5986         uint32_t ftqf, sdpqf;
5987         uint32_t l34timir = 0;
5988         uint8_t mask = 0xff;
5989
5990         i = filter->index;
5991
5992         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5993                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5994         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5995
5996         ftqf = (uint32_t)(filter->filter_info.proto &
5997                 IXGBE_FTQF_PROTOCOL_MASK);
5998         ftqf |= (uint32_t)((filter->filter_info.priority &
5999                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6000         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6001                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6002         if (filter->filter_info.dst_ip_mask == 0)
6003                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6004         if (filter->filter_info.src_port_mask == 0)
6005                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6006         if (filter->filter_info.dst_port_mask == 0)
6007                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6008         if (filter->filter_info.proto_mask == 0)
6009                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6010         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6011         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6012         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6013
6014         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6015         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6016         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6017         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6018
6019         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6020         l34timir |= (uint32_t)(filter->queue <<
6021                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6022         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6023 }
6024
6025 /*
6026  * add a 5tuple filter
6027  *
6028  * @param
6029  * dev: Pointer to struct rte_eth_dev.
6030  * index: the index the filter allocates.
6031  * filter: ponter to the filter that will be added.
6032  * rx_queue: the queue id the filter assigned to.
6033  *
6034  * @return
6035  *    - On success, zero.
6036  *    - On failure, a negative value.
6037  */
6038 static int
6039 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6040                         struct ixgbe_5tuple_filter *filter)
6041 {
6042         struct ixgbe_filter_info *filter_info =
6043                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6044         int i, idx, shift;
6045
6046         /*
6047          * look for an unused 5tuple filter index,
6048          * and insert the filter to list.
6049          */
6050         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6051                 idx = i / (sizeof(uint32_t) * NBBY);
6052                 shift = i % (sizeof(uint32_t) * NBBY);
6053                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6054                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6055                         filter->index = i;
6056                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6057                                           filter,
6058                                           entries);
6059                         break;
6060                 }
6061         }
6062         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6063                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6064                 return -ENOSYS;
6065         }
6066
6067         ixgbe_inject_5tuple_filter(dev, filter);
6068
6069         return 0;
6070 }
6071
6072 /*
6073  * remove a 5tuple filter
6074  *
6075  * @param
6076  * dev: Pointer to struct rte_eth_dev.
6077  * filter: the pointer of the filter will be removed.
6078  */
6079 static void
6080 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6081                         struct ixgbe_5tuple_filter *filter)
6082 {
6083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6084         struct ixgbe_filter_info *filter_info =
6085                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6086         uint16_t index = filter->index;
6087
6088         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6089                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6090         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6091         rte_free(filter);
6092
6093         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6094         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6095         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6096         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6097         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6098 }
6099
6100 static int
6101 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6102 {
6103         struct ixgbe_hw *hw;
6104         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6105         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6106
6107         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6108
6109         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6110                 return -EINVAL;
6111
6112         /* refuse mtu that requires the support of scattered packets when this
6113          * feature has not been enabled before.
6114          */
6115         if (!rx_conf->enable_scatter &&
6116             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6117              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6118                 return -EINVAL;
6119
6120         /*
6121          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6122          * request of the version 2.0 of the mailbox API.
6123          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6124          * of the mailbox API.
6125          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6126          * prior to 3.11.33 which contains the following change:
6127          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6128          */
6129         ixgbevf_rlpml_set_vf(hw, max_frame);
6130
6131         /* update max frame size */
6132         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6133         return 0;
6134 }
6135
6136 static inline struct ixgbe_5tuple_filter *
6137 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6138                         struct ixgbe_5tuple_filter_info *key)
6139 {
6140         struct ixgbe_5tuple_filter *it;
6141
6142         TAILQ_FOREACH(it, filter_list, entries) {
6143                 if (memcmp(key, &it->filter_info,
6144                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6145                         return it;
6146                 }
6147         }
6148         return NULL;
6149 }
6150
6151 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6152 static inline int
6153 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6154                         struct ixgbe_5tuple_filter_info *filter_info)
6155 {
6156         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6157                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6158                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6159                 return -EINVAL;
6160
6161         switch (filter->dst_ip_mask) {
6162         case UINT32_MAX:
6163                 filter_info->dst_ip_mask = 0;
6164                 filter_info->dst_ip = filter->dst_ip;
6165                 break;
6166         case 0:
6167                 filter_info->dst_ip_mask = 1;
6168                 break;
6169         default:
6170                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6171                 return -EINVAL;
6172         }
6173
6174         switch (filter->src_ip_mask) {
6175         case UINT32_MAX:
6176                 filter_info->src_ip_mask = 0;
6177                 filter_info->src_ip = filter->src_ip;
6178                 break;
6179         case 0:
6180                 filter_info->src_ip_mask = 1;
6181                 break;
6182         default:
6183                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6184                 return -EINVAL;
6185         }
6186
6187         switch (filter->dst_port_mask) {
6188         case UINT16_MAX:
6189                 filter_info->dst_port_mask = 0;
6190                 filter_info->dst_port = filter->dst_port;
6191                 break;
6192         case 0:
6193                 filter_info->dst_port_mask = 1;
6194                 break;
6195         default:
6196                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6197                 return -EINVAL;
6198         }
6199
6200         switch (filter->src_port_mask) {
6201         case UINT16_MAX:
6202                 filter_info->src_port_mask = 0;
6203                 filter_info->src_port = filter->src_port;
6204                 break;
6205         case 0:
6206                 filter_info->src_port_mask = 1;
6207                 break;
6208         default:
6209                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6210                 return -EINVAL;
6211         }
6212
6213         switch (filter->proto_mask) {
6214         case UINT8_MAX:
6215                 filter_info->proto_mask = 0;
6216                 filter_info->proto =
6217                         convert_protocol_type(filter->proto);
6218                 break;
6219         case 0:
6220                 filter_info->proto_mask = 1;
6221                 break;
6222         default:
6223                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6224                 return -EINVAL;
6225         }
6226
6227         filter_info->priority = (uint8_t)filter->priority;
6228         return 0;
6229 }
6230
6231 /*
6232  * add or delete a ntuple filter
6233  *
6234  * @param
6235  * dev: Pointer to struct rte_eth_dev.
6236  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6237  * add: if true, add filter, if false, remove filter
6238  *
6239  * @return
6240  *    - On success, zero.
6241  *    - On failure, a negative value.
6242  */
6243 int
6244 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6245                         struct rte_eth_ntuple_filter *ntuple_filter,
6246                         bool add)
6247 {
6248         struct ixgbe_filter_info *filter_info =
6249                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6250         struct ixgbe_5tuple_filter_info filter_5tuple;
6251         struct ixgbe_5tuple_filter *filter;
6252         int ret;
6253
6254         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6255                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6256                 return -EINVAL;
6257         }
6258
6259         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6260         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6261         if (ret < 0)
6262                 return ret;
6263
6264         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6265                                          &filter_5tuple);
6266         if (filter != NULL && add) {
6267                 PMD_DRV_LOG(ERR, "filter exists.");
6268                 return -EEXIST;
6269         }
6270         if (filter == NULL && !add) {
6271                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6272                 return -ENOENT;
6273         }
6274
6275         if (add) {
6276                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6277                                 sizeof(struct ixgbe_5tuple_filter), 0);
6278                 if (filter == NULL)
6279                         return -ENOMEM;
6280                 (void)rte_memcpy(&filter->filter_info,
6281                                  &filter_5tuple,
6282                                  sizeof(struct ixgbe_5tuple_filter_info));
6283                 filter->queue = ntuple_filter->queue;
6284                 ret = ixgbe_add_5tuple_filter(dev, filter);
6285                 if (ret < 0) {
6286                         rte_free(filter);
6287                         return ret;
6288                 }
6289         } else
6290                 ixgbe_remove_5tuple_filter(dev, filter);
6291
6292         return 0;
6293 }
6294
6295 /*
6296  * get a ntuple filter
6297  *
6298  * @param
6299  * dev: Pointer to struct rte_eth_dev.
6300  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6301  *
6302  * @return
6303  *    - On success, zero.
6304  *    - On failure, a negative value.
6305  */
6306 static int
6307 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6308                         struct rte_eth_ntuple_filter *ntuple_filter)
6309 {
6310         struct ixgbe_filter_info *filter_info =
6311                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6312         struct ixgbe_5tuple_filter_info filter_5tuple;
6313         struct ixgbe_5tuple_filter *filter;
6314         int ret;
6315
6316         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6317                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6318                 return -EINVAL;
6319         }
6320
6321         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6322         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6323         if (ret < 0)
6324                 return ret;
6325
6326         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6327                                          &filter_5tuple);
6328         if (filter == NULL) {
6329                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6330                 return -ENOENT;
6331         }
6332         ntuple_filter->queue = filter->queue;
6333         return 0;
6334 }
6335
6336 /*
6337  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6338  * @dev: pointer to rte_eth_dev structure
6339  * @filter_op:operation will be taken.
6340  * @arg: a pointer to specific structure corresponding to the filter_op
6341  *
6342  * @return
6343  *    - On success, zero.
6344  *    - On failure, a negative value.
6345  */
6346 static int
6347 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6348                                 enum rte_filter_op filter_op,
6349                                 void *arg)
6350 {
6351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6352         int ret;
6353
6354         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6355
6356         if (filter_op == RTE_ETH_FILTER_NOP)
6357                 return 0;
6358
6359         if (arg == NULL) {
6360                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6361                             filter_op);
6362                 return -EINVAL;
6363         }
6364
6365         switch (filter_op) {
6366         case RTE_ETH_FILTER_ADD:
6367                 ret = ixgbe_add_del_ntuple_filter(dev,
6368                         (struct rte_eth_ntuple_filter *)arg,
6369                         TRUE);
6370                 break;
6371         case RTE_ETH_FILTER_DELETE:
6372                 ret = ixgbe_add_del_ntuple_filter(dev,
6373                         (struct rte_eth_ntuple_filter *)arg,
6374                         FALSE);
6375                 break;
6376         case RTE_ETH_FILTER_GET:
6377                 ret = ixgbe_get_ntuple_filter(dev,
6378                         (struct rte_eth_ntuple_filter *)arg);
6379                 break;
6380         default:
6381                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6382                 ret = -EINVAL;
6383                 break;
6384         }
6385         return ret;
6386 }
6387
6388 int
6389 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6390                         struct rte_eth_ethertype_filter *filter,
6391                         bool add)
6392 {
6393         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6394         struct ixgbe_filter_info *filter_info =
6395                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6396         uint32_t etqf = 0;
6397         uint32_t etqs = 0;
6398         int ret;
6399         struct ixgbe_ethertype_filter ethertype_filter;
6400
6401         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6402                 return -EINVAL;
6403
6404         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6405                 filter->ether_type == ETHER_TYPE_IPv6) {
6406                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6407                         " ethertype filter.", filter->ether_type);
6408                 return -EINVAL;
6409         }
6410
6411         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6412                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6413                 return -EINVAL;
6414         }
6415         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6416                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6417                 return -EINVAL;
6418         }
6419
6420         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6421         if (ret >= 0 && add) {
6422                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6423                             filter->ether_type);
6424                 return -EEXIST;
6425         }
6426         if (ret < 0 && !add) {
6427                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6428                             filter->ether_type);
6429                 return -ENOENT;
6430         }
6431
6432         if (add) {
6433                 etqf = IXGBE_ETQF_FILTER_EN;
6434                 etqf |= (uint32_t)filter->ether_type;
6435                 etqs |= (uint32_t)((filter->queue <<
6436                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6437                                     IXGBE_ETQS_RX_QUEUE);
6438                 etqs |= IXGBE_ETQS_QUEUE_EN;
6439
6440                 ethertype_filter.ethertype = filter->ether_type;
6441                 ethertype_filter.etqf = etqf;
6442                 ethertype_filter.etqs = etqs;
6443                 ethertype_filter.conf = FALSE;
6444                 ret = ixgbe_ethertype_filter_insert(filter_info,
6445                                                     &ethertype_filter);
6446                 if (ret < 0) {
6447                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6448                         return -ENOSPC;
6449                 }
6450         } else {
6451                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6452                 if (ret < 0)
6453                         return -ENOSYS;
6454         }
6455         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6456         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6457         IXGBE_WRITE_FLUSH(hw);
6458
6459         return 0;
6460 }
6461
6462 static int
6463 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6464                         struct rte_eth_ethertype_filter *filter)
6465 {
6466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6467         struct ixgbe_filter_info *filter_info =
6468                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6469         uint32_t etqf, etqs;
6470         int ret;
6471
6472         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6473         if (ret < 0) {
6474                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6475                             filter->ether_type);
6476                 return -ENOENT;
6477         }
6478
6479         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6480         if (etqf & IXGBE_ETQF_FILTER_EN) {
6481                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6482                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6483                 filter->flags = 0;
6484                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6485                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6486                 return 0;
6487         }
6488         return -ENOENT;
6489 }
6490
6491 /*
6492  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6493  * @dev: pointer to rte_eth_dev structure
6494  * @filter_op:operation will be taken.
6495  * @arg: a pointer to specific structure corresponding to the filter_op
6496  */
6497 static int
6498 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6499                                 enum rte_filter_op filter_op,
6500                                 void *arg)
6501 {
6502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6503         int ret;
6504
6505         MAC_TYPE_FILTER_SUP(hw->mac.type);
6506
6507         if (filter_op == RTE_ETH_FILTER_NOP)
6508                 return 0;
6509
6510         if (arg == NULL) {
6511                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6512                             filter_op);
6513                 return -EINVAL;
6514         }
6515
6516         switch (filter_op) {
6517         case RTE_ETH_FILTER_ADD:
6518                 ret = ixgbe_add_del_ethertype_filter(dev,
6519                         (struct rte_eth_ethertype_filter *)arg,
6520                         TRUE);
6521                 break;
6522         case RTE_ETH_FILTER_DELETE:
6523                 ret = ixgbe_add_del_ethertype_filter(dev,
6524                         (struct rte_eth_ethertype_filter *)arg,
6525                         FALSE);
6526                 break;
6527         case RTE_ETH_FILTER_GET:
6528                 ret = ixgbe_get_ethertype_filter(dev,
6529                         (struct rte_eth_ethertype_filter *)arg);
6530                 break;
6531         default:
6532                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6533                 ret = -EINVAL;
6534                 break;
6535         }
6536         return ret;
6537 }
6538
6539 static int
6540 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6541                      enum rte_filter_type filter_type,
6542                      enum rte_filter_op filter_op,
6543                      void *arg)
6544 {
6545         int ret = 0;
6546
6547         switch (filter_type) {
6548         case RTE_ETH_FILTER_NTUPLE:
6549                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6550                 break;
6551         case RTE_ETH_FILTER_ETHERTYPE:
6552                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6553                 break;
6554         case RTE_ETH_FILTER_SYN:
6555                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6556                 break;
6557         case RTE_ETH_FILTER_FDIR:
6558                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6559                 break;
6560         case RTE_ETH_FILTER_L2_TUNNEL:
6561                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6562                 break;
6563         case RTE_ETH_FILTER_GENERIC:
6564                 if (filter_op != RTE_ETH_FILTER_GET)
6565                         return -EINVAL;
6566                 *(const void **)arg = &ixgbe_flow_ops;
6567                 break;
6568         default:
6569                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6570                                                         filter_type);
6571                 ret = -EINVAL;
6572                 break;
6573         }
6574
6575         return ret;
6576 }
6577
6578 static u8 *
6579 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6580                         u8 **mc_addr_ptr, u32 *vmdq)
6581 {
6582         u8 *mc_addr;
6583
6584         *vmdq = 0;
6585         mc_addr = *mc_addr_ptr;
6586         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6587         return mc_addr;
6588 }
6589
6590 static int
6591 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6592                           struct ether_addr *mc_addr_set,
6593                           uint32_t nb_mc_addr)
6594 {
6595         struct ixgbe_hw *hw;
6596         u8 *mc_addr_list;
6597
6598         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6599         mc_addr_list = (u8 *)mc_addr_set;
6600         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6601                                          ixgbe_dev_addr_list_itr, TRUE);
6602 }
6603
6604 static uint64_t
6605 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6606 {
6607         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6608         uint64_t systime_cycles;
6609
6610         switch (hw->mac.type) {
6611         case ixgbe_mac_X550:
6612         case ixgbe_mac_X550EM_x:
6613         case ixgbe_mac_X550EM_a:
6614                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6615                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6616                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6617                                 * NSEC_PER_SEC;
6618                 break;
6619         default:
6620                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6621                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6622                                 << 32;
6623         }
6624
6625         return systime_cycles;
6626 }
6627
6628 static uint64_t
6629 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6630 {
6631         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6632         uint64_t rx_tstamp_cycles;
6633
6634         switch (hw->mac.type) {
6635         case ixgbe_mac_X550:
6636         case ixgbe_mac_X550EM_x:
6637         case ixgbe_mac_X550EM_a:
6638                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6639                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6640                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6641                                 * NSEC_PER_SEC;
6642                 break;
6643         default:
6644                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6645                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6646                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6647                                 << 32;
6648         }
6649
6650         return rx_tstamp_cycles;
6651 }
6652
6653 static uint64_t
6654 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6655 {
6656         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6657         uint64_t tx_tstamp_cycles;
6658
6659         switch (hw->mac.type) {
6660         case ixgbe_mac_X550:
6661         case ixgbe_mac_X550EM_x:
6662         case ixgbe_mac_X550EM_a:
6663                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6664                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6665                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6666                                 * NSEC_PER_SEC;
6667                 break;
6668         default:
6669                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6670                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6671                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6672                                 << 32;
6673         }
6674
6675         return tx_tstamp_cycles;
6676 }
6677
6678 static void
6679 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6680 {
6681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6682         struct ixgbe_adapter *adapter =
6683                 (struct ixgbe_adapter *)dev->data->dev_private;
6684         struct rte_eth_link link;
6685         uint32_t incval = 0;
6686         uint32_t shift = 0;
6687
6688         /* Get current link speed. */
6689         memset(&link, 0, sizeof(link));
6690         ixgbe_dev_link_update(dev, 1);
6691         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6692
6693         switch (link.link_speed) {
6694         case ETH_SPEED_NUM_100M:
6695                 incval = IXGBE_INCVAL_100;
6696                 shift = IXGBE_INCVAL_SHIFT_100;
6697                 break;
6698         case ETH_SPEED_NUM_1G:
6699                 incval = IXGBE_INCVAL_1GB;
6700                 shift = IXGBE_INCVAL_SHIFT_1GB;
6701                 break;
6702         case ETH_SPEED_NUM_10G:
6703         default:
6704                 incval = IXGBE_INCVAL_10GB;
6705                 shift = IXGBE_INCVAL_SHIFT_10GB;
6706                 break;
6707         }
6708
6709         switch (hw->mac.type) {
6710         case ixgbe_mac_X550:
6711         case ixgbe_mac_X550EM_x:
6712         case ixgbe_mac_X550EM_a:
6713                 /* Independent of link speed. */
6714                 incval = 1;
6715                 /* Cycles read will be interpreted as ns. */
6716                 shift = 0;
6717                 /* Fall-through */
6718         case ixgbe_mac_X540:
6719                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6720                 break;
6721         case ixgbe_mac_82599EB:
6722                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6723                 shift -= IXGBE_INCVAL_SHIFT_82599;
6724                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6725                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6726                 break;
6727         default:
6728                 /* Not supported. */
6729                 return;
6730         }
6731
6732         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6733         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6734         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6735
6736         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6737         adapter->systime_tc.cc_shift = shift;
6738         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6739
6740         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6741         adapter->rx_tstamp_tc.cc_shift = shift;
6742         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6743
6744         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6745         adapter->tx_tstamp_tc.cc_shift = shift;
6746         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6747 }
6748
6749 static int
6750 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6751 {
6752         struct ixgbe_adapter *adapter =
6753                         (struct ixgbe_adapter *)dev->data->dev_private;
6754
6755         adapter->systime_tc.nsec += delta;
6756         adapter->rx_tstamp_tc.nsec += delta;
6757         adapter->tx_tstamp_tc.nsec += delta;
6758
6759         return 0;
6760 }
6761
6762 static int
6763 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6764 {
6765         uint64_t ns;
6766         struct ixgbe_adapter *adapter =
6767                         (struct ixgbe_adapter *)dev->data->dev_private;
6768
6769         ns = rte_timespec_to_ns(ts);
6770         /* Set the timecounters to a new value. */
6771         adapter->systime_tc.nsec = ns;
6772         adapter->rx_tstamp_tc.nsec = ns;
6773         adapter->tx_tstamp_tc.nsec = ns;
6774
6775         return 0;
6776 }
6777
6778 static int
6779 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6780 {
6781         uint64_t ns, systime_cycles;
6782         struct ixgbe_adapter *adapter =
6783                         (struct ixgbe_adapter *)dev->data->dev_private;
6784
6785         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6786         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6787         *ts = rte_ns_to_timespec(ns);
6788
6789         return 0;
6790 }
6791
6792 static int
6793 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6794 {
6795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6796         uint32_t tsync_ctl;
6797         uint32_t tsauxc;
6798
6799         /* Stop the timesync system time. */
6800         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6801         /* Reset the timesync system time value. */
6802         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6803         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6804
6805         /* Enable system time for platforms where it isn't on by default. */
6806         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6807         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6808         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6809
6810         ixgbe_start_timecounters(dev);
6811
6812         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6813         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6814                         (ETHER_TYPE_1588 |
6815                          IXGBE_ETQF_FILTER_EN |
6816                          IXGBE_ETQF_1588));
6817
6818         /* Enable timestamping of received PTP packets. */
6819         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6820         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6821         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6822
6823         /* Enable timestamping of transmitted PTP packets. */
6824         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6825         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6826         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6827
6828         IXGBE_WRITE_FLUSH(hw);
6829
6830         return 0;
6831 }
6832
6833 static int
6834 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6835 {
6836         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6837         uint32_t tsync_ctl;
6838
6839         /* Disable timestamping of transmitted PTP packets. */
6840         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6841         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6842         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6843
6844         /* Disable timestamping of received PTP packets. */
6845         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6846         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6847         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6848
6849         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6850         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6851
6852         /* Stop incrementating the System Time registers. */
6853         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6854
6855         return 0;
6856 }
6857
6858 static int
6859 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6860                                  struct timespec *timestamp,
6861                                  uint32_t flags __rte_unused)
6862 {
6863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6864         struct ixgbe_adapter *adapter =
6865                 (struct ixgbe_adapter *)dev->data->dev_private;
6866         uint32_t tsync_rxctl;
6867         uint64_t rx_tstamp_cycles;
6868         uint64_t ns;
6869
6870         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6871         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6872                 return -EINVAL;
6873
6874         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6875         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6876         *timestamp = rte_ns_to_timespec(ns);
6877
6878         return  0;
6879 }
6880
6881 static int
6882 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6883                                  struct timespec *timestamp)
6884 {
6885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6886         struct ixgbe_adapter *adapter =
6887                 (struct ixgbe_adapter *)dev->data->dev_private;
6888         uint32_t tsync_txctl;
6889         uint64_t tx_tstamp_cycles;
6890         uint64_t ns;
6891
6892         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6893         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6894                 return -EINVAL;
6895
6896         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6897         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6898         *timestamp = rte_ns_to_timespec(ns);
6899
6900         return 0;
6901 }
6902
6903 static int
6904 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6905 {
6906         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6907         int count = 0;
6908         int g_ind = 0;
6909         const struct reg_info *reg_group;
6910         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6911                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6912
6913         while ((reg_group = reg_set[g_ind++]))
6914                 count += ixgbe_regs_group_count(reg_group);
6915
6916         return count;
6917 }
6918
6919 static int
6920 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6921 {
6922         int count = 0;
6923         int g_ind = 0;
6924         const struct reg_info *reg_group;
6925
6926         while ((reg_group = ixgbevf_regs[g_ind++]))
6927                 count += ixgbe_regs_group_count(reg_group);
6928
6929         return count;
6930 }
6931
6932 static int
6933 ixgbe_get_regs(struct rte_eth_dev *dev,
6934               struct rte_dev_reg_info *regs)
6935 {
6936         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6937         uint32_t *data = regs->data;
6938         int g_ind = 0;
6939         int count = 0;
6940         const struct reg_info *reg_group;
6941         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6942                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6943
6944         if (data == NULL) {
6945                 regs->length = ixgbe_get_reg_length(dev);
6946                 regs->width = sizeof(uint32_t);
6947                 return 0;
6948         }
6949
6950         /* Support only full register dump */
6951         if ((regs->length == 0) ||
6952             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6953                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6954                         hw->device_id;
6955                 while ((reg_group = reg_set[g_ind++]))
6956                         count += ixgbe_read_regs_group(dev, &data[count],
6957                                 reg_group);
6958                 return 0;
6959         }
6960
6961         return -ENOTSUP;
6962 }
6963
6964 static int
6965 ixgbevf_get_regs(struct rte_eth_dev *dev,
6966                 struct rte_dev_reg_info *regs)
6967 {
6968         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6969         uint32_t *data = regs->data;
6970         int g_ind = 0;
6971         int count = 0;
6972         const struct reg_info *reg_group;
6973
6974         if (data == NULL) {
6975                 regs->length = ixgbevf_get_reg_length(dev);
6976                 regs->width = sizeof(uint32_t);
6977                 return 0;
6978         }
6979
6980         /* Support only full register dump */
6981         if ((regs->length == 0) ||
6982             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6983                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6984                         hw->device_id;
6985                 while ((reg_group = ixgbevf_regs[g_ind++]))
6986                         count += ixgbe_read_regs_group(dev, &data[count],
6987                                                       reg_group);
6988                 return 0;
6989         }
6990
6991         return -ENOTSUP;
6992 }
6993
6994 static int
6995 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6996 {
6997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6998
6999         /* Return unit is byte count */
7000         return hw->eeprom.word_size * 2;
7001 }
7002
7003 static int
7004 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7005                 struct rte_dev_eeprom_info *in_eeprom)
7006 {
7007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7008         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7009         uint16_t *data = in_eeprom->data;
7010         int first, length;
7011
7012         first = in_eeprom->offset >> 1;
7013         length = in_eeprom->length >> 1;
7014         if ((first > hw->eeprom.word_size) ||
7015             ((first + length) > hw->eeprom.word_size))
7016                 return -EINVAL;
7017
7018         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7019
7020         return eeprom->ops.read_buffer(hw, first, length, data);
7021 }
7022
7023 static int
7024 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7025                 struct rte_dev_eeprom_info *in_eeprom)
7026 {
7027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7028         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7029         uint16_t *data = in_eeprom->data;
7030         int first, length;
7031
7032         first = in_eeprom->offset >> 1;
7033         length = in_eeprom->length >> 1;
7034         if ((first > hw->eeprom.word_size) ||
7035             ((first + length) > hw->eeprom.word_size))
7036                 return -EINVAL;
7037
7038         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7039
7040         return eeprom->ops.write_buffer(hw,  first, length, data);
7041 }
7042
7043 uint16_t
7044 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7045         switch (mac_type) {
7046         case ixgbe_mac_X550:
7047         case ixgbe_mac_X550EM_x:
7048         case ixgbe_mac_X550EM_a:
7049                 return ETH_RSS_RETA_SIZE_512;
7050         case ixgbe_mac_X550_vf:
7051         case ixgbe_mac_X550EM_x_vf:
7052         case ixgbe_mac_X550EM_a_vf:
7053                 return ETH_RSS_RETA_SIZE_64;
7054         default:
7055                 return ETH_RSS_RETA_SIZE_128;
7056         }
7057 }
7058
7059 uint32_t
7060 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7061         switch (mac_type) {
7062         case ixgbe_mac_X550:
7063         case ixgbe_mac_X550EM_x:
7064         case ixgbe_mac_X550EM_a:
7065                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7066                         return IXGBE_RETA(reta_idx >> 2);
7067                 else
7068                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7069         case ixgbe_mac_X550_vf:
7070         case ixgbe_mac_X550EM_x_vf:
7071         case ixgbe_mac_X550EM_a_vf:
7072                 return IXGBE_VFRETA(reta_idx >> 2);
7073         default:
7074                 return IXGBE_RETA(reta_idx >> 2);
7075         }
7076 }
7077
7078 uint32_t
7079 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7080         switch (mac_type) {
7081         case ixgbe_mac_X550_vf:
7082         case ixgbe_mac_X550EM_x_vf:
7083         case ixgbe_mac_X550EM_a_vf:
7084                 return IXGBE_VFMRQC;
7085         default:
7086                 return IXGBE_MRQC;
7087         }
7088 }
7089
7090 uint32_t
7091 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7092         switch (mac_type) {
7093         case ixgbe_mac_X550_vf:
7094         case ixgbe_mac_X550EM_x_vf:
7095         case ixgbe_mac_X550EM_a_vf:
7096                 return IXGBE_VFRSSRK(i);
7097         default:
7098                 return IXGBE_RSSRK(i);
7099         }
7100 }
7101
7102 bool
7103 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7104         switch (mac_type) {
7105         case ixgbe_mac_82599_vf:
7106         case ixgbe_mac_X540_vf:
7107                 return 0;
7108         default:
7109                 return 1;
7110         }
7111 }
7112
7113 static int
7114 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7115                         struct rte_eth_dcb_info *dcb_info)
7116 {
7117         struct ixgbe_dcb_config *dcb_config =
7118                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7119         struct ixgbe_dcb_tc_config *tc;
7120         uint8_t i, j;
7121
7122         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7123                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7124         else
7125                 dcb_info->nb_tcs = 1;
7126
7127         if (dcb_config->vt_mode) { /* vt is enabled*/
7128                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7129                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7130                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7131                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7132                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7133                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7134                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7135                                                 i * dcb_info->nb_tcs + j;
7136                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7137                                 dcb_info->tc_queue.tc_txq[i][j].base =
7138                                                 i * dcb_info->nb_tcs + j;
7139                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7140                         }
7141                 }
7142         } else { /* vt is disabled*/
7143                 struct rte_eth_dcb_rx_conf *rx_conf =
7144                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7145                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7146                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7147                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7148                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7149                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7150                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7151                         }
7152                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7153                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7154                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7155                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7156                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7157                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7158                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7159                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7160                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7161                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7162                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7163                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7164                         }
7165                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7166                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7167                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7168                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7169                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7170                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7171                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7172                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7173                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7174                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7175                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7176                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7177                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7178                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7179                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7180                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7181                 }
7182         }
7183         for (i = 0; i < dcb_info->nb_tcs; i++) {
7184                 tc = &dcb_config->tc_config[i];
7185                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7186         }
7187         return 0;
7188 }
7189
7190 /* Update e-tag ether type */
7191 static int
7192 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7193                             uint16_t ether_type)
7194 {
7195         uint32_t etag_etype;
7196
7197         if (hw->mac.type != ixgbe_mac_X550 &&
7198             hw->mac.type != ixgbe_mac_X550EM_x &&
7199             hw->mac.type != ixgbe_mac_X550EM_a) {
7200                 return -ENOTSUP;
7201         }
7202
7203         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7204         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7205         etag_etype |= ether_type;
7206         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7207         IXGBE_WRITE_FLUSH(hw);
7208
7209         return 0;
7210 }
7211
7212 /* Config l2 tunnel ether type */
7213 static int
7214 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7215                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7216 {
7217         int ret = 0;
7218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7219         struct ixgbe_l2_tn_info *l2_tn_info =
7220                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7221
7222         if (l2_tunnel == NULL)
7223                 return -EINVAL;
7224
7225         switch (l2_tunnel->l2_tunnel_type) {
7226         case RTE_L2_TUNNEL_TYPE_E_TAG:
7227                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7228                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7229                 break;
7230         default:
7231                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7232                 ret = -EINVAL;
7233                 break;
7234         }
7235
7236         return ret;
7237 }
7238
7239 /* Enable e-tag tunnel */
7240 static int
7241 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7242 {
7243         uint32_t etag_etype;
7244
7245         if (hw->mac.type != ixgbe_mac_X550 &&
7246             hw->mac.type != ixgbe_mac_X550EM_x &&
7247             hw->mac.type != ixgbe_mac_X550EM_a) {
7248                 return -ENOTSUP;
7249         }
7250
7251         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7252         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7253         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7254         IXGBE_WRITE_FLUSH(hw);
7255
7256         return 0;
7257 }
7258
7259 /* Enable l2 tunnel */
7260 static int
7261 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7262                            enum rte_eth_tunnel_type l2_tunnel_type)
7263 {
7264         int ret = 0;
7265         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7266         struct ixgbe_l2_tn_info *l2_tn_info =
7267                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7268
7269         switch (l2_tunnel_type) {
7270         case RTE_L2_TUNNEL_TYPE_E_TAG:
7271                 l2_tn_info->e_tag_en = TRUE;
7272                 ret = ixgbe_e_tag_enable(hw);
7273                 break;
7274         default:
7275                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7276                 ret = -EINVAL;
7277                 break;
7278         }
7279
7280         return ret;
7281 }
7282
7283 /* Disable e-tag tunnel */
7284 static int
7285 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7286 {
7287         uint32_t etag_etype;
7288
7289         if (hw->mac.type != ixgbe_mac_X550 &&
7290             hw->mac.type != ixgbe_mac_X550EM_x &&
7291             hw->mac.type != ixgbe_mac_X550EM_a) {
7292                 return -ENOTSUP;
7293         }
7294
7295         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7296         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7297         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7298         IXGBE_WRITE_FLUSH(hw);
7299
7300         return 0;
7301 }
7302
7303 /* Disable l2 tunnel */
7304 static int
7305 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7306                             enum rte_eth_tunnel_type l2_tunnel_type)
7307 {
7308         int ret = 0;
7309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7310         struct ixgbe_l2_tn_info *l2_tn_info =
7311                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7312
7313         switch (l2_tunnel_type) {
7314         case RTE_L2_TUNNEL_TYPE_E_TAG:
7315                 l2_tn_info->e_tag_en = FALSE;
7316                 ret = ixgbe_e_tag_disable(hw);
7317                 break;
7318         default:
7319                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7320                 ret = -EINVAL;
7321                 break;
7322         }
7323
7324         return ret;
7325 }
7326
7327 static int
7328 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7329                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7330 {
7331         int ret = 0;
7332         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7333         uint32_t i, rar_entries;
7334         uint32_t rar_low, rar_high;
7335
7336         if (hw->mac.type != ixgbe_mac_X550 &&
7337             hw->mac.type != ixgbe_mac_X550EM_x &&
7338             hw->mac.type != ixgbe_mac_X550EM_a) {
7339                 return -ENOTSUP;
7340         }
7341
7342         rar_entries = ixgbe_get_num_rx_addrs(hw);
7343
7344         for (i = 1; i < rar_entries; i++) {
7345                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7346                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7347                 if ((rar_high & IXGBE_RAH_AV) &&
7348                     (rar_high & IXGBE_RAH_ADTYPE) &&
7349                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7350                      l2_tunnel->tunnel_id)) {
7351                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7352                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7353
7354                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7355
7356                         return ret;
7357                 }
7358         }
7359
7360         return ret;
7361 }
7362
7363 static int
7364 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7365                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7366 {
7367         int ret = 0;
7368         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7369         uint32_t i, rar_entries;
7370         uint32_t rar_low, rar_high;
7371
7372         if (hw->mac.type != ixgbe_mac_X550 &&
7373             hw->mac.type != ixgbe_mac_X550EM_x &&
7374             hw->mac.type != ixgbe_mac_X550EM_a) {
7375                 return -ENOTSUP;
7376         }
7377
7378         /* One entry for one tunnel. Try to remove potential existing entry. */
7379         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7380
7381         rar_entries = ixgbe_get_num_rx_addrs(hw);
7382
7383         for (i = 1; i < rar_entries; i++) {
7384                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7385                 if (rar_high & IXGBE_RAH_AV) {
7386                         continue;
7387                 } else {
7388                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7389                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7390                         rar_low = l2_tunnel->tunnel_id;
7391
7392                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7393                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7394
7395                         return ret;
7396                 }
7397         }
7398
7399         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7400                      " Please remove a rule before adding a new one.");
7401         return -EINVAL;
7402 }
7403
7404 static inline struct ixgbe_l2_tn_filter *
7405 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7406                           struct ixgbe_l2_tn_key *key)
7407 {
7408         int ret;
7409
7410         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7411         if (ret < 0)
7412                 return NULL;
7413
7414         return l2_tn_info->hash_map[ret];
7415 }
7416
7417 static inline int
7418 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7419                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7420 {
7421         int ret;
7422
7423         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7424                                &l2_tn_filter->key);
7425
7426         if (ret < 0) {
7427                 PMD_DRV_LOG(ERR,
7428                             "Failed to insert L2 tunnel filter"
7429                             " to hash table %d!",
7430                             ret);
7431                 return ret;
7432         }
7433
7434         l2_tn_info->hash_map[ret] = l2_tn_filter;
7435
7436         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7437
7438         return 0;
7439 }
7440
7441 static inline int
7442 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7443                           struct ixgbe_l2_tn_key *key)
7444 {
7445         int ret;
7446         struct ixgbe_l2_tn_filter *l2_tn_filter;
7447
7448         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7449
7450         if (ret < 0) {
7451                 PMD_DRV_LOG(ERR,
7452                             "No such L2 tunnel filter to delete %d!",
7453                             ret);
7454                 return ret;
7455         }
7456
7457         l2_tn_filter = l2_tn_info->hash_map[ret];
7458         l2_tn_info->hash_map[ret] = NULL;
7459
7460         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7461         rte_free(l2_tn_filter);
7462
7463         return 0;
7464 }
7465
7466 /* Add l2 tunnel filter */
7467 int
7468 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7469                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7470                                bool restore)
7471 {
7472         int ret;
7473         struct ixgbe_l2_tn_info *l2_tn_info =
7474                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7475         struct ixgbe_l2_tn_key key;
7476         struct ixgbe_l2_tn_filter *node;
7477
7478         if (!restore) {
7479                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7480                 key.tn_id = l2_tunnel->tunnel_id;
7481
7482                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7483
7484                 if (node) {
7485                         PMD_DRV_LOG(ERR,
7486                                     "The L2 tunnel filter already exists!");
7487                         return -EINVAL;
7488                 }
7489
7490                 node = rte_zmalloc("ixgbe_l2_tn",
7491                                    sizeof(struct ixgbe_l2_tn_filter),
7492                                    0);
7493                 if (!node)
7494                         return -ENOMEM;
7495
7496                 (void)rte_memcpy(&node->key,
7497                                  &key,
7498                                  sizeof(struct ixgbe_l2_tn_key));
7499                 node->pool = l2_tunnel->pool;
7500                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7501                 if (ret < 0) {
7502                         rte_free(node);
7503                         return ret;
7504                 }
7505         }
7506
7507         switch (l2_tunnel->l2_tunnel_type) {
7508         case RTE_L2_TUNNEL_TYPE_E_TAG:
7509                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7510                 break;
7511         default:
7512                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7513                 ret = -EINVAL;
7514                 break;
7515         }
7516
7517         if ((!restore) && (ret < 0))
7518                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7519
7520         return ret;
7521 }
7522
7523 /* Delete l2 tunnel filter */
7524 int
7525 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7526                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7527 {
7528         int ret;
7529         struct ixgbe_l2_tn_info *l2_tn_info =
7530                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7531         struct ixgbe_l2_tn_key key;
7532
7533         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7534         key.tn_id = l2_tunnel->tunnel_id;
7535         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7536         if (ret < 0)
7537                 return ret;
7538
7539         switch (l2_tunnel->l2_tunnel_type) {
7540         case RTE_L2_TUNNEL_TYPE_E_TAG:
7541                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7542                 break;
7543         default:
7544                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7545                 ret = -EINVAL;
7546                 break;
7547         }
7548
7549         return ret;
7550 }
7551
7552 /**
7553  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7554  * @dev: pointer to rte_eth_dev structure
7555  * @filter_op:operation will be taken.
7556  * @arg: a pointer to specific structure corresponding to the filter_op
7557  */
7558 static int
7559 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7560                                   enum rte_filter_op filter_op,
7561                                   void *arg)
7562 {
7563         int ret;
7564
7565         if (filter_op == RTE_ETH_FILTER_NOP)
7566                 return 0;
7567
7568         if (arg == NULL) {
7569                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7570                             filter_op);
7571                 return -EINVAL;
7572         }
7573
7574         switch (filter_op) {
7575         case RTE_ETH_FILTER_ADD:
7576                 ret = ixgbe_dev_l2_tunnel_filter_add
7577                         (dev,
7578                          (struct rte_eth_l2_tunnel_conf *)arg,
7579                          FALSE);
7580                 break;
7581         case RTE_ETH_FILTER_DELETE:
7582                 ret = ixgbe_dev_l2_tunnel_filter_del
7583                         (dev,
7584                          (struct rte_eth_l2_tunnel_conf *)arg);
7585                 break;
7586         default:
7587                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7588                 ret = -EINVAL;
7589                 break;
7590         }
7591         return ret;
7592 }
7593
7594 static int
7595 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7596 {
7597         int ret = 0;
7598         uint32_t ctrl;
7599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7600
7601         if (hw->mac.type != ixgbe_mac_X550 &&
7602             hw->mac.type != ixgbe_mac_X550EM_x &&
7603             hw->mac.type != ixgbe_mac_X550EM_a) {
7604                 return -ENOTSUP;
7605         }
7606
7607         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7608         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7609         if (en)
7610                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7611         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7612
7613         return ret;
7614 }
7615
7616 /* Enable l2 tunnel forwarding */
7617 static int
7618 ixgbe_dev_l2_tunnel_forwarding_enable
7619         (struct rte_eth_dev *dev,
7620          enum rte_eth_tunnel_type l2_tunnel_type)
7621 {
7622         struct ixgbe_l2_tn_info *l2_tn_info =
7623                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7624         int ret = 0;
7625
7626         switch (l2_tunnel_type) {
7627         case RTE_L2_TUNNEL_TYPE_E_TAG:
7628                 l2_tn_info->e_tag_fwd_en = TRUE;
7629                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7630                 break;
7631         default:
7632                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7633                 ret = -EINVAL;
7634                 break;
7635         }
7636
7637         return ret;
7638 }
7639
7640 /* Disable l2 tunnel forwarding */
7641 static int
7642 ixgbe_dev_l2_tunnel_forwarding_disable
7643         (struct rte_eth_dev *dev,
7644          enum rte_eth_tunnel_type l2_tunnel_type)
7645 {
7646         struct ixgbe_l2_tn_info *l2_tn_info =
7647                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7648         int ret = 0;
7649
7650         switch (l2_tunnel_type) {
7651         case RTE_L2_TUNNEL_TYPE_E_TAG:
7652                 l2_tn_info->e_tag_fwd_en = FALSE;
7653                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7654                 break;
7655         default:
7656                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7657                 ret = -EINVAL;
7658                 break;
7659         }
7660
7661         return ret;
7662 }
7663
7664 static int
7665 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7666                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7667                              bool en)
7668 {
7669         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7670         int ret = 0;
7671         uint32_t vmtir, vmvir;
7672         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7673
7674         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7675                 PMD_DRV_LOG(ERR,
7676                             "VF id %u should be less than %u",
7677                             l2_tunnel->vf_id,
7678                             pci_dev->max_vfs);
7679                 return -EINVAL;
7680         }
7681
7682         if (hw->mac.type != ixgbe_mac_X550 &&
7683             hw->mac.type != ixgbe_mac_X550EM_x &&
7684             hw->mac.type != ixgbe_mac_X550EM_a) {
7685                 return -ENOTSUP;
7686         }
7687
7688         if (en)
7689                 vmtir = l2_tunnel->tunnel_id;
7690         else
7691                 vmtir = 0;
7692
7693         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7694
7695         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7696         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7697         if (en)
7698                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7699         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7700
7701         return ret;
7702 }
7703
7704 /* Enable l2 tunnel tag insertion */
7705 static int
7706 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7707                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7708 {
7709         int ret = 0;
7710
7711         switch (l2_tunnel->l2_tunnel_type) {
7712         case RTE_L2_TUNNEL_TYPE_E_TAG:
7713                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7714                 break;
7715         default:
7716                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7717                 ret = -EINVAL;
7718                 break;
7719         }
7720
7721         return ret;
7722 }
7723
7724 /* Disable l2 tunnel tag insertion */
7725 static int
7726 ixgbe_dev_l2_tunnel_insertion_disable
7727         (struct rte_eth_dev *dev,
7728          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7729 {
7730         int ret = 0;
7731
7732         switch (l2_tunnel->l2_tunnel_type) {
7733         case RTE_L2_TUNNEL_TYPE_E_TAG:
7734                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7735                 break;
7736         default:
7737                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7738                 ret = -EINVAL;
7739                 break;
7740         }
7741
7742         return ret;
7743 }
7744
7745 static int
7746 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7747                              bool en)
7748 {
7749         int ret = 0;
7750         uint32_t qde;
7751         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7752
7753         if (hw->mac.type != ixgbe_mac_X550 &&
7754             hw->mac.type != ixgbe_mac_X550EM_x &&
7755             hw->mac.type != ixgbe_mac_X550EM_a) {
7756                 return -ENOTSUP;
7757         }
7758
7759         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7760         if (en)
7761                 qde |= IXGBE_QDE_STRIP_TAG;
7762         else
7763                 qde &= ~IXGBE_QDE_STRIP_TAG;
7764         qde &= ~IXGBE_QDE_READ;
7765         qde |= IXGBE_QDE_WRITE;
7766         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7767
7768         return ret;
7769 }
7770
7771 /* Enable l2 tunnel tag stripping */
7772 static int
7773 ixgbe_dev_l2_tunnel_stripping_enable
7774         (struct rte_eth_dev *dev,
7775          enum rte_eth_tunnel_type l2_tunnel_type)
7776 {
7777         int ret = 0;
7778
7779         switch (l2_tunnel_type) {
7780         case RTE_L2_TUNNEL_TYPE_E_TAG:
7781                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7782                 break;
7783         default:
7784                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7785                 ret = -EINVAL;
7786                 break;
7787         }
7788
7789         return ret;
7790 }
7791
7792 /* Disable l2 tunnel tag stripping */
7793 static int
7794 ixgbe_dev_l2_tunnel_stripping_disable
7795         (struct rte_eth_dev *dev,
7796          enum rte_eth_tunnel_type l2_tunnel_type)
7797 {
7798         int ret = 0;
7799
7800         switch (l2_tunnel_type) {
7801         case RTE_L2_TUNNEL_TYPE_E_TAG:
7802                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7803                 break;
7804         default:
7805                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7806                 ret = -EINVAL;
7807                 break;
7808         }
7809
7810         return ret;
7811 }
7812
7813 /* Enable/disable l2 tunnel offload functions */
7814 static int
7815 ixgbe_dev_l2_tunnel_offload_set
7816         (struct rte_eth_dev *dev,
7817          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7818          uint32_t mask,
7819          uint8_t en)
7820 {
7821         int ret = 0;
7822
7823         if (l2_tunnel == NULL)
7824                 return -EINVAL;
7825
7826         ret = -EINVAL;
7827         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7828                 if (en)
7829                         ret = ixgbe_dev_l2_tunnel_enable(
7830                                 dev,
7831                                 l2_tunnel->l2_tunnel_type);
7832                 else
7833                         ret = ixgbe_dev_l2_tunnel_disable(
7834                                 dev,
7835                                 l2_tunnel->l2_tunnel_type);
7836         }
7837
7838         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7839                 if (en)
7840                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7841                                 dev,
7842                                 l2_tunnel);
7843                 else
7844                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7845                                 dev,
7846                                 l2_tunnel);
7847         }
7848
7849         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7850                 if (en)
7851                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7852                                 dev,
7853                                 l2_tunnel->l2_tunnel_type);
7854                 else
7855                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7856                                 dev,
7857                                 l2_tunnel->l2_tunnel_type);
7858         }
7859
7860         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7861                 if (en)
7862                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7863                                 dev,
7864                                 l2_tunnel->l2_tunnel_type);
7865                 else
7866                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7867                                 dev,
7868                                 l2_tunnel->l2_tunnel_type);
7869         }
7870
7871         return ret;
7872 }
7873
7874 static int
7875 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7876                         uint16_t port)
7877 {
7878         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7879         IXGBE_WRITE_FLUSH(hw);
7880
7881         return 0;
7882 }
7883
7884 /* There's only one register for VxLAN UDP port.
7885  * So, we cannot add several ports. Will update it.
7886  */
7887 static int
7888 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7889                      uint16_t port)
7890 {
7891         if (port == 0) {
7892                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7893                 return -EINVAL;
7894         }
7895
7896         return ixgbe_update_vxlan_port(hw, port);
7897 }
7898
7899 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7900  * UDP port, it must have a value.
7901  * So, will reset it to the original value 0.
7902  */
7903 static int
7904 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7905                      uint16_t port)
7906 {
7907         uint16_t cur_port;
7908
7909         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7910
7911         if (cur_port != port) {
7912                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7913                 return -EINVAL;
7914         }
7915
7916         return ixgbe_update_vxlan_port(hw, 0);
7917 }
7918
7919 /* Add UDP tunneling port */
7920 static int
7921 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7922                               struct rte_eth_udp_tunnel *udp_tunnel)
7923 {
7924         int ret = 0;
7925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7926
7927         if (hw->mac.type != ixgbe_mac_X550 &&
7928             hw->mac.type != ixgbe_mac_X550EM_x &&
7929             hw->mac.type != ixgbe_mac_X550EM_a) {
7930                 return -ENOTSUP;
7931         }
7932
7933         if (udp_tunnel == NULL)
7934                 return -EINVAL;
7935
7936         switch (udp_tunnel->prot_type) {
7937         case RTE_TUNNEL_TYPE_VXLAN:
7938                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7939                 break;
7940
7941         case RTE_TUNNEL_TYPE_GENEVE:
7942         case RTE_TUNNEL_TYPE_TEREDO:
7943                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7944                 ret = -EINVAL;
7945                 break;
7946
7947         default:
7948                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7949                 ret = -EINVAL;
7950                 break;
7951         }
7952
7953         return ret;
7954 }
7955
7956 /* Remove UDP tunneling port */
7957 static int
7958 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7959                               struct rte_eth_udp_tunnel *udp_tunnel)
7960 {
7961         int ret = 0;
7962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7963
7964         if (hw->mac.type != ixgbe_mac_X550 &&
7965             hw->mac.type != ixgbe_mac_X550EM_x &&
7966             hw->mac.type != ixgbe_mac_X550EM_a) {
7967                 return -ENOTSUP;
7968         }
7969
7970         if (udp_tunnel == NULL)
7971                 return -EINVAL;
7972
7973         switch (udp_tunnel->prot_type) {
7974         case RTE_TUNNEL_TYPE_VXLAN:
7975                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7976                 break;
7977         case RTE_TUNNEL_TYPE_GENEVE:
7978         case RTE_TUNNEL_TYPE_TEREDO:
7979                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7980                 ret = -EINVAL;
7981                 break;
7982         default:
7983                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7984                 ret = -EINVAL;
7985                 break;
7986         }
7987
7988         return ret;
7989 }
7990
7991 static void
7992 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7993 {
7994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7995
7996         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7997 }
7998
7999 static void
8000 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8001 {
8002         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8003
8004         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8005 }
8006
8007 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8008 {
8009         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8010         u32 in_msg = 0;
8011
8012         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8013                 return;
8014
8015         /* PF reset VF event */
8016         if (in_msg == IXGBE_PF_CONTROL_MSG)
8017                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8018                                               NULL, NULL);
8019 }
8020
8021 static int
8022 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8023 {
8024         uint32_t eicr;
8025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8026         struct ixgbe_interrupt *intr =
8027                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8028         ixgbevf_intr_disable(hw);
8029
8030         /* read-on-clear nic registers here */
8031         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8032         intr->flags = 0;
8033
8034         /* only one misc vector supported - mailbox */
8035         eicr &= IXGBE_VTEICR_MASK;
8036         if (eicr == IXGBE_MISC_VEC_ID)
8037                 intr->flags |= IXGBE_FLAG_MAILBOX;
8038
8039         return 0;
8040 }
8041
8042 static int
8043 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8044 {
8045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8046         struct ixgbe_interrupt *intr =
8047                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8048
8049         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8050                 ixgbevf_mbx_process(dev);
8051                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8052         }
8053
8054         ixgbevf_intr_enable(hw);
8055
8056         return 0;
8057 }
8058
8059 static void
8060 ixgbevf_dev_interrupt_handler(void *param)
8061 {
8062         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8063
8064         ixgbevf_dev_interrupt_get_status(dev);
8065         ixgbevf_dev_interrupt_action(dev);
8066 }
8067
8068 /**
8069  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8070  *  @hw: pointer to hardware structure
8071  *
8072  *  Stops the transmit data path and waits for the HW to internally empty
8073  *  the Tx security block
8074  **/
8075 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8076 {
8077 #define IXGBE_MAX_SECTX_POLL 40
8078
8079         int i;
8080         int sectxreg;
8081
8082         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8083         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8084         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8085         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8086                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8087                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8088                         break;
8089                 /* Use interrupt-safe sleep just in case */
8090                 usec_delay(1000);
8091         }
8092
8093         /* For informational purposes only */
8094         if (i >= IXGBE_MAX_SECTX_POLL)
8095                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8096                          "path fully disabled.  Continuing with init.");
8097
8098         return IXGBE_SUCCESS;
8099 }
8100
8101 /**
8102  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8103  *  @hw: pointer to hardware structure
8104  *
8105  *  Enables the transmit data path.
8106  **/
8107 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8108 {
8109         uint32_t sectxreg;
8110
8111         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8112         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8113         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8114         IXGBE_WRITE_FLUSH(hw);
8115
8116         return IXGBE_SUCCESS;
8117 }
8118
8119 /* restore n-tuple filter */
8120 static inline void
8121 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8122 {
8123         struct ixgbe_filter_info *filter_info =
8124                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8125         struct ixgbe_5tuple_filter *node;
8126
8127         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8128                 ixgbe_inject_5tuple_filter(dev, node);
8129         }
8130 }
8131
8132 /* restore ethernet type filter */
8133 static inline void
8134 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8135 {
8136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8137         struct ixgbe_filter_info *filter_info =
8138                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8139         int i;
8140
8141         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8142                 if (filter_info->ethertype_mask & (1 << i)) {
8143                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8144                                         filter_info->ethertype_filters[i].etqf);
8145                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8146                                         filter_info->ethertype_filters[i].etqs);
8147                         IXGBE_WRITE_FLUSH(hw);
8148                 }
8149         }
8150 }
8151
8152 /* restore SYN filter */
8153 static inline void
8154 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8155 {
8156         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8157         struct ixgbe_filter_info *filter_info =
8158                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8159         uint32_t synqf;
8160
8161         synqf = filter_info->syn_info;
8162
8163         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8164                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8165                 IXGBE_WRITE_FLUSH(hw);
8166         }
8167 }
8168
8169 /* restore L2 tunnel filter */
8170 static inline void
8171 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8172 {
8173         struct ixgbe_l2_tn_info *l2_tn_info =
8174                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8175         struct ixgbe_l2_tn_filter *node;
8176         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8177
8178         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8179                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8180                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8181                 l2_tn_conf.pool           = node->pool;
8182                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8183         }
8184 }
8185
8186 static int
8187 ixgbe_filter_restore(struct rte_eth_dev *dev)
8188 {
8189         ixgbe_ntuple_filter_restore(dev);
8190         ixgbe_ethertype_filter_restore(dev);
8191         ixgbe_syn_filter_restore(dev);
8192         ixgbe_fdir_filter_restore(dev);
8193         ixgbe_l2_tn_filter_restore(dev);
8194
8195         return 0;
8196 }
8197
8198 static void
8199 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8200 {
8201         struct ixgbe_l2_tn_info *l2_tn_info =
8202                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8204
8205         if (l2_tn_info->e_tag_en)
8206                 (void)ixgbe_e_tag_enable(hw);
8207
8208         if (l2_tn_info->e_tag_fwd_en)
8209                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8210
8211         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8212 }
8213
8214 /* remove all the n-tuple filters */
8215 void
8216 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8217 {
8218         struct ixgbe_filter_info *filter_info =
8219                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8220         struct ixgbe_5tuple_filter *p_5tuple;
8221
8222         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8223                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8224 }
8225
8226 /* remove all the ether type filters */
8227 void
8228 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8229 {
8230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8231         struct ixgbe_filter_info *filter_info =
8232                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8233         int i;
8234
8235         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8236                 if (filter_info->ethertype_mask & (1 << i) &&
8237                     !filter_info->ethertype_filters[i].conf) {
8238                         (void)ixgbe_ethertype_filter_remove(filter_info,
8239                                                             (uint8_t)i);
8240                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8241                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8242                         IXGBE_WRITE_FLUSH(hw);
8243                 }
8244         }
8245 }
8246
8247 /* remove the SYN filter */
8248 void
8249 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8250 {
8251         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8252         struct ixgbe_filter_info *filter_info =
8253                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8254
8255         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8256                 filter_info->syn_info = 0;
8257
8258                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8259                 IXGBE_WRITE_FLUSH(hw);
8260         }
8261 }
8262
8263 /* remove all the L2 tunnel filters */
8264 int
8265 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8266 {
8267         struct ixgbe_l2_tn_info *l2_tn_info =
8268                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8269         struct ixgbe_l2_tn_filter *l2_tn_filter;
8270         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8271         int ret = 0;
8272
8273         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8274                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8275                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8276                 l2_tn_conf.pool           = l2_tn_filter->pool;
8277                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8278                 if (ret < 0)
8279                         return ret;
8280         }
8281
8282         return 0;
8283 }
8284
8285 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8286 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8287 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8288 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8289 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8290 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");