drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 /*
  77  * High threshold controlling when to start sending XOFF frames. Must be at
  78  * least 8 bytes less than receive packet buffer size. This value is in units
  79  * of 1024 bytes.
  80  */
  81 #define IXGBE_FC_HI    0x80
  82
  83 /*
  84  * Low threshold controlling when to start sending XON frames. This value is
  85  * in units of 1024 bytes.
  86  */
  87 #define IXGBE_FC_LO    0x40
  88
  89 /* Default minimum inter-interrupt interval for EITR configuration */
  90 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  91
  92 /* Timer value included in XOFF frames. */
  93 #define IXGBE_FC_PAUSE 0x680
  94
  95 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  96 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  97 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  98
  99 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 100 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 101 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 102
 103 /*
 104  *  Default values for RX/TX configuration
 105  */
 106 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 107 #define IXGBE_DEFAULT_RX_PTHRESH      8
 108 #define IXGBE_DEFAULT_RX_HTHRESH      8
 109 #define IXGBE_DEFAULT_RX_WTHRESH      0
 110
 111 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 112 #define IXGBE_DEFAULT_TX_PTHRESH      32
 113 #define IXGBE_DEFAULT_TX_HTHRESH      0
 114 #define IXGBE_DEFAULT_TX_WTHRESH      0
 115 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 116
 117 /* Bit shift and mask */
 118 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 119 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 120 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 121 #define IXGBE_8_BIT_MASK   UINT8_MAX
 122
 123 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 124
 125 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 126
 127 #define IXGBE_HKEY_MAX_INDEX 10
 128
 129 /* Additional timesync values. */
 130 #define NSEC_PER_SEC             1000000000L
 131 #define IXGBE_INCVAL_10GB        0x66666666
 132 #define IXGBE_INCVAL_1GB         0x40000000
 133 #define IXGBE_INCVAL_100         0x50000000
 134 #define IXGBE_INCVAL_SHIFT_10GB  28
 135 #define IXGBE_INCVAL_SHIFT_1GB   24
 136 #define IXGBE_INCVAL_SHIFT_100   21
 137 #define IXGBE_INCVAL_SHIFT_82599 7
 138 #define IXGBE_INCPER_SHIFT_82599 24
 139
 140 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 141
 142 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 143 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 144 #define DEFAULT_ETAG_ETYPE                     0x893f
 145 #define IXGBE_ETAG_ETYPE                       0x00005084
 146 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 147 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 148 #define IXGBE_RAH_ADTYPE                       0x40000000
 149 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 150 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 151 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 152 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 153 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 154 #define IXGBE_VTEICR_MASK                      0x07
 155
 156 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 157 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 158
 159 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 160 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 161 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 167 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static int
 186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 187                 uint64_t *values, unsigned int n);
 188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names,
 192         unsigned int size);
 193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 195 static int ixgbe_dev_xstats_get_names_by_id(
 196         struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names,
 198         const uint64_t *ids,
 199         unsigned int limit);
 200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 201                                              uint16_t queue_id,
 202                                              uint8_t stat_idx,
 203                                              uint8_t is_rx);
 204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 205                                  size_t fw_size);
 206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_dev_info *dev_info);
 208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 210                                  struct rte_eth_dev_info *dev_info);
 211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 212
 213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 216                                enum rte_vlan_type vlan_type,
 217                                uint16_t tpid_id);
 218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 219                 uint16_t queue, bool on);
 220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 221                 int on);
 222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 227
 228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 233                                struct rte_eth_fc_conf *fc_conf);
 234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 235                 struct rte_eth_pfc_conf *pfc_conf);
 236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 237                         struct rte_eth_rss_reta_entry64 *reta_conf,
 238                         uint16_t reta_size);
 239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_reta_entry64 *reta_conf,
 241                         uint16_t reta_size);
 242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 248                                       struct rte_intr_handle *handle);
 249 static void ixgbe_dev_interrupt_handler(void *param);
 250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 252                          uint32_t index, uint32_t pool);
 253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 255                                            struct ether_addr *mac_addr);
 256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 257 static bool is_device_supported(struct rte_eth_dev *dev,
 258                                 struct rte_pci_driver *drv);
 259
 260 /* For Virtual Function support */
 261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 263 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 264 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 265 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 266                                    int wait_to_complete);
 267 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 268 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 269 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 270 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 271 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 272 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 273                 struct rte_eth_stats *stats);
 274 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 275 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 276                 uint16_t vlan_id, int on);
 277 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 278                 uint16_t queue, int on);
 279 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 280 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 281 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 282                                             uint16_t queue_id);
 283 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 284                                              uint16_t queue_id);
 285 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 286                                  uint8_t queue, uint8_t msix_vector);
 287 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 288 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 289 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 290
 291 /* For Eth VMDQ APIs support */
 292 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 293                 ether_addr * mac_addr, uint8_t on);
 294 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 295 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 296                 struct rte_eth_mirror_conf *mirror_conf,
 297                 uint8_t rule_id, uint8_t on);
 298 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 299                 uint8_t rule_id);
 300 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 301                                           uint16_t queue_id);
 302 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 303                                            uint16_t queue_id);
 304 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 305                                uint8_t queue, uint8_t msix_vector);
 306 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 307
 308 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 309                                 struct ether_addr *mac_addr,
 310                                 uint32_t index, uint32_t pool);
 311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 313                                              struct ether_addr *mac_addr);
 314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter);
 316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 317                         enum rte_filter_op filter_op,
 318                         void *arg);
 319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 322                         struct ixgbe_5tuple_filter *filter);
 323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ntuple_filter *filter);
 328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 332                         struct rte_eth_ethertype_filter *filter);
 333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 334                      enum rte_filter_type filter_type,
 335                      enum rte_filter_op filter_op,
 336                      void *arg);
 337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 338
 339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 340                                       struct ether_addr *mc_addr_set,
 341                                       uint32_t nb_mc_addr);
 342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 343                                    struct rte_eth_dcb_info *dcb_info);
 344
 345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 347                             struct rte_dev_reg_info *regs);
 348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353
 354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 356                                 struct rte_dev_reg_info *regs);
 357
 358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 361                                             struct timespec *timestamp,
 362                                             uint32_t flags);
 363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 364                                             struct timespec *timestamp);
 365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 367                                    struct timespec *timestamp);
 368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 369                                    const struct timespec *timestamp);
 370 static void ixgbevf_dev_interrupt_handler(void *param);
 371
 372 static int ixgbe_dev_l2_tunnel_eth_type_conf
 373         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 374 static int ixgbe_dev_l2_tunnel_offload_set
 375         (struct rte_eth_dev *dev,
 376          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 377          uint32_t mask,
 378          uint8_t en);
 379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 380                                              enum rte_filter_op filter_op,
 381                                              void *arg);
 382
 383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 384                                          struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 386                                          struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 389
 390 /*
 391  * Define VF Stats MACRO for Non "cleared on read" register
 392  */
 393 #define UPDATE_VF_STAT(reg, last, cur)                          \
 394 {                                                               \
 395         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 396         cur += (latest - last) & UINT_MAX;                      \
 397         last = latest;                                          \
 398 }
 399
 400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 401 {                                                                \
 402         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 403         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 404         u64 latest = ((new_msb << 32) | new_lsb);                \
 405         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 406         last = latest;                                           \
 407 }
 408
 409 #define IXGBE_SET_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] |= 1 << bit;\
 413         } while (0)
 414
 415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (h)->bitmap[idx] &= ~(1 << bit);\
 419         } while (0)
 420
 421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 422                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 423                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 424                 (r) = (h)->bitmap[idx] >> bit & 1;\
 425         } while (0)
 426
 427 /*
 428  * The set of PCI devices this driver supports
 429  */
 430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 479 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 481 #endif
 482         { .vendor_id = 0, /* sentinel */ },
 483 };
 484
 485 /*
 486  * The set of PCI devices this driver supports (for 82599 VF)
 487  */
 488 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 499         { .vendor_id = 0, /* sentinel */ },
 500 };
 501
 502 static const struct rte_eth_desc_lim rx_desc_lim = {
 503         .nb_max = IXGBE_MAX_RING_DESC,
 504         .nb_min = IXGBE_MIN_RING_DESC,
 505         .nb_align = IXGBE_RXD_ALIGN,
 506 };
 507
 508 static const struct rte_eth_desc_lim tx_desc_lim = {
 509         .nb_max = IXGBE_MAX_RING_DESC,
 510         .nb_min = IXGBE_MIN_RING_DESC,
 511         .nb_align = IXGBE_TXD_ALIGN,
 512         .nb_seg_max = IXGBE_TX_MAX_SEG,
 513         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 514 };
 515
 516 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 517         .dev_configure        = ixgbe_dev_configure,
 518         .dev_start            = ixgbe_dev_start,
 519         .dev_stop             = ixgbe_dev_stop,
 520         .dev_set_link_up    = ixgbe_dev_set_link_up,
 521         .dev_set_link_down  = ixgbe_dev_set_link_down,
 522         .dev_close            = ixgbe_dev_close,
 523         .dev_reset            = ixgbe_dev_reset,
 524         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 525         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 526         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 527         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 528         .link_update          = ixgbe_dev_link_update,
 529         .stats_get            = ixgbe_dev_stats_get,
 530         .xstats_get           = ixgbe_dev_xstats_get,
 531         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 532         .stats_reset          = ixgbe_dev_stats_reset,
 533         .xstats_reset         = ixgbe_dev_xstats_reset,
 534         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 535         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 536         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 537         .fw_version_get       = ixgbe_fw_version_get,
 538         .dev_infos_get        = ixgbe_dev_info_get,
 539         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 540         .mtu_set              = ixgbe_dev_mtu_set,
 541         .vlan_filter_set      = ixgbe_vlan_filter_set,
 542         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 543         .vlan_offload_set     = ixgbe_vlan_offload_set,
 544         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 545         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 546         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 547         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 548         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 549         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 550         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 551         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 552         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 553         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 554         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 555         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 556         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 557         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 558         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 559         .dev_led_on           = ixgbe_dev_led_on,
 560         .dev_led_off          = ixgbe_dev_led_off,
 561         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 562         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 563         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 564         .mac_addr_add         = ixgbe_add_rar,
 565         .mac_addr_remove      = ixgbe_remove_rar,
 566         .mac_addr_set         = ixgbe_set_default_mac_addr,
 567         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 568         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 569         .mirror_rule_set      = ixgbe_mirror_rule_set,
 570         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 571         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 572         .reta_update          = ixgbe_dev_rss_reta_update,
 573         .reta_query           = ixgbe_dev_rss_reta_query,
 574         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 575         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 576         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 577         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 578         .rxq_info_get         = ixgbe_rxq_info_get,
 579         .txq_info_get         = ixgbe_txq_info_get,
 580         .timesync_enable      = ixgbe_timesync_enable,
 581         .timesync_disable     = ixgbe_timesync_disable,
 582         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 583         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 584         .get_reg              = ixgbe_get_regs,
 585         .get_eeprom_length    = ixgbe_get_eeprom_length,
 586         .get_eeprom           = ixgbe_get_eeprom,
 587         .set_eeprom           = ixgbe_set_eeprom,
 588         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 589         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 590         .timesync_read_time   = ixgbe_timesync_read_time,
 591         .timesync_write_time  = ixgbe_timesync_write_time,
 592         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 593         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 594         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 595         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 596         .tm_ops_get           = ixgbe_tm_ops_get,
 597 };
 598
 599 /*
 600  * dev_ops for virtual function, bare necessities for basic vf
 601  * operation have been implemented
 602  */
 603 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 604         .dev_configure        = ixgbevf_dev_configure,
 605         .dev_start            = ixgbevf_dev_start,
 606         .dev_stop             = ixgbevf_dev_stop,
 607         .link_update          = ixgbevf_dev_link_update,
 608         .stats_get            = ixgbevf_dev_stats_get,
 609         .xstats_get           = ixgbevf_dev_xstats_get,
 610         .stats_reset          = ixgbevf_dev_stats_reset,
 611         .xstats_reset         = ixgbevf_dev_stats_reset,
 612         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 613         .dev_close            = ixgbevf_dev_close,
 614         .dev_reset            = ixgbevf_dev_reset,
 615         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 616         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 617         .dev_infos_get        = ixgbevf_dev_info_get,
 618         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 619         .mtu_set              = ixgbevf_dev_set_mtu,
 620         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 621         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 622         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 623         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 624         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 625         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 626         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 627         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 628         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 629         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 630         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 631         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 632         .mac_addr_add         = ixgbevf_add_mac_addr,
 633         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 634         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 635         .rxq_info_get         = ixgbe_rxq_info_get,
 636         .txq_info_get         = ixgbe_txq_info_get,
 637         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 638         .get_reg              = ixgbevf_get_regs,
 639         .reta_update          = ixgbe_dev_rss_reta_update,
 640         .reta_query           = ixgbe_dev_rss_reta_query,
 641         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 642         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 643 };
 644
 645 /* store statistics names and its offset in stats structure */
 646 struct rte_ixgbe_xstats_name_off {
 647         char name[RTE_ETH_XSTATS_NAME_SIZE];
 648         unsigned offset;
 649 };
 650
 651 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 652         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 653         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 654         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 655         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 656         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 657         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 658         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 659         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 660         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 661         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 662         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 663         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 664         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 665         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 666         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 667                 prc1023)},
 668         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 669                 prc1522)},
 670         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 671         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 672         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 673         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 674         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 675         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 676         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 677         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 678         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 679         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 680         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 681         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 682         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 683         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 684         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 685         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 686         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 687                 ptc1023)},
 688         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 689                 ptc1522)},
 690         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 691         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 692         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 693         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 694
 695         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 696                 fdirustat_add)},
 697         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirustat_remove)},
 699         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 700                 fdirfstat_fadd)},
 701         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 702                 fdirfstat_fremove)},
 703         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 704                 fdirmatch)},
 705         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirmiss)},
 707
 708         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 709         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 710         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 711                 fclast)},
 712         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 713         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 714         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 715         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 716         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 717                 fcoe_noddp)},
 718         {"rx_fcoe_no_direct_data_placement_ext_buff",
 719                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 720
 721         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 722                 lxontxc)},
 723         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 724                 lxonrxc)},
 725         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 726                 lxofftxc)},
 727         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 728                 lxoffrxc)},
 729         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 730 };
 731
 732 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 733                            sizeof(rte_ixgbe_stats_strings[0]))
 734
 735 /* MACsec statistics */
 736 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 737         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 738                 out_pkts_untagged)},
 739         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 740                 out_pkts_encrypted)},
 741         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 742                 out_pkts_protected)},
 743         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 744                 out_octets_encrypted)},
 745         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 746                 out_octets_protected)},
 747         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_untagged)},
 749         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_badtag)},
 751         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_nosci)},
 753         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_unknownsci)},
 755         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 756                 in_octets_decrypted)},
 757         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 758                 in_octets_validated)},
 759         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_unchecked)},
 761         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_delayed)},
 763         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_late)},
 765         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_ok)},
 767         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_invalid)},
 769         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_notvalid)},
 771         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_unusedsa)},
 773         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_notusingsa)},
 775 };
 776
 777 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 778                            sizeof(rte_ixgbe_macsec_strings[0]))
 779
 780 /* Per-queue statistics */
 781 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 782         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 783         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 784         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 785         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 786 };
 787
 788 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 789                            sizeof(rte_ixgbe_rxq_strings[0]))
 790 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 791
 792 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 793         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 794         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 795         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 796                 pxon2offc)},
 797 };
 798
 799 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 800                            sizeof(rte_ixgbe_txq_strings[0]))
 801 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 802
 803 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 804         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 805 };
 806
 807 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 808                 sizeof(rte_ixgbevf_stats_strings[0]))
 809
 810 /**
 811  * Atomically reads the link status information from global
 812  * structure rte_eth_dev.
 813  *
 814  * @param dev
 815  *   - Pointer to the structure rte_eth_dev to read from.
 816  *   - Pointer to the buffer to be saved with the link status.
 817  *
 818  * @return
 819  *   - On success, zero.
 820  *   - On failure, negative value.
 821  */
 822 static inline int
 823 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 824                                 struct rte_eth_link *link)
 825 {
 826         struct rte_eth_link *dst = link;
 827         struct rte_eth_link *src = &(dev->data->dev_link);
 828
 829         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 830                                         *(uint64_t *)src) == 0)
 831                 return -1;
 832
 833         return 0;
 834 }
 835
 836 /**
 837  * Atomically writes the link status information into global
 838  * structure rte_eth_dev.
 839  *
 840  * @param dev
 841  *   - Pointer to the structure rte_eth_dev to read from.
 842  *   - Pointer to the buffer to be saved with the link status.
 843  *
 844  * @return
 845  *   - On success, zero.
 846  *   - On failure, negative value.
 847  */
 848 static inline int
 849 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 850                                 struct rte_eth_link *link)
 851 {
 852         struct rte_eth_link *dst = &(dev->data->dev_link);
 853         struct rte_eth_link *src = link;
 854
 855         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 856                                         *(uint64_t *)src) == 0)
 857                 return -1;
 858
 859         return 0;
 860 }
 861
 862 /*
 863  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 864  */
 865 static inline int
 866 ixgbe_is_sfp(struct ixgbe_hw *hw)
 867 {
 868         switch (hw->phy.type) {
 869         case ixgbe_phy_sfp_avago:
 870         case ixgbe_phy_sfp_ftl:
 871         case ixgbe_phy_sfp_intel:
 872         case ixgbe_phy_sfp_unknown:
 873         case ixgbe_phy_sfp_passive_tyco:
 874         case ixgbe_phy_sfp_passive_unknown:
 875                 return 1;
 876         default:
 877                 return 0;
 878         }
 879 }
 880
 881 static inline int32_t
 882 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 883 {
 884         uint32_t ctrl_ext;
 885         int32_t status;
 886
 887         status = ixgbe_reset_hw(hw);
 888
 889         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 890         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 891         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 892         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 893         IXGBE_WRITE_FLUSH(hw);
 894
 895         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 896                 status = IXGBE_SUCCESS;
 897         return status;
 898 }
 899
 900 static inline void
 901 ixgbe_enable_intr(struct rte_eth_dev *dev)
 902 {
 903         struct ixgbe_interrupt *intr =
 904                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 905         struct ixgbe_hw *hw =
 906                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 907
 908         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 909         IXGBE_WRITE_FLUSH(hw);
 910 }
 911
 912 /*
 913  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 914  */
 915 static void
 916 ixgbe_disable_intr(struct ixgbe_hw *hw)
 917 {
 918         PMD_INIT_FUNC_TRACE();
 919
 920         if (hw->mac.type == ixgbe_mac_82598EB) {
 921                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 922         } else {
 923                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 924                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 926         }
 927         IXGBE_WRITE_FLUSH(hw);
 928 }
 929
 930 /*
 931  * This function resets queue statistics mapping registers.
 932  * From Niantic datasheet, Initialization of Statistics section:
 933  * "...if software requires the queue counters, the RQSMR and TQSM registers
 934  * must be re-programmed following a device reset.
 935  */
 936 static void
 937 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 938 {
 939         uint32_t i;
 940
 941         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 942                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 943                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 944         }
 945 }
 946
 947
 948 static int
 949 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 950                                   uint16_t queue_id,
 951                                   uint8_t stat_idx,
 952                                   uint8_t is_rx)
 953 {
 954 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 955 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 956 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 957
 958         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 959         struct ixgbe_stat_mapping_registers *stat_mappings =
 960                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 961         uint32_t qsmr_mask = 0;
 962         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 963         uint32_t q_map;
 964         uint8_t n, offset;
 965
 966         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 967                 (hw->mac.type != ixgbe_mac_X540) &&
 968                 (hw->mac.type != ixgbe_mac_X550) &&
 969                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 970                 (hw->mac.type != ixgbe_mac_X550EM_a))
 971                 return -ENOSYS;
 972
 973         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 974                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 975                      queue_id, stat_idx);
 976
 977         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 978         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 979                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 980                 return -EIO;
 981         }
 982         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 983
 984         /* Now clear any previous stat_idx set */
 985         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 986         if (!is_rx)
 987                 stat_mappings->tqsm[n] &= ~clearing_mask;
 988         else
 989                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 990
 991         q_map = (uint32_t)stat_idx;
 992         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 993         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 994         if (!is_rx)
 995                 stat_mappings->tqsm[n] |= qsmr_mask;
 996         else
 997                 stat_mappings->rqsmr[n] |= qsmr_mask;
 998
 999         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1000                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1001                      queue_id, stat_idx);
1002         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1003                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1004
1005         /* Now write the mapping in the appropriate register */
1006         if (is_rx) {
1007                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1008                              stat_mappings->rqsmr[n], n);
1009                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1010         } else {
1011                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1012                              stat_mappings->tqsm[n], n);
1013                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1014         }
1015         return 0;
1016 }
1017
1018 static void
1019 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1020 {
1021         struct ixgbe_stat_mapping_registers *stat_mappings =
1022                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024         int i;
1025
1026         /* write whatever was in stat mapping table to the NIC */
1027         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1028                 /* rx */
1029                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1030
1031                 /* tx */
1032                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1033         }
1034 }
1035
1036 static void
1037 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1038 {
1039         uint8_t i;
1040         struct ixgbe_dcb_tc_config *tc;
1041         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1042
1043         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1044         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1045         for (i = 0; i < dcb_max_tc; i++) {
1046                 tc = &dcb_config->tc_config[i];
1047                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1048                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1049                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1050                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1051                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1052                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1053                 tc->pfc = ixgbe_dcb_pfc_disabled;
1054         }
1055
1056         /* Initialize default user to priority mapping, UPx->TC0 */
1057         tc = &dcb_config->tc_config[0];
1058         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1059         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1060         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1061                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1062                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1063         }
1064         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1065         dcb_config->pfc_mode_enable = false;
1066         dcb_config->vt_mode = true;
1067         dcb_config->round_robin_enable = false;
1068         /* support all DCB capabilities in 82599 */
1069         dcb_config->support.capabilities = 0xFF;
1070
1071         /*we only support 4 Tcs for X540, X550 */
1072         if (hw->mac.type == ixgbe_mac_X540 ||
1073                 hw->mac.type == ixgbe_mac_X550 ||
1074                 hw->mac.type == ixgbe_mac_X550EM_x ||
1075                 hw->mac.type == ixgbe_mac_X550EM_a) {
1076                 dcb_config->num_tcs.pg_tcs = 4;
1077                 dcb_config->num_tcs.pfc_tcs = 4;
1078         }
1079 }
1080
1081 /*
1082  * Ensure that all locks are released before first NVM or PHY access
1083  */
1084 static void
1085 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1086 {
1087         uint16_t mask;
1088
1089         /*
1090          * Phy lock should not fail in this early stage. If this is the case,
1091          * it is due to an improper exit of the application.
1092          * So force the release of the faulty lock. Release of common lock
1093          * is done automatically by swfw_sync function.
1094          */
1095         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1096         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1097                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1098         }
1099         ixgbe_release_swfw_semaphore(hw, mask);
1100
1101         /*
1102          * These ones are more tricky since they are common to all ports; but
1103          * swfw_sync retries last long enough (1s) to be almost sure that if
1104          * lock can not be taken it is due to an improper lock of the
1105          * semaphore.
1106          */
1107         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1108         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1109                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1110         }
1111         ixgbe_release_swfw_semaphore(hw, mask);
1112 }
1113
1114 /*
1115  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1116  * It returns 0 on success.
1117  */
1118 static int
1119 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1120 {
1121         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1122         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1123         struct ixgbe_hw *hw =
1124                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1125         struct ixgbe_vfta *shadow_vfta =
1126                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1127         struct ixgbe_hwstrip *hwstrip =
1128                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1129         struct ixgbe_dcb_config *dcb_config =
1130                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1131         struct ixgbe_filter_info *filter_info =
1132                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1133         struct ixgbe_bw_conf *bw_conf =
1134                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1135         uint32_t ctrl_ext;
1136         uint16_t csum;
1137         int diag, i;
1138
1139         PMD_INIT_FUNC_TRACE();
1140
1141         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1142         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1143         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1144         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1145
1146         /*
1147          * For secondary processes, we don't initialise any further as primary
1148          * has already done this work. Only check we don't need a different
1149          * RX and TX function.
1150          */
1151         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1152                 struct ixgbe_tx_queue *txq;
1153                 /* TX queue function in primary, set by last queue initialized
1154                  * Tx queue may not initialized by primary process
1155                  */
1156                 if (eth_dev->data->tx_queues) {
1157                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1158                         ixgbe_set_tx_function(eth_dev, txq);
1159                 } else {
1160                         /* Use default TX function if we get here */
1161                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1162                                      "Using default TX function.");
1163                 }
1164
1165                 ixgbe_set_rx_function(eth_dev);
1166
1167                 return 0;
1168         }
1169
1170         rte_eth_copy_pci_info(eth_dev, pci_dev);
1171         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1172
1173         /* Vendor and Device ID need to be set before init of shared code */
1174         hw->device_id = pci_dev->id.device_id;
1175         hw->vendor_id = pci_dev->id.vendor_id;
1176         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1177         hw->allow_unsupported_sfp = 1;
1178
1179         /* Initialize the shared code (base driver) */
1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1181         diag = ixgbe_bypass_init_shared_code(hw);
1182 #else
1183         diag = ixgbe_init_shared_code(hw);
1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1185
1186         if (diag != IXGBE_SUCCESS) {
1187                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1188                 return -EIO;
1189         }
1190
1191         /* pick up the PCI bus settings for reporting later */
1192         ixgbe_get_bus_info(hw);
1193
1194         /* Unlock any pending hardware semaphore */
1195         ixgbe_swfw_lock_reset(hw);
1196
1197         /* Initialize DCB configuration*/
1198         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1199         ixgbe_dcb_init(hw, dcb_config);
1200         /* Get Hardware Flow Control setting */
1201         hw->fc.requested_mode = ixgbe_fc_full;
1202         hw->fc.current_mode = ixgbe_fc_full;
1203         hw->fc.pause_time = IXGBE_FC_PAUSE;
1204         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1205                 hw->fc.low_water[i] = IXGBE_FC_LO;
1206                 hw->fc.high_water[i] = IXGBE_FC_HI;
1207         }
1208         hw->fc.send_xon = 1;
1209
1210         /* Make sure we have a good EEPROM before we read from it */
1211         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1212         if (diag != IXGBE_SUCCESS) {
1213                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1214                 return -EIO;
1215         }
1216
1217 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1218         diag = ixgbe_bypass_init_hw(hw);
1219 #else
1220         diag = ixgbe_init_hw(hw);
1221 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1222
1223         /*
1224          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1225          * is called too soon after the kernel driver unbinding/binding occurs.
1226          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1227          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1228          * also called. See ixgbe_identify_phy_82599(). The reason for the
1229          * failure is not known, and only occuts when virtualisation features
1230          * are disabled in the bios. A delay of 100ms  was found to be enough by
1231          * trial-and-error, and is doubled to be safe.
1232          */
1233         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1234                 rte_delay_ms(200);
1235                 diag = ixgbe_init_hw(hw);
1236         }
1237
1238         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1239                 diag = IXGBE_SUCCESS;
1240
1241         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1242                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1243                              "LOM.  Please be aware there may be issues associated "
1244                              "with your hardware.");
1245                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1246                              "please contact your Intel or hardware representative "
1247                              "who provided you with this hardware.");
1248         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1249                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1250         if (diag) {
1251                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1252                 return -EIO;
1253         }
1254
1255         /* Reset the hw statistics */
1256         ixgbe_dev_stats_reset(eth_dev);
1257
1258         /* disable interrupt */
1259         ixgbe_disable_intr(hw);
1260
1261         /* reset mappings for queue statistics hw counters*/
1262         ixgbe_reset_qstat_mappings(hw);
1263
1264         /* Allocate memory for storing MAC addresses */
1265         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1266                                                hw->mac.num_rar_entries, 0);
1267         if (eth_dev->data->mac_addrs == NULL) {
1268                 PMD_INIT_LOG(ERR,
1269                              "Failed to allocate %u bytes needed to store "
1270                              "MAC addresses",
1271                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1272                 return -ENOMEM;
1273         }
1274         /* Copy the permanent MAC address */
1275         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1276                         &eth_dev->data->mac_addrs[0]);
1277
1278         /* Allocate memory for storing hash filter MAC addresses */
1279         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1280                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1281         if (eth_dev->data->hash_mac_addrs == NULL) {
1282                 PMD_INIT_LOG(ERR,
1283                              "Failed to allocate %d bytes needed to store MAC addresses",
1284                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1285                 return -ENOMEM;
1286         }
1287
1288         /* initialize the vfta */
1289         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1290
1291         /* initialize the hw strip bitmap*/
1292         memset(hwstrip, 0, sizeof(*hwstrip));
1293
1294         /* initialize PF if max_vfs not zero */
1295         ixgbe_pf_host_init(eth_dev);
1296
1297         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1298         /* let hardware know driver is loaded */
1299         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1300         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1301         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1302         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1303         IXGBE_WRITE_FLUSH(hw);
1304
1305         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1306                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1307                              (int) hw->mac.type, (int) hw->phy.type,
1308                              (int) hw->phy.sfp_type);
1309         else
1310                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1311                              (int) hw->mac.type, (int) hw->phy.type);
1312
1313         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1314                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1315                      pci_dev->id.device_id);
1316
1317         rte_intr_callback_register(intr_handle,
1318                                    ixgbe_dev_interrupt_handler, eth_dev);
1319
1320         /* enable uio/vfio intr/eventfd mapping */
1321         rte_intr_enable(intr_handle);
1322
1323         /* enable support intr */
1324         ixgbe_enable_intr(eth_dev);
1325
1326         /* initialize filter info */
1327         memset(filter_info, 0,
1328                sizeof(struct ixgbe_filter_info));
1329
1330         /* initialize 5tuple filter list */
1331         TAILQ_INIT(&filter_info->fivetuple_list);
1332
1333         /* initialize flow director filter list & hash */
1334         ixgbe_fdir_filter_init(eth_dev);
1335
1336         /* initialize l2 tunnel filter list & hash */
1337         ixgbe_l2_tn_filter_init(eth_dev);
1338
1339         /* initialize flow filter lists */
1340         ixgbe_filterlist_init();
1341
1342         /* initialize bandwidth configuration info */
1343         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1344
1345         /* initialize Traffic Manager configuration */
1346         ixgbe_tm_conf_init(eth_dev);
1347
1348         return 0;
1349 }
1350
1351 static int
1352 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1353 {
1354         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1355         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1356         struct ixgbe_hw *hw;
1357
1358         PMD_INIT_FUNC_TRACE();
1359
1360         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1361                 return -EPERM;
1362
1363         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1364
1365         if (hw->adapter_stopped == 0)
1366                 ixgbe_dev_close(eth_dev);
1367
1368         eth_dev->dev_ops = NULL;
1369         eth_dev->rx_pkt_burst = NULL;
1370         eth_dev->tx_pkt_burst = NULL;
1371
1372         /* Unlock any pending hardware semaphore */
1373         ixgbe_swfw_lock_reset(hw);
1374
1375         /* disable uio intr before callback unregister */
1376         rte_intr_disable(intr_handle);
1377         rte_intr_callback_unregister(intr_handle,
1378                                      ixgbe_dev_interrupt_handler, eth_dev);
1379
1380         /* uninitialize PF if max_vfs not zero */
1381         ixgbe_pf_host_uninit(eth_dev);
1382
1383         rte_free(eth_dev->data->mac_addrs);
1384         eth_dev->data->mac_addrs = NULL;
1385
1386         rte_free(eth_dev->data->hash_mac_addrs);
1387         eth_dev->data->hash_mac_addrs = NULL;
1388
1389         /* remove all the fdir filters & hash */
1390         ixgbe_fdir_filter_uninit(eth_dev);
1391
1392         /* remove all the L2 tunnel filters & hash */
1393         ixgbe_l2_tn_filter_uninit(eth_dev);
1394
1395         /* Remove all ntuple filters of the device */
1396         ixgbe_ntuple_filter_uninit(eth_dev);
1397
1398         /* clear all the filters list */
1399         ixgbe_filterlist_flush();
1400
1401         /* Remove all Traffic Manager configuration */
1402         ixgbe_tm_conf_uninit(eth_dev);
1403
1404         return 0;
1405 }
1406
1407 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1408 {
1409         struct ixgbe_filter_info *filter_info =
1410                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1411         struct ixgbe_5tuple_filter *p_5tuple;
1412
1413         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1414                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1415                              p_5tuple,
1416                              entries);
1417                 rte_free(p_5tuple);
1418         }
1419         memset(filter_info->fivetuple_mask, 0,
1420                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1421
1422         return 0;
1423 }
1424
1425 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1426 {
1427         struct ixgbe_hw_fdir_info *fdir_info =
1428                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1429         struct ixgbe_fdir_filter *fdir_filter;
1430
1431                 if (fdir_info->hash_map)
1432                 rte_free(fdir_info->hash_map);
1433         if (fdir_info->hash_handle)
1434                 rte_hash_free(fdir_info->hash_handle);
1435
1436         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1437                 TAILQ_REMOVE(&fdir_info->fdir_list,
1438                              fdir_filter,
1439                              entries);
1440                 rte_free(fdir_filter);
1441         }
1442
1443         return 0;
1444 }
1445
1446 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1447 {
1448         struct ixgbe_l2_tn_info *l2_tn_info =
1449                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1450         struct ixgbe_l2_tn_filter *l2_tn_filter;
1451
1452         if (l2_tn_info->hash_map)
1453                 rte_free(l2_tn_info->hash_map);
1454         if (l2_tn_info->hash_handle)
1455                 rte_hash_free(l2_tn_info->hash_handle);
1456
1457         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1458                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1459                              l2_tn_filter,
1460                              entries);
1461                 rte_free(l2_tn_filter);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1468 {
1469         struct ixgbe_hw_fdir_info *fdir_info =
1470                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1471         char fdir_hash_name[RTE_HASH_NAMESIZE];
1472         struct rte_hash_parameters fdir_hash_params = {
1473                 .name = fdir_hash_name,
1474                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1475                 .key_len = sizeof(union ixgbe_atr_input),
1476                 .hash_func = rte_hash_crc,
1477                 .hash_func_init_val = 0,
1478                 .socket_id = rte_socket_id(),
1479         };
1480
1481         TAILQ_INIT(&fdir_info->fdir_list);
1482         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1483                  "fdir_%s", eth_dev->device->name);
1484         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1485         if (!fdir_info->hash_handle) {
1486                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1487                 return -EINVAL;
1488         }
1489         fdir_info->hash_map = rte_zmalloc("ixgbe",
1490                                           sizeof(struct ixgbe_fdir_filter *) *
1491                                           IXGBE_MAX_FDIR_FILTER_NUM,
1492                                           0);
1493         if (!fdir_info->hash_map) {
1494                 PMD_INIT_LOG(ERR,
1495                              "Failed to allocate memory for fdir hash map!");
1496                 return -ENOMEM;
1497         }
1498         fdir_info->mask_added = FALSE;
1499
1500         return 0;
1501 }
1502
1503 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1504 {
1505         struct ixgbe_l2_tn_info *l2_tn_info =
1506                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1507         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1508         struct rte_hash_parameters l2_tn_hash_params = {
1509                 .name = l2_tn_hash_name,
1510                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1511                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1512                 .hash_func = rte_hash_crc,
1513                 .hash_func_init_val = 0,
1514                 .socket_id = rte_socket_id(),
1515         };
1516
1517         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1518         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1519                  "l2_tn_%s", eth_dev->device->name);
1520         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1521         if (!l2_tn_info->hash_handle) {
1522                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1523                 return -EINVAL;
1524         }
1525         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1526                                    sizeof(struct ixgbe_l2_tn_filter *) *
1527                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1528                                    0);
1529         if (!l2_tn_info->hash_map) {
1530                 PMD_INIT_LOG(ERR,
1531                         "Failed to allocate memory for L2 TN hash map!");
1532                 return -ENOMEM;
1533         }
1534         l2_tn_info->e_tag_en = FALSE;
1535         l2_tn_info->e_tag_fwd_en = FALSE;
1536         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1537
1538         return 0;
1539 }
1540 /*
1541  * Negotiate mailbox API version with the PF.
1542  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1543  * Then we try to negotiate starting with the most recent one.
1544  * If all negotiation attempts fail, then we will proceed with
1545  * the default one (ixgbe_mbox_api_10).
1546  */
1547 static void
1548 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1549 {
1550         int32_t i;
1551
1552         /* start with highest supported, proceed down */
1553         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1554                 ixgbe_mbox_api_12,
1555                 ixgbe_mbox_api_11,
1556                 ixgbe_mbox_api_10,
1557         };
1558
1559         for (i = 0;
1560                         i != RTE_DIM(sup_ver) &&
1561                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1562                         i++)
1563                 ;
1564 }
1565
1566 static void
1567 generate_random_mac_addr(struct ether_addr *mac_addr)
1568 {
1569         uint64_t random;
1570
1571         /* Set Organizationally Unique Identifier (OUI) prefix. */
1572         mac_addr->addr_bytes[0] = 0x00;
1573         mac_addr->addr_bytes[1] = 0x09;
1574         mac_addr->addr_bytes[2] = 0xC0;
1575         /* Force indication of locally assigned MAC address. */
1576         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1577         /* Generate the last 3 bytes of the MAC address with a random number. */
1578         random = rte_rand();
1579         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1580 }
1581
1582 /*
1583  * Virtual Function device init
1584  */
1585 static int
1586 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1587 {
1588         int diag;
1589         uint32_t tc, tcs;
1590         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1591         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1592         struct ixgbe_hw *hw =
1593                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1594         struct ixgbe_vfta *shadow_vfta =
1595                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1596         struct ixgbe_hwstrip *hwstrip =
1597                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1598         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1603         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1604         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1605
1606         /* for secondary processes, we don't initialise any further as primary
1607          * has already done this work. Only check we don't need a different
1608          * RX function
1609          */
1610         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1611                 struct ixgbe_tx_queue *txq;
1612                 /* TX queue function in primary, set by last queue initialized
1613                  * Tx queue may not initialized by primary process
1614                  */
1615                 if (eth_dev->data->tx_queues) {
1616                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1617                         ixgbe_set_tx_function(eth_dev, txq);
1618                 } else {
1619                         /* Use default TX function if we get here */
1620                         PMD_INIT_LOG(NOTICE,
1621                                      "No TX queues configured yet. Using default TX function.");
1622                 }
1623
1624                 ixgbe_set_rx_function(eth_dev);
1625
1626                 return 0;
1627         }
1628
1629         rte_eth_copy_pci_info(eth_dev, pci_dev);
1630         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1631
1632         hw->device_id = pci_dev->id.device_id;
1633         hw->vendor_id = pci_dev->id.vendor_id;
1634         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1635
1636         /* initialize the vfta */
1637         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1638
1639         /* initialize the hw strip bitmap*/
1640         memset(hwstrip, 0, sizeof(*hwstrip));
1641
1642         /* Initialize the shared code (base driver) */
1643         diag = ixgbe_init_shared_code(hw);
1644         if (diag != IXGBE_SUCCESS) {
1645                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1646                 return -EIO;
1647         }
1648
1649         /* init_mailbox_params */
1650         hw->mbx.ops.init_params(hw);
1651
1652         /* Reset the hw statistics */
1653         ixgbevf_dev_stats_reset(eth_dev);
1654
1655         /* Disable the interrupts for VF */
1656         ixgbevf_intr_disable(hw);
1657
1658         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1659         diag = hw->mac.ops.reset_hw(hw);
1660
1661         /*
1662          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1663          * the underlying PF driver has not assigned a MAC address to the VF.
1664          * In this case, assign a random MAC address.
1665          */
1666         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return diag;
1669         }
1670
1671         /* negotiate mailbox API version to use with the PF. */
1672         ixgbevf_negotiate_api(hw);
1673
1674         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1675         ixgbevf_get_queues(hw, &tcs, &tc);
1676
1677         /* Allocate memory for storing MAC addresses */
1678         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1679                                                hw->mac.num_rar_entries, 0);
1680         if (eth_dev->data->mac_addrs == NULL) {
1681                 PMD_INIT_LOG(ERR,
1682                              "Failed to allocate %u bytes needed to store "
1683                              "MAC addresses",
1684                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1685                 return -ENOMEM;
1686         }
1687
1688         /* Generate a random MAC address, if none was assigned by PF. */
1689         if (is_zero_ether_addr(perm_addr)) {
1690                 generate_random_mac_addr(perm_addr);
1691                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1692                 if (diag) {
1693                         rte_free(eth_dev->data->mac_addrs);
1694                         eth_dev->data->mac_addrs = NULL;
1695                         return diag;
1696                 }
1697                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1698                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1699                              "%02x:%02x:%02x:%02x:%02x:%02x",
1700                              perm_addr->addr_bytes[0],
1701                              perm_addr->addr_bytes[1],
1702                              perm_addr->addr_bytes[2],
1703                              perm_addr->addr_bytes[3],
1704                              perm_addr->addr_bytes[4],
1705                              perm_addr->addr_bytes[5]);
1706         }
1707
1708         /* Copy the permanent MAC address */
1709         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1710
1711         /* reset the hardware with the new settings */
1712         diag = hw->mac.ops.start_hw(hw);
1713         switch (diag) {
1714         case  0:
1715                 break;
1716
1717         default:
1718                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1719                 return -EIO;
1720         }
1721
1722         rte_intr_callback_register(intr_handle,
1723                                    ixgbevf_dev_interrupt_handler, eth_dev);
1724         rte_intr_enable(intr_handle);
1725         ixgbevf_intr_enable(hw);
1726
1727         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1728                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1729                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1730
1731         return 0;
1732 }
1733
1734 /* Virtual Function device uninit */
1735
1736 static int
1737 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1738 {
1739         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1740         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741         struct ixgbe_hw *hw;
1742
1743         PMD_INIT_FUNC_TRACE();
1744
1745         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1746                 return -EPERM;
1747
1748         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1749
1750         if (hw->adapter_stopped == 0)
1751                 ixgbevf_dev_close(eth_dev);
1752
1753         eth_dev->dev_ops = NULL;
1754         eth_dev->rx_pkt_burst = NULL;
1755         eth_dev->tx_pkt_burst = NULL;
1756
1757         /* Disable the interrupts for VF */
1758         ixgbevf_intr_disable(hw);
1759
1760         rte_free(eth_dev->data->mac_addrs);
1761         eth_dev->data->mac_addrs = NULL;
1762
1763         rte_intr_disable(intr_handle);
1764         rte_intr_callback_unregister(intr_handle,
1765                                      ixgbevf_dev_interrupt_handler, eth_dev);
1766
1767         return 0;
1768 }
1769
1770 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1771         struct rte_pci_device *pci_dev)
1772 {
1773         return rte_eth_dev_pci_generic_probe(pci_dev,
1774                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1775 }
1776
1777 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1778 {
1779         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1780 }
1781
1782 static struct rte_pci_driver rte_ixgbe_pmd = {
1783         .id_table = pci_id_ixgbe_map,
1784         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1785                      RTE_PCI_DRV_IOVA_AS_VA,
1786         .probe = eth_ixgbe_pci_probe,
1787         .remove = eth_ixgbe_pci_remove,
1788 };
1789
1790 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1791         struct rte_pci_device *pci_dev)
1792 {
1793         return rte_eth_dev_pci_generic_probe(pci_dev,
1794                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1795 }
1796
1797 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1798 {
1799         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1800 }
1801
1802 /*
1803  * virtual function driver struct
1804  */
1805 static struct rte_pci_driver rte_ixgbevf_pmd = {
1806         .id_table = pci_id_ixgbevf_map,
1807         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1808         .probe = eth_ixgbevf_pci_probe,
1809         .remove = eth_ixgbevf_pci_remove,
1810 };
1811
1812 static int
1813 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1814 {
1815         struct ixgbe_hw *hw =
1816                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1817         struct ixgbe_vfta *shadow_vfta =
1818                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1819         uint32_t vfta;
1820         uint32_t vid_idx;
1821         uint32_t vid_bit;
1822
1823         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1824         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1825         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1826         if (on)
1827                 vfta |= vid_bit;
1828         else
1829                 vfta &= ~vid_bit;
1830         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1831
1832         /* update local VFTA copy */
1833         shadow_vfta->vfta[vid_idx] = vfta;
1834
1835         return 0;
1836 }
1837
1838 static void
1839 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1840 {
1841         if (on)
1842                 ixgbe_vlan_hw_strip_enable(dev, queue);
1843         else
1844                 ixgbe_vlan_hw_strip_disable(dev, queue);
1845 }
1846
1847 static int
1848 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1849                     enum rte_vlan_type vlan_type,
1850                     uint16_t tpid)
1851 {
1852         struct ixgbe_hw *hw =
1853                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1854         int ret = 0;
1855         uint32_t reg;
1856         uint32_t qinq;
1857
1858         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1859         qinq &= IXGBE_DMATXCTL_GDV;
1860
1861         switch (vlan_type) {
1862         case ETH_VLAN_TYPE_INNER:
1863                 if (qinq) {
1864                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1865                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1866                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1867                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1868                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1869                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1870                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1871                 } else {
1872                         ret = -ENOTSUP;
1873                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1874                                     " by single VLAN");
1875                 }
1876                 break;
1877         case ETH_VLAN_TYPE_OUTER:
1878                 if (qinq) {
1879                         /* Only the high 16-bits is valid */
1880                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1881                                         IXGBE_EXVET_VET_EXT_SHIFT);
1882                 } else {
1883                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1884                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1885                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1886                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1888                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1889                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1890                 }
1891
1892                 break;
1893         default:
1894                 ret = -EINVAL;
1895                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1896                 break;
1897         }
1898
1899         return ret;
1900 }
1901
1902 void
1903 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1904 {
1905         struct ixgbe_hw *hw =
1906                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1907         uint32_t vlnctrl;
1908
1909         PMD_INIT_FUNC_TRACE();
1910
1911         /* Filter Table Disable */
1912         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1913         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1914
1915         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1916 }
1917
1918 void
1919 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1920 {
1921         struct ixgbe_hw *hw =
1922                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923         struct ixgbe_vfta *shadow_vfta =
1924                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1925         uint32_t vlnctrl;
1926         uint16_t i;
1927
1928         PMD_INIT_FUNC_TRACE();
1929
1930         /* Filter Table Enable */
1931         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1932         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1933         vlnctrl |= IXGBE_VLNCTRL_VFE;
1934
1935         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1936
1937         /* write whatever is in local vfta copy */
1938         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1939                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1940 }
1941
1942 static void
1943 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1944 {
1945         struct ixgbe_hwstrip *hwstrip =
1946                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1947         struct ixgbe_rx_queue *rxq;
1948
1949         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1950                 return;
1951
1952         if (on)
1953                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1954         else
1955                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1956
1957         if (queue >= dev->data->nb_rx_queues)
1958                 return;
1959
1960         rxq = dev->data->rx_queues[queue];
1961
1962         if (on)
1963                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1964         else
1965                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1966 }
1967
1968 static void
1969 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1970 {
1971         struct ixgbe_hw *hw =
1972                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973         uint32_t ctrl;
1974
1975         PMD_INIT_FUNC_TRACE();
1976
1977         if (hw->mac.type == ixgbe_mac_82598EB) {
1978                 /* No queue level support */
1979                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1980                 return;
1981         }
1982
1983         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1984         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1985         ctrl &= ~IXGBE_RXDCTL_VME;
1986         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1987
1988         /* record those setting for HW strip per queue */
1989         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1990 }
1991
1992 static void
1993 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1994 {
1995         struct ixgbe_hw *hw =
1996                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997         uint32_t ctrl;
1998
1999         PMD_INIT_FUNC_TRACE();
2000
2001         if (hw->mac.type == ixgbe_mac_82598EB) {
2002                 /* No queue level supported */
2003                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2004                 return;
2005         }
2006
2007         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2008         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2009         ctrl |= IXGBE_RXDCTL_VME;
2010         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2011
2012         /* record those setting for HW strip per queue */
2013         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2014 }
2015
2016 void
2017 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2018 {
2019         struct ixgbe_hw *hw =
2020                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2021         uint32_t ctrl;
2022         uint16_t i;
2023         struct ixgbe_rx_queue *rxq;
2024
2025         PMD_INIT_FUNC_TRACE();
2026
2027         if (hw->mac.type == ixgbe_mac_82598EB) {
2028                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2029                 ctrl &= ~IXGBE_VLNCTRL_VME;
2030                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2031         } else {
2032                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2033                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2034                         rxq = dev->data->rx_queues[i];
2035                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2036                         ctrl &= ~IXGBE_RXDCTL_VME;
2037                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2038
2039                         /* record those setting for HW strip per queue */
2040                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2041                 }
2042         }
2043 }
2044
2045 void
2046 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2047 {
2048         struct ixgbe_hw *hw =
2049                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050         uint32_t ctrl;
2051         uint16_t i;
2052         struct ixgbe_rx_queue *rxq;
2053
2054         PMD_INIT_FUNC_TRACE();
2055
2056         if (hw->mac.type == ixgbe_mac_82598EB) {
2057                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2058                 ctrl |= IXGBE_VLNCTRL_VME;
2059                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2060         } else {
2061                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2062                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2063                         rxq = dev->data->rx_queues[i];
2064                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2065                         ctrl |= IXGBE_RXDCTL_VME;
2066                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2067
2068                         /* record those setting for HW strip per queue */
2069                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2070                 }
2071         }
2072 }
2073
2074 static void
2075 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2076 {
2077         struct ixgbe_hw *hw =
2078                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         uint32_t ctrl;
2080
2081         PMD_INIT_FUNC_TRACE();
2082
2083         /* DMATXCTRL: Geric Double VLAN Disable */
2084         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2085         ctrl &= ~IXGBE_DMATXCTL_GDV;
2086         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2087
2088         /* CTRL_EXT: Global Double VLAN Disable */
2089         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2090         ctrl &= ~IXGBE_EXTENDED_VLAN;
2091         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2092
2093 }
2094
2095 static void
2096 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2097 {
2098         struct ixgbe_hw *hw =
2099                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         uint32_t ctrl;
2101
2102         PMD_INIT_FUNC_TRACE();
2103
2104         /* DMATXCTRL: Geric Double VLAN Enable */
2105         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2106         ctrl |= IXGBE_DMATXCTL_GDV;
2107         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2108
2109         /* CTRL_EXT: Global Double VLAN Enable */
2110         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2111         ctrl |= IXGBE_EXTENDED_VLAN;
2112         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2113
2114         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2115         if (hw->mac.type == ixgbe_mac_X550 ||
2116             hw->mac.type == ixgbe_mac_X550EM_x ||
2117             hw->mac.type == ixgbe_mac_X550EM_a) {
2118                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2119                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2120                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2121         }
2122
2123         /*
2124          * VET EXT field in the EXVET register = 0x8100 by default
2125          * So no need to change. Same to VT field of DMATXCTL register
2126          */
2127 }
2128
2129 static void
2130 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2131 {
2132         if (mask & ETH_VLAN_STRIP_MASK) {
2133                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2134                         ixgbe_vlan_hw_strip_enable_all(dev);
2135                 else
2136                         ixgbe_vlan_hw_strip_disable_all(dev);
2137         }
2138
2139         if (mask & ETH_VLAN_FILTER_MASK) {
2140                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2141                         ixgbe_vlan_hw_filter_enable(dev);
2142                 else
2143                         ixgbe_vlan_hw_filter_disable(dev);
2144         }
2145
2146         if (mask & ETH_VLAN_EXTEND_MASK) {
2147                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2148                         ixgbe_vlan_hw_extend_enable(dev);
2149                 else
2150                         ixgbe_vlan_hw_extend_disable(dev);
2151         }
2152 }
2153
2154 static void
2155 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2156 {
2157         struct ixgbe_hw *hw =
2158                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2160         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2161
2162         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2163         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2164 }
2165
2166 static int
2167 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2168 {
2169         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2170
2171         switch (nb_rx_q) {
2172         case 1:
2173         case 2:
2174                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2175                 break;
2176         case 4:
2177                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2178                 break;
2179         default:
2180                 return -EINVAL;
2181         }
2182
2183         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2184         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2185
2186         return 0;
2187 }
2188
2189 static int
2190 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2191 {
2192         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2193         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2194         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2195         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2196
2197         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2198                 /* check multi-queue mode */
2199                 switch (dev_conf->rxmode.mq_mode) {
2200                 case ETH_MQ_RX_VMDQ_DCB:
2201                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2202                         break;
2203                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2204                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2205                         PMD_INIT_LOG(ERR, "SRIOV active,"
2206                                         " unsupported mq_mode rx %d.",
2207                                         dev_conf->rxmode.mq_mode);
2208                         return -EINVAL;
2209                 case ETH_MQ_RX_RSS:
2210                 case ETH_MQ_RX_VMDQ_RSS:
2211                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2212                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2213                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2214                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2215                                                 " invalid queue number"
2216                                                 " for VMDQ RSS, allowed"
2217                                                 " value are 1, 2 or 4.");
2218                                         return -EINVAL;
2219                                 }
2220                         break;
2221                 case ETH_MQ_RX_VMDQ_ONLY:
2222                 case ETH_MQ_RX_NONE:
2223                         /* if nothing mq mode configure, use default scheme */
2224                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2225                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2226                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2227                         break;
2228                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2229                         /* SRIOV only works in VMDq enable mode */
2230                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2231                                         " wrong mq_mode rx %d.",
2232                                         dev_conf->rxmode.mq_mode);
2233                         return -EINVAL;
2234                 }
2235
2236                 switch (dev_conf->txmode.mq_mode) {
2237                 case ETH_MQ_TX_VMDQ_DCB:
2238                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2239                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2240                         break;
2241                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2242                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2243                         break;
2244                 }
2245
2246                 /* check valid queue number */
2247                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2248                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2249                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2250                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2251                                         " must be less than or equal to %d.",
2252                                         nb_rx_q, nb_tx_q,
2253                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2254                         return -EINVAL;
2255                 }
2256         } else {
2257                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2258                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2259                                           " not supported.");
2260                         return -EINVAL;
2261                 }
2262                 /* check configuration for vmdb+dcb mode */
2263                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2264                         const struct rte_eth_vmdq_dcb_conf *conf;
2265
2266                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2267                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2268                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2269                                 return -EINVAL;
2270                         }
2271                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2272                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2273                                conf->nb_queue_pools == ETH_32_POOLS)) {
2274                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2275                                                 " nb_queue_pools must be %d or %d.",
2276                                                 ETH_16_POOLS, ETH_32_POOLS);
2277                                 return -EINVAL;
2278                         }
2279                 }
2280                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2281                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2282
2283                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2284                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2285                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2286                                 return -EINVAL;
2287                         }
2288                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2289                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2290                                conf->nb_queue_pools == ETH_32_POOLS)) {
2291                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2292                                                 " nb_queue_pools != %d and"
2293                                                 " nb_queue_pools != %d.",
2294                                                 ETH_16_POOLS, ETH_32_POOLS);
2295                                 return -EINVAL;
2296                         }
2297                 }
2298
2299                 /* For DCB mode check our configuration before we go further */
2300                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2301                         const struct rte_eth_dcb_rx_conf *conf;
2302
2303                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2304                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2305                                                  IXGBE_DCB_NB_QUEUES);
2306                                 return -EINVAL;
2307                         }
2308                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2309                         if (!(conf->nb_tcs == ETH_4_TCS ||
2310                                conf->nb_tcs == ETH_8_TCS)) {
2311                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2312                                                 " and nb_tcs != %d.",
2313                                                 ETH_4_TCS, ETH_8_TCS);
2314                                 return -EINVAL;
2315                         }
2316                 }
2317
2318                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2319                         const struct rte_eth_dcb_tx_conf *conf;
2320
2321                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2322                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2323                                                  IXGBE_DCB_NB_QUEUES);
2324                                 return -EINVAL;
2325                         }
2326                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2327                         if (!(conf->nb_tcs == ETH_4_TCS ||
2328                                conf->nb_tcs == ETH_8_TCS)) {
2329                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2330                                                 " and nb_tcs != %d.",
2331                                                 ETH_4_TCS, ETH_8_TCS);
2332                                 return -EINVAL;
2333                         }
2334                 }
2335
2336                 /*
2337                  * When DCB/VT is off, maximum number of queues changes,
2338                  * except for 82598EB, which remains constant.
2339                  */
2340                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2341                                 hw->mac.type != ixgbe_mac_82598EB) {
2342                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2343                                 PMD_INIT_LOG(ERR,
2344                                              "Neither VT nor DCB are enabled, "
2345                                              "nb_tx_q > %d.",
2346                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2347                                 return -EINVAL;
2348                         }
2349                 }
2350         }
2351         return 0;
2352 }
2353
2354 static int
2355 ixgbe_dev_configure(struct rte_eth_dev *dev)
2356 {
2357         struct ixgbe_interrupt *intr =
2358                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2359         struct ixgbe_adapter *adapter =
2360                 (struct ixgbe_adapter *)dev->data->dev_private;
2361         int ret;
2362
2363         PMD_INIT_FUNC_TRACE();
2364         /* multipe queue mode checking */
2365         ret  = ixgbe_check_mq_mode(dev);
2366         if (ret != 0) {
2367                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2368                             ret);
2369                 return ret;
2370         }
2371
2372         /* set flag to update link status after init */
2373         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2374
2375         /*
2376          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2377          * allocation or vector Rx preconditions we will reset it.
2378          */
2379         adapter->rx_bulk_alloc_allowed = true;
2380         adapter->rx_vec_allowed = true;
2381
2382         return 0;
2383 }
2384
2385 static void
2386 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2387 {
2388         struct ixgbe_hw *hw =
2389                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390         struct ixgbe_interrupt *intr =
2391                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2392         uint32_t gpie;
2393
2394         /* only set up it on X550EM_X */
2395         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2396                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2397                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2398                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2399                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2400                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2401         }
2402 }
2403
2404 int
2405 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2406                         uint16_t tx_rate, uint64_t q_msk)
2407 {
2408         struct ixgbe_hw *hw;
2409         struct ixgbe_vf_info *vfinfo;
2410         struct rte_eth_link link;
2411         uint8_t  nb_q_per_pool;
2412         uint32_t queue_stride;
2413         uint32_t queue_idx, idx = 0, vf_idx;
2414         uint32_t queue_end;
2415         uint16_t total_rate = 0;
2416         struct rte_pci_device *pci_dev;
2417
2418         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2419         rte_eth_link_get_nowait(dev->data->port_id, &link);
2420
2421         if (vf >= pci_dev->max_vfs)
2422                 return -EINVAL;
2423
2424         if (tx_rate > link.link_speed)
2425                 return -EINVAL;
2426
2427         if (q_msk == 0)
2428                 return 0;
2429
2430         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2431         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2432         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2433         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2434         queue_idx = vf * queue_stride;
2435         queue_end = queue_idx + nb_q_per_pool - 1;
2436         if (queue_end >= hw->mac.max_tx_queues)
2437                 return -EINVAL;
2438
2439         if (vfinfo) {
2440                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2441                         if (vf_idx == vf)
2442                                 continue;
2443                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2444                                 idx++)
2445                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2446                 }
2447         } else {
2448                 return -EINVAL;
2449         }
2450
2451         /* Store tx_rate for this vf. */
2452         for (idx = 0; idx < nb_q_per_pool; idx++) {
2453                 if (((uint64_t)0x1 << idx) & q_msk) {
2454                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2455                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2456                         total_rate += tx_rate;
2457                 }
2458         }
2459
2460         if (total_rate > dev->data->dev_link.link_speed) {
2461                 /* Reset stored TX rate of the VF if it causes exceed
2462                  * link speed.
2463                  */
2464                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2465                 return -EINVAL;
2466         }
2467
2468         /* Set RTTBCNRC of each queue/pool for vf X  */
2469         for (; queue_idx <= queue_end; queue_idx++) {
2470                 if (0x1 & q_msk)
2471                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2472                 q_msk = q_msk >> 1;
2473         }
2474
2475         return 0;
2476 }
2477
2478 /*
2479  * Configure device link speed and setup link.
2480  * It returns 0 on success.
2481  */
2482 static int
2483 ixgbe_dev_start(struct rte_eth_dev *dev)
2484 {
2485         struct ixgbe_hw *hw =
2486                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487         struct ixgbe_vf_info *vfinfo =
2488                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2489         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2490         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2491         uint32_t intr_vector = 0;
2492         int err, link_up = 0, negotiate = 0;
2493         uint32_t speed = 0;
2494         int mask = 0;
2495         int status;
2496         uint16_t vf, idx;
2497         uint32_t *link_speeds;
2498         struct ixgbe_tm_conf *tm_conf =
2499                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2500
2501         PMD_INIT_FUNC_TRACE();
2502
2503         /* IXGBE devices don't support:
2504         *    - half duplex (checked afterwards for valid speeds)
2505         *    - fixed speed: TODO implement
2506         */
2507         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2508                 PMD_INIT_LOG(ERR,
2509                 "Invalid link_speeds for port %u, fix speed not supported",
2510                                 dev->data->port_id);
2511                 return -EINVAL;
2512         }
2513
2514         /* disable uio/vfio intr/eventfd mapping */
2515         rte_intr_disable(intr_handle);
2516
2517         /* stop adapter */
2518         hw->adapter_stopped = 0;
2519         ixgbe_stop_adapter(hw);
2520
2521         /* reinitialize adapter
2522          * this calls reset and start
2523          */
2524         status = ixgbe_pf_reset_hw(hw);
2525         if (status != 0)
2526                 return -1;
2527         hw->mac.ops.start_hw(hw);
2528         hw->mac.get_link_status = true;
2529
2530         /* configure PF module if SRIOV enabled */
2531         ixgbe_pf_host_configure(dev);
2532
2533         ixgbe_dev_phy_intr_setup(dev);
2534
2535         /* check and configure queue intr-vector mapping */
2536         if ((rte_intr_cap_multiple(intr_handle) ||
2537              !RTE_ETH_DEV_SRIOV(dev).active) &&
2538             dev->data->dev_conf.intr_conf.rxq != 0) {
2539                 intr_vector = dev->data->nb_rx_queues;
2540                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2541                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2542                                         IXGBE_MAX_INTR_QUEUE_NUM);
2543                         return -ENOTSUP;
2544                 }
2545                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2546                         return -1;
2547         }
2548
2549         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2550                 intr_handle->intr_vec =
2551                         rte_zmalloc("intr_vec",
2552                                     dev->data->nb_rx_queues * sizeof(int), 0);
2553                 if (intr_handle->intr_vec == NULL) {
2554                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2555                                      " intr_vec", dev->data->nb_rx_queues);
2556                         return -ENOMEM;
2557                 }
2558         }
2559
2560         /* confiugre msix for sleep until rx interrupt */
2561         ixgbe_configure_msix(dev);
2562
2563         /* initialize transmission unit */
2564         ixgbe_dev_tx_init(dev);
2565
2566         /* This can fail when allocating mbufs for descriptor rings */
2567         err = ixgbe_dev_rx_init(dev);
2568         if (err) {
2569                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2570                 goto error;
2571         }
2572
2573     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2574                 ETH_VLAN_EXTEND_MASK;
2575         ixgbe_vlan_offload_set(dev, mask);
2576
2577         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2578                 /* Enable vlan filtering for VMDq */
2579                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2580         }
2581
2582         /* Configure DCB hw */
2583         ixgbe_configure_dcb(dev);
2584
2585         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2586                 err = ixgbe_fdir_configure(dev);
2587                 if (err)
2588                         goto error;
2589         }
2590
2591         /* Restore vf rate limit */
2592         if (vfinfo != NULL) {
2593                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2594                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2595                                 if (vfinfo[vf].tx_rate[idx] != 0)
2596                                         ixgbe_set_vf_rate_limit(
2597                                                 dev, vf,
2598                                                 vfinfo[vf].tx_rate[idx],
2599                                                 1 << idx);
2600         }
2601
2602         ixgbe_restore_statistics_mapping(dev);
2603
2604         err = ixgbe_dev_rxtx_start(dev);
2605         if (err < 0) {
2606                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2607                 goto error;
2608         }
2609
2610         /* Skip link setup if loopback mode is enabled for 82599. */
2611         if (hw->mac.type == ixgbe_mac_82599EB &&
2612                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2613                 goto skip_link_setup;
2614
2615         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2616                 err = hw->mac.ops.setup_sfp(hw);
2617                 if (err)
2618                         goto error;
2619         }
2620
2621         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2622                 /* Turn on the copper */
2623                 ixgbe_set_phy_power(hw, true);
2624         } else {
2625                 /* Turn on the laser */
2626                 ixgbe_enable_tx_laser(hw);
2627         }
2628
2629         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2630         if (err)
2631                 goto error;
2632         dev->data->dev_link.link_status = link_up;
2633
2634         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2635         if (err)
2636                 goto error;
2637
2638         link_speeds = &dev->data->dev_conf.link_speeds;
2639         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2640                         ETH_LINK_SPEED_10G)) {
2641                 PMD_INIT_LOG(ERR, "Invalid link setting");
2642                 goto error;
2643         }
2644
2645         speed = 0x0;
2646         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2647                 switch (hw->mac.type) {
2648                 case ixgbe_mac_82598EB:
2649                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2650                         break;
2651                 case ixgbe_mac_82599EB:
2652                 case ixgbe_mac_X540:
2653                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2654                         break;
2655                 case ixgbe_mac_X550:
2656                 case ixgbe_mac_X550EM_x:
2657                 case ixgbe_mac_X550EM_a:
2658                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2659                         break;
2660                 default:
2661                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2662                 }
2663         } else {
2664                 if (*link_speeds & ETH_LINK_SPEED_10G)
2665                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2666                 if (*link_speeds & ETH_LINK_SPEED_1G)
2667                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2668                 if (*link_speeds & ETH_LINK_SPEED_100M)
2669                         speed |= IXGBE_LINK_SPEED_100_FULL;
2670         }
2671
2672         err = ixgbe_setup_link(hw, speed, link_up);
2673         if (err)
2674                 goto error;
2675
2676 skip_link_setup:
2677
2678         if (rte_intr_allow_others(intr_handle)) {
2679                 /* check if lsc interrupt is enabled */
2680                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2681                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2682                 else
2683                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2684                 ixgbe_dev_macsec_interrupt_setup(dev);
2685         } else {
2686                 rte_intr_callback_unregister(intr_handle,
2687                                              ixgbe_dev_interrupt_handler, dev);
2688                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2689                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2690                                      " no intr multiplex");
2691         }
2692
2693         /* check if rxq interrupt is enabled */
2694         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2695             rte_intr_dp_is_en(intr_handle))
2696                 ixgbe_dev_rxq_interrupt_setup(dev);
2697
2698         /* enable uio/vfio intr/eventfd mapping */
2699         rte_intr_enable(intr_handle);
2700
2701         /* resume enabled intr since hw reset */
2702         ixgbe_enable_intr(dev);
2703         ixgbe_l2_tunnel_conf(dev);
2704         ixgbe_filter_restore(dev);
2705
2706         if (tm_conf->root && !tm_conf->committed)
2707                 PMD_DRV_LOG(WARNING,
2708                             "please call hierarchy_commit() "
2709                             "before starting the port");
2710
2711         return 0;
2712
2713 error:
2714         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2715         ixgbe_dev_clear_queues(dev);
2716         return -EIO;
2717 }
2718
2719 /*
2720  * Stop device: disable rx and tx functions to allow for reconfiguring.
2721  */
2722 static void
2723 ixgbe_dev_stop(struct rte_eth_dev *dev)
2724 {
2725         struct rte_eth_link link;
2726         struct ixgbe_hw *hw =
2727                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2728         struct ixgbe_vf_info *vfinfo =
2729                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2730         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2731         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2732         int vf;
2733         struct ixgbe_tm_conf *tm_conf =
2734                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2735
2736         PMD_INIT_FUNC_TRACE();
2737
2738         /* disable interrupts */
2739         ixgbe_disable_intr(hw);
2740
2741         /* reset the NIC */
2742         ixgbe_pf_reset_hw(hw);
2743         hw->adapter_stopped = 0;
2744
2745         /* stop adapter */
2746         ixgbe_stop_adapter(hw);
2747
2748         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2749                 vfinfo[vf].clear_to_send = false;
2750
2751         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2752                 /* Turn off the copper */
2753                 ixgbe_set_phy_power(hw, false);
2754         } else {
2755                 /* Turn off the laser */
2756                 ixgbe_disable_tx_laser(hw);
2757         }
2758
2759         ixgbe_dev_clear_queues(dev);
2760
2761         /* Clear stored conf */
2762         dev->data->scattered_rx = 0;
2763         dev->data->lro = 0;
2764
2765         /* Clear recorded link status */
2766         memset(&link, 0, sizeof(link));
2767         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2768
2769         if (!rte_intr_allow_others(intr_handle))
2770                 /* resume to the default handler */
2771                 rte_intr_callback_register(intr_handle,
2772                                            ixgbe_dev_interrupt_handler,
2773                                            (void *)dev);
2774
2775         /* Clean datapath event and queue/vec mapping */
2776         rte_intr_efd_disable(intr_handle);
2777         if (intr_handle->intr_vec != NULL) {
2778                 rte_free(intr_handle->intr_vec);
2779                 intr_handle->intr_vec = NULL;
2780         }
2781
2782         /* reset hierarchy commit */
2783         tm_conf->committed = false;
2784 }
2785
2786 /*
2787  * Set device link up: enable tx.
2788  */
2789 static int
2790 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2791 {
2792         struct ixgbe_hw *hw =
2793                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794         if (hw->mac.type == ixgbe_mac_82599EB) {
2795 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2796                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2797                         /* Not suported in bypass mode */
2798                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2799                                      "by device id 0x%x", hw->device_id);
2800                         return -ENOTSUP;
2801                 }
2802 #endif
2803         }
2804
2805         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2806                 /* Turn on the copper */
2807                 ixgbe_set_phy_power(hw, true);
2808         } else {
2809                 /* Turn on the laser */
2810                 ixgbe_enable_tx_laser(hw);
2811         }
2812
2813         return 0;
2814 }
2815
2816 /*
2817  * Set device link down: disable tx.
2818  */
2819 static int
2820 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2821 {
2822         struct ixgbe_hw *hw =
2823                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2824         if (hw->mac.type == ixgbe_mac_82599EB) {
2825 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2826                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2827                         /* Not suported in bypass mode */
2828                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2829                                      "by device id 0x%x", hw->device_id);
2830                         return -ENOTSUP;
2831                 }
2832 #endif
2833         }
2834
2835         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2836                 /* Turn off the copper */
2837                 ixgbe_set_phy_power(hw, false);
2838         } else {
2839                 /* Turn off the laser */
2840                 ixgbe_disable_tx_laser(hw);
2841         }
2842
2843         return 0;
2844 }
2845
2846 /*
2847  * Reset and stop device.
2848  */
2849 static void
2850 ixgbe_dev_close(struct rte_eth_dev *dev)
2851 {
2852         struct ixgbe_hw *hw =
2853                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854
2855         PMD_INIT_FUNC_TRACE();
2856
2857         ixgbe_pf_reset_hw(hw);
2858
2859         ixgbe_dev_stop(dev);
2860         hw->adapter_stopped = 1;
2861
2862         ixgbe_dev_free_queues(dev);
2863
2864         ixgbe_disable_pcie_master(hw);
2865
2866         /* reprogram the RAR[0] in case user changed it. */
2867         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2868 }
2869
2870 /*
2871  * Reset PF device.
2872  */
2873 static int
2874 ixgbe_dev_reset(struct rte_eth_dev *dev)
2875 {
2876         int ret;
2877
2878         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2879          * its VF to make them align with it. The detailed notification
2880          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2881          * To avoid unexpected behavior in VF, currently reset of PF with
2882          * SR-IOV activation is not supported. It might be supported later.
2883          */
2884         if (dev->data->sriov.active)
2885                 return -ENOTSUP;
2886
2887         ret = eth_ixgbe_dev_uninit(dev);
2888         if (ret)
2889                 return ret;
2890
2891         ret = eth_ixgbe_dev_init(dev);
2892
2893         return ret;
2894 }
2895
2896 static void
2897 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2898                            struct ixgbe_hw_stats *hw_stats,
2899                            struct ixgbe_macsec_stats *macsec_stats,
2900                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2901                            uint64_t *total_qprc, uint64_t *total_qprdc)
2902 {
2903         uint32_t bprc, lxon, lxoff, total;
2904         uint32_t delta_gprc = 0;
2905         unsigned i;
2906         /* Workaround for RX byte count not including CRC bytes when CRC
2907          * strip is enabled. CRC bytes are removed from counters when crc_strip
2908          * is disabled.
2909          */
2910         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2911                         IXGBE_HLREG0_RXCRCSTRP);
2912
2913         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2914         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2915         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2916         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2917
2918         for (i = 0; i < 8; i++) {
2919                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2920
2921                 /* global total per queue */
2922                 hw_stats->mpc[i] += mp;
2923                 /* Running comprehensive total for stats display */
2924                 *total_missed_rx += hw_stats->mpc[i];
2925                 if (hw->mac.type == ixgbe_mac_82598EB) {
2926                         hw_stats->rnbc[i] +=
2927                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2928                         hw_stats->pxonrxc[i] +=
2929                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2930                         hw_stats->pxoffrxc[i] +=
2931                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2932                 } else {
2933                         hw_stats->pxonrxc[i] +=
2934                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2935                         hw_stats->pxoffrxc[i] +=
2936                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2937                         hw_stats->pxon2offc[i] +=
2938                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2939                 }
2940                 hw_stats->pxontxc[i] +=
2941                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2942                 hw_stats->pxofftxc[i] +=
2943                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2944         }
2945         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2946                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2947                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2948                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2949
2950                 delta_gprc += delta_qprc;
2951
2952                 hw_stats->qprc[i] += delta_qprc;
2953                 hw_stats->qptc[i] += delta_qptc;
2954
2955                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2956                 hw_stats->qbrc[i] +=
2957                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2958                 if (crc_strip == 0)
2959                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2960
2961                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2962                 hw_stats->qbtc[i] +=
2963                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2964
2965                 hw_stats->qprdc[i] += delta_qprdc;
2966                 *total_qprdc += hw_stats->qprdc[i];
2967
2968                 *total_qprc += hw_stats->qprc[i];
2969                 *total_qbrc += hw_stats->qbrc[i];
2970         }
2971         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2972         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2973         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2974
2975         /*
2976          * An errata states that gprc actually counts good + missed packets:
2977          * Workaround to set gprc to summated queue packet receives
2978          */
2979         hw_stats->gprc = *total_qprc;
2980
2981         if (hw->mac.type != ixgbe_mac_82598EB) {
2982                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2983                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2984                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2985                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2986                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2987                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2988                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2989                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2990         } else {
2991                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2992                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2993                 /* 82598 only has a counter in the high register */
2994                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2995                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2996                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2997         }
2998         uint64_t old_tpr = hw_stats->tpr;
2999
3000         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3001         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3002
3003         if (crc_strip == 0)
3004                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3005
3006         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3007         hw_stats->gptc += delta_gptc;
3008         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3009         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3010
3011         /*
3012          * Workaround: mprc hardware is incorrectly counting
3013          * broadcasts, so for now we subtract those.
3014          */
3015         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3016         hw_stats->bprc += bprc;
3017         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3018         if (hw->mac.type == ixgbe_mac_82598EB)
3019                 hw_stats->mprc -= bprc;
3020
3021         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3022         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3023         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3024         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3025         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3026         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3027
3028         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3029         hw_stats->lxontxc += lxon;
3030         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3031         hw_stats->lxofftxc += lxoff;
3032         total = lxon + lxoff;
3033
3034         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3035         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3036         hw_stats->gptc -= total;
3037         hw_stats->mptc -= total;
3038         hw_stats->ptc64 -= total;
3039         hw_stats->gotc -= total * ETHER_MIN_LEN;
3040
3041         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3042         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3043         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3044         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3045         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3046         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3047         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3048         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3049         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3050         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3051         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3052         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3053         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3054         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3055         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3056         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3057         /* Only read FCOE on 82599 */
3058         if (hw->mac.type != ixgbe_mac_82598EB) {
3059                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3060                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3061                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3062                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3063                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3064         }
3065
3066         /* Flow Director Stats registers */
3067         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3068         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3069
3070         /* MACsec Stats registers */
3071         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3072         macsec_stats->out_pkts_encrypted +=
3073                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3074         macsec_stats->out_pkts_protected +=
3075                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3076         macsec_stats->out_octets_encrypted +=
3077                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3078         macsec_stats->out_octets_protected +=
3079                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3080         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3081         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3082         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3083         macsec_stats->in_pkts_unknownsci +=
3084                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3085         macsec_stats->in_octets_decrypted +=
3086                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3087         macsec_stats->in_octets_validated +=
3088                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3089         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3090         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3091         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3092         for (i = 0; i < 2; i++) {
3093                 macsec_stats->in_pkts_ok +=
3094                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3095                 macsec_stats->in_pkts_invalid +=
3096                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3097                 macsec_stats->in_pkts_notvalid +=
3098                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3099         }
3100         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3101         macsec_stats->in_pkts_notusingsa +=
3102                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3103 }
3104
3105 /*
3106  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3107  */
3108 static int
3109 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3110 {
3111         struct ixgbe_hw *hw =
3112                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3113         struct ixgbe_hw_stats *hw_stats =
3114                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3115         struct ixgbe_macsec_stats *macsec_stats =
3116                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3117                                 dev->data->dev_private);
3118         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3119         unsigned i;
3120
3121         total_missed_rx = 0;
3122         total_qbrc = 0;
3123         total_qprc = 0;
3124         total_qprdc = 0;
3125
3126         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3127                         &total_qbrc, &total_qprc, &total_qprdc);
3128
3129         if (stats == NULL)
3130                 return -EINVAL;
3131
3132         /* Fill out the rte_eth_stats statistics structure */
3133         stats->ipackets = total_qprc;
3134         stats->ibytes = total_qbrc;
3135         stats->opackets = hw_stats->gptc;
3136         stats->obytes = hw_stats->gotc;
3137
3138         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3139                 stats->q_ipackets[i] = hw_stats->qprc[i];
3140                 stats->q_opackets[i] = hw_stats->qptc[i];
3141                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3142                 stats->q_obytes[i] = hw_stats->qbtc[i];
3143                 stats->q_errors[i] = hw_stats->qprdc[i];
3144         }
3145
3146         /* Rx Errors */
3147         stats->imissed  = total_missed_rx;
3148         stats->ierrors  = hw_stats->crcerrs +
3149                           hw_stats->mspdc +
3150                           hw_stats->rlec +
3151                           hw_stats->ruc +
3152                           hw_stats->roc +
3153                           hw_stats->illerrc +
3154                           hw_stats->errbc +
3155                           hw_stats->rfc +
3156                           hw_stats->fccrc +
3157                           hw_stats->fclast;
3158
3159         /* Tx Errors */
3160         stats->oerrors  = 0;
3161         return 0;
3162 }
3163
3164 static void
3165 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3166 {
3167         struct ixgbe_hw_stats *stats =
3168                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3169
3170         /* HW registers are cleared on read */
3171         ixgbe_dev_stats_get(dev, NULL);
3172
3173         /* Reset software totals */
3174         memset(stats, 0, sizeof(*stats));
3175 }
3176
3177 /* This function calculates the number of xstats based on the current config */
3178 static unsigned
3179 ixgbe_xstats_calc_num(void) {
3180         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3181                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3182                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3183 }
3184
3185 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3186         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3187 {
3188         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3189         unsigned stat, i, count;
3190
3191         if (xstats_names != NULL) {
3192                 count = 0;
3193
3194                 /* Note: limit >= cnt_stats checked upstream
3195                  * in rte_eth_xstats_names()
3196                  */
3197
3198                 /* Extended stats from ixgbe_hw_stats */
3199                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3200                         snprintf(xstats_names[count].name,
3201                                 sizeof(xstats_names[count].name),
3202                                 "%s",
3203                                 rte_ixgbe_stats_strings[i].name);
3204                         count++;
3205                 }
3206
3207                 /* MACsec Stats */
3208                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3209                         snprintf(xstats_names[count].name,
3210                                 sizeof(xstats_names[count].name),
3211                                 "%s",
3212                                 rte_ixgbe_macsec_strings[i].name);
3213                         count++;
3214                 }
3215
3216                 /* RX Priority Stats */
3217                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3218                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3219                                 snprintf(xstats_names[count].name,
3220                                         sizeof(xstats_names[count].name),
3221                                         "rx_priority%u_%s", i,
3222                                         rte_ixgbe_rxq_strings[stat].name);
3223                                 count++;
3224                         }
3225                 }
3226
3227                 /* TX Priority Stats */
3228                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3229                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3230                                 snprintf(xstats_names[count].name,
3231                                         sizeof(xstats_names[count].name),
3232                                         "tx_priority%u_%s", i,
3233                                         rte_ixgbe_txq_strings[stat].name);
3234                                 count++;
3235                         }
3236                 }
3237         }
3238         return cnt_stats;
3239 }
3240
3241 static int ixgbe_dev_xstats_get_names_by_id(
3242         struct rte_eth_dev *dev,
3243         struct rte_eth_xstat_name *xstats_names,
3244         const uint64_t *ids,
3245         unsigned int limit)
3246 {
3247         if (!ids) {
3248                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3249                 unsigned int stat, i, count;
3250
3251                 if (xstats_names != NULL) {
3252                         count = 0;
3253
3254                         /* Note: limit >= cnt_stats checked upstream
3255                          * in rte_eth_xstats_names()
3256                          */
3257
3258                         /* Extended stats from ixgbe_hw_stats */
3259                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3260                                 snprintf(xstats_names[count].name,
3261                                         sizeof(xstats_names[count].name),
3262                                         "%s",
3263                                         rte_ixgbe_stats_strings[i].name);
3264                                 count++;
3265                         }
3266
3267                         /* MACsec Stats */
3268                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3269                                 snprintf(xstats_names[count].name,
3270                                         sizeof(xstats_names[count].name),
3271                                         "%s",
3272                                         rte_ixgbe_macsec_strings[i].name);
3273                                 count++;
3274                         }
3275
3276                         /* RX Priority Stats */
3277                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3278                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3279                                         snprintf(xstats_names[count].name,
3280                                             sizeof(xstats_names[count].name),
3281                                             "rx_priority%u_%s", i,
3282                                             rte_ixgbe_rxq_strings[stat].name);
3283                                         count++;
3284                                 }
3285                         }
3286
3287                         /* TX Priority Stats */
3288                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3289                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3290                                         snprintf(xstats_names[count].name,
3291                                             sizeof(xstats_names[count].name),
3292                                             "tx_priority%u_%s", i,
3293                                             rte_ixgbe_txq_strings[stat].name);
3294                                         count++;
3295                                 }
3296                         }
3297                 }
3298                 return cnt_stats;
3299         }
3300
3301         uint16_t i;
3302         uint16_t size = ixgbe_xstats_calc_num();
3303         struct rte_eth_xstat_name xstats_names_copy[size];
3304
3305         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3306                         size);
3307
3308         for (i = 0; i < limit; i++) {
3309                 if (ids[i] >= size) {
3310                         PMD_INIT_LOG(ERR, "id value isn't valid");
3311                         return -1;
3312                 }
3313                 strcpy(xstats_names[i].name,
3314                                 xstats_names_copy[ids[i]].name);
3315         }
3316         return limit;
3317 }
3318
3319 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3320         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3321 {
3322         unsigned i;
3323
3324         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3325                 return -ENOMEM;
3326
3327         if (xstats_names != NULL)
3328                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3329                         snprintf(xstats_names[i].name,
3330                                 sizeof(xstats_names[i].name),
3331                                 "%s", rte_ixgbevf_stats_strings[i].name);
3332         return IXGBEVF_NB_XSTATS;
3333 }
3334
3335 static int
3336 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3337                                          unsigned n)
3338 {
3339         struct ixgbe_hw *hw =
3340                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3341         struct ixgbe_hw_stats *hw_stats =
3342                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3343         struct ixgbe_macsec_stats *macsec_stats =
3344                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3345                                 dev->data->dev_private);
3346         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3347         unsigned i, stat, count = 0;
3348
3349         count = ixgbe_xstats_calc_num();
3350
3351         if (n < count)
3352                 return count;
3353
3354         total_missed_rx = 0;
3355         total_qbrc = 0;
3356         total_qprc = 0;
3357         total_qprdc = 0;
3358
3359         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3360                         &total_qbrc, &total_qprc, &total_qprdc);
3361
3362         /* If this is a reset xstats is NULL, and we have cleared the
3363          * registers by reading them.
3364          */
3365         if (!xstats)
3366                 return 0;
3367
3368         /* Extended stats from ixgbe_hw_stats */
3369         count = 0;
3370         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3371                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3372                                 rte_ixgbe_stats_strings[i].offset);
3373                 xstats[count].id = count;
3374                 count++;
3375         }
3376
3377         /* MACsec Stats */
3378         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3379                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3380                                 rte_ixgbe_macsec_strings[i].offset);
3381                 xstats[count].id = count;
3382                 count++;
3383         }
3384
3385         /* RX Priority Stats */
3386         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3387                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3388                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3389                                         rte_ixgbe_rxq_strings[stat].offset +
3390                                         (sizeof(uint64_t) * i));
3391                         xstats[count].id = count;
3392                         count++;
3393                 }
3394         }
3395
3396         /* TX Priority Stats */
3397         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3398                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3399                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3400                                         rte_ixgbe_txq_strings[stat].offset +
3401                                         (sizeof(uint64_t) * i));
3402                         xstats[count].id = count;
3403                         count++;
3404                 }
3405         }
3406         return count;
3407 }
3408
3409 static int
3410 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3411                 uint64_t *values, unsigned int n)
3412 {
3413         if (!ids) {
3414                 struct ixgbe_hw *hw =
3415                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3416                 struct ixgbe_hw_stats *hw_stats =
3417                                 IXGBE_DEV_PRIVATE_TO_STATS(
3418                                                 dev->data->dev_private);
3419                 struct ixgbe_macsec_stats *macsec_stats =
3420                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3421                                         dev->data->dev_private);
3422                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3423                 unsigned int i, stat, count = 0;
3424
3425                 count = ixgbe_xstats_calc_num();
3426
3427                 if (!ids && n < count)
3428                         return count;
3429
3430                 total_missed_rx = 0;
3431                 total_qbrc = 0;
3432                 total_qprc = 0;
3433                 total_qprdc = 0;
3434
3435                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3436                                 &total_missed_rx, &total_qbrc, &total_qprc,
3437                                 &total_qprdc);
3438
3439                 /* If this is a reset xstats is NULL, and we have cleared the
3440                  * registers by reading them.
3441                  */
3442                 if (!ids && !values)
3443                         return 0;
3444
3445                 /* Extended stats from ixgbe_hw_stats */
3446                 count = 0;
3447                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3448                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3449                                         rte_ixgbe_stats_strings[i].offset);
3450                         count++;
3451                 }
3452
3453                 /* MACsec Stats */
3454                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3455                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3456                                         rte_ixgbe_macsec_strings[i].offset);
3457                         count++;
3458                 }
3459
3460                 /* RX Priority Stats */
3461                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3462                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3463                                 values[count] =
3464                                         *(uint64_t *)(((char *)hw_stats) +
3465                                         rte_ixgbe_rxq_strings[stat].offset +
3466                                         (sizeof(uint64_t) * i));
3467                                 count++;
3468                         }
3469                 }
3470
3471                 /* TX Priority Stats */
3472                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3473                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3474                                 values[count] =
3475                                         *(uint64_t *)(((char *)hw_stats) +
3476                                         rte_ixgbe_txq_strings[stat].offset +
3477                                         (sizeof(uint64_t) * i));
3478                                 count++;
3479                         }
3480                 }
3481                 return count;
3482         }
3483
3484         uint16_t i;
3485         uint16_t size = ixgbe_xstats_calc_num();
3486         uint64_t values_copy[size];
3487
3488         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3489
3490         for (i = 0; i < n; i++) {
3491                 if (ids[i] >= size) {
3492                         PMD_INIT_LOG(ERR, "id value isn't valid");
3493                         return -1;
3494                 }
3495                 values[i] = values_copy[ids[i]];
3496         }
3497         return n;
3498 }
3499
3500 static void
3501 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3502 {
3503         struct ixgbe_hw_stats *stats =
3504                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3505         struct ixgbe_macsec_stats *macsec_stats =
3506                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3507                                 dev->data->dev_private);
3508
3509         unsigned count = ixgbe_xstats_calc_num();
3510
3511         /* HW registers are cleared on read */
3512         ixgbe_dev_xstats_get(dev, NULL, count);
3513
3514         /* Reset software totals */
3515         memset(stats, 0, sizeof(*stats));
3516         memset(macsec_stats, 0, sizeof(*macsec_stats));
3517 }
3518
3519 static void
3520 ixgbevf_update_stats(struct rte_eth_dev *dev)
3521 {
3522         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3523         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3524                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3525
3526         /* Good Rx packet, include VF loopback */
3527         UPDATE_VF_STAT(IXGBE_VFGPRC,
3528             hw_stats->last_vfgprc, hw_stats->vfgprc);
3529
3530         /* Good Rx octets, include VF loopback */
3531         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3532             hw_stats->last_vfgorc, hw_stats->vfgorc);
3533
3534         /* Good Tx packet, include VF loopback */
3535         UPDATE_VF_STAT(IXGBE_VFGPTC,
3536             hw_stats->last_vfgptc, hw_stats->vfgptc);
3537
3538         /* Good Tx octets, include VF loopback */
3539         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3540             hw_stats->last_vfgotc, hw_stats->vfgotc);
3541
3542         /* Rx Multicst Packet */
3543         UPDATE_VF_STAT(IXGBE_VFMPRC,
3544             hw_stats->last_vfmprc, hw_stats->vfmprc);
3545 }
3546
3547 static int
3548 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3549                        unsigned n)
3550 {
3551         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3552                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3553         unsigned i;
3554
3555         if (n < IXGBEVF_NB_XSTATS)
3556                 return IXGBEVF_NB_XSTATS;
3557
3558         ixgbevf_update_stats(dev);
3559
3560         if (!xstats)
3561                 return 0;
3562
3563         /* Extended stats */
3564         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3565                 xstats[i].id = i;
3566                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3567                         rte_ixgbevf_stats_strings[i].offset);
3568         }
3569
3570         return IXGBEVF_NB_XSTATS;
3571 }
3572
3573 static int
3574 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3575 {
3576         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3577                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3578
3579         ixgbevf_update_stats(dev);
3580
3581         if (stats == NULL)
3582                 return -EINVAL;
3583
3584         stats->ipackets = hw_stats->vfgprc;
3585         stats->ibytes = hw_stats->vfgorc;
3586         stats->opackets = hw_stats->vfgptc;
3587         stats->obytes = hw_stats->vfgotc;
3588         return 0;
3589 }
3590
3591 static void
3592 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3593 {
3594         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3595                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3596
3597         /* Sync HW register to the last stats */
3598         ixgbevf_dev_stats_get(dev, NULL);
3599
3600         /* reset HW current stats*/
3601         hw_stats->vfgprc = 0;
3602         hw_stats->vfgorc = 0;
3603         hw_stats->vfgptc = 0;
3604         hw_stats->vfgotc = 0;
3605 }
3606
3607 static int
3608 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3609 {
3610         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3611         u16 eeprom_verh, eeprom_verl;
3612         u32 etrack_id;
3613         int ret;
3614
3615         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3616         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3617
3618         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3619         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3620
3621         ret += 1; /* add the size of '\0' */
3622         if (fw_size < (u32)ret)
3623                 return ret;
3624         else
3625                 return 0;
3626 }
3627
3628 static void
3629 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3630 {
3631         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3632         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3633         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3634
3635         dev_info->pci_dev = pci_dev;
3636         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3637         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3638         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3639                 /*
3640                  * When DCB/VT is off, maximum number of queues changes,
3641                  * except for 82598EB, which remains constant.
3642                  */
3643                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3644                                 hw->mac.type != ixgbe_mac_82598EB)
3645                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3646         }
3647         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3648         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3649         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3650         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3651         dev_info->max_vfs = pci_dev->max_vfs;
3652         if (hw->mac.type == ixgbe_mac_82598EB)
3653                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3654         else
3655                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3656         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3657         dev_info->rx_offload_capa =
3658                 DEV_RX_OFFLOAD_VLAN_STRIP |
3659                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3660                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3661                 DEV_RX_OFFLOAD_TCP_CKSUM;
3662
3663         /*
3664          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3665          * mode.
3666          */
3667         if ((hw->mac.type == ixgbe_mac_82599EB ||
3668              hw->mac.type == ixgbe_mac_X540) &&
3669             !RTE_ETH_DEV_SRIOV(dev).active)
3670                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3671
3672         if (hw->mac.type == ixgbe_mac_82599EB ||
3673             hw->mac.type == ixgbe_mac_X540)
3674                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3675
3676         if (hw->mac.type == ixgbe_mac_X550 ||
3677             hw->mac.type == ixgbe_mac_X550EM_x ||
3678             hw->mac.type == ixgbe_mac_X550EM_a)
3679                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3680
3681         dev_info->tx_offload_capa =
3682                 DEV_TX_OFFLOAD_VLAN_INSERT |
3683                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3684                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3685                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3686                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3687                 DEV_TX_OFFLOAD_TCP_TSO;
3688
3689         if (hw->mac.type == ixgbe_mac_82599EB ||
3690             hw->mac.type == ixgbe_mac_X540)
3691                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3692
3693         if (hw->mac.type == ixgbe_mac_X550 ||
3694             hw->mac.type == ixgbe_mac_X550EM_x ||
3695             hw->mac.type == ixgbe_mac_X550EM_a)
3696                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3697
3698         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3699                 .rx_thresh = {
3700                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3701                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3702                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3703                 },
3704                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3705                 .rx_drop_en = 0,
3706         };
3707
3708         dev_info->default_txconf = (struct rte_eth_txconf) {
3709                 .tx_thresh = {
3710                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3711                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3712                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3713                 },
3714                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3715                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3716                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3717                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3718         };
3719
3720         dev_info->rx_desc_lim = rx_desc_lim;
3721         dev_info->tx_desc_lim = tx_desc_lim;
3722
3723         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3724         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3725         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3726
3727         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3728         if (hw->mac.type == ixgbe_mac_X540 ||
3729             hw->mac.type == ixgbe_mac_X540_vf ||
3730             hw->mac.type == ixgbe_mac_X550 ||
3731             hw->mac.type == ixgbe_mac_X550_vf) {
3732                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3733         }
3734         if (hw->mac.type == ixgbe_mac_X550) {
3735                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3736                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3737         }
3738 }
3739
3740 static const uint32_t *
3741 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3742 {
3743         static const uint32_t ptypes[] = {
3744                 /* For non-vec functions,
3745                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3746                  * for vec functions,
3747                  * refers to _recv_raw_pkts_vec().
3748                  */
3749                 RTE_PTYPE_L2_ETHER,
3750                 RTE_PTYPE_L3_IPV4,
3751                 RTE_PTYPE_L3_IPV4_EXT,
3752                 RTE_PTYPE_L3_IPV6,
3753                 RTE_PTYPE_L3_IPV6_EXT,
3754                 RTE_PTYPE_L4_SCTP,
3755                 RTE_PTYPE_L4_TCP,
3756                 RTE_PTYPE_L4_UDP,
3757                 RTE_PTYPE_TUNNEL_IP,
3758                 RTE_PTYPE_INNER_L3_IPV6,
3759                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3760                 RTE_PTYPE_INNER_L4_TCP,
3761                 RTE_PTYPE_INNER_L4_UDP,
3762                 RTE_PTYPE_UNKNOWN
3763         };
3764
3765         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3766             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3767             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3768             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3769                 return ptypes;
3770
3771 #if defined(RTE_ARCH_X86)
3772         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3773             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3774                 return ptypes;
3775 #endif
3776         return NULL;
3777 }
3778
3779 static void
3780 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3781                      struct rte_eth_dev_info *dev_info)
3782 {
3783         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785
3786         dev_info->pci_dev = pci_dev;
3787         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3788         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3789         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3790         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3791         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3792         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3793         dev_info->max_vfs = pci_dev->max_vfs;
3794         if (hw->mac.type == ixgbe_mac_82598EB)
3795                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3796         else
3797                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3798         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3799                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3800                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3801                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3802         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3803                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3804                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3805                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3806                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3807                                 DEV_TX_OFFLOAD_TCP_TSO;
3808
3809         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3810                 .rx_thresh = {
3811                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3812                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3813                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3814                 },
3815                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3816                 .rx_drop_en = 0,
3817         };
3818
3819         dev_info->default_txconf = (struct rte_eth_txconf) {
3820                 .tx_thresh = {
3821                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3822                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3823                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3824                 },
3825                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3826                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3827                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3828                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3829         };
3830
3831         dev_info->rx_desc_lim = rx_desc_lim;
3832         dev_info->tx_desc_lim = tx_desc_lim;
3833 }
3834
3835 static int
3836 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3837                    int *link_up, int wait_to_complete)
3838 {
3839         /**
3840          * for a quick link status checking, wait_to_compelet == 0,
3841          * skip PF link status checking
3842          */
3843         bool no_pflink_check = wait_to_complete == 0;
3844         struct ixgbe_mbx_info *mbx = &hw->mbx;
3845         struct ixgbe_mac_info *mac = &hw->mac;
3846         uint32_t links_reg, in_msg;
3847         int ret_val = 0;
3848
3849         /* If we were hit with a reset drop the link */
3850         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3851                 mac->get_link_status = true;
3852
3853         if (!mac->get_link_status)
3854                 goto out;
3855
3856         /* if link status is down no point in checking to see if pf is up */
3857         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3858         if (!(links_reg & IXGBE_LINKS_UP))
3859                 goto out;
3860
3861         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3862          * before the link status is correct
3863          */
3864         if (mac->type == ixgbe_mac_82599_vf) {
3865                 int i;
3866
3867                 for (i = 0; i < 5; i++) {
3868                         rte_delay_us(100);
3869                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3870
3871                         if (!(links_reg & IXGBE_LINKS_UP))
3872                                 goto out;
3873                 }
3874         }
3875
3876         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3877         case IXGBE_LINKS_SPEED_10G_82599:
3878                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3879                 if (hw->mac.type >= ixgbe_mac_X550) {
3880                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3881                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3882                 }
3883                 break;
3884         case IXGBE_LINKS_SPEED_1G_82599:
3885                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3886                 break;
3887         case IXGBE_LINKS_SPEED_100_82599:
3888                 *speed = IXGBE_LINK_SPEED_100_FULL;
3889                 if (hw->mac.type == ixgbe_mac_X550) {
3890                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3891                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3892                 }
3893                 break;
3894         case IXGBE_LINKS_SPEED_10_X550EM_A:
3895                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3896                 /* Since Reserved in older MAC's */
3897                 if (hw->mac.type >= ixgbe_mac_X550)
3898                         *speed = IXGBE_LINK_SPEED_10_FULL;
3899                 break;
3900         default:
3901                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3902         }
3903
3904         if (no_pflink_check) {
3905                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3906                         mac->get_link_status = true;
3907                 else
3908                         mac->get_link_status = false;
3909
3910                 goto out;
3911         }
3912         /* if the read failed it could just be a mailbox collision, best wait
3913          * until we are called again and don't report an error
3914          */
3915         if (mbx->ops.read(hw, &in_msg, 1, 0))
3916                 goto out;
3917
3918         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3919                 /* msg is not CTS and is NACK we must have lost CTS status */
3920                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3921                         ret_val = -1;
3922                 goto out;
3923         }
3924
3925         /* the pf is talking, if we timed out in the past we reinit */
3926         if (!mbx->timeout) {
3927                 ret_val = -1;
3928                 goto out;
3929         }
3930
3931         /* if we passed all the tests above then the link is up and we no
3932          * longer need to check for link
3933          */
3934         mac->get_link_status = false;
3935
3936 out:
3937         *link_up = !mac->get_link_status;
3938         return ret_val;
3939 }
3940
3941 /* return 0 means link status changed, -1 means not changed */
3942 static int
3943 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3944                             int wait_to_complete, int vf)
3945 {
3946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947         struct rte_eth_link link, old;
3948         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3949         struct ixgbe_interrupt *intr =
3950                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3951         int link_up;
3952         int diag;
3953         u32 speed = 0;
3954         int wait = 1;
3955         bool autoneg = false;
3956
3957         link.link_status = ETH_LINK_DOWN;
3958         link.link_speed = 0;
3959         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3960         link.link_autoneg = ETH_LINK_AUTONEG;
3961         memset(&old, 0, sizeof(old));
3962         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3963
3964         hw->mac.get_link_status = true;
3965
3966         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3967                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3968                 speed = hw->phy.autoneg_advertised;
3969                 if (!speed)
3970                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3971                 ixgbe_setup_link(hw, speed, true);
3972         }
3973
3974         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3975         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3976                 wait = 0;
3977
3978         if (vf)
3979                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3980         else
3981                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3982
3983         if (diag != 0) {
3984                 link.link_speed = ETH_SPEED_NUM_100M;
3985                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3986                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3987                 if (link.link_status == old.link_status)
3988                         return -1;
3989                 return 0;
3990         }
3991
3992         if (link_up == 0) {
3993                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3994                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3995                 if (link.link_status == old.link_status)
3996                         return -1;
3997                 return 0;
3998         }
3999         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4000         link.link_status = ETH_LINK_UP;
4001         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4002
4003         switch (link_speed) {
4004         default:
4005         case IXGBE_LINK_SPEED_UNKNOWN:
4006                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4007                 link.link_speed = ETH_SPEED_NUM_100M;
4008                 break;
4009
4010         case IXGBE_LINK_SPEED_100_FULL:
4011                 link.link_speed = ETH_SPEED_NUM_100M;
4012                 break;
4013
4014         case IXGBE_LINK_SPEED_1GB_FULL:
4015                 link.link_speed = ETH_SPEED_NUM_1G;
4016                 break;
4017
4018         case IXGBE_LINK_SPEED_2_5GB_FULL:
4019                 link.link_speed = ETH_SPEED_NUM_2_5G;
4020                 break;
4021
4022         case IXGBE_LINK_SPEED_5GB_FULL:
4023                 link.link_speed = ETH_SPEED_NUM_5G;
4024                 break;
4025
4026         case IXGBE_LINK_SPEED_10GB_FULL:
4027                 link.link_speed = ETH_SPEED_NUM_10G;
4028                 break;
4029         }
4030         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4031
4032         if (link.link_status == old.link_status)
4033                 return -1;
4034
4035         return 0;
4036 }
4037
4038 static int
4039 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4040 {
4041         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4042 }
4043
4044 static int
4045 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4046 {
4047         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4048 }
4049
4050 static void
4051 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4052 {
4053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4054         uint32_t fctrl;
4055
4056         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4057         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4058         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4059 }
4060
4061 static void
4062 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4063 {
4064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4065         uint32_t fctrl;
4066
4067         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4068         fctrl &= (~IXGBE_FCTRL_UPE);
4069         if (dev->data->all_multicast == 1)
4070                 fctrl |= IXGBE_FCTRL_MPE;
4071         else
4072                 fctrl &= (~IXGBE_FCTRL_MPE);
4073         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4074 }
4075
4076 static void
4077 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4078 {
4079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4080         uint32_t fctrl;
4081
4082         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4083         fctrl |= IXGBE_FCTRL_MPE;
4084         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4085 }
4086
4087 static void
4088 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4089 {
4090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4091         uint32_t fctrl;
4092
4093         if (dev->data->promiscuous == 1)
4094                 return; /* must remain in all_multicast mode */
4095
4096         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4097         fctrl &= (~IXGBE_FCTRL_MPE);
4098         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4099 }
4100
4101 /**
4102  * It clears the interrupt causes and enables the interrupt.
4103  * It will be called once only during nic initialized.
4104  *
4105  * @param dev
4106  *  Pointer to struct rte_eth_dev.
4107  * @param on
4108  *  Enable or Disable.
4109  *
4110  * @return
4111  *  - On success, zero.
4112  *  - On failure, a negative value.
4113  */
4114 static int
4115 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4116 {
4117         struct ixgbe_interrupt *intr =
4118                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4119
4120         ixgbe_dev_link_status_print(dev);
4121         if (on)
4122                 intr->mask |= IXGBE_EICR_LSC;
4123         else
4124                 intr->mask &= ~IXGBE_EICR_LSC;
4125
4126         return 0;
4127 }
4128
4129 /**
4130  * It clears the interrupt causes and enables the interrupt.
4131  * It will be called once only during nic initialized.
4132  *
4133  * @param dev
4134  *  Pointer to struct rte_eth_dev.
4135  *
4136  * @return
4137  *  - On success, zero.
4138  *  - On failure, a negative value.
4139  */
4140 static int
4141 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4142 {
4143         struct ixgbe_interrupt *intr =
4144                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4145
4146         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4147
4148         return 0;
4149 }
4150
4151 /**
4152  * It clears the interrupt causes and enables the interrupt.
4153  * It will be called once only during nic initialized.
4154  *
4155  * @param dev
4156  *  Pointer to struct rte_eth_dev.
4157  *
4158  * @return
4159  *  - On success, zero.
4160  *  - On failure, a negative value.
4161  */
4162 static int
4163 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4164 {
4165         struct ixgbe_interrupt *intr =
4166                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4167
4168         intr->mask |= IXGBE_EICR_LINKSEC;
4169
4170         return 0;
4171 }
4172
4173 /*
4174  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4175  *
4176  * @param dev
4177  *  Pointer to struct rte_eth_dev.
4178  *
4179  * @return
4180  *  - On success, zero.
4181  *  - On failure, a negative value.
4182  */
4183 static int
4184 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4185 {
4186         uint32_t eicr;
4187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188         struct ixgbe_interrupt *intr =
4189                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4190
4191         /* clear all cause mask */
4192         ixgbe_disable_intr(hw);
4193
4194         /* read-on-clear nic registers here */
4195         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4196         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4197
4198         intr->flags = 0;
4199
4200         /* set flag for async link update */
4201         if (eicr & IXGBE_EICR_LSC)
4202                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4203
4204         if (eicr & IXGBE_EICR_MAILBOX)
4205                 intr->flags |= IXGBE_FLAG_MAILBOX;
4206
4207         if (eicr & IXGBE_EICR_LINKSEC)
4208                 intr->flags |= IXGBE_FLAG_MACSEC;
4209
4210         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4211             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4212             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4213                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4214
4215         return 0;
4216 }
4217
4218 /**
4219  * It gets and then prints the link status.
4220  *
4221  * @param dev
4222  *  Pointer to struct rte_eth_dev.
4223  *
4224  * @return
4225  *  - On success, zero.
4226  *  - On failure, a negative value.
4227  */
4228 static void
4229 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4230 {
4231         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4232         struct rte_eth_link link;
4233
4234         memset(&link, 0, sizeof(link));
4235         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4236         if (link.link_status) {
4237                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4238                                         (int)(dev->data->port_id),
4239                                         (unsigned)link.link_speed,
4240                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4241                                         "full-duplex" : "half-duplex");
4242         } else {
4243                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4244                                 (int)(dev->data->port_id));
4245         }
4246         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4247                                 pci_dev->addr.domain,
4248                                 pci_dev->addr.bus,
4249                                 pci_dev->addr.devid,
4250                                 pci_dev->addr.function);
4251 }
4252
4253 /*
4254  * It executes link_update after knowing an interrupt occurred.
4255  *
4256  * @param dev
4257  *  Pointer to struct rte_eth_dev.
4258  *
4259  * @return
4260  *  - On success, zero.
4261  *  - On failure, a negative value.
4262  */
4263 static int
4264 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4265                            struct rte_intr_handle *intr_handle)
4266 {
4267         struct ixgbe_interrupt *intr =
4268                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4269         int64_t timeout;
4270         struct rte_eth_link link;
4271         struct ixgbe_hw *hw =
4272                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4273
4274         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4275
4276         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4277                 ixgbe_pf_mbx_process(dev);
4278                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4279         }
4280
4281         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4282                 ixgbe_handle_lasi(hw);
4283                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4284         }
4285
4286         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4287                 /* get the link status before link update, for predicting later */
4288                 memset(&link, 0, sizeof(link));
4289                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4290
4291                 ixgbe_dev_link_update(dev, 0);
4292
4293                 /* likely to up */
4294                 if (!link.link_status)
4295                         /* handle it 1 sec later, wait it being stable */
4296                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4297                 /* likely to down */
4298                 else
4299                         /* handle it 4 sec later, wait it being stable */
4300                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4301
4302                 ixgbe_dev_link_status_print(dev);
4303                 if (rte_eal_alarm_set(timeout * 1000,
4304                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4305                         PMD_DRV_LOG(ERR, "Error setting alarm");
4306                 else {
4307                         /* remember original mask */
4308                         intr->mask_original = intr->mask;
4309                         /* only disable lsc interrupt */
4310                         intr->mask &= ~IXGBE_EIMS_LSC;
4311                 }
4312         }
4313
4314         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4315         ixgbe_enable_intr(dev);
4316         rte_intr_enable(intr_handle);
4317
4318         return 0;
4319 }
4320
4321 /**
4322  * Interrupt handler which shall be registered for alarm callback for delayed
4323  * handling specific interrupt to wait for the stable nic state. As the
4324  * NIC interrupt state is not stable for ixgbe after link is just down,
4325  * it needs to wait 4 seconds to get the stable status.
4326  *
4327  * @param handle
4328  *  Pointer to interrupt handle.
4329  * @param param
4330  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4331  *
4332  * @return
4333  *  void
4334  */
4335 static void
4336 ixgbe_dev_interrupt_delayed_handler(void *param)
4337 {
4338         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4339         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4341         struct ixgbe_interrupt *intr =
4342                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4343         struct ixgbe_hw *hw =
4344                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4345         uint32_t eicr;
4346
4347         ixgbe_disable_intr(hw);
4348
4349         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4350         if (eicr & IXGBE_EICR_MAILBOX)
4351                 ixgbe_pf_mbx_process(dev);
4352
4353         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4354                 ixgbe_handle_lasi(hw);
4355                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4356         }
4357
4358         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4359                 ixgbe_dev_link_update(dev, 0);
4360                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4361                 ixgbe_dev_link_status_print(dev);
4362                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4363                                               NULL, NULL);
4364         }
4365
4366         if (intr->flags & IXGBE_FLAG_MACSEC) {
4367                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4368                                               NULL, NULL);
4369                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4370         }
4371
4372         /* restore original mask */
4373         intr->mask = intr->mask_original;
4374         intr->mask_original = 0;
4375
4376         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4377         ixgbe_enable_intr(dev);
4378         rte_intr_enable(intr_handle);
4379 }
4380
4381 /**
4382  * Interrupt handler triggered by NIC  for handling
4383  * specific interrupt.
4384  *
4385  * @param handle
4386  *  Pointer to interrupt handle.
4387  * @param param
4388  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4389  *
4390  * @return
4391  *  void
4392  */
4393 static void
4394 ixgbe_dev_interrupt_handler(void *param)
4395 {
4396         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4397
4398         ixgbe_dev_interrupt_get_status(dev);
4399         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4400 }
4401
4402 static int
4403 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4404 {
4405         struct ixgbe_hw *hw;
4406
4407         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4408         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4409 }
4410
4411 static int
4412 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4413 {
4414         struct ixgbe_hw *hw;
4415
4416         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4417         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4418 }
4419
4420 static int
4421 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4422 {
4423         struct ixgbe_hw *hw;
4424         uint32_t mflcn_reg;
4425         uint32_t fccfg_reg;
4426         int rx_pause;
4427         int tx_pause;
4428
4429         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4430
4431         fc_conf->pause_time = hw->fc.pause_time;
4432         fc_conf->high_water = hw->fc.high_water[0];
4433         fc_conf->low_water = hw->fc.low_water[0];
4434         fc_conf->send_xon = hw->fc.send_xon;
4435         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4436
4437         /*
4438          * Return rx_pause status according to actual setting of
4439          * MFLCN register.
4440          */
4441         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4442         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4443                 rx_pause = 1;
4444         else
4445                 rx_pause = 0;
4446
4447         /*
4448          * Return tx_pause status according to actual setting of
4449          * FCCFG register.
4450          */
4451         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4452         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4453                 tx_pause = 1;
4454         else
4455                 tx_pause = 0;
4456
4457         if (rx_pause && tx_pause)
4458                 fc_conf->mode = RTE_FC_FULL;
4459         else if (rx_pause)
4460                 fc_conf->mode = RTE_FC_RX_PAUSE;
4461         else if (tx_pause)
4462                 fc_conf->mode = RTE_FC_TX_PAUSE;
4463         else
4464                 fc_conf->mode = RTE_FC_NONE;
4465
4466         return 0;
4467 }
4468
4469 static int
4470 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4471 {
4472         struct ixgbe_hw *hw;
4473         int err;
4474         uint32_t rx_buf_size;
4475         uint32_t max_high_water;
4476         uint32_t mflcn;
4477         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4478                 ixgbe_fc_none,
4479                 ixgbe_fc_rx_pause,
4480                 ixgbe_fc_tx_pause,
4481                 ixgbe_fc_full
4482         };
4483
4484         PMD_INIT_FUNC_TRACE();
4485
4486         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4487         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4488         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4489
4490         /*
4491          * At least reserve one Ethernet frame for watermark
4492          * high_water/low_water in kilo bytes for ixgbe
4493          */
4494         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4495         if ((fc_conf->high_water > max_high_water) ||
4496                 (fc_conf->high_water < fc_conf->low_water)) {
4497                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4498                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4499                 return -EINVAL;
4500         }
4501
4502         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4503         hw->fc.pause_time     = fc_conf->pause_time;
4504         hw->fc.high_water[0]  = fc_conf->high_water;
4505         hw->fc.low_water[0]   = fc_conf->low_water;
4506         hw->fc.send_xon       = fc_conf->send_xon;
4507         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4508
4509         err = ixgbe_fc_enable(hw);
4510
4511         /* Not negotiated is not an error case */
4512         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4513
4514                 /* check if we want to forward MAC frames - driver doesn't have native
4515                  * capability to do that, so we'll write the registers ourselves */
4516
4517                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4518
4519                 /* set or clear MFLCN.PMCF bit depending on configuration */
4520                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4521                         mflcn |= IXGBE_MFLCN_PMCF;
4522                 else
4523                         mflcn &= ~IXGBE_MFLCN_PMCF;
4524
4525                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4526                 IXGBE_WRITE_FLUSH(hw);
4527
4528                 return 0;
4529         }
4530
4531         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4532         return -EIO;
4533 }
4534
4535 /**
4536  *  ixgbe_pfc_enable_generic - Enable flow control
4537  *  @hw: pointer to hardware structure
4538  *  @tc_num: traffic class number
4539  *  Enable flow control according to the current settings.
4540  */
4541 static int
4542 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4543 {
4544         int ret_val = 0;
4545         uint32_t mflcn_reg, fccfg_reg;
4546         uint32_t reg;
4547         uint32_t fcrtl, fcrth;
4548         uint8_t i;
4549         uint8_t nb_rx_en;
4550
4551         /* Validate the water mark configuration */
4552         if (!hw->fc.pause_time) {
4553                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4554                 goto out;
4555         }
4556
4557         /* Low water mark of zero causes XOFF floods */
4558         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4559                  /* High/Low water can not be 0 */
4560                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4561                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4562                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4563                         goto out;
4564                 }
4565
4566                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4567                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4568                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4569                         goto out;
4570                 }
4571         }
4572         /* Negotiate the fc mode to use */
4573         ixgbe_fc_autoneg(hw);
4574
4575         /* Disable any previous flow control settings */
4576         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4577         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4578
4579         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4580         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4581
4582         switch (hw->fc.current_mode) {
4583         case ixgbe_fc_none:
4584                 /*
4585                  * If the count of enabled RX Priority Flow control >1,
4586                  * and the TX pause can not be disabled
4587                  */
4588                 nb_rx_en = 0;
4589                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4590                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4591                         if (reg & IXGBE_FCRTH_FCEN)
4592                                 nb_rx_en++;
4593                 }
4594                 if (nb_rx_en > 1)
4595                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4596                 break;
4597         case ixgbe_fc_rx_pause:
4598                 /*
4599                  * Rx Flow control is enabled and Tx Flow control is
4600                  * disabled by software override. Since there really
4601                  * isn't a way to advertise that we are capable of RX
4602                  * Pause ONLY, we will advertise that we support both
4603                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4604                  * disable the adapter's ability to send PAUSE frames.
4605                  */
4606                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4607                 /*
4608                  * If the count of enabled RX Priority Flow control >1,
4609                  * and the TX pause can not be disabled
4610                  */
4611                 nb_rx_en = 0;
4612                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4613                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4614                         if (reg & IXGBE_FCRTH_FCEN)
4615                                 nb_rx_en++;
4616                 }
4617                 if (nb_rx_en > 1)
4618                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4619                 break;
4620         case ixgbe_fc_tx_pause:
4621                 /*
4622                  * Tx Flow control is enabled, and Rx Flow control is
4623                  * disabled by software override.
4624                  */
4625                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4626                 break;
4627         case ixgbe_fc_full:
4628                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4629                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4630                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4631                 break;
4632         default:
4633                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4634                 ret_val = IXGBE_ERR_CONFIG;
4635                 goto out;
4636         }
4637
4638         /* Set 802.3x based flow control settings. */
4639         mflcn_reg |= IXGBE_MFLCN_DPF;
4640         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4641         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4642
4643         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4644         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4645                 hw->fc.high_water[tc_num]) {
4646                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4647                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4648                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4649         } else {
4650                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4651                 /*
4652                  * In order to prevent Tx hangs when the internal Tx
4653                  * switch is enabled we must set the high water mark
4654                  * to the maximum FCRTH value.  This allows the Tx
4655                  * switch to function even under heavy Rx workloads.
4656                  */
4657                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4658         }
4659         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4660
4661         /* Configure pause time (2 TCs per register) */
4662         reg = hw->fc.pause_time * 0x00010001;
4663         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4664                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4665
4666         /* Configure flow control refresh threshold value */
4667         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4668
4669 out:
4670         return ret_val;
4671 }
4672
4673 static int
4674 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4675 {
4676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4678
4679         if (hw->mac.type != ixgbe_mac_82598EB) {
4680                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4681         }
4682         return ret_val;
4683 }
4684
4685 static int
4686 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4687 {
4688         int err;
4689         uint32_t rx_buf_size;
4690         uint32_t max_high_water;
4691         uint8_t tc_num;
4692         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4693         struct ixgbe_hw *hw =
4694                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695         struct ixgbe_dcb_config *dcb_config =
4696                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4697
4698         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4699                 ixgbe_fc_none,
4700                 ixgbe_fc_rx_pause,
4701                 ixgbe_fc_tx_pause,
4702                 ixgbe_fc_full
4703         };
4704
4705         PMD_INIT_FUNC_TRACE();
4706
4707         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4708         tc_num = map[pfc_conf->priority];
4709         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4710         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4711         /*
4712          * At least reserve one Ethernet frame for watermark
4713          * high_water/low_water in kilo bytes for ixgbe
4714          */
4715         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4716         if ((pfc_conf->fc.high_water > max_high_water) ||
4717             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4718                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4719                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4720                 return -EINVAL;
4721         }
4722
4723         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4724         hw->fc.pause_time = pfc_conf->fc.pause_time;
4725         hw->fc.send_xon = pfc_conf->fc.send_xon;
4726         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4727         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4728
4729         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4730
4731         /* Not negotiated is not an error case */
4732         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4733                 return 0;
4734
4735         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4736         return -EIO;
4737 }
4738
4739 static int
4740 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4741                           struct rte_eth_rss_reta_entry64 *reta_conf,
4742                           uint16_t reta_size)
4743 {
4744         uint16_t i, sp_reta_size;
4745         uint8_t j, mask;
4746         uint32_t reta, r;
4747         uint16_t idx, shift;
4748         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4749         uint32_t reta_reg;
4750
4751         PMD_INIT_FUNC_TRACE();
4752
4753         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4754                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4755                         "NIC.");
4756                 return -ENOTSUP;
4757         }
4758
4759         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4760         if (reta_size != sp_reta_size) {
4761                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4762                         "(%d) doesn't match the number hardware can supported "
4763                         "(%d)", reta_size, sp_reta_size);
4764                 return -EINVAL;
4765         }
4766
4767         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4768                 idx = i / RTE_RETA_GROUP_SIZE;
4769                 shift = i % RTE_RETA_GROUP_SIZE;
4770                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4771                                                 IXGBE_4_BIT_MASK);
4772                 if (!mask)
4773                         continue;
4774                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4775                 if (mask == IXGBE_4_BIT_MASK)
4776                         r = 0;
4777                 else
4778                         r = IXGBE_READ_REG(hw, reta_reg);
4779                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4780                         if (mask & (0x1 << j))
4781                                 reta |= reta_conf[idx].reta[shift + j] <<
4782                                                         (CHAR_BIT * j);
4783                         else
4784                                 reta |= r & (IXGBE_8_BIT_MASK <<
4785                                                 (CHAR_BIT * j));
4786                 }
4787                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4788         }
4789
4790         return 0;
4791 }
4792
4793 static int
4794 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4795                          struct rte_eth_rss_reta_entry64 *reta_conf,
4796                          uint16_t reta_size)
4797 {
4798         uint16_t i, sp_reta_size;
4799         uint8_t j, mask;
4800         uint32_t reta;
4801         uint16_t idx, shift;
4802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4803         uint32_t reta_reg;
4804
4805         PMD_INIT_FUNC_TRACE();
4806         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4807         if (reta_size != sp_reta_size) {
4808                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4809                         "(%d) doesn't match the number hardware can supported "
4810                         "(%d)", reta_size, sp_reta_size);
4811                 return -EINVAL;
4812         }
4813
4814         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4815                 idx = i / RTE_RETA_GROUP_SIZE;
4816                 shift = i % RTE_RETA_GROUP_SIZE;
4817                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4818                                                 IXGBE_4_BIT_MASK);
4819                 if (!mask)
4820                         continue;
4821
4822                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4823                 reta = IXGBE_READ_REG(hw, reta_reg);
4824                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4825                         if (mask & (0x1 << j))
4826                                 reta_conf[idx].reta[shift + j] =
4827                                         ((reta >> (CHAR_BIT * j)) &
4828                                                 IXGBE_8_BIT_MASK);
4829                 }
4830         }
4831
4832         return 0;
4833 }
4834
4835 static int
4836 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4837                                 uint32_t index, uint32_t pool)
4838 {
4839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4840         uint32_t enable_addr = 1;
4841
4842         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4843                              pool, enable_addr);
4844 }
4845
4846 static void
4847 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4848 {
4849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850
4851         ixgbe_clear_rar(hw, index);
4852 }
4853
4854 static void
4855 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4856 {
4857         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4858
4859         ixgbe_remove_rar(dev, 0);
4860
4861         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4862 }
4863
4864 static bool
4865 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4866 {
4867         if (strcmp(dev->device->driver->name, drv->driver.name))
4868                 return false;
4869
4870         return true;
4871 }
4872
4873 bool
4874 is_ixgbe_supported(struct rte_eth_dev *dev)
4875 {
4876         return is_device_supported(dev, &rte_ixgbe_pmd);
4877 }
4878
4879 static int
4880 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4881 {
4882         uint32_t hlreg0;
4883         uint32_t maxfrs;
4884         struct ixgbe_hw *hw;
4885         struct rte_eth_dev_info dev_info;
4886         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4887         struct rte_eth_dev_data *dev_data = dev->data;
4888
4889         ixgbe_dev_info_get(dev, &dev_info);
4890
4891         /* check that mtu is within the allowed range */
4892         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4893                 return -EINVAL;
4894
4895         /* If device is started, refuse mtu that requires the support of
4896          * scattered packets when this feature has not been enabled before.
4897          */
4898         if (dev_data->dev_started && !dev_data->scattered_rx &&
4899             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4900              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4901                 PMD_INIT_LOG(ERR, "Stop port first.");
4902                 return -EINVAL;
4903         }
4904
4905         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4907
4908         /* switch to jumbo mode if needed */
4909         if (frame_size > ETHER_MAX_LEN) {
4910                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4911                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4912         } else {
4913                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4914                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4915         }
4916         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4917
4918         /* update max frame size */
4919         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4920
4921         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4922         maxfrs &= 0x0000FFFF;
4923         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4924         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4925
4926         return 0;
4927 }
4928
4929 /*
4930  * Virtual Function operations
4931  */
4932 static void
4933 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4934 {
4935         PMD_INIT_FUNC_TRACE();
4936
4937         /* Clear interrupt mask to stop from interrupts being generated */
4938         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4939
4940         IXGBE_WRITE_FLUSH(hw);
4941 }
4942
4943 static void
4944 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4945 {
4946         PMD_INIT_FUNC_TRACE();
4947
4948         /* VF enable interrupt autoclean */
4949         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4950         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4951         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4952
4953         IXGBE_WRITE_FLUSH(hw);
4954 }
4955
4956 static int
4957 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4958 {
4959         struct rte_eth_conf *conf = &dev->data->dev_conf;
4960         struct ixgbe_adapter *adapter =
4961                         (struct ixgbe_adapter *)dev->data->dev_private;
4962
4963         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4964                      dev->data->port_id);
4965
4966         /*
4967          * VF has no ability to enable/disable HW CRC
4968          * Keep the persistent behavior the same as Host PF
4969          */
4970 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4971         if (!conf->rxmode.hw_strip_crc) {
4972                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4973                 conf->rxmode.hw_strip_crc = 1;
4974         }
4975 #else
4976         if (conf->rxmode.hw_strip_crc) {
4977                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4978                 conf->rxmode.hw_strip_crc = 0;
4979         }
4980 #endif
4981
4982         /*
4983          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4984          * allocation or vector Rx preconditions we will reset it.
4985          */
4986         adapter->rx_bulk_alloc_allowed = true;
4987         adapter->rx_vec_allowed = true;
4988
4989         return 0;
4990 }
4991
4992 static int
4993 ixgbevf_dev_start(struct rte_eth_dev *dev)
4994 {
4995         struct ixgbe_hw *hw =
4996                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4997         uint32_t intr_vector = 0;
4998         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4999         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5000
5001         int err, mask = 0;
5002
5003         PMD_INIT_FUNC_TRACE();
5004
5005         hw->mac.ops.reset_hw(hw);
5006         hw->mac.get_link_status = true;
5007
5008         /* negotiate mailbox API version to use with the PF. */
5009         ixgbevf_negotiate_api(hw);
5010
5011         ixgbevf_dev_tx_init(dev);
5012
5013         /* This can fail when allocating mbufs for descriptor rings */
5014         err = ixgbevf_dev_rx_init(dev);
5015         if (err) {
5016                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5017                 ixgbe_dev_clear_queues(dev);
5018                 return err;
5019         }
5020
5021         /* Set vfta */
5022         ixgbevf_set_vfta_all(dev, 1);
5023
5024         /* Set HW strip */
5025         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5026                 ETH_VLAN_EXTEND_MASK;
5027         ixgbevf_vlan_offload_set(dev, mask);
5028
5029         ixgbevf_dev_rxtx_start(dev);
5030
5031         /* check and configure queue intr-vector mapping */
5032         if (dev->data->dev_conf.intr_conf.rxq != 0) {
5033                 /* According to datasheet, only vector 0/1/2 can be used,
5034                  * now only one vector is used for Rx queue
5035                  */
5036                 intr_vector = 1;
5037                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5038                         return -1;
5039         }
5040
5041         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5042                 intr_handle->intr_vec =
5043                         rte_zmalloc("intr_vec",
5044                                     dev->data->nb_rx_queues * sizeof(int), 0);
5045                 if (intr_handle->intr_vec == NULL) {
5046                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5047                                      " intr_vec", dev->data->nb_rx_queues);
5048                         return -ENOMEM;
5049                 }
5050         }
5051         ixgbevf_configure_msix(dev);
5052
5053         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5054          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5055          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5056          * is not cleared, it will fail when following rte_intr_enable( ) tries
5057          * to map Rx queue interrupt to other VFIO vectors.
5058          * So clear uio/vfio intr/evevnfd first to avoid failure.
5059          */
5060         rte_intr_disable(intr_handle);
5061
5062         rte_intr_enable(intr_handle);
5063
5064         /* Re-enable interrupt for VF */
5065         ixgbevf_intr_enable(hw);
5066
5067         return 0;
5068 }
5069
5070 static void
5071 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5072 {
5073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5074         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5075         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5076
5077         PMD_INIT_FUNC_TRACE();
5078
5079         ixgbevf_intr_disable(hw);
5080
5081         hw->adapter_stopped = 1;
5082         ixgbe_stop_adapter(hw);
5083
5084         /*
5085           * Clear what we set, but we still keep shadow_vfta to
5086           * restore after device starts
5087           */
5088         ixgbevf_set_vfta_all(dev, 0);
5089
5090         /* Clear stored conf */
5091         dev->data->scattered_rx = 0;
5092
5093         ixgbe_dev_clear_queues(dev);
5094
5095         /* Clean datapath event and queue/vec mapping */
5096         rte_intr_efd_disable(intr_handle);
5097         if (intr_handle->intr_vec != NULL) {
5098                 rte_free(intr_handle->intr_vec);
5099                 intr_handle->intr_vec = NULL;
5100         }
5101 }
5102
5103 static void
5104 ixgbevf_dev_close(struct rte_eth_dev *dev)
5105 {
5106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5107
5108         PMD_INIT_FUNC_TRACE();
5109
5110         ixgbe_reset_hw(hw);
5111
5112         ixgbevf_dev_stop(dev);
5113
5114         ixgbe_dev_free_queues(dev);
5115
5116         /**
5117          * Remove the VF MAC address ro ensure
5118          * that the VF traffic goes to the PF
5119          * after stop, close and detach of the VF
5120          **/
5121         ixgbevf_remove_mac_addr(dev, 0);
5122 }
5123
5124 /*
5125  * Reset VF device
5126  */
5127 static int
5128 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5129 {
5130         int ret;
5131
5132         ret = eth_ixgbevf_dev_uninit(dev);
5133         if (ret)
5134                 return ret;
5135
5136         ret = eth_ixgbevf_dev_init(dev);
5137
5138         return ret;
5139 }
5140
5141 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5142 {
5143         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5144         struct ixgbe_vfta *shadow_vfta =
5145                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5146         int i = 0, j = 0, vfta = 0, mask = 1;
5147
5148         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5149                 vfta = shadow_vfta->vfta[i];
5150                 if (vfta) {
5151                         mask = 1;
5152                         for (j = 0; j < 32; j++) {
5153                                 if (vfta & mask)
5154                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5155                                                        on, false);
5156                                 mask <<= 1;
5157                         }
5158                 }
5159         }
5160
5161 }
5162
5163 static int
5164 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5165 {
5166         struct ixgbe_hw *hw =
5167                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5168         struct ixgbe_vfta *shadow_vfta =
5169                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5170         uint32_t vid_idx = 0;
5171         uint32_t vid_bit = 0;
5172         int ret = 0;
5173
5174         PMD_INIT_FUNC_TRACE();
5175
5176         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5177         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5178         if (ret) {
5179                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5180                 return ret;
5181         }
5182         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5183         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5184
5185         /* Save what we set and retore it after device reset */
5186         if (on)
5187                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5188         else
5189                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5190
5191         return 0;
5192 }
5193
5194 static void
5195 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5196 {
5197         struct ixgbe_hw *hw =
5198                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5199         uint32_t ctrl;
5200
5201         PMD_INIT_FUNC_TRACE();
5202
5203         if (queue >= hw->mac.max_rx_queues)
5204                 return;
5205
5206         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5207         if (on)
5208                 ctrl |= IXGBE_RXDCTL_VME;
5209         else
5210                 ctrl &= ~IXGBE_RXDCTL_VME;
5211         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5212
5213         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5214 }
5215
5216 static void
5217 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5218 {
5219         struct ixgbe_hw *hw =
5220                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5221         uint16_t i;
5222         int on = 0;
5223
5224         /* VF function only support hw strip feature, others are not support */
5225         if (mask & ETH_VLAN_STRIP_MASK) {
5226                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5227
5228                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5229                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5230         }
5231 }
5232
5233 int
5234 ixgbe_vt_check(struct ixgbe_hw *hw)
5235 {
5236         uint32_t reg_val;
5237
5238         /* if Virtualization Technology is enabled */
5239         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5240         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5241                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5242                 return -1;
5243         }
5244
5245         return 0;
5246 }
5247
5248 static uint32_t
5249 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5250 {
5251         uint32_t vector = 0;
5252
5253         switch (hw->mac.mc_filter_type) {
5254         case 0:   /* use bits [47:36] of the address */
5255                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5256                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5257                 break;
5258         case 1:   /* use bits [46:35] of the address */
5259                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5260                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5261                 break;
5262         case 2:   /* use bits [45:34] of the address */
5263                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5264                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5265                 break;
5266         case 3:   /* use bits [43:32] of the address */
5267                 vector = ((uc_addr->addr_bytes[4]) |
5268                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5269                 break;
5270         default:  /* Invalid mc_filter_type */
5271                 break;
5272         }
5273
5274         /* vector can only be 12-bits or boundary will be exceeded */
5275         vector &= 0xFFF;
5276         return vector;
5277 }
5278
5279 static int
5280 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5281                         uint8_t on)
5282 {
5283         uint32_t vector;
5284         uint32_t uta_idx;
5285         uint32_t reg_val;
5286         uint32_t uta_shift;
5287         uint32_t rc;
5288         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5289         const uint32_t ixgbe_uta_bit_shift = 5;
5290         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5291         const uint32_t bit1 = 0x1;
5292
5293         struct ixgbe_hw *hw =
5294                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5295         struct ixgbe_uta_info *uta_info =
5296                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5297
5298         /* The UTA table only exists on 82599 hardware and newer */
5299         if (hw->mac.type < ixgbe_mac_82599EB)
5300                 return -ENOTSUP;
5301
5302         vector = ixgbe_uta_vector(hw, mac_addr);
5303         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5304         uta_shift = vector & ixgbe_uta_bit_mask;
5305
5306         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5307         if (rc == on)
5308                 return 0;
5309
5310         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5311         if (on) {
5312                 uta_info->uta_in_use++;
5313                 reg_val |= (bit1 << uta_shift);
5314                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5315         } else {
5316                 uta_info->uta_in_use--;
5317                 reg_val &= ~(bit1 << uta_shift);
5318                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5319         }
5320
5321         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5322
5323         if (uta_info->uta_in_use > 0)
5324                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5325                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5326         else
5327                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5328
5329         return 0;
5330 }
5331
5332 static int
5333 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5334 {
5335         int i;
5336         struct ixgbe_hw *hw =
5337                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5338         struct ixgbe_uta_info *uta_info =
5339                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5340
5341         /* The UTA table only exists on 82599 hardware and newer */
5342         if (hw->mac.type < ixgbe_mac_82599EB)
5343                 return -ENOTSUP;
5344
5345         if (on) {
5346                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5347                         uta_info->uta_shadow[i] = ~0;
5348                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5349                 }
5350         } else {
5351                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5352                         uta_info->uta_shadow[i] = 0;
5353                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5354                 }
5355         }
5356         return 0;
5357
5358 }
5359
5360 uint32_t
5361 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5362 {
5363         uint32_t new_val = orig_val;
5364
5365         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5366                 new_val |= IXGBE_VMOLR_AUPE;
5367         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5368                 new_val |= IXGBE_VMOLR_ROMPE;
5369         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5370                 new_val |= IXGBE_VMOLR_ROPE;
5371         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5372                 new_val |= IXGBE_VMOLR_BAM;
5373         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5374                 new_val |= IXGBE_VMOLR_MPE;
5375
5376         return new_val;
5377 }
5378
5379 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5380 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5381 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5382 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5383 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5384         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5385         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5386
5387 static int
5388 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5389                       struct rte_eth_mirror_conf *mirror_conf,
5390                       uint8_t rule_id, uint8_t on)
5391 {
5392         uint32_t mr_ctl, vlvf;
5393         uint32_t mp_lsb = 0;
5394         uint32_t mv_msb = 0;
5395         uint32_t mv_lsb = 0;
5396         uint32_t mp_msb = 0;
5397         uint8_t i = 0;
5398         int reg_index = 0;
5399         uint64_t vlan_mask = 0;
5400
5401         const uint8_t pool_mask_offset = 32;
5402         const uint8_t vlan_mask_offset = 32;
5403         const uint8_t dst_pool_offset = 8;
5404         const uint8_t rule_mr_offset  = 4;
5405         const uint8_t mirror_rule_mask = 0x0F;
5406
5407         struct ixgbe_mirror_info *mr_info =
5408                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5409         struct ixgbe_hw *hw =
5410                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5411         uint8_t mirror_type = 0;
5412
5413         if (ixgbe_vt_check(hw) < 0)
5414                 return -ENOTSUP;
5415
5416         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5417                 return -EINVAL;
5418
5419         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5420                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5421                             mirror_conf->rule_type);
5422                 return -EINVAL;
5423         }
5424
5425         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5426                 mirror_type |= IXGBE_MRCTL_VLME;
5427                 /* Check if vlan id is valid and find conresponding VLAN ID
5428                  * index in VLVF
5429                  */
5430                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5431                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5432                                 /* search vlan id related pool vlan filter
5433                                  * index
5434                                  */
5435                                 reg_index = ixgbe_find_vlvf_slot(
5436                                                 hw,
5437                                                 mirror_conf->vlan.vlan_id[i],
5438                                                 false);
5439                                 if (reg_index < 0)
5440                                         return -EINVAL;
5441                                 vlvf = IXGBE_READ_REG(hw,
5442                                                       IXGBE_VLVF(reg_index));
5443                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5444                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5445                                       mirror_conf->vlan.vlan_id[i]))
5446                                         vlan_mask |= (1ULL << reg_index);
5447                                 else
5448                                         return -EINVAL;
5449                         }
5450                 }
5451
5452                 if (on) {
5453                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5454                         mv_msb = vlan_mask >> vlan_mask_offset;
5455
5456                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5457                                                 mirror_conf->vlan.vlan_mask;
5458                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5459                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5460                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5461                                                 mirror_conf->vlan.vlan_id[i];
5462                         }
5463                 } else {
5464                         mv_lsb = 0;
5465                         mv_msb = 0;
5466                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5467                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5468                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5469                 }
5470         }
5471
5472         /**
5473          * if enable pool mirror, write related pool mask register,if disable
5474          * pool mirror, clear PFMRVM register
5475          */
5476         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5477                 mirror_type |= IXGBE_MRCTL_VPME;
5478                 if (on) {
5479                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5480                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5481                         mr_info->mr_conf[rule_id].pool_mask =
5482                                         mirror_conf->pool_mask;
5483
5484                 } else {
5485                         mp_lsb = 0;
5486                         mp_msb = 0;
5487                         mr_info->mr_conf[rule_id].pool_mask = 0;
5488                 }
5489         }
5490         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5491                 mirror_type |= IXGBE_MRCTL_UPME;
5492         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5493                 mirror_type |= IXGBE_MRCTL_DPME;
5494
5495         /* read  mirror control register and recalculate it */
5496         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5497
5498         if (on) {
5499                 mr_ctl |= mirror_type;
5500                 mr_ctl &= mirror_rule_mask;
5501                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5502         } else {
5503                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5504         }
5505
5506         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5507         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5508
5509         /* write mirrror control  register */
5510         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5511
5512         /* write pool mirrror control  register */
5513         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5514                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5515                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5516                                 mp_msb);
5517         }
5518         /* write VLAN mirrror control  register */
5519         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5520                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5521                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5522                                 mv_msb);
5523         }
5524
5525         return 0;
5526 }
5527
5528 static int
5529 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5530 {
5531         int mr_ctl = 0;
5532         uint32_t lsb_val = 0;
5533         uint32_t msb_val = 0;
5534         const uint8_t rule_mr_offset = 4;
5535
5536         struct ixgbe_hw *hw =
5537                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5538         struct ixgbe_mirror_info *mr_info =
5539                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5540
5541         if (ixgbe_vt_check(hw) < 0)
5542                 return -ENOTSUP;
5543
5544         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5545                 return -EINVAL;
5546
5547         memset(&mr_info->mr_conf[rule_id], 0,
5548                sizeof(struct rte_eth_mirror_conf));
5549
5550         /* clear PFVMCTL register */
5551         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5552
5553         /* clear pool mask register */
5554         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5555         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5556
5557         /* clear vlan mask register */
5558         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5559         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5560
5561         return 0;
5562 }
5563
5564 static int
5565 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5566 {
5567         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5568         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5569         uint32_t mask;
5570         struct ixgbe_hw *hw =
5571                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5572         uint32_t vec = IXGBE_MISC_VEC_ID;
5573
5574         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5575         if (rte_intr_allow_others(intr_handle))
5576                 vec = IXGBE_RX_VEC_START;
5577         mask |= (1 << vec);
5578         RTE_SET_USED(queue_id);
5579         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5580
5581         rte_intr_enable(intr_handle);
5582
5583         return 0;
5584 }
5585
5586 static int
5587 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5588 {
5589         uint32_t mask;
5590         struct ixgbe_hw *hw =
5591                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5592         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5593         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5594         uint32_t vec = IXGBE_MISC_VEC_ID;
5595
5596         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5597         if (rte_intr_allow_others(intr_handle))
5598                 vec = IXGBE_RX_VEC_START;
5599         mask &= ~(1 << vec);
5600         RTE_SET_USED(queue_id);
5601         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5602
5603         return 0;
5604 }
5605
5606 static int
5607 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5608 {
5609         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5610         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5611         uint32_t mask;
5612         struct ixgbe_hw *hw =
5613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5614         struct ixgbe_interrupt *intr =
5615                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5616
5617         if (queue_id < 16) {
5618                 ixgbe_disable_intr(hw);
5619                 intr->mask |= (1 << queue_id);
5620                 ixgbe_enable_intr(dev);
5621         } else if (queue_id < 32) {
5622                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5623                 mask &= (1 << queue_id);
5624                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5625         } else if (queue_id < 64) {
5626                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5627                 mask &= (1 << (queue_id - 32));
5628                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5629         }
5630         rte_intr_enable(intr_handle);
5631
5632         return 0;
5633 }
5634
5635 static int
5636 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5637 {
5638         uint32_t mask;
5639         struct ixgbe_hw *hw =
5640                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5641         struct ixgbe_interrupt *intr =
5642                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5643
5644         if (queue_id < 16) {
5645                 ixgbe_disable_intr(hw);
5646                 intr->mask &= ~(1 << queue_id);
5647                 ixgbe_enable_intr(dev);
5648         } else if (queue_id < 32) {
5649                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5650                 mask &= ~(1 << queue_id);
5651                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5652         } else if (queue_id < 64) {
5653                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5654                 mask &= ~(1 << (queue_id - 32));
5655                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5656         }
5657
5658         return 0;
5659 }
5660
5661 static void
5662 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5663                      uint8_t queue, uint8_t msix_vector)
5664 {
5665         uint32_t tmp, idx;
5666
5667         if (direction == -1) {
5668                 /* other causes */
5669                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5670                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5671                 tmp &= ~0xFF;
5672                 tmp |= msix_vector;
5673                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5674         } else {
5675                 /* rx or tx cause */
5676                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5677                 idx = ((16 * (queue & 1)) + (8 * direction));
5678                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5679                 tmp &= ~(0xFF << idx);
5680                 tmp |= (msix_vector << idx);
5681                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5682         }
5683 }
5684
5685 /**
5686  * set the IVAR registers, mapping interrupt causes to vectors
5687  * @param hw
5688  *  pointer to ixgbe_hw struct
5689  * @direction
5690  *  0 for Rx, 1 for Tx, -1 for other causes
5691  * @queue
5692  *  queue to map the corresponding interrupt to
5693  * @msix_vector
5694  *  the vector to map to the corresponding queue
5695  */
5696 static void
5697 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5698                    uint8_t queue, uint8_t msix_vector)
5699 {
5700         uint32_t tmp, idx;
5701
5702         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5703         if (hw->mac.type == ixgbe_mac_82598EB) {
5704                 if (direction == -1)
5705                         direction = 0;
5706                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5707                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5708                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5709                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5710                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5711         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5712                         (hw->mac.type == ixgbe_mac_X540) ||
5713                         (hw->mac.type == ixgbe_mac_X550)) {
5714                 if (direction == -1) {
5715                         /* other causes */
5716                         idx = ((queue & 1) * 8);
5717                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5718                         tmp &= ~(0xFF << idx);
5719                         tmp |= (msix_vector << idx);
5720                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5721                 } else {
5722                         /* rx or tx causes */
5723                         idx = ((16 * (queue & 1)) + (8 * direction));
5724                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5725                         tmp &= ~(0xFF << idx);
5726                         tmp |= (msix_vector << idx);
5727                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5728                 }
5729         }
5730 }
5731
5732 static void
5733 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5734 {
5735         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5736         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5737         struct ixgbe_hw *hw =
5738                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5739         uint32_t q_idx;
5740         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5741         uint32_t base = IXGBE_MISC_VEC_ID;
5742
5743         /* Configure VF other cause ivar */
5744         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5745
5746         /* won't configure msix register if no mapping is done
5747          * between intr vector and event fd.
5748          */
5749         if (!rte_intr_dp_is_en(intr_handle))
5750                 return;
5751
5752         if (rte_intr_allow_others(intr_handle)) {
5753                 base = IXGBE_RX_VEC_START;
5754                 vector_idx = IXGBE_RX_VEC_START;
5755         }
5756
5757         /* Configure all RX queues of VF */
5758         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5759                 /* Force all queue use vector 0,
5760                  * as IXGBE_VF_MAXMSIVECOTR = 1
5761                  */
5762                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5763                 intr_handle->intr_vec[q_idx] = vector_idx;
5764                 if (vector_idx < base + intr_handle->nb_efd - 1)
5765                         vector_idx++;
5766         }
5767 }
5768
5769 /**
5770  * Sets up the hardware to properly generate MSI-X interrupts
5771  * @hw
5772  *  board private structure
5773  */
5774 static void
5775 ixgbe_configure_msix(struct rte_eth_dev *dev)
5776 {
5777         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5778         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5779         struct ixgbe_hw *hw =
5780                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5781         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5782         uint32_t vec = IXGBE_MISC_VEC_ID;
5783         uint32_t mask;
5784         uint32_t gpie;
5785
5786         /* won't configure msix register if no mapping is done
5787          * between intr vector and event fd
5788          */
5789         if (!rte_intr_dp_is_en(intr_handle))
5790                 return;
5791
5792         if (rte_intr_allow_others(intr_handle))
5793                 vec = base = IXGBE_RX_VEC_START;
5794
5795         /* setup GPIE for MSI-x mode */
5796         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5797         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5798                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5799         /* auto clearing and auto setting corresponding bits in EIMS
5800          * when MSI-X interrupt is triggered
5801          */
5802         if (hw->mac.type == ixgbe_mac_82598EB) {
5803                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5804         } else {
5805                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5806                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5807         }
5808         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5809
5810         /* Populate the IVAR table and set the ITR values to the
5811          * corresponding register.
5812          */
5813         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5814              queue_id++) {
5815                 /* by default, 1:1 mapping */
5816                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5817                 intr_handle->intr_vec[queue_id] = vec;
5818                 if (vec < base + intr_handle->nb_efd - 1)
5819                         vec++;
5820         }
5821
5822         switch (hw->mac.type) {
5823         case ixgbe_mac_82598EB:
5824                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5825                                    IXGBE_MISC_VEC_ID);
5826                 break;
5827         case ixgbe_mac_82599EB:
5828         case ixgbe_mac_X540:
5829         case ixgbe_mac_X550:
5830                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5831                 break;
5832         default:
5833                 break;
5834         }
5835         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5836                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5837
5838         /* set up to autoclear timer, and the vectors */
5839         mask = IXGBE_EIMS_ENABLE_MASK;
5840         mask &= ~(IXGBE_EIMS_OTHER |
5841                   IXGBE_EIMS_MAILBOX |
5842                   IXGBE_EIMS_LSC);
5843
5844         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5845 }
5846
5847 int
5848 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5849                            uint16_t queue_idx, uint16_t tx_rate)
5850 {
5851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5852         uint32_t rf_dec, rf_int;
5853         uint32_t bcnrc_val;
5854         uint16_t link_speed = dev->data->dev_link.link_speed;
5855
5856         if (queue_idx >= hw->mac.max_tx_queues)
5857                 return -EINVAL;
5858
5859         if (tx_rate != 0) {
5860                 /* Calculate the rate factor values to set */
5861                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5862                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5863                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5864
5865                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5866                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5867                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5868                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5869         } else {
5870                 bcnrc_val = 0;
5871         }
5872
5873         /*
5874          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5875          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5876          * set as 0x4.
5877          */
5878         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5879                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5880                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5881                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5882                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5883         else
5884                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5885                         IXGBE_MMW_SIZE_DEFAULT);
5886
5887         /* Set RTTBCNRC of queue X */
5888         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5889         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5890         IXGBE_WRITE_FLUSH(hw);
5891
5892         return 0;
5893 }
5894
5895 static int
5896 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5897                      __attribute__((unused)) uint32_t index,
5898                      __attribute__((unused)) uint32_t pool)
5899 {
5900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5901         int diag;
5902
5903         /*
5904          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5905          * operation. Trap this case to avoid exhausting the [very limited]
5906          * set of PF resources used to store VF MAC addresses.
5907          */
5908         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5909                 return -1;
5910         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5911         if (diag != 0)
5912                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5913                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5914                             mac_addr->addr_bytes[0],
5915                             mac_addr->addr_bytes[1],
5916                             mac_addr->addr_bytes[2],
5917                             mac_addr->addr_bytes[3],
5918                             mac_addr->addr_bytes[4],
5919                             mac_addr->addr_bytes[5],
5920                             diag);
5921         return diag;
5922 }
5923
5924 static void
5925 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5926 {
5927         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5928         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5929         struct ether_addr *mac_addr;
5930         uint32_t i;
5931         int diag;
5932
5933         /*
5934          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5935          * not support the deletion of a given MAC address.
5936          * Instead, it imposes to delete all MAC addresses, then to add again
5937          * all MAC addresses with the exception of the one to be deleted.
5938          */
5939         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5940
5941         /*
5942          * Add again all MAC addresses, with the exception of the deleted one
5943          * and of the permanent MAC address.
5944          */
5945         for (i = 0, mac_addr = dev->data->mac_addrs;
5946              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5947                 /* Skip the deleted MAC address */
5948                 if (i == index)
5949                         continue;
5950                 /* Skip NULL MAC addresses */
5951                 if (is_zero_ether_addr(mac_addr))
5952                         continue;
5953                 /* Skip the permanent MAC address */
5954                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5955                         continue;
5956                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5957                 if (diag != 0)
5958                         PMD_DRV_LOG(ERR,
5959                                     "Adding again MAC address "
5960                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5961                                     "diag=%d",
5962                                     mac_addr->addr_bytes[0],
5963                                     mac_addr->addr_bytes[1],
5964                                     mac_addr->addr_bytes[2],
5965                                     mac_addr->addr_bytes[3],
5966                                     mac_addr->addr_bytes[4],
5967                                     mac_addr->addr_bytes[5],
5968                                     diag);
5969         }
5970 }
5971
5972 static void
5973 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5974 {
5975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5976
5977         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5978 }
5979
5980 int
5981 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5982                         struct rte_eth_syn_filter *filter,
5983                         bool add)
5984 {
5985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5986         struct ixgbe_filter_info *filter_info =
5987                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5988         uint32_t syn_info;
5989         uint32_t synqf;
5990
5991         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5992                 return -EINVAL;
5993
5994         syn_info = filter_info->syn_info;
5995
5996         if (add) {
5997                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5998                         return -EINVAL;
5999                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6000                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6001
6002                 if (filter->hig_pri)
6003                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6004                 else
6005                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6006         } else {
6007                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6008                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6009                         return -ENOENT;
6010                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6011         }
6012
6013         filter_info->syn_info = synqf;
6014         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6015         IXGBE_WRITE_FLUSH(hw);
6016         return 0;
6017 }
6018
6019 static int
6020 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6021                         struct rte_eth_syn_filter *filter)
6022 {
6023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6024         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6025
6026         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6027                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6028                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6029                 return 0;
6030         }
6031         return -ENOENT;
6032 }
6033
6034 static int
6035 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6036                         enum rte_filter_op filter_op,
6037                         void *arg)
6038 {
6039         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6040         int ret;
6041
6042         MAC_TYPE_FILTER_SUP(hw->mac.type);
6043
6044         if (filter_op == RTE_ETH_FILTER_NOP)
6045                 return 0;
6046
6047         if (arg == NULL) {
6048                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6049                             filter_op);
6050                 return -EINVAL;
6051         }
6052
6053         switch (filter_op) {
6054         case RTE_ETH_FILTER_ADD:
6055                 ret = ixgbe_syn_filter_set(dev,
6056                                 (struct rte_eth_syn_filter *)arg,
6057                                 TRUE);
6058                 break;
6059         case RTE_ETH_FILTER_DELETE:
6060                 ret = ixgbe_syn_filter_set(dev,
6061                                 (struct rte_eth_syn_filter *)arg,
6062                                 FALSE);
6063                 break;
6064         case RTE_ETH_FILTER_GET:
6065                 ret = ixgbe_syn_filter_get(dev,
6066                                 (struct rte_eth_syn_filter *)arg);
6067                 break;
6068         default:
6069                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6070                 ret = -EINVAL;
6071                 break;
6072         }
6073
6074         return ret;
6075 }
6076
6077
6078 static inline enum ixgbe_5tuple_protocol
6079 convert_protocol_type(uint8_t protocol_value)
6080 {
6081         if (protocol_value == IPPROTO_TCP)
6082                 return IXGBE_FILTER_PROTOCOL_TCP;
6083         else if (protocol_value == IPPROTO_UDP)
6084                 return IXGBE_FILTER_PROTOCOL_UDP;
6085         else if (protocol_value == IPPROTO_SCTP)
6086                 return IXGBE_FILTER_PROTOCOL_SCTP;
6087         else
6088                 return IXGBE_FILTER_PROTOCOL_NONE;
6089 }
6090
6091 /* inject a 5-tuple filter to HW */
6092 static inline void
6093 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6094                            struct ixgbe_5tuple_filter *filter)
6095 {
6096         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6097         int i;
6098         uint32_t ftqf, sdpqf;
6099         uint32_t l34timir = 0;
6100         uint8_t mask = 0xff;
6101
6102         i = filter->index;
6103
6104         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6105                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6106         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6107
6108         ftqf = (uint32_t)(filter->filter_info.proto &
6109                 IXGBE_FTQF_PROTOCOL_MASK);
6110         ftqf |= (uint32_t)((filter->filter_info.priority &
6111                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6112         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6113                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6114         if (filter->filter_info.dst_ip_mask == 0)
6115                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6116         if (filter->filter_info.src_port_mask == 0)
6117                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6118         if (filter->filter_info.dst_port_mask == 0)
6119                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6120         if (filter->filter_info.proto_mask == 0)
6121                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6122         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6123         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6124         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6125
6126         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6127         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6128         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6129         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6130
6131         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6132         l34timir |= (uint32_t)(filter->queue <<
6133                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6134         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6135 }
6136
6137 /*
6138  * add a 5tuple filter
6139  *
6140  * @param
6141  * dev: Pointer to struct rte_eth_dev.
6142  * index: the index the filter allocates.
6143  * filter: ponter to the filter that will be added.
6144  * rx_queue: the queue id the filter assigned to.
6145  *
6146  * @return
6147  *    - On success, zero.
6148  *    - On failure, a negative value.
6149  */
6150 static int
6151 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6152                         struct ixgbe_5tuple_filter *filter)
6153 {
6154         struct ixgbe_filter_info *filter_info =
6155                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6156         int i, idx, shift;
6157
6158         /*
6159          * look for an unused 5tuple filter index,
6160          * and insert the filter to list.
6161          */
6162         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6163                 idx = i / (sizeof(uint32_t) * NBBY);
6164                 shift = i % (sizeof(uint32_t) * NBBY);
6165                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6166                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6167                         filter->index = i;
6168                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6169                                           filter,
6170                                           entries);
6171                         break;
6172                 }
6173         }
6174         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6175                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6176                 return -ENOSYS;
6177         }
6178
6179         ixgbe_inject_5tuple_filter(dev, filter);
6180
6181         return 0;
6182 }
6183
6184 /*
6185  * remove a 5tuple filter
6186  *
6187  * @param
6188  * dev: Pointer to struct rte_eth_dev.
6189  * filter: the pointer of the filter will be removed.
6190  */
6191 static void
6192 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6193                         struct ixgbe_5tuple_filter *filter)
6194 {
6195         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6196         struct ixgbe_filter_info *filter_info =
6197                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6198         uint16_t index = filter->index;
6199
6200         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6201                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6202         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6203         rte_free(filter);
6204
6205         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6206         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6207         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6208         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6209         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6210 }
6211
6212 static int
6213 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6214 {
6215         struct ixgbe_hw *hw;
6216         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6217         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6218
6219         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6220
6221         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6222                 return -EINVAL;
6223
6224         /* refuse mtu that requires the support of scattered packets when this
6225          * feature has not been enabled before.
6226          */
6227         if (!rx_conf->enable_scatter &&
6228             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6229              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6230                 return -EINVAL;
6231
6232         /*
6233          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6234          * request of the version 2.0 of the mailbox API.
6235          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6236          * of the mailbox API.
6237          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6238          * prior to 3.11.33 which contains the following change:
6239          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6240          */
6241         ixgbevf_rlpml_set_vf(hw, max_frame);
6242
6243         /* update max frame size */
6244         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6245         return 0;
6246 }
6247
6248 static inline struct ixgbe_5tuple_filter *
6249 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6250                         struct ixgbe_5tuple_filter_info *key)
6251 {
6252         struct ixgbe_5tuple_filter *it;
6253
6254         TAILQ_FOREACH(it, filter_list, entries) {
6255                 if (memcmp(key, &it->filter_info,
6256                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6257                         return it;
6258                 }
6259         }
6260         return NULL;
6261 }
6262
6263 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6264 static inline int
6265 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6266                         struct ixgbe_5tuple_filter_info *filter_info)
6267 {
6268         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6269                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6270                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6271                 return -EINVAL;
6272
6273         switch (filter->dst_ip_mask) {
6274         case UINT32_MAX:
6275                 filter_info->dst_ip_mask = 0;
6276                 filter_info->dst_ip = filter->dst_ip;
6277                 break;
6278         case 0:
6279                 filter_info->dst_ip_mask = 1;
6280                 break;
6281         default:
6282                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6283                 return -EINVAL;
6284         }
6285
6286         switch (filter->src_ip_mask) {
6287         case UINT32_MAX:
6288                 filter_info->src_ip_mask = 0;
6289                 filter_info->src_ip = filter->src_ip;
6290                 break;
6291         case 0:
6292                 filter_info->src_ip_mask = 1;
6293                 break;
6294         default:
6295                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6296                 return -EINVAL;
6297         }
6298
6299         switch (filter->dst_port_mask) {
6300         case UINT16_MAX:
6301                 filter_info->dst_port_mask = 0;
6302                 filter_info->dst_port = filter->dst_port;
6303                 break;
6304         case 0:
6305                 filter_info->dst_port_mask = 1;
6306                 break;
6307         default:
6308                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6309                 return -EINVAL;
6310         }
6311
6312         switch (filter->src_port_mask) {
6313         case UINT16_MAX:
6314                 filter_info->src_port_mask = 0;
6315                 filter_info->src_port = filter->src_port;
6316                 break;
6317         case 0:
6318                 filter_info->src_port_mask = 1;
6319                 break;
6320         default:
6321                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6322                 return -EINVAL;
6323         }
6324
6325         switch (filter->proto_mask) {
6326         case UINT8_MAX:
6327                 filter_info->proto_mask = 0;
6328                 filter_info->proto =
6329                         convert_protocol_type(filter->proto);
6330                 break;
6331         case 0:
6332                 filter_info->proto_mask = 1;
6333                 break;
6334         default:
6335                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6336                 return -EINVAL;
6337         }
6338
6339         filter_info->priority = (uint8_t)filter->priority;
6340         return 0;
6341 }
6342
6343 /*
6344  * add or delete a ntuple filter
6345  *
6346  * @param
6347  * dev: Pointer to struct rte_eth_dev.
6348  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6349  * add: if true, add filter, if false, remove filter
6350  *
6351  * @return
6352  *    - On success, zero.
6353  *    - On failure, a negative value.
6354  */
6355 int
6356 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6357                         struct rte_eth_ntuple_filter *ntuple_filter,
6358                         bool add)
6359 {
6360         struct ixgbe_filter_info *filter_info =
6361                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6362         struct ixgbe_5tuple_filter_info filter_5tuple;
6363         struct ixgbe_5tuple_filter *filter;
6364         int ret;
6365
6366         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6367                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6368                 return -EINVAL;
6369         }
6370
6371         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6372         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6373         if (ret < 0)
6374                 return ret;
6375
6376         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6377                                          &filter_5tuple);
6378         if (filter != NULL && add) {
6379                 PMD_DRV_LOG(ERR, "filter exists.");
6380                 return -EEXIST;
6381         }
6382         if (filter == NULL && !add) {
6383                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6384                 return -ENOENT;
6385         }
6386
6387         if (add) {
6388                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6389                                 sizeof(struct ixgbe_5tuple_filter), 0);
6390                 if (filter == NULL)
6391                         return -ENOMEM;
6392                 rte_memcpy(&filter->filter_info,
6393                                  &filter_5tuple,
6394                                  sizeof(struct ixgbe_5tuple_filter_info));
6395                 filter->queue = ntuple_filter->queue;
6396                 ret = ixgbe_add_5tuple_filter(dev, filter);
6397                 if (ret < 0) {
6398                         rte_free(filter);
6399                         return ret;
6400                 }
6401         } else
6402                 ixgbe_remove_5tuple_filter(dev, filter);
6403
6404         return 0;
6405 }
6406
6407 /*
6408  * get a ntuple filter
6409  *
6410  * @param
6411  * dev: Pointer to struct rte_eth_dev.
6412  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6413  *
6414  * @return
6415  *    - On success, zero.
6416  *    - On failure, a negative value.
6417  */
6418 static int
6419 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6420                         struct rte_eth_ntuple_filter *ntuple_filter)
6421 {
6422         struct ixgbe_filter_info *filter_info =
6423                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6424         struct ixgbe_5tuple_filter_info filter_5tuple;
6425         struct ixgbe_5tuple_filter *filter;
6426         int ret;
6427
6428         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6429                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6430                 return -EINVAL;
6431         }
6432
6433         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6434         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6435         if (ret < 0)
6436                 return ret;
6437
6438         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6439                                          &filter_5tuple);
6440         if (filter == NULL) {
6441                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6442                 return -ENOENT;
6443         }
6444         ntuple_filter->queue = filter->queue;
6445         return 0;
6446 }
6447
6448 /*
6449  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6450  * @dev: pointer to rte_eth_dev structure
6451  * @filter_op:operation will be taken.
6452  * @arg: a pointer to specific structure corresponding to the filter_op
6453  *
6454  * @return
6455  *    - On success, zero.
6456  *    - On failure, a negative value.
6457  */
6458 static int
6459 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6460                                 enum rte_filter_op filter_op,
6461                                 void *arg)
6462 {
6463         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6464         int ret;
6465
6466         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6467
6468         if (filter_op == RTE_ETH_FILTER_NOP)
6469                 return 0;
6470
6471         if (arg == NULL) {
6472                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6473                             filter_op);
6474                 return -EINVAL;
6475         }
6476
6477         switch (filter_op) {
6478         case RTE_ETH_FILTER_ADD:
6479                 ret = ixgbe_add_del_ntuple_filter(dev,
6480                         (struct rte_eth_ntuple_filter *)arg,
6481                         TRUE);
6482                 break;
6483         case RTE_ETH_FILTER_DELETE:
6484                 ret = ixgbe_add_del_ntuple_filter(dev,
6485                         (struct rte_eth_ntuple_filter *)arg,
6486                         FALSE);
6487                 break;
6488         case RTE_ETH_FILTER_GET:
6489                 ret = ixgbe_get_ntuple_filter(dev,
6490                         (struct rte_eth_ntuple_filter *)arg);
6491                 break;
6492         default:
6493                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6494                 ret = -EINVAL;
6495                 break;
6496         }
6497         return ret;
6498 }
6499
6500 int
6501 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6502                         struct rte_eth_ethertype_filter *filter,
6503                         bool add)
6504 {
6505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6506         struct ixgbe_filter_info *filter_info =
6507                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6508         uint32_t etqf = 0;
6509         uint32_t etqs = 0;
6510         int ret;
6511         struct ixgbe_ethertype_filter ethertype_filter;
6512
6513         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6514                 return -EINVAL;
6515
6516         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6517                 filter->ether_type == ETHER_TYPE_IPv6) {
6518                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6519                         " ethertype filter.", filter->ether_type);
6520                 return -EINVAL;
6521         }
6522
6523         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6524                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6525                 return -EINVAL;
6526         }
6527         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6528                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6529                 return -EINVAL;
6530         }
6531
6532         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6533         if (ret >= 0 && add) {
6534                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6535                             filter->ether_type);
6536                 return -EEXIST;
6537         }
6538         if (ret < 0 && !add) {
6539                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6540                             filter->ether_type);
6541                 return -ENOENT;
6542         }
6543
6544         if (add) {
6545                 etqf = IXGBE_ETQF_FILTER_EN;
6546                 etqf |= (uint32_t)filter->ether_type;
6547                 etqs |= (uint32_t)((filter->queue <<
6548                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6549                                     IXGBE_ETQS_RX_QUEUE);
6550                 etqs |= IXGBE_ETQS_QUEUE_EN;
6551
6552                 ethertype_filter.ethertype = filter->ether_type;
6553                 ethertype_filter.etqf = etqf;
6554                 ethertype_filter.etqs = etqs;
6555                 ethertype_filter.conf = FALSE;
6556                 ret = ixgbe_ethertype_filter_insert(filter_info,
6557                                                     &ethertype_filter);
6558                 if (ret < 0) {
6559                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6560                         return -ENOSPC;
6561                 }
6562         } else {
6563                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6564                 if (ret < 0)
6565                         return -ENOSYS;
6566         }
6567         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6568         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6569         IXGBE_WRITE_FLUSH(hw);
6570
6571         return 0;
6572 }
6573
6574 static int
6575 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6576                         struct rte_eth_ethertype_filter *filter)
6577 {
6578         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6579         struct ixgbe_filter_info *filter_info =
6580                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6581         uint32_t etqf, etqs;
6582         int ret;
6583
6584         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6585         if (ret < 0) {
6586                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6587                             filter->ether_type);
6588                 return -ENOENT;
6589         }
6590
6591         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6592         if (etqf & IXGBE_ETQF_FILTER_EN) {
6593                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6594                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6595                 filter->flags = 0;
6596                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6597                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6598                 return 0;
6599         }
6600         return -ENOENT;
6601 }
6602
6603 /*
6604  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6605  * @dev: pointer to rte_eth_dev structure
6606  * @filter_op:operation will be taken.
6607  * @arg: a pointer to specific structure corresponding to the filter_op
6608  */
6609 static int
6610 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6611                                 enum rte_filter_op filter_op,
6612                                 void *arg)
6613 {
6614         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6615         int ret;
6616
6617         MAC_TYPE_FILTER_SUP(hw->mac.type);
6618
6619         if (filter_op == RTE_ETH_FILTER_NOP)
6620                 return 0;
6621
6622         if (arg == NULL) {
6623                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6624                             filter_op);
6625                 return -EINVAL;
6626         }
6627
6628         switch (filter_op) {
6629         case RTE_ETH_FILTER_ADD:
6630                 ret = ixgbe_add_del_ethertype_filter(dev,
6631                         (struct rte_eth_ethertype_filter *)arg,
6632                         TRUE);
6633                 break;
6634         case RTE_ETH_FILTER_DELETE:
6635                 ret = ixgbe_add_del_ethertype_filter(dev,
6636                         (struct rte_eth_ethertype_filter *)arg,
6637                         FALSE);
6638                 break;
6639         case RTE_ETH_FILTER_GET:
6640                 ret = ixgbe_get_ethertype_filter(dev,
6641                         (struct rte_eth_ethertype_filter *)arg);
6642                 break;
6643         default:
6644                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6645                 ret = -EINVAL;
6646                 break;
6647         }
6648         return ret;
6649 }
6650
6651 static int
6652 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6653                      enum rte_filter_type filter_type,
6654                      enum rte_filter_op filter_op,
6655                      void *arg)
6656 {
6657         int ret = 0;
6658
6659         switch (filter_type) {
6660         case RTE_ETH_FILTER_NTUPLE:
6661                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6662                 break;
6663         case RTE_ETH_FILTER_ETHERTYPE:
6664                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6665                 break;
6666         case RTE_ETH_FILTER_SYN:
6667                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6668                 break;
6669         case RTE_ETH_FILTER_FDIR:
6670                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6671                 break;
6672         case RTE_ETH_FILTER_L2_TUNNEL:
6673                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6674                 break;
6675         case RTE_ETH_FILTER_GENERIC:
6676                 if (filter_op != RTE_ETH_FILTER_GET)
6677                         return -EINVAL;
6678                 *(const void **)arg = &ixgbe_flow_ops;
6679                 break;
6680         default:
6681                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6682                                                         filter_type);
6683                 ret = -EINVAL;
6684                 break;
6685         }
6686
6687         return ret;
6688 }
6689
6690 static u8 *
6691 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6692                         u8 **mc_addr_ptr, u32 *vmdq)
6693 {
6694         u8 *mc_addr;
6695
6696         *vmdq = 0;
6697         mc_addr = *mc_addr_ptr;
6698         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6699         return mc_addr;
6700 }
6701
6702 static int
6703 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6704                           struct ether_addr *mc_addr_set,
6705                           uint32_t nb_mc_addr)
6706 {
6707         struct ixgbe_hw *hw;
6708         u8 *mc_addr_list;
6709
6710         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6711         mc_addr_list = (u8 *)mc_addr_set;
6712         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6713                                          ixgbe_dev_addr_list_itr, TRUE);
6714 }
6715
6716 static uint64_t
6717 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6718 {
6719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6720         uint64_t systime_cycles;
6721
6722         switch (hw->mac.type) {
6723         case ixgbe_mac_X550:
6724         case ixgbe_mac_X550EM_x:
6725         case ixgbe_mac_X550EM_a:
6726                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6727                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6728                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6729                                 * NSEC_PER_SEC;
6730                 break;
6731         default:
6732                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6733                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6734                                 << 32;
6735         }
6736
6737         return systime_cycles;
6738 }
6739
6740 static uint64_t
6741 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6742 {
6743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6744         uint64_t rx_tstamp_cycles;
6745
6746         switch (hw->mac.type) {
6747         case ixgbe_mac_X550:
6748         case ixgbe_mac_X550EM_x:
6749         case ixgbe_mac_X550EM_a:
6750                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6751                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6752                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6753                                 * NSEC_PER_SEC;
6754                 break;
6755         default:
6756                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6757                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6758                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6759                                 << 32;
6760         }
6761
6762         return rx_tstamp_cycles;
6763 }
6764
6765 static uint64_t
6766 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6767 {
6768         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6769         uint64_t tx_tstamp_cycles;
6770
6771         switch (hw->mac.type) {
6772         case ixgbe_mac_X550:
6773         case ixgbe_mac_X550EM_x:
6774         case ixgbe_mac_X550EM_a:
6775                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6776                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6777                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6778                                 * NSEC_PER_SEC;
6779                 break;
6780         default:
6781                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6782                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6783                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6784                                 << 32;
6785         }
6786
6787         return tx_tstamp_cycles;
6788 }
6789
6790 static void
6791 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6792 {
6793         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6794         struct ixgbe_adapter *adapter =
6795                 (struct ixgbe_adapter *)dev->data->dev_private;
6796         struct rte_eth_link link;
6797         uint32_t incval = 0;
6798         uint32_t shift = 0;
6799
6800         /* Get current link speed. */
6801         memset(&link, 0, sizeof(link));
6802         ixgbe_dev_link_update(dev, 1);
6803         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6804
6805         switch (link.link_speed) {
6806         case ETH_SPEED_NUM_100M:
6807                 incval = IXGBE_INCVAL_100;
6808                 shift = IXGBE_INCVAL_SHIFT_100;
6809                 break;
6810         case ETH_SPEED_NUM_1G:
6811                 incval = IXGBE_INCVAL_1GB;
6812                 shift = IXGBE_INCVAL_SHIFT_1GB;
6813                 break;
6814         case ETH_SPEED_NUM_10G:
6815         default:
6816                 incval = IXGBE_INCVAL_10GB;
6817                 shift = IXGBE_INCVAL_SHIFT_10GB;
6818                 break;
6819         }
6820
6821         switch (hw->mac.type) {
6822         case ixgbe_mac_X550:
6823         case ixgbe_mac_X550EM_x:
6824         case ixgbe_mac_X550EM_a:
6825                 /* Independent of link speed. */
6826                 incval = 1;
6827                 /* Cycles read will be interpreted as ns. */
6828                 shift = 0;
6829                 /* Fall-through */
6830         case ixgbe_mac_X540:
6831                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6832                 break;
6833         case ixgbe_mac_82599EB:
6834                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6835                 shift -= IXGBE_INCVAL_SHIFT_82599;
6836                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6837                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6838                 break;
6839         default:
6840                 /* Not supported. */
6841                 return;
6842         }
6843
6844         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6845         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6846         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6847
6848         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6849         adapter->systime_tc.cc_shift = shift;
6850         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6851
6852         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6853         adapter->rx_tstamp_tc.cc_shift = shift;
6854         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6855
6856         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6857         adapter->tx_tstamp_tc.cc_shift = shift;
6858         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6859 }
6860
6861 static int
6862 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6863 {
6864         struct ixgbe_adapter *adapter =
6865                         (struct ixgbe_adapter *)dev->data->dev_private;
6866
6867         adapter->systime_tc.nsec += delta;
6868         adapter->rx_tstamp_tc.nsec += delta;
6869         adapter->tx_tstamp_tc.nsec += delta;
6870
6871         return 0;
6872 }
6873
6874 static int
6875 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6876 {
6877         uint64_t ns;
6878         struct ixgbe_adapter *adapter =
6879                         (struct ixgbe_adapter *)dev->data->dev_private;
6880
6881         ns = rte_timespec_to_ns(ts);
6882         /* Set the timecounters to a new value. */
6883         adapter->systime_tc.nsec = ns;
6884         adapter->rx_tstamp_tc.nsec = ns;
6885         adapter->tx_tstamp_tc.nsec = ns;
6886
6887         return 0;
6888 }
6889
6890 static int
6891 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6892 {
6893         uint64_t ns, systime_cycles;
6894         struct ixgbe_adapter *adapter =
6895                         (struct ixgbe_adapter *)dev->data->dev_private;
6896
6897         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6898         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6899         *ts = rte_ns_to_timespec(ns);
6900
6901         return 0;
6902 }
6903
6904 static int
6905 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6906 {
6907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6908         uint32_t tsync_ctl;
6909         uint32_t tsauxc;
6910
6911         /* Stop the timesync system time. */
6912         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6913         /* Reset the timesync system time value. */
6914         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6915         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6916
6917         /* Enable system time for platforms where it isn't on by default. */
6918         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6919         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6920         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6921
6922         ixgbe_start_timecounters(dev);
6923
6924         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6925         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6926                         (ETHER_TYPE_1588 |
6927                          IXGBE_ETQF_FILTER_EN |
6928                          IXGBE_ETQF_1588));
6929
6930         /* Enable timestamping of received PTP packets. */
6931         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6932         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6933         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6934
6935         /* Enable timestamping of transmitted PTP packets. */
6936         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6937         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6938         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6939
6940         IXGBE_WRITE_FLUSH(hw);
6941
6942         return 0;
6943 }
6944
6945 static int
6946 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6947 {
6948         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6949         uint32_t tsync_ctl;
6950
6951         /* Disable timestamping of transmitted PTP packets. */
6952         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6953         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6954         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6955
6956         /* Disable timestamping of received PTP packets. */
6957         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6958         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6959         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6960
6961         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6962         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6963
6964         /* Stop incrementating the System Time registers. */
6965         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6966
6967         return 0;
6968 }
6969
6970 static int
6971 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6972                                  struct timespec *timestamp,
6973                                  uint32_t flags __rte_unused)
6974 {
6975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6976         struct ixgbe_adapter *adapter =
6977                 (struct ixgbe_adapter *)dev->data->dev_private;
6978         uint32_t tsync_rxctl;
6979         uint64_t rx_tstamp_cycles;
6980         uint64_t ns;
6981
6982         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6983         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6984                 return -EINVAL;
6985
6986         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6987         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6988         *timestamp = rte_ns_to_timespec(ns);
6989
6990         return  0;
6991 }
6992
6993 static int
6994 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6995                                  struct timespec *timestamp)
6996 {
6997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6998         struct ixgbe_adapter *adapter =
6999                 (struct ixgbe_adapter *)dev->data->dev_private;
7000         uint32_t tsync_txctl;
7001         uint64_t tx_tstamp_cycles;
7002         uint64_t ns;
7003
7004         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7005         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7006                 return -EINVAL;
7007
7008         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7009         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7010         *timestamp = rte_ns_to_timespec(ns);
7011
7012         return 0;
7013 }
7014
7015 static int
7016 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7017 {
7018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7019         int count = 0;
7020         int g_ind = 0;
7021         const struct reg_info *reg_group;
7022         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7023                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7024
7025         while ((reg_group = reg_set[g_ind++]))
7026                 count += ixgbe_regs_group_count(reg_group);
7027
7028         return count;
7029 }
7030
7031 static int
7032 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7033 {
7034         int count = 0;
7035         int g_ind = 0;
7036         const struct reg_info *reg_group;
7037
7038         while ((reg_group = ixgbevf_regs[g_ind++]))
7039                 count += ixgbe_regs_group_count(reg_group);
7040
7041         return count;
7042 }
7043
7044 static int
7045 ixgbe_get_regs(struct rte_eth_dev *dev,
7046               struct rte_dev_reg_info *regs)
7047 {
7048         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7049         uint32_t *data = regs->data;
7050         int g_ind = 0;
7051         int count = 0;
7052         const struct reg_info *reg_group;
7053         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7054                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7055
7056         if (data == NULL) {
7057                 regs->length = ixgbe_get_reg_length(dev);
7058                 regs->width = sizeof(uint32_t);
7059                 return 0;
7060         }
7061
7062         /* Support only full register dump */
7063         if ((regs->length == 0) ||
7064             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7065                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7066                         hw->device_id;
7067                 while ((reg_group = reg_set[g_ind++]))
7068                         count += ixgbe_read_regs_group(dev, &data[count],
7069                                 reg_group);
7070                 return 0;
7071         }
7072
7073         return -ENOTSUP;
7074 }
7075
7076 static int
7077 ixgbevf_get_regs(struct rte_eth_dev *dev,
7078                 struct rte_dev_reg_info *regs)
7079 {
7080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7081         uint32_t *data = regs->data;
7082         int g_ind = 0;
7083         int count = 0;
7084         const struct reg_info *reg_group;
7085
7086         if (data == NULL) {
7087                 regs->length = ixgbevf_get_reg_length(dev);
7088                 regs->width = sizeof(uint32_t);
7089                 return 0;
7090         }
7091
7092         /* Support only full register dump */
7093         if ((regs->length == 0) ||
7094             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7095                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7096                         hw->device_id;
7097                 while ((reg_group = ixgbevf_regs[g_ind++]))
7098                         count += ixgbe_read_regs_group(dev, &data[count],
7099                                                       reg_group);
7100                 return 0;
7101         }
7102
7103         return -ENOTSUP;
7104 }
7105
7106 static int
7107 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7108 {
7109         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7110
7111         /* Return unit is byte count */
7112         return hw->eeprom.word_size * 2;
7113 }
7114
7115 static int
7116 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7117                 struct rte_dev_eeprom_info *in_eeprom)
7118 {
7119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7120         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7121         uint16_t *data = in_eeprom->data;
7122         int first, length;
7123
7124         first = in_eeprom->offset >> 1;
7125         length = in_eeprom->length >> 1;
7126         if ((first > hw->eeprom.word_size) ||
7127             ((first + length) > hw->eeprom.word_size))
7128                 return -EINVAL;
7129
7130         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7131
7132         return eeprom->ops.read_buffer(hw, first, length, data);
7133 }
7134
7135 static int
7136 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7137                 struct rte_dev_eeprom_info *in_eeprom)
7138 {
7139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7140         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7141         uint16_t *data = in_eeprom->data;
7142         int first, length;
7143
7144         first = in_eeprom->offset >> 1;
7145         length = in_eeprom->length >> 1;
7146         if ((first > hw->eeprom.word_size) ||
7147             ((first + length) > hw->eeprom.word_size))
7148                 return -EINVAL;
7149
7150         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7151
7152         return eeprom->ops.write_buffer(hw,  first, length, data);
7153 }
7154
7155 uint16_t
7156 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7157         switch (mac_type) {
7158         case ixgbe_mac_X550:
7159         case ixgbe_mac_X550EM_x:
7160         case ixgbe_mac_X550EM_a:
7161                 return ETH_RSS_RETA_SIZE_512;
7162         case ixgbe_mac_X550_vf:
7163         case ixgbe_mac_X550EM_x_vf:
7164         case ixgbe_mac_X550EM_a_vf:
7165                 return ETH_RSS_RETA_SIZE_64;
7166         default:
7167                 return ETH_RSS_RETA_SIZE_128;
7168         }
7169 }
7170
7171 uint32_t
7172 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7173         switch (mac_type) {
7174         case ixgbe_mac_X550:
7175         case ixgbe_mac_X550EM_x:
7176         case ixgbe_mac_X550EM_a:
7177                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7178                         return IXGBE_RETA(reta_idx >> 2);
7179                 else
7180                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7181         case ixgbe_mac_X550_vf:
7182         case ixgbe_mac_X550EM_x_vf:
7183         case ixgbe_mac_X550EM_a_vf:
7184                 return IXGBE_VFRETA(reta_idx >> 2);
7185         default:
7186                 return IXGBE_RETA(reta_idx >> 2);
7187         }
7188 }
7189
7190 uint32_t
7191 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7192         switch (mac_type) {
7193         case ixgbe_mac_X550_vf:
7194         case ixgbe_mac_X550EM_x_vf:
7195         case ixgbe_mac_X550EM_a_vf:
7196                 return IXGBE_VFMRQC;
7197         default:
7198                 return IXGBE_MRQC;
7199         }
7200 }
7201
7202 uint32_t
7203 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7204         switch (mac_type) {
7205         case ixgbe_mac_X550_vf:
7206         case ixgbe_mac_X550EM_x_vf:
7207         case ixgbe_mac_X550EM_a_vf:
7208                 return IXGBE_VFRSSRK(i);
7209         default:
7210                 return IXGBE_RSSRK(i);
7211         }
7212 }
7213
7214 bool
7215 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7216         switch (mac_type) {
7217         case ixgbe_mac_82599_vf:
7218         case ixgbe_mac_X540_vf:
7219                 return 0;
7220         default:
7221                 return 1;
7222         }
7223 }
7224
7225 static int
7226 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7227                         struct rte_eth_dcb_info *dcb_info)
7228 {
7229         struct ixgbe_dcb_config *dcb_config =
7230                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7231         struct ixgbe_dcb_tc_config *tc;
7232         uint8_t i, j;
7233
7234         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7235                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7236         else
7237                 dcb_info->nb_tcs = 1;
7238
7239         if (dcb_config->vt_mode) { /* vt is enabled*/
7240                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7241                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7242                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7243                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7244                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7245                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7246                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7247                                                 i * dcb_info->nb_tcs + j;
7248                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7249                                 dcb_info->tc_queue.tc_txq[i][j].base =
7250                                                 i * dcb_info->nb_tcs + j;
7251                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7252                         }
7253                 }
7254         } else { /* vt is disabled*/
7255                 struct rte_eth_dcb_rx_conf *rx_conf =
7256                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7257                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7258                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7259                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7260                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7261                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7262                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7263                         }
7264                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7265                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7266                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7267                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7268                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7269                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7270                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7271                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7272                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7273                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7274                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7275                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7276                         }
7277                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7278                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7279                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7280                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7281                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7282                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7283                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7284                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7285                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7286                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7287                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7288                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7289                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7290                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7291                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7292                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7293                 }
7294         }
7295         for (i = 0; i < dcb_info->nb_tcs; i++) {
7296                 tc = &dcb_config->tc_config[i];
7297                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7298         }
7299         return 0;
7300 }
7301
7302 /* Update e-tag ether type */
7303 static int
7304 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7305                             uint16_t ether_type)
7306 {
7307         uint32_t etag_etype;
7308
7309         if (hw->mac.type != ixgbe_mac_X550 &&
7310             hw->mac.type != ixgbe_mac_X550EM_x &&
7311             hw->mac.type != ixgbe_mac_X550EM_a) {
7312                 return -ENOTSUP;
7313         }
7314
7315         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7316         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7317         etag_etype |= ether_type;
7318         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7319         IXGBE_WRITE_FLUSH(hw);
7320
7321         return 0;
7322 }
7323
7324 /* Config l2 tunnel ether type */
7325 static int
7326 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7327                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7328 {
7329         int ret = 0;
7330         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7331         struct ixgbe_l2_tn_info *l2_tn_info =
7332                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7333
7334         if (l2_tunnel == NULL)
7335                 return -EINVAL;
7336
7337         switch (l2_tunnel->l2_tunnel_type) {
7338         case RTE_L2_TUNNEL_TYPE_E_TAG:
7339                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7340                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7341                 break;
7342         default:
7343                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7344                 ret = -EINVAL;
7345                 break;
7346         }
7347
7348         return ret;
7349 }
7350
7351 /* Enable e-tag tunnel */
7352 static int
7353 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7354 {
7355         uint32_t etag_etype;
7356
7357         if (hw->mac.type != ixgbe_mac_X550 &&
7358             hw->mac.type != ixgbe_mac_X550EM_x &&
7359             hw->mac.type != ixgbe_mac_X550EM_a) {
7360                 return -ENOTSUP;
7361         }
7362
7363         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7364         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7365         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7366         IXGBE_WRITE_FLUSH(hw);
7367
7368         return 0;
7369 }
7370
7371 /* Enable l2 tunnel */
7372 static int
7373 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7374                            enum rte_eth_tunnel_type l2_tunnel_type)
7375 {
7376         int ret = 0;
7377         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7378         struct ixgbe_l2_tn_info *l2_tn_info =
7379                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7380
7381         switch (l2_tunnel_type) {
7382         case RTE_L2_TUNNEL_TYPE_E_TAG:
7383                 l2_tn_info->e_tag_en = TRUE;
7384                 ret = ixgbe_e_tag_enable(hw);
7385                 break;
7386         default:
7387                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7388                 ret = -EINVAL;
7389                 break;
7390         }
7391
7392         return ret;
7393 }
7394
7395 /* Disable e-tag tunnel */
7396 static int
7397 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7398 {
7399         uint32_t etag_etype;
7400
7401         if (hw->mac.type != ixgbe_mac_X550 &&
7402             hw->mac.type != ixgbe_mac_X550EM_x &&
7403             hw->mac.type != ixgbe_mac_X550EM_a) {
7404                 return -ENOTSUP;
7405         }
7406
7407         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7408         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7409         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7410         IXGBE_WRITE_FLUSH(hw);
7411
7412         return 0;
7413 }
7414
7415 /* Disable l2 tunnel */
7416 static int
7417 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7418                             enum rte_eth_tunnel_type l2_tunnel_type)
7419 {
7420         int ret = 0;
7421         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7422         struct ixgbe_l2_tn_info *l2_tn_info =
7423                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7424
7425         switch (l2_tunnel_type) {
7426         case RTE_L2_TUNNEL_TYPE_E_TAG:
7427                 l2_tn_info->e_tag_en = FALSE;
7428                 ret = ixgbe_e_tag_disable(hw);
7429                 break;
7430         default:
7431                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7432                 ret = -EINVAL;
7433                 break;
7434         }
7435
7436         return ret;
7437 }
7438
7439 static int
7440 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7441                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7442 {
7443         int ret = 0;
7444         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7445         uint32_t i, rar_entries;
7446         uint32_t rar_low, rar_high;
7447
7448         if (hw->mac.type != ixgbe_mac_X550 &&
7449             hw->mac.type != ixgbe_mac_X550EM_x &&
7450             hw->mac.type != ixgbe_mac_X550EM_a) {
7451                 return -ENOTSUP;
7452         }
7453
7454         rar_entries = ixgbe_get_num_rx_addrs(hw);
7455
7456         for (i = 1; i < rar_entries; i++) {
7457                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7458                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7459                 if ((rar_high & IXGBE_RAH_AV) &&
7460                     (rar_high & IXGBE_RAH_ADTYPE) &&
7461                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7462                      l2_tunnel->tunnel_id)) {
7463                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7464                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7465
7466                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7467
7468                         return ret;
7469                 }
7470         }
7471
7472         return ret;
7473 }
7474
7475 static int
7476 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7477                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7478 {
7479         int ret = 0;
7480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7481         uint32_t i, rar_entries;
7482         uint32_t rar_low, rar_high;
7483
7484         if (hw->mac.type != ixgbe_mac_X550 &&
7485             hw->mac.type != ixgbe_mac_X550EM_x &&
7486             hw->mac.type != ixgbe_mac_X550EM_a) {
7487                 return -ENOTSUP;
7488         }
7489
7490         /* One entry for one tunnel. Try to remove potential existing entry. */
7491         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7492
7493         rar_entries = ixgbe_get_num_rx_addrs(hw);
7494
7495         for (i = 1; i < rar_entries; i++) {
7496                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7497                 if (rar_high & IXGBE_RAH_AV) {
7498                         continue;
7499                 } else {
7500                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7501                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7502                         rar_low = l2_tunnel->tunnel_id;
7503
7504                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7505                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7506
7507                         return ret;
7508                 }
7509         }
7510
7511         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7512                      " Please remove a rule before adding a new one.");
7513         return -EINVAL;
7514 }
7515
7516 static inline struct ixgbe_l2_tn_filter *
7517 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7518                           struct ixgbe_l2_tn_key *key)
7519 {
7520         int ret;
7521
7522         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7523         if (ret < 0)
7524                 return NULL;
7525
7526         return l2_tn_info->hash_map[ret];
7527 }
7528
7529 static inline int
7530 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7531                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7532 {
7533         int ret;
7534
7535         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7536                                &l2_tn_filter->key);
7537
7538         if (ret < 0) {
7539                 PMD_DRV_LOG(ERR,
7540                             "Failed to insert L2 tunnel filter"
7541                             " to hash table %d!",
7542                             ret);
7543                 return ret;
7544         }
7545
7546         l2_tn_info->hash_map[ret] = l2_tn_filter;
7547
7548         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7549
7550         return 0;
7551 }
7552
7553 static inline int
7554 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7555                           struct ixgbe_l2_tn_key *key)
7556 {
7557         int ret;
7558         struct ixgbe_l2_tn_filter *l2_tn_filter;
7559
7560         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7561
7562         if (ret < 0) {
7563                 PMD_DRV_LOG(ERR,
7564                             "No such L2 tunnel filter to delete %d!",
7565                             ret);
7566                 return ret;
7567         }
7568
7569         l2_tn_filter = l2_tn_info->hash_map[ret];
7570         l2_tn_info->hash_map[ret] = NULL;
7571
7572         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7573         rte_free(l2_tn_filter);
7574
7575         return 0;
7576 }
7577
7578 /* Add l2 tunnel filter */
7579 int
7580 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7581                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7582                                bool restore)
7583 {
7584         int ret;
7585         struct ixgbe_l2_tn_info *l2_tn_info =
7586                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7587         struct ixgbe_l2_tn_key key;
7588         struct ixgbe_l2_tn_filter *node;
7589
7590         if (!restore) {
7591                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7592                 key.tn_id = l2_tunnel->tunnel_id;
7593
7594                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7595
7596                 if (node) {
7597                         PMD_DRV_LOG(ERR,
7598                                     "The L2 tunnel filter already exists!");
7599                         return -EINVAL;
7600                 }
7601
7602                 node = rte_zmalloc("ixgbe_l2_tn",
7603                                    sizeof(struct ixgbe_l2_tn_filter),
7604                                    0);
7605                 if (!node)
7606                         return -ENOMEM;
7607
7608                 rte_memcpy(&node->key,
7609                                  &key,
7610                                  sizeof(struct ixgbe_l2_tn_key));
7611                 node->pool = l2_tunnel->pool;
7612                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7613                 if (ret < 0) {
7614                         rte_free(node);
7615                         return ret;
7616                 }
7617         }
7618
7619         switch (l2_tunnel->l2_tunnel_type) {
7620         case RTE_L2_TUNNEL_TYPE_E_TAG:
7621                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7622                 break;
7623         default:
7624                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7625                 ret = -EINVAL;
7626                 break;
7627         }
7628
7629         if ((!restore) && (ret < 0))
7630                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7631
7632         return ret;
7633 }
7634
7635 /* Delete l2 tunnel filter */
7636 int
7637 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7638                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7639 {
7640         int ret;
7641         struct ixgbe_l2_tn_info *l2_tn_info =
7642                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7643         struct ixgbe_l2_tn_key key;
7644
7645         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7646         key.tn_id = l2_tunnel->tunnel_id;
7647         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7648         if (ret < 0)
7649                 return ret;
7650
7651         switch (l2_tunnel->l2_tunnel_type) {
7652         case RTE_L2_TUNNEL_TYPE_E_TAG:
7653                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7654                 break;
7655         default:
7656                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7657                 ret = -EINVAL;
7658                 break;
7659         }
7660
7661         return ret;
7662 }
7663
7664 /**
7665  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7666  * @dev: pointer to rte_eth_dev structure
7667  * @filter_op:operation will be taken.
7668  * @arg: a pointer to specific structure corresponding to the filter_op
7669  */
7670 static int
7671 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7672                                   enum rte_filter_op filter_op,
7673                                   void *arg)
7674 {
7675         int ret;
7676
7677         if (filter_op == RTE_ETH_FILTER_NOP)
7678                 return 0;
7679
7680         if (arg == NULL) {
7681                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7682                             filter_op);
7683                 return -EINVAL;
7684         }
7685
7686         switch (filter_op) {
7687         case RTE_ETH_FILTER_ADD:
7688                 ret = ixgbe_dev_l2_tunnel_filter_add
7689                         (dev,
7690                          (struct rte_eth_l2_tunnel_conf *)arg,
7691                          FALSE);
7692                 break;
7693         case RTE_ETH_FILTER_DELETE:
7694                 ret = ixgbe_dev_l2_tunnel_filter_del
7695                         (dev,
7696                          (struct rte_eth_l2_tunnel_conf *)arg);
7697                 break;
7698         default:
7699                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7700                 ret = -EINVAL;
7701                 break;
7702         }
7703         return ret;
7704 }
7705
7706 static int
7707 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7708 {
7709         int ret = 0;
7710         uint32_t ctrl;
7711         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7712
7713         if (hw->mac.type != ixgbe_mac_X550 &&
7714             hw->mac.type != ixgbe_mac_X550EM_x &&
7715             hw->mac.type != ixgbe_mac_X550EM_a) {
7716                 return -ENOTSUP;
7717         }
7718
7719         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7720         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7721         if (en)
7722                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7723         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7724
7725         return ret;
7726 }
7727
7728 /* Enable l2 tunnel forwarding */
7729 static int
7730 ixgbe_dev_l2_tunnel_forwarding_enable
7731         (struct rte_eth_dev *dev,
7732          enum rte_eth_tunnel_type l2_tunnel_type)
7733 {
7734         struct ixgbe_l2_tn_info *l2_tn_info =
7735                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7736         int ret = 0;
7737
7738         switch (l2_tunnel_type) {
7739         case RTE_L2_TUNNEL_TYPE_E_TAG:
7740                 l2_tn_info->e_tag_fwd_en = TRUE;
7741                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7742                 break;
7743         default:
7744                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7745                 ret = -EINVAL;
7746                 break;
7747         }
7748
7749         return ret;
7750 }
7751
7752 /* Disable l2 tunnel forwarding */
7753 static int
7754 ixgbe_dev_l2_tunnel_forwarding_disable
7755         (struct rte_eth_dev *dev,
7756          enum rte_eth_tunnel_type l2_tunnel_type)
7757 {
7758         struct ixgbe_l2_tn_info *l2_tn_info =
7759                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7760         int ret = 0;
7761
7762         switch (l2_tunnel_type) {
7763         case RTE_L2_TUNNEL_TYPE_E_TAG:
7764                 l2_tn_info->e_tag_fwd_en = FALSE;
7765                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7766                 break;
7767         default:
7768                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7769                 ret = -EINVAL;
7770                 break;
7771         }
7772
7773         return ret;
7774 }
7775
7776 static int
7777 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7778                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7779                              bool en)
7780 {
7781         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7782         int ret = 0;
7783         uint32_t vmtir, vmvir;
7784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7785
7786         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7787                 PMD_DRV_LOG(ERR,
7788                             "VF id %u should be less than %u",
7789                             l2_tunnel->vf_id,
7790                             pci_dev->max_vfs);
7791                 return -EINVAL;
7792         }
7793
7794         if (hw->mac.type != ixgbe_mac_X550 &&
7795             hw->mac.type != ixgbe_mac_X550EM_x &&
7796             hw->mac.type != ixgbe_mac_X550EM_a) {
7797                 return -ENOTSUP;
7798         }
7799
7800         if (en)
7801                 vmtir = l2_tunnel->tunnel_id;
7802         else
7803                 vmtir = 0;
7804
7805         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7806
7807         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7808         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7809         if (en)
7810                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7811         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7812
7813         return ret;
7814 }
7815
7816 /* Enable l2 tunnel tag insertion */
7817 static int
7818 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7819                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7820 {
7821         int ret = 0;
7822
7823         switch (l2_tunnel->l2_tunnel_type) {
7824         case RTE_L2_TUNNEL_TYPE_E_TAG:
7825                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7826                 break;
7827         default:
7828                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7829                 ret = -EINVAL;
7830                 break;
7831         }
7832
7833         return ret;
7834 }
7835
7836 /* Disable l2 tunnel tag insertion */
7837 static int
7838 ixgbe_dev_l2_tunnel_insertion_disable
7839         (struct rte_eth_dev *dev,
7840          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7841 {
7842         int ret = 0;
7843
7844         switch (l2_tunnel->l2_tunnel_type) {
7845         case RTE_L2_TUNNEL_TYPE_E_TAG:
7846                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7847                 break;
7848         default:
7849                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7850                 ret = -EINVAL;
7851                 break;
7852         }
7853
7854         return ret;
7855 }
7856
7857 static int
7858 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7859                              bool en)
7860 {
7861         int ret = 0;
7862         uint32_t qde;
7863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7864
7865         if (hw->mac.type != ixgbe_mac_X550 &&
7866             hw->mac.type != ixgbe_mac_X550EM_x &&
7867             hw->mac.type != ixgbe_mac_X550EM_a) {
7868                 return -ENOTSUP;
7869         }
7870
7871         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7872         if (en)
7873                 qde |= IXGBE_QDE_STRIP_TAG;
7874         else
7875                 qde &= ~IXGBE_QDE_STRIP_TAG;
7876         qde &= ~IXGBE_QDE_READ;
7877         qde |= IXGBE_QDE_WRITE;
7878         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7879
7880         return ret;
7881 }
7882
7883 /* Enable l2 tunnel tag stripping */
7884 static int
7885 ixgbe_dev_l2_tunnel_stripping_enable
7886         (struct rte_eth_dev *dev,
7887          enum rte_eth_tunnel_type l2_tunnel_type)
7888 {
7889         int ret = 0;
7890
7891         switch (l2_tunnel_type) {
7892         case RTE_L2_TUNNEL_TYPE_E_TAG:
7893                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7894                 break;
7895         default:
7896                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7897                 ret = -EINVAL;
7898                 break;
7899         }
7900
7901         return ret;
7902 }
7903
7904 /* Disable l2 tunnel tag stripping */
7905 static int
7906 ixgbe_dev_l2_tunnel_stripping_disable
7907         (struct rte_eth_dev *dev,
7908          enum rte_eth_tunnel_type l2_tunnel_type)
7909 {
7910         int ret = 0;
7911
7912         switch (l2_tunnel_type) {
7913         case RTE_L2_TUNNEL_TYPE_E_TAG:
7914                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7915                 break;
7916         default:
7917                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7918                 ret = -EINVAL;
7919                 break;
7920         }
7921
7922         return ret;
7923 }
7924
7925 /* Enable/disable l2 tunnel offload functions */
7926 static int
7927 ixgbe_dev_l2_tunnel_offload_set
7928         (struct rte_eth_dev *dev,
7929          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7930          uint32_t mask,
7931          uint8_t en)
7932 {
7933         int ret = 0;
7934
7935         if (l2_tunnel == NULL)
7936                 return -EINVAL;
7937
7938         ret = -EINVAL;
7939         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7940                 if (en)
7941                         ret = ixgbe_dev_l2_tunnel_enable(
7942                                 dev,
7943                                 l2_tunnel->l2_tunnel_type);
7944                 else
7945                         ret = ixgbe_dev_l2_tunnel_disable(
7946                                 dev,
7947                                 l2_tunnel->l2_tunnel_type);
7948         }
7949
7950         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7951                 if (en)
7952                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7953                                 dev,
7954                                 l2_tunnel);
7955                 else
7956                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7957                                 dev,
7958                                 l2_tunnel);
7959         }
7960
7961         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7962                 if (en)
7963                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7964                                 dev,
7965                                 l2_tunnel->l2_tunnel_type);
7966                 else
7967                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7968                                 dev,
7969                                 l2_tunnel->l2_tunnel_type);
7970         }
7971
7972         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7973                 if (en)
7974                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7975                                 dev,
7976                                 l2_tunnel->l2_tunnel_type);
7977                 else
7978                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7979                                 dev,
7980                                 l2_tunnel->l2_tunnel_type);
7981         }
7982
7983         return ret;
7984 }
7985
7986 static int
7987 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7988                         uint16_t port)
7989 {
7990         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7991         IXGBE_WRITE_FLUSH(hw);
7992
7993         return 0;
7994 }
7995
7996 /* There's only one register for VxLAN UDP port.
7997  * So, we cannot add several ports. Will update it.
7998  */
7999 static int
8000 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8001                      uint16_t port)
8002 {
8003         if (port == 0) {
8004                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8005                 return -EINVAL;
8006         }
8007
8008         return ixgbe_update_vxlan_port(hw, port);
8009 }
8010
8011 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8012  * UDP port, it must have a value.
8013  * So, will reset it to the original value 0.
8014  */
8015 static int
8016 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8017                      uint16_t port)
8018 {
8019         uint16_t cur_port;
8020
8021         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8022
8023         if (cur_port != port) {
8024                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8025                 return -EINVAL;
8026         }
8027
8028         return ixgbe_update_vxlan_port(hw, 0);
8029 }
8030
8031 /* Add UDP tunneling port */
8032 static int
8033 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8034                               struct rte_eth_udp_tunnel *udp_tunnel)
8035 {
8036         int ret = 0;
8037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8038
8039         if (hw->mac.type != ixgbe_mac_X550 &&
8040             hw->mac.type != ixgbe_mac_X550EM_x &&
8041             hw->mac.type != ixgbe_mac_X550EM_a) {
8042                 return -ENOTSUP;
8043         }
8044
8045         if (udp_tunnel == NULL)
8046                 return -EINVAL;
8047
8048         switch (udp_tunnel->prot_type) {
8049         case RTE_TUNNEL_TYPE_VXLAN:
8050                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8051                 break;
8052
8053         case RTE_TUNNEL_TYPE_GENEVE:
8054         case RTE_TUNNEL_TYPE_TEREDO:
8055                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8056                 ret = -EINVAL;
8057                 break;
8058
8059         default:
8060                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8061                 ret = -EINVAL;
8062                 break;
8063         }
8064
8065         return ret;
8066 }
8067
8068 /* Remove UDP tunneling port */
8069 static int
8070 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8071                               struct rte_eth_udp_tunnel *udp_tunnel)
8072 {
8073         int ret = 0;
8074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8075
8076         if (hw->mac.type != ixgbe_mac_X550 &&
8077             hw->mac.type != ixgbe_mac_X550EM_x &&
8078             hw->mac.type != ixgbe_mac_X550EM_a) {
8079                 return -ENOTSUP;
8080         }
8081
8082         if (udp_tunnel == NULL)
8083                 return -EINVAL;
8084
8085         switch (udp_tunnel->prot_type) {
8086         case RTE_TUNNEL_TYPE_VXLAN:
8087                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8088                 break;
8089         case RTE_TUNNEL_TYPE_GENEVE:
8090         case RTE_TUNNEL_TYPE_TEREDO:
8091                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8092                 ret = -EINVAL;
8093                 break;
8094         default:
8095                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8096                 ret = -EINVAL;
8097                 break;
8098         }
8099
8100         return ret;
8101 }
8102
8103 static void
8104 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8105 {
8106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8107
8108         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8109 }
8110
8111 static void
8112 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8113 {
8114         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8115
8116         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8117 }
8118
8119 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8120 {
8121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8122         u32 in_msg = 0;
8123
8124         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8125                 return;
8126
8127         /* PF reset VF event */
8128         if (in_msg == IXGBE_PF_CONTROL_MSG)
8129                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8130                                               NULL, NULL);
8131 }
8132
8133 static int
8134 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8135 {
8136         uint32_t eicr;
8137         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8138         struct ixgbe_interrupt *intr =
8139                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8140         ixgbevf_intr_disable(hw);
8141
8142         /* read-on-clear nic registers here */
8143         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8144         intr->flags = 0;
8145
8146         /* only one misc vector supported - mailbox */
8147         eicr &= IXGBE_VTEICR_MASK;
8148         if (eicr == IXGBE_MISC_VEC_ID)
8149                 intr->flags |= IXGBE_FLAG_MAILBOX;
8150
8151         return 0;
8152 }
8153
8154 static int
8155 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8156 {
8157         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8158         struct ixgbe_interrupt *intr =
8159                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8160
8161         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8162                 ixgbevf_mbx_process(dev);
8163                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8164         }
8165
8166         ixgbevf_intr_enable(hw);
8167
8168         return 0;
8169 }
8170
8171 static void
8172 ixgbevf_dev_interrupt_handler(void *param)
8173 {
8174         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8175
8176         ixgbevf_dev_interrupt_get_status(dev);
8177         ixgbevf_dev_interrupt_action(dev);
8178 }
8179
8180 /**
8181  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8182  *  @hw: pointer to hardware structure
8183  *
8184  *  Stops the transmit data path and waits for the HW to internally empty
8185  *  the Tx security block
8186  **/
8187 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8188 {
8189 #define IXGBE_MAX_SECTX_POLL 40
8190
8191         int i;
8192         int sectxreg;
8193
8194         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8195         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8196         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8197         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8198                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8199                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8200                         break;
8201                 /* Use interrupt-safe sleep just in case */
8202                 usec_delay(1000);
8203         }
8204
8205         /* For informational purposes only */
8206         if (i >= IXGBE_MAX_SECTX_POLL)
8207                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8208                          "path fully disabled.  Continuing with init.");
8209
8210         return IXGBE_SUCCESS;
8211 }
8212
8213 /**
8214  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8215  *  @hw: pointer to hardware structure
8216  *
8217  *  Enables the transmit data path.
8218  **/
8219 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8220 {
8221         uint32_t sectxreg;
8222
8223         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8224         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8225         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8226         IXGBE_WRITE_FLUSH(hw);
8227
8228         return IXGBE_SUCCESS;
8229 }
8230
8231 /* restore n-tuple filter */
8232 static inline void
8233 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8234 {
8235         struct ixgbe_filter_info *filter_info =
8236                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8237         struct ixgbe_5tuple_filter *node;
8238
8239         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8240                 ixgbe_inject_5tuple_filter(dev, node);
8241         }
8242 }
8243
8244 /* restore ethernet type filter */
8245 static inline void
8246 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8247 {
8248         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8249         struct ixgbe_filter_info *filter_info =
8250                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8251         int i;
8252
8253         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8254                 if (filter_info->ethertype_mask & (1 << i)) {
8255                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8256                                         filter_info->ethertype_filters[i].etqf);
8257                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8258                                         filter_info->ethertype_filters[i].etqs);
8259                         IXGBE_WRITE_FLUSH(hw);
8260                 }
8261         }
8262 }
8263
8264 /* restore SYN filter */
8265 static inline void
8266 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8267 {
8268         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8269         struct ixgbe_filter_info *filter_info =
8270                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8271         uint32_t synqf;
8272
8273         synqf = filter_info->syn_info;
8274
8275         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8276                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8277                 IXGBE_WRITE_FLUSH(hw);
8278         }
8279 }
8280
8281 /* restore L2 tunnel filter */
8282 static inline void
8283 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8284 {
8285         struct ixgbe_l2_tn_info *l2_tn_info =
8286                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8287         struct ixgbe_l2_tn_filter *node;
8288         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8289
8290         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8291                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8292                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8293                 l2_tn_conf.pool           = node->pool;
8294                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8295         }
8296 }
8297
8298 static int
8299 ixgbe_filter_restore(struct rte_eth_dev *dev)
8300 {
8301         ixgbe_ntuple_filter_restore(dev);
8302         ixgbe_ethertype_filter_restore(dev);
8303         ixgbe_syn_filter_restore(dev);
8304         ixgbe_fdir_filter_restore(dev);
8305         ixgbe_l2_tn_filter_restore(dev);
8306
8307         return 0;
8308 }
8309
8310 static void
8311 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8312 {
8313         struct ixgbe_l2_tn_info *l2_tn_info =
8314                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8315         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8316
8317         if (l2_tn_info->e_tag_en)
8318                 (void)ixgbe_e_tag_enable(hw);
8319
8320         if (l2_tn_info->e_tag_fwd_en)
8321                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8322
8323         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8324 }
8325
8326 /* remove all the n-tuple filters */
8327 void
8328 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8329 {
8330         struct ixgbe_filter_info *filter_info =
8331                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8332         struct ixgbe_5tuple_filter *p_5tuple;
8333
8334         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8335                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8336 }
8337
8338 /* remove all the ether type filters */
8339 void
8340 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8341 {
8342         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8343         struct ixgbe_filter_info *filter_info =
8344                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8345         int i;
8346
8347         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8348                 if (filter_info->ethertype_mask & (1 << i) &&
8349                     !filter_info->ethertype_filters[i].conf) {
8350                         (void)ixgbe_ethertype_filter_remove(filter_info,
8351                                                             (uint8_t)i);
8352                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8353                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8354                         IXGBE_WRITE_FLUSH(hw);
8355                 }
8356         }
8357 }
8358
8359 /* remove the SYN filter */
8360 void
8361 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8362 {
8363         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8364         struct ixgbe_filter_info *filter_info =
8365                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8366
8367         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8368                 filter_info->syn_info = 0;
8369
8370                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8371                 IXGBE_WRITE_FLUSH(hw);
8372         }
8373 }
8374
8375 /* remove all the L2 tunnel filters */
8376 int
8377 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8378 {
8379         struct ixgbe_l2_tn_info *l2_tn_info =
8380                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8381         struct ixgbe_l2_tn_filter *l2_tn_filter;
8382         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8383         int ret = 0;
8384
8385         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8386                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8387                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8388                 l2_tn_conf.pool           = l2_tn_filter->pool;
8389                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8390                 if (ret < 0)
8391                         return ret;
8392         }
8393
8394         return 0;
8395 }
8396
8397 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8398 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8399 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8400 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8401 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8402 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");