drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 #define IXGBE_HKEY_MAX_INDEX 10
 104
 105 /* Additional timesync values. */
 106 #define NSEC_PER_SEC             1000000000L
 107 #define IXGBE_INCVAL_10GB        0x66666666
 108 #define IXGBE_INCVAL_1GB         0x40000000
 109 #define IXGBE_INCVAL_100         0x50000000
 110 #define IXGBE_INCVAL_SHIFT_10GB  28
 111 #define IXGBE_INCVAL_SHIFT_1GB   24
 112 #define IXGBE_INCVAL_SHIFT_100   21
 113 #define IXGBE_INCVAL_SHIFT_82599 7
 114 #define IXGBE_INCPER_SHIFT_82599 24
 115
 116 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 117
 118 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 119 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 120 #define DEFAULT_ETAG_ETYPE                     0x893f
 121 #define IXGBE_ETAG_ETYPE                       0x00005084
 122 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 123 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 124 #define IXGBE_RAH_ADTYPE                       0x40000000
 125 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 126 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 127 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 128 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 129 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 130 #define IXGBE_VTEICR_MASK                      0x07
 131
 132 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 133 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 134
 135 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 136 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 154                                 int wait_to_complete);
 155 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *stats);
 157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstat *xstats, unsigned n);
 159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 160                                   struct rte_eth_xstat *xstats, unsigned n);
 161 static int
 162 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 163                 uint64_t *values, unsigned int n);
 164 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         unsigned int size);
 169 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 171 static int ixgbe_dev_xstats_get_names_by_id(
 172         struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names,
 174         const uint64_t *ids,
 175         unsigned int limit);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 181                                  size_t fw_size);
 182 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 183                                struct rte_eth_dev_info *dev_info);
 184 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 185 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 186                                  struct rte_eth_dev_info *dev_info);
 187 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 188
 189 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 190                 uint16_t vlan_id, int on);
 191 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 192                                enum rte_vlan_type vlan_type,
 193                                uint16_t tpid_id);
 194 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 195                 uint16_t queue, bool on);
 196 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 197                 int on);
 198 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 200 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 201 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 202 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 203
 204 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 205 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 206 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 209                                struct rte_eth_fc_conf *fc_conf);
 210 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 211                 struct rte_eth_pfc_conf *pfc_conf);
 212 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 220 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 224                                       struct rte_intr_handle *handle);
 225 static void ixgbe_dev_interrupt_handler(void *param);
 226 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 227 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 228                          uint32_t index, uint32_t pool);
 229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 230 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 231                                            struct ether_addr *mac_addr);
 232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 233 static bool is_device_supported(struct rte_eth_dev *dev,
 234                                 struct rte_pci_driver *drv);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 242                                    int wait_to_complete);
 243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 247 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 249                 struct rte_eth_stats *stats);
 250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 252                 uint16_t vlan_id, int on);
 253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                 uint16_t queue, int on);
 255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 258                                             uint16_t queue_id);
 259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 260                                              uint16_t queue_id);
 261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 262                                  uint8_t queue, uint8_t msix_vector);
 263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 266
 267 /* For Eth VMDQ APIs support */
 268 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 269                 ether_addr * mac_addr, uint8_t on);
 270 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 271 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 272                 struct rte_eth_mirror_conf *mirror_conf,
 273                 uint8_t rule_id, uint8_t on);
 274 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 275                 uint8_t rule_id);
 276 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                           uint16_t queue_id);
 278 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                            uint16_t queue_id);
 280 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                uint8_t queue, uint8_t msix_vector);
 282 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 283
 284 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                 struct ether_addr *mac_addr,
 286                                 uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter);
 292 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 293                         enum rte_filter_op filter_op,
 294                         void *arg);
 295 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 298                         struct ixgbe_5tuple_filter *filter);
 299 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 300                                 enum rte_filter_op filter_op,
 301                                 void *arg);
 302 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter);
 304 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 305                                 enum rte_filter_op filter_op,
 306                                 void *arg);
 307 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 308                         struct rte_eth_ethertype_filter *filter);
 309 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 310                      enum rte_filter_type filter_type,
 311                      enum rte_filter_op filter_op,
 312                      void *arg);
 313 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 314
 315 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 316                                       struct ether_addr *mc_addr_set,
 317                                       uint32_t nb_mc_addr);
 318 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 319                                    struct rte_eth_dcb_info *dcb_info);
 320
 321 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 323                             struct rte_dev_reg_info *regs);
 324 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 325 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 328                                 struct rte_dev_eeprom_info *eeprom);
 329
 330 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 331 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 332                                 struct rte_dev_reg_info *regs);
 333
 334 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 335 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 336 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 337                                             struct timespec *timestamp,
 338                                             uint32_t flags);
 339 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp);
 341 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 342 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 343                                    struct timespec *timestamp);
 344 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 345                                    const struct timespec *timestamp);
 346 static void ixgbevf_dev_interrupt_handler(void *param);
 347
 348 static int ixgbe_dev_l2_tunnel_eth_type_conf
 349         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 350 static int ixgbe_dev_l2_tunnel_offload_set
 351         (struct rte_eth_dev *dev,
 352          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 353          uint32_t mask,
 354          uint8_t en);
 355 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 356                                              enum rte_filter_op filter_op,
 357                                              void *arg);
 358
 359 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 360                                          struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 364 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 365
 366 /*
 367  * Define VF Stats MACRO for Non "cleared on read" register
 368  */
 369 #define UPDATE_VF_STAT(reg, last, cur)                          \
 370 {                                                               \
 371         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 372         cur += (latest - last) & UINT_MAX;                      \
 373         last = latest;                                          \
 374 }
 375
 376 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 377 {                                                                \
 378         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 379         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 380         u64 latest = ((new_msb << 32) | new_lsb);                \
 381         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 382         last = latest;                                           \
 383 }
 384
 385 #define IXGBE_SET_HWSTRIP(h, q) do {\
 386                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 387                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 388                 (h)->bitmap[idx] |= 1 << bit;\
 389         } while (0)
 390
 391 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 392                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] &= ~(1 << bit);\
 395         } while (0)
 396
 397 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 398                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 400                 (r) = (h)->bitmap[idx] >> bit & 1;\
 401         } while (0)
 402
 403 int ixgbe_logtype_init;
 404 int ixgbe_logtype_driver;
 405
 406 /*
 407  * The set of PCI devices this driver supports
 408  */
 409 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 458 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 460 #endif
 461         { .vendor_id = 0, /* sentinel */ },
 462 };
 463
 464 /*
 465  * The set of PCI devices this driver supports (for 82599 VF)
 466  */
 467 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct rte_eth_desc_lim rx_desc_lim = {
 482         .nb_max = IXGBE_MAX_RING_DESC,
 483         .nb_min = IXGBE_MIN_RING_DESC,
 484         .nb_align = IXGBE_RXD_ALIGN,
 485 };
 486
 487 static const struct rte_eth_desc_lim tx_desc_lim = {
 488         .nb_max = IXGBE_MAX_RING_DESC,
 489         .nb_min = IXGBE_MIN_RING_DESC,
 490         .nb_align = IXGBE_TXD_ALIGN,
 491         .nb_seg_max = IXGBE_TX_MAX_SEG,
 492         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 493 };
 494
 495 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 496         .dev_configure        = ixgbe_dev_configure,
 497         .dev_start            = ixgbe_dev_start,
 498         .dev_stop             = ixgbe_dev_stop,
 499         .dev_set_link_up    = ixgbe_dev_set_link_up,
 500         .dev_set_link_down  = ixgbe_dev_set_link_down,
 501         .dev_close            = ixgbe_dev_close,
 502         .dev_reset            = ixgbe_dev_reset,
 503         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 504         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 505         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 506         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 507         .link_update          = ixgbe_dev_link_update,
 508         .stats_get            = ixgbe_dev_stats_get,
 509         .xstats_get           = ixgbe_dev_xstats_get,
 510         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 511         .stats_reset          = ixgbe_dev_stats_reset,
 512         .xstats_reset         = ixgbe_dev_xstats_reset,
 513         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 514         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 515         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 516         .fw_version_get       = ixgbe_fw_version_get,
 517         .dev_infos_get        = ixgbe_dev_info_get,
 518         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 519         .mtu_set              = ixgbe_dev_mtu_set,
 520         .vlan_filter_set      = ixgbe_vlan_filter_set,
 521         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 522         .vlan_offload_set     = ixgbe_vlan_offload_set,
 523         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 524         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 525         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 526         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 527         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 528         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 529         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 530         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 531         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 532         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 533         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 534         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 535         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 536         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 537         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 538         .dev_led_on           = ixgbe_dev_led_on,
 539         .dev_led_off          = ixgbe_dev_led_off,
 540         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 541         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 542         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 543         .mac_addr_add         = ixgbe_add_rar,
 544         .mac_addr_remove      = ixgbe_remove_rar,
 545         .mac_addr_set         = ixgbe_set_default_mac_addr,
 546         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 547         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 548         .mirror_rule_set      = ixgbe_mirror_rule_set,
 549         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 550         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 551         .reta_update          = ixgbe_dev_rss_reta_update,
 552         .reta_query           = ixgbe_dev_rss_reta_query,
 553         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 554         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 555         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 556         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 557         .rxq_info_get         = ixgbe_rxq_info_get,
 558         .txq_info_get         = ixgbe_txq_info_get,
 559         .timesync_enable      = ixgbe_timesync_enable,
 560         .timesync_disable     = ixgbe_timesync_disable,
 561         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 562         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 563         .get_reg              = ixgbe_get_regs,
 564         .get_eeprom_length    = ixgbe_get_eeprom_length,
 565         .get_eeprom           = ixgbe_get_eeprom,
 566         .set_eeprom           = ixgbe_set_eeprom,
 567         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 568         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 569         .timesync_read_time   = ixgbe_timesync_read_time,
 570         .timesync_write_time  = ixgbe_timesync_write_time,
 571         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 572         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 573         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 574         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 575         .tm_ops_get           = ixgbe_tm_ops_get,
 576 };
 577
 578 /*
 579  * dev_ops for virtual function, bare necessities for basic vf
 580  * operation have been implemented
 581  */
 582 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 583         .dev_configure        = ixgbevf_dev_configure,
 584         .dev_start            = ixgbevf_dev_start,
 585         .dev_stop             = ixgbevf_dev_stop,
 586         .link_update          = ixgbevf_dev_link_update,
 587         .stats_get            = ixgbevf_dev_stats_get,
 588         .xstats_get           = ixgbevf_dev_xstats_get,
 589         .stats_reset          = ixgbevf_dev_stats_reset,
 590         .xstats_reset         = ixgbevf_dev_stats_reset,
 591         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 592         .dev_close            = ixgbevf_dev_close,
 593         .dev_reset            = ixgbevf_dev_reset,
 594         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 595         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 596         .dev_infos_get        = ixgbevf_dev_info_get,
 597         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 598         .mtu_set              = ixgbevf_dev_set_mtu,
 599         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 600         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 601         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 602         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 603         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 604         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 605         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 606         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 607         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 608         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 609         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 610         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 611         .mac_addr_add         = ixgbevf_add_mac_addr,
 612         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 613         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 614         .rxq_info_get         = ixgbe_rxq_info_get,
 615         .txq_info_get         = ixgbe_txq_info_get,
 616         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 617         .get_reg              = ixgbevf_get_regs,
 618         .reta_update          = ixgbe_dev_rss_reta_update,
 619         .reta_query           = ixgbe_dev_rss_reta_query,
 620         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 621         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 622 };
 623
 624 /* store statistics names and its offset in stats structure */
 625 struct rte_ixgbe_xstats_name_off {
 626         char name[RTE_ETH_XSTATS_NAME_SIZE];
 627         unsigned offset;
 628 };
 629
 630 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 631         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 632         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 633         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 634         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 635         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 636         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 637         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 638         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 639         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 640         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 641         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 642         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 643         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 644         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 645         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 646                 prc1023)},
 647         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 648                 prc1522)},
 649         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 650         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 651         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 652         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 653         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 654         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 655         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 656         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 657         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 658         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 659         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 660         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 661         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 662         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 663         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 664         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 665         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 666                 ptc1023)},
 667         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 668                 ptc1522)},
 669         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 670         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 671         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 672         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 673
 674         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 675                 fdirustat_add)},
 676         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 677                 fdirustat_remove)},
 678         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 679                 fdirfstat_fadd)},
 680         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 681                 fdirfstat_fremove)},
 682         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 683                 fdirmatch)},
 684         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 685                 fdirmiss)},
 686
 687         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 688         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 689         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 690                 fclast)},
 691         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 692         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 693         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 694         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 695         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 696                 fcoe_noddp)},
 697         {"rx_fcoe_no_direct_data_placement_ext_buff",
 698                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 699
 700         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 701                 lxontxc)},
 702         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 703                 lxonrxc)},
 704         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxofftxc)},
 706         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxoffrxc)},
 708         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 709 };
 710
 711 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 712                            sizeof(rte_ixgbe_stats_strings[0]))
 713
 714 /* MACsec statistics */
 715 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 716         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 717                 out_pkts_untagged)},
 718         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 719                 out_pkts_encrypted)},
 720         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_protected)},
 722         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_octets_encrypted)},
 724         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_octets_protected)},
 726         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_untagged)},
 728         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 729                 in_pkts_badtag)},
 730         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_nosci)},
 732         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_unknownsci)},
 734         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 735                 in_octets_decrypted)},
 736         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 737                 in_octets_validated)},
 738         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_unchecked)},
 740         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_delayed)},
 742         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_late)},
 744         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_ok)},
 746         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_invalid)},
 748         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_notvalid)},
 750         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_unusedsa)},
 752         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notusingsa)},
 754 };
 755
 756 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 757                            sizeof(rte_ixgbe_macsec_strings[0]))
 758
 759 /* Per-queue statistics */
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 761         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 762         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 763         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 764         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 765 };
 766
 767 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 768                            sizeof(rte_ixgbe_rxq_strings[0]))
 769 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 772         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 773         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 774         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 775                 pxon2offc)},
 776 };
 777
 778 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 779                            sizeof(rte_ixgbe_txq_strings[0]))
 780 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 781
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 783         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 784 };
 785
 786 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 787                 sizeof(rte_ixgbevf_stats_strings[0]))
 788
 789 /*
 790  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 791  */
 792 static inline int
 793 ixgbe_is_sfp(struct ixgbe_hw *hw)
 794 {
 795         switch (hw->phy.type) {
 796         case ixgbe_phy_sfp_avago:
 797         case ixgbe_phy_sfp_ftl:
 798         case ixgbe_phy_sfp_intel:
 799         case ixgbe_phy_sfp_unknown:
 800         case ixgbe_phy_sfp_passive_tyco:
 801         case ixgbe_phy_sfp_passive_unknown:
 802                 return 1;
 803         default:
 804                 return 0;
 805         }
 806 }
 807
 808 static inline int32_t
 809 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 810 {
 811         uint32_t ctrl_ext;
 812         int32_t status;
 813
 814         status = ixgbe_reset_hw(hw);
 815
 816         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 817         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 818         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 819         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 820         IXGBE_WRITE_FLUSH(hw);
 821
 822         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 823                 status = IXGBE_SUCCESS;
 824         return status;
 825 }
 826
 827 static inline void
 828 ixgbe_enable_intr(struct rte_eth_dev *dev)
 829 {
 830         struct ixgbe_interrupt *intr =
 831                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 832         struct ixgbe_hw *hw =
 833                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 834
 835         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 836         IXGBE_WRITE_FLUSH(hw);
 837 }
 838
 839 /*
 840  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 841  */
 842 static void
 843 ixgbe_disable_intr(struct ixgbe_hw *hw)
 844 {
 845         PMD_INIT_FUNC_TRACE();
 846
 847         if (hw->mac.type == ixgbe_mac_82598EB) {
 848                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 849         } else {
 850                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 853         }
 854         IXGBE_WRITE_FLUSH(hw);
 855 }
 856
 857 /*
 858  * This function resets queue statistics mapping registers.
 859  * From Niantic datasheet, Initialization of Statistics section:
 860  * "...if software requires the queue counters, the RQSMR and TQSM registers
 861  * must be re-programmed following a device reset.
 862  */
 863 static void
 864 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 865 {
 866         uint32_t i;
 867
 868         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 869                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 870                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 871         }
 872 }
 873
 874
 875 static int
 876 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 877                                   uint16_t queue_id,
 878                                   uint8_t stat_idx,
 879                                   uint8_t is_rx)
 880 {
 881 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 882 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 883 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 884
 885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 886         struct ixgbe_stat_mapping_registers *stat_mappings =
 887                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 888         uint32_t qsmr_mask = 0;
 889         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 890         uint32_t q_map;
 891         uint8_t n, offset;
 892
 893         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 894                 (hw->mac.type != ixgbe_mac_X540) &&
 895                 (hw->mac.type != ixgbe_mac_X550) &&
 896                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 897                 (hw->mac.type != ixgbe_mac_X550EM_a))
 898                 return -ENOSYS;
 899
 900         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 901                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 902                      queue_id, stat_idx);
 903
 904         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 905         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 906                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 907                 return -EIO;
 908         }
 909         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 910
 911         /* Now clear any previous stat_idx set */
 912         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 913         if (!is_rx)
 914                 stat_mappings->tqsm[n] &= ~clearing_mask;
 915         else
 916                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 917
 918         q_map = (uint32_t)stat_idx;
 919         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 920         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 921         if (!is_rx)
 922                 stat_mappings->tqsm[n] |= qsmr_mask;
 923         else
 924                 stat_mappings->rqsmr[n] |= qsmr_mask;
 925
 926         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 927                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 928                      queue_id, stat_idx);
 929         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 930                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 931
 932         /* Now write the mapping in the appropriate register */
 933         if (is_rx) {
 934                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 935                              stat_mappings->rqsmr[n], n);
 936                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 937         } else {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 939                              stat_mappings->tqsm[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 941         }
 942         return 0;
 943 }
 944
 945 static void
 946 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 947 {
 948         struct ixgbe_stat_mapping_registers *stat_mappings =
 949                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951         int i;
 952
 953         /* write whatever was in stat mapping table to the NIC */
 954         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 /* rx */
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 957
 958                 /* tx */
 959                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 960         }
 961 }
 962
 963 static void
 964 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 965 {
 966         uint8_t i;
 967         struct ixgbe_dcb_tc_config *tc;
 968         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 969
 970         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 971         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 972         for (i = 0; i < dcb_max_tc; i++) {
 973                 tc = &dcb_config->tc_config[i];
 974                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 975                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 976                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 977                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 978                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 979                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 980                 tc->pfc = ixgbe_dcb_pfc_disabled;
 981         }
 982
 983         /* Initialize default user to priority mapping, UPx->TC0 */
 984         tc = &dcb_config->tc_config[0];
 985         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 986         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 987         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 988                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 989                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 990         }
 991         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 992         dcb_config->pfc_mode_enable = false;
 993         dcb_config->vt_mode = true;
 994         dcb_config->round_robin_enable = false;
 995         /* support all DCB capabilities in 82599 */
 996         dcb_config->support.capabilities = 0xFF;
 997
 998         /*we only support 4 Tcs for X540, X550 */
 999         if (hw->mac.type == ixgbe_mac_X540 ||
1000                 hw->mac.type == ixgbe_mac_X550 ||
1001                 hw->mac.type == ixgbe_mac_X550EM_x ||
1002                 hw->mac.type == ixgbe_mac_X550EM_a) {
1003                 dcb_config->num_tcs.pg_tcs = 4;
1004                 dcb_config->num_tcs.pfc_tcs = 4;
1005         }
1006 }
1007
1008 /*
1009  * Ensure that all locks are released before first NVM or PHY access
1010  */
1011 static void
1012 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1013 {
1014         uint16_t mask;
1015
1016         /*
1017          * Phy lock should not fail in this early stage. If this is the case,
1018          * it is due to an improper exit of the application.
1019          * So force the release of the faulty lock. Release of common lock
1020          * is done automatically by swfw_sync function.
1021          */
1022         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1023         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1024                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1025         }
1026         ixgbe_release_swfw_semaphore(hw, mask);
1027
1028         /*
1029          * These ones are more tricky since they are common to all ports; but
1030          * swfw_sync retries last long enough (1s) to be almost sure that if
1031          * lock can not be taken it is due to an improper lock of the
1032          * semaphore.
1033          */
1034         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1035         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1037         }
1038         ixgbe_release_swfw_semaphore(hw, mask);
1039 }
1040
1041 /*
1042  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1043  * It returns 0 on success.
1044  */
1045 static int
1046 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1047 {
1048         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1049         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1050         struct ixgbe_hw *hw =
1051                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1052         struct ixgbe_vfta *shadow_vfta =
1053                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1054         struct ixgbe_hwstrip *hwstrip =
1055                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1056         struct ixgbe_dcb_config *dcb_config =
1057                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1058         struct ixgbe_filter_info *filter_info =
1059                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1060         struct ixgbe_bw_conf *bw_conf =
1061                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1062         uint32_t ctrl_ext;
1063         uint16_t csum;
1064         int diag, i;
1065
1066         PMD_INIT_FUNC_TRACE();
1067
1068         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1069         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1070         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1071         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1072
1073         /*
1074          * For secondary processes, we don't initialise any further as primary
1075          * has already done this work. Only check we don't need a different
1076          * RX and TX function.
1077          */
1078         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1079                 struct ixgbe_tx_queue *txq;
1080                 /* TX queue function in primary, set by last queue initialized
1081                  * Tx queue may not initialized by primary process
1082                  */
1083                 if (eth_dev->data->tx_queues) {
1084                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1085                         ixgbe_set_tx_function(eth_dev, txq);
1086                 } else {
1087                         /* Use default TX function if we get here */
1088                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1089                                      "Using default TX function.");
1090                 }
1091
1092                 ixgbe_set_rx_function(eth_dev);
1093
1094                 return 0;
1095         }
1096
1097         rte_eth_copy_pci_info(eth_dev, pci_dev);
1098
1099         /* Vendor and Device ID need to be set before init of shared code */
1100         hw->device_id = pci_dev->id.device_id;
1101         hw->vendor_id = pci_dev->id.vendor_id;
1102         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1103         hw->allow_unsupported_sfp = 1;
1104
1105         /* Initialize the shared code (base driver) */
1106 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1107         diag = ixgbe_bypass_init_shared_code(hw);
1108 #else
1109         diag = ixgbe_init_shared_code(hw);
1110 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1111
1112         if (diag != IXGBE_SUCCESS) {
1113                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1114                 return -EIO;
1115         }
1116
1117         /* pick up the PCI bus settings for reporting later */
1118         ixgbe_get_bus_info(hw);
1119
1120         /* Unlock any pending hardware semaphore */
1121         ixgbe_swfw_lock_reset(hw);
1122
1123 #ifdef RTE_LIBRTE_SECURITY
1124         /* Initialize security_ctx only for primary process*/
1125         if (ixgbe_ipsec_ctx_create(eth_dev))
1126                 return -ENOMEM;
1127 #endif
1128
1129         /* Initialize DCB configuration*/
1130         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1131         ixgbe_dcb_init(hw, dcb_config);
1132         /* Get Hardware Flow Control setting */
1133         hw->fc.requested_mode = ixgbe_fc_full;
1134         hw->fc.current_mode = ixgbe_fc_full;
1135         hw->fc.pause_time = IXGBE_FC_PAUSE;
1136         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1137                 hw->fc.low_water[i] = IXGBE_FC_LO;
1138                 hw->fc.high_water[i] = IXGBE_FC_HI;
1139         }
1140         hw->fc.send_xon = 1;
1141
1142         /* Make sure we have a good EEPROM before we read from it */
1143         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1144         if (diag != IXGBE_SUCCESS) {
1145                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1146                 return -EIO;
1147         }
1148
1149 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1150         diag = ixgbe_bypass_init_hw(hw);
1151 #else
1152         diag = ixgbe_init_hw(hw);
1153 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1154
1155         /*
1156          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1157          * is called too soon after the kernel driver unbinding/binding occurs.
1158          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1159          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1160          * also called. See ixgbe_identify_phy_82599(). The reason for the
1161          * failure is not known, and only occuts when virtualisation features
1162          * are disabled in the bios. A delay of 100ms  was found to be enough by
1163          * trial-and-error, and is doubled to be safe.
1164          */
1165         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1166                 rte_delay_ms(200);
1167                 diag = ixgbe_init_hw(hw);
1168         }
1169
1170         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1171                 diag = IXGBE_SUCCESS;
1172
1173         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1174                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1175                              "LOM.  Please be aware there may be issues associated "
1176                              "with your hardware.");
1177                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1178                              "please contact your Intel or hardware representative "
1179                              "who provided you with this hardware.");
1180         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1181                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1182         if (diag) {
1183                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1184                 return -EIO;
1185         }
1186
1187         /* Reset the hw statistics */
1188         ixgbe_dev_stats_reset(eth_dev);
1189
1190         /* disable interrupt */
1191         ixgbe_disable_intr(hw);
1192
1193         /* reset mappings for queue statistics hw counters*/
1194         ixgbe_reset_qstat_mappings(hw);
1195
1196         /* Allocate memory for storing MAC addresses */
1197         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1198                                                hw->mac.num_rar_entries, 0);
1199         if (eth_dev->data->mac_addrs == NULL) {
1200                 PMD_INIT_LOG(ERR,
1201                              "Failed to allocate %u bytes needed to store "
1202                              "MAC addresses",
1203                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1204                 return -ENOMEM;
1205         }
1206         /* Copy the permanent MAC address */
1207         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1208                         &eth_dev->data->mac_addrs[0]);
1209
1210         /* Allocate memory for storing hash filter MAC addresses */
1211         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1212                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1213         if (eth_dev->data->hash_mac_addrs == NULL) {
1214                 PMD_INIT_LOG(ERR,
1215                              "Failed to allocate %d bytes needed to store MAC addresses",
1216                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1217                 return -ENOMEM;
1218         }
1219
1220         /* initialize the vfta */
1221         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1222
1223         /* initialize the hw strip bitmap*/
1224         memset(hwstrip, 0, sizeof(*hwstrip));
1225
1226         /* initialize PF if max_vfs not zero */
1227         ixgbe_pf_host_init(eth_dev);
1228
1229         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1230         /* let hardware know driver is loaded */
1231         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1232         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1233         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1234         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1235         IXGBE_WRITE_FLUSH(hw);
1236
1237         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1238                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1239                              (int) hw->mac.type, (int) hw->phy.type,
1240                              (int) hw->phy.sfp_type);
1241         else
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type);
1244
1245         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1246                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1247                      pci_dev->id.device_id);
1248
1249         rte_intr_callback_register(intr_handle,
1250                                    ixgbe_dev_interrupt_handler, eth_dev);
1251
1252         /* enable uio/vfio intr/eventfd mapping */
1253         rte_intr_enable(intr_handle);
1254
1255         /* enable support intr */
1256         ixgbe_enable_intr(eth_dev);
1257
1258         /* initialize filter info */
1259         memset(filter_info, 0,
1260                sizeof(struct ixgbe_filter_info));
1261
1262         /* initialize 5tuple filter list */
1263         TAILQ_INIT(&filter_info->fivetuple_list);
1264
1265         /* initialize flow director filter list & hash */
1266         ixgbe_fdir_filter_init(eth_dev);
1267
1268         /* initialize l2 tunnel filter list & hash */
1269         ixgbe_l2_tn_filter_init(eth_dev);
1270
1271         /* initialize flow filter lists */
1272         ixgbe_filterlist_init();
1273
1274         /* initialize bandwidth configuration info */
1275         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1276
1277         /* initialize Traffic Manager configuration */
1278         ixgbe_tm_conf_init(eth_dev);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1285 {
1286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1287         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288         struct ixgbe_hw *hw;
1289
1290         PMD_INIT_FUNC_TRACE();
1291
1292         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1293                 return -EPERM;
1294
1295         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1296
1297         if (hw->adapter_stopped == 0)
1298                 ixgbe_dev_close(eth_dev);
1299
1300         eth_dev->dev_ops = NULL;
1301         eth_dev->rx_pkt_burst = NULL;
1302         eth_dev->tx_pkt_burst = NULL;
1303
1304         /* Unlock any pending hardware semaphore */
1305         ixgbe_swfw_lock_reset(hw);
1306
1307         /* disable uio intr before callback unregister */
1308         rte_intr_disable(intr_handle);
1309         rte_intr_callback_unregister(intr_handle,
1310                                      ixgbe_dev_interrupt_handler, eth_dev);
1311
1312         /* uninitialize PF if max_vfs not zero */
1313         ixgbe_pf_host_uninit(eth_dev);
1314
1315         rte_free(eth_dev->data->mac_addrs);
1316         eth_dev->data->mac_addrs = NULL;
1317
1318         rte_free(eth_dev->data->hash_mac_addrs);
1319         eth_dev->data->hash_mac_addrs = NULL;
1320
1321         /* remove all the fdir filters & hash */
1322         ixgbe_fdir_filter_uninit(eth_dev);
1323
1324         /* remove all the L2 tunnel filters & hash */
1325         ixgbe_l2_tn_filter_uninit(eth_dev);
1326
1327         /* Remove all ntuple filters of the device */
1328         ixgbe_ntuple_filter_uninit(eth_dev);
1329
1330         /* clear all the filters list */
1331         ixgbe_filterlist_flush();
1332
1333         /* Remove all Traffic Manager configuration */
1334         ixgbe_tm_conf_uninit(eth_dev);
1335
1336 #ifdef RTE_LIBRTE_SECURITY
1337         rte_free(eth_dev->security_ctx);
1338 #endif
1339
1340         return 0;
1341 }
1342
1343 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1344 {
1345         struct ixgbe_filter_info *filter_info =
1346                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1347         struct ixgbe_5tuple_filter *p_5tuple;
1348
1349         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1350                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1351                              p_5tuple,
1352                              entries);
1353                 rte_free(p_5tuple);
1354         }
1355         memset(filter_info->fivetuple_mask, 0,
1356                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1357
1358         return 0;
1359 }
1360
1361 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1362 {
1363         struct ixgbe_hw_fdir_info *fdir_info =
1364                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1365         struct ixgbe_fdir_filter *fdir_filter;
1366
1367                 if (fdir_info->hash_map)
1368                 rte_free(fdir_info->hash_map);
1369         if (fdir_info->hash_handle)
1370                 rte_hash_free(fdir_info->hash_handle);
1371
1372         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1373                 TAILQ_REMOVE(&fdir_info->fdir_list,
1374                              fdir_filter,
1375                              entries);
1376                 rte_free(fdir_filter);
1377         }
1378
1379         return 0;
1380 }
1381
1382 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1383 {
1384         struct ixgbe_l2_tn_info *l2_tn_info =
1385                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1386         struct ixgbe_l2_tn_filter *l2_tn_filter;
1387
1388         if (l2_tn_info->hash_map)
1389                 rte_free(l2_tn_info->hash_map);
1390         if (l2_tn_info->hash_handle)
1391                 rte_hash_free(l2_tn_info->hash_handle);
1392
1393         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1394                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1395                              l2_tn_filter,
1396                              entries);
1397                 rte_free(l2_tn_filter);
1398         }
1399
1400         return 0;
1401 }
1402
1403 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1404 {
1405         struct ixgbe_hw_fdir_info *fdir_info =
1406                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1407         char fdir_hash_name[RTE_HASH_NAMESIZE];
1408         struct rte_hash_parameters fdir_hash_params = {
1409                 .name = fdir_hash_name,
1410                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1411                 .key_len = sizeof(union ixgbe_atr_input),
1412                 .hash_func = rte_hash_crc,
1413                 .hash_func_init_val = 0,
1414                 .socket_id = rte_socket_id(),
1415         };
1416
1417         TAILQ_INIT(&fdir_info->fdir_list);
1418         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1419                  "fdir_%s", eth_dev->device->name);
1420         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1421         if (!fdir_info->hash_handle) {
1422                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1423                 return -EINVAL;
1424         }
1425         fdir_info->hash_map = rte_zmalloc("ixgbe",
1426                                           sizeof(struct ixgbe_fdir_filter *) *
1427                                           IXGBE_MAX_FDIR_FILTER_NUM,
1428                                           0);
1429         if (!fdir_info->hash_map) {
1430                 PMD_INIT_LOG(ERR,
1431                              "Failed to allocate memory for fdir hash map!");
1432                 return -ENOMEM;
1433         }
1434         fdir_info->mask_added = FALSE;
1435
1436         return 0;
1437 }
1438
1439 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1440 {
1441         struct ixgbe_l2_tn_info *l2_tn_info =
1442                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1443         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1444         struct rte_hash_parameters l2_tn_hash_params = {
1445                 .name = l2_tn_hash_name,
1446                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1447                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1448                 .hash_func = rte_hash_crc,
1449                 .hash_func_init_val = 0,
1450                 .socket_id = rte_socket_id(),
1451         };
1452
1453         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1454         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1455                  "l2_tn_%s", eth_dev->device->name);
1456         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1457         if (!l2_tn_info->hash_handle) {
1458                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1459                 return -EINVAL;
1460         }
1461         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1462                                    sizeof(struct ixgbe_l2_tn_filter *) *
1463                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1464                                    0);
1465         if (!l2_tn_info->hash_map) {
1466                 PMD_INIT_LOG(ERR,
1467                         "Failed to allocate memory for L2 TN hash map!");
1468                 return -ENOMEM;
1469         }
1470         l2_tn_info->e_tag_en = FALSE;
1471         l2_tn_info->e_tag_fwd_en = FALSE;
1472         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1473
1474         return 0;
1475 }
1476 /*
1477  * Negotiate mailbox API version with the PF.
1478  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1479  * Then we try to negotiate starting with the most recent one.
1480  * If all negotiation attempts fail, then we will proceed with
1481  * the default one (ixgbe_mbox_api_10).
1482  */
1483 static void
1484 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1485 {
1486         int32_t i;
1487
1488         /* start with highest supported, proceed down */
1489         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1490                 ixgbe_mbox_api_12,
1491                 ixgbe_mbox_api_11,
1492                 ixgbe_mbox_api_10,
1493         };
1494
1495         for (i = 0;
1496                         i != RTE_DIM(sup_ver) &&
1497                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1498                         i++)
1499                 ;
1500 }
1501
1502 static void
1503 generate_random_mac_addr(struct ether_addr *mac_addr)
1504 {
1505         uint64_t random;
1506
1507         /* Set Organizationally Unique Identifier (OUI) prefix. */
1508         mac_addr->addr_bytes[0] = 0x00;
1509         mac_addr->addr_bytes[1] = 0x09;
1510         mac_addr->addr_bytes[2] = 0xC0;
1511         /* Force indication of locally assigned MAC address. */
1512         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1513         /* Generate the last 3 bytes of the MAC address with a random number. */
1514         random = rte_rand();
1515         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1516 }
1517
1518 /*
1519  * Virtual Function device init
1520  */
1521 static int
1522 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1523 {
1524         int diag;
1525         uint32_t tc, tcs;
1526         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1527         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1528         struct ixgbe_hw *hw =
1529                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1530         struct ixgbe_vfta *shadow_vfta =
1531                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1532         struct ixgbe_hwstrip *hwstrip =
1533                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1534         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1535
1536         PMD_INIT_FUNC_TRACE();
1537
1538         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1539         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1540         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1541
1542         /* for secondary processes, we don't initialise any further as primary
1543          * has already done this work. Only check we don't need a different
1544          * RX function
1545          */
1546         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1547                 struct ixgbe_tx_queue *txq;
1548                 /* TX queue function in primary, set by last queue initialized
1549                  * Tx queue may not initialized by primary process
1550                  */
1551                 if (eth_dev->data->tx_queues) {
1552                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1553                         ixgbe_set_tx_function(eth_dev, txq);
1554                 } else {
1555                         /* Use default TX function if we get here */
1556                         PMD_INIT_LOG(NOTICE,
1557                                      "No TX queues configured yet. Using default TX function.");
1558                 }
1559
1560                 ixgbe_set_rx_function(eth_dev);
1561
1562                 return 0;
1563         }
1564
1565         rte_eth_copy_pci_info(eth_dev, pci_dev);
1566
1567         hw->device_id = pci_dev->id.device_id;
1568         hw->vendor_id = pci_dev->id.vendor_id;
1569         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1570
1571         /* initialize the vfta */
1572         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1573
1574         /* initialize the hw strip bitmap*/
1575         memset(hwstrip, 0, sizeof(*hwstrip));
1576
1577         /* Initialize the shared code (base driver) */
1578         diag = ixgbe_init_shared_code(hw);
1579         if (diag != IXGBE_SUCCESS) {
1580                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1581                 return -EIO;
1582         }
1583
1584         /* init_mailbox_params */
1585         hw->mbx.ops.init_params(hw);
1586
1587         /* Reset the hw statistics */
1588         ixgbevf_dev_stats_reset(eth_dev);
1589
1590         /* Disable the interrupts for VF */
1591         ixgbevf_intr_disable(hw);
1592
1593         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1594         diag = hw->mac.ops.reset_hw(hw);
1595
1596         /*
1597          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1598          * the underlying PF driver has not assigned a MAC address to the VF.
1599          * In this case, assign a random MAC address.
1600          */
1601         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1602                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1603                 return diag;
1604         }
1605
1606         /* negotiate mailbox API version to use with the PF. */
1607         ixgbevf_negotiate_api(hw);
1608
1609         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1610         ixgbevf_get_queues(hw, &tcs, &tc);
1611
1612         /* Allocate memory for storing MAC addresses */
1613         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1614                                                hw->mac.num_rar_entries, 0);
1615         if (eth_dev->data->mac_addrs == NULL) {
1616                 PMD_INIT_LOG(ERR,
1617                              "Failed to allocate %u bytes needed to store "
1618                              "MAC addresses",
1619                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1620                 return -ENOMEM;
1621         }
1622
1623         /* Generate a random MAC address, if none was assigned by PF. */
1624         if (is_zero_ether_addr(perm_addr)) {
1625                 generate_random_mac_addr(perm_addr);
1626                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1627                 if (diag) {
1628                         rte_free(eth_dev->data->mac_addrs);
1629                         eth_dev->data->mac_addrs = NULL;
1630                         return diag;
1631                 }
1632                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1633                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1634                              "%02x:%02x:%02x:%02x:%02x:%02x",
1635                              perm_addr->addr_bytes[0],
1636                              perm_addr->addr_bytes[1],
1637                              perm_addr->addr_bytes[2],
1638                              perm_addr->addr_bytes[3],
1639                              perm_addr->addr_bytes[4],
1640                              perm_addr->addr_bytes[5]);
1641         }
1642
1643         /* Copy the permanent MAC address */
1644         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1645
1646         /* reset the hardware with the new settings */
1647         diag = hw->mac.ops.start_hw(hw);
1648         switch (diag) {
1649         case  0:
1650                 break;
1651
1652         default:
1653                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1654                 return -EIO;
1655         }
1656
1657         rte_intr_callback_register(intr_handle,
1658                                    ixgbevf_dev_interrupt_handler, eth_dev);
1659         rte_intr_enable(intr_handle);
1660         ixgbevf_intr_enable(hw);
1661
1662         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1663                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1664                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1665
1666         return 0;
1667 }
1668
1669 /* Virtual Function device uninit */
1670
1671 static int
1672 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1673 {
1674         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1675         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1676         struct ixgbe_hw *hw;
1677
1678         PMD_INIT_FUNC_TRACE();
1679
1680         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1681                 return -EPERM;
1682
1683         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1684
1685         if (hw->adapter_stopped == 0)
1686                 ixgbevf_dev_close(eth_dev);
1687
1688         eth_dev->dev_ops = NULL;
1689         eth_dev->rx_pkt_burst = NULL;
1690         eth_dev->tx_pkt_burst = NULL;
1691
1692         /* Disable the interrupts for VF */
1693         ixgbevf_intr_disable(hw);
1694
1695         rte_free(eth_dev->data->mac_addrs);
1696         eth_dev->data->mac_addrs = NULL;
1697
1698         rte_intr_disable(intr_handle);
1699         rte_intr_callback_unregister(intr_handle,
1700                                      ixgbevf_dev_interrupt_handler, eth_dev);
1701
1702         return 0;
1703 }
1704
1705 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1706         struct rte_pci_device *pci_dev)
1707 {
1708         return rte_eth_dev_pci_generic_probe(pci_dev,
1709                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1710 }
1711
1712 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1713 {
1714         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1715 }
1716
1717 static struct rte_pci_driver rte_ixgbe_pmd = {
1718         .id_table = pci_id_ixgbe_map,
1719         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1720                      RTE_PCI_DRV_IOVA_AS_VA,
1721         .probe = eth_ixgbe_pci_probe,
1722         .remove = eth_ixgbe_pci_remove,
1723 };
1724
1725 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1726         struct rte_pci_device *pci_dev)
1727 {
1728         return rte_eth_dev_pci_generic_probe(pci_dev,
1729                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1730 }
1731
1732 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1733 {
1734         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1735 }
1736
1737 /*
1738  * virtual function driver struct
1739  */
1740 static struct rte_pci_driver rte_ixgbevf_pmd = {
1741         .id_table = pci_id_ixgbevf_map,
1742         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1743         .probe = eth_ixgbevf_pci_probe,
1744         .remove = eth_ixgbevf_pci_remove,
1745 };
1746
1747 static int
1748 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1749 {
1750         struct ixgbe_hw *hw =
1751                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752         struct ixgbe_vfta *shadow_vfta =
1753                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1754         uint32_t vfta;
1755         uint32_t vid_idx;
1756         uint32_t vid_bit;
1757
1758         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1759         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1760         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1761         if (on)
1762                 vfta |= vid_bit;
1763         else
1764                 vfta &= ~vid_bit;
1765         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1766
1767         /* update local VFTA copy */
1768         shadow_vfta->vfta[vid_idx] = vfta;
1769
1770         return 0;
1771 }
1772
1773 static void
1774 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1775 {
1776         if (on)
1777                 ixgbe_vlan_hw_strip_enable(dev, queue);
1778         else
1779                 ixgbe_vlan_hw_strip_disable(dev, queue);
1780 }
1781
1782 static int
1783 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1784                     enum rte_vlan_type vlan_type,
1785                     uint16_t tpid)
1786 {
1787         struct ixgbe_hw *hw =
1788                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1789         int ret = 0;
1790         uint32_t reg;
1791         uint32_t qinq;
1792
1793         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1794         qinq &= IXGBE_DMATXCTL_GDV;
1795
1796         switch (vlan_type) {
1797         case ETH_VLAN_TYPE_INNER:
1798                 if (qinq) {
1799                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1800                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1801                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1802                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1803                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1804                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1805                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1806                 } else {
1807                         ret = -ENOTSUP;
1808                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1809                                     " by single VLAN");
1810                 }
1811                 break;
1812         case ETH_VLAN_TYPE_OUTER:
1813                 if (qinq) {
1814                         /* Only the high 16-bits is valid */
1815                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1816                                         IXGBE_EXVET_VET_EXT_SHIFT);
1817                 } else {
1818                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1819                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1820                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1821                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1822                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1823                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1824                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1825                 }
1826
1827                 break;
1828         default:
1829                 ret = -EINVAL;
1830                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1831                 break;
1832         }
1833
1834         return ret;
1835 }
1836
1837 void
1838 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1839 {
1840         struct ixgbe_hw *hw =
1841                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         uint32_t vlnctrl;
1843
1844         PMD_INIT_FUNC_TRACE();
1845
1846         /* Filter Table Disable */
1847         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1848         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1849
1850         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1851 }
1852
1853 void
1854 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1855 {
1856         struct ixgbe_hw *hw =
1857                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858         struct ixgbe_vfta *shadow_vfta =
1859                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1860         uint32_t vlnctrl;
1861         uint16_t i;
1862
1863         PMD_INIT_FUNC_TRACE();
1864
1865         /* Filter Table Enable */
1866         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1867         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1868         vlnctrl |= IXGBE_VLNCTRL_VFE;
1869
1870         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1871
1872         /* write whatever is in local vfta copy */
1873         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1874                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1875 }
1876
1877 static void
1878 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1879 {
1880         struct ixgbe_hwstrip *hwstrip =
1881                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1882         struct ixgbe_rx_queue *rxq;
1883
1884         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1885                 return;
1886
1887         if (on)
1888                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1889         else
1890                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1891
1892         if (queue >= dev->data->nb_rx_queues)
1893                 return;
1894
1895         rxq = dev->data->rx_queues[queue];
1896
1897         if (on)
1898                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1899         else
1900                 rxq->vlan_flags = PKT_RX_VLAN;
1901 }
1902
1903 static void
1904 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1905 {
1906         struct ixgbe_hw *hw =
1907                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908         uint32_t ctrl;
1909
1910         PMD_INIT_FUNC_TRACE();
1911
1912         if (hw->mac.type == ixgbe_mac_82598EB) {
1913                 /* No queue level support */
1914                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1915                 return;
1916         }
1917
1918         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1919         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1920         ctrl &= ~IXGBE_RXDCTL_VME;
1921         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1922
1923         /* record those setting for HW strip per queue */
1924         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1925 }
1926
1927 static void
1928 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1929 {
1930         struct ixgbe_hw *hw =
1931                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1932         uint32_t ctrl;
1933
1934         PMD_INIT_FUNC_TRACE();
1935
1936         if (hw->mac.type == ixgbe_mac_82598EB) {
1937                 /* No queue level supported */
1938                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1939                 return;
1940         }
1941
1942         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1943         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1944         ctrl |= IXGBE_RXDCTL_VME;
1945         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1946
1947         /* record those setting for HW strip per queue */
1948         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1949 }
1950
1951 void
1952 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1953 {
1954         struct ixgbe_hw *hw =
1955                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1956         uint32_t ctrl;
1957         uint16_t i;
1958         struct ixgbe_rx_queue *rxq;
1959
1960         PMD_INIT_FUNC_TRACE();
1961
1962         if (hw->mac.type == ixgbe_mac_82598EB) {
1963                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1964                 ctrl &= ~IXGBE_VLNCTRL_VME;
1965                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1966         } else {
1967                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1968                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1969                         rxq = dev->data->rx_queues[i];
1970                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1971                         ctrl &= ~IXGBE_RXDCTL_VME;
1972                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1973
1974                         /* record those setting for HW strip per queue */
1975                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1976                 }
1977         }
1978 }
1979
1980 void
1981 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1982 {
1983         struct ixgbe_hw *hw =
1984                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985         uint32_t ctrl;
1986         uint16_t i;
1987         struct ixgbe_rx_queue *rxq;
1988
1989         PMD_INIT_FUNC_TRACE();
1990
1991         if (hw->mac.type == ixgbe_mac_82598EB) {
1992                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1993                 ctrl |= IXGBE_VLNCTRL_VME;
1994                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1995         } else {
1996                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1997                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1998                         rxq = dev->data->rx_queues[i];
1999                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2000                         ctrl |= IXGBE_RXDCTL_VME;
2001                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2002
2003                         /* record those setting for HW strip per queue */
2004                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2005                 }
2006         }
2007 }
2008
2009 static void
2010 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2011 {
2012         struct ixgbe_hw *hw =
2013                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014         uint32_t ctrl;
2015
2016         PMD_INIT_FUNC_TRACE();
2017
2018         /* DMATXCTRL: Geric Double VLAN Disable */
2019         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2020         ctrl &= ~IXGBE_DMATXCTL_GDV;
2021         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2022
2023         /* CTRL_EXT: Global Double VLAN Disable */
2024         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2025         ctrl &= ~IXGBE_EXTENDED_VLAN;
2026         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2027
2028 }
2029
2030 static void
2031 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2032 {
2033         struct ixgbe_hw *hw =
2034                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2035         uint32_t ctrl;
2036
2037         PMD_INIT_FUNC_TRACE();
2038
2039         /* DMATXCTRL: Geric Double VLAN Enable */
2040         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2041         ctrl |= IXGBE_DMATXCTL_GDV;
2042         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2043
2044         /* CTRL_EXT: Global Double VLAN Enable */
2045         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2046         ctrl |= IXGBE_EXTENDED_VLAN;
2047         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2048
2049         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2050         if (hw->mac.type == ixgbe_mac_X550 ||
2051             hw->mac.type == ixgbe_mac_X550EM_x ||
2052             hw->mac.type == ixgbe_mac_X550EM_a) {
2053                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2054                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2055                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2056         }
2057
2058         /*
2059          * VET EXT field in the EXVET register = 0x8100 by default
2060          * So no need to change. Same to VT field of DMATXCTL register
2061          */
2062 }
2063
2064 static int
2065 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2066 {
2067         if (mask & ETH_VLAN_STRIP_MASK) {
2068                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2069                         ixgbe_vlan_hw_strip_enable_all(dev);
2070                 else
2071                         ixgbe_vlan_hw_strip_disable_all(dev);
2072         }
2073
2074         if (mask & ETH_VLAN_FILTER_MASK) {
2075                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2076                         ixgbe_vlan_hw_filter_enable(dev);
2077                 else
2078                         ixgbe_vlan_hw_filter_disable(dev);
2079         }
2080
2081         if (mask & ETH_VLAN_EXTEND_MASK) {
2082                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2083                         ixgbe_vlan_hw_extend_enable(dev);
2084                 else
2085                         ixgbe_vlan_hw_extend_disable(dev);
2086         }
2087
2088         return 0;
2089 }
2090
2091 static void
2092 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2093 {
2094         struct ixgbe_hw *hw =
2095                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2097         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2098
2099         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2100         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2101 }
2102
2103 static int
2104 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2105 {
2106         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2107
2108         switch (nb_rx_q) {
2109         case 1:
2110         case 2:
2111                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2112                 break;
2113         case 4:
2114                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2115                 break;
2116         default:
2117                 return -EINVAL;
2118         }
2119
2120         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2121                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2122         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2123                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2124         return 0;
2125 }
2126
2127 static int
2128 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2129 {
2130         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2133         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2134
2135         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2136                 /* check multi-queue mode */
2137                 switch (dev_conf->rxmode.mq_mode) {
2138                 case ETH_MQ_RX_VMDQ_DCB:
2139                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2140                         break;
2141                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2142                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2143                         PMD_INIT_LOG(ERR, "SRIOV active,"
2144                                         " unsupported mq_mode rx %d.",
2145                                         dev_conf->rxmode.mq_mode);
2146                         return -EINVAL;
2147                 case ETH_MQ_RX_RSS:
2148                 case ETH_MQ_RX_VMDQ_RSS:
2149                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2150                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2151                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2152                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2153                                                 " invalid queue number"
2154                                                 " for VMDQ RSS, allowed"
2155                                                 " value are 1, 2 or 4.");
2156                                         return -EINVAL;
2157                                 }
2158                         break;
2159                 case ETH_MQ_RX_VMDQ_ONLY:
2160                 case ETH_MQ_RX_NONE:
2161                         /* if nothing mq mode configure, use default scheme */
2162                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2163                         break;
2164                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2165                         /* SRIOV only works in VMDq enable mode */
2166                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2167                                         " wrong mq_mode rx %d.",
2168                                         dev_conf->rxmode.mq_mode);
2169                         return -EINVAL;
2170                 }
2171
2172                 switch (dev_conf->txmode.mq_mode) {
2173                 case ETH_MQ_TX_VMDQ_DCB:
2174                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2175                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2176                         break;
2177                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2178                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2179                         break;
2180                 }
2181
2182                 /* check valid queue number */
2183                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2184                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2185                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2186                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2187                                         " must be less than or equal to %d.",
2188                                         nb_rx_q, nb_tx_q,
2189                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2190                         return -EINVAL;
2191                 }
2192         } else {
2193                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2194                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2195                                           " not supported.");
2196                         return -EINVAL;
2197                 }
2198                 /* check configuration for vmdb+dcb mode */
2199                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2200                         const struct rte_eth_vmdq_dcb_conf *conf;
2201
2202                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2203                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2204                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2205                                 return -EINVAL;
2206                         }
2207                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2208                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2209                                conf->nb_queue_pools == ETH_32_POOLS)) {
2210                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2211                                                 " nb_queue_pools must be %d or %d.",
2212                                                 ETH_16_POOLS, ETH_32_POOLS);
2213                                 return -EINVAL;
2214                         }
2215                 }
2216                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2217                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2218
2219                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2220                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2221                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2222                                 return -EINVAL;
2223                         }
2224                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2225                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2226                                conf->nb_queue_pools == ETH_32_POOLS)) {
2227                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2228                                                 " nb_queue_pools != %d and"
2229                                                 " nb_queue_pools != %d.",
2230                                                 ETH_16_POOLS, ETH_32_POOLS);
2231                                 return -EINVAL;
2232                         }
2233                 }
2234
2235                 /* For DCB mode check our configuration before we go further */
2236                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2237                         const struct rte_eth_dcb_rx_conf *conf;
2238
2239                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2240                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2241                                                  IXGBE_DCB_NB_QUEUES);
2242                                 return -EINVAL;
2243                         }
2244                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2245                         if (!(conf->nb_tcs == ETH_4_TCS ||
2246                                conf->nb_tcs == ETH_8_TCS)) {
2247                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2248                                                 " and nb_tcs != %d.",
2249                                                 ETH_4_TCS, ETH_8_TCS);
2250                                 return -EINVAL;
2251                         }
2252                 }
2253
2254                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2255                         const struct rte_eth_dcb_tx_conf *conf;
2256
2257                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2258                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2259                                                  IXGBE_DCB_NB_QUEUES);
2260                                 return -EINVAL;
2261                         }
2262                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2263                         if (!(conf->nb_tcs == ETH_4_TCS ||
2264                                conf->nb_tcs == ETH_8_TCS)) {
2265                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2266                                                 " and nb_tcs != %d.",
2267                                                 ETH_4_TCS, ETH_8_TCS);
2268                                 return -EINVAL;
2269                         }
2270                 }
2271
2272                 /*
2273                  * When DCB/VT is off, maximum number of queues changes,
2274                  * except for 82598EB, which remains constant.
2275                  */
2276                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2277                                 hw->mac.type != ixgbe_mac_82598EB) {
2278                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2279                                 PMD_INIT_LOG(ERR,
2280                                              "Neither VT nor DCB are enabled, "
2281                                              "nb_tx_q > %d.",
2282                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2283                                 return -EINVAL;
2284                         }
2285                 }
2286         }
2287         return 0;
2288 }
2289
2290 static int
2291 ixgbe_dev_configure(struct rte_eth_dev *dev)
2292 {
2293         struct ixgbe_interrupt *intr =
2294                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2295         struct ixgbe_adapter *adapter =
2296                 (struct ixgbe_adapter *)dev->data->dev_private;
2297         int ret;
2298
2299         PMD_INIT_FUNC_TRACE();
2300         /* multipe queue mode checking */
2301         ret  = ixgbe_check_mq_mode(dev);
2302         if (ret != 0) {
2303                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2304                             ret);
2305                 return ret;
2306         }
2307
2308         /* set flag to update link status after init */
2309         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2310
2311         /*
2312          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2313          * allocation or vector Rx preconditions we will reset it.
2314          */
2315         adapter->rx_bulk_alloc_allowed = true;
2316         adapter->rx_vec_allowed = true;
2317
2318         return 0;
2319 }
2320
2321 static void
2322 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2323 {
2324         struct ixgbe_hw *hw =
2325                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326         struct ixgbe_interrupt *intr =
2327                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2328         uint32_t gpie;
2329
2330         /* only set up it on X550EM_X */
2331         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2332                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2333                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2334                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2335                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2336                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2337         }
2338 }
2339
2340 int
2341 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2342                         uint16_t tx_rate, uint64_t q_msk)
2343 {
2344         struct ixgbe_hw *hw;
2345         struct ixgbe_vf_info *vfinfo;
2346         struct rte_eth_link link;
2347         uint8_t  nb_q_per_pool;
2348         uint32_t queue_stride;
2349         uint32_t queue_idx, idx = 0, vf_idx;
2350         uint32_t queue_end;
2351         uint16_t total_rate = 0;
2352         struct rte_pci_device *pci_dev;
2353
2354         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2355         rte_eth_link_get_nowait(dev->data->port_id, &link);
2356
2357         if (vf >= pci_dev->max_vfs)
2358                 return -EINVAL;
2359
2360         if (tx_rate > link.link_speed)
2361                 return -EINVAL;
2362
2363         if (q_msk == 0)
2364                 return 0;
2365
2366         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2367         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2368         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2369         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2370         queue_idx = vf * queue_stride;
2371         queue_end = queue_idx + nb_q_per_pool - 1;
2372         if (queue_end >= hw->mac.max_tx_queues)
2373                 return -EINVAL;
2374
2375         if (vfinfo) {
2376                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2377                         if (vf_idx == vf)
2378                                 continue;
2379                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2380                                 idx++)
2381                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2382                 }
2383         } else {
2384                 return -EINVAL;
2385         }
2386
2387         /* Store tx_rate for this vf. */
2388         for (idx = 0; idx < nb_q_per_pool; idx++) {
2389                 if (((uint64_t)0x1 << idx) & q_msk) {
2390                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2391                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2392                         total_rate += tx_rate;
2393                 }
2394         }
2395
2396         if (total_rate > dev->data->dev_link.link_speed) {
2397                 /* Reset stored TX rate of the VF if it causes exceed
2398                  * link speed.
2399                  */
2400                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2401                 return -EINVAL;
2402         }
2403
2404         /* Set RTTBCNRC of each queue/pool for vf X  */
2405         for (; queue_idx <= queue_end; queue_idx++) {
2406                 if (0x1 & q_msk)
2407                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2408                 q_msk = q_msk >> 1;
2409         }
2410
2411         return 0;
2412 }
2413
2414 /*
2415  * Configure device link speed and setup link.
2416  * It returns 0 on success.
2417  */
2418 static int
2419 ixgbe_dev_start(struct rte_eth_dev *dev)
2420 {
2421         struct ixgbe_hw *hw =
2422                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         struct ixgbe_vf_info *vfinfo =
2424                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2425         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2426         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2427         uint32_t intr_vector = 0;
2428         int err, link_up = 0, negotiate = 0;
2429         uint32_t speed = 0;
2430         int mask = 0;
2431         int status;
2432         uint16_t vf, idx;
2433         uint32_t *link_speeds;
2434         struct ixgbe_tm_conf *tm_conf =
2435                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2436
2437         PMD_INIT_FUNC_TRACE();
2438
2439         /* IXGBE devices don't support:
2440         *    - half duplex (checked afterwards for valid speeds)
2441         *    - fixed speed: TODO implement
2442         */
2443         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2444                 PMD_INIT_LOG(ERR,
2445                 "Invalid link_speeds for port %u, fix speed not supported",
2446                                 dev->data->port_id);
2447                 return -EINVAL;
2448         }
2449
2450         /* disable uio/vfio intr/eventfd mapping */
2451         rte_intr_disable(intr_handle);
2452
2453         /* stop adapter */
2454         hw->adapter_stopped = 0;
2455         ixgbe_stop_adapter(hw);
2456
2457         /* reinitialize adapter
2458          * this calls reset and start
2459          */
2460         status = ixgbe_pf_reset_hw(hw);
2461         if (status != 0)
2462                 return -1;
2463         hw->mac.ops.start_hw(hw);
2464         hw->mac.get_link_status = true;
2465
2466         /* configure PF module if SRIOV enabled */
2467         ixgbe_pf_host_configure(dev);
2468
2469         ixgbe_dev_phy_intr_setup(dev);
2470
2471         /* check and configure queue intr-vector mapping */
2472         if ((rte_intr_cap_multiple(intr_handle) ||
2473              !RTE_ETH_DEV_SRIOV(dev).active) &&
2474             dev->data->dev_conf.intr_conf.rxq != 0) {
2475                 intr_vector = dev->data->nb_rx_queues;
2476                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2477                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2478                                         IXGBE_MAX_INTR_QUEUE_NUM);
2479                         return -ENOTSUP;
2480                 }
2481                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2482                         return -1;
2483         }
2484
2485         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2486                 intr_handle->intr_vec =
2487                         rte_zmalloc("intr_vec",
2488                                     dev->data->nb_rx_queues * sizeof(int), 0);
2489                 if (intr_handle->intr_vec == NULL) {
2490                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2491                                      " intr_vec", dev->data->nb_rx_queues);
2492                         return -ENOMEM;
2493                 }
2494         }
2495
2496         /* confiugre msix for sleep until rx interrupt */
2497         ixgbe_configure_msix(dev);
2498
2499         /* initialize transmission unit */
2500         ixgbe_dev_tx_init(dev);
2501
2502         /* This can fail when allocating mbufs for descriptor rings */
2503         err = ixgbe_dev_rx_init(dev);
2504         if (err) {
2505                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2506                 goto error;
2507         }
2508
2509         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2510                 ETH_VLAN_EXTEND_MASK;
2511         err = ixgbe_vlan_offload_set(dev, mask);
2512         if (err) {
2513                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2514                 goto error;
2515         }
2516
2517         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2518                 /* Enable vlan filtering for VMDq */
2519                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2520         }
2521
2522         /* Configure DCB hw */
2523         ixgbe_configure_dcb(dev);
2524
2525         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2526                 err = ixgbe_fdir_configure(dev);
2527                 if (err)
2528                         goto error;
2529         }
2530
2531         /* Restore vf rate limit */
2532         if (vfinfo != NULL) {
2533                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2534                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2535                                 if (vfinfo[vf].tx_rate[idx] != 0)
2536                                         ixgbe_set_vf_rate_limit(
2537                                                 dev, vf,
2538                                                 vfinfo[vf].tx_rate[idx],
2539                                                 1 << idx);
2540         }
2541
2542         ixgbe_restore_statistics_mapping(dev);
2543
2544         err = ixgbe_dev_rxtx_start(dev);
2545         if (err < 0) {
2546                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2547                 goto error;
2548         }
2549
2550         /* Skip link setup if loopback mode is enabled for 82599. */
2551         if (hw->mac.type == ixgbe_mac_82599EB &&
2552                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2553                 goto skip_link_setup;
2554
2555         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2556                 err = hw->mac.ops.setup_sfp(hw);
2557                 if (err)
2558                         goto error;
2559         }
2560
2561         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2562                 /* Turn on the copper */
2563                 ixgbe_set_phy_power(hw, true);
2564         } else {
2565                 /* Turn on the laser */
2566                 ixgbe_enable_tx_laser(hw);
2567         }
2568
2569         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2570         if (err)
2571                 goto error;
2572         dev->data->dev_link.link_status = link_up;
2573
2574         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2575         if (err)
2576                 goto error;
2577
2578         link_speeds = &dev->data->dev_conf.link_speeds;
2579         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2580                         ETH_LINK_SPEED_10G)) {
2581                 PMD_INIT_LOG(ERR, "Invalid link setting");
2582                 goto error;
2583         }
2584
2585         speed = 0x0;
2586         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2587                 switch (hw->mac.type) {
2588                 case ixgbe_mac_82598EB:
2589                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2590                         break;
2591                 case ixgbe_mac_82599EB:
2592                 case ixgbe_mac_X540:
2593                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2594                         break;
2595                 case ixgbe_mac_X550:
2596                 case ixgbe_mac_X550EM_x:
2597                 case ixgbe_mac_X550EM_a:
2598                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2599                         break;
2600                 default:
2601                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2602                 }
2603         } else {
2604                 if (*link_speeds & ETH_LINK_SPEED_10G)
2605                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2606                 if (*link_speeds & ETH_LINK_SPEED_1G)
2607                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2608                 if (*link_speeds & ETH_LINK_SPEED_100M)
2609                         speed |= IXGBE_LINK_SPEED_100_FULL;
2610         }
2611
2612         err = ixgbe_setup_link(hw, speed, link_up);
2613         if (err)
2614                 goto error;
2615
2616 skip_link_setup:
2617
2618         if (rte_intr_allow_others(intr_handle)) {
2619                 /* check if lsc interrupt is enabled */
2620                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2621                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2622                 else
2623                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2624                 ixgbe_dev_macsec_interrupt_setup(dev);
2625         } else {
2626                 rte_intr_callback_unregister(intr_handle,
2627                                              ixgbe_dev_interrupt_handler, dev);
2628                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2629                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2630                                      " no intr multiplex");
2631         }
2632
2633         /* check if rxq interrupt is enabled */
2634         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2635             rte_intr_dp_is_en(intr_handle))
2636                 ixgbe_dev_rxq_interrupt_setup(dev);
2637
2638         /* enable uio/vfio intr/eventfd mapping */
2639         rte_intr_enable(intr_handle);
2640
2641         /* resume enabled intr since hw reset */
2642         ixgbe_enable_intr(dev);
2643         ixgbe_l2_tunnel_conf(dev);
2644         ixgbe_filter_restore(dev);
2645
2646         if (tm_conf->root && !tm_conf->committed)
2647                 PMD_DRV_LOG(WARNING,
2648                             "please call hierarchy_commit() "
2649                             "before starting the port");
2650
2651         return 0;
2652
2653 error:
2654         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2655         ixgbe_dev_clear_queues(dev);
2656         return -EIO;
2657 }
2658
2659 /*
2660  * Stop device: disable rx and tx functions to allow for reconfiguring.
2661  */
2662 static void
2663 ixgbe_dev_stop(struct rte_eth_dev *dev)
2664 {
2665         struct rte_eth_link link;
2666         struct ixgbe_hw *hw =
2667                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2668         struct ixgbe_vf_info *vfinfo =
2669                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2670         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2671         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2672         int vf;
2673         struct ixgbe_tm_conf *tm_conf =
2674                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2675
2676         PMD_INIT_FUNC_TRACE();
2677
2678         /* disable interrupts */
2679         ixgbe_disable_intr(hw);
2680
2681         /* reset the NIC */
2682         ixgbe_pf_reset_hw(hw);
2683         hw->adapter_stopped = 0;
2684
2685         /* stop adapter */
2686         ixgbe_stop_adapter(hw);
2687
2688         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2689                 vfinfo[vf].clear_to_send = false;
2690
2691         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2692                 /* Turn off the copper */
2693                 ixgbe_set_phy_power(hw, false);
2694         } else {
2695                 /* Turn off the laser */
2696                 ixgbe_disable_tx_laser(hw);
2697         }
2698
2699         ixgbe_dev_clear_queues(dev);
2700
2701         /* Clear stored conf */
2702         dev->data->scattered_rx = 0;
2703         dev->data->lro = 0;
2704
2705         /* Clear recorded link status */
2706         memset(&link, 0, sizeof(link));
2707         rte_eth_linkstatus_set(dev, &link);
2708
2709         if (!rte_intr_allow_others(intr_handle))
2710                 /* resume to the default handler */
2711                 rte_intr_callback_register(intr_handle,
2712                                            ixgbe_dev_interrupt_handler,
2713                                            (void *)dev);
2714
2715         /* Clean datapath event and queue/vec mapping */
2716         rte_intr_efd_disable(intr_handle);
2717         if (intr_handle->intr_vec != NULL) {
2718                 rte_free(intr_handle->intr_vec);
2719                 intr_handle->intr_vec = NULL;
2720         }
2721
2722         /* reset hierarchy commit */
2723         tm_conf->committed = false;
2724 }
2725
2726 /*
2727  * Set device link up: enable tx.
2728  */
2729 static int
2730 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2731 {
2732         struct ixgbe_hw *hw =
2733                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734         if (hw->mac.type == ixgbe_mac_82599EB) {
2735 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2736                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2737                         /* Not suported in bypass mode */
2738                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2739                                      "by device id 0x%x", hw->device_id);
2740                         return -ENOTSUP;
2741                 }
2742 #endif
2743         }
2744
2745         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2746                 /* Turn on the copper */
2747                 ixgbe_set_phy_power(hw, true);
2748         } else {
2749                 /* Turn on the laser */
2750                 ixgbe_enable_tx_laser(hw);
2751         }
2752
2753         return 0;
2754 }
2755
2756 /*
2757  * Set device link down: disable tx.
2758  */
2759 static int
2760 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2761 {
2762         struct ixgbe_hw *hw =
2763                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2764         if (hw->mac.type == ixgbe_mac_82599EB) {
2765 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2766                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2767                         /* Not suported in bypass mode */
2768                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2769                                      "by device id 0x%x", hw->device_id);
2770                         return -ENOTSUP;
2771                 }
2772 #endif
2773         }
2774
2775         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2776                 /* Turn off the copper */
2777                 ixgbe_set_phy_power(hw, false);
2778         } else {
2779                 /* Turn off the laser */
2780                 ixgbe_disable_tx_laser(hw);
2781         }
2782
2783         return 0;
2784 }
2785
2786 /*
2787  * Reset and stop device.
2788  */
2789 static void
2790 ixgbe_dev_close(struct rte_eth_dev *dev)
2791 {
2792         struct ixgbe_hw *hw =
2793                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794
2795         PMD_INIT_FUNC_TRACE();
2796
2797         ixgbe_pf_reset_hw(hw);
2798
2799         ixgbe_dev_stop(dev);
2800         hw->adapter_stopped = 1;
2801
2802         ixgbe_dev_free_queues(dev);
2803
2804         ixgbe_disable_pcie_master(hw);
2805
2806         /* reprogram the RAR[0] in case user changed it. */
2807         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2808 }
2809
2810 /*
2811  * Reset PF device.
2812  */
2813 static int
2814 ixgbe_dev_reset(struct rte_eth_dev *dev)
2815 {
2816         int ret;
2817
2818         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2819          * its VF to make them align with it. The detailed notification
2820          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2821          * To avoid unexpected behavior in VF, currently reset of PF with
2822          * SR-IOV activation is not supported. It might be supported later.
2823          */
2824         if (dev->data->sriov.active)
2825                 return -ENOTSUP;
2826
2827         ret = eth_ixgbe_dev_uninit(dev);
2828         if (ret)
2829                 return ret;
2830
2831         ret = eth_ixgbe_dev_init(dev);
2832
2833         return ret;
2834 }
2835
2836 static void
2837 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2838                            struct ixgbe_hw_stats *hw_stats,
2839                            struct ixgbe_macsec_stats *macsec_stats,
2840                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2841                            uint64_t *total_qprc, uint64_t *total_qprdc)
2842 {
2843         uint32_t bprc, lxon, lxoff, total;
2844         uint32_t delta_gprc = 0;
2845         unsigned i;
2846         /* Workaround for RX byte count not including CRC bytes when CRC
2847          * strip is enabled. CRC bytes are removed from counters when crc_strip
2848          * is disabled.
2849          */
2850         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2851                         IXGBE_HLREG0_RXCRCSTRP);
2852
2853         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2854         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2855         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2856         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2857
2858         for (i = 0; i < 8; i++) {
2859                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2860
2861                 /* global total per queue */
2862                 hw_stats->mpc[i] += mp;
2863                 /* Running comprehensive total for stats display */
2864                 *total_missed_rx += hw_stats->mpc[i];
2865                 if (hw->mac.type == ixgbe_mac_82598EB) {
2866                         hw_stats->rnbc[i] +=
2867                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2868                         hw_stats->pxonrxc[i] +=
2869                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2870                         hw_stats->pxoffrxc[i] +=
2871                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2872                 } else {
2873                         hw_stats->pxonrxc[i] +=
2874                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2875                         hw_stats->pxoffrxc[i] +=
2876                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2877                         hw_stats->pxon2offc[i] +=
2878                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2879                 }
2880                 hw_stats->pxontxc[i] +=
2881                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2882                 hw_stats->pxofftxc[i] +=
2883                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2884         }
2885         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2886                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2887                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2888                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2889
2890                 delta_gprc += delta_qprc;
2891
2892                 hw_stats->qprc[i] += delta_qprc;
2893                 hw_stats->qptc[i] += delta_qptc;
2894
2895                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2896                 hw_stats->qbrc[i] +=
2897                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2898                 if (crc_strip == 0)
2899                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2900
2901                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2902                 hw_stats->qbtc[i] +=
2903                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2904
2905                 hw_stats->qprdc[i] += delta_qprdc;
2906                 *total_qprdc += hw_stats->qprdc[i];
2907
2908                 *total_qprc += hw_stats->qprc[i];
2909                 *total_qbrc += hw_stats->qbrc[i];
2910         }
2911         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2912         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2913         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2914
2915         /*
2916          * An errata states that gprc actually counts good + missed packets:
2917          * Workaround to set gprc to summated queue packet receives
2918          */
2919         hw_stats->gprc = *total_qprc;
2920
2921         if (hw->mac.type != ixgbe_mac_82598EB) {
2922                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2923                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2924                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2925                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2926                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2927                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2928                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2929                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2930         } else {
2931                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2932                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2933                 /* 82598 only has a counter in the high register */
2934                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2935                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2936                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2937         }
2938         uint64_t old_tpr = hw_stats->tpr;
2939
2940         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2941         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2942
2943         if (crc_strip == 0)
2944                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2945
2946         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2947         hw_stats->gptc += delta_gptc;
2948         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2949         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2950
2951         /*
2952          * Workaround: mprc hardware is incorrectly counting
2953          * broadcasts, so for now we subtract those.
2954          */
2955         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2956         hw_stats->bprc += bprc;
2957         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2958         if (hw->mac.type == ixgbe_mac_82598EB)
2959                 hw_stats->mprc -= bprc;
2960
2961         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2962         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2963         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2964         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2965         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2966         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2967
2968         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2969         hw_stats->lxontxc += lxon;
2970         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2971         hw_stats->lxofftxc += lxoff;
2972         total = lxon + lxoff;
2973
2974         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2975         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2976         hw_stats->gptc -= total;
2977         hw_stats->mptc -= total;
2978         hw_stats->ptc64 -= total;
2979         hw_stats->gotc -= total * ETHER_MIN_LEN;
2980
2981         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2982         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2983         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2984         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2985         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2986         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2987         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2988         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2989         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2990         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2991         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2992         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2993         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2994         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2995         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2996         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2997         /* Only read FCOE on 82599 */
2998         if (hw->mac.type != ixgbe_mac_82598EB) {
2999                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3000                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3001                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3002                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3003                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3004         }
3005
3006         /* Flow Director Stats registers */
3007         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3008         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3009
3010         /* MACsec Stats registers */
3011         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3012         macsec_stats->out_pkts_encrypted +=
3013                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3014         macsec_stats->out_pkts_protected +=
3015                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3016         macsec_stats->out_octets_encrypted +=
3017                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3018         macsec_stats->out_octets_protected +=
3019                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3020         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3021         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3022         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3023         macsec_stats->in_pkts_unknownsci +=
3024                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3025         macsec_stats->in_octets_decrypted +=
3026                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3027         macsec_stats->in_octets_validated +=
3028                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3029         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3030         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3031         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3032         for (i = 0; i < 2; i++) {
3033                 macsec_stats->in_pkts_ok +=
3034                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3035                 macsec_stats->in_pkts_invalid +=
3036                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3037                 macsec_stats->in_pkts_notvalid +=
3038                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3039         }
3040         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3041         macsec_stats->in_pkts_notusingsa +=
3042                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3043 }
3044
3045 /*
3046  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3047  */
3048 static int
3049 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3050 {
3051         struct ixgbe_hw *hw =
3052                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3053         struct ixgbe_hw_stats *hw_stats =
3054                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3055         struct ixgbe_macsec_stats *macsec_stats =
3056                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3057                                 dev->data->dev_private);
3058         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3059         unsigned i;
3060
3061         total_missed_rx = 0;
3062         total_qbrc = 0;
3063         total_qprc = 0;
3064         total_qprdc = 0;
3065
3066         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3067                         &total_qbrc, &total_qprc, &total_qprdc);
3068
3069         if (stats == NULL)
3070                 return -EINVAL;
3071
3072         /* Fill out the rte_eth_stats statistics structure */
3073         stats->ipackets = total_qprc;
3074         stats->ibytes = total_qbrc;
3075         stats->opackets = hw_stats->gptc;
3076         stats->obytes = hw_stats->gotc;
3077
3078         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3079                 stats->q_ipackets[i] = hw_stats->qprc[i];
3080                 stats->q_opackets[i] = hw_stats->qptc[i];
3081                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3082                 stats->q_obytes[i] = hw_stats->qbtc[i];
3083                 stats->q_errors[i] = hw_stats->qprdc[i];
3084         }
3085
3086         /* Rx Errors */
3087         stats->imissed  = total_missed_rx;
3088         stats->ierrors  = hw_stats->crcerrs +
3089                           hw_stats->mspdc +
3090                           hw_stats->rlec +
3091                           hw_stats->ruc +
3092                           hw_stats->roc +
3093                           hw_stats->illerrc +
3094                           hw_stats->errbc +
3095                           hw_stats->rfc +
3096                           hw_stats->fccrc +
3097                           hw_stats->fclast;
3098
3099         /* Tx Errors */
3100         stats->oerrors  = 0;
3101         return 0;
3102 }
3103
3104 static void
3105 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3106 {
3107         struct ixgbe_hw_stats *stats =
3108                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3109
3110         /* HW registers are cleared on read */
3111         ixgbe_dev_stats_get(dev, NULL);
3112
3113         /* Reset software totals */
3114         memset(stats, 0, sizeof(*stats));
3115 }
3116
3117 /* This function calculates the number of xstats based on the current config */
3118 static unsigned
3119 ixgbe_xstats_calc_num(void) {
3120         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3121                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3122                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3123 }
3124
3125 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3126         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3127 {
3128         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3129         unsigned stat, i, count;
3130
3131         if (xstats_names != NULL) {
3132                 count = 0;
3133
3134                 /* Note: limit >= cnt_stats checked upstream
3135                  * in rte_eth_xstats_names()
3136                  */
3137
3138                 /* Extended stats from ixgbe_hw_stats */
3139                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3140                         snprintf(xstats_names[count].name,
3141                                 sizeof(xstats_names[count].name),
3142                                 "%s",
3143                                 rte_ixgbe_stats_strings[i].name);
3144                         count++;
3145                 }
3146
3147                 /* MACsec Stats */
3148                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3149                         snprintf(xstats_names[count].name,
3150                                 sizeof(xstats_names[count].name),
3151                                 "%s",
3152                                 rte_ixgbe_macsec_strings[i].name);
3153                         count++;
3154                 }
3155
3156                 /* RX Priority Stats */
3157                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3158                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3159                                 snprintf(xstats_names[count].name,
3160                                         sizeof(xstats_names[count].name),
3161                                         "rx_priority%u_%s", i,
3162                                         rte_ixgbe_rxq_strings[stat].name);
3163                                 count++;
3164                         }
3165                 }
3166
3167                 /* TX Priority Stats */
3168                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3169                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3170                                 snprintf(xstats_names[count].name,
3171                                         sizeof(xstats_names[count].name),
3172                                         "tx_priority%u_%s", i,
3173                                         rte_ixgbe_txq_strings[stat].name);
3174                                 count++;
3175                         }
3176                 }
3177         }
3178         return cnt_stats;
3179 }
3180
3181 static int ixgbe_dev_xstats_get_names_by_id(
3182         struct rte_eth_dev *dev,
3183         struct rte_eth_xstat_name *xstats_names,
3184         const uint64_t *ids,
3185         unsigned int limit)
3186 {
3187         if (!ids) {
3188                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3189                 unsigned int stat, i, count;
3190
3191                 if (xstats_names != NULL) {
3192                         count = 0;
3193
3194                         /* Note: limit >= cnt_stats checked upstream
3195                          * in rte_eth_xstats_names()
3196                          */
3197
3198                         /* Extended stats from ixgbe_hw_stats */
3199                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3200                                 snprintf(xstats_names[count].name,
3201                                         sizeof(xstats_names[count].name),
3202                                         "%s",
3203                                         rte_ixgbe_stats_strings[i].name);
3204                                 count++;
3205                         }
3206
3207                         /* MACsec Stats */
3208                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3209                                 snprintf(xstats_names[count].name,
3210                                         sizeof(xstats_names[count].name),
3211                                         "%s",
3212                                         rte_ixgbe_macsec_strings[i].name);
3213                                 count++;
3214                         }
3215
3216                         /* RX Priority Stats */
3217                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3218                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3219                                         snprintf(xstats_names[count].name,
3220                                             sizeof(xstats_names[count].name),
3221                                             "rx_priority%u_%s", i,
3222                                             rte_ixgbe_rxq_strings[stat].name);
3223                                         count++;
3224                                 }
3225                         }
3226
3227                         /* TX Priority Stats */
3228                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3229                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3230                                         snprintf(xstats_names[count].name,
3231                                             sizeof(xstats_names[count].name),
3232                                             "tx_priority%u_%s", i,
3233                                             rte_ixgbe_txq_strings[stat].name);
3234                                         count++;
3235                                 }
3236                         }
3237                 }
3238                 return cnt_stats;
3239         }
3240
3241         uint16_t i;
3242         uint16_t size = ixgbe_xstats_calc_num();
3243         struct rte_eth_xstat_name xstats_names_copy[size];
3244
3245         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3246                         size);
3247
3248         for (i = 0; i < limit; i++) {
3249                 if (ids[i] >= size) {
3250                         PMD_INIT_LOG(ERR, "id value isn't valid");
3251                         return -1;
3252                 }
3253                 strcpy(xstats_names[i].name,
3254                                 xstats_names_copy[ids[i]].name);
3255         }
3256         return limit;
3257 }
3258
3259 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3260         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3261 {
3262         unsigned i;
3263
3264         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3265                 return -ENOMEM;
3266
3267         if (xstats_names != NULL)
3268                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3269                         snprintf(xstats_names[i].name,
3270                                 sizeof(xstats_names[i].name),
3271                                 "%s", rte_ixgbevf_stats_strings[i].name);
3272         return IXGBEVF_NB_XSTATS;
3273 }
3274
3275 static int
3276 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3277                                          unsigned n)
3278 {
3279         struct ixgbe_hw *hw =
3280                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281         struct ixgbe_hw_stats *hw_stats =
3282                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3283         struct ixgbe_macsec_stats *macsec_stats =
3284                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3285                                 dev->data->dev_private);
3286         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3287         unsigned i, stat, count = 0;
3288
3289         count = ixgbe_xstats_calc_num();
3290
3291         if (n < count)
3292                 return count;
3293
3294         total_missed_rx = 0;
3295         total_qbrc = 0;
3296         total_qprc = 0;
3297         total_qprdc = 0;
3298
3299         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3300                         &total_qbrc, &total_qprc, &total_qprdc);
3301
3302         /* If this is a reset xstats is NULL, and we have cleared the
3303          * registers by reading them.
3304          */
3305         if (!xstats)
3306                 return 0;
3307
3308         /* Extended stats from ixgbe_hw_stats */
3309         count = 0;
3310         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3311                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3312                                 rte_ixgbe_stats_strings[i].offset);
3313                 xstats[count].id = count;
3314                 count++;
3315         }
3316
3317         /* MACsec Stats */
3318         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3319                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3320                                 rte_ixgbe_macsec_strings[i].offset);
3321                 xstats[count].id = count;
3322                 count++;
3323         }
3324
3325         /* RX Priority Stats */
3326         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3327                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3328                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3329                                         rte_ixgbe_rxq_strings[stat].offset +
3330                                         (sizeof(uint64_t) * i));
3331                         xstats[count].id = count;
3332                         count++;
3333                 }
3334         }
3335
3336         /* TX Priority Stats */
3337         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3338                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3339                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3340                                         rte_ixgbe_txq_strings[stat].offset +
3341                                         (sizeof(uint64_t) * i));
3342                         xstats[count].id = count;
3343                         count++;
3344                 }
3345         }
3346         return count;
3347 }
3348
3349 static int
3350 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3351                 uint64_t *values, unsigned int n)
3352 {
3353         if (!ids) {
3354                 struct ixgbe_hw *hw =
3355                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3356                 struct ixgbe_hw_stats *hw_stats =
3357                                 IXGBE_DEV_PRIVATE_TO_STATS(
3358                                                 dev->data->dev_private);
3359                 struct ixgbe_macsec_stats *macsec_stats =
3360                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3361                                         dev->data->dev_private);
3362                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3363                 unsigned int i, stat, count = 0;
3364
3365                 count = ixgbe_xstats_calc_num();
3366
3367                 if (!ids && n < count)
3368                         return count;
3369
3370                 total_missed_rx = 0;
3371                 total_qbrc = 0;
3372                 total_qprc = 0;
3373                 total_qprdc = 0;
3374
3375                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3376                                 &total_missed_rx, &total_qbrc, &total_qprc,
3377                                 &total_qprdc);
3378
3379                 /* If this is a reset xstats is NULL, and we have cleared the
3380                  * registers by reading them.
3381                  */
3382                 if (!ids && !values)
3383                         return 0;
3384
3385                 /* Extended stats from ixgbe_hw_stats */
3386                 count = 0;
3387                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3388                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3389                                         rte_ixgbe_stats_strings[i].offset);
3390                         count++;
3391                 }
3392
3393                 /* MACsec Stats */
3394                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3395                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3396                                         rte_ixgbe_macsec_strings[i].offset);
3397                         count++;
3398                 }
3399
3400                 /* RX Priority Stats */
3401                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3402                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3403                                 values[count] =
3404                                         *(uint64_t *)(((char *)hw_stats) +
3405                                         rte_ixgbe_rxq_strings[stat].offset +
3406                                         (sizeof(uint64_t) * i));
3407                                 count++;
3408                         }
3409                 }
3410
3411                 /* TX Priority Stats */
3412                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3413                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3414                                 values[count] =
3415                                         *(uint64_t *)(((char *)hw_stats) +
3416                                         rte_ixgbe_txq_strings[stat].offset +
3417                                         (sizeof(uint64_t) * i));
3418                                 count++;
3419                         }
3420                 }
3421                 return count;
3422         }
3423
3424         uint16_t i;
3425         uint16_t size = ixgbe_xstats_calc_num();
3426         uint64_t values_copy[size];
3427
3428         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3429
3430         for (i = 0; i < n; i++) {
3431                 if (ids[i] >= size) {
3432                         PMD_INIT_LOG(ERR, "id value isn't valid");
3433                         return -1;
3434                 }
3435                 values[i] = values_copy[ids[i]];
3436         }
3437         return n;
3438 }
3439
3440 static void
3441 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3442 {
3443         struct ixgbe_hw_stats *stats =
3444                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3445         struct ixgbe_macsec_stats *macsec_stats =
3446                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3447                                 dev->data->dev_private);
3448
3449         unsigned count = ixgbe_xstats_calc_num();
3450
3451         /* HW registers are cleared on read */
3452         ixgbe_dev_xstats_get(dev, NULL, count);
3453
3454         /* Reset software totals */
3455         memset(stats, 0, sizeof(*stats));
3456         memset(macsec_stats, 0, sizeof(*macsec_stats));
3457 }
3458
3459 static void
3460 ixgbevf_update_stats(struct rte_eth_dev *dev)
3461 {
3462         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3463         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3464                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3465
3466         /* Good Rx packet, include VF loopback */
3467         UPDATE_VF_STAT(IXGBE_VFGPRC,
3468             hw_stats->last_vfgprc, hw_stats->vfgprc);
3469
3470         /* Good Rx octets, include VF loopback */
3471         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3472             hw_stats->last_vfgorc, hw_stats->vfgorc);
3473
3474         /* Good Tx packet, include VF loopback */
3475         UPDATE_VF_STAT(IXGBE_VFGPTC,
3476             hw_stats->last_vfgptc, hw_stats->vfgptc);
3477
3478         /* Good Tx octets, include VF loopback */
3479         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3480             hw_stats->last_vfgotc, hw_stats->vfgotc);
3481
3482         /* Rx Multicst Packet */
3483         UPDATE_VF_STAT(IXGBE_VFMPRC,
3484             hw_stats->last_vfmprc, hw_stats->vfmprc);
3485 }
3486
3487 static int
3488 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3489                        unsigned n)
3490 {
3491         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3492                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3493         unsigned i;
3494
3495         if (n < IXGBEVF_NB_XSTATS)
3496                 return IXGBEVF_NB_XSTATS;
3497
3498         ixgbevf_update_stats(dev);
3499
3500         if (!xstats)
3501                 return 0;
3502
3503         /* Extended stats */
3504         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3505                 xstats[i].id = i;
3506                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3507                         rte_ixgbevf_stats_strings[i].offset);
3508         }
3509
3510         return IXGBEVF_NB_XSTATS;
3511 }
3512
3513 static int
3514 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3515 {
3516         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3517                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3518
3519         ixgbevf_update_stats(dev);
3520
3521         if (stats == NULL)
3522                 return -EINVAL;
3523
3524         stats->ipackets = hw_stats->vfgprc;
3525         stats->ibytes = hw_stats->vfgorc;
3526         stats->opackets = hw_stats->vfgptc;
3527         stats->obytes = hw_stats->vfgotc;
3528         return 0;
3529 }
3530
3531 static void
3532 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3533 {
3534         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3535                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3536
3537         /* Sync HW register to the last stats */
3538         ixgbevf_dev_stats_get(dev, NULL);
3539
3540         /* reset HW current stats*/
3541         hw_stats->vfgprc = 0;
3542         hw_stats->vfgorc = 0;
3543         hw_stats->vfgptc = 0;
3544         hw_stats->vfgotc = 0;
3545 }
3546
3547 static int
3548 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3549 {
3550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3551         u16 eeprom_verh, eeprom_verl;
3552         u32 etrack_id;
3553         int ret;
3554
3555         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3556         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3557
3558         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3559         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3560
3561         ret += 1; /* add the size of '\0' */
3562         if (fw_size < (u32)ret)
3563                 return ret;
3564         else
3565                 return 0;
3566 }
3567
3568 static void
3569 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3570 {
3571         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3572         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3573         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3574
3575         dev_info->pci_dev = pci_dev;
3576         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3577         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3578         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3579                 /*
3580                  * When DCB/VT is off, maximum number of queues changes,
3581                  * except for 82598EB, which remains constant.
3582                  */
3583                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3584                                 hw->mac.type != ixgbe_mac_82598EB)
3585                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3586         }
3587         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3588         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3589         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3590         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3591         dev_info->max_vfs = pci_dev->max_vfs;
3592         if (hw->mac.type == ixgbe_mac_82598EB)
3593                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3594         else
3595                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3596         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3597         dev_info->rx_offload_capa =
3598                 DEV_RX_OFFLOAD_VLAN_STRIP |
3599                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3600                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3601                 DEV_RX_OFFLOAD_TCP_CKSUM  |
3602                 DEV_RX_OFFLOAD_CRC_STRIP;
3603
3604         /*
3605          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3606          * mode.
3607          */
3608         if ((hw->mac.type == ixgbe_mac_82599EB ||
3609              hw->mac.type == ixgbe_mac_X540) &&
3610             !RTE_ETH_DEV_SRIOV(dev).active)
3611                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3612
3613         if (hw->mac.type == ixgbe_mac_82599EB ||
3614             hw->mac.type == ixgbe_mac_X540)
3615                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3616
3617         if (hw->mac.type == ixgbe_mac_X550 ||
3618             hw->mac.type == ixgbe_mac_X550EM_x ||
3619             hw->mac.type == ixgbe_mac_X550EM_a)
3620                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3621
3622         dev_info->tx_offload_capa =
3623                 DEV_TX_OFFLOAD_VLAN_INSERT |
3624                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3625                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3626                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3627                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3628                 DEV_TX_OFFLOAD_TCP_TSO;
3629
3630         if (hw->mac.type == ixgbe_mac_82599EB ||
3631             hw->mac.type == ixgbe_mac_X540)
3632                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3633
3634         if (hw->mac.type == ixgbe_mac_X550 ||
3635             hw->mac.type == ixgbe_mac_X550EM_x ||
3636             hw->mac.type == ixgbe_mac_X550EM_a)
3637                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3638
3639 #ifdef RTE_LIBRTE_SECURITY
3640         if (dev->security_ctx) {
3641                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3642                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3643         }
3644 #endif
3645
3646         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3647                 .rx_thresh = {
3648                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3649                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3650                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3651                 },
3652                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3653                 .rx_drop_en = 0,
3654         };
3655
3656         dev_info->default_txconf = (struct rte_eth_txconf) {
3657                 .tx_thresh = {
3658                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3659                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3660                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3661                 },
3662                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3663                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3664                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3665                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3666         };
3667
3668         dev_info->rx_desc_lim = rx_desc_lim;
3669         dev_info->tx_desc_lim = tx_desc_lim;
3670
3671         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3672         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3673         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3674
3675         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3676         if (hw->mac.type == ixgbe_mac_X540 ||
3677             hw->mac.type == ixgbe_mac_X540_vf ||
3678             hw->mac.type == ixgbe_mac_X550 ||
3679             hw->mac.type == ixgbe_mac_X550_vf) {
3680                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3681         }
3682         if (hw->mac.type == ixgbe_mac_X550) {
3683                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3684                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3685         }
3686 }
3687
3688 static const uint32_t *
3689 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3690 {
3691         static const uint32_t ptypes[] = {
3692                 /* For non-vec functions,
3693                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3694                  * for vec functions,
3695                  * refers to _recv_raw_pkts_vec().
3696                  */
3697                 RTE_PTYPE_L2_ETHER,
3698                 RTE_PTYPE_L3_IPV4,
3699                 RTE_PTYPE_L3_IPV4_EXT,
3700                 RTE_PTYPE_L3_IPV6,
3701                 RTE_PTYPE_L3_IPV6_EXT,
3702                 RTE_PTYPE_L4_SCTP,
3703                 RTE_PTYPE_L4_TCP,
3704                 RTE_PTYPE_L4_UDP,
3705                 RTE_PTYPE_TUNNEL_IP,
3706                 RTE_PTYPE_INNER_L3_IPV6,
3707                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3708                 RTE_PTYPE_INNER_L4_TCP,
3709                 RTE_PTYPE_INNER_L4_UDP,
3710                 RTE_PTYPE_UNKNOWN
3711         };
3712
3713         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3714             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3715             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3716             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3717                 return ptypes;
3718
3719 #if defined(RTE_ARCH_X86)
3720         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3721             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3722                 return ptypes;
3723 #endif
3724         return NULL;
3725 }
3726
3727 static void
3728 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3729                      struct rte_eth_dev_info *dev_info)
3730 {
3731         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3732         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3733
3734         dev_info->pci_dev = pci_dev;
3735         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3736         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3737         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3738         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3739         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3740         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3741         dev_info->max_vfs = pci_dev->max_vfs;
3742         if (hw->mac.type == ixgbe_mac_82598EB)
3743                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3744         else
3745                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3746         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3747                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3748                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3749                                 DEV_RX_OFFLOAD_TCP_CKSUM  |
3750                                 DEV_RX_OFFLOAD_CRC_STRIP;
3751         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3752                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3753                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3754                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3755                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3756                                 DEV_TX_OFFLOAD_TCP_TSO;
3757
3758         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3759                 .rx_thresh = {
3760                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3761                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3762                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3763                 },
3764                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3765                 .rx_drop_en = 0,
3766         };
3767
3768         dev_info->default_txconf = (struct rte_eth_txconf) {
3769                 .tx_thresh = {
3770                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3771                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3772                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3773                 },
3774                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3775                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3776                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3777                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3778         };
3779
3780         dev_info->rx_desc_lim = rx_desc_lim;
3781         dev_info->tx_desc_lim = tx_desc_lim;
3782 }
3783
3784 static int
3785 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3786                    int *link_up, int wait_to_complete)
3787 {
3788         /**
3789          * for a quick link status checking, wait_to_compelet == 0,
3790          * skip PF link status checking
3791          */
3792         bool no_pflink_check = wait_to_complete == 0;
3793         struct ixgbe_mbx_info *mbx = &hw->mbx;
3794         struct ixgbe_mac_info *mac = &hw->mac;
3795         uint32_t links_reg, in_msg;
3796         int ret_val = 0;
3797
3798         /* If we were hit with a reset drop the link */
3799         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3800                 mac->get_link_status = true;
3801
3802         if (!mac->get_link_status)
3803                 goto out;
3804
3805         /* if link status is down no point in checking to see if pf is up */
3806         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3807         if (!(links_reg & IXGBE_LINKS_UP))
3808                 goto out;
3809
3810         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3811          * before the link status is correct
3812          */
3813         if (mac->type == ixgbe_mac_82599_vf) {
3814                 int i;
3815
3816                 for (i = 0; i < 5; i++) {
3817                         rte_delay_us(100);
3818                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3819
3820                         if (!(links_reg & IXGBE_LINKS_UP))
3821                                 goto out;
3822                 }
3823         }
3824
3825         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3826         case IXGBE_LINKS_SPEED_10G_82599:
3827                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3828                 if (hw->mac.type >= ixgbe_mac_X550) {
3829                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3830                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3831                 }
3832                 break;
3833         case IXGBE_LINKS_SPEED_1G_82599:
3834                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3835                 break;
3836         case IXGBE_LINKS_SPEED_100_82599:
3837                 *speed = IXGBE_LINK_SPEED_100_FULL;
3838                 if (hw->mac.type == ixgbe_mac_X550) {
3839                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3840                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3841                 }
3842                 break;
3843         case IXGBE_LINKS_SPEED_10_X550EM_A:
3844                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3845                 /* Since Reserved in older MAC's */
3846                 if (hw->mac.type >= ixgbe_mac_X550)
3847                         *speed = IXGBE_LINK_SPEED_10_FULL;
3848                 break;
3849         default:
3850                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3851         }
3852
3853         if (no_pflink_check) {
3854                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3855                         mac->get_link_status = true;
3856                 else
3857                         mac->get_link_status = false;
3858
3859                 goto out;
3860         }
3861         /* if the read failed it could just be a mailbox collision, best wait
3862          * until we are called again and don't report an error
3863          */
3864         if (mbx->ops.read(hw, &in_msg, 1, 0))
3865                 goto out;
3866
3867         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3868                 /* msg is not CTS and is NACK we must have lost CTS status */
3869                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3870                         ret_val = -1;
3871                 goto out;
3872         }
3873
3874         /* the pf is talking, if we timed out in the past we reinit */
3875         if (!mbx->timeout) {
3876                 ret_val = -1;
3877                 goto out;
3878         }
3879
3880         /* if we passed all the tests above then the link is up and we no
3881          * longer need to check for link
3882          */
3883         mac->get_link_status = false;
3884
3885 out:
3886         *link_up = !mac->get_link_status;
3887         return ret_val;
3888 }
3889
3890 /* return 0 means link status changed, -1 means not changed */
3891 static int
3892 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3893                             int wait_to_complete, int vf)
3894 {
3895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3896         struct rte_eth_link link;
3897         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3898         struct ixgbe_interrupt *intr =
3899                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3900         int link_up;
3901         int diag;
3902         u32 speed = 0;
3903         int wait = 1;
3904         bool autoneg = false;
3905
3906         memset(&link, 0, sizeof(link));
3907         link.link_status = ETH_LINK_DOWN;
3908         link.link_speed = 0;
3909         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3910         link.link_autoneg = ETH_LINK_AUTONEG;
3911
3912         hw->mac.get_link_status = true;
3913
3914         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3915                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3916                 speed = hw->phy.autoneg_advertised;
3917                 if (!speed)
3918                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3919                 ixgbe_setup_link(hw, speed, true);
3920         }
3921
3922         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3923         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3924                 wait = 0;
3925
3926         if (vf)
3927                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3928         else
3929                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3930
3931         if (diag != 0) {
3932                 link.link_speed = ETH_SPEED_NUM_100M;
3933                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3934                 return rte_eth_linkstatus_set(dev, &link);
3935         }
3936
3937         if (link_up == 0) {
3938                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3939                 return rte_eth_linkstatus_set(dev, &link);
3940         }
3941
3942         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3943         link.link_status = ETH_LINK_UP;
3944         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3945
3946         switch (link_speed) {
3947         default:
3948         case IXGBE_LINK_SPEED_UNKNOWN:
3949                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3950                 link.link_speed = ETH_SPEED_NUM_100M;
3951                 break;
3952
3953         case IXGBE_LINK_SPEED_100_FULL:
3954                 link.link_speed = ETH_SPEED_NUM_100M;
3955                 break;
3956
3957         case IXGBE_LINK_SPEED_1GB_FULL:
3958                 link.link_speed = ETH_SPEED_NUM_1G;
3959                 break;
3960
3961         case IXGBE_LINK_SPEED_2_5GB_FULL:
3962                 link.link_speed = ETH_SPEED_NUM_2_5G;
3963                 break;
3964
3965         case IXGBE_LINK_SPEED_5GB_FULL:
3966                 link.link_speed = ETH_SPEED_NUM_5G;
3967                 break;
3968
3969         case IXGBE_LINK_SPEED_10GB_FULL:
3970                 link.link_speed = ETH_SPEED_NUM_10G;
3971                 break;
3972         }
3973
3974         return rte_eth_linkstatus_set(dev, &link);
3975 }
3976
3977 static int
3978 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3979 {
3980         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3981 }
3982
3983 static int
3984 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3985 {
3986         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3987 }
3988
3989 static void
3990 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3991 {
3992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3993         uint32_t fctrl;
3994
3995         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3996         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3997         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3998 }
3999
4000 static void
4001 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4002 {
4003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4004         uint32_t fctrl;
4005
4006         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4007         fctrl &= (~IXGBE_FCTRL_UPE);
4008         if (dev->data->all_multicast == 1)
4009                 fctrl |= IXGBE_FCTRL_MPE;
4010         else
4011                 fctrl &= (~IXGBE_FCTRL_MPE);
4012         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4013 }
4014
4015 static void
4016 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4017 {
4018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4019         uint32_t fctrl;
4020
4021         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4022         fctrl |= IXGBE_FCTRL_MPE;
4023         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4024 }
4025
4026 static void
4027 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4028 {
4029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4030         uint32_t fctrl;
4031
4032         if (dev->data->promiscuous == 1)
4033                 return; /* must remain in all_multicast mode */
4034
4035         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4036         fctrl &= (~IXGBE_FCTRL_MPE);
4037         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4038 }
4039
4040 /**
4041  * It clears the interrupt causes and enables the interrupt.
4042  * It will be called once only during nic initialized.
4043  *
4044  * @param dev
4045  *  Pointer to struct rte_eth_dev.
4046  * @param on
4047  *  Enable or Disable.
4048  *
4049  * @return
4050  *  - On success, zero.
4051  *  - On failure, a negative value.
4052  */
4053 static int
4054 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4055 {
4056         struct ixgbe_interrupt *intr =
4057                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4058
4059         ixgbe_dev_link_status_print(dev);
4060         if (on)
4061                 intr->mask |= IXGBE_EICR_LSC;
4062         else
4063                 intr->mask &= ~IXGBE_EICR_LSC;
4064
4065         return 0;
4066 }
4067
4068 /**
4069  * It clears the interrupt causes and enables the interrupt.
4070  * It will be called once only during nic initialized.
4071  *
4072  * @param dev
4073  *  Pointer to struct rte_eth_dev.
4074  *
4075  * @return
4076  *  - On success, zero.
4077  *  - On failure, a negative value.
4078  */
4079 static int
4080 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4081 {
4082         struct ixgbe_interrupt *intr =
4083                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4084
4085         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4086
4087         return 0;
4088 }
4089
4090 /**
4091  * It clears the interrupt causes and enables the interrupt.
4092  * It will be called once only during nic initialized.
4093  *
4094  * @param dev
4095  *  Pointer to struct rte_eth_dev.
4096  *
4097  * @return
4098  *  - On success, zero.
4099  *  - On failure, a negative value.
4100  */
4101 static int
4102 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4103 {
4104         struct ixgbe_interrupt *intr =
4105                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4106
4107         intr->mask |= IXGBE_EICR_LINKSEC;
4108
4109         return 0;
4110 }
4111
4112 /*
4113  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4114  *
4115  * @param dev
4116  *  Pointer to struct rte_eth_dev.
4117  *
4118  * @return
4119  *  - On success, zero.
4120  *  - On failure, a negative value.
4121  */
4122 static int
4123 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4124 {
4125         uint32_t eicr;
4126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127         struct ixgbe_interrupt *intr =
4128                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4129
4130         /* clear all cause mask */
4131         ixgbe_disable_intr(hw);
4132
4133         /* read-on-clear nic registers here */
4134         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4135         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4136
4137         intr->flags = 0;
4138
4139         /* set flag for async link update */
4140         if (eicr & IXGBE_EICR_LSC)
4141                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4142
4143         if (eicr & IXGBE_EICR_MAILBOX)
4144                 intr->flags |= IXGBE_FLAG_MAILBOX;
4145
4146         if (eicr & IXGBE_EICR_LINKSEC)
4147                 intr->flags |= IXGBE_FLAG_MACSEC;
4148
4149         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4150             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4151             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4152                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4153
4154         return 0;
4155 }
4156
4157 /**
4158  * It gets and then prints the link status.
4159  *
4160  * @param dev
4161  *  Pointer to struct rte_eth_dev.
4162  *
4163  * @return
4164  *  - On success, zero.
4165  *  - On failure, a negative value.
4166  */
4167 static void
4168 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4169 {
4170         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4171         struct rte_eth_link link;
4172
4173         rte_eth_linkstatus_get(dev, &link);
4174
4175         if (link.link_status) {
4176                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4177                                         (int)(dev->data->port_id),
4178                                         (unsigned)link.link_speed,
4179                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4180                                         "full-duplex" : "half-duplex");
4181         } else {
4182                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4183                                 (int)(dev->data->port_id));
4184         }
4185         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4186                                 pci_dev->addr.domain,
4187                                 pci_dev->addr.bus,
4188                                 pci_dev->addr.devid,
4189                                 pci_dev->addr.function);
4190 }
4191
4192 /*
4193  * It executes link_update after knowing an interrupt occurred.
4194  *
4195  * @param dev
4196  *  Pointer to struct rte_eth_dev.
4197  *
4198  * @return
4199  *  - On success, zero.
4200  *  - On failure, a negative value.
4201  */
4202 static int
4203 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4204                            struct rte_intr_handle *intr_handle)
4205 {
4206         struct ixgbe_interrupt *intr =
4207                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4208         int64_t timeout;
4209         struct ixgbe_hw *hw =
4210                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4211
4212         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4213
4214         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4215                 ixgbe_pf_mbx_process(dev);
4216                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4217         }
4218
4219         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4220                 ixgbe_handle_lasi(hw);
4221                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4222         }
4223
4224         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4225                 struct rte_eth_link link;
4226
4227                 /* get the link status before link update, for predicting later */
4228                 rte_eth_linkstatus_get(dev, &link);
4229
4230                 ixgbe_dev_link_update(dev, 0);
4231
4232                 /* likely to up */
4233                 if (!link.link_status)
4234                         /* handle it 1 sec later, wait it being stable */
4235                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4236                 /* likely to down */
4237                 else
4238                         /* handle it 4 sec later, wait it being stable */
4239                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4240
4241                 ixgbe_dev_link_status_print(dev);
4242                 if (rte_eal_alarm_set(timeout * 1000,
4243                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4244                         PMD_DRV_LOG(ERR, "Error setting alarm");
4245                 else {
4246                         /* remember original mask */
4247                         intr->mask_original = intr->mask;
4248                         /* only disable lsc interrupt */
4249                         intr->mask &= ~IXGBE_EIMS_LSC;
4250                 }
4251         }
4252
4253         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4254         ixgbe_enable_intr(dev);
4255         rte_intr_enable(intr_handle);
4256
4257         return 0;
4258 }
4259
4260 /**
4261  * Interrupt handler which shall be registered for alarm callback for delayed
4262  * handling specific interrupt to wait for the stable nic state. As the
4263  * NIC interrupt state is not stable for ixgbe after link is just down,
4264  * it needs to wait 4 seconds to get the stable status.
4265  *
4266  * @param handle
4267  *  Pointer to interrupt handle.
4268  * @param param
4269  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4270  *
4271  * @return
4272  *  void
4273  */
4274 static void
4275 ixgbe_dev_interrupt_delayed_handler(void *param)
4276 {
4277         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4278         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4279         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4280         struct ixgbe_interrupt *intr =
4281                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4282         struct ixgbe_hw *hw =
4283                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4284         uint32_t eicr;
4285
4286         ixgbe_disable_intr(hw);
4287
4288         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4289         if (eicr & IXGBE_EICR_MAILBOX)
4290                 ixgbe_pf_mbx_process(dev);
4291
4292         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4293                 ixgbe_handle_lasi(hw);
4294                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4295         }
4296
4297         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4298                 ixgbe_dev_link_update(dev, 0);
4299                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4300                 ixgbe_dev_link_status_print(dev);
4301                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4302                                               NULL);
4303         }
4304
4305         if (intr->flags & IXGBE_FLAG_MACSEC) {
4306                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4307                                               NULL);
4308                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4309         }
4310
4311         /* restore original mask */
4312         intr->mask = intr->mask_original;
4313         intr->mask_original = 0;
4314
4315         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4316         ixgbe_enable_intr(dev);
4317         rte_intr_enable(intr_handle);
4318 }
4319
4320 /**
4321  * Interrupt handler triggered by NIC  for handling
4322  * specific interrupt.
4323  *
4324  * @param handle
4325  *  Pointer to interrupt handle.
4326  * @param param
4327  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4328  *
4329  * @return
4330  *  void
4331  */
4332 static void
4333 ixgbe_dev_interrupt_handler(void *param)
4334 {
4335         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4336
4337         ixgbe_dev_interrupt_get_status(dev);
4338         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4339 }
4340
4341 static int
4342 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4343 {
4344         struct ixgbe_hw *hw;
4345
4346         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4347         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4348 }
4349
4350 static int
4351 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4352 {
4353         struct ixgbe_hw *hw;
4354
4355         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4356         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4357 }
4358
4359 static int
4360 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4361 {
4362         struct ixgbe_hw *hw;
4363         uint32_t mflcn_reg;
4364         uint32_t fccfg_reg;
4365         int rx_pause;
4366         int tx_pause;
4367
4368         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4369
4370         fc_conf->pause_time = hw->fc.pause_time;
4371         fc_conf->high_water = hw->fc.high_water[0];
4372         fc_conf->low_water = hw->fc.low_water[0];
4373         fc_conf->send_xon = hw->fc.send_xon;
4374         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4375
4376         /*
4377          * Return rx_pause status according to actual setting of
4378          * MFLCN register.
4379          */
4380         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4381         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4382                 rx_pause = 1;
4383         else
4384                 rx_pause = 0;
4385
4386         /*
4387          * Return tx_pause status according to actual setting of
4388          * FCCFG register.
4389          */
4390         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4391         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4392                 tx_pause = 1;
4393         else
4394                 tx_pause = 0;
4395
4396         if (rx_pause && tx_pause)
4397                 fc_conf->mode = RTE_FC_FULL;
4398         else if (rx_pause)
4399                 fc_conf->mode = RTE_FC_RX_PAUSE;
4400         else if (tx_pause)
4401                 fc_conf->mode = RTE_FC_TX_PAUSE;
4402         else
4403                 fc_conf->mode = RTE_FC_NONE;
4404
4405         return 0;
4406 }
4407
4408 static int
4409 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4410 {
4411         struct ixgbe_hw *hw;
4412         int err;
4413         uint32_t rx_buf_size;
4414         uint32_t max_high_water;
4415         uint32_t mflcn;
4416         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4417                 ixgbe_fc_none,
4418                 ixgbe_fc_rx_pause,
4419                 ixgbe_fc_tx_pause,
4420                 ixgbe_fc_full
4421         };
4422
4423         PMD_INIT_FUNC_TRACE();
4424
4425         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4426         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4427         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4428
4429         /*
4430          * At least reserve one Ethernet frame for watermark
4431          * high_water/low_water in kilo bytes for ixgbe
4432          */
4433         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4434         if ((fc_conf->high_water > max_high_water) ||
4435                 (fc_conf->high_water < fc_conf->low_water)) {
4436                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4437                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4438                 return -EINVAL;
4439         }
4440
4441         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4442         hw->fc.pause_time     = fc_conf->pause_time;
4443         hw->fc.high_water[0]  = fc_conf->high_water;
4444         hw->fc.low_water[0]   = fc_conf->low_water;
4445         hw->fc.send_xon       = fc_conf->send_xon;
4446         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4447
4448         err = ixgbe_fc_enable(hw);
4449
4450         /* Not negotiated is not an error case */
4451         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4452
4453                 /* check if we want to forward MAC frames - driver doesn't have native
4454                  * capability to do that, so we'll write the registers ourselves */
4455
4456                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4457
4458                 /* set or clear MFLCN.PMCF bit depending on configuration */
4459                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4460                         mflcn |= IXGBE_MFLCN_PMCF;
4461                 else
4462                         mflcn &= ~IXGBE_MFLCN_PMCF;
4463
4464                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4465                 IXGBE_WRITE_FLUSH(hw);
4466
4467                 return 0;
4468         }
4469
4470         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4471         return -EIO;
4472 }
4473
4474 /**
4475  *  ixgbe_pfc_enable_generic - Enable flow control
4476  *  @hw: pointer to hardware structure
4477  *  @tc_num: traffic class number
4478  *  Enable flow control according to the current settings.
4479  */
4480 static int
4481 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4482 {
4483         int ret_val = 0;
4484         uint32_t mflcn_reg, fccfg_reg;
4485         uint32_t reg;
4486         uint32_t fcrtl, fcrth;
4487         uint8_t i;
4488         uint8_t nb_rx_en;
4489
4490         /* Validate the water mark configuration */
4491         if (!hw->fc.pause_time) {
4492                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4493                 goto out;
4494         }
4495
4496         /* Low water mark of zero causes XOFF floods */
4497         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4498                  /* High/Low water can not be 0 */
4499                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4500                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4501                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4502                         goto out;
4503                 }
4504
4505                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4506                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4507                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4508                         goto out;
4509                 }
4510         }
4511         /* Negotiate the fc mode to use */
4512         ixgbe_fc_autoneg(hw);
4513
4514         /* Disable any previous flow control settings */
4515         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4516         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4517
4518         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4519         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4520
4521         switch (hw->fc.current_mode) {
4522         case ixgbe_fc_none:
4523                 /*
4524                  * If the count of enabled RX Priority Flow control >1,
4525                  * and the TX pause can not be disabled
4526                  */
4527                 nb_rx_en = 0;
4528                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4529                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4530                         if (reg & IXGBE_FCRTH_FCEN)
4531                                 nb_rx_en++;
4532                 }
4533                 if (nb_rx_en > 1)
4534                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4535                 break;
4536         case ixgbe_fc_rx_pause:
4537                 /*
4538                  * Rx Flow control is enabled and Tx Flow control is
4539                  * disabled by software override. Since there really
4540                  * isn't a way to advertise that we are capable of RX
4541                  * Pause ONLY, we will advertise that we support both
4542                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4543                  * disable the adapter's ability to send PAUSE frames.
4544                  */
4545                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4546                 /*
4547                  * If the count of enabled RX Priority Flow control >1,
4548                  * and the TX pause can not be disabled
4549                  */
4550                 nb_rx_en = 0;
4551                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4552                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4553                         if (reg & IXGBE_FCRTH_FCEN)
4554                                 nb_rx_en++;
4555                 }
4556                 if (nb_rx_en > 1)
4557                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4558                 break;
4559         case ixgbe_fc_tx_pause:
4560                 /*
4561                  * Tx Flow control is enabled, and Rx Flow control is
4562                  * disabled by software override.
4563                  */
4564                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4565                 break;
4566         case ixgbe_fc_full:
4567                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4568                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4569                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4570                 break;
4571         default:
4572                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4573                 ret_val = IXGBE_ERR_CONFIG;
4574                 goto out;
4575         }
4576
4577         /* Set 802.3x based flow control settings. */
4578         mflcn_reg |= IXGBE_MFLCN_DPF;
4579         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4580         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4581
4582         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4583         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4584                 hw->fc.high_water[tc_num]) {
4585                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4586                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4587                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4588         } else {
4589                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4590                 /*
4591                  * In order to prevent Tx hangs when the internal Tx
4592                  * switch is enabled we must set the high water mark
4593                  * to the maximum FCRTH value.  This allows the Tx
4594                  * switch to function even under heavy Rx workloads.
4595                  */
4596                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4597         }
4598         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4599
4600         /* Configure pause time (2 TCs per register) */
4601         reg = hw->fc.pause_time * 0x00010001;
4602         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4603                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4604
4605         /* Configure flow control refresh threshold value */
4606         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4607
4608 out:
4609         return ret_val;
4610 }
4611
4612 static int
4613 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4614 {
4615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4617
4618         if (hw->mac.type != ixgbe_mac_82598EB) {
4619                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4620         }
4621         return ret_val;
4622 }
4623
4624 static int
4625 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4626 {
4627         int err;
4628         uint32_t rx_buf_size;
4629         uint32_t max_high_water;
4630         uint8_t tc_num;
4631         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4632         struct ixgbe_hw *hw =
4633                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4634         struct ixgbe_dcb_config *dcb_config =
4635                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4636
4637         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4638                 ixgbe_fc_none,
4639                 ixgbe_fc_rx_pause,
4640                 ixgbe_fc_tx_pause,
4641                 ixgbe_fc_full
4642         };
4643
4644         PMD_INIT_FUNC_TRACE();
4645
4646         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4647         tc_num = map[pfc_conf->priority];
4648         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4649         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4650         /*
4651          * At least reserve one Ethernet frame for watermark
4652          * high_water/low_water in kilo bytes for ixgbe
4653          */
4654         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4655         if ((pfc_conf->fc.high_water > max_high_water) ||
4656             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4657                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4658                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4659                 return -EINVAL;
4660         }
4661
4662         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4663         hw->fc.pause_time = pfc_conf->fc.pause_time;
4664         hw->fc.send_xon = pfc_conf->fc.send_xon;
4665         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4666         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4667
4668         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4669
4670         /* Not negotiated is not an error case */
4671         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4672                 return 0;
4673
4674         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4675         return -EIO;
4676 }
4677
4678 static int
4679 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4680                           struct rte_eth_rss_reta_entry64 *reta_conf,
4681                           uint16_t reta_size)
4682 {
4683         uint16_t i, sp_reta_size;
4684         uint8_t j, mask;
4685         uint32_t reta, r;
4686         uint16_t idx, shift;
4687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4688         uint32_t reta_reg;
4689
4690         PMD_INIT_FUNC_TRACE();
4691
4692         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4693                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4694                         "NIC.");
4695                 return -ENOTSUP;
4696         }
4697
4698         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4699         if (reta_size != sp_reta_size) {
4700                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4701                         "(%d) doesn't match the number hardware can supported "
4702                         "(%d)", reta_size, sp_reta_size);
4703                 return -EINVAL;
4704         }
4705
4706         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4707                 idx = i / RTE_RETA_GROUP_SIZE;
4708                 shift = i % RTE_RETA_GROUP_SIZE;
4709                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4710                                                 IXGBE_4_BIT_MASK);
4711                 if (!mask)
4712                         continue;
4713                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4714                 if (mask == IXGBE_4_BIT_MASK)
4715                         r = 0;
4716                 else
4717                         r = IXGBE_READ_REG(hw, reta_reg);
4718                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4719                         if (mask & (0x1 << j))
4720                                 reta |= reta_conf[idx].reta[shift + j] <<
4721                                                         (CHAR_BIT * j);
4722                         else
4723                                 reta |= r & (IXGBE_8_BIT_MASK <<
4724                                                 (CHAR_BIT * j));
4725                 }
4726                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4727         }
4728
4729         return 0;
4730 }
4731
4732 static int
4733 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4734                          struct rte_eth_rss_reta_entry64 *reta_conf,
4735                          uint16_t reta_size)
4736 {
4737         uint16_t i, sp_reta_size;
4738         uint8_t j, mask;
4739         uint32_t reta;
4740         uint16_t idx, shift;
4741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742         uint32_t reta_reg;
4743
4744         PMD_INIT_FUNC_TRACE();
4745         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4746         if (reta_size != sp_reta_size) {
4747                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4748                         "(%d) doesn't match the number hardware can supported "
4749                         "(%d)", reta_size, sp_reta_size);
4750                 return -EINVAL;
4751         }
4752
4753         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4754                 idx = i / RTE_RETA_GROUP_SIZE;
4755                 shift = i % RTE_RETA_GROUP_SIZE;
4756                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4757                                                 IXGBE_4_BIT_MASK);
4758                 if (!mask)
4759                         continue;
4760
4761                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4762                 reta = IXGBE_READ_REG(hw, reta_reg);
4763                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4764                         if (mask & (0x1 << j))
4765                                 reta_conf[idx].reta[shift + j] =
4766                                         ((reta >> (CHAR_BIT * j)) &
4767                                                 IXGBE_8_BIT_MASK);
4768                 }
4769         }
4770
4771         return 0;
4772 }
4773
4774 static int
4775 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4776                                 uint32_t index, uint32_t pool)
4777 {
4778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4779         uint32_t enable_addr = 1;
4780
4781         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4782                              pool, enable_addr);
4783 }
4784
4785 static void
4786 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4787 {
4788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789
4790         ixgbe_clear_rar(hw, index);
4791 }
4792
4793 static void
4794 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4795 {
4796         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4797
4798         ixgbe_remove_rar(dev, 0);
4799
4800         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4801 }
4802
4803 static bool
4804 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4805 {
4806         if (strcmp(dev->device->driver->name, drv->driver.name))
4807                 return false;
4808
4809         return true;
4810 }
4811
4812 bool
4813 is_ixgbe_supported(struct rte_eth_dev *dev)
4814 {
4815         return is_device_supported(dev, &rte_ixgbe_pmd);
4816 }
4817
4818 static int
4819 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4820 {
4821         uint32_t hlreg0;
4822         uint32_t maxfrs;
4823         struct ixgbe_hw *hw;
4824         struct rte_eth_dev_info dev_info;
4825         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4826         struct rte_eth_dev_data *dev_data = dev->data;
4827
4828         ixgbe_dev_info_get(dev, &dev_info);
4829
4830         /* check that mtu is within the allowed range */
4831         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4832                 return -EINVAL;
4833
4834         /* If device is started, refuse mtu that requires the support of
4835          * scattered packets when this feature has not been enabled before.
4836          */
4837         if (dev_data->dev_started && !dev_data->scattered_rx &&
4838             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4839              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4840                 PMD_INIT_LOG(ERR, "Stop port first.");
4841                 return -EINVAL;
4842         }
4843
4844         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4846
4847         /* switch to jumbo mode if needed */
4848         if (frame_size > ETHER_MAX_LEN) {
4849                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4850                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4851         } else {
4852                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4853                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4854         }
4855         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4856
4857         /* update max frame size */
4858         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4859
4860         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4861         maxfrs &= 0x0000FFFF;
4862         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4863         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4864
4865         return 0;
4866 }
4867
4868 /*
4869  * Virtual Function operations
4870  */
4871 static void
4872 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4873 {
4874         PMD_INIT_FUNC_TRACE();
4875
4876         /* Clear interrupt mask to stop from interrupts being generated */
4877         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4878
4879         IXGBE_WRITE_FLUSH(hw);
4880 }
4881
4882 static void
4883 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4884 {
4885         PMD_INIT_FUNC_TRACE();
4886
4887         /* VF enable interrupt autoclean */
4888         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4889         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4890         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4891
4892         IXGBE_WRITE_FLUSH(hw);
4893 }
4894
4895 static int
4896 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4897 {
4898         struct rte_eth_conf *conf = &dev->data->dev_conf;
4899         struct ixgbe_adapter *adapter =
4900                         (struct ixgbe_adapter *)dev->data->dev_private;
4901
4902         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4903                      dev->data->port_id);
4904
4905         /*
4906          * VF has no ability to enable/disable HW CRC
4907          * Keep the persistent behavior the same as Host PF
4908          */
4909 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4910         if (!conf->rxmode.hw_strip_crc) {
4911                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4912                 conf->rxmode.hw_strip_crc = 1;
4913         }
4914 #else
4915         if (conf->rxmode.hw_strip_crc) {
4916                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4917                 conf->rxmode.hw_strip_crc = 0;
4918         }
4919 #endif
4920
4921         /*
4922          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4923          * allocation or vector Rx preconditions we will reset it.
4924          */
4925         adapter->rx_bulk_alloc_allowed = true;
4926         adapter->rx_vec_allowed = true;
4927
4928         return 0;
4929 }
4930
4931 static int
4932 ixgbevf_dev_start(struct rte_eth_dev *dev)
4933 {
4934         struct ixgbe_hw *hw =
4935                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4936         uint32_t intr_vector = 0;
4937         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4938         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4939
4940         int err, mask = 0;
4941
4942         PMD_INIT_FUNC_TRACE();
4943
4944         err = hw->mac.ops.reset_hw(hw);
4945         if (err) {
4946                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4947                 return err;
4948         }
4949         hw->mac.get_link_status = true;
4950
4951         /* negotiate mailbox API version to use with the PF. */
4952         ixgbevf_negotiate_api(hw);
4953
4954         ixgbevf_dev_tx_init(dev);
4955
4956         /* This can fail when allocating mbufs for descriptor rings */
4957         err = ixgbevf_dev_rx_init(dev);
4958         if (err) {
4959                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4960                 ixgbe_dev_clear_queues(dev);
4961                 return err;
4962         }
4963
4964         /* Set vfta */
4965         ixgbevf_set_vfta_all(dev, 1);
4966
4967         /* Set HW strip */
4968         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4969                 ETH_VLAN_EXTEND_MASK;
4970         err = ixgbevf_vlan_offload_set(dev, mask);
4971         if (err) {
4972                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4973                 ixgbe_dev_clear_queues(dev);
4974                 return err;
4975         }
4976
4977         ixgbevf_dev_rxtx_start(dev);
4978
4979         /* check and configure queue intr-vector mapping */
4980         if (rte_intr_cap_multiple(intr_handle) &&
4981             dev->data->dev_conf.intr_conf.rxq) {
4982                 /* According to datasheet, only vector 0/1/2 can be used,
4983                  * now only one vector is used for Rx queue
4984                  */
4985                 intr_vector = 1;
4986                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4987                         return -1;
4988         }
4989
4990         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4991                 intr_handle->intr_vec =
4992                         rte_zmalloc("intr_vec",
4993                                     dev->data->nb_rx_queues * sizeof(int), 0);
4994                 if (intr_handle->intr_vec == NULL) {
4995                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4996                                      " intr_vec", dev->data->nb_rx_queues);
4997                         return -ENOMEM;
4998                 }
4999         }
5000         ixgbevf_configure_msix(dev);
5001
5002         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5003          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5004          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5005          * is not cleared, it will fail when following rte_intr_enable( ) tries
5006          * to map Rx queue interrupt to other VFIO vectors.
5007          * So clear uio/vfio intr/evevnfd first to avoid failure.
5008          */
5009         rte_intr_disable(intr_handle);
5010
5011         rte_intr_enable(intr_handle);
5012
5013         /* Re-enable interrupt for VF */
5014         ixgbevf_intr_enable(hw);
5015
5016         return 0;
5017 }
5018
5019 static void
5020 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5021 {
5022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5023         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5024         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5025
5026         PMD_INIT_FUNC_TRACE();
5027
5028         ixgbevf_intr_disable(hw);
5029
5030         hw->adapter_stopped = 1;
5031         ixgbe_stop_adapter(hw);
5032
5033         /*
5034           * Clear what we set, but we still keep shadow_vfta to
5035           * restore after device starts
5036           */
5037         ixgbevf_set_vfta_all(dev, 0);
5038
5039         /* Clear stored conf */
5040         dev->data->scattered_rx = 0;
5041
5042         ixgbe_dev_clear_queues(dev);
5043
5044         /* Clean datapath event and queue/vec mapping */
5045         rte_intr_efd_disable(intr_handle);
5046         if (intr_handle->intr_vec != NULL) {
5047                 rte_free(intr_handle->intr_vec);
5048                 intr_handle->intr_vec = NULL;
5049         }
5050 }
5051
5052 static void
5053 ixgbevf_dev_close(struct rte_eth_dev *dev)
5054 {
5055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5056
5057         PMD_INIT_FUNC_TRACE();
5058
5059         ixgbe_reset_hw(hw);
5060
5061         ixgbevf_dev_stop(dev);
5062
5063         ixgbe_dev_free_queues(dev);
5064
5065         /**
5066          * Remove the VF MAC address ro ensure
5067          * that the VF traffic goes to the PF
5068          * after stop, close and detach of the VF
5069          **/
5070         ixgbevf_remove_mac_addr(dev, 0);
5071 }
5072
5073 /*
5074  * Reset VF device
5075  */
5076 static int
5077 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5078 {
5079         int ret;
5080
5081         ret = eth_ixgbevf_dev_uninit(dev);
5082         if (ret)
5083                 return ret;
5084
5085         ret = eth_ixgbevf_dev_init(dev);
5086
5087         return ret;
5088 }
5089
5090 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5091 {
5092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5093         struct ixgbe_vfta *shadow_vfta =
5094                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5095         int i = 0, j = 0, vfta = 0, mask = 1;
5096
5097         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5098                 vfta = shadow_vfta->vfta[i];
5099                 if (vfta) {
5100                         mask = 1;
5101                         for (j = 0; j < 32; j++) {
5102                                 if (vfta & mask)
5103                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5104                                                        on, false);
5105                                 mask <<= 1;
5106                         }
5107                 }
5108         }
5109
5110 }
5111
5112 static int
5113 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5114 {
5115         struct ixgbe_hw *hw =
5116                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5117         struct ixgbe_vfta *shadow_vfta =
5118                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5119         uint32_t vid_idx = 0;
5120         uint32_t vid_bit = 0;
5121         int ret = 0;
5122
5123         PMD_INIT_FUNC_TRACE();
5124
5125         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5126         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5127         if (ret) {
5128                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5129                 return ret;
5130         }
5131         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5132         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5133
5134         /* Save what we set and retore it after device reset */
5135         if (on)
5136                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5137         else
5138                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5139
5140         return 0;
5141 }
5142
5143 static void
5144 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5145 {
5146         struct ixgbe_hw *hw =
5147                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5148         uint32_t ctrl;
5149
5150         PMD_INIT_FUNC_TRACE();
5151
5152         if (queue >= hw->mac.max_rx_queues)
5153                 return;
5154
5155         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5156         if (on)
5157                 ctrl |= IXGBE_RXDCTL_VME;
5158         else
5159                 ctrl &= ~IXGBE_RXDCTL_VME;
5160         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5161
5162         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5163 }
5164
5165 static int
5166 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5167 {
5168         struct ixgbe_hw *hw =
5169                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5170         uint16_t i;
5171         int on = 0;
5172
5173         /* VF function only support hw strip feature, others are not support */
5174         if (mask & ETH_VLAN_STRIP_MASK) {
5175                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5176
5177                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5178                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5179         }
5180
5181         return 0;
5182 }
5183
5184 int
5185 ixgbe_vt_check(struct ixgbe_hw *hw)
5186 {
5187         uint32_t reg_val;
5188
5189         /* if Virtualization Technology is enabled */
5190         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5191         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5192                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5193                 return -1;
5194         }
5195
5196         return 0;
5197 }
5198
5199 static uint32_t
5200 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5201 {
5202         uint32_t vector = 0;
5203
5204         switch (hw->mac.mc_filter_type) {
5205         case 0:   /* use bits [47:36] of the address */
5206                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5207                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5208                 break;
5209         case 1:   /* use bits [46:35] of the address */
5210                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5211                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5212                 break;
5213         case 2:   /* use bits [45:34] of the address */
5214                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5215                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5216                 break;
5217         case 3:   /* use bits [43:32] of the address */
5218                 vector = ((uc_addr->addr_bytes[4]) |
5219                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5220                 break;
5221         default:  /* Invalid mc_filter_type */
5222                 break;
5223         }
5224
5225         /* vector can only be 12-bits or boundary will be exceeded */
5226         vector &= 0xFFF;
5227         return vector;
5228 }
5229
5230 static int
5231 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5232                         uint8_t on)
5233 {
5234         uint32_t vector;
5235         uint32_t uta_idx;
5236         uint32_t reg_val;
5237         uint32_t uta_shift;
5238         uint32_t rc;
5239         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5240         const uint32_t ixgbe_uta_bit_shift = 5;
5241         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5242         const uint32_t bit1 = 0x1;
5243
5244         struct ixgbe_hw *hw =
5245                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5246         struct ixgbe_uta_info *uta_info =
5247                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5248
5249         /* The UTA table only exists on 82599 hardware and newer */
5250         if (hw->mac.type < ixgbe_mac_82599EB)
5251                 return -ENOTSUP;
5252
5253         vector = ixgbe_uta_vector(hw, mac_addr);
5254         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5255         uta_shift = vector & ixgbe_uta_bit_mask;
5256
5257         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5258         if (rc == on)
5259                 return 0;
5260
5261         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5262         if (on) {
5263                 uta_info->uta_in_use++;
5264                 reg_val |= (bit1 << uta_shift);
5265                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5266         } else {
5267                 uta_info->uta_in_use--;
5268                 reg_val &= ~(bit1 << uta_shift);
5269                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5270         }
5271
5272         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5273
5274         if (uta_info->uta_in_use > 0)
5275                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5276                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5277         else
5278                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5279
5280         return 0;
5281 }
5282
5283 static int
5284 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5285 {
5286         int i;
5287         struct ixgbe_hw *hw =
5288                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5289         struct ixgbe_uta_info *uta_info =
5290                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5291
5292         /* The UTA table only exists on 82599 hardware and newer */
5293         if (hw->mac.type < ixgbe_mac_82599EB)
5294                 return -ENOTSUP;
5295
5296         if (on) {
5297                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5298                         uta_info->uta_shadow[i] = ~0;
5299                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5300                 }
5301         } else {
5302                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5303                         uta_info->uta_shadow[i] = 0;
5304                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5305                 }
5306         }
5307         return 0;
5308
5309 }
5310
5311 uint32_t
5312 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5313 {
5314         uint32_t new_val = orig_val;
5315
5316         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5317                 new_val |= IXGBE_VMOLR_AUPE;
5318         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5319                 new_val |= IXGBE_VMOLR_ROMPE;
5320         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5321                 new_val |= IXGBE_VMOLR_ROPE;
5322         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5323                 new_val |= IXGBE_VMOLR_BAM;
5324         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5325                 new_val |= IXGBE_VMOLR_MPE;
5326
5327         return new_val;
5328 }
5329
5330 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5331 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5332 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5333 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5334 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5335         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5336         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5337
5338 static int
5339 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5340                       struct rte_eth_mirror_conf *mirror_conf,
5341                       uint8_t rule_id, uint8_t on)
5342 {
5343         uint32_t mr_ctl, vlvf;
5344         uint32_t mp_lsb = 0;
5345         uint32_t mv_msb = 0;
5346         uint32_t mv_lsb = 0;
5347         uint32_t mp_msb = 0;
5348         uint8_t i = 0;
5349         int reg_index = 0;
5350         uint64_t vlan_mask = 0;
5351
5352         const uint8_t pool_mask_offset = 32;
5353         const uint8_t vlan_mask_offset = 32;
5354         const uint8_t dst_pool_offset = 8;
5355         const uint8_t rule_mr_offset  = 4;
5356         const uint8_t mirror_rule_mask = 0x0F;
5357
5358         struct ixgbe_mirror_info *mr_info =
5359                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5360         struct ixgbe_hw *hw =
5361                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5362         uint8_t mirror_type = 0;
5363
5364         if (ixgbe_vt_check(hw) < 0)
5365                 return -ENOTSUP;
5366
5367         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5368                 return -EINVAL;
5369
5370         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5371                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5372                             mirror_conf->rule_type);
5373                 return -EINVAL;
5374         }
5375
5376         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5377                 mirror_type |= IXGBE_MRCTL_VLME;
5378                 /* Check if vlan id is valid and find conresponding VLAN ID
5379                  * index in VLVF
5380                  */
5381                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5382                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5383                                 /* search vlan id related pool vlan filter
5384                                  * index
5385                                  */
5386                                 reg_index = ixgbe_find_vlvf_slot(
5387                                                 hw,
5388                                                 mirror_conf->vlan.vlan_id[i],
5389                                                 false);
5390                                 if (reg_index < 0)
5391                                         return -EINVAL;
5392                                 vlvf = IXGBE_READ_REG(hw,
5393                                                       IXGBE_VLVF(reg_index));
5394                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5395                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5396                                       mirror_conf->vlan.vlan_id[i]))
5397                                         vlan_mask |= (1ULL << reg_index);
5398                                 else
5399                                         return -EINVAL;
5400                         }
5401                 }
5402
5403                 if (on) {
5404                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5405                         mv_msb = vlan_mask >> vlan_mask_offset;
5406
5407                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5408                                                 mirror_conf->vlan.vlan_mask;
5409                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5410                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5411                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5412                                                 mirror_conf->vlan.vlan_id[i];
5413                         }
5414                 } else {
5415                         mv_lsb = 0;
5416                         mv_msb = 0;
5417                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5418                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5419                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5420                 }
5421         }
5422
5423         /**
5424          * if enable pool mirror, write related pool mask register,if disable
5425          * pool mirror, clear PFMRVM register
5426          */
5427         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5428                 mirror_type |= IXGBE_MRCTL_VPME;
5429                 if (on) {
5430                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5431                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5432                         mr_info->mr_conf[rule_id].pool_mask =
5433                                         mirror_conf->pool_mask;
5434
5435                 } else {
5436                         mp_lsb = 0;
5437                         mp_msb = 0;
5438                         mr_info->mr_conf[rule_id].pool_mask = 0;
5439                 }
5440         }
5441         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5442                 mirror_type |= IXGBE_MRCTL_UPME;
5443         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5444                 mirror_type |= IXGBE_MRCTL_DPME;
5445
5446         /* read  mirror control register and recalculate it */
5447         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5448
5449         if (on) {
5450                 mr_ctl |= mirror_type;
5451                 mr_ctl &= mirror_rule_mask;
5452                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5453         } else {
5454                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5455         }
5456
5457         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5458         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5459
5460         /* write mirrror control  register */
5461         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5462
5463         /* write pool mirrror control  register */
5464         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5465                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5466                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5467                                 mp_msb);
5468         }
5469         /* write VLAN mirrror control  register */
5470         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5471                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5472                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5473                                 mv_msb);
5474         }
5475
5476         return 0;
5477 }
5478
5479 static int
5480 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5481 {
5482         int mr_ctl = 0;
5483         uint32_t lsb_val = 0;
5484         uint32_t msb_val = 0;
5485         const uint8_t rule_mr_offset = 4;
5486
5487         struct ixgbe_hw *hw =
5488                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5489         struct ixgbe_mirror_info *mr_info =
5490                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5491
5492         if (ixgbe_vt_check(hw) < 0)
5493                 return -ENOTSUP;
5494
5495         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5496                 return -EINVAL;
5497
5498         memset(&mr_info->mr_conf[rule_id], 0,
5499                sizeof(struct rte_eth_mirror_conf));
5500
5501         /* clear PFVMCTL register */
5502         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5503
5504         /* clear pool mask register */
5505         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5506         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5507
5508         /* clear vlan mask register */
5509         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5510         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5511
5512         return 0;
5513 }
5514
5515 static int
5516 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5517 {
5518         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5519         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5520         uint32_t mask;
5521         struct ixgbe_hw *hw =
5522                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5523         uint32_t vec = IXGBE_MISC_VEC_ID;
5524
5525         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5526         if (rte_intr_allow_others(intr_handle))
5527                 vec = IXGBE_RX_VEC_START;
5528         mask |= (1 << vec);
5529         RTE_SET_USED(queue_id);
5530         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5531
5532         rte_intr_enable(intr_handle);
5533
5534         return 0;
5535 }
5536
5537 static int
5538 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5539 {
5540         uint32_t mask;
5541         struct ixgbe_hw *hw =
5542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5543         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5544         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5545         uint32_t vec = IXGBE_MISC_VEC_ID;
5546
5547         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5548         if (rte_intr_allow_others(intr_handle))
5549                 vec = IXGBE_RX_VEC_START;
5550         mask &= ~(1 << vec);
5551         RTE_SET_USED(queue_id);
5552         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5553
5554         return 0;
5555 }
5556
5557 static int
5558 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5559 {
5560         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5561         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5562         uint32_t mask;
5563         struct ixgbe_hw *hw =
5564                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5565         struct ixgbe_interrupt *intr =
5566                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5567
5568         if (queue_id < 16) {
5569                 ixgbe_disable_intr(hw);
5570                 intr->mask |= (1 << queue_id);
5571                 ixgbe_enable_intr(dev);
5572         } else if (queue_id < 32) {
5573                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5574                 mask &= (1 << queue_id);
5575                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5576         } else if (queue_id < 64) {
5577                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5578                 mask &= (1 << (queue_id - 32));
5579                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5580         }
5581         rte_intr_enable(intr_handle);
5582
5583         return 0;
5584 }
5585
5586 static int
5587 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5588 {
5589         uint32_t mask;
5590         struct ixgbe_hw *hw =
5591                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5592         struct ixgbe_interrupt *intr =
5593                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5594
5595         if (queue_id < 16) {
5596                 ixgbe_disable_intr(hw);
5597                 intr->mask &= ~(1 << queue_id);
5598                 ixgbe_enable_intr(dev);
5599         } else if (queue_id < 32) {
5600                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5601                 mask &= ~(1 << queue_id);
5602                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5603         } else if (queue_id < 64) {
5604                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5605                 mask &= ~(1 << (queue_id - 32));
5606                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5607         }
5608
5609         return 0;
5610 }
5611
5612 static void
5613 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5614                      uint8_t queue, uint8_t msix_vector)
5615 {
5616         uint32_t tmp, idx;
5617
5618         if (direction == -1) {
5619                 /* other causes */
5620                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5621                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5622                 tmp &= ~0xFF;
5623                 tmp |= msix_vector;
5624                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5625         } else {
5626                 /* rx or tx cause */
5627                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5628                 idx = ((16 * (queue & 1)) + (8 * direction));
5629                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5630                 tmp &= ~(0xFF << idx);
5631                 tmp |= (msix_vector << idx);
5632                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5633         }
5634 }
5635
5636 /**
5637  * set the IVAR registers, mapping interrupt causes to vectors
5638  * @param hw
5639  *  pointer to ixgbe_hw struct
5640  * @direction
5641  *  0 for Rx, 1 for Tx, -1 for other causes
5642  * @queue
5643  *  queue to map the corresponding interrupt to
5644  * @msix_vector
5645  *  the vector to map to the corresponding queue
5646  */
5647 static void
5648 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5649                    uint8_t queue, uint8_t msix_vector)
5650 {
5651         uint32_t tmp, idx;
5652
5653         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5654         if (hw->mac.type == ixgbe_mac_82598EB) {
5655                 if (direction == -1)
5656                         direction = 0;
5657                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5658                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5659                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5660                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5661                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5662         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5663                         (hw->mac.type == ixgbe_mac_X540) ||
5664                         (hw->mac.type == ixgbe_mac_X550)) {
5665                 if (direction == -1) {
5666                         /* other causes */
5667                         idx = ((queue & 1) * 8);
5668                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5669                         tmp &= ~(0xFF << idx);
5670                         tmp |= (msix_vector << idx);
5671                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5672                 } else {
5673                         /* rx or tx causes */
5674                         idx = ((16 * (queue & 1)) + (8 * direction));
5675                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5676                         tmp &= ~(0xFF << idx);
5677                         tmp |= (msix_vector << idx);
5678                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5679                 }
5680         }
5681 }
5682
5683 static void
5684 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5685 {
5686         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5687         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5688         struct ixgbe_hw *hw =
5689                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5690         uint32_t q_idx;
5691         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5692         uint32_t base = IXGBE_MISC_VEC_ID;
5693
5694         /* Configure VF other cause ivar */
5695         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5696
5697         /* won't configure msix register if no mapping is done
5698          * between intr vector and event fd.
5699          */
5700         if (!rte_intr_dp_is_en(intr_handle))
5701                 return;
5702
5703         if (rte_intr_allow_others(intr_handle)) {
5704                 base = IXGBE_RX_VEC_START;
5705                 vector_idx = IXGBE_RX_VEC_START;
5706         }
5707
5708         /* Configure all RX queues of VF */
5709         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5710                 /* Force all queue use vector 0,
5711                  * as IXGBE_VF_MAXMSIVECOTR = 1
5712                  */
5713                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5714                 intr_handle->intr_vec[q_idx] = vector_idx;
5715                 if (vector_idx < base + intr_handle->nb_efd - 1)
5716                         vector_idx++;
5717         }
5718 }
5719
5720 /**
5721  * Sets up the hardware to properly generate MSI-X interrupts
5722  * @hw
5723  *  board private structure
5724  */
5725 static void
5726 ixgbe_configure_msix(struct rte_eth_dev *dev)
5727 {
5728         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5729         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5730         struct ixgbe_hw *hw =
5731                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5732         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5733         uint32_t vec = IXGBE_MISC_VEC_ID;
5734         uint32_t mask;
5735         uint32_t gpie;
5736
5737         /* won't configure msix register if no mapping is done
5738          * between intr vector and event fd
5739          */
5740         if (!rte_intr_dp_is_en(intr_handle))
5741                 return;
5742
5743         if (rte_intr_allow_others(intr_handle))
5744                 vec = base = IXGBE_RX_VEC_START;
5745
5746         /* setup GPIE for MSI-x mode */
5747         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5748         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5749                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5750         /* auto clearing and auto setting corresponding bits in EIMS
5751          * when MSI-X interrupt is triggered
5752          */
5753         if (hw->mac.type == ixgbe_mac_82598EB) {
5754                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5755         } else {
5756                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5757                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5758         }
5759         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5760
5761         /* Populate the IVAR table and set the ITR values to the
5762          * corresponding register.
5763          */
5764         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5765              queue_id++) {
5766                 /* by default, 1:1 mapping */
5767                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5768                 intr_handle->intr_vec[queue_id] = vec;
5769                 if (vec < base + intr_handle->nb_efd - 1)
5770                         vec++;
5771         }
5772
5773         switch (hw->mac.type) {
5774         case ixgbe_mac_82598EB:
5775                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5776                                    IXGBE_MISC_VEC_ID);
5777                 break;
5778         case ixgbe_mac_82599EB:
5779         case ixgbe_mac_X540:
5780         case ixgbe_mac_X550:
5781                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5782                 break;
5783         default:
5784                 break;
5785         }
5786         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5787                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5788
5789         /* set up to autoclear timer, and the vectors */
5790         mask = IXGBE_EIMS_ENABLE_MASK;
5791         mask &= ~(IXGBE_EIMS_OTHER |
5792                   IXGBE_EIMS_MAILBOX |
5793                   IXGBE_EIMS_LSC);
5794
5795         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5796 }
5797
5798 int
5799 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5800                            uint16_t queue_idx, uint16_t tx_rate)
5801 {
5802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5803         uint32_t rf_dec, rf_int;
5804         uint32_t bcnrc_val;
5805         uint16_t link_speed = dev->data->dev_link.link_speed;
5806
5807         if (queue_idx >= hw->mac.max_tx_queues)
5808                 return -EINVAL;
5809
5810         if (tx_rate != 0) {
5811                 /* Calculate the rate factor values to set */
5812                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5813                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5814                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5815
5816                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5817                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5818                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5819                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5820         } else {
5821                 bcnrc_val = 0;
5822         }
5823
5824         /*
5825          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5826          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5827          * set as 0x4.
5828          */
5829         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5830                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5831                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5832                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5833                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5834         else
5835                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5836                         IXGBE_MMW_SIZE_DEFAULT);
5837
5838         /* Set RTTBCNRC of queue X */
5839         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5840         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5841         IXGBE_WRITE_FLUSH(hw);
5842
5843         return 0;
5844 }
5845
5846 static int
5847 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5848                      __attribute__((unused)) uint32_t index,
5849                      __attribute__((unused)) uint32_t pool)
5850 {
5851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5852         int diag;
5853
5854         /*
5855          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5856          * operation. Trap this case to avoid exhausting the [very limited]
5857          * set of PF resources used to store VF MAC addresses.
5858          */
5859         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5860                 return -1;
5861         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5862         if (diag != 0)
5863                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5864                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5865                             mac_addr->addr_bytes[0],
5866                             mac_addr->addr_bytes[1],
5867                             mac_addr->addr_bytes[2],
5868                             mac_addr->addr_bytes[3],
5869                             mac_addr->addr_bytes[4],
5870                             mac_addr->addr_bytes[5],
5871                             diag);
5872         return diag;
5873 }
5874
5875 static void
5876 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5877 {
5878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5879         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5880         struct ether_addr *mac_addr;
5881         uint32_t i;
5882         int diag;
5883
5884         /*
5885          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5886          * not support the deletion of a given MAC address.
5887          * Instead, it imposes to delete all MAC addresses, then to add again
5888          * all MAC addresses with the exception of the one to be deleted.
5889          */
5890         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5891
5892         /*
5893          * Add again all MAC addresses, with the exception of the deleted one
5894          * and of the permanent MAC address.
5895          */
5896         for (i = 0, mac_addr = dev->data->mac_addrs;
5897              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5898                 /* Skip the deleted MAC address */
5899                 if (i == index)
5900                         continue;
5901                 /* Skip NULL MAC addresses */
5902                 if (is_zero_ether_addr(mac_addr))
5903                         continue;
5904                 /* Skip the permanent MAC address */
5905                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5906                         continue;
5907                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5908                 if (diag != 0)
5909                         PMD_DRV_LOG(ERR,
5910                                     "Adding again MAC address "
5911                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5912                                     "diag=%d",
5913                                     mac_addr->addr_bytes[0],
5914                                     mac_addr->addr_bytes[1],
5915                                     mac_addr->addr_bytes[2],
5916                                     mac_addr->addr_bytes[3],
5917                                     mac_addr->addr_bytes[4],
5918                                     mac_addr->addr_bytes[5],
5919                                     diag);
5920         }
5921 }
5922
5923 static void
5924 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5925 {
5926         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5927
5928         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5929 }
5930
5931 int
5932 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5933                         struct rte_eth_syn_filter *filter,
5934                         bool add)
5935 {
5936         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5937         struct ixgbe_filter_info *filter_info =
5938                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5939         uint32_t syn_info;
5940         uint32_t synqf;
5941
5942         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5943                 return -EINVAL;
5944
5945         syn_info = filter_info->syn_info;
5946
5947         if (add) {
5948                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5949                         return -EINVAL;
5950                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5951                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5952
5953                 if (filter->hig_pri)
5954                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5955                 else
5956                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5957         } else {
5958                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5959                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5960                         return -ENOENT;
5961                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5962         }
5963
5964         filter_info->syn_info = synqf;
5965         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5966         IXGBE_WRITE_FLUSH(hw);
5967         return 0;
5968 }
5969
5970 static int
5971 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5972                         struct rte_eth_syn_filter *filter)
5973 {
5974         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5975         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5976
5977         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5978                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5979                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5980                 return 0;
5981         }
5982         return -ENOENT;
5983 }
5984
5985 static int
5986 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5987                         enum rte_filter_op filter_op,
5988                         void *arg)
5989 {
5990         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5991         int ret;
5992
5993         MAC_TYPE_FILTER_SUP(hw->mac.type);
5994
5995         if (filter_op == RTE_ETH_FILTER_NOP)
5996                 return 0;
5997
5998         if (arg == NULL) {
5999                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6000                             filter_op);
6001                 return -EINVAL;
6002         }
6003
6004         switch (filter_op) {
6005         case RTE_ETH_FILTER_ADD:
6006                 ret = ixgbe_syn_filter_set(dev,
6007                                 (struct rte_eth_syn_filter *)arg,
6008                                 TRUE);
6009                 break;
6010         case RTE_ETH_FILTER_DELETE:
6011                 ret = ixgbe_syn_filter_set(dev,
6012                                 (struct rte_eth_syn_filter *)arg,
6013                                 FALSE);
6014                 break;
6015         case RTE_ETH_FILTER_GET:
6016                 ret = ixgbe_syn_filter_get(dev,
6017                                 (struct rte_eth_syn_filter *)arg);
6018                 break;
6019         default:
6020                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6021                 ret = -EINVAL;
6022                 break;
6023         }
6024
6025         return ret;
6026 }
6027
6028
6029 static inline enum ixgbe_5tuple_protocol
6030 convert_protocol_type(uint8_t protocol_value)
6031 {
6032         if (protocol_value == IPPROTO_TCP)
6033                 return IXGBE_FILTER_PROTOCOL_TCP;
6034         else if (protocol_value == IPPROTO_UDP)
6035                 return IXGBE_FILTER_PROTOCOL_UDP;
6036         else if (protocol_value == IPPROTO_SCTP)
6037                 return IXGBE_FILTER_PROTOCOL_SCTP;
6038         else
6039                 return IXGBE_FILTER_PROTOCOL_NONE;
6040 }
6041
6042 /* inject a 5-tuple filter to HW */
6043 static inline void
6044 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6045                            struct ixgbe_5tuple_filter *filter)
6046 {
6047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6048         int i;
6049         uint32_t ftqf, sdpqf;
6050         uint32_t l34timir = 0;
6051         uint8_t mask = 0xff;
6052
6053         i = filter->index;
6054
6055         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6056                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6057         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6058
6059         ftqf = (uint32_t)(filter->filter_info.proto &
6060                 IXGBE_FTQF_PROTOCOL_MASK);
6061         ftqf |= (uint32_t)((filter->filter_info.priority &
6062                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6063         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6064                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6065         if (filter->filter_info.dst_ip_mask == 0)
6066                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6067         if (filter->filter_info.src_port_mask == 0)
6068                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6069         if (filter->filter_info.dst_port_mask == 0)
6070                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6071         if (filter->filter_info.proto_mask == 0)
6072                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6073         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6074         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6075         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6076
6077         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6078         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6079         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6080         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6081
6082         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6083         l34timir |= (uint32_t)(filter->queue <<
6084                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6085         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6086 }
6087
6088 /*
6089  * add a 5tuple filter
6090  *
6091  * @param
6092  * dev: Pointer to struct rte_eth_dev.
6093  * index: the index the filter allocates.
6094  * filter: ponter to the filter that will be added.
6095  * rx_queue: the queue id the filter assigned to.
6096  *
6097  * @return
6098  *    - On success, zero.
6099  *    - On failure, a negative value.
6100  */
6101 static int
6102 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6103                         struct ixgbe_5tuple_filter *filter)
6104 {
6105         struct ixgbe_filter_info *filter_info =
6106                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6107         int i, idx, shift;
6108
6109         /*
6110          * look for an unused 5tuple filter index,
6111          * and insert the filter to list.
6112          */
6113         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6114                 idx = i / (sizeof(uint32_t) * NBBY);
6115                 shift = i % (sizeof(uint32_t) * NBBY);
6116                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6117                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6118                         filter->index = i;
6119                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6120                                           filter,
6121                                           entries);
6122                         break;
6123                 }
6124         }
6125         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6126                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6127                 return -ENOSYS;
6128         }
6129
6130         ixgbe_inject_5tuple_filter(dev, filter);
6131
6132         return 0;
6133 }
6134
6135 /*
6136  * remove a 5tuple filter
6137  *
6138  * @param
6139  * dev: Pointer to struct rte_eth_dev.
6140  * filter: the pointer of the filter will be removed.
6141  */
6142 static void
6143 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6144                         struct ixgbe_5tuple_filter *filter)
6145 {
6146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6147         struct ixgbe_filter_info *filter_info =
6148                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6149         uint16_t index = filter->index;
6150
6151         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6152                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6153         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6154         rte_free(filter);
6155
6156         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6157         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6158         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6159         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6160         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6161 }
6162
6163 static int
6164 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6165 {
6166         struct ixgbe_hw *hw;
6167         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6168         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6169
6170         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6171
6172         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6173                 return -EINVAL;
6174
6175         /* refuse mtu that requires the support of scattered packets when this
6176          * feature has not been enabled before.
6177          */
6178         if (!rx_conf->enable_scatter &&
6179             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6180              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6181                 return -EINVAL;
6182
6183         /*
6184          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6185          * request of the version 2.0 of the mailbox API.
6186          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6187          * of the mailbox API.
6188          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6189          * prior to 3.11.33 which contains the following change:
6190          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6191          */
6192         ixgbevf_rlpml_set_vf(hw, max_frame);
6193
6194         /* update max frame size */
6195         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6196         return 0;
6197 }
6198
6199 static inline struct ixgbe_5tuple_filter *
6200 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6201                         struct ixgbe_5tuple_filter_info *key)
6202 {
6203         struct ixgbe_5tuple_filter *it;
6204
6205         TAILQ_FOREACH(it, filter_list, entries) {
6206                 if (memcmp(key, &it->filter_info,
6207                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6208                         return it;
6209                 }
6210         }
6211         return NULL;
6212 }
6213
6214 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6215 static inline int
6216 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6217                         struct ixgbe_5tuple_filter_info *filter_info)
6218 {
6219         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6220                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6221                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6222                 return -EINVAL;
6223
6224         switch (filter->dst_ip_mask) {
6225         case UINT32_MAX:
6226                 filter_info->dst_ip_mask = 0;
6227                 filter_info->dst_ip = filter->dst_ip;
6228                 break;
6229         case 0:
6230                 filter_info->dst_ip_mask = 1;
6231                 break;
6232         default:
6233                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6234                 return -EINVAL;
6235         }
6236
6237         switch (filter->src_ip_mask) {
6238         case UINT32_MAX:
6239                 filter_info->src_ip_mask = 0;
6240                 filter_info->src_ip = filter->src_ip;
6241                 break;
6242         case 0:
6243                 filter_info->src_ip_mask = 1;
6244                 break;
6245         default:
6246                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6247                 return -EINVAL;
6248         }
6249
6250         switch (filter->dst_port_mask) {
6251         case UINT16_MAX:
6252                 filter_info->dst_port_mask = 0;
6253                 filter_info->dst_port = filter->dst_port;
6254                 break;
6255         case 0:
6256                 filter_info->dst_port_mask = 1;
6257                 break;
6258         default:
6259                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6260                 return -EINVAL;
6261         }
6262
6263         switch (filter->src_port_mask) {
6264         case UINT16_MAX:
6265                 filter_info->src_port_mask = 0;
6266                 filter_info->src_port = filter->src_port;
6267                 break;
6268         case 0:
6269                 filter_info->src_port_mask = 1;
6270                 break;
6271         default:
6272                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6273                 return -EINVAL;
6274         }
6275
6276         switch (filter->proto_mask) {
6277         case UINT8_MAX:
6278                 filter_info->proto_mask = 0;
6279                 filter_info->proto =
6280                         convert_protocol_type(filter->proto);
6281                 break;
6282         case 0:
6283                 filter_info->proto_mask = 1;
6284                 break;
6285         default:
6286                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6287                 return -EINVAL;
6288         }
6289
6290         filter_info->priority = (uint8_t)filter->priority;
6291         return 0;
6292 }
6293
6294 /*
6295  * add or delete a ntuple filter
6296  *
6297  * @param
6298  * dev: Pointer to struct rte_eth_dev.
6299  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6300  * add: if true, add filter, if false, remove filter
6301  *
6302  * @return
6303  *    - On success, zero.
6304  *    - On failure, a negative value.
6305  */
6306 int
6307 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6308                         struct rte_eth_ntuple_filter *ntuple_filter,
6309                         bool add)
6310 {
6311         struct ixgbe_filter_info *filter_info =
6312                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6313         struct ixgbe_5tuple_filter_info filter_5tuple;
6314         struct ixgbe_5tuple_filter *filter;
6315         int ret;
6316
6317         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6318                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6319                 return -EINVAL;
6320         }
6321
6322         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6323         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6324         if (ret < 0)
6325                 return ret;
6326
6327         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6328                                          &filter_5tuple);
6329         if (filter != NULL && add) {
6330                 PMD_DRV_LOG(ERR, "filter exists.");
6331                 return -EEXIST;
6332         }
6333         if (filter == NULL && !add) {
6334                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6335                 return -ENOENT;
6336         }
6337
6338         if (add) {
6339                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6340                                 sizeof(struct ixgbe_5tuple_filter), 0);
6341                 if (filter == NULL)
6342                         return -ENOMEM;
6343                 rte_memcpy(&filter->filter_info,
6344                                  &filter_5tuple,
6345                                  sizeof(struct ixgbe_5tuple_filter_info));
6346                 filter->queue = ntuple_filter->queue;
6347                 ret = ixgbe_add_5tuple_filter(dev, filter);
6348                 if (ret < 0) {
6349                         rte_free(filter);
6350                         return ret;
6351                 }
6352         } else
6353                 ixgbe_remove_5tuple_filter(dev, filter);
6354
6355         return 0;
6356 }
6357
6358 /*
6359  * get a ntuple filter
6360  *
6361  * @param
6362  * dev: Pointer to struct rte_eth_dev.
6363  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6364  *
6365  * @return
6366  *    - On success, zero.
6367  *    - On failure, a negative value.
6368  */
6369 static int
6370 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6371                         struct rte_eth_ntuple_filter *ntuple_filter)
6372 {
6373         struct ixgbe_filter_info *filter_info =
6374                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6375         struct ixgbe_5tuple_filter_info filter_5tuple;
6376         struct ixgbe_5tuple_filter *filter;
6377         int ret;
6378
6379         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6380                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6381                 return -EINVAL;
6382         }
6383
6384         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6385         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6386         if (ret < 0)
6387                 return ret;
6388
6389         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6390                                          &filter_5tuple);
6391         if (filter == NULL) {
6392                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6393                 return -ENOENT;
6394         }
6395         ntuple_filter->queue = filter->queue;
6396         return 0;
6397 }
6398
6399 /*
6400  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6401  * @dev: pointer to rte_eth_dev structure
6402  * @filter_op:operation will be taken.
6403  * @arg: a pointer to specific structure corresponding to the filter_op
6404  *
6405  * @return
6406  *    - On success, zero.
6407  *    - On failure, a negative value.
6408  */
6409 static int
6410 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6411                                 enum rte_filter_op filter_op,
6412                                 void *arg)
6413 {
6414         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6415         int ret;
6416
6417         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6418
6419         if (filter_op == RTE_ETH_FILTER_NOP)
6420                 return 0;
6421
6422         if (arg == NULL) {
6423                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6424                             filter_op);
6425                 return -EINVAL;
6426         }
6427
6428         switch (filter_op) {
6429         case RTE_ETH_FILTER_ADD:
6430                 ret = ixgbe_add_del_ntuple_filter(dev,
6431                         (struct rte_eth_ntuple_filter *)arg,
6432                         TRUE);
6433                 break;
6434         case RTE_ETH_FILTER_DELETE:
6435                 ret = ixgbe_add_del_ntuple_filter(dev,
6436                         (struct rte_eth_ntuple_filter *)arg,
6437                         FALSE);
6438                 break;
6439         case RTE_ETH_FILTER_GET:
6440                 ret = ixgbe_get_ntuple_filter(dev,
6441                         (struct rte_eth_ntuple_filter *)arg);
6442                 break;
6443         default:
6444                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6445                 ret = -EINVAL;
6446                 break;
6447         }
6448         return ret;
6449 }
6450
6451 int
6452 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6453                         struct rte_eth_ethertype_filter *filter,
6454                         bool add)
6455 {
6456         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6457         struct ixgbe_filter_info *filter_info =
6458                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6459         uint32_t etqf = 0;
6460         uint32_t etqs = 0;
6461         int ret;
6462         struct ixgbe_ethertype_filter ethertype_filter;
6463
6464         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6465                 return -EINVAL;
6466
6467         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6468                 filter->ether_type == ETHER_TYPE_IPv6) {
6469                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6470                         " ethertype filter.", filter->ether_type);
6471                 return -EINVAL;
6472         }
6473
6474         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6475                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6476                 return -EINVAL;
6477         }
6478         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6479                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6480                 return -EINVAL;
6481         }
6482
6483         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6484         if (ret >= 0 && add) {
6485                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6486                             filter->ether_type);
6487                 return -EEXIST;
6488         }
6489         if (ret < 0 && !add) {
6490                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6491                             filter->ether_type);
6492                 return -ENOENT;
6493         }
6494
6495         if (add) {
6496                 etqf = IXGBE_ETQF_FILTER_EN;
6497                 etqf |= (uint32_t)filter->ether_type;
6498                 etqs |= (uint32_t)((filter->queue <<
6499                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6500                                     IXGBE_ETQS_RX_QUEUE);
6501                 etqs |= IXGBE_ETQS_QUEUE_EN;
6502
6503                 ethertype_filter.ethertype = filter->ether_type;
6504                 ethertype_filter.etqf = etqf;
6505                 ethertype_filter.etqs = etqs;
6506                 ethertype_filter.conf = FALSE;
6507                 ret = ixgbe_ethertype_filter_insert(filter_info,
6508                                                     &ethertype_filter);
6509                 if (ret < 0) {
6510                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6511                         return -ENOSPC;
6512                 }
6513         } else {
6514                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6515                 if (ret < 0)
6516                         return -ENOSYS;
6517         }
6518         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6519         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6520         IXGBE_WRITE_FLUSH(hw);
6521
6522         return 0;
6523 }
6524
6525 static int
6526 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6527                         struct rte_eth_ethertype_filter *filter)
6528 {
6529         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6530         struct ixgbe_filter_info *filter_info =
6531                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6532         uint32_t etqf, etqs;
6533         int ret;
6534
6535         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6536         if (ret < 0) {
6537                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6538                             filter->ether_type);
6539                 return -ENOENT;
6540         }
6541
6542         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6543         if (etqf & IXGBE_ETQF_FILTER_EN) {
6544                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6545                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6546                 filter->flags = 0;
6547                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6548                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6549                 return 0;
6550         }
6551         return -ENOENT;
6552 }
6553
6554 /*
6555  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6556  * @dev: pointer to rte_eth_dev structure
6557  * @filter_op:operation will be taken.
6558  * @arg: a pointer to specific structure corresponding to the filter_op
6559  */
6560 static int
6561 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6562                                 enum rte_filter_op filter_op,
6563                                 void *arg)
6564 {
6565         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6566         int ret;
6567
6568         MAC_TYPE_FILTER_SUP(hw->mac.type);
6569
6570         if (filter_op == RTE_ETH_FILTER_NOP)
6571                 return 0;
6572
6573         if (arg == NULL) {
6574                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6575                             filter_op);
6576                 return -EINVAL;
6577         }
6578
6579         switch (filter_op) {
6580         case RTE_ETH_FILTER_ADD:
6581                 ret = ixgbe_add_del_ethertype_filter(dev,
6582                         (struct rte_eth_ethertype_filter *)arg,
6583                         TRUE);
6584                 break;
6585         case RTE_ETH_FILTER_DELETE:
6586                 ret = ixgbe_add_del_ethertype_filter(dev,
6587                         (struct rte_eth_ethertype_filter *)arg,
6588                         FALSE);
6589                 break;
6590         case RTE_ETH_FILTER_GET:
6591                 ret = ixgbe_get_ethertype_filter(dev,
6592                         (struct rte_eth_ethertype_filter *)arg);
6593                 break;
6594         default:
6595                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6596                 ret = -EINVAL;
6597                 break;
6598         }
6599         return ret;
6600 }
6601
6602 static int
6603 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6604                      enum rte_filter_type filter_type,
6605                      enum rte_filter_op filter_op,
6606                      void *arg)
6607 {
6608         int ret = 0;
6609
6610         switch (filter_type) {
6611         case RTE_ETH_FILTER_NTUPLE:
6612                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6613                 break;
6614         case RTE_ETH_FILTER_ETHERTYPE:
6615                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6616                 break;
6617         case RTE_ETH_FILTER_SYN:
6618                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6619                 break;
6620         case RTE_ETH_FILTER_FDIR:
6621                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6622                 break;
6623         case RTE_ETH_FILTER_L2_TUNNEL:
6624                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6625                 break;
6626         case RTE_ETH_FILTER_GENERIC:
6627                 if (filter_op != RTE_ETH_FILTER_GET)
6628                         return -EINVAL;
6629                 *(const void **)arg = &ixgbe_flow_ops;
6630                 break;
6631         default:
6632                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6633                                                         filter_type);
6634                 ret = -EINVAL;
6635                 break;
6636         }
6637
6638         return ret;
6639 }
6640
6641 static u8 *
6642 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6643                         u8 **mc_addr_ptr, u32 *vmdq)
6644 {
6645         u8 *mc_addr;
6646
6647         *vmdq = 0;
6648         mc_addr = *mc_addr_ptr;
6649         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6650         return mc_addr;
6651 }
6652
6653 static int
6654 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6655                           struct ether_addr *mc_addr_set,
6656                           uint32_t nb_mc_addr)
6657 {
6658         struct ixgbe_hw *hw;
6659         u8 *mc_addr_list;
6660
6661         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6662         mc_addr_list = (u8 *)mc_addr_set;
6663         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6664                                          ixgbe_dev_addr_list_itr, TRUE);
6665 }
6666
6667 static uint64_t
6668 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6669 {
6670         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6671         uint64_t systime_cycles;
6672
6673         switch (hw->mac.type) {
6674         case ixgbe_mac_X550:
6675         case ixgbe_mac_X550EM_x:
6676         case ixgbe_mac_X550EM_a:
6677                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6678                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6679                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6680                                 * NSEC_PER_SEC;
6681                 break;
6682         default:
6683                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6684                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6685                                 << 32;
6686         }
6687
6688         return systime_cycles;
6689 }
6690
6691 static uint64_t
6692 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6693 {
6694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6695         uint64_t rx_tstamp_cycles;
6696
6697         switch (hw->mac.type) {
6698         case ixgbe_mac_X550:
6699         case ixgbe_mac_X550EM_x:
6700         case ixgbe_mac_X550EM_a:
6701                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6702                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6703                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6704                                 * NSEC_PER_SEC;
6705                 break;
6706         default:
6707                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6708                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6709                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6710                                 << 32;
6711         }
6712
6713         return rx_tstamp_cycles;
6714 }
6715
6716 static uint64_t
6717 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6718 {
6719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6720         uint64_t tx_tstamp_cycles;
6721
6722         switch (hw->mac.type) {
6723         case ixgbe_mac_X550:
6724         case ixgbe_mac_X550EM_x:
6725         case ixgbe_mac_X550EM_a:
6726                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6727                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6728                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6729                                 * NSEC_PER_SEC;
6730                 break;
6731         default:
6732                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6733                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6734                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6735                                 << 32;
6736         }
6737
6738         return tx_tstamp_cycles;
6739 }
6740
6741 static void
6742 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6743 {
6744         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6745         struct ixgbe_adapter *adapter =
6746                 (struct ixgbe_adapter *)dev->data->dev_private;
6747         struct rte_eth_link link;
6748         uint32_t incval = 0;
6749         uint32_t shift = 0;
6750
6751         /* Get current link speed. */
6752         ixgbe_dev_link_update(dev, 1);
6753         rte_eth_linkstatus_get(dev, &link);
6754
6755         switch (link.link_speed) {
6756         case ETH_SPEED_NUM_100M:
6757                 incval = IXGBE_INCVAL_100;
6758                 shift = IXGBE_INCVAL_SHIFT_100;
6759                 break;
6760         case ETH_SPEED_NUM_1G:
6761                 incval = IXGBE_INCVAL_1GB;
6762                 shift = IXGBE_INCVAL_SHIFT_1GB;
6763                 break;
6764         case ETH_SPEED_NUM_10G:
6765         default:
6766                 incval = IXGBE_INCVAL_10GB;
6767                 shift = IXGBE_INCVAL_SHIFT_10GB;
6768                 break;
6769         }
6770
6771         switch (hw->mac.type) {
6772         case ixgbe_mac_X550:
6773         case ixgbe_mac_X550EM_x:
6774         case ixgbe_mac_X550EM_a:
6775                 /* Independent of link speed. */
6776                 incval = 1;
6777                 /* Cycles read will be interpreted as ns. */
6778                 shift = 0;
6779                 /* Fall-through */
6780         case ixgbe_mac_X540:
6781                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6782                 break;
6783         case ixgbe_mac_82599EB:
6784                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6785                 shift -= IXGBE_INCVAL_SHIFT_82599;
6786                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6787                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6788                 break;
6789         default:
6790                 /* Not supported. */
6791                 return;
6792         }
6793
6794         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6795         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6796         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6797
6798         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6799         adapter->systime_tc.cc_shift = shift;
6800         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6801
6802         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6803         adapter->rx_tstamp_tc.cc_shift = shift;
6804         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6805
6806         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6807         adapter->tx_tstamp_tc.cc_shift = shift;
6808         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6809 }
6810
6811 static int
6812 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6813 {
6814         struct ixgbe_adapter *adapter =
6815                         (struct ixgbe_adapter *)dev->data->dev_private;
6816
6817         adapter->systime_tc.nsec += delta;
6818         adapter->rx_tstamp_tc.nsec += delta;
6819         adapter->tx_tstamp_tc.nsec += delta;
6820
6821         return 0;
6822 }
6823
6824 static int
6825 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6826 {
6827         uint64_t ns;
6828         struct ixgbe_adapter *adapter =
6829                         (struct ixgbe_adapter *)dev->data->dev_private;
6830
6831         ns = rte_timespec_to_ns(ts);
6832         /* Set the timecounters to a new value. */
6833         adapter->systime_tc.nsec = ns;
6834         adapter->rx_tstamp_tc.nsec = ns;
6835         adapter->tx_tstamp_tc.nsec = ns;
6836
6837         return 0;
6838 }
6839
6840 static int
6841 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6842 {
6843         uint64_t ns, systime_cycles;
6844         struct ixgbe_adapter *adapter =
6845                         (struct ixgbe_adapter *)dev->data->dev_private;
6846
6847         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6848         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6849         *ts = rte_ns_to_timespec(ns);
6850
6851         return 0;
6852 }
6853
6854 static int
6855 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6856 {
6857         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6858         uint32_t tsync_ctl;
6859         uint32_t tsauxc;
6860
6861         /* Stop the timesync system time. */
6862         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6863         /* Reset the timesync system time value. */
6864         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6865         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6866
6867         /* Enable system time for platforms where it isn't on by default. */
6868         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6869         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6870         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6871
6872         ixgbe_start_timecounters(dev);
6873
6874         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6875         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6876                         (ETHER_TYPE_1588 |
6877                          IXGBE_ETQF_FILTER_EN |
6878                          IXGBE_ETQF_1588));
6879
6880         /* Enable timestamping of received PTP packets. */
6881         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6882         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6883         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6884
6885         /* Enable timestamping of transmitted PTP packets. */
6886         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6887         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6888         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6889
6890         IXGBE_WRITE_FLUSH(hw);
6891
6892         return 0;
6893 }
6894
6895 static int
6896 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6897 {
6898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6899         uint32_t tsync_ctl;
6900
6901         /* Disable timestamping of transmitted PTP packets. */
6902         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6903         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6904         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6905
6906         /* Disable timestamping of received PTP packets. */
6907         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6908         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6909         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6910
6911         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6912         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6913
6914         /* Stop incrementating the System Time registers. */
6915         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6916
6917         return 0;
6918 }
6919
6920 static int
6921 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6922                                  struct timespec *timestamp,
6923                                  uint32_t flags __rte_unused)
6924 {
6925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6926         struct ixgbe_adapter *adapter =
6927                 (struct ixgbe_adapter *)dev->data->dev_private;
6928         uint32_t tsync_rxctl;
6929         uint64_t rx_tstamp_cycles;
6930         uint64_t ns;
6931
6932         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6933         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6934                 return -EINVAL;
6935
6936         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6937         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6938         *timestamp = rte_ns_to_timespec(ns);
6939
6940         return  0;
6941 }
6942
6943 static int
6944 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6945                                  struct timespec *timestamp)
6946 {
6947         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6948         struct ixgbe_adapter *adapter =
6949                 (struct ixgbe_adapter *)dev->data->dev_private;
6950         uint32_t tsync_txctl;
6951         uint64_t tx_tstamp_cycles;
6952         uint64_t ns;
6953
6954         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6955         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6956                 return -EINVAL;
6957
6958         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6959         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6960         *timestamp = rte_ns_to_timespec(ns);
6961
6962         return 0;
6963 }
6964
6965 static int
6966 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6967 {
6968         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6969         int count = 0;
6970         int g_ind = 0;
6971         const struct reg_info *reg_group;
6972         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6973                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6974
6975         while ((reg_group = reg_set[g_ind++]))
6976                 count += ixgbe_regs_group_count(reg_group);
6977
6978         return count;
6979 }
6980
6981 static int
6982 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6983 {
6984         int count = 0;
6985         int g_ind = 0;
6986         const struct reg_info *reg_group;
6987
6988         while ((reg_group = ixgbevf_regs[g_ind++]))
6989                 count += ixgbe_regs_group_count(reg_group);
6990
6991         return count;
6992 }
6993
6994 static int
6995 ixgbe_get_regs(struct rte_eth_dev *dev,
6996               struct rte_dev_reg_info *regs)
6997 {
6998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6999         uint32_t *data = regs->data;
7000         int g_ind = 0;
7001         int count = 0;
7002         const struct reg_info *reg_group;
7003         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7004                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7005
7006         if (data == NULL) {
7007                 regs->length = ixgbe_get_reg_length(dev);
7008                 regs->width = sizeof(uint32_t);
7009                 return 0;
7010         }
7011
7012         /* Support only full register dump */
7013         if ((regs->length == 0) ||
7014             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7015                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7016                         hw->device_id;
7017                 while ((reg_group = reg_set[g_ind++]))
7018                         count += ixgbe_read_regs_group(dev, &data[count],
7019                                 reg_group);
7020                 return 0;
7021         }
7022
7023         return -ENOTSUP;
7024 }
7025
7026 static int
7027 ixgbevf_get_regs(struct rte_eth_dev *dev,
7028                 struct rte_dev_reg_info *regs)
7029 {
7030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7031         uint32_t *data = regs->data;
7032         int g_ind = 0;
7033         int count = 0;
7034         const struct reg_info *reg_group;
7035
7036         if (data == NULL) {
7037                 regs->length = ixgbevf_get_reg_length(dev);
7038                 regs->width = sizeof(uint32_t);
7039                 return 0;
7040         }
7041
7042         /* Support only full register dump */
7043         if ((regs->length == 0) ||
7044             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7045                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7046                         hw->device_id;
7047                 while ((reg_group = ixgbevf_regs[g_ind++]))
7048                         count += ixgbe_read_regs_group(dev, &data[count],
7049                                                       reg_group);
7050                 return 0;
7051         }
7052
7053         return -ENOTSUP;
7054 }
7055
7056 static int
7057 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7058 {
7059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7060
7061         /* Return unit is byte count */
7062         return hw->eeprom.word_size * 2;
7063 }
7064
7065 static int
7066 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7067                 struct rte_dev_eeprom_info *in_eeprom)
7068 {
7069         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7070         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7071         uint16_t *data = in_eeprom->data;
7072         int first, length;
7073
7074         first = in_eeprom->offset >> 1;
7075         length = in_eeprom->length >> 1;
7076         if ((first > hw->eeprom.word_size) ||
7077             ((first + length) > hw->eeprom.word_size))
7078                 return -EINVAL;
7079
7080         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7081
7082         return eeprom->ops.read_buffer(hw, first, length, data);
7083 }
7084
7085 static int
7086 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7087                 struct rte_dev_eeprom_info *in_eeprom)
7088 {
7089         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7090         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7091         uint16_t *data = in_eeprom->data;
7092         int first, length;
7093
7094         first = in_eeprom->offset >> 1;
7095         length = in_eeprom->length >> 1;
7096         if ((first > hw->eeprom.word_size) ||
7097             ((first + length) > hw->eeprom.word_size))
7098                 return -EINVAL;
7099
7100         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7101
7102         return eeprom->ops.write_buffer(hw,  first, length, data);
7103 }
7104
7105 uint16_t
7106 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7107         switch (mac_type) {
7108         case ixgbe_mac_X550:
7109         case ixgbe_mac_X550EM_x:
7110         case ixgbe_mac_X550EM_a:
7111                 return ETH_RSS_RETA_SIZE_512;
7112         case ixgbe_mac_X550_vf:
7113         case ixgbe_mac_X550EM_x_vf:
7114         case ixgbe_mac_X550EM_a_vf:
7115                 return ETH_RSS_RETA_SIZE_64;
7116         default:
7117                 return ETH_RSS_RETA_SIZE_128;
7118         }
7119 }
7120
7121 uint32_t
7122 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7123         switch (mac_type) {
7124         case ixgbe_mac_X550:
7125         case ixgbe_mac_X550EM_x:
7126         case ixgbe_mac_X550EM_a:
7127                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7128                         return IXGBE_RETA(reta_idx >> 2);
7129                 else
7130                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7131         case ixgbe_mac_X550_vf:
7132         case ixgbe_mac_X550EM_x_vf:
7133         case ixgbe_mac_X550EM_a_vf:
7134                 return IXGBE_VFRETA(reta_idx >> 2);
7135         default:
7136                 return IXGBE_RETA(reta_idx >> 2);
7137         }
7138 }
7139
7140 uint32_t
7141 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7142         switch (mac_type) {
7143         case ixgbe_mac_X550_vf:
7144         case ixgbe_mac_X550EM_x_vf:
7145         case ixgbe_mac_X550EM_a_vf:
7146                 return IXGBE_VFMRQC;
7147         default:
7148                 return IXGBE_MRQC;
7149         }
7150 }
7151
7152 uint32_t
7153 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7154         switch (mac_type) {
7155         case ixgbe_mac_X550_vf:
7156         case ixgbe_mac_X550EM_x_vf:
7157         case ixgbe_mac_X550EM_a_vf:
7158                 return IXGBE_VFRSSRK(i);
7159         default:
7160                 return IXGBE_RSSRK(i);
7161         }
7162 }
7163
7164 bool
7165 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7166         switch (mac_type) {
7167         case ixgbe_mac_82599_vf:
7168         case ixgbe_mac_X540_vf:
7169                 return 0;
7170         default:
7171                 return 1;
7172         }
7173 }
7174
7175 static int
7176 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7177                         struct rte_eth_dcb_info *dcb_info)
7178 {
7179         struct ixgbe_dcb_config *dcb_config =
7180                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7181         struct ixgbe_dcb_tc_config *tc;
7182         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7183         uint8_t nb_tcs;
7184         uint8_t i, j;
7185
7186         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7187                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7188         else
7189                 dcb_info->nb_tcs = 1;
7190
7191         tc_queue = &dcb_info->tc_queue;
7192         nb_tcs = dcb_info->nb_tcs;
7193
7194         if (dcb_config->vt_mode) { /* vt is enabled*/
7195                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7196                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7197                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7198                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7199                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7200                         for (j = 0; j < nb_tcs; j++) {
7201                                 tc_queue->tc_rxq[0][j].base = j;
7202                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7203                                 tc_queue->tc_txq[0][j].base = j;
7204                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7205                         }
7206                 } else {
7207                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7208                                 for (j = 0; j < nb_tcs; j++) {
7209                                         tc_queue->tc_rxq[i][j].base =
7210                                                 i * nb_tcs + j;
7211                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7212                                         tc_queue->tc_txq[i][j].base =
7213                                                 i * nb_tcs + j;
7214                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7215                                 }
7216                         }
7217                 }
7218         } else { /* vt is disabled*/
7219                 struct rte_eth_dcb_rx_conf *rx_conf =
7220                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7221                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7222                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7223                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7224                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7225                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7226                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7227                         }
7228                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7229                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7230                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7231                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7232                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7233                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7234                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7235                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7236                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7237                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7238                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7239                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7240                         }
7241                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7242                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7243                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7244                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7245                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7246                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7247                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7248                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7249                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7250                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7251                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7252                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7253                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7254                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7255                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7256                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7257                 }
7258         }
7259         for (i = 0; i < dcb_info->nb_tcs; i++) {
7260                 tc = &dcb_config->tc_config[i];
7261                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7262         }
7263         return 0;
7264 }
7265
7266 /* Update e-tag ether type */
7267 static int
7268 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7269                             uint16_t ether_type)
7270 {
7271         uint32_t etag_etype;
7272
7273         if (hw->mac.type != ixgbe_mac_X550 &&
7274             hw->mac.type != ixgbe_mac_X550EM_x &&
7275             hw->mac.type != ixgbe_mac_X550EM_a) {
7276                 return -ENOTSUP;
7277         }
7278
7279         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7280         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7281         etag_etype |= ether_type;
7282         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7283         IXGBE_WRITE_FLUSH(hw);
7284
7285         return 0;
7286 }
7287
7288 /* Config l2 tunnel ether type */
7289 static int
7290 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7291                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7292 {
7293         int ret = 0;
7294         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7295         struct ixgbe_l2_tn_info *l2_tn_info =
7296                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7297
7298         if (l2_tunnel == NULL)
7299                 return -EINVAL;
7300
7301         switch (l2_tunnel->l2_tunnel_type) {
7302         case RTE_L2_TUNNEL_TYPE_E_TAG:
7303                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7304                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7305                 break;
7306         default:
7307                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7308                 ret = -EINVAL;
7309                 break;
7310         }
7311
7312         return ret;
7313 }
7314
7315 /* Enable e-tag tunnel */
7316 static int
7317 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7318 {
7319         uint32_t etag_etype;
7320
7321         if (hw->mac.type != ixgbe_mac_X550 &&
7322             hw->mac.type != ixgbe_mac_X550EM_x &&
7323             hw->mac.type != ixgbe_mac_X550EM_a) {
7324                 return -ENOTSUP;
7325         }
7326
7327         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7328         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7329         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7330         IXGBE_WRITE_FLUSH(hw);
7331
7332         return 0;
7333 }
7334
7335 /* Enable l2 tunnel */
7336 static int
7337 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7338                            enum rte_eth_tunnel_type l2_tunnel_type)
7339 {
7340         int ret = 0;
7341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7342         struct ixgbe_l2_tn_info *l2_tn_info =
7343                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7344
7345         switch (l2_tunnel_type) {
7346         case RTE_L2_TUNNEL_TYPE_E_TAG:
7347                 l2_tn_info->e_tag_en = TRUE;
7348                 ret = ixgbe_e_tag_enable(hw);
7349                 break;
7350         default:
7351                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7352                 ret = -EINVAL;
7353                 break;
7354         }
7355
7356         return ret;
7357 }
7358
7359 /* Disable e-tag tunnel */
7360 static int
7361 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7362 {
7363         uint32_t etag_etype;
7364
7365         if (hw->mac.type != ixgbe_mac_X550 &&
7366             hw->mac.type != ixgbe_mac_X550EM_x &&
7367             hw->mac.type != ixgbe_mac_X550EM_a) {
7368                 return -ENOTSUP;
7369         }
7370
7371         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7372         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7373         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7374         IXGBE_WRITE_FLUSH(hw);
7375
7376         return 0;
7377 }
7378
7379 /* Disable l2 tunnel */
7380 static int
7381 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7382                             enum rte_eth_tunnel_type l2_tunnel_type)
7383 {
7384         int ret = 0;
7385         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7386         struct ixgbe_l2_tn_info *l2_tn_info =
7387                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7388
7389         switch (l2_tunnel_type) {
7390         case RTE_L2_TUNNEL_TYPE_E_TAG:
7391                 l2_tn_info->e_tag_en = FALSE;
7392                 ret = ixgbe_e_tag_disable(hw);
7393                 break;
7394         default:
7395                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7396                 ret = -EINVAL;
7397                 break;
7398         }
7399
7400         return ret;
7401 }
7402
7403 static int
7404 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7405                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7406 {
7407         int ret = 0;
7408         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7409         uint32_t i, rar_entries;
7410         uint32_t rar_low, rar_high;
7411
7412         if (hw->mac.type != ixgbe_mac_X550 &&
7413             hw->mac.type != ixgbe_mac_X550EM_x &&
7414             hw->mac.type != ixgbe_mac_X550EM_a) {
7415                 return -ENOTSUP;
7416         }
7417
7418         rar_entries = ixgbe_get_num_rx_addrs(hw);
7419
7420         for (i = 1; i < rar_entries; i++) {
7421                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7422                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7423                 if ((rar_high & IXGBE_RAH_AV) &&
7424                     (rar_high & IXGBE_RAH_ADTYPE) &&
7425                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7426                      l2_tunnel->tunnel_id)) {
7427                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7428                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7429
7430                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7431
7432                         return ret;
7433                 }
7434         }
7435
7436         return ret;
7437 }
7438
7439 static int
7440 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7441                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7442 {
7443         int ret = 0;
7444         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7445         uint32_t i, rar_entries;
7446         uint32_t rar_low, rar_high;
7447
7448         if (hw->mac.type != ixgbe_mac_X550 &&
7449             hw->mac.type != ixgbe_mac_X550EM_x &&
7450             hw->mac.type != ixgbe_mac_X550EM_a) {
7451                 return -ENOTSUP;
7452         }
7453
7454         /* One entry for one tunnel. Try to remove potential existing entry. */
7455         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7456
7457         rar_entries = ixgbe_get_num_rx_addrs(hw);
7458
7459         for (i = 1; i < rar_entries; i++) {
7460                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7461                 if (rar_high & IXGBE_RAH_AV) {
7462                         continue;
7463                 } else {
7464                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7465                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7466                         rar_low = l2_tunnel->tunnel_id;
7467
7468                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7469                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7470
7471                         return ret;
7472                 }
7473         }
7474
7475         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7476                      " Please remove a rule before adding a new one.");
7477         return -EINVAL;
7478 }
7479
7480 static inline struct ixgbe_l2_tn_filter *
7481 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7482                           struct ixgbe_l2_tn_key *key)
7483 {
7484         int ret;
7485
7486         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7487         if (ret < 0)
7488                 return NULL;
7489
7490         return l2_tn_info->hash_map[ret];
7491 }
7492
7493 static inline int
7494 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7495                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7496 {
7497         int ret;
7498
7499         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7500                                &l2_tn_filter->key);
7501
7502         if (ret < 0) {
7503                 PMD_DRV_LOG(ERR,
7504                             "Failed to insert L2 tunnel filter"
7505                             " to hash table %d!",
7506                             ret);
7507                 return ret;
7508         }
7509
7510         l2_tn_info->hash_map[ret] = l2_tn_filter;
7511
7512         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7513
7514         return 0;
7515 }
7516
7517 static inline int
7518 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7519                           struct ixgbe_l2_tn_key *key)
7520 {
7521         int ret;
7522         struct ixgbe_l2_tn_filter *l2_tn_filter;
7523
7524         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7525
7526         if (ret < 0) {
7527                 PMD_DRV_LOG(ERR,
7528                             "No such L2 tunnel filter to delete %d!",
7529                             ret);
7530                 return ret;
7531         }
7532
7533         l2_tn_filter = l2_tn_info->hash_map[ret];
7534         l2_tn_info->hash_map[ret] = NULL;
7535
7536         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7537         rte_free(l2_tn_filter);
7538
7539         return 0;
7540 }
7541
7542 /* Add l2 tunnel filter */
7543 int
7544 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7545                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7546                                bool restore)
7547 {
7548         int ret;
7549         struct ixgbe_l2_tn_info *l2_tn_info =
7550                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7551         struct ixgbe_l2_tn_key key;
7552         struct ixgbe_l2_tn_filter *node;
7553
7554         if (!restore) {
7555                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7556                 key.tn_id = l2_tunnel->tunnel_id;
7557
7558                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7559
7560                 if (node) {
7561                         PMD_DRV_LOG(ERR,
7562                                     "The L2 tunnel filter already exists!");
7563                         return -EINVAL;
7564                 }
7565
7566                 node = rte_zmalloc("ixgbe_l2_tn",
7567                                    sizeof(struct ixgbe_l2_tn_filter),
7568                                    0);
7569                 if (!node)
7570                         return -ENOMEM;
7571
7572                 rte_memcpy(&node->key,
7573                                  &key,
7574                                  sizeof(struct ixgbe_l2_tn_key));
7575                 node->pool = l2_tunnel->pool;
7576                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7577                 if (ret < 0) {
7578                         rte_free(node);
7579                         return ret;
7580                 }
7581         }
7582
7583         switch (l2_tunnel->l2_tunnel_type) {
7584         case RTE_L2_TUNNEL_TYPE_E_TAG:
7585                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7586                 break;
7587         default:
7588                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7589                 ret = -EINVAL;
7590                 break;
7591         }
7592
7593         if ((!restore) && (ret < 0))
7594                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7595
7596         return ret;
7597 }
7598
7599 /* Delete l2 tunnel filter */
7600 int
7601 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7602                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7603 {
7604         int ret;
7605         struct ixgbe_l2_tn_info *l2_tn_info =
7606                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7607         struct ixgbe_l2_tn_key key;
7608
7609         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7610         key.tn_id = l2_tunnel->tunnel_id;
7611         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7612         if (ret < 0)
7613                 return ret;
7614
7615         switch (l2_tunnel->l2_tunnel_type) {
7616         case RTE_L2_TUNNEL_TYPE_E_TAG:
7617                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7618                 break;
7619         default:
7620                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7621                 ret = -EINVAL;
7622                 break;
7623         }
7624
7625         return ret;
7626 }
7627
7628 /**
7629  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7630  * @dev: pointer to rte_eth_dev structure
7631  * @filter_op:operation will be taken.
7632  * @arg: a pointer to specific structure corresponding to the filter_op
7633  */
7634 static int
7635 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7636                                   enum rte_filter_op filter_op,
7637                                   void *arg)
7638 {
7639         int ret;
7640
7641         if (filter_op == RTE_ETH_FILTER_NOP)
7642                 return 0;
7643
7644         if (arg == NULL) {
7645                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7646                             filter_op);
7647                 return -EINVAL;
7648         }
7649
7650         switch (filter_op) {
7651         case RTE_ETH_FILTER_ADD:
7652                 ret = ixgbe_dev_l2_tunnel_filter_add
7653                         (dev,
7654                          (struct rte_eth_l2_tunnel_conf *)arg,
7655                          FALSE);
7656                 break;
7657         case RTE_ETH_FILTER_DELETE:
7658                 ret = ixgbe_dev_l2_tunnel_filter_del
7659                         (dev,
7660                          (struct rte_eth_l2_tunnel_conf *)arg);
7661                 break;
7662         default:
7663                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7664                 ret = -EINVAL;
7665                 break;
7666         }
7667         return ret;
7668 }
7669
7670 static int
7671 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7672 {
7673         int ret = 0;
7674         uint32_t ctrl;
7675         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7676
7677         if (hw->mac.type != ixgbe_mac_X550 &&
7678             hw->mac.type != ixgbe_mac_X550EM_x &&
7679             hw->mac.type != ixgbe_mac_X550EM_a) {
7680                 return -ENOTSUP;
7681         }
7682
7683         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7684         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7685         if (en)
7686                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7687         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7688
7689         return ret;
7690 }
7691
7692 /* Enable l2 tunnel forwarding */
7693 static int
7694 ixgbe_dev_l2_tunnel_forwarding_enable
7695         (struct rte_eth_dev *dev,
7696          enum rte_eth_tunnel_type l2_tunnel_type)
7697 {
7698         struct ixgbe_l2_tn_info *l2_tn_info =
7699                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7700         int ret = 0;
7701
7702         switch (l2_tunnel_type) {
7703         case RTE_L2_TUNNEL_TYPE_E_TAG:
7704                 l2_tn_info->e_tag_fwd_en = TRUE;
7705                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7706                 break;
7707         default:
7708                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7709                 ret = -EINVAL;
7710                 break;
7711         }
7712
7713         return ret;
7714 }
7715
7716 /* Disable l2 tunnel forwarding */
7717 static int
7718 ixgbe_dev_l2_tunnel_forwarding_disable
7719         (struct rte_eth_dev *dev,
7720          enum rte_eth_tunnel_type l2_tunnel_type)
7721 {
7722         struct ixgbe_l2_tn_info *l2_tn_info =
7723                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7724         int ret = 0;
7725
7726         switch (l2_tunnel_type) {
7727         case RTE_L2_TUNNEL_TYPE_E_TAG:
7728                 l2_tn_info->e_tag_fwd_en = FALSE;
7729                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7730                 break;
7731         default:
7732                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7733                 ret = -EINVAL;
7734                 break;
7735         }
7736
7737         return ret;
7738 }
7739
7740 static int
7741 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7742                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7743                              bool en)
7744 {
7745         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7746         int ret = 0;
7747         uint32_t vmtir, vmvir;
7748         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7749
7750         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7751                 PMD_DRV_LOG(ERR,
7752                             "VF id %u should be less than %u",
7753                             l2_tunnel->vf_id,
7754                             pci_dev->max_vfs);
7755                 return -EINVAL;
7756         }
7757
7758         if (hw->mac.type != ixgbe_mac_X550 &&
7759             hw->mac.type != ixgbe_mac_X550EM_x &&
7760             hw->mac.type != ixgbe_mac_X550EM_a) {
7761                 return -ENOTSUP;
7762         }
7763
7764         if (en)
7765                 vmtir = l2_tunnel->tunnel_id;
7766         else
7767                 vmtir = 0;
7768
7769         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7770
7771         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7772         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7773         if (en)
7774                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7775         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7776
7777         return ret;
7778 }
7779
7780 /* Enable l2 tunnel tag insertion */
7781 static int
7782 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7783                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7784 {
7785         int ret = 0;
7786
7787         switch (l2_tunnel->l2_tunnel_type) {
7788         case RTE_L2_TUNNEL_TYPE_E_TAG:
7789                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7790                 break;
7791         default:
7792                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7793                 ret = -EINVAL;
7794                 break;
7795         }
7796
7797         return ret;
7798 }
7799
7800 /* Disable l2 tunnel tag insertion */
7801 static int
7802 ixgbe_dev_l2_tunnel_insertion_disable
7803         (struct rte_eth_dev *dev,
7804          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7805 {
7806         int ret = 0;
7807
7808         switch (l2_tunnel->l2_tunnel_type) {
7809         case RTE_L2_TUNNEL_TYPE_E_TAG:
7810                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7811                 break;
7812         default:
7813                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7814                 ret = -EINVAL;
7815                 break;
7816         }
7817
7818         return ret;
7819 }
7820
7821 static int
7822 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7823                              bool en)
7824 {
7825         int ret = 0;
7826         uint32_t qde;
7827         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7828
7829         if (hw->mac.type != ixgbe_mac_X550 &&
7830             hw->mac.type != ixgbe_mac_X550EM_x &&
7831             hw->mac.type != ixgbe_mac_X550EM_a) {
7832                 return -ENOTSUP;
7833         }
7834
7835         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7836         if (en)
7837                 qde |= IXGBE_QDE_STRIP_TAG;
7838         else
7839                 qde &= ~IXGBE_QDE_STRIP_TAG;
7840         qde &= ~IXGBE_QDE_READ;
7841         qde |= IXGBE_QDE_WRITE;
7842         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7843
7844         return ret;
7845 }
7846
7847 /* Enable l2 tunnel tag stripping */
7848 static int
7849 ixgbe_dev_l2_tunnel_stripping_enable
7850         (struct rte_eth_dev *dev,
7851          enum rte_eth_tunnel_type l2_tunnel_type)
7852 {
7853         int ret = 0;
7854
7855         switch (l2_tunnel_type) {
7856         case RTE_L2_TUNNEL_TYPE_E_TAG:
7857                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7858                 break;
7859         default:
7860                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7861                 ret = -EINVAL;
7862                 break;
7863         }
7864
7865         return ret;
7866 }
7867
7868 /* Disable l2 tunnel tag stripping */
7869 static int
7870 ixgbe_dev_l2_tunnel_stripping_disable
7871         (struct rte_eth_dev *dev,
7872          enum rte_eth_tunnel_type l2_tunnel_type)
7873 {
7874         int ret = 0;
7875
7876         switch (l2_tunnel_type) {
7877         case RTE_L2_TUNNEL_TYPE_E_TAG:
7878                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7879                 break;
7880         default:
7881                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7882                 ret = -EINVAL;
7883                 break;
7884         }
7885
7886         return ret;
7887 }
7888
7889 /* Enable/disable l2 tunnel offload functions */
7890 static int
7891 ixgbe_dev_l2_tunnel_offload_set
7892         (struct rte_eth_dev *dev,
7893          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7894          uint32_t mask,
7895          uint8_t en)
7896 {
7897         int ret = 0;
7898
7899         if (l2_tunnel == NULL)
7900                 return -EINVAL;
7901
7902         ret = -EINVAL;
7903         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7904                 if (en)
7905                         ret = ixgbe_dev_l2_tunnel_enable(
7906                                 dev,
7907                                 l2_tunnel->l2_tunnel_type);
7908                 else
7909                         ret = ixgbe_dev_l2_tunnel_disable(
7910                                 dev,
7911                                 l2_tunnel->l2_tunnel_type);
7912         }
7913
7914         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7915                 if (en)
7916                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7917                                 dev,
7918                                 l2_tunnel);
7919                 else
7920                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7921                                 dev,
7922                                 l2_tunnel);
7923         }
7924
7925         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7926                 if (en)
7927                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7928                                 dev,
7929                                 l2_tunnel->l2_tunnel_type);
7930                 else
7931                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7932                                 dev,
7933                                 l2_tunnel->l2_tunnel_type);
7934         }
7935
7936         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7937                 if (en)
7938                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7939                                 dev,
7940                                 l2_tunnel->l2_tunnel_type);
7941                 else
7942                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7943                                 dev,
7944                                 l2_tunnel->l2_tunnel_type);
7945         }
7946
7947         return ret;
7948 }
7949
7950 static int
7951 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7952                         uint16_t port)
7953 {
7954         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7955         IXGBE_WRITE_FLUSH(hw);
7956
7957         return 0;
7958 }
7959
7960 /* There's only one register for VxLAN UDP port.
7961  * So, we cannot add several ports. Will update it.
7962  */
7963 static int
7964 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7965                      uint16_t port)
7966 {
7967         if (port == 0) {
7968                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7969                 return -EINVAL;
7970         }
7971
7972         return ixgbe_update_vxlan_port(hw, port);
7973 }
7974
7975 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7976  * UDP port, it must have a value.
7977  * So, will reset it to the original value 0.
7978  */
7979 static int
7980 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7981                      uint16_t port)
7982 {
7983         uint16_t cur_port;
7984
7985         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7986
7987         if (cur_port != port) {
7988                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7989                 return -EINVAL;
7990         }
7991
7992         return ixgbe_update_vxlan_port(hw, 0);
7993 }
7994
7995 /* Add UDP tunneling port */
7996 static int
7997 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7998                               struct rte_eth_udp_tunnel *udp_tunnel)
7999 {
8000         int ret = 0;
8001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8002
8003         if (hw->mac.type != ixgbe_mac_X550 &&
8004             hw->mac.type != ixgbe_mac_X550EM_x &&
8005             hw->mac.type != ixgbe_mac_X550EM_a) {
8006                 return -ENOTSUP;
8007         }
8008
8009         if (udp_tunnel == NULL)
8010                 return -EINVAL;
8011
8012         switch (udp_tunnel->prot_type) {
8013         case RTE_TUNNEL_TYPE_VXLAN:
8014                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8015                 break;
8016
8017         case RTE_TUNNEL_TYPE_GENEVE:
8018         case RTE_TUNNEL_TYPE_TEREDO:
8019                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8020                 ret = -EINVAL;
8021                 break;
8022
8023         default:
8024                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8025                 ret = -EINVAL;
8026                 break;
8027         }
8028
8029         return ret;
8030 }
8031
8032 /* Remove UDP tunneling port */
8033 static int
8034 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8035                               struct rte_eth_udp_tunnel *udp_tunnel)
8036 {
8037         int ret = 0;
8038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8039
8040         if (hw->mac.type != ixgbe_mac_X550 &&
8041             hw->mac.type != ixgbe_mac_X550EM_x &&
8042             hw->mac.type != ixgbe_mac_X550EM_a) {
8043                 return -ENOTSUP;
8044         }
8045
8046         if (udp_tunnel == NULL)
8047                 return -EINVAL;
8048
8049         switch (udp_tunnel->prot_type) {
8050         case RTE_TUNNEL_TYPE_VXLAN:
8051                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8052                 break;
8053         case RTE_TUNNEL_TYPE_GENEVE:
8054         case RTE_TUNNEL_TYPE_TEREDO:
8055                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8056                 ret = -EINVAL;
8057                 break;
8058         default:
8059                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8060                 ret = -EINVAL;
8061                 break;
8062         }
8063
8064         return ret;
8065 }
8066
8067 static void
8068 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8069 {
8070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8071
8072         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8073 }
8074
8075 static void
8076 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8077 {
8078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8079
8080         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8081 }
8082
8083 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8084 {
8085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8086         u32 in_msg = 0;
8087
8088         /* peek the message first */
8089         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8090
8091         /* PF reset VF event */
8092         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8093                 /* dummy mbx read to ack pf */
8094                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8095                         return;
8096                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8097                                               NULL);
8098         }
8099 }
8100
8101 static int
8102 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8103 {
8104         uint32_t eicr;
8105         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8106         struct ixgbe_interrupt *intr =
8107                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8108         ixgbevf_intr_disable(hw);
8109
8110         /* read-on-clear nic registers here */
8111         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8112         intr->flags = 0;
8113
8114         /* only one misc vector supported - mailbox */
8115         eicr &= IXGBE_VTEICR_MASK;
8116         if (eicr == IXGBE_MISC_VEC_ID)
8117                 intr->flags |= IXGBE_FLAG_MAILBOX;
8118
8119         return 0;
8120 }
8121
8122 static int
8123 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8124 {
8125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8126         struct ixgbe_interrupt *intr =
8127                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8128
8129         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8130                 ixgbevf_mbx_process(dev);
8131                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8132         }
8133
8134         ixgbevf_intr_enable(hw);
8135
8136         return 0;
8137 }
8138
8139 static void
8140 ixgbevf_dev_interrupt_handler(void *param)
8141 {
8142         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8143
8144         ixgbevf_dev_interrupt_get_status(dev);
8145         ixgbevf_dev_interrupt_action(dev);
8146 }
8147
8148 /**
8149  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8150  *  @hw: pointer to hardware structure
8151  *
8152  *  Stops the transmit data path and waits for the HW to internally empty
8153  *  the Tx security block
8154  **/
8155 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8156 {
8157 #define IXGBE_MAX_SECTX_POLL 40
8158
8159         int i;
8160         int sectxreg;
8161
8162         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8163         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8164         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8165         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8166                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8167                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8168                         break;
8169                 /* Use interrupt-safe sleep just in case */
8170                 usec_delay(1000);
8171         }
8172
8173         /* For informational purposes only */
8174         if (i >= IXGBE_MAX_SECTX_POLL)
8175                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8176                          "path fully disabled.  Continuing with init.");
8177
8178         return IXGBE_SUCCESS;
8179 }
8180
8181 /**
8182  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8183  *  @hw: pointer to hardware structure
8184  *
8185  *  Enables the transmit data path.
8186  **/
8187 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8188 {
8189         uint32_t sectxreg;
8190
8191         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8192         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8193         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8194         IXGBE_WRITE_FLUSH(hw);
8195
8196         return IXGBE_SUCCESS;
8197 }
8198
8199 /* restore n-tuple filter */
8200 static inline void
8201 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8202 {
8203         struct ixgbe_filter_info *filter_info =
8204                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8205         struct ixgbe_5tuple_filter *node;
8206
8207         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8208                 ixgbe_inject_5tuple_filter(dev, node);
8209         }
8210 }
8211
8212 /* restore ethernet type filter */
8213 static inline void
8214 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8215 {
8216         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8217         struct ixgbe_filter_info *filter_info =
8218                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8219         int i;
8220
8221         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8222                 if (filter_info->ethertype_mask & (1 << i)) {
8223                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8224                                         filter_info->ethertype_filters[i].etqf);
8225                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8226                                         filter_info->ethertype_filters[i].etqs);
8227                         IXGBE_WRITE_FLUSH(hw);
8228                 }
8229         }
8230 }
8231
8232 /* restore SYN filter */
8233 static inline void
8234 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8235 {
8236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8237         struct ixgbe_filter_info *filter_info =
8238                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8239         uint32_t synqf;
8240
8241         synqf = filter_info->syn_info;
8242
8243         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8244                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8245                 IXGBE_WRITE_FLUSH(hw);
8246         }
8247 }
8248
8249 /* restore L2 tunnel filter */
8250 static inline void
8251 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8252 {
8253         struct ixgbe_l2_tn_info *l2_tn_info =
8254                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8255         struct ixgbe_l2_tn_filter *node;
8256         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8257
8258         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8259                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8260                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8261                 l2_tn_conf.pool           = node->pool;
8262                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8263         }
8264 }
8265
8266 /* restore rss filter */
8267 static inline void
8268 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8269 {
8270         struct ixgbe_filter_info *filter_info =
8271                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8272
8273         if (filter_info->rss_info.num)
8274                 ixgbe_config_rss_filter(dev,
8275                         &filter_info->rss_info, TRUE);
8276 }
8277
8278 static int
8279 ixgbe_filter_restore(struct rte_eth_dev *dev)
8280 {
8281         ixgbe_ntuple_filter_restore(dev);
8282         ixgbe_ethertype_filter_restore(dev);
8283         ixgbe_syn_filter_restore(dev);
8284         ixgbe_fdir_filter_restore(dev);
8285         ixgbe_l2_tn_filter_restore(dev);
8286         ixgbe_rss_filter_restore(dev);
8287
8288         return 0;
8289 }
8290
8291 static void
8292 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8293 {
8294         struct ixgbe_l2_tn_info *l2_tn_info =
8295                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8296         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8297
8298         if (l2_tn_info->e_tag_en)
8299                 (void)ixgbe_e_tag_enable(hw);
8300
8301         if (l2_tn_info->e_tag_fwd_en)
8302                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8303
8304         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8305 }
8306
8307 /* remove all the n-tuple filters */
8308 void
8309 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8310 {
8311         struct ixgbe_filter_info *filter_info =
8312                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8313         struct ixgbe_5tuple_filter *p_5tuple;
8314
8315         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8316                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8317 }
8318
8319 /* remove all the ether type filters */
8320 void
8321 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8322 {
8323         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8324         struct ixgbe_filter_info *filter_info =
8325                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8326         int i;
8327
8328         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8329                 if (filter_info->ethertype_mask & (1 << i) &&
8330                     !filter_info->ethertype_filters[i].conf) {
8331                         (void)ixgbe_ethertype_filter_remove(filter_info,
8332                                                             (uint8_t)i);
8333                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8334                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8335                         IXGBE_WRITE_FLUSH(hw);
8336                 }
8337         }
8338 }
8339
8340 /* remove the SYN filter */
8341 void
8342 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8343 {
8344         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8345         struct ixgbe_filter_info *filter_info =
8346                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8347
8348         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8349                 filter_info->syn_info = 0;
8350
8351                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8352                 IXGBE_WRITE_FLUSH(hw);
8353         }
8354 }
8355
8356 /* remove all the L2 tunnel filters */
8357 int
8358 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8359 {
8360         struct ixgbe_l2_tn_info *l2_tn_info =
8361                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8362         struct ixgbe_l2_tn_filter *l2_tn_filter;
8363         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8364         int ret = 0;
8365
8366         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8367                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8368                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8369                 l2_tn_conf.pool           = l2_tn_filter->pool;
8370                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8371                 if (ret < 0)
8372                         return ret;
8373         }
8374
8375         return 0;
8376 }
8377
8378 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8379 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8380 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8381 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8382 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8383 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8384
8385 RTE_INIT(ixgbe_init_log);
8386 static void
8387 ixgbe_init_log(void)
8388 {
8389         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8390         if (ixgbe_logtype_init >= 0)
8391                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8392         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8393         if (ixgbe_logtype_driver >= 0)
8394                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8395 }